[MIPS] Allow hardwiring of the CPU type to a single type for optimization.
This saves a few k on systems which only ever ship with a single CPU type.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cf48371..8b7b7c5 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -328,7 +328,7 @@
r4k_blast_dcache();
r4k_blast_icache();
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@@ -377,10 +377,10 @@
* R4000SC and R4400SC indexed S-cache ops also invalidate primary
* caches, so we can bail out early.
*/
- if (current_cpu_data.cputype == CPU_R4000SC ||
- current_cpu_data.cputype == CPU_R4000MC ||
- current_cpu_data.cputype == CPU_R4400SC ||
- current_cpu_data.cputype == CPU_R4400MC) {
+ if (current_cpu_type() == CPU_R4000SC ||
+ current_cpu_type() == CPU_R4000MC ||
+ current_cpu_type() == CPU_R4400SC ||
+ current_cpu_type() == CPU_R4400MC) {
r4k_blast_scache();
return;
}
@@ -1197,7 +1197,7 @@
* this bit and; some wire it to zero, others like Toshiba had the
* silly idea of putting something else there ...
*/
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 560a6de..9ea121e 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -69,7 +69,7 @@
/* TX39H2,TX39H3 */
static inline void tx39_blast_dcache_page(unsigned long addr)
{
- if (current_cpu_data.cputype != CPU_TX3912)
+ if (current_cpu_type() != CPU_TX3912)
blast_dcache16_page(addr);
}
@@ -307,7 +307,7 @@
TX39_CONF_DCS_SHIFT));
current_cpu_data.icache.linesz = 16;
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_TX3912:
current_cpu_data.icache.ways = 1;
current_cpu_data.dcache.ways = 1;
@@ -341,7 +341,7 @@
tx39_probe_cache();
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_TX3912:
/* TX39/H core (writethru direct-map cache) */
flush_cache_all = tx39h_flush_icache_all;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f60b3dc..98b5e5b 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -35,8 +35,8 @@
static inline int cpu_is_noncoherent_r10000(struct device *dev)
{
return !plat_device_is_coherent(dev) &&
- (current_cpu_data.cputype == CPU_R10000 ||
- current_cpu_data.cputype == CPU_R12000);
+ (current_cpu_type() == CPU_R10000 ||
+ current_cpu_type() == CPU_R12000);
}
void *dma_alloc_noncoherent(struct device *dev, size_t size,
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index c029454..4f770ac 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -354,7 +354,7 @@
store_offset = 0;
if (cpu_has_prefetch) {
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_TX49XX:
/* TX49 supports only Pref_Load */
pref_offset_clear = 0;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 7325074..c3da4fe 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -827,7 +827,7 @@
*/
static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
{
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
/* Found by experiment: R4600 v2.0 needs this, too. */
case CPU_R4600:
case CPU_R5000:
@@ -860,7 +860,7 @@
case tlb_indexed: tlbw = i_tlbwi; break;
}
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
@@ -1158,7 +1158,7 @@
unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_VR41XX:
case CPU_VR4111:
case CPU_VR4121:
@@ -1188,7 +1188,7 @@
* in a different cacheline or a load instruction, probably any
* memory reference, is between them.
*/
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_NEVADA:
i_LW(p, ptr, 0, ptr);
GET_CONTEXT(p, tmp); /* get context reg */
@@ -1872,7 +1872,7 @@
*/
static int run_once = 0;
- switch (current_cpu_data.cputype) {
+ switch (current_cpu_type()) {
case CPU_R2000:
case CPU_R3000:
case CPU_R3000A: