Merge "power: qpnp-charger: implement software end of charge"
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index 4a312a8..ded8f77 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -30,7 +30,8 @@
 - qcom,vdd_pll:       Voltage to be set for the PLL's rail.
 - reg-names:          "cxrail_bhs_reg" - control register for modem power
 		      domain.
-- qcom,is-loadable:   Boolean- Present if the image needs to be loaded.
+- qcom,is-not-loadable: Boolean- Present if the image does not need to
+			be loaded.
 - qcom,pil-self-auth: Boolean- True if authentication is required.
 
 Example:
@@ -47,7 +48,7 @@
 		vdd_cx-supply = <&pm8841_s2>;
 		vdd_mx-supply = <&pm8841_s1>;
 
-		qcom,is-loadable;
+		qcom,is-not-loadable;
 		qcom,firmware-name = "mba";
 		qcom,pil-self-auth;
 
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index 0375b9a..ce6bc63 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -585,10 +585,10 @@
 			};
 
 			chan@3 {
-				label = "spare1";
+				label = "spare1_div3";
 				reg = <3>;
 				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <6>;
+				qcom,pre-div-channel-scaling = <1>;
 				qcom,calibration-type = "absolute";
 				qcom,scale-function = <0>;
 				qcom,hw-settle-time = <0>;
@@ -596,10 +596,10 @@
 			};
 
 			chan@4 {
-				label = "spare2";
+				label = "usb_id_mv";
 				reg = <4>;
 				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <6>;
+				qcom,pre-div-channel-scaling = <1>;
 				qcom,calibration-type = "absolute";
 				qcom,scale-function = <0>;
 				qcom,hw-settle-time = <0>;
@@ -873,7 +873,7 @@
 				reg = <0xb5>;
 				qcom,decimation = <0>;
 				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
+				qcom,calibration-type = "ratiometric";
 				qcom,scale-function = <2>;
 				qcom,hw-settle-time = <2>;
 				qcom,fast-avg-setup = <3>;
diff --git a/arch/arm/boot/dts/msm8226-coresight.dtsi b/arch/arm/boot/dts/msm8226-coresight.dtsi
index e4a42fa..7c19bc0 100644
--- a/arch/arm/boot/dts/msm8226-coresight.dtsi
+++ b/arch/arm/boot/dts/msm8226-coresight.dtsi
@@ -355,4 +355,18 @@
 		coresight-name = "coresight-cti-cpu3";
 		coresight-nr-inports = <0>;
 	};
+
+	hwevent: hwevent@fd828018 {
+		compatible = "qcom,coresight-hwevent";
+		reg = <0xfd828018 0x80>,
+		      <0xf9011080 0x80>,
+		      <0xfd4ab160 0x80>;
+		reg-names = "mmss-mux", "apcs-mux", "ppss-mux";
+
+		coresight-id = <29>;
+		coresight-name = "coresight-hwevent";
+		coresight-nr-inports = <0>;
+
+		qcom,hwevent-clks = "core_mmss_clk";
+	};
 };
diff --git a/arch/arm/boot/dts/msm8226-mtp.dts b/arch/arm/boot/dts/msm8226-mtp.dts
index 3dd517b..589fe69 100644
--- a/arch/arm/boot/dts/msm8226-mtp.dts
+++ b/arch/arm/boot/dts/msm8226-mtp.dts
@@ -365,3 +365,10 @@
 &pm8226_chg {
 	qcom,charging-disabled;
 };
+
+&slim_msm {
+	tapan_codec {
+		qcom,cdc-micbias1-ext-cap;
+		qcom,cdc-micbias2-ext-cap;
+	};
+};
diff --git a/arch/arm/boot/dts/msm8226-qrd.dts b/arch/arm/boot/dts/msm8226-qrd.dts
index 721bcbb..f917d45 100644
--- a/arch/arm/boot/dts/msm8226-qrd.dts
+++ b/arch/arm/boot/dts/msm8226-qrd.dts
@@ -331,3 +331,10 @@
 	mpp@a700 { /* MPP 8 */
 	};
 };
+
+&slim_msm {
+	tapan_codec {
+		qcom,cdc-micbias1-ext-cap;
+	};
+
+};
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index 3cd9cb5..620b4a1 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -282,7 +282,7 @@
 		interrupt-names = "cdc-int";
 	};
 
-	slim@fe12f000 {
+	slim_msm: slim@fe12f000 {
 		cell-index = <1>;
 		compatible = "qcom,slim-ngd";
 		reg = <0xfe12f000 0x35000>,
diff --git a/arch/arm/boot/dts/msm8610-cdp.dts b/arch/arm/boot/dts/msm8610-cdp.dts
index 1bf7c2b..d3fc917 100644
--- a/arch/arm/boot/dts/msm8610-cdp.dts
+++ b/arch/arm/boot/dts/msm8610-cdp.dts
@@ -88,6 +88,49 @@
 			};
 		};
 	};
+
+	gen-vkeys {
+		compatible = "qcom,gen-vkeys";
+		label = "atmel_mxt_ts";
+		qcom,disp-maxx = <480>;
+		qcom,disp-maxy = <800>;
+		qcom,panel-maxx = <508>;
+		qcom,panel-maxy = <880>;
+		qcom,key-codes = <158 102 139>;
+		qcom,y-offset = <35>;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		input-name = "gpio-keys";
+
+		camera_snapshot {
+			label = "camera_snapshot";
+			gpios = <&msmgpio 73 0x1>;
+			linux,input-type = <1>;
+			linux,code = <0x2fe>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+		};
+
+		camera_focus {
+			label = "camera_focus";
+			gpios = <&msmgpio 74 0x1>;
+			linux,input-type = <1>;
+			linux,code = <0x210>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+		};
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&msmgpio 72 0x1>;
+			linux,input-type = <1>;
+			linux,code = <115>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+		};
+	};
 };
 
 &i2c_cdc  {
@@ -165,38 +208,6 @@
 			};
 		};
 	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		input-name = "gpio-keys";
-
-		camera_snapshot {
-			label = "camera_snapshot";
-			gpios = <&msmgpio 73 0x1>;
-			linux,input-type = <1>;
-			linux,code = <0x2fe>;
-			gpio-key,wakeup;
-			debounce-interval = <15>;
-		};
-
-		camera_focus {
-			label = "camera_focus";
-			gpios = <&msmgpio 74 0x1>;
-			linux,input-type = <1>;
-			linux,code = <0x210>;
-			gpio-key,wakeup;
-			debounce-interval = <15>;
-		};
-
-		vol_up {
-			label = "volume_up";
-			gpios = <&msmgpio 72 0x1>;
-			linux,input-type = <1>;
-			linux,code = <115>;
-			gpio-key,wakeup;
-			debounce-interval = <15>;
-		};
-	};
 };
 
 &spmi_bus {
@@ -207,17 +218,6 @@
 			qcom,vib-vtg-level-mV = <3100>;
 		};
 	};
-
-	gen-vkeys {
-		compatible = "qcom,gen-vkeys";
-		label = "atmel_mxt_ts";
-		qcom,disp-maxx = <480>;
-		qcom,disp-maxy = <800>;
-		qcom,panel-maxx = <508>;
-		qcom,panel-maxy = <880>;
-		qcom,key-codes = <158 102 139>;
-		qcom,y-offset = <35>;
-	};
 };
 
 &sdhc_1 {
@@ -327,3 +327,52 @@
 	mpp@a300 { /* MPP 4 */
 	};
 };
+
+/* CoreSight */
+&tpiu {
+	qcom,seta-gpios = <&msmgpio 4 0>,
+			  <&msmgpio 5 0>,
+			  <&msmgpio 6 0>,
+			  <&msmgpio 7 0>,
+			  <&msmgpio 22 0>,
+			  <&msmgpio 23 0>,
+			  <&msmgpio 24 0>,
+			  <&msmgpio 25 0>,
+			  <&msmgpio 26 0>,
+			  <&msmgpio 27 0>,
+			  <&msmgpio 28 0>,
+			  <&msmgpio 29 0>,
+			  <&msmgpio 30 0>,
+			  <&msmgpio 31 0>,
+			  <&msmgpio 94 0>,
+			  <&msmgpio 95 0>,
+			  <&msmgpio 96 0>,
+			  <&msmgpio 97 0>;
+	qcom,seta-gpios-func = <9 9 8 11 2 2 2 2 2 2 3 2 3 3 4 4 4 4>;
+	qcom,seta-gpios-drv =  <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>;
+	qcom,seta-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+	qcom,seta-gpios-dir =  <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>;
+
+	qcom,setb-gpios = <&msmgpio 8 0>,
+			  <&msmgpio 10 0>,
+			  <&msmgpio 11 0>,
+			  <&msmgpio 13 0>,
+			  <&msmgpio 14 0>,
+			  <&msmgpio 15 0>,
+			  <&msmgpio 16 0>,
+			  <&msmgpio 17 0>,
+			  <&msmgpio 18 0>,
+			  <&msmgpio 19 0>,
+			  <&msmgpio 20 0>,
+			  <&msmgpio 21 0>,
+			  <&msmgpio 42 0>,
+			  <&msmgpio 80 0>,
+			  <&msmgpio 81 0>,
+			  <&msmgpio 82 0>,
+			  <&msmgpio 83 0>,
+			  <&msmgpio 84 0>;
+	qcom,setb-gpios-func = <10 8 8 6 9 9 9 9 9 9 9 9 5 7 7 8 8 8>;
+	qcom,setb-gpios-drv =  <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>;
+	qcom,setb-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+	qcom,setb-gpios-dir =  <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>;
+};
diff --git a/arch/arm/boot/dts/msm8610-coresight.dtsi b/arch/arm/boot/dts/msm8610-coresight.dtsi
index 4945693..0d9ae9a 100644
--- a/arch/arm/boot/dts/msm8610-coresight.dtsi
+++ b/arch/arm/boot/dts/msm8610-coresight.dtsi
@@ -34,6 +34,11 @@
 		coresight-id = <1>;
 		coresight-name = "coresight-tpiu";
 		coresight-nr-inports = <1>;
+
+		vdd-supply = <&pm8110_l18>;
+
+		qcom,vdd-voltage-level = <2950000 2950000>;
+		qcom,vdd-current-level = <15000 400000>;
 	};
 
 	replicator: replicator@fc324000 {
diff --git a/arch/arm/boot/dts/msm8610-mtp.dts b/arch/arm/boot/dts/msm8610-mtp.dts
index 3fbc820..35e8909 100644
--- a/arch/arm/boot/dts/msm8610-mtp.dts
+++ b/arch/arm/boot/dts/msm8610-mtp.dts
@@ -88,6 +88,49 @@
 			};
 		};
 	};
+
+	gen-vkeys {
+		compatible = "qcom,gen-vkeys";
+		label = "atmel_mxt_ts";
+		qcom,disp-maxx = <480>;
+		qcom,disp-maxy = <800>;
+		qcom,panel-maxx = <508>;
+		qcom,panel-maxy = <880>;
+		qcom,key-codes = <158 102 139>;
+		qcom,y-offset = <35>;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		input-name = "gpio-keys";
+
+		camera_snapshot {
+			label = "camera_snapshot";
+			gpios = <&msmgpio 73 0x1>;
+			linux,input-type = <1>;
+			linux,code = <0x2fe>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+		};
+
+		camera_focus {
+			label = "camera_focus";
+			gpios = <&msmgpio 74 0x1>;
+			linux,input-type = <1>;
+			linux,code = <0x210>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+		};
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&msmgpio 72 0x1>;
+			linux,input-type = <1>;
+			linux,code = <115>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+		};
+	};
 };
 
 &i2c_cdc  {
@@ -165,38 +208,6 @@
 			};
 		};
 	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		input-name = "gpio-keys";
-
-		camera_snapshot {
-			label = "camera_snapshot";
-			gpios = <&msmgpio 73 0x1>;
-			linux,input-type = <1>;
-			linux,code = <0x2fe>;
-			gpio-key,wakeup;
-			debounce-interval = <15>;
-		};
-
-		camera_focus {
-			label = "camera_focus";
-			gpios = <&msmgpio 74 0x1>;
-			linux,input-type = <1>;
-			linux,code = <0x210>;
-			gpio-key,wakeup;
-			debounce-interval = <15>;
-		};
-
-		vol_up {
-			label = "volume_up";
-			gpios = <&msmgpio 72 0x1>;
-			linux,input-type = <1>;
-			linux,code = <115>;
-			gpio-key,wakeup;
-			debounce-interval = <15>;
-		};
-	};
 };
 
 &spmi_bus {
@@ -207,17 +218,6 @@
 			qcom,vib-vtg-level-mV = <3100>;
 		};
 	};
-
-	gen-vkeys {
-		compatible = "qcom,gen-vkeys";
-		label = "atmel_mxt_ts";
-		qcom,disp-maxx = <480>;
-		qcom,disp-maxy = <800>;
-		qcom,panel-maxx = <508>;
-		qcom,panel-maxy = <880>;
-		qcom,key-codes = <158 102 139>;
-		qcom,y-offset = <35>;
-	};
 };
 
 &sdhc_1 {
diff --git a/arch/arm/boot/dts/msm8610.dtsi b/arch/arm/boot/dts/msm8610.dtsi
index b1f3813..aff8759 100644
--- a/arch/arm/boot/dts/msm8610.dtsi
+++ b/arch/arm/boot/dts/msm8610.dtsi
@@ -730,7 +730,7 @@
 
 	qcom,msm-thermal {
 		compatible = "qcom,msm-thermal";
-		qcom,sensor-id = <0>;
+		qcom,sensor-id = <5>;
 		qcom,poll-ms = <250>;
 		qcom,limit-temp = <60>;
 		qcom,temp-hysteresis = <10>;
diff --git a/arch/arm/boot/dts/msm8974-v1-cdp.dts b/arch/arm/boot/dts/msm8974-v1-cdp.dts
index cb58026..c3fd98d 100644
--- a/arch/arm/boot/dts/msm8974-v1-cdp.dts
+++ b/arch/arm/boot/dts/msm8974-v1-cdp.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974 CDP";
 	compatible = "qcom,msm8974-cdp", "qcom,msm8974", "qcom,cdp";
-	qcom,msm-id = <126 1 0>;
+	qcom,msm-id = <126 1 0>,
+		      <185 1 0>,
+		      <186 1 0>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/msm8974-v1-fluid.dts b/arch/arm/boot/dts/msm8974-v1-fluid.dts
index 8ab24df..2b96ecb 100644
--- a/arch/arm/boot/dts/msm8974-v1-fluid.dts
+++ b/arch/arm/boot/dts/msm8974-v1-fluid.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974 FLUID";
 	compatible = "qcom,msm8974-fluid", "qcom,msm8974", "qcom,fluid";
-	qcom,msm-id = <126 3 0>;
+	qcom,msm-id = <126 3 0>,
+		      <185 3 0>,
+		      <186 3 0>;
 
 };
 
diff --git a/arch/arm/boot/dts/msm8974-v1-liquid.dts b/arch/arm/boot/dts/msm8974-v1-liquid.dts
index ccbd82f..29d6150 100644
--- a/arch/arm/boot/dts/msm8974-v1-liquid.dts
+++ b/arch/arm/boot/dts/msm8974-v1-liquid.dts
@@ -18,5 +18,7 @@
 / {
 	model = "Qualcomm MSM 8974 LIQUID";
 	compatible = "qcom,msm8974-liquid", "qcom,msm8974", "qcom,liquid";
-	qcom,msm-id = <126 9 0>;
+	qcom,msm-id = <126 9 0>,
+		      <185 9 0>,
+		      <186 9 0>;
 };
diff --git a/arch/arm/boot/dts/msm8974-v1-mtp.dts b/arch/arm/boot/dts/msm8974-v1-mtp.dts
index 09ea84b..8cbcca0 100644
--- a/arch/arm/boot/dts/msm8974-v1-mtp.dts
+++ b/arch/arm/boot/dts/msm8974-v1-mtp.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974 MTP";
 	compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp";
-	qcom,msm-id = <126 8 0>;
+	qcom,msm-id = <126 8 0>,
+		      <185 8 0>,
+		      <186 8 0>;
 };
 
 &pm8941_chg {
diff --git a/arch/arm/boot/dts/msm8974-v1-rumi.dts b/arch/arm/boot/dts/msm8974-v1-rumi.dts
index caf89ee..85aab17 100644
--- a/arch/arm/boot/dts/msm8974-v1-rumi.dts
+++ b/arch/arm/boot/dts/msm8974-v1-rumi.dts
@@ -18,5 +18,7 @@
 / {
 	model = "Qualcomm MSM 8974 RUMI";
 	compatible = "qcom,msm8974-rumi", "qcom,msm8974", "qcom,rumi";
-	qcom,msm-id = <126 15 0>;
+	qcom,msm-id = <126 15 0>,
+		      <185 15 0>,
+		      <186 15 0>;
 };
diff --git a/arch/arm/boot/dts/msm8974-v1-sim.dts b/arch/arm/boot/dts/msm8974-v1-sim.dts
index c4b29c2..fc9858d 100644
--- a/arch/arm/boot/dts/msm8974-v1-sim.dts
+++ b/arch/arm/boot/dts/msm8974-v1-sim.dts
@@ -18,5 +18,7 @@
 / {
 	model = "Qualcomm MSM 8974 Simulator";
 	compatible = "qcom,msm8974-sim", "qcom,msm8974", "qcom,sim";
-	qcom,msm-id = <126 16 0>;
+	qcom,msm-id = <126 16 0>,
+		      <185 16 0>,
+		      <186 16 0>;
 };
diff --git a/arch/arm/boot/dts/msm8974-v2-cdp.dts b/arch/arm/boot/dts/msm8974-v2-cdp.dts
index 4fa1f2a..85d478b 100644
--- a/arch/arm/boot/dts/msm8974-v2-cdp.dts
+++ b/arch/arm/boot/dts/msm8974-v2-cdp.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974v2 CDP";
 	compatible = "qcom,msm8974-cdp", "qcom,msm8974", "qcom,cdp";
-	qcom,msm-id = <126 1 0x20000>;
+	qcom,msm-id = <126 1 0x20000>,
+		      <185 1 0x20000>,
+		      <186 1 0x20000>;
 };
 
 &usb3 {
diff --git a/arch/arm/boot/dts/msm8974-v2-fluid.dts b/arch/arm/boot/dts/msm8974-v2-fluid.dts
index c5779b1..d83d130 100644
--- a/arch/arm/boot/dts/msm8974-v2-fluid.dts
+++ b/arch/arm/boot/dts/msm8974-v2-fluid.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974v2 FLUID";
 	compatible = "qcom,msm8974-fluid", "qcom,msm8974", "qcom,fluid";
-	qcom,msm-id = <126 3 0x20000>;
+	qcom,msm-id = <126 3 0x20000>,
+		      <185 3 0x20000>,
+		      <186 3 0x20000>;
 };
 
 &usb3 {
diff --git a/arch/arm/boot/dts/msm8974-v2-liquid.dts b/arch/arm/boot/dts/msm8974-v2-liquid.dts
index 7132f43..53983dc 100644
--- a/arch/arm/boot/dts/msm8974-v2-liquid.dts
+++ b/arch/arm/boot/dts/msm8974-v2-liquid.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974v2 LIQUID";
 	compatible = "qcom,msm8974-liquid", "qcom,msm8974", "qcom,liquid";
-	qcom,msm-id = <126 9 0x20000>;
+	qcom,msm-id = <126 9 0x20000>,
+		      <185 9 0x20000>,
+		      <186 9 0x20000>;
 };
 
 &usb3 {
diff --git a/arch/arm/boot/dts/msm8974-v2-mtp.dts b/arch/arm/boot/dts/msm8974-v2-mtp.dts
index d38e663..c25c385 100644
--- a/arch/arm/boot/dts/msm8974-v2-mtp.dts
+++ b/arch/arm/boot/dts/msm8974-v2-mtp.dts
@@ -18,7 +18,9 @@
 / {
 	model = "Qualcomm MSM 8974v2 MTP";
 	compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp";
-	qcom,msm-id = <126 8 0x20000>;
+	qcom,msm-id = <126 8 0x20000>,
+		      <185 8 0x20000>,
+		      <186 8 0x20000>;
 };
 
 &usb3 {
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 71bbdc5..825fe8c 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1127,7 +1127,6 @@
 		vdd_mx-supply = <&pm8841_s1>;
 		vdd_pll-supply = <&pm8941_l12>;
 		qcom,vdd_pll = <1800000>;
-		qcom,is-loadable;
 		qcom,firmware-name = "mba";
 		qcom,pil-self-auth;
 
diff --git a/arch/arm/boot/dts/msm9625-coresight.dtsi b/arch/arm/boot/dts/msm9625-coresight.dtsi
index 8520b19..9b18b72 100644
--- a/arch/arm/boot/dts/msm9625-coresight.dtsi
+++ b/arch/arm/boot/dts/msm9625-coresight.dtsi
@@ -243,4 +243,15 @@
 		coresight-name = "coresight-cti-cpu";
 		coresight-nr-inports = <0>;
 	};
+
+	hwevent: hwevent@f9011038 {
+		compatible = "qcom,coresight-hwevent";
+		reg = <0xf9011038 0x8>,
+		      <0xfd4ab160 0x80>;
+		reg-names = "apcs-mux", "ppss-mux";
+
+		coresight-id = <20>;
+		coresight-name = "coresight-hwevent";
+		coresight-nr-inports = <0>;
+	};
 };
diff --git a/arch/arm/boot/dts/msm9625.dtsi b/arch/arm/boot/dts/msm9625.dtsi
index 5abfab8..6e258b5 100644
--- a/arch/arm/boot/dts/msm9625.dtsi
+++ b/arch/arm/boot/dts/msm9625.dtsi
@@ -763,6 +763,7 @@
 	qcom,mss {
 		compatible = "qcom,pil-q6v5-mss";
 		interrupts = <0 24 1>;
+		qcom,is-not-loadable;
 
 		/* GPIO inputs from mss */
 		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
diff --git a/arch/arm/configs/mpq8092_defconfig b/arch/arm/configs/mpq8092_defconfig
new file mode 100644
index 0000000..28ca32f
--- /dev/null
+++ b/arch/arm/configs/mpq8092_defconfig
@@ -0,0 +1,368 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_IOSCHED_TEST=y
+CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MPQ8092=y
+CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
+CONFIG_MSM_MPM_OF=y
+# CONFIG_MSM_STACKED_MEMORY is not set
+CONFIG_CPU_HAS_L2_PMU=y
+# CONFIG_MSM_FIQ_SUPPORT is not set
+# CONFIG_MSM_PROC_COMM is not set
+CONFIG_MSM_SMD=y
+CONFIG_MSM_SMD_PKG4=y
+CONFIG_MSM_IPC_LOGGING=y
+CONFIG_MSM_IPC_ROUTER=y
+CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
+CONFIG_MSM_IPC_ROUTER_SECURITY=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
+CONFIG_MSM_DIRECT_SCLK_ACCESS=y
+CONFIG_MSM_WATCHDOG_V2=y
+CONFIG_MSM_DLOAD_MODE=y
+CONFIG_MSM_RUN_QUEUE_STATS=y
+CONFIG_MSM_SPM_V2=y
+CONFIG_MSM_L2_SPM=y
+CONFIG_MSM_OCMEM=y
+CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
+CONFIG_MSM_OCMEM_DEBUG=y
+CONFIG_MSM_OCMEM_NONSECURE=y
+CONFIG_SENSORS_ADSP=y
+CONFIG_MSM_RTB=y
+CONFIG_MSM_RTB_SEPARATE_CPUS=y
+CONFIG_MSM_CACHE_ERP=y
+CONFIG_MSM_L1_ERR_PANIC=y
+CONFIG_MSM_L1_RECOV_ERR_PANIC=y
+CONFIG_MSM_L1_ERR_LOG=y
+CONFIG_MSM_L2_ERP_PRINT_ACCESS_ERRORS=y
+CONFIG_MSM_L2_ERP_PORT_PANIC=y
+CONFIG_MSM_L2_ERP_1BIT_PANIC=y
+CONFIG_MSM_L2_ERP_2BIT_PANIC=y
+CONFIG_MSM_CACHE_DUMP=y
+CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
+CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_SCHED_MC=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_CP_ACCESS=y
+CONFIG_USE_OF=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_GENLOCK=y
+CONFIG_GENLOCK_MISCDEVICE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_HAPTIC_ISA1200=y
+CONFIG_USB_HSIC_SMSC_HUB=y
+CONFIG_TI_DRV2667=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_KS8851=m
+# CONFIG_MSM_RMNET is not set
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_USBNET=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_MSM_HSL=y
+CONFIG_SERIAL_MSM_HSL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_QUP=y
+CONFIG_SPI=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_MSM_QPNP_INT=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_QPNP_PIN=y
+CONFIG_GPIO_QPNP_PIN_DEBUG=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SMB350_CHARGER=y
+CONFIG_BATTERY_BQ28400=y
+CONFIG_QPNP_CHARGER=y
+CONFIG_BATTERY_BCL=y
+CONFIG_SENSORS_EPM_ADC=y
+CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
+CONFIG_SENSORS_QPNP_ADC_CURRENT=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_QPNP=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_REGULATOR_QPNP=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MSM_KGSL=y
+CONFIG_FB=y
+CONFIG_FB_MSM=y
+# CONFIG_FB_MSM_BACKLIGHT is not set
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_FB_MSM_MDSS_HDMI_PANEL=y
+CONFIG_FB_MSM_MDSS_HDMI_MHL_SII8334=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_USB=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_EHCI_MSM_HSIC=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_STORAGE_ENE_UB6250=y
+CONFIG_LEDS_QPNP=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_SWITCH=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ASHMEM=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
+CONFIG_SPS=y
+CONFIG_SPS_SUPPORT_BAMDMA=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_QPNP_PWM=y
+CONFIG_QPNP_POWER_ON=y
+CONFIG_QPNP_CLKDIV=y
+CONFIG_MSM_IOMMU=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_PSTORE=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_DETECT_HUNG_TASK is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+CONFIG_FAULT_INJECTION=y
+CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_FAULT_INJECTION_DEBUG_FS=y
+CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_CPU_FREQ_SWITCH_PROFILER=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_KEYS=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEV_QCRYPTO=m
+CONFIG_CRYPTO_DEV_QCE=m
+CONFIG_CRYPTO_DEV_QCEDEV=m
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/msm8226_defconfig b/arch/arm/configs/msm8226_defconfig
new file mode 100644
index 0000000..d0c32e8
--- /dev/null
+++ b/arch/arm/configs/msm8226_defconfig
@@ -0,0 +1,382 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MSM8226=y
+# CONFIG_MSM_STACKED_MEMORY is not set
+CONFIG_CPU_HAS_L2_PMU=y
+# CONFIG_MSM_FIQ_SUPPORT is not set
+# CONFIG_MSM_PROC_COMM is not set
+CONFIG_MSM_SMD=y
+CONFIG_MSM_SMD_PKG4=y
+CONFIG_MSM_BAM_DMUX=y
+CONFIG_MSM_SMP2P=y
+CONFIG_MSM_SMP2P_TEST=y
+CONFIG_MSM_IPC_LOGGING=y
+CONFIG_MSM_IPC_ROUTER=y
+CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
+CONFIG_MSM_QMI_INTERFACE=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
+CONFIG_MSM_PIL_LPASS_QDSP6V5=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
+CONFIG_MSM_PIL_VENUS=y
+CONFIG_MSM_PIL_PRONTO=y
+CONFIG_MSM_TZ_LOG=y
+CONFIG_MSM_DIRECT_SCLK_ACCESS=y
+CONFIG_MSM_WATCHDOG_V2=y
+CONFIG_MSM_MEMORY_DUMP=y
+CONFIG_MSM_DLOAD_MODE=y
+CONFIG_MSM_ADSP_LOADER=m
+CONFIG_MSM_OCMEM=y
+CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
+CONFIG_MSM_OCMEM_DEBUG=y
+CONFIG_MSM_OCMEM_NONSECURE=y
+CONFIG_MSM_OCMEM_POWER_DISABLE=y
+CONFIG_SENSORS_ADSP=y
+CONFIG_MSM_RTB=y
+CONFIG_MSM_RTB_SEPARATE_CPUS=y
+CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
+CONFIG_MSM_BOOT_STATS=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_USE_OF=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+# CONFIG_PM_WAKELOCKS_GC is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_CLS_FW=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCISMD=y
+CONFIG_CFG80211=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CMA=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_MSM_RMNET is not set
+CONFIG_MSM_RMNET_BAM=y
+CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_CORE_PRONTO=y
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI4_DEV=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=m
+CONFIG_SERIAL_MSM_HSL=y
+CONFIG_SERIAL_MSM_HSL_CONSOLE=y
+CONFIG_DIAG_CHAR=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_QUP=y
+CONFIG_SPI=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPMI=y
+CONFIG_MSM_BUS_SCALING=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_MSM_QPNP_INT=y
+CONFIG_SLIMBUS_MSM_NGD=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_QPNP_PIN=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_QPNP_CHARGER=y
+CONFIG_QPNP_BMS=y
+CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
+CONFIG_SENSORS_QPNP_ADC_CURRENT=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_TSENS8974=y
+CONFIG_THERMAL_MONITOR=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_WCD9306_CODEC=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_REGULATOR_QPNP=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_MSM_CAMERA is not set
+CONFIG_OV8825=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_ISPIF=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_OV9724=y
+CONFIG_MSMB_JPEG=y
+CONFIG_SWITCH=y
+CONFIG_MSM_WFD=y
+CONFIG_MSM_VIDC_V4L2=y
+CONFIG_VIDEOBUF2_MSM_MEM=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=m
+CONFIG_ION=y
+CONFIG_ION_MSM=y
+CONFIG_MSM_KGSL=y
+CONFIG_FB=y
+CONFIG_FB_MSM=y
+# CONFIG_FB_MSM_BACKLIGHT is not set
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_MSM8226=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_MMC=y
+CONFIG_MMC_PERF_PROFILING=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=m
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_MSM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_MSM_SPS_SUPPORT=y
+CONFIG_LEDS_QPNP=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_MSM is not set
+CONFIG_RTC_DRV_QPNP=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ASHMEM=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_SPS=y
+CONFIG_USB_BAM=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_QPNP_PWM=y
+CONFIG_QPNP_POWER_ON=y
+CONFIG_MSM_IOMMU=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_TMC=y
+CONFIG_CORESIGHT_TPIU=y
+CONFIG_CORESIGHT_FUNNEL=y
+CONFIG_CORESIGHT_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_ETM=y
+CONFIG_CORESIGHT_EVENT=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+CONFIG_FAULT_INJECTION=y
+CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_FAULT_INJECTION_DEBUG_FS=y
+CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_USER=y
+CONFIG_KEYS=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_TWOFISH=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
+CONFIG_QPNP_VIBRATOR=y
+CONFIG_QSEECOM=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_QCRYPTO=m
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCEDEV=m
\ No newline at end of file
diff --git a/arch/arm/configs/msm8610_defconfig b/arch/arm/configs/msm8610_defconfig
index bff59db..5e38ef1 100644
--- a/arch/arm/configs/msm8610_defconfig
+++ b/arch/arm/configs/msm8610_defconfig
@@ -336,6 +336,7 @@
 CONFIG_CORESIGHT_FUNNEL=y
 CONFIG_CORESIGHT_REPLICATOR=y
 CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_HWEVENT=y
 CONFIG_CORESIGHT_ETM=y
 CONFIG_CORESIGHT_EVENT=m
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index 6dfa8b0..8036a44 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -455,6 +455,7 @@
 CONFIG_CORESIGHT_FUNNEL=y
 CONFIG_CORESIGHT_REPLICATOR=y
 CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_HWEVENT=y
 CONFIG_CORESIGHT_ETM=y
 CONFIG_CORESIGHT_ETM_PCSAVE_DEFAULT_ENABLE=y
 CONFIG_CORESIGHT_EVENT=m
diff --git a/arch/arm/configs/msm9625_defconfig b/arch/arm/configs/msm9625_defconfig
index 7e92748..7891990 100644
--- a/arch/arm/configs/msm9625_defconfig
+++ b/arch/arm/configs/msm9625_defconfig
@@ -285,6 +285,7 @@
 CONFIG_CORESIGHT_FUNNEL=y
 CONFIG_CORESIGHT_REPLICATOR=y
 CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_HWEVENT=y
 CONFIG_CORESIGHT_ETM=y
 CONFIG_CORESIGHT_EVENT=m
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8efc000..321040e 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -297,6 +297,7 @@
 obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o board-9615-gpiomux.o board-9615-storage.o board-9615-display.o
 obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o clock-pll.o
 obj-$(CONFIG_ARCH_APQ8084) += board-8084.o board-8084-gpiomux.o
+obj-$(CONFIG_ARCH_APQ8084) += clock-8084.o
 obj-$(CONFIG_ARCH_MSM8974) += board-8974.o board-8974-gpiomux.o
 obj-$(CONFIG_ARCH_MSM8974) += acpuclock-8974.o
 obj-$(CONFIG_ARCH_MSM8974) += clock-local2.o clock-pll.o clock-8974.o clock-rpm.o clock-voter.o clock-mdss-8974.o
diff --git a/arch/arm/mach-msm/board-8084.c b/arch/arm/mach-msm/board-8084.c
index c20ba92..500c302 100644
--- a/arch/arm/mach-msm/board-8084.c
+++ b/arch/arm/mach-msm/board-8084.c
@@ -74,27 +74,6 @@
 	of_scan_flat_dt(dt_scan_for_memory_hole, apq8084_reserve_table);
 }
 
-static struct clk_lookup msm_clocks_dummy[] = {
-	CLK_DUMMY("core_clk",   BLSP1_UART_CLK, "f991f000.serial", OFF),
-	CLK_DUMMY("iface_clk",  BLSP1_UART_CLK, "f991f000.serial", OFF),
-	CLK_DUMMY("core_clk",	SDC1_CLK,	"msm_sdcc.1", OFF),
-	CLK_DUMMY("iface_clk",	SDC1_P_CLK,	"msm_sdcc.1", OFF),
-	CLK_DUMMY("core_clk",	SDC2_CLK,	"msm_sdcc.2", OFF),
-	CLK_DUMMY("iface_clk",	SDC2_P_CLK,	"msm_sdcc.2", OFF),
-	CLK_DUMMY("xo",   NULL, "f9200000.qcom,ssusb", OFF),
-	CLK_DUMMY("core_clk",   NULL, "f9200000.qcom,ssusb", OFF),
-	CLK_DUMMY("iface_clk",  NULL, "f9200000.qcom,ssusb", OFF),
-	CLK_DUMMY("sleep_clk",  NULL, "f9200000.qcom,ssusb", OFF),
-	CLK_DUMMY("sleep_a_clk",   NULL, "f9200000.qcom,ssusb", OFF),
-	CLK_DUMMY("utmi_clk",   NULL, "f9200000.qcom,ssusb", OFF),
-	CLK_DUMMY("ref_clk",    NULL, "f9200000.qcom,ssusb", OFF),
-};
-
-static struct clock_init_data msm_dummy_clock_init_data __initdata = {
-	.table = msm_clocks_dummy,
-	.size = ARRAY_SIZE(msm_clocks_dummy),
-};
-
 /*
  * Used to satisfy dependencies for devices that need to be
  * run early or in a particular order. Most likely your device doesn't fall
@@ -104,7 +83,7 @@
 void __init apq8084_add_drivers(void)
 {
 	msm_smd_init();
-	msm_clock_init(&msm_dummy_clock_init_data);
+	msm_clock_init(&msm8084_clock_init_data);
 }
 
 static void __init apq8084_map_io(void)
diff --git a/arch/arm/mach-msm/board-8092.c b/arch/arm/mach-msm/board-8092.c
index 3da3e2d..6adff30 100644
--- a/arch/arm/mach-msm/board-8092.c
+++ b/arch/arm/mach-msm/board-8092.c
@@ -29,6 +29,7 @@
 #include <linux/gpio.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <mach/clk-provider.h>
 
 #include "board-dt.h"
 #include "clock.h"
diff --git a/arch/arm/mach-msm/clock-8084.c b/arch/arm/mach-msm/clock-8084.c
new file mode 100644
index 0000000..424b694
--- /dev/null
+++ b/arch/arm/mach-msm/clock-8084.c
@@ -0,0 +1,351 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/rpm-regulator-smd.h>
+#include <mach/socinfo.h>
+#include <mach/rpm-smd.h>
+
+#include "clock-local2.h"
+#include "clock-pll.h"
+#include "clock-rpm.h"
+#include "clock-voter.h"
+#include "clock.h"
+
+/*
+ * TODO: Drivers need to fill in the clock names and device names for the clocks
+ *       they need to control.
+ */
+static struct clk_lookup msm_clocks_8084[] = {
+	CLK_DUMMY("core_clk",   BLSP1_UART_CLK, "f991f000.serial", OFF),
+	CLK_DUMMY("iface_clk",  BLSP1_UART_CLK, "f991f000.serial", OFF),
+	CLK_DUMMY("core_clk",	SDC1_CLK,	"msm_sdcc.1", OFF),
+	CLK_DUMMY("iface_clk",	SDC1_P_CLK,	"msm_sdcc.1", OFF),
+	CLK_DUMMY("core_clk",	SDC2_CLK,	"msm_sdcc.2", OFF),
+	CLK_DUMMY("iface_clk",	SDC2_P_CLK,	"msm_sdcc.2", OFF),
+	CLK_DUMMY("xo",   NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("core_clk",   NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("iface_clk",  NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("sleep_clk",  NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("sleep_a_clk",   NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("utmi_clk",   NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("ref_clk",    NULL, "f9200000.qcom,ssusb", OFF),
+	CLK_DUMMY("",	ufs_axi_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb30_master_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb30_sec_master_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb_hsic_ahb_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sata_asic0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sata_pmalive_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sata_rx_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sata_rx_oob_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sdcc1_apps_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sdcc2_apps_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sdcc3_apps_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	sdcc4_apps_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	tsif_ref_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	ufs_rx_cfg_postdiv_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	ufs_tx_cfg_postdiv_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb30_mock_utmi_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb30_sec_mock_utmi_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb_hs_system_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb_hsic_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb_hsic_io_cal_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb_hsic_mock_utmi_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	usb_hsic_system_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	gcc_bam_dma_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_bam_dma_inactivity_timers_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup1_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup1_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup2_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup2_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup3_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup3_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup4_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup4_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup5_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup5_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup6_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_qup6_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_uart1_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_uart2_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_uart3_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_uart4_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_uart5_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp1_uart6_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup1_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup1_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup2_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup2_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup3_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup3_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup4_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup4_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup5_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup5_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup6_i2c_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_qup6_spi_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_uart1_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_uart2_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_uart3_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_uart4_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_uart5_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_blsp2_uart6_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_boot_rom_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce1_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce1_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce1_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce2_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce2_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce2_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce3_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce3_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ce3_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_copss_smmu_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_copss_smmu_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_dcd_xo_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_bimc_gfx_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_xo_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_xo_div4_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_gp1_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_gp2_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_gp3_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_lpass_mport_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_lpass_q6_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_lpass_sway_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_mmss_bimc_gfx_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_mmss_vpu_maple_sys_noc_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ocmem_noc_cfg_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_msg_ram_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_pdm2_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_pdm_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_pdm_xo4_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_periph_noc_usb_hsic_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_prng_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sata_asic0_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sata_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sata_cfg_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sata_pmalive_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sata_rx_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sata_rx_oob_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc1_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc1_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc1_cdccal_ff_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc1_cdccal_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc2_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc2_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc2_inactivity_timers_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc3_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc3_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc3_inactivity_timers_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc4_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc4_apps_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sdcc4_inactivity_timers_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_spss_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sys_noc_ufs_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sys_noc_usb3_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_sys_noc_usb3_sec_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_tsif_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_tsif_inactivity_timers_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_tsif_ref_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_rx_cfg_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_rx_symbol_0_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_rx_symbol_1_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_tx_cfg_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_tx_symbol_0_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_ufs_tx_symbol_1_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb2a_phy_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb2b_phy_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb30_master_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb30_mock_utmi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb30_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb30_sec_master_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb30_sec_mock_utmi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb30_sec_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hs_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hs_inactivity_timers_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hs_system_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hsic_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hsic_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hsic_io_cal_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hsic_io_cal_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hsic_mock_utmi_clk.c,	"", OFF),
+	CLK_DUMMY("",	gcc_usb_hsic_system_clk.c,	"", OFF),
+
+	CLK_DUMMY("",	axi_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mmpll0_pll_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mmpll1_pll_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mmpll2_pll_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mmpll3_pll_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mmpll4_pll_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi2_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi3_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vcodec0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vfe0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vfe1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	edppixel_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	extpclk_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mdp_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	pclk0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	pclk1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	ocmemnoc_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	gfx3d_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vp_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	cci_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	gp0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	gp1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	jpeg0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	jpeg1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	jpeg2_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mclk0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mclk1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mclk2_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	mclk3_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi0phytimer_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi1phytimer_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	csi2phytimer_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	cpp_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	byte0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	byte1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	edpaux_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	edplink_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	esc0_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	esc1_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	hdmi_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vsync_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	rbbmtimer_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	maple_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vdp_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	vpu_bus_clk_src.c,	"", OFF),
+	CLK_DUMMY("",	dsi0_phy_pll_out_byteclk.c,	"", OFF),
+	CLK_DUMMY("",	dsi0_phy_pll_out_dsiclk.c,	"", OFF),
+	CLK_DUMMY("",	dsi1_phy_pll_out_byteclk.c,	"", OFF),
+	CLK_DUMMY("",	dsi1_phy_pll_out_dsiclk.c,	"", OFF),
+	CLK_DUMMY("",	edpphy_cc_link_clk.c,	"", OFF),
+	CLK_DUMMY("",	edpphy_cc_vco_div_clk.c,	"", OFF),
+	CLK_DUMMY("",	hdmi_phy_pll_out.c,	"", OFF),
+	CLK_DUMMY("",	csiphy_bist_clk.c,	"", OFF),
+	CLK_DUMMY("",	avsync_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	avsync_edppixel_clk.c,	"", OFF),
+	CLK_DUMMY("",	avsync_extpclk_clk.c,	"", OFF),
+	CLK_DUMMY("",	avsync_pclk0_clk.c,	"", OFF),
+	CLK_DUMMY("",	avsync_pclk1_clk.c,	"", OFF),
+	CLK_DUMMY("",	avsync_vp_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_cci_cci_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_cci_cci_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi0_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi0_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi0phy_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi0pix_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi0rdi_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi1_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi1_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi1phy_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi1pix_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi1rdi_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi2_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi2_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi2phy_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi2pix_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi2rdi_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi3_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi3_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi3phy_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi3pix_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi3rdi_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi_vfe0_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_csi_vfe1_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_gp0_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_gp1_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_ispif_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_jpeg_jpeg0_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_jpeg_jpeg1_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_jpeg_jpeg2_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_jpeg_jpeg_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_jpeg_jpeg_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_mclk0_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_mclk1_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_mclk2_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_mclk3_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_micro_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_phy0_csi0phytimer_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_phy1_csi1phytimer_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_phy2_csi2phytimer_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_top_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_vfe_cpp_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_vfe_cpp_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_vfe_vfe0_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_vfe_vfe1_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_vfe_vfe_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	camss_vfe_vfe_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_byte0_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_byte1_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_edpaux_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_edplink_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_edppixel_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_esc0_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_esc1_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_extpclk_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_hdmi_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_hdmi_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_mdp_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_mdp_lut_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_pclk0_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_pclk1_clk.c,	"", OFF),
+	CLK_DUMMY("",	mdss_vsync_clk.c,	"", OFF),
+	CLK_DUMMY("",	mmss_misc_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	mmss_mmssnoc_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	mmss_mmssnoc_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	mmss_s0_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	ocmemcx_ocmemnoc_clk.c,	"", OFF),
+	CLK_DUMMY("",	oxili_ocmemgx_clk.c,	"", OFF),
+	CLK_DUMMY("",	oxili_gfx3d_clk.c,	"", OFF),
+	CLK_DUMMY("",	oxili_rbbmtimer_clk.c,	"", OFF),
+	CLK_DUMMY("",	oxilicx_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	venus0_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	venus0_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	venus0_core0_vcodec_clk.c,	"", OFF),
+	CLK_DUMMY("",	venus0_core1_vcodec_clk.c,	"", OFF),
+	CLK_DUMMY("",	venus0_ocmemnoc_clk.c,	"", OFF),
+	CLK_DUMMY("",	venus0_vcodec0_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_ahb_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_axi_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_bus_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_cxo_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_maple_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_sleep_clk.c,	"", OFF),
+	CLK_DUMMY("",	vpu_vdp_clk.c,	"", OFF),
+};
+
+struct clock_init_data msm8084_clock_init_data __initdata = {
+	.table = msm_clocks_8084,
+	.size = ARRAY_SIZE(msm_clocks_8084),
+};
diff --git a/arch/arm/mach-msm/clock-8226.c b/arch/arm/mach-msm/clock-8226.c
index 6212a4d..ac5efc1 100644
--- a/arch/arm/mach-msm/clock-8226.c
+++ b/arch/arm/mach-msm/clock-8226.c
@@ -3123,6 +3123,7 @@
 	CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
 	CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
 	CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
+	CLK_LOOKUP("core_clk", qdss_clk.c, "fd828018.hwevent"),
 
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
@@ -3156,6 +3157,9 @@
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
+	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fd828018.hwevent"),
+
+	CLK_LOOKUP("core_mmss_clk", mmss_misc_ahb_clk.c, "fd828018.hwevent"),
 
 	/* HSUSB-OTG Clocks */
 	CLK_LOOKUP("xo",                 cxo_otg_clk.c, "f9a55000.usb"),
diff --git a/arch/arm/mach-msm/clock-9625.c b/arch/arm/mach-msm/clock-9625.c
index 313e04c..5bfc4bb 100644
--- a/arch/arm/mach-msm/clock-9625.c
+++ b/arch/arm/mach-msm/clock-9625.c
@@ -1924,6 +1924,7 @@
 	CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
 	CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
 	CLK_LOOKUP("core_clk", qdss_clk.c, "fc333000.cti"),
+	CLK_LOOKUP("core_clk", qdss_clk.c, "f9011038.hwevent"),
 
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
@@ -1945,7 +1946,7 @@
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
 	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc333000.cti"),
-
+	CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "f9011038.hwevent"),
 };
 
 #define PLL_AUX_OUTPUT_BIT 1
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 9ca1965..674ef77 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -53,6 +53,7 @@
 extern struct clock_init_data msm8610_rumi_clock_init_data;
 extern struct clock_init_data msm8226_clock_init_data;
 extern struct clock_init_data msm8226_rumi_clock_init_data;
+extern struct clock_init_data msm8084_clock_init_data;
 
 int msm_clock_init(struct clock_init_data *data);
 int find_vdd_level(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-msm/include/mach/qseecomi.h b/arch/arm/mach-msm/include/mach/qseecomi.h
index e889242..3a997be 100644
--- a/arch/arm/mach-msm/include/mach/qseecomi.h
+++ b/arch/arm/mach-msm/include/mach/qseecomi.h
@@ -67,9 +67,9 @@
 };
 
 enum qseecom_pipe_type {
-	QSEOS_PIPE_ENC = 0,
-	QSEOS_PIPE_ENC_XTS,
-	QSEOS_PIPE_AUTH,
+	QSEOS_PIPE_ENC = 0x1,
+	QSEOS_PIPE_ENC_XTS = 0x2,
+	QSEOS_PIPE_AUTH = 0x4,
 	QSEOS_PIPE_ENUM_FILL = 0x7FFFFFFF
 };
 
diff --git a/arch/arm/mach-msm/include/mach/subsystem_restart.h b/arch/arm/mach-msm/include/mach/subsystem_restart.h
index 893db0b..35b1f76 100644
--- a/arch/arm/mach-msm/include/mach/subsystem_restart.h
+++ b/arch/arm/mach-msm/include/mach/subsystem_restart.h
@@ -41,7 +41,8 @@
  * @powerup: Start a subsystem
  * @crash_shutdown: Shutdown a subsystem when the system crashes (can't sleep)
  * @ramdump: Collect a ramdump of the subsystem
- * @is_loadable: Indicate if subsystem firmware is loadable via pil framework
+ * @is_not_loadable: Indicate if subsystem firmware is not loadable via pil
+ * framework
  */
 struct subsys_desc {
 	const char *name;
@@ -57,7 +58,7 @@
 	void (*crash_shutdown)(const struct subsys_desc *desc);
 	int (*ramdump)(int, const struct subsys_desc *desc);
 	unsigned int err_ready_irq;
-	int is_loadable;
+	int is_not_loadable;
 };
 
 #if defined(CONFIG_MSM_SUBSYSTEM_RESTART)
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_arb.c b/arch/arm/mach-msm/msm_bus/msm_bus_arb.c
index 5002a7d..eddf017 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_arb.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_arb.c
@@ -247,6 +247,11 @@
 				struct msm_bus_fabric_device *gwfab =
 					msm_bus_get_fabric_device(fabnodeinfo->
 						info->node_info->priv_id);
+				if (!gwfab) {
+					MSM_BUS_ERR("Err: No gateway found\n");
+					return -ENXIO;
+				}
+
 				if (!gwfab->visited) {
 					MSM_BUS_DBG("VISITED ID: %d\n",
 						gwfab->id);
@@ -320,6 +325,12 @@
 	struct msm_bus_fabric_device *fabdev = msm_bus_get_fabric_device
 		(GET_FABID(curr));
 
+	if (!fabdev) {
+		MSM_BUS_ERR("Bus device for bus ID: %d not found!\n",
+			GET_FABID(curr));
+		return -ENXIO;
+	}
+
 	MSM_BUS_DBG("args: %d %d %d %llu %llu %llu %llu %u\n",
 		curr, GET_NODE(pnode), GET_INDEX(pnode), req_clk, req_bw,
 		curr_clk, curr_bw, ctx);
@@ -525,6 +536,11 @@
 			goto err;
 		}
 		srcfab = msm_bus_get_fabric_device(GET_FABID(src));
+		if (!srcfab) {
+			MSM_BUS_ERR("Fabric not found\n");
+			goto err;
+		}
+
 		srcfab->visited = true;
 		pnode[i] = getpath(src, dest);
 		bus_for_each_dev(&msm_bus_type, NULL, NULL, clearvisitedflag);
@@ -661,6 +677,12 @@
 	struct msm_bus_fabric_device *fabdev;
 	int index, next_pnode;
 	fabdev = msm_bus_get_fabric_device(GET_FABID(curr));
+	if (!fabdev) {
+		MSM_BUS_ERR("Fabric not found for: %d\n",
+			(GET_FABID(curr)));
+			return -ENXIO;
+	}
+
 	index = GET_INDEX(pnode);
 	info = fabdev->algo->find_node(fabdev, curr);
 	if (!info) {
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c b/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c
index cd6693e..f05b381 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c
@@ -1769,8 +1769,13 @@
 		}
 	}
 
+	if (fab_pdata->virt) {
+		MSM_BUS_DBG("Don't get memory regions for virtual fabric\n");
+		goto skip_mem;
+	}
+
 	bimc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!bimc_mem && !fab_pdata->virt) {
+	if (!bimc_mem) {
 		MSM_BUS_ERR("Cannot get BIMC Base address\n");
 		kfree(binfo);
 		return NULL;
@@ -1792,6 +1797,7 @@
 		return NULL;
 	}
 
+skip_mem:
 	fab_pdata->hw_data = (void *)binfo;
 	return (void *)binfo;
 }
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_config.c b/arch/arm/mach-msm/msm_bus/msm_bus_config.c
index c6fa250..858b15e 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_config.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_config.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -39,7 +39,7 @@
 	MSM_BUS_DBG("master_port: %d iid: %d fabid%d\n",
 		master_port, priv_id, GET_FABID(priv_id));
 	fabdev = msm_bus_get_fabric_device(GET_FABID(priv_id));
-	if (IS_ERR(fabdev)) {
+	if (IS_ERR_OR_NULL(fabdev)) {
 		MSM_BUS_ERR("Fabric device not found for mport: %d\n",
 			master_port);
 		return -ENODEV;
@@ -65,7 +65,7 @@
 	MSM_BUS_DBG("master_port: %d iid: %d fabid: %d\n",
 		master_port, priv_id, GET_FABID(priv_id));
 	fabdev = msm_bus_get_fabric_device(GET_FABID(priv_id));
-	if (IS_ERR(fabdev)) {
+	if (IS_ERR_OR_NULL(fabdev)) {
 		MSM_BUS_ERR("Fabric device not found for mport: %d\n",
 			master_port);
 		return -ENODEV;
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_of.c b/arch/arm/mach-msm/msm_bus/msm_bus_of.c
index af3537c..4e25637 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_of.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_of.c
@@ -103,6 +103,11 @@
 	}
 
 	vec_arr = of_get_property(of_node, "qcom,msm-bus,vectors-KBps", &len);
+	if (vec_arr == NULL) {
+		pr_err("Error: Vector array not found\n");
+		goto err;
+	}
+
 	if (len != num_usecases * num_paths * sizeof(uint32_t) * 4) {
 		pr_err("Error: Length-error on getting vectors\n");
 		goto err;
@@ -432,7 +437,7 @@
 struct msm_bus_fabric_registration
 	*msm_bus_of_get_fab_data(struct platform_device *pdev)
 {
-	struct device_node *of_node = pdev->dev.of_node;
+	struct device_node *of_node;
 	struct msm_bus_fabric_registration *pdata;
 	bool mem_err = false;
 	int ret = 0;
@@ -443,6 +448,7 @@
 		return NULL;
 	}
 
+	of_node = pdev->dev.of_node;
 	pdata = devm_kzalloc(&pdev->dev,
 			sizeof(struct msm_bus_fabric_registration), GFP_KERNEL);
 	if (!pdata) {
diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c
index 9e0be63..1a919fc 100644
--- a/arch/arm/mach-msm/msm_dcvs.c
+++ b/arch/arm/mach-msm/msm_dcvs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -1026,6 +1026,9 @@
 	uint32_t ret1;
 	uint32_t ret2;
 
+	if (!msm_dcvs_enabled)
+		return ret;
+
 	offset = get_core_offset(type, type_core_num);
 	if (offset < 0)
 		return ret;
@@ -1277,6 +1280,9 @@
 	struct kobject *module_kobj = NULL;
 	int ret = 0;
 
+	if (!msm_dcvs_enabled)
+		return ret;
+
 	module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME);
 	if (!module_kobj) {
 		pr_err("%s: cannot find kobject for module %s\n",
@@ -1343,6 +1349,7 @@
 	ret = msm_dcvs_scm_init(SZ_32K);
 	if (ret) {
 		__err("Unable to initialize DCVS err=%d\n", ret);
+		msm_dcvs_enabled = 0;
 		goto done;
 	}
 
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index d657b05..979458e 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -506,7 +506,7 @@
 {
 	struct mba_data *drv = subsys_to_drv(subsys);
 
-	if (!subsys->is_loadable)
+	if (subsys->is_not_loadable)
 		return 0;
 	pil_shutdown(&drv->desc);
 	pil_shutdown(&drv->q6->desc);
@@ -518,7 +518,7 @@
 	struct mba_data *drv = subsys_to_drv(subsys);
 	int ret;
 
-	if (!subsys->is_loadable)
+	if (subsys->is_not_loadable)
 		return 0;
 	/*
 	 * At this time, the modem is shutdown. Therefore this function cannot
@@ -605,7 +605,7 @@
 	int ret;
 	struct mba_data *drv = subsys_to_drv(desc);
 
-	if (!desc->is_loadable)
+	if (desc->is_not_loadable)
 		return 0;
 
 	ret = pil_boot(&drv->q6->desc);
@@ -628,7 +628,7 @@
 {
 	struct mba_data *drv = subsys_to_drv(desc);
 
-	if (!desc->is_loadable)
+	if (desc->is_not_loadable)
 		return;
 
 	pil_shutdown(&drv->desc);
@@ -836,17 +836,18 @@
 static int __devinit pil_mss_driver_probe(struct platform_device *pdev)
 {
 	struct mba_data *drv;
-	int ret, err_fatal_gpio, is_loadable;
+	int ret, err_fatal_gpio, is_not_loadable;
 
 	drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
 	if (!drv)
 		return -ENOMEM;
 	platform_set_drvdata(pdev, drv);
 
-	is_loadable = of_property_read_bool(pdev->dev.of_node,
-							"qcom,is-loadable");
-	if (is_loadable) {
-		drv->subsys_desc.is_loadable = 1;
+	is_not_loadable = of_property_read_bool(pdev->dev.of_node,
+							"qcom,is-not-loadable");
+	if (is_not_loadable) {
+		drv->subsys_desc.is_not_loadable = 1;
+	} else {
 		ret = pil_mss_loadable_init(drv, pdev);
 		if (ret)
 			return ret;
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index 4fca346..33ad83f 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -1248,24 +1248,19 @@
 
 static void setup_broadcast_timer(void *arg)
 {
-	unsigned long reason = (unsigned long)arg;
 	int cpu = smp_processor_id();
 
-	reason = reason ?
-		CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
-
-	clockevents_notify(reason, &cpu);
+	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
 }
 
 static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
 		unsigned long action, void *hcpu)
 {
-	int hotcpu = (unsigned long)hcpu;
+	int cpu = (unsigned long)hcpu;
 
 	switch (action & ~CPU_TASKS_FROZEN) {
 	case CPU_ONLINE:
-		smp_call_function_single(hotcpu, setup_broadcast_timer,
-				(void *)true, 1);
+		smp_call_function_single(cpu, setup_broadcast_timer, NULL, 1);
 		break;
 	}
 
@@ -1292,10 +1287,7 @@
 	msm_cpuidle_init();
 
 	if (msm_pm_pc_reset_timer) {
-		get_cpu();
-		smp_call_function_many(cpu_online_mask, setup_broadcast_timer,
-				(void *)true, 1);
-		put_cpu();
+		on_each_cpu(setup_broadcast_timer, NULL, 1);
 		register_cpu_notifier(&setup_broadcast_notifier);
 	}
 
diff --git a/arch/arm/mach-msm/subsystem_restart.c b/arch/arm/mach-msm/subsystem_restart.c
index 9479d46c..26f0210 100644
--- a/arch/arm/mach-msm/subsystem_restart.c
+++ b/arch/arm/mach-msm/subsystem_restart.c
@@ -495,7 +495,7 @@
 	if (ret)
 		return ret;
 
-	if (!subsys->desc->is_loadable)
+	if (subsys->desc->is_not_loadable)
 		return 0;
 
 	ret = wait_for_err_ready(subsys);
diff --git a/drivers/coresight/coresight-tpiu.c b/drivers/coresight/coresight-tpiu.c
index 7ea71d3..8597e29 100644
--- a/drivers/coresight/coresight-tpiu.c
+++ b/drivers/coresight/coresight-tpiu.c
@@ -218,6 +218,24 @@
 	return 0;
 }
 
+static int tpiu_reg_set_optimum_mode(struct regulator *reg,
+				     unsigned int reg_hpm)
+{
+	if (regulator_count_voltages(reg) <= 0)
+		return 0;
+
+	return regulator_set_optimum_mode(reg, reg_hpm);
+}
+
+static int tpiu_reg_set_voltage(struct regulator *reg, unsigned int reg_low,
+				unsigned int reg_high)
+{
+	if (regulator_count_voltages(reg) <= 0)
+		return 0;
+
+	return regulator_set_voltage(reg, reg_low, reg_high);
+}
+
 static int __tpiu_enable_to_sdc(struct tpiu_drvdata *drvdata)
 {
 	int ret;
@@ -225,11 +243,11 @@
 	if (!drvdata->reg)
 		return -EINVAL;
 
-	ret = regulator_set_optimum_mode(drvdata->reg, drvdata->reg_hpm);
+	ret = tpiu_reg_set_optimum_mode(drvdata->reg, drvdata->reg_hpm);
 	if (ret < 0)
 		return ret;
-	ret = regulator_set_voltage(drvdata->reg, drvdata->reg_low,
-				    drvdata->reg_high);
+	ret = tpiu_reg_set_voltage(drvdata->reg, drvdata->reg_low,
+				   drvdata->reg_high);
 	if (ret)
 		goto err0;
 	ret = regulator_enable(drvdata->reg);
@@ -248,9 +266,9 @@
 
 	return 0;
 err1:
-	regulator_set_voltage(drvdata->reg, 0, drvdata->reg_high);
+	tpiu_reg_set_voltage(drvdata->reg, 0, drvdata->reg_high);
 err0:
-	regulator_set_optimum_mode(drvdata->reg, 0);
+	tpiu_reg_set_optimum_mode(drvdata->reg, 0);
 	return ret;
 }
 
@@ -325,8 +343,8 @@
 	msm_tlmm_misc_reg_write(TLMM_ETM_MODE_REG, 0);
 
 	regulator_disable(drvdata->reg);
-	regulator_set_optimum_mode(drvdata->reg, 0);
-	regulator_set_voltage(drvdata->reg, 0, drvdata->reg_high);
+	tpiu_reg_set_optimum_mode(drvdata->reg, 0);
+	tpiu_reg_set_voltage(drvdata->reg, 0, drvdata->reg_high);
 }
 
 static void tpiu_disable(struct coresight_device *csdev)
@@ -531,7 +549,7 @@
 		prop = of_get_property(node, "qcom,vdd-voltage-level", &len);
 		if (!prop || (len != (2 * sizeof(__be32)))) {
 			of_node_put(reg_node);
-			return -EINVAL;
+			dev_err(dev, "sdc voltage levels not specified\n");
 		} else {
 			drvdata->reg_low = be32_to_cpup(&prop[0]);
 			drvdata->reg_high = be32_to_cpup(&prop[1]);
@@ -540,7 +558,7 @@
 		prop = of_get_property(node, "qcom,vdd-current-level", &len);
 		if (!prop || (len != (2 * sizeof(__be32)))) {
 			of_node_put(reg_node);
-			return -EINVAL;
+			dev_err(dev, "sdc current levels not specified\n");
 		} else {
 			drvdata->reg_lpm = be32_to_cpup(&prop[0]);
 			drvdata->reg_hpm = be32_to_cpup(&prop[1]);
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index f071801..a4f60f9 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -101,13 +101,6 @@
 		.iomemname = KGSL_3D0_REG_MEMORY,
 		.shadermemname = KGSL_3D0_SHADER_MEMORY,
 		.ftbl = &adreno_functable,
-#ifdef CONFIG_HAS_EARLYSUSPEND
-		.display_off = {
-			.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING,
-			.suspend = kgsl_early_suspend_driver,
-			.resume = kgsl_late_resume_driver,
-		},
-#endif
 	},
 	.gmem_base = 0,
 	.gmem_size = SZ_256K,
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 07f8ef5..992f88d 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -625,20 +625,6 @@
 };
 EXPORT_SYMBOL(kgsl_pm_ops);
 
-void kgsl_early_suspend_driver(struct early_suspend *h)
-{
-	struct kgsl_device *device = container_of(h,
-					struct kgsl_device, display_off);
-	KGSL_PWR_WARN(device, "early suspend start\n");
-	mutex_lock(&device->mutex);
-	device->pwrctrl.restore_slumber = true;
-	kgsl_pwrctrl_request_state(device, KGSL_STATE_SLUMBER);
-	kgsl_pwrctrl_sleep(device);
-	mutex_unlock(&device->mutex);
-	KGSL_PWR_WARN(device, "early suspend end\n");
-}
-EXPORT_SYMBOL(kgsl_early_suspend_driver);
-
 int kgsl_suspend_driver(struct platform_device *pdev,
 					pm_message_t state)
 {
@@ -654,29 +640,6 @@
 }
 EXPORT_SYMBOL(kgsl_resume_driver);
 
-void kgsl_late_resume_driver(struct early_suspend *h)
-{
-	struct kgsl_device *device = container_of(h,
-					struct kgsl_device, display_off);
-	KGSL_PWR_WARN(device, "late resume start\n");
-	mutex_lock(&device->mutex);
-	device->pwrctrl.restore_slumber = false;
-	if (device->pwrscale.policy == NULL)
-		kgsl_pwrctrl_pwrlevel_change(device, KGSL_PWRLEVEL_TURBO);
-	if (kgsl_pwrctrl_wake(device) != 0)
-		return;
-	/*
-	 * We don't have a way to go directly from
-	 * a deeper sleep state to NAP, which is
-	 * the desired state here.
-	 */
-	kgsl_pwrctrl_request_state(device, KGSL_STATE_NAP);
-	kgsl_pwrctrl_sleep(device);
-	mutex_unlock(&device->mutex);
-	KGSL_PWR_WARN(device, "late resume end\n");
-}
-EXPORT_SYMBOL(kgsl_late_resume_driver);
-
 /**
  * kgsl_destroy_process_private() - Cleanup function to free process private
  * @kref: - Pointer to object being destroyed's kref struct
@@ -946,7 +909,12 @@
 		result = device->ftbl->start(device);
 		if (result)
 			goto err_freedevpriv;
-
+		/*
+		 * Make sure the gates are open, so they don't block until
+		 * we start suspend or FT.
+		 */
+		complete_all(&device->ft_gate);
+		complete_all(&device->hwaccess_gate);
 		kgsl_pwrctrl_set_state(device, KGSL_STATE_ACTIVE);
 		kgsl_active_count_put(device);
 	}
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index 94cc551..c7cbaf8 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -226,11 +226,8 @@
 
 extern const struct dev_pm_ops kgsl_pm_ops;
 
-struct early_suspend;
 int kgsl_suspend_driver(struct platform_device *pdev, pm_message_t state);
 int kgsl_resume_driver(struct platform_device *pdev);
-void kgsl_early_suspend_driver(struct early_suspend *h);
-void kgsl_late_resume_driver(struct early_suspend *h);
 
 void kgsl_trace_regwrite(struct kgsl_device *device, unsigned int offset,
 		unsigned int value);
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index 42c1475..e80721a 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -15,7 +15,6 @@
 
 #include <linux/idr.h>
 #include <linux/pm_qos.h>
-#include <linux/earlysuspend.h>
 
 #include "kgsl.h"
 #include "kgsl_mmu.h"
@@ -190,7 +189,6 @@
 	struct completion ft_gate;
 	struct dentry *d_debugfs;
 	struct idr context_idr;
-	struct early_suspend display_off;
 
 	void *snapshot;		/* Pointer to the snapshot memory region */
 	int snapshot_maxsize;   /* Max size of the snapshot region */
diff --git a/drivers/gpu/msm/kgsl_events.c b/drivers/gpu/msm/kgsl_events.c
index d872783..3b01e54 100644
--- a/drivers/gpu/msm/kgsl_events.c
+++ b/drivers/gpu/msm/kgsl_events.c
@@ -143,6 +143,15 @@
 	cur = kgsl_readtimestamp(device, context, KGSL_TIMESTAMP_RETIRED);
 	id = context->id;
 
+	/*
+	 * Increment the refcount to avoid freeing the context while
+	 * cancelling its events
+	 */
+	kgsl_context_get(context);
+
+	/* Remove ourselves from the master pending list */
+	list_del_init(&context->events_list);
+
 	list_for_each_entry_safe(event, event_tmp, &context->events, list) {
 		/*
 		 * "cancel" the events by calling their callback.
@@ -165,9 +174,7 @@
 
 		kgsl_active_count_put(device);
 	}
-
-	/* Remove ourselves from the master pending list */
-	list_del_init(&context->events_list);
+	kgsl_context_put(context);
 }
 
 /**
@@ -313,12 +320,18 @@
 		events_list) {
 
 		/*
+		 * Increment the refcount to make sure that the list_del_init
+		 * is called with a valid context's list
+		 */
+		kgsl_context_get(context);
+		/*
 		 * If kgsl_timestamp_expired_context returns 0 then it no longer
 		 * has any pending events and can be removed from the list
 		 */
 
 		if (kgsl_process_context_events(device, context) == 0)
 			list_del_init(&context->events_list);
+		kgsl_context_put(context);
 	}
 
 	mutex_unlock(&device->mutex);
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index b124257..e071650 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -1021,7 +1021,6 @@
 	pwr->pm_qos_latency = 501;
 
 	pm_runtime_enable(device->parentdev);
-	register_early_suspend(&device->display_off);
 	return result;
 
 clk_err:
@@ -1041,7 +1040,6 @@
 	KGSL_PWR_INFO(device, "close device %d\n", device->id);
 
 	pm_runtime_disable(device->parentdev);
-	unregister_early_suspend(&device->display_off);
 
 	clk_put(pwr->ebi1_clk);
 
@@ -1151,8 +1149,7 @@
 
 	KGSL_PWR_INFO(device, "idle timer expired device %d\n", device->id);
 	if (device->requested_state != KGSL_STATE_SUSPEND) {
-		if (device->pwrctrl.restore_slumber ||
-					device->pwrctrl.strtstp_sleepwake)
+		if (device->pwrctrl.strtstp_sleepwake)
 			kgsl_pwrctrl_request_state(device, KGSL_STATE_SLUMBER);
 		else
 			kgsl_pwrctrl_request_state(device, KGSL_STATE_SLEEP);
@@ -1448,16 +1445,11 @@
 	BUG_ON(!mutex_is_locked(&device->mutex));
 
 	if (device->active_cnt == 0) {
-		if (device->requested_state == KGSL_STATE_SUSPEND ||
-				device->state == KGSL_STATE_SUSPEND) {
-			mutex_unlock(&device->mutex);
-			wait_for_completion(&device->hwaccess_gate);
-			mutex_lock(&device->mutex);
-		} else if (device->state == KGSL_STATE_DUMP_AND_FT) {
-			mutex_unlock(&device->mutex);
-			wait_for_completion(&device->ft_gate);
-			mutex_lock(&device->mutex);
-		}
+		mutex_unlock(&device->mutex);
+		wait_for_completion(&device->hwaccess_gate);
+		wait_for_completion(&device->ft_gate);
+		mutex_lock(&device->mutex);
+
 		ret = kgsl_pwrctrl_wake(device);
 	}
 	if (ret == 0)
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index b3e8702..2b986c8 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -58,7 +58,6 @@
  * @nap_allowed - true if the device supports naps
  * @idle_needed - true if the device needs a idle before clock change
  * @irq_name - resource name for the IRQ
- * @restore_slumber - Flag to indicate that we are in a suspend/restore sequence
  * @clk_stats - structure of clock statistics
  * @pm_qos_req_dma - the power management quality of service structure
  * @pm_qos_latency - allowed CPU latency in microseconds
@@ -86,7 +85,6 @@
 	unsigned int idle_needed;
 	const char *irq_name;
 	s64 time;
-	unsigned int restore_slumber;
 	struct kgsl_clk_stats clk_stats;
 	struct pm_qos_request pm_qos_req_dma;
 	unsigned int pm_qos_latency;
diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c
index 275291f..09fcd0e 100644
--- a/drivers/hwmon/qpnp-adc-current.c
+++ b/drivers/hwmon/qpnp-adc-current.c
@@ -95,6 +95,7 @@
 #define QPNP_IADC_LSB_OFFSET				0xF3
 #define QPNP_IADC_NOMINAL_RSENSE			0xF4
 #define QPNP_IADC_ATE_GAIN_CALIB_OFFSET			0xF5
+#define QPNP_INT_TEST_VAL				0xE1
 
 #define QPNP_IADC_ADC_CH_SEL_CTL			0x48
 #define QPNP_IADC_ADC_CHX_SEL_SHIFT			3
@@ -126,16 +127,24 @@
 #define QPNP_RSENSE_MSB_SIGN_CHECK			0x80
 #define QPNP_ADC_COMPLETION_TIMEOUT			HZ
 
+struct qpnp_iadc_comp {
+	bool	ext_rsense;
+	u8	id;
+	u8	sys_gain;
+	u8	revision;
+};
+
 struct qpnp_iadc_drv {
 	struct qpnp_adc_drv			*adc;
 	int32_t					rsense;
 	bool					external_rsense;
 	struct device				*iadc_hwmon;
 	bool					iadc_initialized;
-	int64_t					die_temp_calib_offset;
+	int64_t					die_temp;
 	struct delayed_work			iadc_work;
 	struct mutex				iadc_vadc_lock;
 	bool					iadc_mode_sel;
+	struct qpnp_iadc_comp			iadc_comp;
 	struct sensor_device_attribute		sens_attr[0];
 };
 
@@ -293,6 +302,99 @@
 	return 0;
 }
 
+static int32_t qpnp_iadc_comp(int64_t *result, struct qpnp_iadc_comp comp,
+							int64_t die_temp)
+{
+	int64_t temp_var = 0, sign_coeff = 0, sys_gain_coeff = 0;
+
+	*result = *result * 1000000;
+
+	if (comp.revision == QPNP_IADC_VER_3_1) {
+		/* revision 3.1 */
+		if (comp.sys_gain > 127)
+			sys_gain_coeff = -QPNP_COEFF_6 * (comp.sys_gain - 128);
+		else
+			sys_gain_coeff = QPNP_COEFF_6 * comp.sys_gain;
+	}
+
+	comp.id = 0;
+	if (!comp.ext_rsense) {
+		/* internal rsense */
+		switch (comp.id) {
+		case COMP_ID_TSMC:
+			temp_var = ((QPNP_COEFF_2 * die_temp) -
+						QPNP_COEFF_3_TYPEB);
+		break;
+		case COMP_ID_GF:
+		default:
+			temp_var = ((QPNP_COEFF_2 * die_temp) -
+						QPNP_COEFF_3_TYPEA);
+		break;
+		}
+		temp_var = div64_s64(temp_var, QPNP_COEFF_4);
+		if (comp.revision == QPNP_IADC_VER_3_0)
+			temp_var = QPNP_COEFF_1 * (1000000 - temp_var);
+		else if (comp.revision == QPNP_IADC_VER_3_1)
+			temp_var = (1000000 - temp_var);
+		*result = div64_s64(*result, temp_var);
+	}
+
+	sign_coeff = *result < 0 ? QPNP_COEFF_7 : QPNP_COEFF_5;
+	if (comp.ext_rsense) {
+		/* external rsense and current charging */
+		temp_var = div64_s64((-sign_coeff * die_temp) + QPNP_COEFF_8,
+						QPNP_COEFF_4);
+		temp_var = 1000000000 - temp_var;
+		if (comp.revision == QPNP_IADC_VER_3_1) {
+			sys_gain_coeff = (1000000 +
+				div64_s64(sys_gain_coeff, QPNP_COEFF_4));
+			temp_var = div64_s64(temp_var * sys_gain_coeff,
+				1000000000);
+		}
+		*result = div64_s64(*result, temp_var);
+	}
+
+	return 0;
+}
+
+int32_t qpnp_iadc_comp_result(int64_t *result)
+{
+	struct qpnp_iadc_drv *iadc = qpnp_iadc;
+
+	return qpnp_iadc_comp(result, iadc->iadc_comp, iadc->die_temp);
+}
+EXPORT_SYMBOL(qpnp_iadc_comp_result);
+
+static int32_t qpnp_iadc_comp_info(void)
+{
+	struct qpnp_iadc_drv *iadc = qpnp_iadc;
+	int rc = 0;
+
+	rc = qpnp_iadc_read_reg(QPNP_INT_TEST_VAL, &iadc->iadc_comp.id);
+	if (rc < 0) {
+		pr_err("qpnp adc comp id failed with %d\n", rc);
+		return rc;
+	}
+
+	rc = qpnp_iadc_read_reg(QPNP_IADC_REVISION2, &iadc->iadc_comp.revision);
+	if (rc < 0) {
+		pr_err("qpnp adc revision read failed with %d\n", rc);
+		return rc;
+	}
+
+	rc = qpnp_iadc_read_reg(QPNP_IADC_ATE_GAIN_CALIB_OFFSET,
+						&iadc->iadc_comp.sys_gain);
+	if (rc < 0)
+		pr_err("full scale read failed with %d\n", rc);
+
+	pr_debug("fab id = %u, revision = %u, sys gain = %u, external_rsense = %d\n",
+			iadc->iadc_comp.id,
+			iadc->iadc_comp.revision,
+			iadc->iadc_comp.sys_gain,
+			iadc->iadc_comp.ext_rsense);
+	return rc;
+}
+
 static int32_t qpnp_iadc_configure(enum qpnp_iadc_channels channel,
 					uint16_t *raw_code, uint32_t mode_sel)
 {
@@ -583,12 +685,12 @@
 		return rc;
 
 	die_temp_offset = result_pmic_therm.physical -
-			iadc->die_temp_calib_offset;
+			iadc->die_temp;
 	if (die_temp_offset < 0)
 		die_temp_offset = -die_temp_offset;
 
 	if (die_temp_offset > QPNP_IADC_DIE_TEMP_CALIB_OFFSET) {
-		iadc->die_temp_calib_offset =
+		iadc->die_temp =
 			result_pmic_therm.physical;
 		rc = qpnp_iadc_calibrate_for_trim();
 		if (rc)
@@ -640,12 +742,17 @@
 		(iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw);
 	result_current = result->result_uv;
 	result_current *= QPNP_IADC_NANO_VOLTS_FACTOR;
+	/* Intentional fall through. Process the result w/o comp */
 	do_div(result_current, rsense_u_ohms);
 
 	if (sign) {
 		result->result_uv = -result->result_uv;
 		result_current = -result_current;
 	}
+	rc = qpnp_iadc_comp_result(&result_current);
+	if (rc < 0)
+		pr_err("Error during compensating the IADC\n");
+	rc = 0;
 
 	result->result_ua = (int32_t) result_current;
 fail:
@@ -868,6 +975,11 @@
 
 	mutex_init(&iadc->iadc_vadc_lock);
 	INIT_DELAYED_WORK(&iadc->iadc_work, qpnp_iadc_work);
+	rc = qpnp_iadc_comp_info();
+	if (rc) {
+		dev_err(&spmi->dev, "abstracting IADC comp info failed!\n");
+		goto fail;
+	}
 	iadc->iadc_initialized = true;
 
 	rc = qpnp_iadc_calibrate_for_trim();
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index edb1d66..cc7073e 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -83,6 +83,7 @@
 #define QPNP_VADC_M1_LOW_THR_MSB					0x6a
 #define QPNP_VADC_M1_HIGH_THR_LSB				0x6b
 #define QPNP_VADC_M1_HIGH_THR_MSB				0x6c
+#define QPNP_INT_TEST_VAL					0xE1
 
 #define QPNP_VADC_DATA0						0x60
 #define QPNP_VADC_DATA1						0x61
@@ -100,7 +101,8 @@
 	bool				vadc_initialized;
 	int				max_channels_available;
 	bool				vadc_iadc_sync_lock;
-	struct sensor_device_attribute		sens_attr[0];
+	u8				id;
+	struct sensor_device_attribute	sens_attr[0];
 };
 
 struct qpnp_vadc_drv *qpnp_vadc;
@@ -432,6 +434,60 @@
 	return 0;
 }
 
+static int32_t qpnp_vbat_sns_comp(int64_t *result, u8 id, int64_t die_temp)
+{
+	int64_t temp_var = 0;
+
+	if (die_temp < 25000)
+		return 0;
+
+	switch (id) {
+	case COMP_ID_TSMC:
+		temp_var = (((die_temp *
+			(-QPNP_VBAT_SNS_COEFF_1_TYPEB))
+			+ QPNP_VBAT_SNS_COEFF_2_TYPEB));
+	break;
+	default:
+	case COMP_ID_GF:
+		temp_var = (((die_temp *
+			(-QPNP_VBAT_SNS_COEFF_1_TYPEA))
+			+ QPNP_VBAT_SNS_COEFF_2_TYPEA));
+	break;
+	}
+
+	temp_var = div64_s64(temp_var, QPNP_VBAT_SNS_COEFF_3);
+
+	temp_var = 1000000 + temp_var;
+
+	*result = *result * temp_var;
+
+	*result = div64_s64(*result, 1000000);
+
+	return 0;
+}
+
+int32_t qpnp_vbat_sns_comp_result(int64_t *result)
+{
+	struct qpnp_vadc_drv *vadc = qpnp_vadc;
+	struct qpnp_vadc_result die_temp_result;
+	int rc = 0;
+
+	rc = qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
+			DIE_TEMP, &die_temp_result);
+	if (rc < 0) {
+		pr_err("Error reading die_temp\n");
+		return rc;
+	}
+
+	rc = qpnp_vbat_sns_comp(result, vadc->id,
+					die_temp_result.physical);
+	if (rc < 0)
+		pr_err("Error with vbat compensation\n");
+
+	return rc;
+}
+EXPORT_SYMBOL(qpnp_vbat_sns_comp_result);
+
 static void qpnp_vadc_625mv_channel_sel(uint32_t *ref_channel_sel)
 {
 	struct qpnp_vadc_drv *vadc = qpnp_vadc;
@@ -790,7 +846,34 @@
 int32_t qpnp_vadc_read(enum qpnp_vadc_channels channel,
 				struct qpnp_vadc_result *result)
 {
-	return qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
+	struct qpnp_vadc_drv *vadc = qpnp_vadc;
+	enum qpnp_vadc_channels;
+	struct qpnp_vadc_result die_temp_result;
+	int rc = 0;
+
+	if (channel == VBAT_SNS) {
+		rc = qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
+				channel, result);
+		if (rc < 0) {
+			pr_err("Error reading vbatt\n");
+			return rc;
+		}
+
+		rc = qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
+				DIE_TEMP, &die_temp_result);
+		if (rc < 0) {
+			pr_err("Error reading die_temp\n");
+			return rc;
+		}
+
+		rc = qpnp_vbat_sns_comp(&result->physical, vadc->id,
+						die_temp_result.physical);
+		if (rc < 0)
+			pr_err("Error with vbat compensation\n");
+
+		return 0;
+	} else
+		return qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
 				channel, result);
 }
 EXPORT_SYMBOL(qpnp_vadc_read);
@@ -970,6 +1053,7 @@
 	struct device_node *node = spmi->dev.of_node;
 	struct device_node *child;
 	int rc, count_adc_channel_list = 0;
+	u8 fab_id = 0;
 
 	if (!node)
 		return -EINVAL;
@@ -1033,6 +1117,13 @@
 	vadc->vadc_hwmon = hwmon_device_register(&vadc->adc->spmi->dev);
 	vadc->vadc_init_calib = false;
 	vadc->max_channels_available = count_adc_channel_list;
+	rc = qpnp_vadc_read_reg(QPNP_INT_TEST_VAL, &fab_id);
+	if (rc < 0) {
+		pr_err("qpnp adc comp id failed with %d\n", rc);
+		return rc;
+	}
+	vadc->id = fab_id;
+
 	vadc->vadc_initialized = true;
 	vadc->vadc_iadc_sync_lock = false;
 
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c
index 59b9746..509567c 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c
@@ -70,7 +70,7 @@
 }
 
 static struct msm_cam_clk_info jpeg_8x_clk_info[] = {
-	{"core_clk", 228570000},
+	{"core_clk", JPEG_CLK_RATE},
 	{"iface_clk", -1},
 	{"bus_clk0", -1},
 	{"camss_top_ahb_clk", -1},
@@ -135,8 +135,8 @@
 	{
 		.src = MSM_BUS_MASTER_JPEG,
 		.dst = MSM_BUS_SLAVE_EBI_CH0,
-		.ab  = 1027648000,
-		.ib  = 1105920000,
+		.ab  = JPEG_CLK_RATE * 2.5,
+		.ib  = JPEG_CLK_RATE * 2.5,
 	},
 };
 
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h
index cd80d2e..a14b8ee 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,7 @@
 #include <linux/iommu.h>
 #include <mach/iommu.h>
 #include "msm_jpeg_sync.h"
+#define JPEG_CLK_RATE 266670000
 
 void msm_jpeg_platform_p2v(struct msm_jpeg_device *pgmn_dev, struct file *file,
 	struct ion_handle **ionhandle, int domain_num);
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index fcadc30..fa28d6a 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -1918,6 +1918,10 @@
 		qclk = &qseecom.ce_drv;
 
 	mutex_lock(&clk_access_lock);
+
+	if (qclk->clk_access_cnt == ULONG_MAX)
+		goto err;
+
 	if (qclk->clk_access_cnt > 0) {
 		qclk->clk_access_cnt++;
 		mutex_unlock(&clk_access_lock);
@@ -1965,6 +1969,12 @@
 		qclk = &qseecom.ce_drv;
 
 	mutex_lock(&clk_access_lock);
+
+	if (qclk->clk_access_cnt == 0) {
+		mutex_unlock(&clk_access_lock);
+		return;
+	}
+
 	if (qclk->clk_access_cnt == 1) {
 		if (qclk->ce_clk != NULL)
 			clk_disable_unprepare(qclk->ce_clk);
@@ -2495,8 +2505,8 @@
 	ireq.pipe = set_key_para->pipe;
 	ireq.flags = set_key_para->flags;
 
-	/* set PIPE_ENC */
-	ireq.pipe_type = QSEOS_PIPE_ENC;
+	/* set both PIPE_ENC and PIPE_ENC_XTS*/
+	ireq.pipe_type = QSEOS_PIPE_ENC|QSEOS_PIPE_ENC_XTS;
 
 	if (set_key_para->set_clear_key_flag ==
 			QSEECOM_SET_CE_KEY_CMD)
@@ -2513,17 +2523,6 @@
 		return ret;
 	}
 
-	/* set PIPE_ENC_XTS */
-	ireq.pipe_type = QSEOS_PIPE_ENC_XTS;
-	ret = scm_call(SCM_SVC_TZSCHEDULER, 1,
-				&ireq, sizeof(struct qseecom_key_select_ireq),
-				&resp, sizeof(struct qseecom_command_scm_resp));
-	if (ret) {
-		pr_err("scm call to set QSEOS_PIPE_ENC_XTS key failed : %d\n",
-			ret);
-		return ret;
-	}
-
 	switch (resp.result) {
 	case QSEOS_RESULT_SUCCESS:
 		break;
diff --git a/drivers/platform/msm/ipa/ipa_dp.c b/drivers/platform/msm/ipa/ipa_dp.c
index 76aaad0..1b6181f 100644
--- a/drivers/platform/msm/ipa/ipa_dp.c
+++ b/drivers/platform/msm/ipa/ipa_dp.c
@@ -232,7 +232,7 @@
 	struct ipa_tx_pkt_wrapper *tx_pkt;
 	unsigned long irq_flags;
 	int result;
-	u16 sps_flags = SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_INT;
+	u16 sps_flags = SPS_IOVEC_FLAG_EOT;
 	dma_addr_t dma_address;
 	u16 len;
 	u32 mem_flag = GFP_ATOMIC;
@@ -469,8 +469,7 @@
 		}
 
 		if (i == (num_desc - 1)) {
-			iovec->flags |= (SPS_IOVEC_FLAG_EOT |
-					SPS_IOVEC_FLAG_INT);
+			iovec->flags |= SPS_IOVEC_FLAG_EOT;
 			/* "mark" the last desc */
 			tx_pkt->cnt = IPA_LAST_DESC_CNT;
 		}
@@ -1018,11 +1017,8 @@
 		ipa_ctx->ep[ipa_ep_idx].connect.dest_pipe_index =
 			ipa_ctx->a5_pipe_index++;
 		ipa_ctx->ep[ipa_ep_idx].connect.src_pipe_index = ipa_ep_idx;
-		ipa_ctx->ep[ipa_ep_idx].connect.options =
-			SPS_O_AUTO_ENABLE | SPS_O_EOT | SPS_O_ACK_TRANSFERS |
+		ipa_ctx->ep[ipa_ep_idx].connect.options = SPS_O_ACK_TRANSFERS |
 			SPS_O_NO_DISABLE;
-		if (ipa_ctx->polling_mode)
-			ipa_ctx->ep[ipa_ep_idx].connect.options |= SPS_O_POLL;
 	} else {
 		ipa_ctx->ep[ipa_ep_idx].connect.mode = SPS_MODE_DEST;
 		ipa_ctx->ep[ipa_ep_idx].connect.source = SPS_DEV_HANDLE_MEM;
@@ -1031,13 +1027,16 @@
 		ipa_ctx->ep[ipa_ep_idx].connect.src_pipe_index =
 			ipa_ctx->a5_pipe_index++;
 		ipa_ctx->ep[ipa_ep_idx].connect.dest_pipe_index = ipa_ep_idx;
-		ipa_ctx->ep[ipa_ep_idx].connect.options =
-			SPS_O_AUTO_ENABLE | SPS_O_EOT;
-		if (ipa_ctx->polling_mode)
+		if (sys_in->client == IPA_CLIENT_A5_LAN_WAN_PROD)
 			ipa_ctx->ep[ipa_ep_idx].connect.options |=
-				SPS_O_ACK_TRANSFERS | SPS_O_POLL;
+				SPS_O_ACK_TRANSFERS;
 	}
 
+	ipa_ctx->ep[ipa_ep_idx].connect.options |= (SPS_O_AUTO_ENABLE |
+		SPS_O_EOT);
+	if (ipa_ctx->polling_mode)
+		ipa_ctx->ep[ipa_ep_idx].connect.options |= SPS_O_POLL;
+
 	ipa_ctx->ep[ipa_ep_idx].connect.desc.size = sys_in->desc_fifo_sz;
 	ipa_ctx->ep[ipa_ep_idx].connect.desc.base =
 	   dma_alloc_coherent(NULL, ipa_ctx->ep[ipa_ep_idx].connect.desc.size,
@@ -1346,7 +1345,7 @@
 
 		ret = sps_transfer_one(sys->ep->ep_hdl, rx_pkt->dma_address,
 				       IPA_RX_SKB_SIZE, rx_pkt,
-				       SPS_IOVEC_FLAG_INT);
+				       0);
 
 		if (ret) {
 			IPAERR("sps_transfer_one failed %d\n", ret);
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index 1907adc..a85e31c 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -24,47 +24,51 @@
 #include <linux/log2.h>
 
 /* PON common register addresses */
-#define QPNP_PON_RT_STS(base)		(base + 0x10)
-#define QPNP_PON_PULL_CTL(base)		(base + 0x70)
-#define QPNP_PON_DBC_CTL(base)		(base + 0x71)
+#define QPNP_PON_RT_STS(base)			(base + 0x10)
+#define QPNP_PON_PULL_CTL(base)			(base + 0x70)
+#define QPNP_PON_DBC_CTL(base)			(base + 0x71)
 
 /* PON/RESET sources register addresses */
-#define QPNP_PON_KPDPWR_S1_TIMER(base)	(base + 0x40)
-#define QPNP_PON_KPDPWR_S2_TIMER(base)	(base + 0x41)
-#define QPNP_PON_KPDPWR_S2_CNTL(base)	(base + 0x42)
-#define QPNP_PON_RESIN_S1_TIMER(base)	(base + 0x44)
-#define QPNP_PON_RESIN_S2_TIMER(base)	(base + 0x45)
-#define QPNP_PON_RESIN_S2_CNTL(base)	(base + 0x46)
-#define QPNP_PON_PS_HOLD_RST_CTL(base)	(base + 0x5A)
+#define QPNP_PON_WARM_RESET_REASON1(base)	(base + 0xA)
+#define QPNP_PON_WARM_RESET_REASON2(base)	(base + 0xB)
+#define QPNP_PON_KPDPWR_S1_TIMER(base)		(base + 0x40)
+#define QPNP_PON_KPDPWR_S2_TIMER(base)		(base + 0x41)
+#define QPNP_PON_KPDPWR_S2_CNTL(base)		(base + 0x42)
+#define QPNP_PON_RESIN_S1_TIMER(base)		(base + 0x44)
+#define QPNP_PON_RESIN_S2_TIMER(base)		(base + 0x45)
+#define QPNP_PON_RESIN_S2_CNTL(base)		(base + 0x46)
+#define QPNP_PON_PS_HOLD_RST_CTL(base)		(base + 0x5A)
 
-#define QPNP_PON_RESIN_PULL_UP		BIT(0)
-#define QPNP_PON_KPDPWR_PULL_UP		BIT(1)
-#define QPNP_PON_CBLPWR_PULL_UP		BIT(2)
-#define QPNP_PON_S2_CNTL_EN		BIT(7)
-#define QPNP_PON_S2_RESET_ENABLE	BIT(7)
-#define QPNP_PON_DELAY_BIT_SHIFT	6
+#define QPNP_PON_WARM_RESET_TFT			BIT(4)
 
-#define QPNP_PON_S1_TIMER_MASK		(0xF)
-#define QPNP_PON_S2_TIMER_MASK		(0x7)
-#define QPNP_PON_S2_CNTL_TYPE_MASK	(0xF)
+#define QPNP_PON_RESIN_PULL_UP			BIT(0)
+#define QPNP_PON_KPDPWR_PULL_UP			BIT(1)
+#define QPNP_PON_CBLPWR_PULL_UP			BIT(2)
+#define QPNP_PON_S2_CNTL_EN			BIT(7)
+#define QPNP_PON_S2_RESET_ENABLE		BIT(7)
+#define QPNP_PON_DELAY_BIT_SHIFT		6
 
-#define QPNP_PON_DBC_DELAY_MASK		(0x7)
-#define QPNP_PON_KPDPWR_N_SET		BIT(0)
-#define QPNP_PON_RESIN_N_SET		BIT(1)
-#define QPNP_PON_CBLPWR_N_SET		BIT(2)
-#define QPNP_PON_RESIN_BARK_N_SET	BIT(4)
+#define QPNP_PON_S1_TIMER_MASK			(0xF)
+#define QPNP_PON_S2_TIMER_MASK			(0x7)
+#define QPNP_PON_S2_CNTL_TYPE_MASK		(0xF)
 
-#define QPNP_PON_RESET_EN		BIT(7)
-#define QPNP_PON_WARM_RESET		BIT(0)
-#define QPNP_PON_SHUTDOWN		BIT(2)
+#define QPNP_PON_DBC_DELAY_MASK			(0x7)
+#define QPNP_PON_KPDPWR_N_SET			BIT(0)
+#define QPNP_PON_RESIN_N_SET			BIT(1)
+#define QPNP_PON_CBLPWR_N_SET			BIT(2)
+#define QPNP_PON_RESIN_BARK_N_SET		BIT(4)
+
+#define QPNP_PON_RESET_EN			BIT(7)
+#define QPNP_PON_WARM_RESET			BIT(0)
+#define QPNP_PON_SHUTDOWN			BIT(2)
 
 /* Ranges */
-#define QPNP_PON_S1_TIMER_MAX		10256
-#define QPNP_PON_S2_TIMER_MAX		2000
-#define QPNP_PON_RESET_TYPE_MAX		0xF
-#define PON_S1_COUNT_MAX		0xF
+#define QPNP_PON_S1_TIMER_MAX			10256
+#define QPNP_PON_S2_TIMER_MAX			2000
+#define QPNP_PON_RESET_TYPE_MAX			0xF
+#define PON_S1_COUNT_MAX			0xF
 
-#define QPNP_KEY_STATUS_DELAY		msecs_to_jiffies(250)
+#define QPNP_KEY_STATUS_DELAY			msecs_to_jiffies(250)
 
 enum pon_type {
 	PON_KPDPWR,
@@ -175,6 +179,50 @@
 }
 EXPORT_SYMBOL(qpnp_pon_system_pwr_off);
 
+/**
+ * qpnp_pon_is_warm_reset - Checks if the PMIC went through a warm reset.
+ *
+ * Returns > 0 for warm resets, 0 for not warm reset, < 0 for errors
+ *
+ * Note that this function will only return the warm vs not-warm reset status
+ * of the PMIC that is configured as the system-reset device.
+ */
+int qpnp_pon_is_warm_reset(void)
+{
+	struct qpnp_pon *pon = sys_reset_dev;
+	int rc;
+	u8 reg;
+
+	if (!pon)
+		return -EPROBE_DEFER;
+
+	rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
+			QPNP_PON_WARM_RESET_REASON1(pon->base), &reg, 1);
+	if (rc) {
+		dev_err(&pon->spmi->dev,
+			"Unable to read addr=%x, rc(%d)\n",
+			QPNP_PON_WARM_RESET_REASON1(pon->base), rc);
+		return rc;
+	}
+
+	if (reg)
+		return 1;
+
+	rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
+			QPNP_PON_WARM_RESET_REASON2(pon->base), &reg, 1);
+	if (rc) {
+		dev_err(&pon->spmi->dev,
+			"Unable to read addr=%x, rc(%d)\n",
+			QPNP_PON_WARM_RESET_REASON2(pon->base), rc);
+		return rc;
+	}
+	if (reg & QPNP_PON_WARM_RESET_TFT)
+		return 1;
+
+	return 0;
+}
+EXPORT_SYMBOL(qpnp_pon_is_warm_reset);
+
 static struct qpnp_pon_config *
 qpnp_get_cfg(struct qpnp_pon *pon, u32 pon_type)
 {
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index c09373a..9b3973b 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -177,6 +177,9 @@
 	int			vbatt_cutoff_count;
 	int			low_voltage_detect;
 	int			vbatt_cutoff_retries;
+	bool			first_report_after_suspend;
+	bool			soc_updated_on_resume;
+	int			last_soc_at_suspend;
 };
 
 /*
@@ -2387,10 +2390,11 @@
 			rbatt, fcc_uah, unusable_charge_uah, cc_uah);
 
 	pr_debug("calculated SOC = %d\n", new_calculated_soc);
-	if (new_calculated_soc != calculated_soc)
+	if (new_calculated_soc != calculated_soc) {
+		calculated_soc = new_calculated_soc;
 		update_power_supply(chip);
+	}
 
-	calculated_soc = new_calculated_soc;
 	firsttime = 0;
 	get_current_time(&chip->last_recalc_time);
 
@@ -2495,15 +2499,31 @@
 
 	/* last_soc < soc  ... scale and catch up */
 	if (last_soc != -EINVAL && last_soc < soc && soc != 100)
-			soc = scale_soc_while_chg(chip, delta_time_us,
-							soc, last_soc);
+		soc = scale_soc_while_chg(chip, delta_time_us, soc, last_soc);
 
-	/* restrict soc to 1% change */
 	if (last_soc != -EINVAL) {
-		if (soc < last_soc && soc != 0)
+		if (chip->first_report_after_suspend) {
+			chip->first_report_after_suspend = false;
+			if (chip->soc_updated_on_resume) {
+				/*  coming here after a long suspend */
+				chip->soc_updated_on_resume = false;
+				if (last_soc < soc)
+					/* if soc has falsely increased during
+					 * suspend, set the soc_at_suspend
+					 */
+					soc = chip->last_soc_at_suspend;
+			} else {
+				/*
+				 * suspended for a short time
+				 * report the last_soc before suspend
+				 */
+				soc = chip->last_soc_at_suspend;
+			}
+		} else if (soc < last_soc && soc != 0) {
 			soc = last_soc - 1;
-		if (soc > last_soc && soc != 100)
+		} else if (soc > last_soc && soc != 100) {
 			soc = last_soc + 1;
+		}
 	}
 
 	last_soc = bound_soc(soc);
@@ -3560,12 +3580,11 @@
 
 static int pm8921_bms_suspend(struct device *dev)
 {
-	/*
-	 * set the last reported soc to invalid, so that
-	 * next time we resume we don't want to restrict
-	 * the decrease of soc by only 1%
-	 */
-	last_soc = -EINVAL;
+	struct pm8921_bms_chip *chip = dev_get_drvdata(dev);
+
+	cancel_delayed_work_sync(&chip->calculate_soc_delayed_work);
+
+	chip->last_soc_at_suspend = last_soc;
 
 	return 0;
 }
@@ -3575,22 +3594,30 @@
 	int rc;
 	unsigned long time_since_last_recalc;
 	unsigned long tm_now_sec;
+	struct pm8921_bms_chip *chip = dev_get_drvdata(dev);
 
 	rc = get_current_time(&tm_now_sec);
 	if (rc) {
 		pr_err("Could not read current time: %d\n", rc);
 		return 0;
 	}
-	if (tm_now_sec > the_chip->last_recalc_time) {
+
+	if (tm_now_sec > chip->last_recalc_time) {
 		time_since_last_recalc = tm_now_sec -
-				the_chip->last_recalc_time;
+				chip->last_recalc_time;
 		pr_debug("Time since last recalc: %lu\n",
 				time_since_last_recalc);
-		if (time_since_last_recalc >= the_chip->soc_calc_period) {
-			the_chip->last_recalc_time = tm_now_sec;
-			recalculate_soc(the_chip);
+		if ((time_since_last_recalc * 1000) >=
+					chip->soc_calc_period) {
+			chip->last_recalc_time = tm_now_sec;
+			recalculate_soc(chip);
+			chip->soc_updated_on_resume = true;
 		}
 	}
+	chip->first_report_after_suspend = true;
+	update_power_supply(chip);
+	schedule_delayed_work(&chip->calculate_soc_delayed_work,
+				msecs_to_jiffies(chip->soc_calc_period));
 
 	return 0;
 }
diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c
index 63fb0a5..5cdb666 100644
--- a/drivers/power/power_supply_sysfs.c
+++ b/drivers/power/power_supply_sysfs.c
@@ -176,6 +176,7 @@
 	POWER_SUPPLY_ATTR(type),
 	POWER_SUPPLY_ATTR(scope),
 	POWER_SUPPLY_ATTR(system_temp_level),
+	POWER_SUPPLY_ATTR(resistance),
 	/* Properties of type `const char *' */
 	POWER_SUPPLY_ATTR(model_name),
 	POWER_SUPPLY_ATTR(manufacturer),
diff --git a/drivers/power/qpnp-bms.c b/drivers/power/qpnp-bms.c
index eec6d39..4f9254f 100644
--- a/drivers/power/qpnp-bms.c
+++ b/drivers/power/qpnp-bms.c
@@ -24,6 +24,7 @@
 #include <linux/rtc.h>
 #include <linux/delay.h>
 #include <linux/qpnp/qpnp-adc.h>
+#include <linux/qpnp/power-on.h>
 #include <linux/mfd/pm8xxx/batterydata-lib.h>
 
 /* BMS Register Offsets */
@@ -135,13 +136,17 @@
 	struct sf_lut			*rbatt_sf_lut;
 	int				default_rbatt_mohm;
 	int				rbatt_capacitive_mohm;
+	int				rbatt_mohm;
 
 	struct delayed_work		calculate_soc_delayed_work;
 	struct work_struct		recalc_work;
+	struct work_struct		battery_insertion_work;
 
 	struct mutex			bms_output_lock;
 	struct mutex			last_ocv_uv_mutex;
+	struct mutex			vbat_monitor_mutex;
 	struct mutex			soc_invalidation_mutex;
+	struct mutex			last_soc_mutex;
 
 	bool				use_external_rsense;
 	bool				use_ocv_thresholds;
@@ -152,19 +157,21 @@
 	int				shutdown_iavg_ma;
 
 	struct wake_lock		low_voltage_wake_lock;
-	bool				low_voltage_wake_lock_held;
 	int				low_voltage_threshold;
 	int				low_soc_calc_threshold;
 	int				low_soc_calculate_soc_ms;
 	int				calculate_soc_ms;
 	struct wake_lock		soc_wake_lock;
+	struct wake_lock		cv_wake_lock;
 
 	uint16_t			ocv_reading_at_100;
 	uint16_t			prev_last_good_ocv_raw;
 	int				last_ocv_uv;
 	int				last_ocv_temp;
 	int				last_cc_uah;
+	unsigned long			last_soc_change_sec;
 	unsigned long			tm_sec;
+	unsigned long			report_tm_sec;
 	bool				first_time_calc_soc;
 	bool				first_time_calc_uuc;
 	int				pon_ocv_uv;
@@ -176,15 +183,15 @@
 	int				last_soc;
 	int				last_soc_est;
 	int				last_soc_unbound;
-
-	int				charge_time_us;
-	int				catch_up_time_us;
+	bool				was_charging_at_sleep;
+	int				charge_start_tm_sec;
+	int				catch_up_time_sec;
 	struct single_row_lut		*adjusted_fcc_temp_lut;
 
+	struct qpnp_adc_tm_btm_param	vbat_monitor_params;
 	unsigned int			vadc_v0625;
 	unsigned int			vadc_v1250;
 
-	int				ibat_max_ua;
 	int				prev_uuc_iavg_ma;
 	int				prev_pc_unusable;
 	int				ibat_at_cv_ua;
@@ -193,6 +200,7 @@
 	int				calculated_soc;
 	int				prev_voltage_based_soc;
 	bool				use_voltage_soc;
+	bool				in_cv_range;
 
 	int				prev_batt_terminal_uv;
 	int				high_ocv_correction_limit_uv;
@@ -218,7 +226,7 @@
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_CAPACITY,
 	POWER_SUPPLY_PROP_CURRENT_NOW,
-	POWER_SUPPLY_PROP_CURRENT_MAX,
+	POWER_SUPPLY_PROP_RESISTANCE,
 	POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
 };
 
@@ -582,6 +590,24 @@
 	return false;
 }
 
+static bool is_battery_present(struct qpnp_bms_chip *chip)
+{
+	union power_supply_propval ret = {0,};
+
+	if (chip->batt_psy == NULL)
+		chip->batt_psy = power_supply_get_by_name("battery");
+	if (chip->batt_psy) {
+		/* if battery has been registered, use the status property */
+		chip->batt_psy->get_property(chip->batt_psy,
+					POWER_SUPPLY_PROP_PRESENT, &ret);
+		return ret.intval;
+	}
+
+	/* Default to false if the battery power supply is not registered. */
+	pr_debug("battery power supply is not registered\n");
+	return false;
+}
+
 static bool is_battery_full(struct qpnp_bms_chip *chip)
 {
 	union power_supply_propval ret = {0,};
@@ -661,7 +687,10 @@
 static void reset_for_new_battery(struct qpnp_bms_chip *chip, int batt_temp)
 {
 	chip->last_ocv_uv = estimate_ocv(chip);
+	mutex_lock(&chip->last_soc_mutex);
 	chip->last_soc = -EINVAL;
+	chip->last_soc_invalid = true;
+	mutex_unlock(&chip->last_soc_mutex);
 	chip->soc_at_cv = -EINVAL;
 	chip->shutdown_soc_invalid = true;
 	chip->shutdown_soc = 0;
@@ -670,15 +699,16 @@
 	reset_cc(chip);
 	chip->last_cc_uah = INT_MIN;
 	chip->last_ocv_temp = batt_temp;
-	chip->last_soc_invalid = true;
 	chip->prev_batt_terminal_uv = 0;
 }
 
 #define OCV_RAW_UNINITIALIZED	0xFFFF
+#define MIN_OCV_UV		2000000
 static int read_soc_params_raw(struct qpnp_bms_chip *chip,
 				struct raw_soc_params *raw,
 				int batt_temp)
 {
+	bool warm_reset = false;
 	int rc;
 
 	mutex_lock(&chip->bms_output_lock);
@@ -711,7 +741,18 @@
 
 	if (chip->prev_last_good_ocv_raw == OCV_RAW_UNINITIALIZED) {
 		convert_and_store_ocv(chip, raw, batt_temp);
-		pr_debug("PON_OCV_UV = %d\n", chip->last_ocv_uv);
+		pr_debug("PON_OCV_UV = %d, cc = %llx\n",
+				chip->last_ocv_uv, raw->cc);
+		warm_reset = qpnp_pon_is_warm_reset();
+		if (raw->last_good_ocv_uv < MIN_OCV_UV
+				|| warm_reset > 0) {
+			pr_debug("OCV is stale or bad, estimating new OCV.\n");
+			chip->last_ocv_uv = estimate_ocv(chip);
+			raw->last_good_ocv_uv = chip->last_ocv_uv;
+			reset_cc(chip);
+			pr_debug("New PON_OCV_UV = %d, cc = %llx\n",
+					chip->last_ocv_uv, raw->cc);
+		}
 	} else if (chip->new_battery) {
 		/* if a new battery was inserted, estimate the ocv */
 		reset_for_new_battery(chip, batt_temp);
@@ -1123,21 +1164,22 @@
 	return rc;
 }
 
-static int calculate_delta_time(struct qpnp_bms_chip *chip, int *delta_time_s)
+static int calculate_delta_time(unsigned long *time_stamp, int *delta_time_s)
 {
 	unsigned long now_tm_sec = 0;
 
 	/* default to delta time = 0 if anything fails */
 	*delta_time_s = 0;
 
-	get_current_time(&now_tm_sec);
+	if (get_current_time(&now_tm_sec)) {
+		pr_err("RTC read failed\n");
+		return 0;
+	}
 
-	*delta_time_s = (now_tm_sec - chip->tm_sec);
-	pr_debug("tm_sec = %ld, now_tm_sec = %ld delta_s = %d\n",
-		chip->tm_sec, now_tm_sec, *delta_time_s);
+	*delta_time_s = (now_tm_sec - *time_stamp);
 
 	/* remember this time */
-	chip->tm_sec = now_tm_sec;
+	*time_stamp = now_tm_sec;
 	return 0;
 }
 
@@ -1148,7 +1190,9 @@
 {
 	int soc_rbatt;
 
-	calculate_delta_time(chip, &params->delta_time_s);
+	calculate_delta_time(&chip->tm_sec, &params->delta_time_s);
+	pr_debug("tm_sec = %ld, delta_s = %d\n",
+		chip->tm_sec, params->delta_time_s);
 	params->fcc_uah = calculate_fcc(chip, batt_temp);
 	pr_debug("FCC = %uuAh batt_temp = %d\n", params->fcc_uah, batt_temp);
 
@@ -1169,6 +1213,12 @@
 	params->rbatt_mohm = get_rbatt(chip, soc_rbatt, batt_temp);
 	pr_debug("rbatt_mohm = %d\n", params->rbatt_mohm);
 
+	if (params->rbatt_mohm != chip->rbatt_mohm
+			&& chip->bms_psy.name != NULL) {
+		chip->rbatt_mohm = params->rbatt_mohm;
+		power_supply_changed(&chip->bms_psy);
+	}
+
 	calculate_iavg(chip, params->cc_uah, &params->iavg_ua,
 						params->delta_time_s);
 
@@ -1234,8 +1284,10 @@
 	ocv_est_uv = vbat_uv + (ibat_ua * chip->r_conn_mohm) / 1000;
 	pr_debug("forcing ocv to be %d due to bms reset mode\n", ocv_est_uv);
 	chip->last_ocv_uv = ocv_est_uv;
+	mutex_lock(&chip->last_soc_mutex);
 	chip->last_soc = -EINVAL;
 	chip->last_soc_invalid = true;
+	mutex_unlock(&chip->last_soc_mutex);
 	reset_cc(chip);
 	chip->last_cc_uah = INT_MIN;
 	stop_ocv_updates(chip);
@@ -1277,25 +1329,26 @@
 
 module_param_cb(bms_reset, &bms_reset_ops, &bms_reset, 0644);
 
+#define VBATT_ERROR_MARGIN	20000
 static int charging_adjustments(struct qpnp_bms_chip *chip,
 				struct soc_params *params, int soc,
 				int vbat_uv, int ibat_ua, int batt_temp)
 {
-	int chg_soc;
-	int batt_terminal_uv = vbat_uv + (ibat_ua * chip->r_conn_mohm) / 1000;
+	int chg_soc, batt_terminal_uv;
+
+	batt_terminal_uv = vbat_uv + VBATT_ERROR_MARGIN
+				+ (ibat_ua * chip->r_conn_mohm) / 1000;
 
 	if (chip->soc_at_cv == -EINVAL) {
-		/* In constant current charging return the calc soc */
-		if (batt_terminal_uv <= chip->max_voltage_uv)
-			pr_debug("CC CHG SOC %d\n", soc);
-
-		/* Note the CC to CV point */
 		if (batt_terminal_uv >= chip->max_voltage_uv) {
 			chip->soc_at_cv = soc;
 			chip->prev_chg_soc = soc;
 			chip->ibat_at_cv_ua = ibat_ua;
 			pr_debug("CC_TO_CV ibat_ua = %d CHG SOC %d\n",
 					ibat_ua, soc);
+		} else {
+			/* In constant current charging return the calc soc */
+			pr_debug("CC CHG SOC %d\n", soc);
 		}
 
 		chip->prev_batt_terminal_uv = batt_terminal_uv;
@@ -1349,18 +1402,40 @@
 	 * a wakelock untill soc = 0%
 	 */
 	if (vbat_uv <= chip->low_voltage_threshold
-			&& !chip->low_voltage_wake_lock_held) {
+			&& !wake_lock_active(&chip->low_voltage_wake_lock)) {
 		pr_debug("voltage = %d low holding wakelock\n", vbat_uv);
 		wake_lock(&chip->low_voltage_wake_lock);
-		chip->low_voltage_wake_lock_held = 1;
 	} else if (vbat_uv > chip->low_voltage_threshold
-			&& chip->low_voltage_wake_lock_held) {
+			&& wake_lock_active(&chip->low_voltage_wake_lock)) {
 		pr_debug("voltage = %d releasing wakelock\n", vbat_uv);
-		chip->low_voltage_wake_lock_held = 0;
 		wake_unlock(&chip->low_voltage_wake_lock);
 	}
 }
 
+#define VBATT_ERROR_MARGIN	20000
+static void cv_voltage_check(struct qpnp_bms_chip *chip, int vbat_uv)
+{
+	/*
+	 * if battery is very low (v_cutoff voltage + 20mv) hold
+	 * a wakelock untill soc = 0%
+	 */
+	if (wake_lock_active(&chip->cv_wake_lock)) {
+		if (chip->soc_at_cv != -EINVAL) {
+			pr_debug("hit CV, releasing cv wakelock\n");
+			wake_unlock(&chip->cv_wake_lock);
+		} else if (!is_battery_charging(chip)) {
+			pr_debug("charging stopped, releasing cv wakelock\n");
+			wake_unlock(&chip->cv_wake_lock);
+		}
+	} else if (vbat_uv > chip->max_voltage_uv - VBATT_ERROR_MARGIN
+			&& chip->soc_at_cv == -EINVAL
+			&& is_battery_charging(chip)
+			&& !wake_lock_active(&chip->cv_wake_lock)) {
+		pr_debug("voltage = %d holding cv wakelock\n", vbat_uv);
+		wake_lock(&chip->cv_wake_lock);
+	}
+}
+
 #define NO_ADJUST_HIGH_SOC_THRESHOLD	90
 static int adjust_soc(struct qpnp_bms_chip *chip, struct soc_params *params,
 							int soc, int batt_temp)
@@ -1384,14 +1459,12 @@
 	}
 
 	very_low_voltage_check(chip, vbat_uv);
+	cv_voltage_check(chip, vbat_uv);
 
 	delta_ocv_uv_limit = DIV_ROUND_CLOSEST(ibat_ua, 1000);
 
 	ocv_est_uv = vbat_uv + (ibat_ua * params->rbatt_mohm)/1000;
 
-	chip->ibat_max_ua = (ocv_est_uv - chip->v_cutoff_uv) * 1000
-					/ (params->rbatt_mohm);
-
 	pc_est = calculate_pc(chip, ocv_est_uv, batt_temp);
 	soc_est = div_s64((s64)params->fcc_uah * pc_est - params->uuc_uah*100,
 				(s64)params->fcc_uah - params->uuc_uah);
@@ -1529,6 +1602,7 @@
 	}
 }
 
+#define SLEEP_RECALC_INTERVAL	3
 static int calculate_state_of_charge(struct qpnp_bms_chip *chip,
 					struct raw_soc_params *raw,
 					int batt_temp)
@@ -1537,7 +1611,7 @@
 	int shutdown_soc, new_calculated_soc, remaining_usable_charge_uah;
 	struct soc_params params;
 
-	if (!chip->battery_present) {
+	if (!is_battery_present(chip)) {
 		pr_debug("battery gone, reporting 100\n");
 		new_calculated_soc = 100;
 		goto done_calculating;
@@ -1640,13 +1714,30 @@
 	}
 
 	chip->calculated_soc = new_calculated_soc;
+	pr_debug("CC based calculated SOC = %d\n", chip->calculated_soc);
+	mutex_lock(&chip->last_soc_mutex);
 	if (chip->last_soc_invalid) {
 		chip->last_soc_invalid = false;
 		chip->last_soc = -EINVAL;
 	}
-	pr_debug("CC based calculated SOC = %d\n", chip->calculated_soc);
-	chip->first_time_calc_soc = 0;
+	/*
+	 * Check if more than a long time has passed since the last
+	 * calculation (more than n times compared to the soc recalculation
+	 * rate, where n is defined by SLEEP_RECALC_INTERVAL). If this is true,
+	 * then the system must have gone through a long sleep, and SoC can be
+	 * allowed to become unbounded by the last reported SoC
+	 */
+	if (params.delta_time_s * 1000 >
+			chip->calculate_soc_ms * SLEEP_RECALC_INTERVAL
+			&& !chip->first_time_calc_soc) {
+		chip->last_soc_unbound = true;
+		chip->last_soc_change_sec = chip->last_recalc_time;
+		pr_debug("last_soc unbound because elapsed time = %d\n",
+				params.delta_time_s);
+	}
+	mutex_unlock(&chip->last_soc_mutex);
 	get_current_time(&chip->last_recalc_time);
+	chip->first_time_calc_soc = 0;
 	return chip->calculated_soc;
 }
 
@@ -1684,7 +1775,11 @@
 	struct qpnp_vadc_result result;
 	struct raw_soc_params raw;
 
-	wake_lock(&chip->soc_wake_lock);
+	if (!wake_lock_active(&chip->soc_wake_lock))
+		wake_lock(&chip->soc_wake_lock);
+	mutex_lock(&chip->vbat_monitor_mutex);
+	qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params);
+	mutex_unlock(&chip->vbat_monitor_mutex);
 	if (chip->use_voltage_soc) {
 		soc = calculate_soc_from_voltage(chip);
 	} else {
@@ -1726,7 +1821,7 @@
 	int soc = recalculate_soc(chip);
 
 	if (soc < chip->low_soc_calc_threshold
-			|| chip->low_voltage_wake_lock_held)
+			|| wake_lock_active(&chip->low_voltage_wake_lock))
 		schedule_delayed_work(&chip->calculate_soc_delayed_work,
 			round_jiffies_relative(msecs_to_jiffies
 			(chip->low_soc_calculate_soc_ms)));
@@ -1762,32 +1857,20 @@
 #define SOC_CATCHUP_SEC_MAX		600
 #define SOC_CATCHUP_SEC_PER_PERCENT	60
 #define MAX_CATCHUP_SOC	(SOC_CATCHUP_SEC_MAX/SOC_CATCHUP_SEC_PER_PERCENT)
-static int scale_soc_while_chg(struct qpnp_bms_chip *chip,
-				int delta_time_us, int new_soc, int prev_soc)
+static int scale_soc_while_chg(struct qpnp_bms_chip *chip, int chg_time_sec,
+				int catch_up_sec, int new_soc, int prev_soc)
 {
-	int chg_time_sec;
-	int catch_up_sec;
 	int scaled_soc;
 	int numerator;
 
 	/*
-	 * The device must be charging for reporting a higher soc, if
-	 * not ignore this soc and continue reporting the prev_soc.
-	 * Also don't report a high value immediately slowly scale the
+	 * Don't report a high value immediately slowly scale the
 	 * value from prev_soc to the new soc based on a charge time
 	 * weighted average
 	 */
-
-	/* if not charging, return last soc */
-	if (!is_battery_charging(chip))
-		return prev_soc;
-
-	chg_time_sec = DIV_ROUND_UP(chip->charge_time_us, USEC_PER_SEC);
-	catch_up_sec = DIV_ROUND_UP(chip->catch_up_time_us, USEC_PER_SEC);
+	pr_debug("cts = %d catch_up_sec = %d\n", chg_time_sec, catch_up_sec);
 	if (catch_up_sec == 0)
 		return new_soc;
-	pr_debug("cts= %d catch_up_sec = %d\n", chg_time_sec, catch_up_sec);
-
 	/*
 	 * if charging for more than catch_up time, simply return
 	 * new soc
@@ -1820,14 +1903,17 @@
 	return chip->prev_voltage_based_soc;
 }
 
+#define SOC_CHANGE_PER_SEC	20
 static int report_cc_based_soc(struct qpnp_bms_chip *chip)
 {
-	int soc;
-	int delta_time_us;
+	int soc, soc_change;
+	int time_since_last_change_sec, charge_time_sec = 0;
+	unsigned long last_change_sec;
 	struct timespec now;
 	struct qpnp_vadc_result result;
 	int batt_temp;
 	int rc;
+	bool charging, charging_since_last_report;
 
 	soc = chip->calculated_soc;
 
@@ -1842,68 +1928,84 @@
 						result.measurement);
 	batt_temp = (int)result.physical;
 
-	do_posix_clock_monotonic_gettime(&now);
-	if (chip->t_soc_queried.tv_sec != 0) {
-		delta_time_us
-		= (now.tv_sec - chip->t_soc_queried.tv_sec) * USEC_PER_SEC
-			+ (now.tv_nsec - chip->t_soc_queried.tv_nsec) / 1000;
-	} else {
-		/* calculation for the first time */
-		delta_time_us = 0;
-	}
+	mutex_lock(&chip->last_soc_mutex);
+	last_change_sec = chip->last_soc_change_sec;
+	calculate_delta_time(&last_change_sec, &time_since_last_change_sec);
 
+	charging = is_battery_charging(chip);
+	charging_since_last_report = charging || (chip->last_soc_unbound
+			&& chip->was_charging_at_sleep);
 	/*
 	 * account for charge time - limit it to SOC_CATCHUP_SEC to
 	 * avoid overflows when charging continues for extended periods
 	 */
-	if (is_battery_charging(chip)) {
-		if (chip->charge_time_us == 0) {
+	if (charging) {
+		if (chip->charge_start_tm_sec == 0) {
 			/*
 			 * calculating soc for the first time
 			 * after start of chg. Initialize catchup time
 			 */
 			if (abs(soc - chip->last_soc) < MAX_CATCHUP_SOC)
-				chip->catch_up_time_us =
+				chip->catch_up_time_sec =
 				(soc - chip->last_soc)
-					* SOC_CATCHUP_SEC_PER_PERCENT
-					* USEC_PER_SEC;
+					* SOC_CATCHUP_SEC_PER_PERCENT;
 			else
-				chip->catch_up_time_us =
-				SOC_CATCHUP_SEC_MAX * USEC_PER_SEC;
+				chip->catch_up_time_sec = SOC_CATCHUP_SEC_MAX;
 
-			if (chip->catch_up_time_us < 0)
-				chip->catch_up_time_us = 0;
+			if (chip->catch_up_time_sec < 0)
+				chip->catch_up_time_sec = 0;
+			chip->charge_start_tm_sec = last_change_sec;
 		}
 
-		/* add charge time */
-		if (chip->charge_time_us < SOC_CATCHUP_SEC_MAX * USEC_PER_SEC)
-			chip->charge_time_us += delta_time_us;
+		charge_time_sec = min(SOC_CATCHUP_SEC_MAX, (int)last_change_sec
+				- chip->charge_start_tm_sec);
 
 		/* end catchup if calculated soc and last soc are same */
 		if (chip->last_soc == soc)
-			chip->catch_up_time_us = 0;
+			chip->catch_up_time_sec = 0;
 	}
 
-	/* last_soc < soc  ... scale and catch up */
-	if (chip->last_soc != -EINVAL && chip->last_soc < soc && soc != 100)
-		soc = scale_soc_while_chg(chip, delta_time_us,
-						soc, chip->last_soc);
+	if (chip->last_soc != -EINVAL) {
+		/* last_soc < soc  ... if we have not been charging at all
+		 * since the last time this was called, report previous SoC.
+		 * Otherwise, scale and catch up.
+		 */
+		if (chip->last_soc < soc && !charging_since_last_report)
+			soc = chip->last_soc;
+		else if (chip->last_soc < soc && soc != 100)
+			soc = scale_soc_while_chg(chip, charge_time_sec,
+					chip->catch_up_time_sec,
+					soc, chip->last_soc);
 
-	if (chip->last_soc_unbound)
-		chip->last_soc_unbound = false;
-	else if (chip->last_soc != -EINVAL) {
+		soc_change = min((int)abs(chip->last_soc - soc),
+			time_since_last_change_sec / SOC_CHANGE_PER_SEC);
+		if (chip->last_soc_unbound) {
+			chip->last_soc_unbound = false;
+		} else {
+			/*
+			 * if soc have not been unbound by resume,
+			 * only change reported SoC by 1.
+			 */
+			soc_change = min(1, soc_change);
+		}
+
 		if (soc < chip->last_soc && soc != 0)
-			soc = chip->last_soc - 1;
+			soc = chip->last_soc - soc_change;
 		if (soc > chip->last_soc && soc != 100)
-			soc = chip->last_soc + 1;
+			soc = chip->last_soc + soc_change;
 	}
 
-	pr_debug("last_soc = %d, calculated_soc = %d, soc = %d\n",
-			chip->last_soc, chip->calculated_soc, soc);
+	if (chip->last_soc != soc)
+		chip->last_soc_change_sec = last_change_sec;
+
+	pr_debug("last_soc = %d, calculated_soc = %d, soc = %d, time since last change = %d\n",
+			chip->last_soc, chip->calculated_soc,
+			soc, time_since_last_change_sec);
 	chip->last_soc = bound_soc(soc);
 	backup_soc_and_iavg(chip, batt_temp, chip->last_soc);
 	pr_debug("Reported SOC = %d\n", chip->last_soc);
 	chip->t_soc_queried = now;
+	mutex_unlock(&chip->last_soc_mutex);
 
 	return soc;
 }
@@ -1919,16 +2021,236 @@
 		return report_cc_based_soc(chip);
 }
 
+static void configure_vbat_monitor_low(struct qpnp_bms_chip *chip)
+{
+	mutex_lock(&chip->vbat_monitor_mutex);
+	if (chip->vbat_monitor_params.state_request
+			== ADC_TM_HIGH_LOW_THR_ENABLE) {
+		/*
+		 * Battery is now around or below v_cutoff
+		 */
+		pr_debug("battery entered cutoff range\n");
+		if (!wake_lock_active(&chip->low_voltage_wake_lock)) {
+			pr_debug("voltage low, holding wakelock\n");
+			wake_lock(&chip->low_voltage_wake_lock);
+			cancel_delayed_work_sync(
+					&chip->calculate_soc_delayed_work);
+			schedule_delayed_work(
+					&chip->calculate_soc_delayed_work, 0);
+		}
+		chip->vbat_monitor_params.state_request =
+					ADC_TM_HIGH_THR_ENABLE;
+		chip->vbat_monitor_params.high_thr =
+			(chip->low_voltage_threshold + VBATT_ERROR_MARGIN);
+		pr_debug("set low thr to %d and high to %d\n",
+				chip->vbat_monitor_params.low_thr,
+				chip->vbat_monitor_params.high_thr);
+		chip->vbat_monitor_params.low_thr = 0;
+	} else if (chip->vbat_monitor_params.state_request
+			== ADC_TM_LOW_THR_ENABLE) {
+		/*
+		 * Battery is in normal operation range.
+		 */
+		pr_debug("battery entered normal range\n");
+		if (wake_lock_active(&chip->cv_wake_lock)) {
+			wake_unlock(&chip->cv_wake_lock);
+			pr_debug("releasing cv wake lock\n");
+		}
+		chip->in_cv_range = false;
+		chip->vbat_monitor_params.state_request =
+					ADC_TM_HIGH_LOW_THR_ENABLE;
+		chip->vbat_monitor_params.high_thr = chip->max_voltage_uv
+				- VBATT_ERROR_MARGIN;
+		chip->vbat_monitor_params.low_thr =
+				chip->low_voltage_threshold;
+		pr_debug("set low thr to %d and high to %d\n",
+				chip->vbat_monitor_params.low_thr,
+				chip->vbat_monitor_params.high_thr);
+	}
+	qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params);
+	mutex_unlock(&chip->vbat_monitor_mutex);
+}
+
+#define CV_LOW_THRESHOLD_HYST_UV 100000
+static void configure_vbat_monitor_high(struct qpnp_bms_chip *chip)
+{
+	mutex_lock(&chip->vbat_monitor_mutex);
+	if (chip->vbat_monitor_params.state_request
+			== ADC_TM_HIGH_LOW_THR_ENABLE) {
+		/*
+		 * Battery is around vddmax
+		 */
+		pr_debug("battery entered vddmax range\n");
+		chip->in_cv_range = true;
+		if (!wake_lock_active(&chip->cv_wake_lock)) {
+			wake_lock(&chip->cv_wake_lock);
+			pr_debug("holding cv wake lock\n");
+		}
+		schedule_work(&chip->recalc_work);
+		chip->vbat_monitor_params.state_request =
+					ADC_TM_LOW_THR_ENABLE;
+		chip->vbat_monitor_params.low_thr =
+			(chip->max_voltage_uv - CV_LOW_THRESHOLD_HYST_UV);
+		chip->vbat_monitor_params.high_thr = chip->max_voltage_uv * 2;
+		pr_debug("set low thr to %d and high to %d\n",
+				chip->vbat_monitor_params.low_thr,
+				chip->vbat_monitor_params.high_thr);
+	} else if (chip->vbat_monitor_params.state_request
+			== ADC_TM_HIGH_THR_ENABLE) {
+		/*
+		 * Battery is in normal operation range.
+		 */
+		pr_debug("battery entered normal range\n");
+		if (wake_lock_active(&chip->low_voltage_wake_lock)) {
+			pr_debug("voltage high, releasing wakelock\n");
+			wake_unlock(&chip->low_voltage_wake_lock);
+		}
+		chip->vbat_monitor_params.state_request =
+					ADC_TM_HIGH_LOW_THR_ENABLE;
+		chip->vbat_monitor_params.high_thr =
+			chip->max_voltage_uv - VBATT_ERROR_MARGIN;
+		chip->vbat_monitor_params.low_thr =
+				chip->low_voltage_threshold;
+		pr_debug("set low thr to %d and high to %d\n",
+				chip->vbat_monitor_params.low_thr,
+				chip->vbat_monitor_params.high_thr);
+	}
+	qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params);
+	mutex_unlock(&chip->vbat_monitor_mutex);
+}
+
+static void btm_notify_vbat(enum qpnp_tm_state state, void *ctx)
+{
+	struct qpnp_bms_chip *chip = ctx;
+	int vbat_uv;
+	struct qpnp_vadc_result result;
+	int rc;
+
+	rc = qpnp_vadc_read(VBAT_SNS, &result);
+	pr_debug("vbat = %lld, raw = 0x%x\n", result.physical, result.adc_code);
+
+	get_battery_voltage(&vbat_uv);
+	pr_debug("vbat is at %d, state is at %d\n", vbat_uv, state);
+
+	if (state == ADC_TM_LOW_STATE) {
+		pr_debug("low voltage btm notification triggered\n");
+		if (vbat_uv - VBATT_ERROR_MARGIN
+				< chip->vbat_monitor_params.low_thr) {
+			configure_vbat_monitor_low(chip);
+		} else {
+			pr_debug("faulty btm trigger, discarding\n");
+			qpnp_adc_tm_channel_measure(
+					&chip->vbat_monitor_params);
+		}
+	} else if (state == ADC_TM_HIGH_STATE) {
+		pr_debug("high voltage btm notification triggered\n");
+		if (vbat_uv + VBATT_ERROR_MARGIN
+				> chip->vbat_monitor_params.high_thr) {
+			configure_vbat_monitor_high(chip);
+		} else {
+			pr_debug("faulty btm trigger, discarding\n");
+			qpnp_adc_tm_channel_measure(
+					&chip->vbat_monitor_params);
+		}
+	} else {
+		pr_debug("unknown voltage notification state: %d\n", state);
+	}
+	power_supply_changed(&chip->bms_psy);
+}
+
+static int reset_vbat_monitoring(struct qpnp_bms_chip *chip)
+{
+	int rc;
+
+	chip->vbat_monitor_params.state_request = ADC_TM_HIGH_LOW_THR_DISABLE;
+	rc = qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params);
+	if (rc) {
+		pr_err("tm measure failed: %d\n", rc);
+		return rc;
+	}
+	mutex_lock(&chip->vbat_monitor_mutex);
+	if (wake_lock_active(&chip->low_voltage_wake_lock)) {
+		pr_debug("battery removed, releasing wakelock\n");
+		wake_unlock(&chip->low_voltage_wake_lock);
+	}
+	if (chip->in_cv_range) {
+		pr_debug("battery removed, removing in_cv_range state\n");
+		chip->in_cv_range = false;
+	}
+	mutex_unlock(&chip->vbat_monitor_mutex);
+	return 0;
+}
+
+static int setup_vbat_monitoring(struct qpnp_bms_chip *chip)
+{
+	int rc;
+
+	rc = qpnp_adc_tm_is_ready();
+	if (rc) {
+		pr_info("adc tm is not ready yet: %d, defer probe\n", rc);
+		return -EPROBE_DEFER;
+	}
+
+	if (!is_battery_present(chip)) {
+		pr_debug("no battery inserted, do not setup vbat monitoring\n");
+		return 0;
+	}
+
+	chip->vbat_monitor_params.low_thr = chip->low_voltage_threshold;
+	chip->vbat_monitor_params.high_thr = chip->max_voltage_uv
+							- VBATT_ERROR_MARGIN;
+	chip->vbat_monitor_params.state_request = ADC_TM_HIGH_LOW_THR_ENABLE;
+	chip->vbat_monitor_params.channel = VBAT_SNS;
+	chip->vbat_monitor_params.btm_ctx = (void *)chip;
+	chip->vbat_monitor_params.timer_interval = ADC_MEAS1_INTERVAL_1S;
+	chip->vbat_monitor_params.threshold_notification = &btm_notify_vbat;
+	pr_debug("set low thr to %d and high to %d\n",
+			chip->vbat_monitor_params.low_thr,
+			chip->vbat_monitor_params.high_thr);
+	rc = qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params);
+	if (rc) {
+		pr_err("tm setup failed: %d\n", rc);
+		return rc;
+	}
+	pr_debug("setup complete\n");
+	return 0;
+}
+
+static void battery_insertion_work(struct work_struct *work)
+{
+	struct qpnp_bms_chip *chip = container_of(work,
+				struct qpnp_bms_chip,
+				battery_insertion_work);
+	bool present = is_battery_present(chip);
+
+	mutex_lock(&chip->vbat_monitor_mutex);
+	if (chip->battery_present != present) {
+		if (chip->battery_present != -EINVAL) {
+			if (present) {
+				setup_vbat_monitoring(chip);
+				chip->new_battery = true;
+			} else {
+				reset_vbat_monitoring(chip);
+			}
+		}
+		chip->battery_present = present;
+		/* a new battery was inserted or removed, so force a soc
+		 * recalculation to update the SoC */
+		schedule_work(&chip->recalc_work);
+	}
+	mutex_unlock(&chip->vbat_monitor_mutex);
+}
+
 /* Returns capacity as a SoC percentage between 0 and 100 */
 static int get_prop_bms_capacity(struct qpnp_bms_chip *chip)
 {
 	return report_state_of_charge(chip);
 }
 
-/* Returns estimated max current that the battery can supply in uA */
-static int get_prop_bms_current_max(struct qpnp_bms_chip *chip)
+/* Returns estimated battery resistance */
+static int get_prop_bms_batt_resistance(struct qpnp_bms_chip *chip)
 {
-	return chip->ibat_max_ua;
+	return chip->rbatt_mohm * 1000;
 }
 
 /* Returns instantaneous current in uA */
@@ -1952,19 +2274,12 @@
 
 static int get_prop_bms_present(struct qpnp_bms_chip *chip)
 {
-	return chip->battery_present;
+	return is_battery_present(chip);
 }
 
 static void set_prop_bms_present(struct qpnp_bms_chip *chip, int present)
 {
-	if (chip->battery_present != present) {
-		chip->battery_present = present;
-		if (present)
-			chip->new_battery = true;
-		/* a new battery was inserted or removed, so force a soc
-		 * recalculation to update the SoC */
-		schedule_work(&chip->recalc_work);
-	}
+	schedule_work(&chip->battery_insertion_work);
 }
 
 static void qpnp_bms_external_power_changed(struct power_supply *psy)
@@ -1985,8 +2300,8 @@
 	case POWER_SUPPLY_PROP_CURRENT_NOW:
 		val->intval = get_prop_bms_current_now(chip);
 		break;
-	case POWER_SUPPLY_PROP_CURRENT_MAX:
-		val->intval = get_prop_bms_current_max(chip);
+	case POWER_SUPPLY_PROP_RESISTANCE:
+		val->intval = get_prop_bms_batt_resistance(chip);
 		break;
 	case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
 		val->intval = get_prop_bms_charge_full_design(chip);
@@ -2255,6 +2570,7 @@
 	chip->calculated_soc = -EINVAL;
 	chip->last_soc = -EINVAL;
 	chip->last_soc_est = -EINVAL;
+	chip->battery_present = -EINVAL;
 	chip->last_cc_uah = INT_MIN;
 	chip->ocv_reading_at_100 = OCV_RAW_UNINITIALIZED;
 	chip->prev_last_good_ocv_raw = OCV_RAW_UNINITIALIZED;
@@ -2402,7 +2718,7 @@
 static int __devinit qpnp_bms_probe(struct spmi_device *spmi)
 {
 	struct qpnp_bms_chip *chip;
-	union power_supply_propval retval = {0,};
+	bool warm_reset;
 	int rc, vbatt;
 
 	chip = kzalloc(sizeof *chip, GFP_KERNEL);
@@ -2415,15 +2731,22 @@
 	rc = qpnp_vadc_is_ready();
 	if (rc) {
 		pr_info("vadc not ready: %d, deferring probe\n", rc);
+		rc = -EPROBE_DEFER;
 		goto error_read;
 	}
 
 	rc = qpnp_iadc_is_ready();
 	if (rc) {
 		pr_info("iadc not ready: %d, deferring probe\n", rc);
+		rc = -EPROBE_DEFER;
 		goto error_read;
 	}
 
+	warm_reset = qpnp_pon_is_warm_reset();
+	rc = warm_reset;
+	if (rc < 0)
+		goto error_read;
+
 	rc = register_spmi(chip, spmi);
 	if (rc) {
 		pr_err("error registering spmi resource %d\n", rc);
@@ -2478,30 +2801,30 @@
 
 	mutex_init(&chip->bms_output_lock);
 	mutex_init(&chip->last_ocv_uv_mutex);
+	mutex_init(&chip->vbat_monitor_mutex);
 	mutex_init(&chip->soc_invalidation_mutex);
+	mutex_init(&chip->last_soc_mutex);
 
 	wake_lock_init(&chip->soc_wake_lock, WAKE_LOCK_SUSPEND,
 			"qpnp_soc_lock");
 	wake_lock_init(&chip->low_voltage_wake_lock, WAKE_LOCK_SUSPEND,
 			"qpnp_low_voltage_lock");
+	wake_lock_init(&chip->cv_wake_lock, WAKE_LOCK_SUSPEND,
+			"qpnp_cv_lock");
 	INIT_DELAYED_WORK(&chip->calculate_soc_delayed_work,
 			calculate_soc_work);
 	INIT_WORK(&chip->recalc_work, recalculate_work);
+	INIT_WORK(&chip->battery_insertion_work, battery_insertion_work);
 
 	read_shutdown_soc_and_iavg(chip);
 
 	dev_set_drvdata(&spmi->dev, chip);
 	device_init_wakeup(&spmi->dev, 1);
 
-	if (!chip->batt_psy)
-		chip->batt_psy = power_supply_get_by_name("battery");
-	if (chip->batt_psy) {
-		chip->batt_psy->get_property(chip->batt_psy,
-					POWER_SUPPLY_PROP_PRESENT, &retval);
-		chip->battery_present = retval.intval;
-		pr_debug("present = %d\n", chip->battery_present);
-	} else {
-		chip->battery_present = 1;
+	rc = setup_vbat_monitoring(chip);
+	if (rc < 0) {
+		pr_err("failed to set up voltage notifications: %d\n", rc);
+		goto error_setup;
 	}
 
 	calculate_soc_work(&(chip->calculate_soc_delayed_work.work));
@@ -2533,16 +2856,18 @@
 		goto unregister_dc;
 	}
 
-	pr_info("probe success: soc =%d vbatt = %d ocv = %d r_sense_uohm = %u\n",
-				get_prop_bms_capacity(chip),
-				vbatt, chip->last_ocv_uv, chip->r_sense_uohm);
+	pr_info("probe success: soc =%d vbatt = %d ocv = %d r_sense_uohm = %u warm_reset = %d\n",
+			get_prop_bms_capacity(chip), vbatt, chip->last_ocv_uv,
+			chip->r_sense_uohm, warm_reset);
 	return 0;
 
 unregister_dc:
+	power_supply_unregister(&chip->bms_psy);
+error_setup:
+	dev_set_drvdata(&spmi->dev, NULL);
 	wake_lock_destroy(&chip->soc_wake_lock);
 	wake_lock_destroy(&chip->low_voltage_wake_lock);
-	power_supply_unregister(&chip->bms_psy);
-	dev_set_drvdata(&spmi->dev, NULL);
+	wake_lock_destroy(&chip->cv_wake_lock);
 error_resource:
 error_read:
 	kfree(chip);
@@ -2564,7 +2889,7 @@
 	struct qpnp_bms_chip *chip = dev_get_drvdata(dev);
 
 	cancel_delayed_work_sync(&chip->calculate_soc_delayed_work);
-	chip->last_soc_unbound = true;
+	chip->was_charging_at_sleep = is_battery_charging(chip);
 	return 0;
 }
 
@@ -2581,10 +2906,6 @@
 	if (rc) {
 		pr_err("Could not read current time: %d\n", rc);
 	} else if (tm_now_sec > chip->last_recalc_time) {
-		/*
-		 * unbind the last soc so that the next
-		 * recalculation is not limited to changing by 1%
-		 */
 		time_since_last_recalc = tm_now_sec - chip->last_recalc_time;
 		pr_debug("Time since last recalc: %lu\n",
 				time_since_last_recalc);
@@ -2596,6 +2917,10 @@
 		time_until_next_recalc = max(0, soc_calc_period
 				- (int)(time_since_last_recalc * 1000));
 
+		if (!wake_lock_active(&chip->soc_wake_lock)
+				&& time_until_next_recalc == 0)
+			wake_lock(&chip->soc_wake_lock);
+
 		schedule_delayed_work(&chip->calculate_soc_delayed_work,
 			round_jiffies_relative(msecs_to_jiffies
 			(time_until_next_recalc)));
diff --git a/drivers/power/qpnp-charger.c b/drivers/power/qpnp-charger.c
index 7a2d9a8..cd07b20 100644
--- a/drivers/power/qpnp-charger.c
+++ b/drivers/power/qpnp-charger.c
@@ -918,7 +918,6 @@
 	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
 	POWER_SUPPLY_PROP_VOLTAGE_NOW,
 	POWER_SUPPLY_PROP_CAPACITY,
-	POWER_SUPPLY_PROP_CURRENT_MAX,
 	POWER_SUPPLY_PROP_CURRENT_NOW,
 	POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
 	POWER_SUPPLY_PROP_TEMP,
@@ -1059,21 +1058,6 @@
 
 	return POWER_SUPPLY_STATUS_DISCHARGING;
 }
-static int
-get_prop_current_max(struct qpnp_chg_chip *chip)
-{
-	union power_supply_propval ret = {0,};
-
-	if (chip->bms_psy) {
-		chip->bms_psy->get_property(chip->bms_psy,
-			  POWER_SUPPLY_PROP_CURRENT_MAX, &ret);
-		return ret.intval;
-	} else {
-		pr_debug("No BMS supply registered return 0\n");
-	}
-
-	return 0;
-}
 
 static int
 get_prop_current_now(struct qpnp_chg_chip *chip)
@@ -1252,9 +1236,6 @@
 	case POWER_SUPPLY_PROP_CAPACITY:
 		val->intval = get_prop_capacity(chip);
 		break;
-	case POWER_SUPPLY_PROP_CURRENT_MAX:
-		val->intval = get_prop_current_max(chip);
-		break;
 	case POWER_SUPPLY_PROP_CURRENT_NOW:
 		val->intval = get_prop_current_now(chip);
 		break;
diff --git a/drivers/regulator/qpnp-regulator.c b/drivers/regulator/qpnp-regulator.c
index 2d10f89..c9d0500 100644
--- a/drivers/regulator/qpnp-regulator.c
+++ b/drivers/regulator/qpnp-regulator.c
@@ -514,8 +514,10 @@
 {
 	struct qpnp_regulator *vreg = rdev_get_drvdata(rdev);
 
-	if (vreg->ocp_irq)
+	if (vreg->ocp_irq) {
+		vreg->ocp_count = 0;
 		vreg->vs_enable_time = ktime_get();
+	}
 
 	return qpnp_regulator_common_enable(rdev);
 }
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 6e30ca2..1de9aaa 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -127,6 +127,7 @@
 	POWER_SUPPLY_PROP_TYPE, /* use power_supply.type instead */
 	POWER_SUPPLY_PROP_SCOPE,
 	POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL,
+	POWER_SUPPLY_PROP_RESISTANCE,
 	/* Properties of type `const char *' */
 	POWER_SUPPLY_PROP_MODEL_NAME,
 	POWER_SUPPLY_PROP_MANUFACTURER,
diff --git a/include/linux/qpnp/power-on.h b/include/linux/qpnp/power-on.h
index 85dbce9..6394988 100644
--- a/include/linux/qpnp/power-on.h
+++ b/include/linux/qpnp/power-on.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -17,8 +17,10 @@
 
 #ifdef CONFIG_QPNP_POWER_ON
 int qpnp_pon_system_pwr_off(bool reset);
+int qpnp_pon_is_warm_reset(void);
 #else
 static int qpnp_pon_system_pwr_off(bool reset) { return -ENODEV; }
+static inline int qpnp_pon_is_warm_reset(void) { return -ENODEV; }
 #endif
 
 #endif
diff --git a/include/linux/qpnp/qpnp-adc.h b/include/linux/qpnp/qpnp-adc.h
index 13d0b80..dfb156f 100644
--- a/include/linux/qpnp/qpnp-adc.h
+++ b/include/linux/qpnp/qpnp-adc.h
@@ -602,6 +602,34 @@
 	QPNP_ADC_TM_CH_SELECT_NONE
 };
 
+enum qpnp_comp_scheme_type {
+	COMP_ID_GF = 0,
+	COMP_ID_SMIC,
+	COMP_ID_TSMC,
+	COMP_ID_NUM,
+};
+
+enum qpnp_iadc_rev {
+	QPNP_IADC_VER_3_0 = 0x1,
+	QPNP_IADC_VER_3_1 = 0x3,
+};
+
+#define QPNP_VBAT_SNS_COEFF_1_TYPEA				3000
+#define QPNP_VBAT_SNS_COEFF_2_TYPEA				45810000
+#define QPNP_VBAT_SNS_COEFF_3					100000
+#define QPNP_VBAT_SNS_COEFF_1_TYPEB				3500
+#define QPNP_VBAT_SNS_COEFF_2_TYPEB				80000000
+
+#define QPNP_COEFF_1					969000
+#define QPNP_COEFF_2					34
+#define QPNP_COEFF_3_TYPEA				1700000
+#define QPNP_COEFF_3_TYPEB				1000000
+#define QPNP_COEFF_4					100
+#define QPNP_COEFF_5					15000
+#define QPNP_COEFF_6					100000
+#define QPNP_COEFF_7					21700
+#define QPNP_COEFF_8					100000000
+
 /**
  * struct qpnp_adc_tm_config - Represent ADC Thermal Monitor configuration.
  * @channel: ADC channel for which thermal monitoring is requested.
@@ -1252,6 +1280,11 @@
  */
 int32_t qpnp_vadc_iadc_sync_complete_request(
 	enum qpnp_vadc_channels channel, struct qpnp_vadc_result *result);
+/**
+ * qpnp_vadc_sns_comp_result() - Compensate vbatt readings based on temperature
+ * @result:	Voltage in uV that needs compensation.
+ */
+int32_t qpnp_vbat_sns_comp_result(int64_t *result);
 #else
 static inline int32_t qpnp_vadc_read(uint32_t channel,
 				struct qpnp_vadc_result *result)
@@ -1336,6 +1369,8 @@
 				enum qpnp_vadc_channels channel,
 				struct qpnp_vadc_result *result)
 { return -ENXIO; }
+static inline int32_t qpnp_vbat_sns_comp_result(int64_t *result)
+{ return -ENXIO; }
 #endif
 
 /* Public API */
@@ -1389,6 +1424,7 @@
  * @result:	0 on success.
  */
 int32_t qpnp_iadc_calibrate_for_trim(void);
+int32_t qpnp_iadc_comp_result(int64_t *result);
 #else
 static inline int32_t qpnp_iadc_read(enum qpnp_iadc_channels channel,
 						struct qpnp_iadc_result *result)
@@ -1406,6 +1442,8 @@
 { return -ENXIO; }
 static inline int32_t qpnp_iadc_calibrate_for_trim(void)
 { return -ENXIO; }
+static inline int32_t qpnp_iadc_comp_result(int64_t *result, int32_t sign)
+{ return -ENXIO; }
 #endif
 
 /* Public API */
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index 2a60b88..945840d 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -1260,6 +1260,22 @@
 	return 0;
 }
 
+static int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+					    struct snd_pcm_hw_params *params)
+{
+	struct snd_interval *rate = hw_param_interval(params,
+	SNDRV_PCM_HW_PARAM_RATE);
+
+	struct snd_interval *channels = hw_param_interval(params,
+			SNDRV_PCM_HW_PARAM_CHANNELS);
+
+	pr_debug("%s()\n", __func__);
+	rate->min = rate->max = 48000;
+	channels->min = channels->max = 2;
+
+	return 0;
+}
+
 static int msm_slim_5_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
 					    struct snd_pcm_hw_params *params)
 {
@@ -2195,7 +2211,7 @@
 		.codec_name = "taiko_codec",
 		.codec_dai_name	= "taiko_vifeedback",
 		.be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
-		.be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup,
+		.be_hw_params_fixup = msm_slim_4_tx_be_hw_params_fixup,
 		.ops = &msm8974_be_ops,
 		.no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
 		.ignore_suspend = 1,