commit 12efdde3139c568a59561b69865fd14f37c75603
author Thomas Gleixner <tglx@cruncher.tec.linutronix.de> Wed May 24 22:57:09 2006 +0200
committer David Woodhouse <dwmw2@infradead.org> Wed May 24 23:45:24 2006 +0100
tree ef5b0b445dd6da3ab61120bee09b3c93fae953a8
parent ace4dfee56fff184e07d7248a759b574321afa8b

[MTD] NAND fix cmd_ctrl breakage

The cmd_ctrl rework lacks some state transition flags.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

drivers/mtd/nand/nand_base.c

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 6036d32..5690de2 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -538,7 +538,8 @@
 		udelay(chip->chip_delay);
 		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 			       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
+		chip->cmd_ctrl(mtd,
+			       NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 		return;
 
@@ -641,14 +642,18 @@
 		if (chip->dev_ready)
 			break;
 		udelay(chip->chip_delay);
-		chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_NCE | NAND_CLE);
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
+		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
+			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
+			       NAND_NCE | NAND_CTRL_CHANGE);
 		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 		return;
 
 	case NAND_CMD_READ0:
-		chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_NCE | NAND_CLE);
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
+		chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
+			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
+			       NAND_NCE | NAND_CTRL_CHANGE);
 
 		/* This applies to read commands */
 	default: