ASoC: Support FLL input clock selection on WM8994
The WM8994 FLL can be clocked from one of four inputs, the two MCLKs and
the LRCLK and BCLK of the AIF associated with the FLL. Allow all four
inputs to be used rather than defaulting to MCLK1.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 29c4cfc..a27b2ff 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -2843,6 +2843,16 @@
return -EINVAL;
}
+ switch (src) {
+ case WM8994_FLL_SRC_MCLK1:
+ case WM8994_FLL_SRC_MCLK2:
+ case WM8994_FLL_SRC_LRCLK:
+ case WM8994_FLL_SRC_BCLK:
+ break;
+ default:
+ return -EINVAL;
+ }
+
/* Are we changing anything? */
if (wm8994->fll[id].src == src &&
wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
@@ -2883,8 +2893,10 @@
fll.n << WM8994_FLL1_N_SHIFT);
snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
- WM8994_FLL1_REFCLK_DIV_MASK,
- fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT);
+ WM8994_FLL1_REFCLK_DIV_MASK |
+ WM8994_FLL1_REFCLK_SRC_MASK,
+ (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
+ (src - 1));
/* Enable (with fractional mode if required) */
if (freq_out) {
@@ -2899,6 +2911,7 @@
wm8994->fll[id].in = freq_in;
wm8994->fll[id].out = freq_out;
+ wm8994->fll[id].src = src;
/* Enable any gated AIF clocks */
snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,