Merge "msm: clock-copper: Allow the bus driver to control mmssnoc_axi_clk" into msm-3.4
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 54a8392..174a799 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -248,28 +248,17 @@
u32 enabled;
unsigned long pending[32];
void __iomem *base = gic_data_dist_base(gic);
-#ifdef CONFIG_ARCH_MSM8625
- unsigned long flags;
-#endif
if (!msm_show_resume_irq_mask)
return;
-#ifdef CONFIG_ARCH_MSM8625
- raw_spin_lock_irqsave(&irq_controller_lock, flags);
-#else
raw_spin_lock(&irq_controller_lock);
-#endif
for (i = 0; i * 32 < gic->max_irq; i++) {
enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4);
pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4);
pending[i] &= enabled;
}
-#ifdef CONFIG_ARCH_MSM8625
- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
-#else
- raw_spin_lock(&irq_controller_lock);
-#endif
+ raw_spin_unlock(&irq_controller_lock);
for (i = find_first_bit(pending, gic->max_irq);
i < gic->max_irq;
@@ -283,22 +272,14 @@
{
unsigned int i;
void __iomem *base = gic_data_dist_base(gic);
-#ifdef CONFIG_ARCH_MSM8625
- unsigned long flags;
-#endif
+
gic_show_resume_irq(gic);
for (i = 0; i * 32 < gic->max_irq; i++) {
-#ifdef CONFIG_ARCH_MSM8625
- raw_spin_lock_irqsave(&irq_controller_lock, flags);
-#endif
/* disable all of them */
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4);
/* enable the enabled set */
writel_relaxed(gic->enabled_irqs[i],
base + GIC_DIST_ENABLE_SET + i * 4);
-#ifdef CONFIG_ARCH_MSM8625
- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
-#endif
}
mb();
}
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 2fecc60..a40f81e 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -25,7 +25,9 @@
ARM_PERF_PMU_ID_CA7,
ARM_PERF_PMU_ID_SCORPION,
ARM_PERF_PMU_ID_SCORPIONMP,
+ ARM_PERF_PMU_ID_SCORPIONMP_L2,
ARM_PERF_PMU_ID_KRAIT,
+ ARM_PERF_PMU_ID_KRAIT_L2,
ARM_NUM_PMU_IDS,
};
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 1e54b58..37cbfcb 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -21,7 +21,7 @@
*/
enum arm_pmu_type {
ARM_PMU_DEVICE_CPU = 0,
- ARM_PMU_DEVICE_L2 = 1,
+ ARM_PMU_DEVICE_L2CC = 1,
ARM_NUM_PMU_DEVICES,
};
@@ -129,11 +129,13 @@
u64 max_period;
struct platform_device *plat_device;
struct pmu_hw_events *(*get_hw_events)(void);
+ int (*test_set_event_constraints)(struct perf_event *event);
+ int (*clear_event_constraints)(struct perf_event *event);
};
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
u64 armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index af6e7e6..e37b28b 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -28,6 +28,8 @@
#include <asm/pmu.h>
#include <asm/stacktrace.h>
+#include <linux/cpu_pm.h>
+
/*
* ARMv6 supports a maximum of 3 events, starting from index 0. If we add
* another platform that supports more, we need to increase this to be the
@@ -271,6 +273,10 @@
hw_events->events[idx] = NULL;
clear_bit(idx, hw_events->used_mask);
+ /* Clear event constraints. */
+ if (armpmu->clear_event_constraints)
+ armpmu->clear_event_constraints(event);
+
perf_event_update_userpage(event);
}
@@ -284,6 +290,17 @@
int err = 0;
perf_pmu_disable(event->pmu);
+ /*
+ * Tests if event is constrained. If not sets it so that next
+ * collision can be detected.
+ */
+ if (armpmu->test_set_event_constraints)
+ if (armpmu->test_set_event_constraints(event) < 0) {
+ pr_err("Event: %llx failed constraint check.\n",
+ event->attr.config);
+ event->state = PERF_EVENT_STATE_OFF;
+ goto out;
+ }
/* If we don't have a space for the counter then finish early. */
idx = armpmu->get_event_idx(hw_events, hwc);
@@ -383,10 +400,7 @@
{
int i, irq, irqs;
struct platform_device *pmu_device = armpmu->plat_device;
-#if 0
- struct arm_pmu_platdata *plat =
- dev_get_platdata(&pmu_device->dev);
-#endif
+
irqs = min(pmu_device->num_resources, num_possible_cpus());
for (i = 0; i < irqs; ++i) {
@@ -394,13 +408,6 @@
continue;
irq = platform_get_irq(pmu_device, i);
armpmu->free_pmu_irq(irq);
-#if 0
- if (irq >= 0) {
- if (plat && plat->disable_irq)
- plat->disable_irq(irq);
- free_irq(irq, armpmu);
- }
-#endif
}
release_pmu(armpmu->type);
@@ -462,19 +469,6 @@
return err;
}
-#if 0
- err = request_irq(irq, handle_irq,
- IRQF_DISABLED | IRQF_NOBALANCING,
- "arm-pmu", armpmu);
- if (err) {
- pr_err("unable to request IRQ%d for ARM PMU counters\n",
- irq);
- armpmu_release_hardware(armpmu);
- return err;
- } else if (plat && plat->enable_irq)
- plat->enable_irq(irq);
-#endif
-
cpumask_set_cpu(i, &armpmu->active_irqs);
}
@@ -538,6 +532,7 @@
return -EPERM;
}
+
/*
* Store the event encoding into the config_base field.
*/
@@ -616,7 +611,7 @@
armpmu->stop();
}
-static void __init armpmu_init(struct arm_pmu *armpmu)
+static void armpmu_init(struct arm_pmu *armpmu)
{
atomic_set(&armpmu->active_events, 0);
mutex_init(&armpmu->reserve_mutex);
@@ -633,7 +628,7 @@
};
}
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
{
armpmu_init(armpmu);
return perf_pmu_register(&armpmu->pmu, name, type);
@@ -644,6 +639,7 @@
#include "perf_event_v6.c"
#include "perf_event_v7.c"
#include "perf_event_msm_krait.c"
+#include "perf_event_msm.c"
/*
* Ensure the PMU has sane values out of reset.
@@ -734,10 +730,76 @@
return NOTIFY_OK;
}
+static void armpmu_update_counters(void)
+{
+ struct pmu_hw_events *hw_events;
+ int idx;
+
+ if (!cpu_pmu)
+ return;
+
+ hw_events = cpu_pmu->get_hw_events();
+
+ for (idx = 0; idx <= cpu_pmu->num_events; ++idx) {
+ struct perf_event *event = hw_events->events[idx];
+
+ if (!event)
+ continue;
+
+ armpmu_read(event);
+ }
+}
+
+static int cpu_has_active_perf(void)
+{
+ struct pmu_hw_events *hw_events;
+ int enabled;
+
+ if (!cpu_pmu)
+ return 0;
+
+ hw_events = cpu_pmu->get_hw_events();
+ enabled = bitmap_weight(hw_events->used_mask, cpu_pmu->num_events);
+
+ if (enabled)
+ /*Even one event's existence is good enough.*/
+ return 1;
+
+ return 0;
+}
+
static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
.notifier_call = pmu_cpu_notify,
};
+/*TODO: Unify with pending patch from ARM */
+static int perf_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd,
+ void *v)
+{
+ switch (cmd) {
+ case CPU_PM_ENTER:
+ if (cpu_has_active_perf()) {
+ armpmu_update_counters();
+ perf_pmu_disable(&cpu_pmu->pmu);
+ }
+ break;
+
+ case CPU_PM_ENTER_FAILED:
+ case CPU_PM_EXIT:
+ if (cpu_has_active_perf() && cpu_pmu->reset) {
+ cpu_pmu->reset(NULL);
+ perf_pmu_enable(&cpu_pmu->pmu);
+ }
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block perf_cpu_pm_notifier_block = {
+ .notifier_call = perf_cpu_pm_notifier,
+};
+
/*
* CPU PMU identification and registration.
*/
@@ -790,11 +852,11 @@
} else if (0x51 == implementor) {
switch (part_number) {
case 0x00F0: /* 8x50 & 7x30*/
-// cpu_pmu = armv7_scorpion_pmu_init();
+ cpu_pmu = armv7_scorpion_pmu_init();
break;
case 0x02D0: /* 8x60 */
// fabricmon_pmu_init();
-// cpu_pmu = armv7_scorpionmp_pmu_init();
+ cpu_pmu = armv7_scorpionmp_pmu_init();
// scorpionmp_l2_pmu_init();
break;
case 0x0490: /* 8960 sim */
@@ -814,6 +876,7 @@
cpu_pmu_init(cpu_pmu);
register_cpu_notifier(&pmu_cpu_notifier);
armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
+ cpu_pm_register_notifier(&perf_cpu_pm_notifier_block);
} else {
pr_info("no hardware support available\n");
}
diff --git a/arch/arm/kernel/perf_event_msm.c b/arch/arm/kernel/perf_event_msm.c
index 0ca5164..46fa8fe 100644
--- a/arch/arm/kernel/perf_event_msm.c
+++ b/arch/arm/kernel/perf_event_msm.c
@@ -12,7 +12,7 @@
*/
#include <linux/cpumask.h>
-
+#include <asm/cp15.h>
#include <asm/vfp.h>
#include <asm/system.h>
#include "../vfp/vfpinstr.h"
@@ -143,12 +143,16 @@
* combined.
*/
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
+ [C(RESULT_ACCESS)]
+ = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)]
+ = ARMV7_PERFCTR_L1_DCACHE_REFILL,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
+ [C(RESULT_ACCESS)]
+ = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)]
+ = ARMV7_PERFCTR_L1_DCACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -236,6 +240,13 @@
},
};
+static int msm_scorpion_map_event(struct perf_event *event)
+{
+ return map_cpu_event(event, &armv7_scorpion_perf_map,
+ &armv7_scorpion_perf_cache_map, 0xfffff);
+}
+
+
struct scorpion_evt {
/*
* The scorpion_evt_type field corresponds to the actual Scorpion
@@ -483,9 +494,9 @@
u32 v_orig_val;
u32 f_orig_val;
- /* CPACR Enable CP10 access */
+ /* CPACR Enable CP10 and CP11 access */
v_orig_val = get_copro_access();
- venum_new_val = v_orig_val | CPACC_SVC(10);
+ venum_new_val = v_orig_val | CPACC_SVC(10) | CPACC_SVC(11);
set_copro_access(venum_new_val);
/* Store orig venum val */
__get_cpu_var(venum_orig_val) = v_orig_val;
@@ -551,17 +562,13 @@
static void scorpion_clear_pmuregs(void)
{
- unsigned long flags;
-
scorpion_write_lpm0(0);
scorpion_write_lpm1(0);
scorpion_write_lpm2(0);
scorpion_write_l2lpm(0);
- raw_spin_lock_irqsave(&pmu_lock, flags);
scorpion_pre_vlpm();
scorpion_write_vlpm(0);
scorpion_post_vlpm();
- raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void scorpion_clearpmu(u32 grp, u32 val, u32 evt_code)
@@ -585,9 +592,11 @@
u32 gr;
unsigned long event;
struct scorpion_evt evtinfo;
+ struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+
/* Disable counter and interrupt */
- raw_spin_lock_irqsave(&pmu_lock, flags);
+ raw_spin_lock_irqsave(&events->pmu_lock, flags);
/* Disable counter */
armv7_pmnc_disable_counter(idx);
@@ -596,7 +605,7 @@
* Clear lpm code (if destined for PMNx counters)
* We don't need to set the event if it's a cycle count
*/
- if (idx != ARMV7_CYCLE_COUNTER) {
+ if (idx != ARMV7_IDX_CYCLE_COUNTER) {
val = hwc->config_base;
val &= SCORPION_EVTYPE_EVENT;
@@ -613,10 +622,11 @@
armv7_pmnc_disable_intens(idx);
scorpion_dis_out:
- raw_spin_unlock_irqrestore(&pmu_lock, flags);
+ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
-static void scorpion_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+static void scorpion_pmu_enable_event(struct hw_perf_event *hwc,
+ int idx, int cpu)
{
unsigned long flags;
u32 val = 0;
@@ -624,12 +634,13 @@
unsigned long event;
struct scorpion_evt evtinfo;
unsigned long long prev_count = local64_read(&hwc->prev_count);
+ struct pmu_hw_events *events = cpu_pmu->get_hw_events();
/*
* Enable counter and interrupt, and set the counter to count
* the event that we're interested in.
*/
- raw_spin_lock_irqsave(&pmu_lock, flags);
+ raw_spin_lock_irqsave(&events->pmu_lock, flags);
/* Disable counter */
armv7_pmnc_disable_counter(idx);
@@ -638,7 +649,7 @@
* Set event (if destined for PMNx counters)
* We don't need to set the event if it's a cycle count
*/
- if (idx != ARMV7_CYCLE_COUNTER) {
+ if (idx != ARMV7_IDX_CYCLE_COUNTER) {
val = hwc->config_base;
val &= SCORPION_EVTYPE_EVENT;
@@ -673,59 +684,12 @@
armv7_pmnc_enable_counter(idx);
scorpion_out:
- raw_spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void enable_irq_callback(void *info)
-{
- int irq = *(unsigned int *)info;
-
- enable_percpu_irq(irq, IRQ_TYPE_EDGE_RISING);
-}
-
-static void disable_irq_callback(void *info)
-{
- int irq = *(unsigned int *)info;
-
- disable_percpu_irq(irq);
-}
-
-static int
-msm_request_irq(int irq, irq_handler_t *handle_irq)
-{
- int err = 0;
- int cpu;
-
- err = request_percpu_irq(irq, *handle_irq, "armpmu",
- &cpu_hw_events);
-
- if (!err) {
- for_each_cpu(cpu, cpu_online_mask) {
- smp_call_function_single(cpu,
- enable_irq_callback, &irq, 1);
- }
- }
-
- return err;
-}
-
-static void
-msm_free_irq(int irq)
-{
- int cpu;
-
- if (irq >= 0) {
- for_each_cpu(cpu, cpu_online_mask) {
- smp_call_function_single(cpu,
- disable_irq_callback, &irq, 1);
- }
- free_percpu_irq(irq, &cpu_hw_events);
- }
+ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
static void scorpion_pmu_reset(void *info)
{
- u32 idx, nb_cnt = armpmu->num_events;
+ u32 idx, nb_cnt = cpu_pmu->num_events;
/* Stop all counters and their interrupts */
for (idx = 1; idx < nb_cnt; ++idx) {
@@ -751,7 +715,7 @@
.disable = scorpion_pmu_disable_event,
.read_counter = armv7pmu_read_counter,
.write_counter = armv7pmu_write_counter,
- .raw_event_mask = 0xFFFFF,
+ .map_event = msm_scorpion_map_event,
.get_event_idx = armv7pmu_get_event_idx,
.start = armv7pmu_start,
.stop = armv7pmu_stop,
@@ -759,33 +723,29 @@
.max_period = (1LLU << 32) - 1,
};
-static const struct arm_pmu *__init armv7_scorpion_pmu_init(void)
+static struct arm_pmu *__init armv7_scorpion_pmu_init(void)
{
scorpion_pmu.id = ARM_PERF_PMU_ID_SCORPION;
scorpion_pmu.name = "ARMv7 Scorpion";
- scorpion_pmu.cache_map = &armv7_scorpion_perf_cache_map;
- scorpion_pmu.event_map = &armv7_scorpion_perf_map;
scorpion_pmu.num_events = armv7_read_num_pmnc_events();
scorpion_clear_pmuregs();
return &scorpion_pmu;
}
-static const struct arm_pmu *__init armv7_scorpionmp_pmu_init(void)
+static struct arm_pmu *__init armv7_scorpionmp_pmu_init(void)
{
scorpion_pmu.id = ARM_PERF_PMU_ID_SCORPIONMP;
scorpion_pmu.name = "ARMv7 Scorpion-MP";
- scorpion_pmu.cache_map = &armv7_scorpion_perf_cache_map;
- scorpion_pmu.event_map = &armv7_scorpion_perf_map;
scorpion_pmu.num_events = armv7_read_num_pmnc_events();
scorpion_clear_pmuregs();
return &scorpion_pmu;
}
#else
-static const struct arm_pmu *__init armv7_scorpion_pmu_init(void)
+static struct arm_pmu *__init armv7_scorpion_pmu_init(void)
{
return NULL;
}
-static const struct arm_pmu *__init armv7_scorpionmp_pmu_init(void)
+static struct arm_pmu *__init armv7_scorpionmp_pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/perf_event_msm_krait.c b/arch/arm/kernel/perf_event_msm_krait.c
index 8dbd047..1b115b4 100644
--- a/arch/arm/kernel/perf_event_msm_krait.c
+++ b/arch/arm/kernel/perf_event_msm_krait.c
@@ -58,6 +58,17 @@
static u32 krait_ver, evt_index;
static u32 krait_max_l1_reg;
+
+/*
+ * Every 4 bytes represents a prefix.
+ * Every nibble represents a register.
+ * Every bit represents a group within a register.
+ *
+ * This supports up to 4 groups per register, upto 8
+ * registers per prefix and upto 2 prefixes.
+ */
+static DEFINE_PER_CPU(u64, pmu_bitmap);
+
static const unsigned armv7_krait_perf_map[PERF_COUNT_HW_MAX] = {
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
@@ -556,6 +567,58 @@
}
}
+/*
+ * We check for column exclusion constraints here.
+ * Two events cant have same reg and same group.
+ */
+static int msm_test_set_ev_constraint(struct perf_event *event)
+{
+ u32 krait_evt_type = event->attr.config & KRAIT_EVENT_MASK;
+ u8 prefix = (krait_evt_type & 0xF0000) >> 16;
+ u8 reg = (krait_evt_type & 0x0F000) >> 12;
+ u8 group = krait_evt_type & 0x0000F;
+ u64 cpu_pmu_bitmap = __get_cpu_var(pmu_bitmap);
+ u64 bitmap_t;
+
+ /* Return if non MSM event. */
+ if (!prefix)
+ return 0;
+
+ bitmap_t = 1 << (((prefix - 1) * 32) + (reg * 4) + group);
+
+ /* Set it if not already set. */
+ if (!(cpu_pmu_bitmap & bitmap_t)) {
+ cpu_pmu_bitmap |= bitmap_t;
+ __get_cpu_var(pmu_bitmap) = cpu_pmu_bitmap;
+ return 1;
+ }
+ /* Bit is already set. Constraint failed. */
+ return -EPERM;
+}
+
+static int msm_clear_ev_constraint(struct perf_event *event)
+{
+ u32 krait_evt_type = event->attr.config & KRAIT_EVENT_MASK;
+ u8 prefix = (krait_evt_type & 0xF0000) >> 16;
+ u8 reg = (krait_evt_type & 0x0F000) >> 12;
+ u8 group = krait_evt_type & 0x0000F;
+ u64 cpu_pmu_bitmap = __get_cpu_var(pmu_bitmap);
+ u64 bitmap_t;
+
+ /* Return if non MSM event. */
+ if (!prefix)
+ return 0;
+
+ bitmap_t = 1 << (((prefix - 1) * 32) + (reg * 4) + group);
+
+ /* Clear constraint bit. */
+ cpu_pmu_bitmap &= ~(bitmap_t);
+
+ __get_cpu_var(pmu_bitmap) = cpu_pmu_bitmap;
+
+ return 1;
+}
+
static struct arm_pmu krait_pmu = {
.handle_irq = armv7pmu_handle_irq,
.request_pmu_irq = msm_request_irq,
@@ -568,6 +631,8 @@
.start = armv7pmu_start,
.stop = armv7pmu_stop,
.reset = krait_pmu_reset,
+ .test_set_event_constraints = msm_test_set_ev_constraint,
+ .clear_event_constraints = msm_clear_ev_constraint,
.max_period = (1LLU << 32) - 1,
};
diff --git a/arch/arm/kernel/perf_event_msm_krait_l2.c b/arch/arm/kernel/perf_event_msm_krait_l2.c
deleted file mode 100644
index baa05ac..0000000
--- a/arch/arm/kernel/perf_event_msm_krait_l2.c
+++ /dev/null
@@ -1,667 +0,0 @@
-/*
- * Copyright (c) 2011, 2012 Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifdef CONFIG_ARCH_MSM_KRAIT
-
-#include <linux/irq.h>
-
-#include <mach/msm-krait-l2-accessors.h>
-
-#define MAX_L2_PERIOD ((1ULL << 32) - 1)
-#define MAX_KRAIT_L2_CTRS 5
-
-#define L2PMCCNTR 0x409
-#define L2PMCCNTCR 0x408
-#define L2PMCCNTSR 0x40A
-#define L2CYCLE_CTR_BIT 31
-#define L2CYCLE_CTR_EVENT_IDX 4
-#define L2CYCLE_CTR_RAW_CODE 0xfe
-
-#define L2PMOVSR 0x406
-
-#define L2PMCR 0x400
-#define L2PMCR_RESET_ALL 0x6
-#define L2PMCR_GLOBAL_ENABLE 0x1
-#define L2PMCR_GLOBAL_DISABLE 0x0
-
-#define L2PMCNTENSET 0x403
-#define L2PMCNTENCLR 0x402
-
-#define L2PMINTENSET 0x405
-#define L2PMINTENCLR 0x404
-
-#define IA_L2PMXEVCNTCR_BASE 0x420
-#define IA_L2PMXEVTYPER_BASE 0x424
-#define IA_L2PMRESX_BASE 0x410
-#define IA_L2PMXEVFILTER_BASE 0x423
-#define IA_L2PMXEVCNTR_BASE 0x421
-
-/* event format is -e rsRCCG See get_event_desc() */
-
-#define EVENT_REG_MASK 0xf000
-#define EVENT_GROUPSEL_MASK 0x000f
-#define EVENT_GROUPCODE_MASK 0x0ff0
-#define EVENT_REG_SHIFT 12
-#define EVENT_GROUPCODE_SHIFT 4
-
-#define RESRX_VALUE_EN 0x80000000
-
-static struct platform_device *l2_pmu_device;
-
-struct hw_krait_l2_pmu {
- struct perf_event *events[MAX_KRAIT_L2_CTRS];
- unsigned long active_mask[BITS_TO_LONGS(MAX_KRAIT_L2_CTRS)];
- raw_spinlock_t lock;
-};
-
-struct hw_krait_l2_pmu hw_krait_l2_pmu;
-
-struct event_desc {
- int event_groupsel;
- int event_reg;
- int event_group_code;
-};
-
-void get_event_desc(u64 config, struct event_desc *evdesc)
-{
- /* L2PMEVCNTRX */
- evdesc->event_reg = (config & EVENT_REG_MASK) >> EVENT_REG_SHIFT;
- /* Group code (row ) */
- evdesc->event_group_code =
- (config & EVENT_GROUPCODE_MASK) >> EVENT_GROUPCODE_SHIFT;
- /* Group sel (col) */
- evdesc->event_groupsel = (config & EVENT_GROUPSEL_MASK);
-
- pr_debug("%s: reg: %x, group_code: %x, groupsel: %x\n", __func__,
- evdesc->event_reg, evdesc->event_group_code,
- evdesc->event_groupsel);
-}
-
-static void set_evcntcr(int ctr)
-{
- u32 evtcr_reg = (ctr * 16) + IA_L2PMXEVCNTCR_BASE;
-
- set_l2_indirect_reg(evtcr_reg, 0x0);
-}
-
-static void set_evtyper(int event_groupsel, int event_reg, int ctr)
-{
- u32 evtype_reg = (ctr * 16) + IA_L2PMXEVTYPER_BASE;
- u32 evtype_val = event_groupsel + (4 * event_reg);
-
- set_l2_indirect_reg(evtype_reg, evtype_val);
-}
-
-static void set_evres(int event_groupsel, int event_reg, int event_group_code)
-{
- u32 group_reg = event_reg + IA_L2PMRESX_BASE;
- u32 group_val =
- RESRX_VALUE_EN | (event_group_code << (8 * event_groupsel));
- u32 resr_val;
- u32 group_byte = 0xff;
- u32 group_mask = ~(group_byte << (8 * event_groupsel));
-
- resr_val = get_l2_indirect_reg(group_reg);
- resr_val &= group_mask;
- resr_val |= group_val;
-
- set_l2_indirect_reg(group_reg, resr_val);
-}
-
-static void set_evfilter_task_mode(int ctr)
-{
- u32 filter_reg = (ctr * 16) + IA_L2PMXEVFILTER_BASE;
- u32 filter_val = 0x000f0030 | 1 << smp_processor_id();
-
- set_l2_indirect_reg(filter_reg, filter_val);
-}
-
-static void set_evfilter_sys_mode(int ctr)
-{
- u32 filter_reg = (ctr * 16) + IA_L2PMXEVFILTER_BASE;
- u32 filter_val = 0x000f003f;
-
- set_l2_indirect_reg(filter_reg, filter_val);
-}
-
-static void enable_intenset(u32 idx)
-{
- if (idx == L2CYCLE_CTR_EVENT_IDX)
- set_l2_indirect_reg(L2PMINTENSET, 1 << L2CYCLE_CTR_BIT);
- else
- set_l2_indirect_reg(L2PMINTENSET, 1 << idx);
-}
-
-static void disable_intenclr(u32 idx)
-{
- if (idx == L2CYCLE_CTR_EVENT_IDX)
- set_l2_indirect_reg(L2PMINTENCLR, 1 << L2CYCLE_CTR_BIT);
- else
- set_l2_indirect_reg(L2PMINTENCLR, 1 << idx);
-}
-
-static void enable_counter(u32 idx)
-{
- if (idx == L2CYCLE_CTR_EVENT_IDX)
- set_l2_indirect_reg(L2PMCNTENSET, 1 << L2CYCLE_CTR_BIT);
- else
- set_l2_indirect_reg(L2PMCNTENSET, 1 << idx);
-}
-
-static void disable_counter(u32 idx)
-{
- if (idx == L2CYCLE_CTR_EVENT_IDX)
- set_l2_indirect_reg(L2PMCNTENCLR, 1 << L2CYCLE_CTR_BIT);
- else
- set_l2_indirect_reg(L2PMCNTENCLR, 1 << idx);
-}
-
-static u64 read_counter(u32 idx)
-{
- u32 val;
- u32 counter_reg = (idx * 16) + IA_L2PMXEVCNTR_BASE;
-
- if (idx == L2CYCLE_CTR_EVENT_IDX)
- val = get_l2_indirect_reg(L2PMCCNTR);
- else
- val = get_l2_indirect_reg(counter_reg);
-
- return val;
-}
-
-static void write_counter(u32 idx, u32 val)
-{
- u32 counter_reg = (idx * 16) + IA_L2PMXEVCNTR_BASE;
-
- if (idx == L2CYCLE_CTR_EVENT_IDX)
- set_l2_indirect_reg(L2PMCCNTR, val);
- else
- set_l2_indirect_reg(counter_reg, val);
-}
-
-static int
-pmu_event_set_period(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- s64 left = local64_read(&hwc->period_left);
- s64 period = hwc->sample_period;
- int ret = 0;
-
- if (unlikely(left <= -period)) {
- left = period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (unlikely(left <= 0)) {
- left += period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (left > (s64) MAX_L2_PERIOD)
- left = MAX_L2_PERIOD;
-
- local64_set(&hwc->prev_count, (u64)-left);
-
- write_counter(idx, (u64) (-left) & 0xffffffff);
-
- perf_event_update_userpage(event);
-
- return ret;
-}
-
-static u64
-pmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, int idx,
- int overflow)
-{
- u64 prev_raw_count, new_raw_count;
- u64 delta;
-
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = read_counter(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- new_raw_count &= MAX_L2_PERIOD;
- prev_raw_count &= MAX_L2_PERIOD;
-
- if (overflow)
- delta = MAX_L2_PERIOD - prev_raw_count + new_raw_count;
- else
- delta = new_raw_count - prev_raw_count;
-
- local64_add(delta, &event->count);
- local64_sub(delta, &hwc->period_left);
-
- pr_debug("%s: new: %lld, prev: %lld, event: %ld count: %lld\n",
- __func__, new_raw_count, prev_raw_count,
- hwc->config_base, local64_read(&event->count));
-
- return new_raw_count;
-}
-
-static void krait_l2_read(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
-
- pmu_event_update(event, hwc, hwc->idx, 0);
-}
-
-static void krait_l2_stop_counter(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (!(hwc->state & PERF_HES_STOPPED)) {
- disable_intenclr(idx);
- disable_counter(idx);
-
- pmu_event_update(event, hwc, idx, 0);
- hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
- }
-
- pr_debug("%s: event: %ld ctr: %d stopped\n", __func__, hwc->config_base,
- idx);
-}
-
-static void krait_l2_start_counter(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- struct event_desc evdesc;
-
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
-
- hwc->state = 0;
-
- pmu_event_set_period(event, hwc, idx);
-
- if (hwc->config_base == L2CYCLE_CTR_RAW_CODE)
- goto out;
-
- set_evcntcr(idx);
-
- memset(&evdesc, 0, sizeof(evdesc));
-
- get_event_desc(hwc->config_base, &evdesc);
-
- set_evtyper(evdesc.event_groupsel, evdesc.event_reg, idx);
-
- set_evres(evdesc.event_groupsel, evdesc.event_reg,
- evdesc.event_group_code);
-
- if (event->cpu < 0)
- set_evfilter_task_mode(idx);
- else
- set_evfilter_sys_mode(idx);
-
-out:
- enable_intenset(idx);
- enable_counter(idx);
-
- pr_debug
- ("%s: ctr: %d group: %ld group_code: %lld started from cpu:%d\n",
- __func__, idx, hwc->config_base, hwc->config, smp_processor_id());
-}
-
-static void krait_l2_del_event(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- unsigned long iflags;
-
- raw_spin_lock_irqsave(&hw_krait_l2_pmu.lock, iflags);
-
- clear_bit(idx, (long unsigned int *)(&hw_krait_l2_pmu.active_mask));
-
- krait_l2_stop_counter(event, PERF_EF_UPDATE);
- hw_krait_l2_pmu.events[idx] = NULL;
- hwc->idx = -1;
-
- raw_spin_unlock_irqrestore(&hw_krait_l2_pmu.lock, iflags);
-
- pr_debug("%s: event: %ld deleted\n", __func__, hwc->config_base);
-
- perf_event_update_userpage(event);
-}
-
-static int krait_l2_add_event(struct perf_event *event, int flags)
-{
- int ctr = 0;
- struct hw_perf_event *hwc = &event->hw;
- unsigned long iflags;
- int err = 0;
-
- perf_pmu_disable(event->pmu);
-
- raw_spin_lock_irqsave(&hw_krait_l2_pmu.lock, iflags);
-
- /* Cycle counter has a resrvd index */
- if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
- if (hw_krait_l2_pmu.events[L2CYCLE_CTR_EVENT_IDX]) {
- pr_err("%s: Stale cycle ctr event ptr !\n", __func__);
- err = -EINVAL;
- goto out;
- }
- hwc->idx = L2CYCLE_CTR_EVENT_IDX;
- hw_krait_l2_pmu.events[L2CYCLE_CTR_EVENT_IDX] = event;
- set_bit(L2CYCLE_CTR_EVENT_IDX,
- (long unsigned int *)&hw_krait_l2_pmu.active_mask);
- goto skip_ctr_loop;
- }
-
- for (ctr = 0; ctr < MAX_KRAIT_L2_CTRS - 1; ctr++) {
- if (!hw_krait_l2_pmu.events[ctr]) {
- hwc->idx = ctr;
- hw_krait_l2_pmu.events[ctr] = event;
- set_bit(ctr,
- (long unsigned int *)
- &hw_krait_l2_pmu.active_mask);
- break;
- }
- }
-
- if (hwc->idx < 0) {
- err = -ENOSPC;
- pr_err("%s: No space for event: %llx!!\n", __func__,
- event->attr.config);
- goto out;
- }
-
-skip_ctr_loop:
-
- disable_counter(hwc->idx);
-
- hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
-
- if (flags & PERF_EF_START)
- krait_l2_start_counter(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
-
- pr_debug("%s: event: %ld, ctr: %d added from cpu:%d\n",
- __func__, hwc->config_base, hwc->idx, smp_processor_id());
-out:
- raw_spin_unlock_irqrestore(&hw_krait_l2_pmu.lock, iflags);
-
- /* Resume the PMU even if this event could not be added */
- perf_pmu_enable(event->pmu);
-
- return err;
-}
-
-static void krait_l2_pmu_enable(struct pmu *pmu)
-{
- isb();
- set_l2_indirect_reg(L2PMCR, L2PMCR_GLOBAL_ENABLE);
-}
-
-static void krait_l2_pmu_disable(struct pmu *pmu)
-{
- set_l2_indirect_reg(L2PMCR, L2PMCR_GLOBAL_DISABLE);
- isb();
-}
-
-u32 get_reset_pmovsr(void)
-{
- int val;
-
- val = get_l2_indirect_reg(L2PMOVSR);
- /* reset it */
- val &= 0xffffffff;
- set_l2_indirect_reg(L2PMOVSR, val);
-
- return val;
-}
-
-static irqreturn_t krait_l2_handle_irq(int irq_num, void *dev)
-{
- unsigned long pmovsr;
- struct perf_sample_data data;
- struct pt_regs *regs;
- struct perf_event *event;
- struct hw_perf_event *hwc;
- int bitp;
- int idx = 0;
-
- pmovsr = get_reset_pmovsr();
-
- if (!(pmovsr & 0xffffffff))
- return IRQ_NONE;
-
- regs = get_irq_regs();
-
- perf_sample_data_init(&data, 0);
-
- raw_spin_lock(&hw_krait_l2_pmu.lock);
-
- while (pmovsr) {
- bitp = __ffs(pmovsr);
-
- if (bitp == L2CYCLE_CTR_BIT)
- idx = L2CYCLE_CTR_EVENT_IDX;
- else
- idx = bitp;
-
- event = hw_krait_l2_pmu.events[idx];
-
- if (!event)
- goto next;
-
- if (!test_bit(idx, hw_krait_l2_pmu.active_mask))
- goto next;
-
- hwc = &event->hw;
- pmu_event_update(event, hwc, idx, 1);
- data.period = event->hw.last_period;
-
- if (!pmu_event_set_period(event, hwc, idx))
- goto next;
-
- if (perf_event_overflow(event, 0, &data, regs))
- disable_counter(hwc->idx);
-next:
- pmovsr &= (pmovsr - 1);
- }
-
- raw_spin_unlock(&hw_krait_l2_pmu.lock);
-
- irq_work_run();
-
- return IRQ_HANDLED;
-}
-
-static atomic_t active_l2_events = ATOMIC_INIT(0);
-static DEFINE_MUTEX(krait_pmu_reserve_mutex);
-
-static int pmu_reserve_hardware(void)
-{
- int i, err = -ENODEV, irq;
-
- l2_pmu_device = reserve_pmu(ARM_PMU_DEVICE_L2);
-
- if (IS_ERR(l2_pmu_device)) {
- pr_warning("unable to reserve pmu\n");
- return PTR_ERR(l2_pmu_device);
- }
-
- if (l2_pmu_device->num_resources < 1) {
- pr_err("no irqs for PMUs defined\n");
- return -ENODEV;
- }
-
- if (strncmp(l2_pmu_device->name, "l2-arm-pmu", 6)) {
- pr_err("Incorrect pdev reserved !\n");
- return -EINVAL;
- }
-
- for (i = 0; i < l2_pmu_device->num_resources; ++i) {
- irq = platform_get_irq(l2_pmu_device, i);
- if (irq < 0)
- continue;
-
- err = request_irq(irq, krait_l2_handle_irq,
- IRQF_DISABLED | IRQF_NOBALANCING,
- "krait-l2-pmu", NULL);
- if (err) {
- pr_warning("unable to request IRQ%d for Krait L2 perf "
- "counters\n", irq);
- break;
- }
-
- irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
- }
-
- if (err) {
- for (i = i - 1; i >= 0; --i) {
- irq = platform_get_irq(l2_pmu_device, i);
- if (irq >= 0)
- free_irq(irq, NULL);
- }
- release_pmu(l2_pmu_device);
- l2_pmu_device = NULL;
- }
-
- return err;
-}
-
-static void pmu_release_hardware(void)
-{
- int i, irq;
-
- for (i = l2_pmu_device->num_resources - 1; i >= 0; --i) {
- irq = platform_get_irq(l2_pmu_device, i);
- if (irq >= 0)
- free_irq(irq, NULL);
- }
-
- krait_l2_pmu_disable(NULL);
-
- release_pmu(l2_pmu_device);
- l2_pmu_device = NULL;
-}
-
-static void pmu_perf_event_destroy(struct perf_event *event)
-{
- if (atomic_dec_and_mutex_lock
- (&active_l2_events, &krait_pmu_reserve_mutex)) {
- pmu_release_hardware();
- mutex_unlock(&krait_pmu_reserve_mutex);
- }
-}
-
-static int krait_l2_event_init(struct perf_event *event)
-{
- int err = 0;
- struct hw_perf_event *hwc = &event->hw;
- int status = 0;
-
- switch (event->attr.type) {
- case PERF_TYPE_SHARED:
- break;
-
- default:
- return -ENOENT;
- }
-
- hwc->idx = -1;
-
- event->destroy = pmu_perf_event_destroy;
-
- if (!atomic_inc_not_zero(&active_l2_events)) {
- /* 0 active events */
- mutex_lock(&krait_pmu_reserve_mutex);
- err = pmu_reserve_hardware();
- mutex_unlock(&krait_pmu_reserve_mutex);
- if (!err)
- atomic_inc(&active_l2_events);
- else
- return err;
- }
-
- hwc->config = 0;
- hwc->event_base = 0;
-
- /* Check if we came via perf default syms */
- if (event->attr.config == PERF_COUNT_HW_L2_CYCLES)
- hwc->config_base = L2CYCLE_CTR_RAW_CODE;
- else
- hwc->config_base = event->attr.config;
-
- /* Only one CPU can control the cycle counter */
- if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
- /* Check if its already running */
- status = get_l2_indirect_reg(L2PMCCNTSR);
- if (status == 0x2) {
- err = -ENOSPC;
- goto out;
- }
- }
-
- if (!hwc->sample_period) {
- hwc->sample_period = MAX_L2_PERIOD;
- hwc->last_period = hwc->sample_period;
- local64_set(&hwc->period_left, hwc->sample_period);
- }
-
- pr_debug("%s: event: %lld init'd\n", __func__, event->attr.config);
-
-out:
- if (err < 0)
- pmu_perf_event_destroy(event);
-
- return err;
-}
-
-static struct pmu krait_l2_pmu = {
- .pmu_enable = krait_l2_pmu_enable,
- .pmu_disable = krait_l2_pmu_disable,
- .event_init = krait_l2_event_init,
- .add = krait_l2_add_event,
- .del = krait_l2_del_event,
- .start = krait_l2_start_counter,
- .stop = krait_l2_stop_counter,
- .read = krait_l2_read,
-};
-
-static const struct arm_pmu *__init krait_l2_pmu_init(void)
-{
- /* Register our own PMU here */
- perf_pmu_register(&krait_l2_pmu, "Krait L2", PERF_TYPE_SHARED);
-
- memset(&hw_krait_l2_pmu, 0, sizeof(hw_krait_l2_pmu));
-
- /* Reset all ctrs */
- set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
-
- /* Avoid spurious interrupt if any */
- get_reset_pmovsr();
-
- raw_spin_lock_init(&hw_krait_l2_pmu.lock);
-
- /* Don't return an arm_pmu here */
- return NULL;
-}
-#else
-
-static const struct arm_pmu *__init krait_l2_pmu_init(void)
-{
- return NULL;
-}
-#endif
diff --git a/arch/arm/kernel/perf_event_msm_l2.c b/arch/arm/kernel/perf_event_msm_l2.c
deleted file mode 100644
index 26753d8..0000000
--- a/arch/arm/kernel/perf_event_msm_l2.c
+++ /dev/null
@@ -1,1013 +0,0 @@
-/*
- * Copyright (c) 2011, 2012 Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifdef CONFIG_ARCH_MSM8X60
-
-#include <linux/irq.h>
-
-#define MAX_BB_L2_PERIOD ((1ULL << 32) - 1)
-#define MAX_BB_L2_CTRS 5
-#define BB_L2CYCLE_CTR_BIT 31
-#define BB_L2CYCLE_CTR_EVENT_IDX 4
-#define BB_L2CYCLE_CTR_RAW_CODE 0xfe
-#define SCORPIONL2_PMNC_E (1 << 0) /* Enable all counters */
-#define SCORPION_L2_EVT_PREFIX 3
-#define SCORPION_MAX_L2_REG 4
-
-/*
- * Lock to protect r/m/w sequences to the L2 PMU.
- */
-DEFINE_RAW_SPINLOCK(bb_l2_pmu_lock);
-
-static struct platform_device *bb_l2_pmu_device;
-
-struct hw_bb_l2_pmu {
- struct perf_event *events[MAX_BB_L2_CTRS];
- unsigned long active_mask[BITS_TO_LONGS(MAX_BB_L2_CTRS)];
- raw_spinlock_t lock;
-};
-
-struct hw_bb_l2_pmu hw_bb_l2_pmu;
-
-struct bb_l2_scorp_evt {
- u32 evt_type;
- u32 val;
- u8 grp;
- u32 evt_type_act;
-};
-
-enum scorpion_perf_types {
- SCORPIONL2_TOTAL_BANK_REQ = 0x90,
- SCORPIONL2_DSIDE_READ = 0x91,
- SCORPIONL2_DSIDE_WRITE = 0x92,
- SCORPIONL2_ISIDE_READ = 0x93,
- SCORPIONL2_L2CACHE_ISIDE_READ = 0x94,
- SCORPIONL2_L2CACHE_BANK_REQ = 0x95,
- SCORPIONL2_L2CACHE_DSIDE_READ = 0x96,
- SCORPIONL2_L2CACHE_DSIDE_WRITE = 0x97,
- SCORPIONL2_L2NOCACHE_DSIDE_WRITE = 0x98,
- SCORPIONL2_L2NOCACHE_ISIDE_READ = 0x99,
- SCORPIONL2_L2NOCACHE_TOTAL_REQ = 0x9a,
- SCORPIONL2_L2NOCACHE_DSIDE_READ = 0x9b,
- SCORPIONL2_DSIDE_READ_NOL1 = 0x9c,
- SCORPIONL2_L2CACHE_WRITETHROUGH = 0x9d,
- SCORPIONL2_BARRIERS = 0x9e,
- SCORPIONL2_HARDWARE_TABLE_WALKS = 0x9f,
- SCORPIONL2_MVA_POC = 0xa0,
- SCORPIONL2_L2CACHE_HW_TABLE_WALKS = 0xa1,
- SCORPIONL2_SETWAY_CACHE_OPS = 0xa2,
- SCORPIONL2_DSIDE_WRITE_HITS = 0xa3,
- SCORPIONL2_ISIDE_READ_HITS = 0xa4,
- SCORPIONL2_CACHE_DSIDE_READ_NOL1 = 0xa5,
- SCORPIONL2_TOTAL_CACHE_HITS = 0xa6,
- SCORPIONL2_CACHE_MATCH_MISS = 0xa7,
- SCORPIONL2_DREAD_HIT_L1_DATA = 0xa8,
- SCORPIONL2_L2LINE_LOCKED = 0xa9,
- SCORPIONL2_HW_TABLE_WALK_HIT = 0xaa,
- SCORPIONL2_CACHE_MVA_POC = 0xab,
- SCORPIONL2_L2ALLOC_DWRITE_MISS = 0xac,
- SCORPIONL2_CORRECTED_TAG_ARRAY = 0xad,
- SCORPIONL2_CORRECTED_DATA_ARRAY = 0xae,
- SCORPIONL2_CORRECTED_REPLACEMENT_ARRAY = 0xaf,
- SCORPIONL2_PMBUS_MPAAF = 0xb0,
- SCORPIONL2_PMBUS_MPWDAF = 0xb1,
- SCORPIONL2_PMBUS_MPBRT = 0xb2,
- SCORPIONL2_CPU0_GRANT = 0xb3,
- SCORPIONL2_CPU1_GRANT = 0xb4,
- SCORPIONL2_CPU0_NOGRANT = 0xb5,
- SCORPIONL2_CPU1_NOGRANT = 0xb6,
- SCORPIONL2_CPU0_LOSING_ARB = 0xb7,
- SCORPIONL2_CPU1_LOSING_ARB = 0xb8,
- SCORPIONL2_SLAVEPORT_NOGRANT = 0xb9,
- SCORPIONL2_SLAVEPORT_BPQ_FULL = 0xba,
- SCORPIONL2_SLAVEPORT_LOSING_ARB = 0xbb,
- SCORPIONL2_SLAVEPORT_GRANT = 0xbc,
- SCORPIONL2_SLAVEPORT_GRANTLOCK = 0xbd,
- SCORPIONL2_L2EM_STREX_PASS = 0xbe,
- SCORPIONL2_L2EM_STREX_FAIL = 0xbf,
- SCORPIONL2_LDREX_RESERVE_L2EM = 0xc0,
- SCORPIONL2_SLAVEPORT_LDREX = 0xc1,
- SCORPIONL2_CPU0_L2EM_CLEARED = 0xc2,
- SCORPIONL2_CPU1_L2EM_CLEARED = 0xc3,
- SCORPIONL2_SLAVEPORT_L2EM_CLEARED = 0xc4,
- SCORPIONL2_CPU0_CLAMPED = 0xc5,
- SCORPIONL2_CPU1_CLAMPED = 0xc6,
- SCORPIONL2_CPU0_WAIT = 0xc7,
- SCORPIONL2_CPU1_WAIT = 0xc8,
- SCORPIONL2_CPU0_NONAMBAS_WAIT = 0xc9,
- SCORPIONL2_CPU1_NONAMBAS_WAIT = 0xca,
- SCORPIONL2_CPU0_DSB_WAIT = 0xcb,
- SCORPIONL2_CPU1_DSB_WAIT = 0xcc,
- SCORPIONL2_AXI_READ = 0xcd,
- SCORPIONL2_AXI_WRITE = 0xce,
-
- SCORPIONL2_1BEAT_WRITE = 0xcf,
- SCORPIONL2_2BEAT_WRITE = 0xd0,
- SCORPIONL2_4BEAT_WRITE = 0xd1,
- SCORPIONL2_8BEAT_WRITE = 0xd2,
- SCORPIONL2_12BEAT_WRITE = 0xd3,
- SCORPIONL2_16BEAT_WRITE = 0xd4,
- SCORPIONL2_1BEAT_DSIDE_READ = 0xd5,
- SCORPIONL2_2BEAT_DSIDE_READ = 0xd6,
- SCORPIONL2_4BEAT_DSIDE_READ = 0xd7,
- SCORPIONL2_8BEAT_DSIDE_READ = 0xd8,
- SCORPIONL2_CSYS_READ_1BEAT = 0xd9,
- SCORPIONL2_CSYS_READ_2BEAT = 0xda,
- SCORPIONL2_CSYS_READ_4BEAT = 0xdb,
- SCORPIONL2_CSYS_READ_8BEAT = 0xdc,
- SCORPIONL2_4BEAT_IFETCH_READ = 0xdd,
- SCORPIONL2_8BEAT_IFETCH_READ = 0xde,
- SCORPIONL2_CSYS_WRITE_1BEAT = 0xdf,
- SCORPIONL2_CSYS_WRITE_2BEAT = 0xe0,
- SCORPIONL2_AXI_READ_DATA_BEAT = 0xe1,
- SCORPIONL2_AXI_WRITE_EVT1 = 0xe2,
- SCORPIONL2_AXI_WRITE_EVT2 = 0xe3,
- SCORPIONL2_LDREX_REQ = 0xe4,
- SCORPIONL2_STREX_PASS = 0xe5,
- SCORPIONL2_STREX_FAIL = 0xe6,
- SCORPIONL2_CPREAD = 0xe7,
- SCORPIONL2_CPWRITE = 0xe8,
- SCORPIONL2_BARRIER_REQ = 0xe9,
- SCORPIONL2_AXI_READ_SLVPORT = 0xea,
- SCORPIONL2_AXI_WRITE_SLVPORT = 0xeb,
- SCORPIONL2_AXI_READ_SLVPORT_DATABEAT = 0xec,
- SCORPIONL2_AXI_WRITE_SLVPORT_DATABEAT = 0xed,
- SCORPIONL2_SNOOPKILL_PREFILTER = 0xee,
- SCORPIONL2_SNOOPKILL_FILTEROUT = 0xef,
- SCORPIONL2_SNOOPED_IC = 0xf0,
- SCORPIONL2_SNOOPED_BP = 0xf1,
- SCORPIONL2_SNOOPED_BARRIERS = 0xf2,
- SCORPIONL2_SNOOPED_TLB = 0xf3,
- BB_L2_MAX_EVT,
-};
-
-static const struct bb_l2_scorp_evt sc_evt[] = {
- {SCORPIONL2_TOTAL_BANK_REQ, 0x80000001, 0, 0x00},
- {SCORPIONL2_DSIDE_READ, 0x80000100, 0, 0x01},
- {SCORPIONL2_DSIDE_WRITE, 0x80010000, 0, 0x02},
- {SCORPIONL2_ISIDE_READ, 0x81000000, 0, 0x03},
- {SCORPIONL2_L2CACHE_ISIDE_READ, 0x80000002, 0, 0x00},
- {SCORPIONL2_L2CACHE_BANK_REQ, 0x80000200, 0, 0x01},
- {SCORPIONL2_L2CACHE_DSIDE_READ, 0x80020000, 0, 0x02},
- {SCORPIONL2_L2CACHE_DSIDE_WRITE, 0x82000000, 0, 0x03},
- {SCORPIONL2_L2NOCACHE_DSIDE_WRITE, 0x80000003, 0, 0x00},
- {SCORPIONL2_L2NOCACHE_ISIDE_READ, 0x80000300, 0, 0x01},
- {SCORPIONL2_L2NOCACHE_TOTAL_REQ, 0x80030000, 0, 0x02},
- {SCORPIONL2_L2NOCACHE_DSIDE_READ, 0x83000000, 0, 0x03},
- {SCORPIONL2_DSIDE_READ_NOL1, 0x80000004, 0, 0x00},
- {SCORPIONL2_L2CACHE_WRITETHROUGH, 0x80000400, 0, 0x01},
- {SCORPIONL2_BARRIERS, 0x84000000, 0, 0x03},
- {SCORPIONL2_HARDWARE_TABLE_WALKS, 0x80000005, 0, 0x00},
- {SCORPIONL2_MVA_POC, 0x80000500, 0, 0x01},
- {SCORPIONL2_L2CACHE_HW_TABLE_WALKS, 0x80050000, 0, 0x02},
- {SCORPIONL2_SETWAY_CACHE_OPS, 0x85000000, 0, 0x03},
- {SCORPIONL2_DSIDE_WRITE_HITS, 0x80000006, 0, 0x00},
- {SCORPIONL2_ISIDE_READ_HITS, 0x80000600, 0, 0x01},
- {SCORPIONL2_CACHE_DSIDE_READ_NOL1, 0x80060000, 0, 0x02},
- {SCORPIONL2_TOTAL_CACHE_HITS, 0x86000000, 0, 0x03},
- {SCORPIONL2_CACHE_MATCH_MISS, 0x80000007, 0, 0x00},
- {SCORPIONL2_DREAD_HIT_L1_DATA, 0x87000000, 0, 0x03},
- {SCORPIONL2_L2LINE_LOCKED, 0x80000008, 0, 0x00},
- {SCORPIONL2_HW_TABLE_WALK_HIT, 0x80000800, 0, 0x01},
- {SCORPIONL2_CACHE_MVA_POC, 0x80080000, 0, 0x02},
- {SCORPIONL2_L2ALLOC_DWRITE_MISS, 0x88000000, 0, 0x03},
- {SCORPIONL2_CORRECTED_TAG_ARRAY, 0x80001A00, 0, 0x01},
- {SCORPIONL2_CORRECTED_DATA_ARRAY, 0x801A0000, 0, 0x02},
- {SCORPIONL2_CORRECTED_REPLACEMENT_ARRAY, 0x9A000000, 0, 0x03},
- {SCORPIONL2_PMBUS_MPAAF, 0x80001C00, 0, 0x01},
- {SCORPIONL2_PMBUS_MPWDAF, 0x801C0000, 0, 0x02},
- {SCORPIONL2_PMBUS_MPBRT, 0x9C000000, 0, 0x03},
-
- {SCORPIONL2_CPU0_GRANT, 0x80000001, 1, 0x04},
- {SCORPIONL2_CPU1_GRANT, 0x80000100, 1, 0x05},
- {SCORPIONL2_CPU0_NOGRANT, 0x80020000, 1, 0x06},
- {SCORPIONL2_CPU1_NOGRANT, 0x82000000, 1, 0x07},
- {SCORPIONL2_CPU0_LOSING_ARB, 0x80040000, 1, 0x06},
- {SCORPIONL2_CPU1_LOSING_ARB, 0x84000000, 1, 0x07},
- {SCORPIONL2_SLAVEPORT_NOGRANT, 0x80000007, 1, 0x04},
- {SCORPIONL2_SLAVEPORT_BPQ_FULL, 0x80000700, 1, 0x05},
- {SCORPIONL2_SLAVEPORT_LOSING_ARB, 0x80070000, 1, 0x06},
- {SCORPIONL2_SLAVEPORT_GRANT, 0x87000000, 1, 0x07},
- {SCORPIONL2_SLAVEPORT_GRANTLOCK, 0x80000008, 1, 0x04},
- {SCORPIONL2_L2EM_STREX_PASS, 0x80000009, 1, 0x04},
- {SCORPIONL2_L2EM_STREX_FAIL, 0x80000900, 1, 0x05},
- {SCORPIONL2_LDREX_RESERVE_L2EM, 0x80090000, 1, 0x06},
- {SCORPIONL2_SLAVEPORT_LDREX, 0x89000000, 1, 0x07},
- {SCORPIONL2_CPU0_L2EM_CLEARED, 0x800A0000, 1, 0x06},
- {SCORPIONL2_CPU1_L2EM_CLEARED, 0x8A000000, 1, 0x07},
- {SCORPIONL2_SLAVEPORT_L2EM_CLEARED, 0x80000B00, 1, 0x05},
- {SCORPIONL2_CPU0_CLAMPED, 0x8000000E, 1, 0x04},
- {SCORPIONL2_CPU1_CLAMPED, 0x80000E00, 1, 0x05},
- {SCORPIONL2_CPU0_WAIT, 0x800F0000, 1, 0x06},
- {SCORPIONL2_CPU1_WAIT, 0x8F000000, 1, 0x07},
- {SCORPIONL2_CPU0_NONAMBAS_WAIT, 0x80000010, 1, 0x04},
- {SCORPIONL2_CPU1_NONAMBAS_WAIT, 0x80001000, 1, 0x05},
- {SCORPIONL2_CPU0_DSB_WAIT, 0x80000014, 1, 0x04},
- {SCORPIONL2_CPU1_DSB_WAIT, 0x80001400, 1, 0x05},
-
- {SCORPIONL2_AXI_READ, 0x80000001, 2, 0x08},
- {SCORPIONL2_AXI_WRITE, 0x80000100, 2, 0x09},
- {SCORPIONL2_1BEAT_WRITE, 0x80010000, 2, 0x0a},
- {SCORPIONL2_2BEAT_WRITE, 0x80010000, 2, 0x0b},
- {SCORPIONL2_4BEAT_WRITE, 0x80000002, 2, 0x08},
- {SCORPIONL2_8BEAT_WRITE, 0x80000200, 2, 0x09},
- {SCORPIONL2_12BEAT_WRITE, 0x80020000, 2, 0x0a},
- {SCORPIONL2_16BEAT_WRITE, 0x82000000, 2, 0x0b},
- {SCORPIONL2_1BEAT_DSIDE_READ, 0x80000003, 2, 0x08},
- {SCORPIONL2_2BEAT_DSIDE_READ, 0x80000300, 2, 0x09},
- {SCORPIONL2_4BEAT_DSIDE_READ, 0x80030000, 2, 0x0a},
- {SCORPIONL2_8BEAT_DSIDE_READ, 0x83000000, 2, 0x0b},
- {SCORPIONL2_CSYS_READ_1BEAT, 0x80000004, 2, 0x08},
- {SCORPIONL2_CSYS_READ_2BEAT, 0x80000400, 2, 0x09},
- {SCORPIONL2_CSYS_READ_4BEAT, 0x80040000, 2, 0x0a},
- {SCORPIONL2_CSYS_READ_8BEAT, 0x84000000, 2, 0x0b},
- {SCORPIONL2_4BEAT_IFETCH_READ, 0x80000005, 2, 0x08},
- {SCORPIONL2_8BEAT_IFETCH_READ, 0x80000500, 2, 0x09},
- {SCORPIONL2_CSYS_WRITE_1BEAT, 0x80050000, 2, 0x0a},
- {SCORPIONL2_CSYS_WRITE_2BEAT, 0x85000000, 2, 0x0b},
- {SCORPIONL2_AXI_READ_DATA_BEAT, 0x80000600, 2, 0x09},
- {SCORPIONL2_AXI_WRITE_EVT1, 0x80060000, 2, 0x0a},
- {SCORPIONL2_AXI_WRITE_EVT2, 0x86000000, 2, 0x0b},
- {SCORPIONL2_LDREX_REQ, 0x80000007, 2, 0x08},
- {SCORPIONL2_STREX_PASS, 0x80000700, 2, 0x09},
- {SCORPIONL2_STREX_FAIL, 0x80070000, 2, 0x0a},
- {SCORPIONL2_CPREAD, 0x80000008, 2, 0x08},
- {SCORPIONL2_CPWRITE, 0x80000800, 2, 0x09},
- {SCORPIONL2_BARRIER_REQ, 0x88000000, 2, 0x0b},
-
- {SCORPIONL2_AXI_READ_SLVPORT, 0x80000001, 3, 0x0c},
- {SCORPIONL2_AXI_WRITE_SLVPORT, 0x80000100, 3, 0x0d},
- {SCORPIONL2_AXI_READ_SLVPORT_DATABEAT, 0x80010000, 3, 0x0e},
- {SCORPIONL2_AXI_WRITE_SLVPORT_DATABEAT, 0x81000000, 3, 0x0f},
-
- {SCORPIONL2_SNOOPKILL_PREFILTER, 0x80000001, 4, 0x10},
- {SCORPIONL2_SNOOPKILL_FILTEROUT, 0x80000100, 4, 0x11},
- {SCORPIONL2_SNOOPED_IC, 0x80000002, 4, 0x10},
- {SCORPIONL2_SNOOPED_BP, 0x80000200, 4, 0x11},
- {SCORPIONL2_SNOOPED_BARRIERS, 0x80020000, 4, 0x12},
- {SCORPIONL2_SNOOPED_TLB, 0x82000000, 4, 0x13},
-};
-
-static u32 bb_l2_read_l2pm0(void)
-{
- u32 val;
- asm volatile ("mrc p15, 3, %0, c15, c7, 0" : "=r" (val));
- return val;
-}
-
-static void bb_l2_write_l2pm0(u32 val)
-{
- asm volatile ("mcr p15, 3, %0, c15, c7, 0" : : "r" (val));
-}
-
-static u32 bb_l2_read_l2pm1(void)
-{
- u32 val;
- asm volatile ("mrc p15, 3, %0, c15, c7, 1" : "=r" (val));
- return val;
-}
-
-static void bb_l2_write_l2pm1(u32 val)
-{
- asm volatile ("mcr p15, 3, %0, c15, c7, 1" : : "r" (val));
-}
-
-static u32 bb_l2_read_l2pm2(void)
-{
- u32 val;
- asm volatile ("mrc p15, 3, %0, c15, c7, 2" : "=r" (val));
- return val;
-}
-
-static void bb_l2_write_l2pm2(u32 val)
-{
- asm volatile ("mcr p15, 3, %0, c15, c7, 2" : : "r" (val));
-}
-
-static u32 bb_l2_read_l2pm3(void)
-{
- u32 val;
- asm volatile ("mrc p15, 3, %0, c15, c7, 3" : "=r" (val));
- return val;
-}
-
-static void bb_l2_write_l2pm3(u32 val)
-{
- asm volatile ("mcr p15, 3, %0, c15, c7, 3" : : "r" (val));
-}
-
-static u32 bb_l2_read_l2pm4(void)
-{
- u32 val;
- asm volatile ("mrc p15, 3, %0, c15, c7, 4" : "=r" (val));
- return val;
-}
-
-static void bb_l2_write_l2pm4(u32 val)
-{
- asm volatile ("mcr p15, 3, %0, c15, c7, 4" : : "r" (val));
-}
-
-struct bb_scorpion_access_funcs {
- u32(*read) (void);
- void (*write) (u32);
- void (*pre) (void);
- void (*post) (void);
-};
-
-struct bb_scorpion_access_funcs bb_l2_func[] = {
- {bb_l2_read_l2pm0, bb_l2_write_l2pm0, NULL, NULL},
- {bb_l2_read_l2pm1, bb_l2_write_l2pm1, NULL, NULL},
- {bb_l2_read_l2pm2, bb_l2_write_l2pm2, NULL, NULL},
- {bb_l2_read_l2pm3, bb_l2_write_l2pm3, NULL, NULL},
- {bb_l2_read_l2pm4, bb_l2_write_l2pm4, NULL, NULL},
-};
-
-#define COLMN0MASK 0x000000ff
-#define COLMN1MASK 0x0000ff00
-#define COLMN2MASK 0x00ff0000
-
-static u32 bb_l2_get_columnmask(u32 setval)
-{
- if (setval & COLMN0MASK)
- return 0xffffff00;
- else if (setval & COLMN1MASK)
- return 0xffff00ff;
- else if (setval & COLMN2MASK)
- return 0xff00ffff;
- else
- return 0x80ffffff;
-}
-
-static void bb_l2_evt_setup(u32 gr, u32 setval)
-{
- u32 val;
- if (bb_l2_func[gr].pre)
- bb_l2_func[gr].pre();
- val = bb_l2_get_columnmask(setval) & bb_l2_func[gr].read();
- val = val | setval;
- bb_l2_func[gr].write(val);
- if (bb_l2_func[gr].post)
- bb_l2_func[gr].post();
-}
-
-#define BB_L2_EVT_START_IDX 0x90
-#define BB_L2_INV_EVTYPE 0
-
-static unsigned int get_bb_l2_evtinfo(unsigned int evt_type,
- struct bb_l2_scorp_evt *evtinfo)
-{
- u32 idx;
- u8 prefix;
- u8 reg;
- u8 code;
- u8 group;
-
- prefix = (evt_type & 0xF0000) >> 16;
- if (prefix == SCORPION_L2_EVT_PREFIX) {
- reg = (evt_type & 0x0F000) >> 12;
- code = (evt_type & 0x00FF0) >> 4;
- group = evt_type & 0x0000F;
-
- if ((group > 3) || (reg > SCORPION_MAX_L2_REG))
- return BB_L2_INV_EVTYPE;
-
- evtinfo->val = 0x80000000 | (code << (group * 8));
- evtinfo->grp = reg;
- evtinfo->evt_type_act = group | (reg << 2);
- return evtinfo->evt_type_act;
- }
-
- if (evt_type < BB_L2_EVT_START_IDX || evt_type >= BB_L2_MAX_EVT)
- return BB_L2_INV_EVTYPE;
- idx = evt_type - BB_L2_EVT_START_IDX;
- if (sc_evt[idx].evt_type == evt_type) {
- evtinfo->val = sc_evt[idx].val;
- evtinfo->grp = sc_evt[idx].grp;
- evtinfo->evt_type_act = sc_evt[idx].evt_type_act;
- return sc_evt[idx].evt_type_act;
- }
- return BB_L2_INV_EVTYPE;
-}
-
-static inline void bb_l2_pmnc_write(unsigned long val)
-{
- val &= 0xff;
- asm volatile ("mcr p15, 3, %0, c15, c4, 0" : : "r" (val));
-}
-
-static inline unsigned long bb_l2_pmnc_read(void)
-{
- u32 val;
- asm volatile ("mrc p15, 3, %0, c15, c4, 0" : "=r" (val));
- return val;
-}
-
-static void bb_l2_set_evcntcr(void)
-{
- u32 val = 0x0;
- asm volatile ("mcr p15, 3, %0, c15, c6, 4" : : "r" (val));
-}
-
-static inline void bb_l2_set_evtyper(int ctr, int val)
-{
- /* select ctr */
- asm volatile ("mcr p15, 3, %0, c15, c6, 0" : : "r" (ctr));
-
- /* write into EVTYPER */
- asm volatile ("mcr p15, 3, %0, c15, c6, 7" : : "r" (val));
-}
-
-static void bb_l2_set_evfilter_task_mode(void)
-{
- u32 filter_val = 0x000f0030 | 1 << smp_processor_id();
-
- asm volatile ("mcr p15, 3, %0, c15, c6, 3" : : "r" (filter_val));
-}
-
-static void bb_l2_set_evfilter_sys_mode(void)
-{
- u32 filter_val = 0x000f003f;
-
- asm volatile ("mcr p15, 3, %0, c15, c6, 3" : : "r" (filter_val));
-}
-
-static void bb_l2_enable_intenset(u32 idx)
-{
- if (idx == BB_L2CYCLE_CTR_EVENT_IDX) {
- asm volatile ("mcr p15, 3, %0, c15, c5, 1" : : "r"
- (1 << BB_L2CYCLE_CTR_BIT));
- } else {
- asm volatile ("mcr p15, 3, %0, c15, c5, 1" : : "r" (1 << idx));
- }
-}
-
-static void bb_l2_disable_intenclr(u32 idx)
-{
- if (idx == BB_L2CYCLE_CTR_EVENT_IDX) {
- asm volatile ("mcr p15, 3, %0, c15, c5, 0" : : "r"
- (1 << BB_L2CYCLE_CTR_BIT));
- } else {
- asm volatile ("mcr p15, 3, %0, c15, c5, 0" : : "r" (1 << idx));
- }
-}
-
-static void bb_l2_enable_counter(u32 idx)
-{
- if (idx == BB_L2CYCLE_CTR_EVENT_IDX) {
- asm volatile ("mcr p15, 3, %0, c15, c4, 3" : : "r"
- (1 << BB_L2CYCLE_CTR_BIT));
- } else {
- asm volatile ("mcr p15, 3, %0, c15, c4, 3" : : "r" (1 << idx));
- }
-}
-
-static void bb_l2_disable_counter(u32 idx)
-{
- if (idx == BB_L2CYCLE_CTR_EVENT_IDX) {
- asm volatile ("mcr p15, 3, %0, c15, c4, 2" : : "r"
- (1 << BB_L2CYCLE_CTR_BIT));
-
- } else {
- asm volatile ("mcr p15, 3, %0, c15, c4, 2" : : "r" (1 << idx));
- }
-}
-
-static u64 bb_l2_read_counter(u32 idx)
-{
- u32 val;
- unsigned long flags;
-
- if (idx == BB_L2CYCLE_CTR_EVENT_IDX) {
- asm volatile ("mrc p15, 3, %0, c15, c4, 5" : "=r" (val));
- } else {
- raw_spin_lock_irqsave(&bb_l2_pmu_lock, flags);
- asm volatile ("mcr p15, 3, %0, c15, c6, 0" : : "r" (idx));
-
- /* read val from counter */
- asm volatile ("mrc p15, 3, %0, c15, c6, 5" : "=r" (val));
- raw_spin_unlock_irqrestore(&bb_l2_pmu_lock, flags);
- }
-
- return val;
-}
-
-static void bb_l2_write_counter(u32 idx, u32 val)
-{
- unsigned long flags;
-
- if (idx == BB_L2CYCLE_CTR_EVENT_IDX) {
- asm volatile ("mcr p15, 3, %0, c15, c4, 5" : : "r" (val));
- } else {
- raw_spin_lock_irqsave(&bb_l2_pmu_lock, flags);
- /* select counter */
- asm volatile ("mcr p15, 3, %0, c15, c6, 0" : : "r" (idx));
-
- /* write val into counter */
- asm volatile ("mcr p15, 3, %0, c15, c6, 5" : : "r" (val));
- raw_spin_unlock_irqrestore(&bb_l2_pmu_lock, flags);
- }
-}
-
-static int
-bb_pmu_event_set_period(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- s64 left = local64_read(&hwc->period_left);
- s64 period = hwc->sample_period;
- int ret = 0;
-
- if (unlikely(left <= -period)) {
- left = period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (unlikely(left <= 0)) {
- left += period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (left > (s64) MAX_BB_L2_PERIOD)
- left = MAX_BB_L2_PERIOD;
-
- local64_set(&hwc->prev_count, (u64)-left);
-
- bb_l2_write_counter(idx, (u64) (-left) & 0xffffffff);
-
- perf_event_update_userpage(event);
-
- return ret;
-}
-
-static u64
-bb_pmu_event_update(struct perf_event *event, struct hw_perf_event *hwc,
- int idx, int overflow)
-{
- u64 prev_raw_count, new_raw_count;
- u64 delta;
-
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = bb_l2_read_counter(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- new_raw_count &= MAX_BB_L2_PERIOD;
- prev_raw_count &= MAX_BB_L2_PERIOD;
-
- if (overflow) {
- delta = MAX_BB_L2_PERIOD - prev_raw_count + new_raw_count;
- pr_err("%s: delta: %lld\n", __func__, delta);
- } else
- delta = new_raw_count - prev_raw_count;
-
- local64_add(delta, &event->count);
- local64_sub(delta, &hwc->period_left);
-
- pr_debug("%s: new: %lld, prev: %lld, event: %ld count: %lld\n",
- __func__, new_raw_count, prev_raw_count,
- hwc->config_base, local64_read(&event->count));
-
- return new_raw_count;
-}
-
-static void bb_l2_read(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
-
- bb_pmu_event_update(event, hwc, hwc->idx, 0);
-}
-
-static void bb_l2_stop_counter(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (!(hwc->state & PERF_HES_STOPPED)) {
- bb_l2_disable_intenclr(idx);
- bb_l2_disable_counter(idx);
-
- bb_pmu_event_update(event, hwc, idx, 0);
- hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
- }
-
- pr_debug("%s: event: %ld ctr: %d stopped\n", __func__, hwc->config_base,
- idx);
-}
-
-static void bb_l2_start_counter(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- struct bb_l2_scorp_evt evtinfo;
- int evtype = hwc->config_base;
- int ev_typer;
- unsigned long iflags;
- int cpu_id = smp_processor_id();
-
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
-
- hwc->state = 0;
-
- bb_pmu_event_set_period(event, hwc, idx);
-
- if (hwc->config_base == BB_L2CYCLE_CTR_RAW_CODE)
- goto out;
-
- memset(&evtinfo, 0, sizeof(evtinfo));
-
- ev_typer = get_bb_l2_evtinfo(evtype, &evtinfo);
-
- raw_spin_lock_irqsave(&bb_l2_pmu_lock, iflags);
-
- bb_l2_set_evtyper(idx, ev_typer);
-
- bb_l2_set_evcntcr();
-
- if (event->cpu < 0)
- bb_l2_set_evfilter_task_mode();
- else
- bb_l2_set_evfilter_sys_mode();
-
- bb_l2_evt_setup(evtinfo.grp, evtinfo.val);
-
- raw_spin_unlock_irqrestore(&bb_l2_pmu_lock, iflags);
-
-out:
-
- bb_l2_enable_intenset(idx);
-
- bb_l2_enable_counter(idx);
-
- pr_debug("%s: idx: %d, event: %d, val: %x, cpu: %d\n",
- __func__, idx, evtype, evtinfo.val, cpu_id);
-}
-
-static void bb_l2_del_event(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- unsigned long iflags;
-
- raw_spin_lock_irqsave(&hw_bb_l2_pmu.lock, iflags);
-
- clear_bit(idx, (long unsigned int *)(&hw_bb_l2_pmu.active_mask));
-
- bb_l2_stop_counter(event, PERF_EF_UPDATE);
- hw_bb_l2_pmu.events[idx] = NULL;
- hwc->idx = -1;
-
- raw_spin_unlock_irqrestore(&hw_bb_l2_pmu.lock, iflags);
-
- pr_debug("%s: event: %ld deleted\n", __func__, hwc->config_base);
-
- perf_event_update_userpage(event);
-}
-
-static int bb_l2_add_event(struct perf_event *event, int flags)
-{
- int ctr = 0;
- struct hw_perf_event *hwc = &event->hw;
- unsigned long iflags;
- int err = 0;
-
- perf_pmu_disable(event->pmu);
-
- raw_spin_lock_irqsave(&hw_bb_l2_pmu.lock, iflags);
-
- /* Cycle counter has a resrvd index */
- if (hwc->config_base == BB_L2CYCLE_CTR_RAW_CODE) {
- if (hw_bb_l2_pmu.events[BB_L2CYCLE_CTR_EVENT_IDX]) {
- pr_err("%s: Stale cycle ctr event ptr !\n", __func__);
- err = -EINVAL;
- goto out;
- }
- hwc->idx = BB_L2CYCLE_CTR_EVENT_IDX;
- hw_bb_l2_pmu.events[BB_L2CYCLE_CTR_EVENT_IDX] = event;
- set_bit(BB_L2CYCLE_CTR_EVENT_IDX,
- (long unsigned int *)&hw_bb_l2_pmu.active_mask);
- goto skip_ctr_loop;
- }
-
- for (ctr = 0; ctr < MAX_BB_L2_CTRS - 1; ctr++) {
- if (!hw_bb_l2_pmu.events[ctr]) {
- hwc->idx = ctr;
- hw_bb_l2_pmu.events[ctr] = event;
- set_bit(ctr, (long unsigned int *)
- &hw_bb_l2_pmu.active_mask);
- break;
- }
- }
-
- if (hwc->idx < 0) {
- err = -ENOSPC;
- pr_err("%s: No space for event: %llx!!\n", __func__,
- event->attr.config);
- goto out;
- }
-
-skip_ctr_loop:
-
- bb_l2_disable_counter(hwc->idx);
-
- hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
-
- if (flags & PERF_EF_START)
- bb_l2_start_counter(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
-
- pr_debug("%s: event: %ld, ctr: %d added from cpu:%d\n",
- __func__, hwc->config_base, hwc->idx, smp_processor_id());
-out:
- raw_spin_unlock_irqrestore(&hw_bb_l2_pmu.lock, iflags);
-
- /* Resume the PMU even if this event could not be added */
- perf_pmu_enable(event->pmu);
-
- return err;
-}
-
-static void bb_l2_pmu_enable(struct pmu *pmu)
-{
- unsigned long flags;
- isb();
- raw_spin_lock_irqsave(&bb_l2_pmu_lock, flags);
- /* Enable all counters */
- bb_l2_pmnc_write(bb_l2_pmnc_read() | SCORPIONL2_PMNC_E);
- raw_spin_unlock_irqrestore(&bb_l2_pmu_lock, flags);
-}
-
-static void bb_l2_pmu_disable(struct pmu *pmu)
-{
- unsigned long flags;
- raw_spin_lock_irqsave(&bb_l2_pmu_lock, flags);
- /* Disable all counters */
- bb_l2_pmnc_write(bb_l2_pmnc_read() & ~SCORPIONL2_PMNC_E);
- raw_spin_unlock_irqrestore(&bb_l2_pmu_lock, flags);
- isb();
-}
-
-static inline u32 bb_l2_get_reset_pmovsr(void)
-{
- u32 val;
-
- /* Read */
- asm volatile ("mrc p15, 3, %0, c15, c4, 1" : "=r" (val));
-
- /* Write to clear flags */
- val &= 0xffffffff;
- asm volatile ("mcr p15, 3, %0, c15, c4, 1" : : "r" (val));
-
- return val;
-}
-
-static irqreturn_t bb_l2_handle_irq(int irq_num, void *dev)
-{
- unsigned long pmovsr;
- struct perf_sample_data data;
- struct pt_regs *regs;
- struct perf_event *event;
- struct hw_perf_event *hwc;
- int bitp;
- int idx = 0;
-
- pmovsr = bb_l2_get_reset_pmovsr();
-
- if (!(pmovsr & 0xffffffff))
- return IRQ_NONE;
-
- regs = get_irq_regs();
-
- perf_sample_data_init(&data, 0);
-
- raw_spin_lock(&hw_bb_l2_pmu.lock);
-
- while (pmovsr) {
- bitp = __ffs(pmovsr);
-
- if (bitp == BB_L2CYCLE_CTR_BIT)
- idx = BB_L2CYCLE_CTR_EVENT_IDX;
- else
- idx = bitp;
-
- event = hw_bb_l2_pmu.events[idx];
-
- if (!event)
- goto next;
-
- if (!test_bit(idx, hw_bb_l2_pmu.active_mask))
- goto next;
-
- hwc = &event->hw;
- bb_pmu_event_update(event, hwc, idx, 1);
- data.period = event->hw.last_period;
-
- if (!bb_pmu_event_set_period(event, hwc, idx))
- goto next;
-
- if (perf_event_overflow(event, 0, &data, regs))
- bb_l2_disable_counter(hwc->idx);
-next:
- pmovsr &= (pmovsr - 1);
- }
-
- raw_spin_unlock(&hw_bb_l2_pmu.lock);
-
- irq_work_run();
-
- return IRQ_HANDLED;
-}
-
-static atomic_t active_bb_l2_events = ATOMIC_INIT(0);
-static DEFINE_MUTEX(bb_pmu_reserve_mutex);
-
-static int bb_pmu_reserve_hardware(void)
-{
- int i, err = -ENODEV, irq;
-
- bb_l2_pmu_device = reserve_pmu(ARM_PMU_DEVICE_L2);
-
- if (IS_ERR(bb_l2_pmu_device)) {
- pr_warning("unable to reserve pmu\n");
- return PTR_ERR(bb_l2_pmu_device);
- }
-
- if (bb_l2_pmu_device->num_resources < 1) {
- pr_err("no irqs for PMUs defined\n");
- return -ENODEV;
- }
-
- if (strncmp(bb_l2_pmu_device->name, "l2-arm-pmu", 6)) {
- pr_err("Incorrect pdev reserved !\n");
- return -EINVAL;
- }
-
- for (i = 0; i < bb_l2_pmu_device->num_resources; ++i) {
- irq = platform_get_irq(bb_l2_pmu_device, i);
- if (irq < 0)
- continue;
-
- err = request_irq(irq, bb_l2_handle_irq,
- IRQF_DISABLED | IRQF_NOBALANCING,
- "bb-l2-pmu", NULL);
- if (err) {
- pr_warning("unable to request IRQ%d for Krait L2 perf "
- "counters\n", irq);
- break;
- }
-
- irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
- }
-
- if (err) {
- for (i = i - 1; i >= 0; --i) {
- irq = platform_get_irq(bb_l2_pmu_device, i);
- if (irq >= 0)
- free_irq(irq, NULL);
- }
- release_pmu(bb_l2_pmu_device);
- bb_l2_pmu_device = NULL;
- }
-
- return err;
-}
-
-static void bb_pmu_release_hardware(void)
-{
- int i, irq;
-
- for (i = bb_l2_pmu_device->num_resources - 1; i >= 0; --i) {
- irq = platform_get_irq(bb_l2_pmu_device, i);
- if (irq >= 0)
- free_irq(irq, NULL);
- }
-
- bb_l2_pmu_disable(NULL);
-
- release_pmu(bb_l2_pmu_device);
- bb_l2_pmu_device = NULL;
-}
-
-static void bb_pmu_perf_event_destroy(struct perf_event *event)
-{
- if (atomic_dec_and_mutex_lock
- (&active_bb_l2_events, &bb_pmu_reserve_mutex)) {
- bb_pmu_release_hardware();
- mutex_unlock(&bb_pmu_reserve_mutex);
- }
-}
-
-static int bb_l2_event_init(struct perf_event *event)
-{
- int err = 0;
- struct hw_perf_event *hwc = &event->hw;
- int status = 0;
-
- switch (event->attr.type) {
- case PERF_TYPE_SHARED:
- break;
-
- default:
- return -ENOENT;
- }
-
- hwc->idx = -1;
-
- event->destroy = bb_pmu_perf_event_destroy;
-
- if (!atomic_inc_not_zero(&active_bb_l2_events)) {
- /* 0 active events */
- mutex_lock(&bb_pmu_reserve_mutex);
- err = bb_pmu_reserve_hardware();
- mutex_unlock(&bb_pmu_reserve_mutex);
- if (!err)
- atomic_inc(&active_bb_l2_events);
- else
- return err;
- }
-
- hwc->config = 0;
- hwc->event_base = 0;
-
- /* Check if we came via perf default syms */
- if (event->attr.config == PERF_COUNT_HW_L2_CYCLES)
- hwc->config_base = BB_L2CYCLE_CTR_RAW_CODE;
- else
- hwc->config_base = event->attr.config;
-
- /* Only one CPU can control the cycle counter */
- if (hwc->config_base == BB_L2CYCLE_CTR_RAW_CODE) {
- /* Check if its already running */
- asm volatile ("mrc p15, 3, %0, c15, c4, 6" : "=r" (status));
- if (status == 0x2) {
- err = -ENOSPC;
- goto out;
- }
- }
-
- if (!hwc->sample_period) {
- hwc->sample_period = MAX_BB_L2_PERIOD;
- hwc->last_period = hwc->sample_period;
- local64_set(&hwc->period_left, hwc->sample_period);
- }
-
- pr_debug("%s: event: %lld init'd\n", __func__, event->attr.config);
-
-out:
- if (err < 0)
- bb_pmu_perf_event_destroy(event);
-
- return err;
-}
-
-static struct pmu bb_l2_pmu = {
- .pmu_enable = bb_l2_pmu_enable,
- .pmu_disable = bb_l2_pmu_disable,
- .event_init = bb_l2_event_init,
- .add = bb_l2_add_event,
- .del = bb_l2_del_event,
- .start = bb_l2_start_counter,
- .stop = bb_l2_stop_counter,
- .read = bb_l2_read,
-};
-
-static const struct arm_pmu *__init scorpionmp_l2_pmu_init(void)
-{
- /* Register our own PMU here */
- perf_pmu_register(&bb_l2_pmu, "BB L2", PERF_TYPE_SHARED);
-
- memset(&hw_bb_l2_pmu, 0, sizeof(hw_bb_l2_pmu));
-
- /* Avoid spurious interrupts at startup */
- bb_l2_get_reset_pmovsr();
-
- raw_spin_lock_init(&hw_bb_l2_pmu.lock);
-
- /* Don't return an arm_pmu here */
- return NULL;
-}
-#else
-
-static const struct arm_pmu *__init scorpionmp_l2_pmu_init(void)
-{
- return NULL;
-}
-
-#endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 6034fe9..1896059 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -25,7 +25,8 @@
obj-y += acpuclock.o
obj-$(CONFIG_ARCH_MSM7X27) += acpuclock-7627.o clock-pll.o
obj-$(CONFIG_ARCH_MSM_SCORPION) += pmu.o
-obj-$(CONFIG_ARCH_MSM_KRAIT) += msm-krait-l2-accessors.o pmu.o
+obj-$(CONFIG_ARCH_MSM_SCORPIONMP) += perf_event_msm_l2.o
+obj-$(CONFIG_ARCH_MSM_KRAIT) += msm-krait-l2-accessors.o pmu.o perf_event_msm_krait_l2.o
obj-$(CONFIG_ARCH_MSM7X27A) += pmu.o
ifndef CONFIG_MSM_SMP
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index a58eb6e..afa98c1 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -660,7 +660,7 @@
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1212500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
{ 0, { 0 } }
};
@@ -687,7 +687,7 @@
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1175000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },
{ 0, { 0 } }
};
@@ -715,27 +715,80 @@
};
/* TODO: Update core voltages when data is available. */
-static struct acpu_level acpu_freq_tbl_8930[] = {
- { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 925000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 925000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 937500 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 962500 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 987500 },
+static struct acpu_level acpu_freq_tbl_8930_slow[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
+ { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
+ { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
{ 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1037500 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1062500 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1087500 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1075000 },
{ 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1125000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(16), 1137500 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(16), 1162500 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1187500 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1200000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1225000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(11), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(11), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1237500 },
{ 0, { 0 } }
};
+static struct acpu_level acpu_freq_tbl_8930_nom[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 925000 },
+ { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 950000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 950000 },
+ { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 975000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 975000 },
+ { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1000000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1000000 },
+ { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1050000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1050000 },
+ { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1075000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1075000 },
+ { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(11), 1100000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(11), 1100000 },
+ { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1150000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1150000 },
+ { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1175000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1175000 },
+ { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1200000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1200000 },
+ { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1212500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8930_fast[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
+ { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 900000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 900000 },
+ { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 925000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 925000 },
+ { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 950000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 950000 },
+ { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1000000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1000000 },
+ { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1025000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1025000 },
+ { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(11), 1050000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(11), 1050000 },
+ { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1100000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1100000 },
+ { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1125000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1125000 },
+ { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1150000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1150000 },
+ { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1162500 },
+ { 0, { 0 } }
+};
/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
#undef L2
#define L2(x) (&l2_freq_tbl_8627[(x)])
@@ -793,6 +846,12 @@
[PVS_FASTER] = acpu_freq_tbl_8064_fast,
};
+static struct acpu_level *acpu_freq_tbl_8930_pvs[NUM_PVS] __initdata = {
+ [PVS_SLOW] = acpu_freq_tbl_8930_slow,
+ [PVS_NOM] = acpu_freq_tbl_8930_nom,
+ [PVS_FAST] = acpu_freq_tbl_8930_fast,
+};
+
static unsigned long acpuclk_8960_get_rate(int cpu)
{
return scalable[cpu].current_speed->khz;
@@ -1560,8 +1619,10 @@
l2_freq_tbl = l2_freq_tbl_8627;
l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_8627);
} else if (cpu_is_msm8930()) {
+ enum pvs pvs_id = get_pvs();
+
scalable = scalable_8930;
- acpu_freq_tbl = acpu_freq_tbl_8930;
+ acpu_freq_tbl = acpu_freq_tbl_8930_pvs[pvs_id];
l2_freq_tbl = l2_freq_tbl_8930;
l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_8930);
} else {
diff --git a/arch/arm/mach-msm/board-8064-regulator.c b/arch/arm/mach-msm/board-8064-regulator.c
index f7d5403..622b213 100644
--- a/arch/arm/mach-msm/board-8064-regulator.c
+++ b/arch/arm/mach-msm/board-8064-regulator.c
@@ -560,7 +560,7 @@
RPM_SMPS(S2, 0, 1, 0, 1300000, 1300000, NULL, 0, 1p60, NONE, NONE),
RPM_SMPS(S3, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80, NONE, NONE),
RPM_SMPS(S4, 1, 1, 0, 1800000, 1800000, NULL, 100000, 1p60, AUTO, AUTO),
- RPM_SMPS(S7, 0, 1, 0, 1300000, 1300000, NULL, 100000, 3p20, NONE, NONE),
+ RPM_SMPS(S7, 0, 0, 0, 1300000, 1300000, NULL, 100000, 3p20, NONE, NONE),
RPM_SMPS(S8, 0, 1, 0, 2200000, 2200000, NULL, 0, 1p60, NONE, NONE),
/* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
@@ -586,7 +586,7 @@
RPM_LDO(L23, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
RPM_LDO(L24, 0, 1, 1, 750000, 1150000, "8921_s1", 10000, 10000),
RPM_LDO(L25, 1, 1, 0, 1250000, 1250000, "8921_s1", 10000, 10000),
- RPM_LDO(L27, 0, 1, 0, 1100000, 1100000, "8921_s7", 0, 0),
+ RPM_LDO(L27, 0, 0, 0, 1100000, 1100000, "8921_s7", 0, 0),
RPM_LDO(L28, 0, 1, 0, 1050000, 1050000, "8921_s7", 0, 0),
RPM_LDO(L29, 0, 1, 0, 2000000, 2000000, NULL, 0, 0),
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 1521a6c..dc473e6 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -162,7 +162,7 @@
#define MSM_PMEM_MDP_SIZE 0x2300000
#define MSM7x25A_MSM_PMEM_MDP_SIZE 0x1500000
-#define MSM_PMEM_ADSP_SIZE 0x1100000
+#define MSM_PMEM_ADSP_SIZE 0x1200000
#define MSM7x25A_MSM_PMEM_ADSP_SIZE 0xB91000
#endif
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 010d9ec..96d8b17 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -105,7 +105,7 @@
*/
#define MSM_V4L2_VIDEO_OVERLAY_BUF_SIZE 2764800
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
+#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL
#define MSM_FB_EXT_BUF_SIZE (1280 * 720 * 2 * 1) /* 2 bpp x 1 page */
#else
#define MSM_FB_EXT_BUF_SIZE 0
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index d8d8934..9c80c8b 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -130,7 +130,7 @@
#ifdef CONFIG_ARCH_MSM7X27A
#define MSM_PMEM_MDP_SIZE 0x2300000
-#define MSM_PMEM_ADSP_SIZE 0x1100000
+#define MSM_PMEM_ADSP_SIZE 0x1200000
#endif
static struct android_usb_platform_data android_usb_pdata = {
diff --git a/arch/arm/mach-msm/clock-local2.c b/arch/arm/mach-msm/clock-local2.c
index 467d5d1..9fe9591 100644
--- a/arch/arm/mach-msm/clock-local2.c
+++ b/arch/arm/mach-msm/clock-local2.c
@@ -408,6 +408,19 @@
return -EPERM;
}
+static long branch_clk_round_rate(struct clk *c, unsigned long rate)
+{
+ struct branch_clk *branch = to_branch_clk(c);
+
+ if (branch->max_div)
+ return rate <= (branch->max_div) ? rate : -EPERM;
+
+ if (!branch->has_sibling)
+ return clk_round_rate(branch->parent, rate);
+
+ return -EPERM;
+}
+
static unsigned long branch_clk_get_rate(struct clk *c)
{
struct branch_clk *branch = to_branch_clk(c);
@@ -580,6 +593,7 @@
.set_rate = branch_clk_set_rate,
.get_rate = branch_clk_get_rate,
.list_rate = branch_clk_list_rate,
+ .round_rate = branch_clk_round_rate,
.reset = branch_clk_reset,
.get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 63534a4..0fa1e2d 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -19,6 +19,7 @@
#include <linux/earlysuspend.h>
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/cpufreq.h>
#include <linux/workqueue.h>
#include <linux/completion.h>
@@ -27,6 +28,7 @@
#include <linux/sched.h>
#include <linux/suspend.h>
#include <mach/socinfo.h>
+#include <mach/cpufreq.h>
#include "acpuclock.h"
@@ -50,10 +52,33 @@
static DEFINE_PER_CPU(struct cpufreq_suspend_t, cpufreq_suspend);
+struct cpu_freq {
+ uint32_t max;
+ uint32_t min;
+ uint32_t allowed_max;
+ uint32_t allowed_min;
+ uint32_t limits_init;
+};
+
+static DEFINE_PER_CPU(struct cpu_freq, cpu_freq_info);
+
static int set_cpu_freq(struct cpufreq_policy *policy, unsigned int new_freq)
{
int ret = 0;
struct cpufreq_freqs freqs;
+ struct cpu_freq *limit = &per_cpu(cpu_freq_info, policy->cpu);
+
+ if (limit->limits_init) {
+ if (new_freq > limit->allowed_max) {
+ new_freq = limit->allowed_max;
+ pr_debug("max: limiting freq to %d\n", new_freq);
+ }
+
+ if (new_freq < limit->allowed_min) {
+ new_freq = limit->allowed_min;
+ pr_debug("min: limiting freq to %d\n", new_freq);
+ }
+ }
freqs.old = policy->cur;
freqs.new = new_freq;
@@ -158,6 +183,72 @@
return 0;
}
+static unsigned int msm_cpufreq_get_freq(unsigned int cpu)
+{
+ return acpuclk_get_rate(cpu);
+}
+
+static inline int msm_cpufreq_limits_init(void)
+{
+ int cpu = 0;
+ int i = 0;
+ struct cpufreq_frequency_table *table = NULL;
+ uint32_t min = (uint32_t) -1;
+ uint32_t max = 0;
+ struct cpu_freq *limit = NULL;
+
+ for_each_possible_cpu(cpu) {
+ limit = &per_cpu(cpu_freq_info, cpu);
+ table = cpufreq_frequency_get_table(cpu);
+ if (table == NULL) {
+ pr_err("%s: error reading cpufreq table for cpu %d\n",
+ __func__, cpu);
+ continue;
+ }
+ for (i = 0; (table[i].frequency != CPUFREQ_TABLE_END); i++) {
+ if (table[i].frequency > max)
+ max = table[i].frequency;
+ if (table[i].frequency < min)
+ min = table[i].frequency;
+ }
+ limit->allowed_min = min;
+ limit->allowed_max = max;
+ limit->min = min;
+ limit->max = max;
+ limit->limits_init = 1;
+ }
+
+ return 0;
+}
+
+int msm_cpufreq_set_freq_limits(uint32_t cpu, uint32_t min, uint32_t max)
+{
+ struct cpu_freq *limit = &per_cpu(cpu_freq_info, cpu);
+
+ if (!limit->limits_init)
+ msm_cpufreq_limits_init();
+
+ if ((min != MSM_CPUFREQ_NO_LIMIT) &&
+ min >= limit->min && min <= limit->max)
+ limit->allowed_min = min;
+ else
+ limit->allowed_min = limit->min;
+
+
+ if ((max != MSM_CPUFREQ_NO_LIMIT) &&
+ max <= limit->max && max >= limit->min)
+ limit->allowed_max = max;
+ else
+ limit->allowed_max = limit->max;
+
+ pr_debug("%s: Limiting cpu %d min = %d, max = %d\n",
+ __func__, cpu,
+ limit->allowed_min, limit->allowed_max);
+
+ return 0;
+}
+EXPORT_SYMBOL(msm_cpufreq_set_freq_limits);
+
static int __cpuinit msm_cpufreq_init(struct cpufreq_policy *policy)
{
int cur_freq;
@@ -274,6 +365,7 @@
.init = msm_cpufreq_init,
.verify = msm_cpufreq_verify,
.target = msm_cpufreq_target,
+ .get = msm_cpufreq_get_freq,
.name = "msm",
.attr = msm_freq_attr,
};
@@ -300,4 +392,3 @@
}
late_initcall(msm_cpufreq_register);
-
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 09e30c1..66ce30e 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -1061,6 +1061,59 @@
},
};
+static struct msm_bus_vectors vidc_venc_1080p_turbo_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_ENC,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 222298112,
+ .ib = 3522000000U,
+ },
+ {
+ .src = MSM_BUS_MASTER_VIDEO_DEC,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 330301440,
+ .ib = 3522000000U,
+ },
+ {
+ .src = MSM_BUS_MASTER_AMPSS_M0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2500000,
+ .ib = 700000000,
+ },
+ {
+ .src = MSM_BUS_MASTER_AMPSS_M0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2500000,
+ .ib = 10000000,
+ },
+};
+static struct msm_bus_vectors vidc_vdec_1080p_turbo_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_ENC,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 222298112,
+ .ib = 3522000000U,
+ },
+ {
+ .src = MSM_BUS_MASTER_VIDEO_DEC,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 330301440,
+ .ib = 3522000000U,
+ },
+ {
+ .src = MSM_BUS_MASTER_AMPSS_M0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2500000,
+ .ib = 700000000,
+ },
+ {
+ .src = MSM_BUS_MASTER_AMPSS_M0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2500000,
+ .ib = 10000000,
+ },
+};
+
static struct msm_bus_paths vidc_bus_client_config[] = {
{
ARRAY_SIZE(vidc_init_vectors),
@@ -1090,6 +1143,14 @@
ARRAY_SIZE(vidc_vdec_1080p_vectors),
vidc_vdec_1080p_vectors,
},
+ {
+ ARRAY_SIZE(vidc_venc_1080p_turbo_vectors),
+ vidc_venc_1080p_turbo_vectors,
+ },
+ {
+ ARRAY_SIZE(vidc_vdec_1080p_turbo_vectors),
+ vidc_vdec_1080p_turbo_vectors,
+ },
};
static struct msm_bus_scale_pdata vidc_bus_client_data = {
diff --git a/arch/arm/mach-msm/include/mach/cpufreq.h b/arch/arm/mach-msm/include/mach/cpufreq.h
new file mode 100644
index 0000000..8c2be11
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/cpufreq.h
@@ -0,0 +1,42 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_MACH_CPUFREQ_H
+#define __ARCH_ARM_MACH_MSM_MACH_CPUFREQ_H
+
+#define MSM_CPUFREQ_NO_LIMIT 0xFFFFFFFF
+
+#ifdef CONFIG_CPU_FREQ_MSM
+
+/**
+ * msm_cpufreq_set_freq_limit() - Set max/min freq limits on cpu
+ *
+ * @cpu: The cpu core for which the limits apply
+ * @max: The max frequency allowed
+ * @min: The min frequency allowed
+ *
+ * If the @max or @min is set to MSM_CPUFREQ_NO_LIMIT, the limit
+ * will default to the CPUFreq limit.
+ *
+ * returns 0 on success, errno on failure
+ */
+extern int msm_cpufreq_set_freq_limits(
+ uint32_t cpu, uint32_t min, uint32_t max);
+#else
+static inline int msm_cpufreq_set_freq_limits(
+ uint32_t cpu, uint32_t min, uint32_t max)
+{
+ return -ENOSYS;
+}
+#endif
+
+#endif /* __ARCH_ARM_MACH_MSM_MACH_CPUFREQ_H */
diff --git a/arch/arm/mach-msm/perf_event_msm_krait_l2.c b/arch/arm/mach-msm/perf_event_msm_krait_l2.c
new file mode 100644
index 0000000..d82f4dd
--- /dev/null
+++ b/arch/arm/mach-msm/perf_event_msm_krait_l2.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2011, 2012 Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/irq.h>
+#include <asm/pmu.h>
+#include <linux/platform_device.h>
+
+#include <mach/msm-krait-l2-accessors.h>
+
+#define MAX_L2_PERIOD ((1ULL << 32) - 1)
+#define MAX_KRAIT_L2_CTRS 5
+
+#define L2PMCCNTR 0x409
+#define L2PMCCNTCR 0x408
+#define L2PMCCNTSR 0x40A
+#define L2CYCLE_CTR_BIT 31
+#define L2CYCLE_CTR_EVENT_IDX 4
+#define L2CYCLE_CTR_RAW_CODE 0xfe
+
+#define L2PMOVSR 0x406
+
+#define L2PMCR 0x400
+#define L2PMCR_RESET_ALL 0x6
+#define L2PMCR_GLOBAL_ENABLE 0x1
+#define L2PMCR_GLOBAL_DISABLE 0x0
+
+#define L2PMCNTENSET 0x403
+#define L2PMCNTENCLR 0x402
+
+#define L2PMINTENSET 0x405
+#define L2PMINTENCLR 0x404
+
+#define IA_L2PMXEVCNTCR_BASE 0x420
+#define IA_L2PMXEVTYPER_BASE 0x424
+#define IA_L2PMRESX_BASE 0x410
+#define IA_L2PMXEVFILTER_BASE 0x423
+#define IA_L2PMXEVCNTR_BASE 0x421
+
+/* event format is -e rsRCCG See get_event_desc() */
+
+#define EVENT_REG_MASK 0xf000
+#define EVENT_GROUPSEL_MASK 0x000f
+#define EVENT_GROUPCODE_MASK 0x0ff0
+#define EVENT_REG_SHIFT 12
+#define EVENT_GROUPCODE_SHIFT 4
+
+#define RESRX_VALUE_EN 0x80000000
+
+static u32 l2_orig_filter_prefix = 0x000f0030;
+
+static u32 pmu_type;
+
+static struct arm_pmu krait_l2_pmu;
+
+static struct perf_event *l2_events[MAX_KRAIT_L2_CTRS];
+static unsigned long l2_used_mask[BITS_TO_LONGS(MAX_KRAIT_L2_CTRS)];
+
+static struct pmu_hw_events krait_l2_pmu_hw_events = {
+ .events = l2_events,
+ .used_mask = l2_used_mask,
+ .pmu_lock = __RAW_SPIN_LOCK_UNLOCKED(krait_l2_pmu_hw_events.pmu_lock),
+};
+
+struct event_desc {
+ int event_groupsel;
+ int event_reg;
+ int event_group_code;
+};
+
+static struct pmu_hw_events *krait_l2_get_hw_events(void)
+{
+ return &krait_l2_pmu_hw_events;
+}
+
+void get_event_desc(u64 config, struct event_desc *evdesc)
+{
+ /* L2PMEVCNTRX */
+ evdesc->event_reg = (config & EVENT_REG_MASK) >> EVENT_REG_SHIFT;
+ /* Group code (row ) */
+ evdesc->event_group_code =
+ (config & EVENT_GROUPCODE_MASK) >> EVENT_GROUPCODE_SHIFT;
+ /* Group sel (col) */
+ evdesc->event_groupsel = (config & EVENT_GROUPSEL_MASK);
+
+ pr_debug("%s: reg: %x, group_code: %x, groupsel: %x\n", __func__,
+ evdesc->event_reg, evdesc->event_group_code,
+ evdesc->event_groupsel);
+}
+
+static void set_evcntcr(int ctr)
+{
+ u32 evtcr_reg = (ctr * 16) + IA_L2PMXEVCNTCR_BASE;
+
+ set_l2_indirect_reg(evtcr_reg, 0x0);
+}
+
+static void set_evtyper(int event_groupsel, int event_reg, int ctr)
+{
+ u32 evtype_reg = (ctr * 16) + IA_L2PMXEVTYPER_BASE;
+ u32 evtype_val = event_groupsel + (4 * event_reg);
+
+ set_l2_indirect_reg(evtype_reg, evtype_val);
+}
+
+static void set_evres(int event_groupsel, int event_reg, int event_group_code)
+{
+ u32 group_reg = event_reg + IA_L2PMRESX_BASE;
+ u32 group_val =
+ RESRX_VALUE_EN | (event_group_code << (8 * event_groupsel));
+ u32 resr_val;
+ u32 group_byte = 0xff;
+ u32 group_mask = ~(group_byte << (8 * event_groupsel));
+
+ resr_val = get_l2_indirect_reg(group_reg);
+ resr_val &= group_mask;
+ resr_val |= group_val;
+
+ set_l2_indirect_reg(group_reg, resr_val);
+}
+
+static void set_evfilter_task_mode(int ctr)
+{
+ u32 filter_reg = (ctr * 16) + IA_L2PMXEVFILTER_BASE;
+ u32 filter_val = l2_orig_filter_prefix | 1 << smp_processor_id();
+
+ set_l2_indirect_reg(filter_reg, filter_val);
+}
+
+static void set_evfilter_sys_mode(int ctr)
+{
+ u32 filter_reg = (ctr * 16) + IA_L2PMXEVFILTER_BASE;
+ u32 filter_val = l2_orig_filter_prefix | 0xf;
+
+ set_l2_indirect_reg(filter_reg, filter_val);
+}
+
+static void enable_intenset(u32 idx)
+{
+ if (idx == L2CYCLE_CTR_EVENT_IDX)
+ set_l2_indirect_reg(L2PMINTENSET, 1 << L2CYCLE_CTR_BIT);
+ else
+ set_l2_indirect_reg(L2PMINTENSET, 1 << idx);
+}
+
+static void disable_intenclr(u32 idx)
+{
+ if (idx == L2CYCLE_CTR_EVENT_IDX)
+ set_l2_indirect_reg(L2PMINTENCLR, 1 << L2CYCLE_CTR_BIT);
+ else
+ set_l2_indirect_reg(L2PMINTENCLR, 1 << idx);
+}
+
+static void enable_counter(u32 idx)
+{
+ if (idx == L2CYCLE_CTR_EVENT_IDX)
+ set_l2_indirect_reg(L2PMCNTENSET, 1 << L2CYCLE_CTR_BIT);
+ else
+ set_l2_indirect_reg(L2PMCNTENSET, 1 << idx);
+}
+
+static void disable_counter(u32 idx)
+{
+ if (idx == L2CYCLE_CTR_EVENT_IDX)
+ set_l2_indirect_reg(L2PMCNTENCLR, 1 << L2CYCLE_CTR_BIT);
+ else
+ set_l2_indirect_reg(L2PMCNTENCLR, 1 << idx);
+}
+
+static u32 krait_l2_read_counter(int idx)
+{
+ u32 val;
+ u32 counter_reg = (idx * 16) + IA_L2PMXEVCNTR_BASE;
+
+ if (idx == L2CYCLE_CTR_EVENT_IDX)
+ val = get_l2_indirect_reg(L2PMCCNTR);
+ else
+ val = get_l2_indirect_reg(counter_reg);
+
+ return val;
+}
+
+static void krait_l2_write_counter(int idx, u32 val)
+{
+ u32 counter_reg = (idx * 16) + IA_L2PMXEVCNTR_BASE;
+
+ if (idx == L2CYCLE_CTR_EVENT_IDX)
+ set_l2_indirect_reg(L2PMCCNTR, val);
+ else
+ set_l2_indirect_reg(counter_reg, val);
+}
+
+static void krait_l2_stop_counter(struct hw_perf_event *hwc, int idx)
+{
+ disable_intenclr(idx);
+ disable_counter(idx);
+
+ pr_debug("%s: event: %ld ctr: %d stopped\n", __func__,
+ hwc->config_base, idx);
+}
+
+static void krait_l2_enable(struct hw_perf_event *hwc, int idx, int cpu)
+{
+ struct event_desc evdesc;
+ unsigned long iflags;
+
+ raw_spin_lock_irqsave(&krait_l2_pmu_hw_events.pmu_lock, iflags);
+
+ if (hwc->config_base == L2CYCLE_CTR_RAW_CODE)
+ goto out;
+
+ set_evcntcr(idx);
+
+ memset(&evdesc, 0, sizeof(evdesc));
+
+ get_event_desc(hwc->config_base, &evdesc);
+
+ set_evtyper(evdesc.event_groupsel, evdesc.event_reg, idx);
+
+ set_evres(evdesc.event_groupsel, evdesc.event_reg,
+ evdesc.event_group_code);
+
+ if (cpu < 0)
+ set_evfilter_task_mode(idx);
+ else
+ set_evfilter_sys_mode(idx);
+
+out:
+ enable_intenset(idx);
+ enable_counter(idx);
+
+ raw_spin_unlock_irqrestore(&krait_l2_pmu_hw_events.pmu_lock, iflags);
+
+ pr_debug("%s: ctr: %d group: %ld group_code: %lld started from cpu:%d\n",
+ __func__, idx, hwc->config_base, hwc->config, smp_processor_id());
+}
+
+static void krait_l2_disable(struct hw_perf_event *hwc, int idx)
+{
+ unsigned long iflags;
+
+ raw_spin_lock_irqsave(&krait_l2_pmu_hw_events.pmu_lock, iflags);
+
+ krait_l2_stop_counter(hwc, idx);
+
+ raw_spin_unlock_irqrestore(&krait_l2_pmu_hw_events.pmu_lock, iflags);
+
+ pr_debug("%s: event: %ld deleted\n", __func__, hwc->config_base);
+
+}
+
+static int krait_l2_get_event_idx(struct pmu_hw_events *cpuc,
+ struct hw_perf_event *hwc)
+{
+ int ctr = 0;
+
+ if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
+ if (!test_and_set_bit(L2CYCLE_CTR_EVENT_IDX, cpuc->used_mask))
+ return L2CYCLE_CTR_EVENT_IDX;
+ }
+
+ for (ctr = 0; ctr < MAX_KRAIT_L2_CTRS - 1; ctr++) {
+ if (!test_and_set_bit(ctr, cpuc->used_mask))
+ return ctr;
+ }
+
+ return -EAGAIN;
+}
+
+static void krait_l2_start(void)
+{
+ isb();
+ set_l2_indirect_reg(L2PMCR, L2PMCR_GLOBAL_ENABLE);
+}
+
+static void krait_l2_stop(void)
+{
+ set_l2_indirect_reg(L2PMCR, L2PMCR_GLOBAL_DISABLE);
+ isb();
+}
+
+u32 get_reset_pmovsr(void)
+{
+ int val;
+
+ val = get_l2_indirect_reg(L2PMOVSR);
+ /* reset it */
+ val &= 0xffffffff;
+ set_l2_indirect_reg(L2PMOVSR, val);
+
+ return val;
+}
+
+static irqreturn_t krait_l2_handle_irq(int irq_num, void *dev)
+{
+ unsigned long pmovsr;
+ struct perf_sample_data data;
+ struct pt_regs *regs;
+ struct perf_event *event;
+ struct hw_perf_event *hwc;
+ int bitp;
+ int idx = 0;
+
+ pmovsr = get_reset_pmovsr();
+
+ if (!(pmovsr & 0xffffffff))
+ return IRQ_NONE;
+
+ regs = get_irq_regs();
+
+ perf_sample_data_init(&data, 0);
+
+ while (pmovsr) {
+ bitp = __ffs(pmovsr);
+
+ if (bitp == L2CYCLE_CTR_BIT)
+ idx = L2CYCLE_CTR_EVENT_IDX;
+ else
+ idx = bitp;
+
+ event = krait_l2_pmu_hw_events.events[idx];
+
+ if (!event)
+ goto next;
+
+ if (!test_bit(idx, krait_l2_pmu_hw_events.used_mask))
+ goto next;
+
+ hwc = &event->hw;
+
+ armpmu_event_update(event, hwc, idx);
+
+ data.period = event->hw.last_period;
+
+ if (!armpmu_event_set_period(event, hwc, idx))
+ goto next;
+
+ if (perf_event_overflow(event, &data, regs))
+ disable_counter(hwc->idx);
+next:
+ pmovsr &= (pmovsr - 1);
+ }
+
+ irq_work_run();
+
+ return IRQ_HANDLED;
+}
+
+static int krait_l2_map_event(struct perf_event *event)
+{
+ if (pmu_type > 0 && pmu_type == event->attr.type)
+ return event->attr.config & 0xfffff;
+ else
+ return -ENOENT;
+}
+
+static int
+krait_l2_pmu_generic_request_irq(int irq, irq_handler_t *handle_irq)
+{
+ return request_irq(irq, *handle_irq,
+ IRQF_DISABLED | IRQF_NOBALANCING,
+ "krait-l2-armpmu", NULL);
+}
+
+static void
+krait_l2_pmu_generic_free_irq(int irq)
+{
+ if (irq >= 0)
+ free_irq(irq, NULL);
+}
+
+static struct arm_pmu krait_l2_pmu = {
+ .id = ARM_PERF_PMU_ID_KRAIT_L2,
+ .type = ARM_PMU_DEVICE_L2CC,
+ .name = "Krait L2CC PMU",
+ .start = krait_l2_start,
+ .stop = krait_l2_stop,
+ .handle_irq = krait_l2_handle_irq,
+ .request_pmu_irq = krait_l2_pmu_generic_request_irq,
+ .free_pmu_irq = krait_l2_pmu_generic_free_irq,
+ .enable = krait_l2_enable,
+ .disable = krait_l2_disable,
+ .get_event_idx = krait_l2_get_event_idx,
+ .read_counter = krait_l2_read_counter,
+ .write_counter = krait_l2_write_counter,
+ .map_event = krait_l2_map_event,
+ .max_period = (1LLU << 32) - 1,
+ .get_hw_events = krait_l2_get_hw_events,
+ .num_events = MAX_KRAIT_L2_CTRS,
+};
+
+static int __devinit krait_l2_pmu_device_probe(struct platform_device *pdev)
+{
+ krait_l2_pmu.plat_device = pdev;
+
+ if (!armpmu_register(&krait_l2_pmu, "krait-l2", -1))
+ pmu_type = krait_l2_pmu.pmu.type;
+
+ return 0;
+}
+
+static struct platform_driver krait_l2_pmu_driver = {
+ .driver = {
+ .name = "l2-arm-pmu",
+ },
+ .probe = krait_l2_pmu_device_probe,
+};
+
+static int __init register_krait_l2_pmu_driver(void)
+{
+ /* Reset all ctrs */
+ set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
+
+ /* Avoid spurious interrupt if any */
+ get_reset_pmovsr();
+
+ return platform_driver_register(&krait_l2_pmu_driver);
+}
+device_initcall(register_krait_l2_pmu_driver);
diff --git a/arch/arm/mach-msm/perf_event_msm_l2.c b/arch/arm/mach-msm/perf_event_msm_l2.c
new file mode 100644
index 0000000..3310d92
--- /dev/null
+++ b/arch/arm/mach-msm/perf_event_msm_l2.c
@@ -0,0 +1,760 @@
+/*
+ * Copyright (c) 2011, 2012 Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/irq.h>
+#include <asm/pmu.h>
+#include <linux/platform_device.h>
+
+
+#define MAX_SCORPION_L2_CTRS 5
+#define SCORPION_L2CYCLE_CTR_BIT 31
+#define SCORPION_L2CYCLE_CTR_EVENT_IDX 4
+#define SCORPION_L2CYCLE_CTR_RAW_CODE 0xfe
+#define SCORPIONL2_PMNC_E (1 << 0) /* Enable all counters */
+#define SCORPION_L2_EVT_PREFIX 3
+#define SCORPION_MAX_L2_REG 4
+
+static u32 pmu_type;
+
+static struct arm_pmu scorpion_l2_pmu;
+
+static struct perf_event *l2_events[MAX_SCORPION_L2_CTRS];
+static unsigned long l2_used_mask[BITS_TO_LONGS(MAX_SCORPION_L2_CTRS)];
+
+static struct pmu_hw_events scorpion_l2_pmu_hw_events = {
+ .events = l2_events,
+ .used_mask = l2_used_mask,
+ .pmu_lock =
+ __RAW_SPIN_LOCK_UNLOCKED(scorpion_l2_pmu_hw_events.pmu_lock),
+};
+
+struct scorpion_l2_scorp_evt {
+ u32 evt_type;
+ u32 val;
+ u8 grp;
+ u32 evt_type_act;
+};
+
+enum scorpion_perf_types {
+ SCORPIONL2_TOTAL_BANK_REQ = 0x90,
+ SCORPIONL2_DSIDE_READ = 0x91,
+ SCORPIONL2_DSIDE_WRITE = 0x92,
+ SCORPIONL2_ISIDE_READ = 0x93,
+ SCORPIONL2_L2CACHE_ISIDE_READ = 0x94,
+ SCORPIONL2_L2CACHE_BANK_REQ = 0x95,
+ SCORPIONL2_L2CACHE_DSIDE_READ = 0x96,
+ SCORPIONL2_L2CACHE_DSIDE_WRITE = 0x97,
+ SCORPIONL2_L2NOCACHE_DSIDE_WRITE = 0x98,
+ SCORPIONL2_L2NOCACHE_ISIDE_READ = 0x99,
+ SCORPIONL2_L2NOCACHE_TOTAL_REQ = 0x9a,
+ SCORPIONL2_L2NOCACHE_DSIDE_READ = 0x9b,
+ SCORPIONL2_DSIDE_READ_NOL1 = 0x9c,
+ SCORPIONL2_L2CACHE_WRITETHROUGH = 0x9d,
+ SCORPIONL2_BARRIERS = 0x9e,
+ SCORPIONL2_HARDWARE_TABLE_WALKS = 0x9f,
+ SCORPIONL2_MVA_POC = 0xa0,
+ SCORPIONL2_L2CACHE_HW_TABLE_WALKS = 0xa1,
+ SCORPIONL2_SETWAY_CACHE_OPS = 0xa2,
+ SCORPIONL2_DSIDE_WRITE_HITS = 0xa3,
+ SCORPIONL2_ISIDE_READ_HITS = 0xa4,
+ SCORPIONL2_CACHE_DSIDE_READ_NOL1 = 0xa5,
+ SCORPIONL2_TOTAL_CACHE_HITS = 0xa6,
+ SCORPIONL2_CACHE_MATCH_MISS = 0xa7,
+ SCORPIONL2_DREAD_HIT_L1_DATA = 0xa8,
+ SCORPIONL2_L2LINE_LOCKED = 0xa9,
+ SCORPIONL2_HW_TABLE_WALK_HIT = 0xaa,
+ SCORPIONL2_CACHE_MVA_POC = 0xab,
+ SCORPIONL2_L2ALLOC_DWRITE_MISS = 0xac,
+ SCORPIONL2_CORRECTED_TAG_ARRAY = 0xad,
+ SCORPIONL2_CORRECTED_DATA_ARRAY = 0xae,
+ SCORPIONL2_CORRECTED_REPLACEMENT_ARRAY = 0xaf,
+ SCORPIONL2_PMBUS_MPAAF = 0xb0,
+ SCORPIONL2_PMBUS_MPWDAF = 0xb1,
+ SCORPIONL2_PMBUS_MPBRT = 0xb2,
+ SCORPIONL2_CPU0_GRANT = 0xb3,
+ SCORPIONL2_CPU1_GRANT = 0xb4,
+ SCORPIONL2_CPU0_NOGRANT = 0xb5,
+ SCORPIONL2_CPU1_NOGRANT = 0xb6,
+ SCORPIONL2_CPU0_LOSING_ARB = 0xb7,
+ SCORPIONL2_CPU1_LOSING_ARB = 0xb8,
+ SCORPIONL2_SLAVEPORT_NOGRANT = 0xb9,
+ SCORPIONL2_SLAVEPORT_BPQ_FULL = 0xba,
+ SCORPIONL2_SLAVEPORT_LOSING_ARB = 0xbb,
+ SCORPIONL2_SLAVEPORT_GRANT = 0xbc,
+ SCORPIONL2_SLAVEPORT_GRANTLOCK = 0xbd,
+ SCORPIONL2_L2EM_STREX_PASS = 0xbe,
+ SCORPIONL2_L2EM_STREX_FAIL = 0xbf,
+ SCORPIONL2_LDREX_RESERVE_L2EM = 0xc0,
+ SCORPIONL2_SLAVEPORT_LDREX = 0xc1,
+ SCORPIONL2_CPU0_L2EM_CLEARED = 0xc2,
+ SCORPIONL2_CPU1_L2EM_CLEARED = 0xc3,
+ SCORPIONL2_SLAVEPORT_L2EM_CLEARED = 0xc4,
+ SCORPIONL2_CPU0_CLAMPED = 0xc5,
+ SCORPIONL2_CPU1_CLAMPED = 0xc6,
+ SCORPIONL2_CPU0_WAIT = 0xc7,
+ SCORPIONL2_CPU1_WAIT = 0xc8,
+ SCORPIONL2_CPU0_NONAMBAS_WAIT = 0xc9,
+ SCORPIONL2_CPU1_NONAMBAS_WAIT = 0xca,
+ SCORPIONL2_CPU0_DSB_WAIT = 0xcb,
+ SCORPIONL2_CPU1_DSB_WAIT = 0xcc,
+ SCORPIONL2_AXI_READ = 0xcd,
+ SCORPIONL2_AXI_WRITE = 0xce,
+
+ SCORPIONL2_1BEAT_WRITE = 0xcf,
+ SCORPIONL2_2BEAT_WRITE = 0xd0,
+ SCORPIONL2_4BEAT_WRITE = 0xd1,
+ SCORPIONL2_8BEAT_WRITE = 0xd2,
+ SCORPIONL2_12BEAT_WRITE = 0xd3,
+ SCORPIONL2_16BEAT_WRITE = 0xd4,
+ SCORPIONL2_1BEAT_DSIDE_READ = 0xd5,
+ SCORPIONL2_2BEAT_DSIDE_READ = 0xd6,
+ SCORPIONL2_4BEAT_DSIDE_READ = 0xd7,
+ SCORPIONL2_8BEAT_DSIDE_READ = 0xd8,
+ SCORPIONL2_CSYS_READ_1BEAT = 0xd9,
+ SCORPIONL2_CSYS_READ_2BEAT = 0xda,
+ SCORPIONL2_CSYS_READ_4BEAT = 0xdb,
+ SCORPIONL2_CSYS_READ_8BEAT = 0xdc,
+ SCORPIONL2_4BEAT_IFETCH_READ = 0xdd,
+ SCORPIONL2_8BEAT_IFETCH_READ = 0xde,
+ SCORPIONL2_CSYS_WRITE_1BEAT = 0xdf,
+ SCORPIONL2_CSYS_WRITE_2BEAT = 0xe0,
+ SCORPIONL2_AXI_READ_DATA_BEAT = 0xe1,
+ SCORPIONL2_AXI_WRITE_EVT1 = 0xe2,
+ SCORPIONL2_AXI_WRITE_EVT2 = 0xe3,
+ SCORPIONL2_LDREX_REQ = 0xe4,
+ SCORPIONL2_STREX_PASS = 0xe5,
+ SCORPIONL2_STREX_FAIL = 0xe6,
+ SCORPIONL2_CPREAD = 0xe7,
+ SCORPIONL2_CPWRITE = 0xe8,
+ SCORPIONL2_BARRIER_REQ = 0xe9,
+ SCORPIONL2_AXI_READ_SLVPORT = 0xea,
+ SCORPIONL2_AXI_WRITE_SLVPORT = 0xeb,
+ SCORPIONL2_AXI_READ_SLVPORT_DATABEAT = 0xec,
+ SCORPIONL2_AXI_WRITE_SLVPORT_DATABEAT = 0xed,
+ SCORPIONL2_SNOOPKILL_PREFILTER = 0xee,
+ SCORPIONL2_SNOOPKILL_FILTEROUT = 0xef,
+ SCORPIONL2_SNOOPED_IC = 0xf0,
+ SCORPIONL2_SNOOPED_BP = 0xf1,
+ SCORPIONL2_SNOOPED_BARRIERS = 0xf2,
+ SCORPIONL2_SNOOPED_TLB = 0xf3,
+ SCORPION_L2_MAX_EVT,
+};
+
+static const struct scorpion_l2_scorp_evt sc_evt[] = {
+ {SCORPIONL2_TOTAL_BANK_REQ, 0x80000001, 0, 0x00},
+ {SCORPIONL2_DSIDE_READ, 0x80000100, 0, 0x01},
+ {SCORPIONL2_DSIDE_WRITE, 0x80010000, 0, 0x02},
+ {SCORPIONL2_ISIDE_READ, 0x81000000, 0, 0x03},
+ {SCORPIONL2_L2CACHE_ISIDE_READ, 0x80000002, 0, 0x00},
+ {SCORPIONL2_L2CACHE_BANK_REQ, 0x80000200, 0, 0x01},
+ {SCORPIONL2_L2CACHE_DSIDE_READ, 0x80020000, 0, 0x02},
+ {SCORPIONL2_L2CACHE_DSIDE_WRITE, 0x82000000, 0, 0x03},
+ {SCORPIONL2_L2NOCACHE_DSIDE_WRITE, 0x80000003, 0, 0x00},
+ {SCORPIONL2_L2NOCACHE_ISIDE_READ, 0x80000300, 0, 0x01},
+ {SCORPIONL2_L2NOCACHE_TOTAL_REQ, 0x80030000, 0, 0x02},
+ {SCORPIONL2_L2NOCACHE_DSIDE_READ, 0x83000000, 0, 0x03},
+ {SCORPIONL2_DSIDE_READ_NOL1, 0x80000004, 0, 0x00},
+ {SCORPIONL2_L2CACHE_WRITETHROUGH, 0x80000400, 0, 0x01},
+ {SCORPIONL2_BARRIERS, 0x84000000, 0, 0x03},
+ {SCORPIONL2_HARDWARE_TABLE_WALKS, 0x80000005, 0, 0x00},
+ {SCORPIONL2_MVA_POC, 0x80000500, 0, 0x01},
+ {SCORPIONL2_L2CACHE_HW_TABLE_WALKS, 0x80050000, 0, 0x02},
+ {SCORPIONL2_SETWAY_CACHE_OPS, 0x85000000, 0, 0x03},
+ {SCORPIONL2_DSIDE_WRITE_HITS, 0x80000006, 0, 0x00},
+ {SCORPIONL2_ISIDE_READ_HITS, 0x80000600, 0, 0x01},
+ {SCORPIONL2_CACHE_DSIDE_READ_NOL1, 0x80060000, 0, 0x02},
+ {SCORPIONL2_TOTAL_CACHE_HITS, 0x86000000, 0, 0x03},
+ {SCORPIONL2_CACHE_MATCH_MISS, 0x80000007, 0, 0x00},
+ {SCORPIONL2_DREAD_HIT_L1_DATA, 0x87000000, 0, 0x03},
+ {SCORPIONL2_L2LINE_LOCKED, 0x80000008, 0, 0x00},
+ {SCORPIONL2_HW_TABLE_WALK_HIT, 0x80000800, 0, 0x01},
+ {SCORPIONL2_CACHE_MVA_POC, 0x80080000, 0, 0x02},
+ {SCORPIONL2_L2ALLOC_DWRITE_MISS, 0x88000000, 0, 0x03},
+ {SCORPIONL2_CORRECTED_TAG_ARRAY, 0x80001A00, 0, 0x01},
+ {SCORPIONL2_CORRECTED_DATA_ARRAY, 0x801A0000, 0, 0x02},
+ {SCORPIONL2_CORRECTED_REPLACEMENT_ARRAY, 0x9A000000, 0, 0x03},
+ {SCORPIONL2_PMBUS_MPAAF, 0x80001C00, 0, 0x01},
+ {SCORPIONL2_PMBUS_MPWDAF, 0x801C0000, 0, 0x02},
+ {SCORPIONL2_PMBUS_MPBRT, 0x9C000000, 0, 0x03},
+
+ {SCORPIONL2_CPU0_GRANT, 0x80000001, 1, 0x04},
+ {SCORPIONL2_CPU1_GRANT, 0x80000100, 1, 0x05},
+ {SCORPIONL2_CPU0_NOGRANT, 0x80020000, 1, 0x06},
+ {SCORPIONL2_CPU1_NOGRANT, 0x82000000, 1, 0x07},
+ {SCORPIONL2_CPU0_LOSING_ARB, 0x80040000, 1, 0x06},
+ {SCORPIONL2_CPU1_LOSING_ARB, 0x84000000, 1, 0x07},
+ {SCORPIONL2_SLAVEPORT_NOGRANT, 0x80000007, 1, 0x04},
+ {SCORPIONL2_SLAVEPORT_BPQ_FULL, 0x80000700, 1, 0x05},
+ {SCORPIONL2_SLAVEPORT_LOSING_ARB, 0x80070000, 1, 0x06},
+ {SCORPIONL2_SLAVEPORT_GRANT, 0x87000000, 1, 0x07},
+ {SCORPIONL2_SLAVEPORT_GRANTLOCK, 0x80000008, 1, 0x04},
+ {SCORPIONL2_L2EM_STREX_PASS, 0x80000009, 1, 0x04},
+ {SCORPIONL2_L2EM_STREX_FAIL, 0x80000900, 1, 0x05},
+ {SCORPIONL2_LDREX_RESERVE_L2EM, 0x80090000, 1, 0x06},
+ {SCORPIONL2_SLAVEPORT_LDREX, 0x89000000, 1, 0x07},
+ {SCORPIONL2_CPU0_L2EM_CLEARED, 0x800A0000, 1, 0x06},
+ {SCORPIONL2_CPU1_L2EM_CLEARED, 0x8A000000, 1, 0x07},
+ {SCORPIONL2_SLAVEPORT_L2EM_CLEARED, 0x80000B00, 1, 0x05},
+ {SCORPIONL2_CPU0_CLAMPED, 0x8000000E, 1, 0x04},
+ {SCORPIONL2_CPU1_CLAMPED, 0x80000E00, 1, 0x05},
+ {SCORPIONL2_CPU0_WAIT, 0x800F0000, 1, 0x06},
+ {SCORPIONL2_CPU1_WAIT, 0x8F000000, 1, 0x07},
+ {SCORPIONL2_CPU0_NONAMBAS_WAIT, 0x80000010, 1, 0x04},
+ {SCORPIONL2_CPU1_NONAMBAS_WAIT, 0x80001000, 1, 0x05},
+ {SCORPIONL2_CPU0_DSB_WAIT, 0x80000014, 1, 0x04},
+ {SCORPIONL2_CPU1_DSB_WAIT, 0x80001400, 1, 0x05},
+
+ {SCORPIONL2_AXI_READ, 0x80000001, 2, 0x08},
+ {SCORPIONL2_AXI_WRITE, 0x80000100, 2, 0x09},
+ {SCORPIONL2_1BEAT_WRITE, 0x80010000, 2, 0x0a},
+ {SCORPIONL2_2BEAT_WRITE, 0x80010000, 2, 0x0b},
+ {SCORPIONL2_4BEAT_WRITE, 0x80000002, 2, 0x08},
+ {SCORPIONL2_8BEAT_WRITE, 0x80000200, 2, 0x09},
+ {SCORPIONL2_12BEAT_WRITE, 0x80020000, 2, 0x0a},
+ {SCORPIONL2_16BEAT_WRITE, 0x82000000, 2, 0x0b},
+ {SCORPIONL2_1BEAT_DSIDE_READ, 0x80000003, 2, 0x08},
+ {SCORPIONL2_2BEAT_DSIDE_READ, 0x80000300, 2, 0x09},
+ {SCORPIONL2_4BEAT_DSIDE_READ, 0x80030000, 2, 0x0a},
+ {SCORPIONL2_8BEAT_DSIDE_READ, 0x83000000, 2, 0x0b},
+ {SCORPIONL2_CSYS_READ_1BEAT, 0x80000004, 2, 0x08},
+ {SCORPIONL2_CSYS_READ_2BEAT, 0x80000400, 2, 0x09},
+ {SCORPIONL2_CSYS_READ_4BEAT, 0x80040000, 2, 0x0a},
+ {SCORPIONL2_CSYS_READ_8BEAT, 0x84000000, 2, 0x0b},
+ {SCORPIONL2_4BEAT_IFETCH_READ, 0x80000005, 2, 0x08},
+ {SCORPIONL2_8BEAT_IFETCH_READ, 0x80000500, 2, 0x09},
+ {SCORPIONL2_CSYS_WRITE_1BEAT, 0x80050000, 2, 0x0a},
+ {SCORPIONL2_CSYS_WRITE_2BEAT, 0x85000000, 2, 0x0b},
+ {SCORPIONL2_AXI_READ_DATA_BEAT, 0x80000600, 2, 0x09},
+ {SCORPIONL2_AXI_WRITE_EVT1, 0x80060000, 2, 0x0a},
+ {SCORPIONL2_AXI_WRITE_EVT2, 0x86000000, 2, 0x0b},
+ {SCORPIONL2_LDREX_REQ, 0x80000007, 2, 0x08},
+ {SCORPIONL2_STREX_PASS, 0x80000700, 2, 0x09},
+ {SCORPIONL2_STREX_FAIL, 0x80070000, 2, 0x0a},
+ {SCORPIONL2_CPREAD, 0x80000008, 2, 0x08},
+ {SCORPIONL2_CPWRITE, 0x80000800, 2, 0x09},
+ {SCORPIONL2_BARRIER_REQ, 0x88000000, 2, 0x0b},
+
+ {SCORPIONL2_AXI_READ_SLVPORT, 0x80000001, 3, 0x0c},
+ {SCORPIONL2_AXI_WRITE_SLVPORT, 0x80000100, 3, 0x0d},
+ {SCORPIONL2_AXI_READ_SLVPORT_DATABEAT, 0x80010000, 3, 0x0e},
+ {SCORPIONL2_AXI_WRITE_SLVPORT_DATABEAT, 0x81000000, 3, 0x0f},
+
+ {SCORPIONL2_SNOOPKILL_PREFILTER, 0x80000001, 4, 0x10},
+ {SCORPIONL2_SNOOPKILL_FILTEROUT, 0x80000100, 4, 0x11},
+ {SCORPIONL2_SNOOPED_IC, 0x80000002, 4, 0x10},
+ {SCORPIONL2_SNOOPED_BP, 0x80000200, 4, 0x11},
+ {SCORPIONL2_SNOOPED_BARRIERS, 0x80020000, 4, 0x12},
+ {SCORPIONL2_SNOOPED_TLB, 0x82000000, 4, 0x13},
+};
+
+static struct pmu_hw_events *scorpion_l2_get_hw_events(void)
+{
+ return &scorpion_l2_pmu_hw_events;
+}
+static u32 scorpion_l2_read_l2pm0(void)
+{
+ u32 val;
+ asm volatile ("mrc p15, 3, %0, c15, c7, 0" : "=r" (val));
+ return val;
+}
+
+static void scorpion_l2_write_l2pm0(u32 val)
+{
+ asm volatile ("mcr p15, 3, %0, c15, c7, 0" : : "r" (val));
+}
+
+static u32 scorpion_l2_read_l2pm1(void)
+{
+ u32 val;
+ asm volatile ("mrc p15, 3, %0, c15, c7, 1" : "=r" (val));
+ return val;
+}
+
+static void scorpion_l2_write_l2pm1(u32 val)
+{
+ asm volatile ("mcr p15, 3, %0, c15, c7, 1" : : "r" (val));
+}
+
+static u32 scorpion_l2_read_l2pm2(void)
+{
+ u32 val;
+ asm volatile ("mrc p15, 3, %0, c15, c7, 2" : "=r" (val));
+ return val;
+}
+
+static void scorpion_l2_write_l2pm2(u32 val)
+{
+ asm volatile ("mcr p15, 3, %0, c15, c7, 2" : : "r" (val));
+}
+
+static u32 scorpion_l2_read_l2pm3(void)
+{
+ u32 val;
+ asm volatile ("mrc p15, 3, %0, c15, c7, 3" : "=r" (val));
+ return val;
+}
+
+static void scorpion_l2_write_l2pm3(u32 val)
+{
+ asm volatile ("mcr p15, 3, %0, c15, c7, 3" : : "r" (val));
+}
+
+static u32 scorpion_l2_read_l2pm4(void)
+{
+ u32 val;
+ asm volatile ("mrc p15, 3, %0, c15, c7, 4" : "=r" (val));
+ return val;
+}
+
+static void scorpion_l2_write_l2pm4(u32 val)
+{
+ asm volatile ("mcr p15, 3, %0, c15, c7, 4" : : "r" (val));
+}
+
+struct scorpion_scorpion_access_funcs {
+ u32(*read) (void);
+ void (*write) (u32);
+ void (*pre) (void);
+ void (*post) (void);
+};
+
+struct scorpion_scorpion_access_funcs scorpion_l2_func[] = {
+ {scorpion_l2_read_l2pm0, scorpion_l2_write_l2pm0, NULL, NULL},
+ {scorpion_l2_read_l2pm1, scorpion_l2_write_l2pm1, NULL, NULL},
+ {scorpion_l2_read_l2pm2, scorpion_l2_write_l2pm2, NULL, NULL},
+ {scorpion_l2_read_l2pm3, scorpion_l2_write_l2pm3, NULL, NULL},
+ {scorpion_l2_read_l2pm4, scorpion_l2_write_l2pm4, NULL, NULL},
+};
+
+#define COLMN0MASK 0x000000ff
+#define COLMN1MASK 0x0000ff00
+#define COLMN2MASK 0x00ff0000
+
+static u32 scorpion_l2_get_columnmask(u32 setval)
+{
+ if (setval & COLMN0MASK)
+ return 0xffffff00;
+ else if (setval & COLMN1MASK)
+ return 0xffff00ff;
+ else if (setval & COLMN2MASK)
+ return 0xff00ffff;
+ else
+ return 0x80ffffff;
+}
+
+static void scorpion_l2_evt_setup(u32 gr, u32 setval)
+{
+ u32 val;
+ if (scorpion_l2_func[gr].pre)
+ scorpion_l2_func[gr].pre();
+ val = scorpion_l2_get_columnmask(setval) & scorpion_l2_func[gr].read();
+ val = val | setval;
+ scorpion_l2_func[gr].write(val);
+ if (scorpion_l2_func[gr].post)
+ scorpion_l2_func[gr].post();
+}
+
+#define SCORPION_L2_EVT_START_IDX 0x90
+#define SCORPION_L2_INV_EVTYPE 0
+
+static unsigned int get_scorpion_l2_evtinfo(unsigned int evt_type,
+ struct scorpion_l2_scorp_evt *evtinfo)
+{
+ u32 idx;
+ u8 prefix;
+ u8 reg;
+ u8 code;
+ u8 group;
+
+ prefix = (evt_type & 0xF0000) >> 16;
+ if (prefix == SCORPION_L2_EVT_PREFIX) {
+ reg = (evt_type & 0x0F000) >> 12;
+ code = (evt_type & 0x00FF0) >> 4;
+ group = evt_type & 0x0000F;
+
+ if ((group > 3) || (reg > SCORPION_MAX_L2_REG))
+ return SCORPION_L2_INV_EVTYPE;
+
+ evtinfo->val = 0x80000000 | (code << (group * 8));
+ evtinfo->grp = reg;
+ evtinfo->evt_type_act = group | (reg << 2);
+ return evtinfo->evt_type_act;
+ }
+
+ if (evt_type < SCORPION_L2_EVT_START_IDX
+ || evt_type >= SCORPION_L2_MAX_EVT)
+ return SCORPION_L2_INV_EVTYPE;
+
+ idx = evt_type - SCORPION_L2_EVT_START_IDX;
+
+ if (sc_evt[idx].evt_type == evt_type) {
+ evtinfo->val = sc_evt[idx].val;
+ evtinfo->grp = sc_evt[idx].grp;
+ evtinfo->evt_type_act = sc_evt[idx].evt_type_act;
+ return sc_evt[idx].evt_type_act;
+ }
+ return SCORPION_L2_INV_EVTYPE;
+}
+
+static inline void scorpion_l2_pmnc_write(unsigned long val)
+{
+ val &= 0xff;
+ asm volatile ("mcr p15, 3, %0, c15, c4, 0" : : "r" (val));
+}
+
+static inline unsigned long scorpion_l2_pmnc_read(void)
+{
+ u32 val;
+ asm volatile ("mrc p15, 3, %0, c15, c4, 0" : "=r" (val));
+ return val;
+}
+
+static void scorpion_l2_set_evcntcr(void)
+{
+ u32 val = 0x0;
+ asm volatile ("mcr p15, 3, %0, c15, c6, 4" : : "r" (val));
+}
+
+static inline void scorpion_l2_set_evtyper(int ctr, int val)
+{
+ /* select ctr */
+ asm volatile ("mcr p15, 3, %0, c15, c6, 0" : : "r" (ctr));
+
+ /* write into EVTYPER */
+ asm volatile ("mcr p15, 3, %0, c15, c6, 7" : : "r" (val));
+}
+
+static void scorpion_l2_set_evfilter_task_mode(void)
+{
+ u32 filter_val = 0x000f0030 | 1 << smp_processor_id();
+
+ asm volatile ("mcr p15, 3, %0, c15, c6, 3" : : "r" (filter_val));
+}
+
+static void scorpion_l2_set_evfilter_sys_mode(void)
+{
+ u32 filter_val = 0x000f003f;
+
+ asm volatile ("mcr p15, 3, %0, c15, c6, 3" : : "r" (filter_val));
+}
+
+static void scorpion_l2_enable_intenset(u32 idx)
+{
+ if (idx == SCORPION_L2CYCLE_CTR_EVENT_IDX) {
+ asm volatile ("mcr p15, 3, %0, c15, c5, 1" : : "r"
+ (1 << SCORPION_L2CYCLE_CTR_BIT));
+ } else {
+ asm volatile ("mcr p15, 3, %0, c15, c5, 1" : : "r" (1 << idx));
+ }
+}
+
+static void scorpion_l2_disable_intenclr(u32 idx)
+{
+ if (idx == SCORPION_L2CYCLE_CTR_EVENT_IDX) {
+ asm volatile ("mcr p15, 3, %0, c15, c5, 0" : : "r"
+ (1 << SCORPION_L2CYCLE_CTR_BIT));
+ } else {
+ asm volatile ("mcr p15, 3, %0, c15, c5, 0" : : "r" (1 << idx));
+ }
+}
+
+static void scorpion_l2_enable_counter(u32 idx)
+{
+ if (idx == SCORPION_L2CYCLE_CTR_EVENT_IDX) {
+ asm volatile ("mcr p15, 3, %0, c15, c4, 3" : : "r"
+ (1 << SCORPION_L2CYCLE_CTR_BIT));
+ } else {
+ asm volatile ("mcr p15, 3, %0, c15, c4, 3" : : "r" (1 << idx));
+ }
+}
+
+static void scorpion_l2_disable_counter(u32 idx)
+{
+ if (idx == SCORPION_L2CYCLE_CTR_EVENT_IDX) {
+ asm volatile ("mcr p15, 3, %0, c15, c4, 2" : : "r"
+ (1 << SCORPION_L2CYCLE_CTR_BIT));
+ } else {
+ asm volatile ("mcr p15, 3, %0, c15, c4, 2" : : "r" (1 << idx));
+ }
+}
+
+static u32 scorpion_l2_read_counter(int idx)
+{
+ u32 val;
+ unsigned long iflags;
+
+ if (idx == SCORPION_L2CYCLE_CTR_EVENT_IDX) {
+ asm volatile ("mrc p15, 3, %0, c15, c4, 5" : "=r" (val));
+ } else {
+ raw_spin_lock_irqsave(&scorpion_l2_pmu_hw_events.pmu_lock,
+ iflags);
+ asm volatile ("mcr p15, 3, %0, c15, c6, 0" : : "r" (idx));
+
+ /* read val from counter */
+ asm volatile ("mrc p15, 3, %0, c15, c6, 5" : "=r" (val));
+ raw_spin_unlock_irqrestore(&scorpion_l2_pmu_hw_events.pmu_lock,
+ iflags);
+ }
+
+ return val;
+}
+
+static void scorpion_l2_write_counter(int idx, u32 val)
+{
+ unsigned long iflags;
+
+ if (idx == SCORPION_L2CYCLE_CTR_EVENT_IDX) {
+ asm volatile ("mcr p15, 3, %0, c15, c4, 5" : : "r" (val));
+ } else {
+ raw_spin_lock_irqsave(&scorpion_l2_pmu_hw_events.pmu_lock,
+ iflags);
+
+ /* select counter */
+ asm volatile ("mcr p15, 3, %0, c15, c6, 0" : : "r" (idx));
+
+ /* write val into counter */
+ asm volatile ("mcr p15, 3, %0, c15, c6, 5" : : "r" (val));
+ raw_spin_unlock_irqrestore(&scorpion_l2_pmu_hw_events.pmu_lock,
+ iflags);
+ }
+}
+
+static void scorpion_l2_stop_counter(struct hw_perf_event *hwc, int idx)
+{
+ scorpion_l2_disable_intenclr(idx);
+ scorpion_l2_disable_counter(idx);
+ pr_debug("%s: event: %ld ctr: %d stopped\n", __func__,
+ hwc->config_base, idx);
+}
+
+static void scorpion_l2_enable(struct hw_perf_event *hwc, int idx, int cpu)
+{
+ struct scorpion_l2_scorp_evt evtinfo;
+ int evtype = hwc->config_base;
+ int ev_typer;
+ unsigned long iflags;
+
+ raw_spin_lock_irqsave(&scorpion_l2_pmu_hw_events.pmu_lock, iflags);
+
+ if (hwc->config_base == SCORPION_L2CYCLE_CTR_RAW_CODE)
+ goto out;
+
+ memset(&evtinfo, 0, sizeof(evtinfo));
+
+ ev_typer = get_scorpion_l2_evtinfo(evtype, &evtinfo);
+
+ scorpion_l2_set_evtyper(idx, ev_typer);
+
+ scorpion_l2_set_evcntcr();
+
+ if (cpu < 0)
+ scorpion_l2_set_evfilter_task_mode();
+ else
+ scorpion_l2_set_evfilter_sys_mode();
+
+ scorpion_l2_evt_setup(evtinfo.grp, evtinfo.val);
+
+out:
+
+ scorpion_l2_enable_intenset(idx);
+
+ scorpion_l2_enable_counter(idx);
+
+ raw_spin_unlock_irqrestore(&scorpion_l2_pmu_hw_events.pmu_lock, iflags);
+
+ pr_debug("%s: ctr: %d group: %ld group_code: %lld started from cpu:%d\n",
+ __func__, idx, hwc->config_base, hwc->config, smp_processor_id());
+}
+
+static void scorpion_l2_disable(struct hw_perf_event *hwc, int idx)
+{
+ unsigned long iflags;
+
+ raw_spin_lock_irqsave(&scorpion_l2_pmu_hw_events.pmu_lock, iflags);
+
+ scorpion_l2_stop_counter(hwc, idx);
+
+ raw_spin_unlock_irqrestore(&scorpion_l2_pmu_hw_events.pmu_lock, iflags);
+
+ pr_debug("%s: event: %ld deleted\n", __func__, hwc->config_base);
+}
+
+static int scorpion_l2_get_event_idx(struct pmu_hw_events *cpuc,
+ struct hw_perf_event *hwc)
+{
+ int ctr = 0;
+
+ if (hwc->config_base == SCORPION_L2CYCLE_CTR_RAW_CODE) {
+ if (!test_and_set_bit(SCORPION_L2CYCLE_CTR_EVENT_IDX,
+ cpuc->used_mask))
+ return SCORPION_L2CYCLE_CTR_EVENT_IDX;
+ }
+
+ for (ctr = 0; ctr < MAX_SCORPION_L2_CTRS - 1; ctr++) {
+ if (!test_and_set_bit(ctr, cpuc->used_mask))
+ return ctr;
+ }
+
+ return -EAGAIN;
+}
+
+static void scorpion_l2_start(void)
+{
+ isb();
+ /* Enable all counters */
+ scorpion_l2_pmnc_write(scorpion_l2_pmnc_read() | SCORPIONL2_PMNC_E);
+}
+
+static void scorpion_l2_stop(void)
+{
+ /* Disable all counters */
+ scorpion_l2_pmnc_write(scorpion_l2_pmnc_read() & ~SCORPIONL2_PMNC_E);
+ isb();
+}
+
+static inline u32 scorpion_l2_get_reset_pmovsr(void)
+{
+ u32 val;
+
+ /* Read */
+ asm volatile ("mrc p15, 3, %0, c15, c4, 1" : "=r" (val));
+
+ /* Write to clear flags */
+ val &= 0xffffffff;
+ asm volatile ("mcr p15, 3, %0, c15, c4, 1" : : "r" (val));
+
+ return val;
+}
+
+static irqreturn_t scorpion_l2_handle_irq(int irq_num, void *dev)
+{
+ unsigned long pmovsr;
+ struct perf_sample_data data;
+ struct pt_regs *regs;
+ struct perf_event *event;
+ struct hw_perf_event *hwc;
+ int bitp;
+ int idx = 0;
+
+ pmovsr = scorpion_l2_get_reset_pmovsr();
+
+ if (!(pmovsr & 0xffffffff))
+ return IRQ_NONE;
+
+ regs = get_irq_regs();
+
+ perf_sample_data_init(&data, 0);
+
+ while (pmovsr) {
+ bitp = __ffs(pmovsr);
+
+ if (bitp == SCORPION_L2CYCLE_CTR_BIT)
+ idx = SCORPION_L2CYCLE_CTR_EVENT_IDX;
+ else
+ idx = bitp;
+
+ event = scorpion_l2_pmu_hw_events.events[idx];
+
+ if (!event)
+ goto next;
+
+ if (!test_bit(idx, scorpion_l2_pmu_hw_events.used_mask))
+ goto next;
+
+ hwc = &event->hw;
+
+ armpmu_event_update(event, hwc, idx);
+
+ data.period = event->hw.last_period;
+
+ if (!armpmu_event_set_period(event, hwc, idx))
+ goto next;
+
+ if (perf_event_overflow(event, &data, regs))
+ scorpion_l2_disable_counter(hwc->idx);
+next:
+ pmovsr &= (pmovsr - 1);
+ }
+
+ irq_work_run();
+
+ return IRQ_HANDLED;
+}
+
+static int scorpion_l2_map_event(struct perf_event *event)
+{
+ if (pmu_type > 0 && pmu_type == event->attr.type)
+ return event->attr.config & 0xfffff;
+ else
+ return -ENOENT;
+}
+
+static int
+scorpion_l2_pmu_generic_request_irq(int irq, irq_handler_t *handle_irq)
+{
+ return request_irq(irq, *handle_irq,
+ IRQF_DISABLED | IRQF_NOBALANCING,
+ "scorpion-l2-armpmu", NULL);
+}
+
+static void
+scorpion_l2_pmu_generic_free_irq(int irq)
+{
+ if (irq >= 0)
+ free_irq(irq, NULL);
+}
+
+static struct arm_pmu scorpion_l2_pmu = {
+ .id = ARM_PERF_PMU_ID_SCORPIONMP_L2,
+ .type = ARM_PMU_DEVICE_L2CC,
+ .name = "Scorpion L2CC PMU",
+ .start = scorpion_l2_start,
+ .stop = scorpion_l2_stop,
+ .handle_irq = scorpion_l2_handle_irq,
+ .request_pmu_irq = scorpion_l2_pmu_generic_request_irq,
+ .free_pmu_irq = scorpion_l2_pmu_generic_free_irq,
+ .enable = scorpion_l2_enable,
+ .disable = scorpion_l2_disable,
+ .read_counter = scorpion_l2_read_counter,
+ .get_event_idx = scorpion_l2_get_event_idx,
+ .write_counter = scorpion_l2_write_counter,
+ .map_event = scorpion_l2_map_event,
+ .max_period = (1LLU << 32) - 1,
+ .get_hw_events = scorpion_l2_get_hw_events,
+ .num_events = MAX_SCORPION_L2_CTRS,
+};
+
+static int __devinit scorpion_l2_pmu_device_probe(struct platform_device *pdev)
+{
+ scorpion_l2_pmu.plat_device = pdev;
+
+ if (!armpmu_register(&scorpion_l2_pmu, "scorpion-l2", -1))
+ pmu_type = scorpion_l2_pmu.pmu.type;
+
+ return 0;
+}
+
+static struct platform_driver scorpion_l2_pmu_driver = {
+ .driver = {
+ .name = "l2-arm-pmu",
+ },
+ .probe = scorpion_l2_pmu_device_probe,
+};
+
+static int __init register_scorpion_l2_pmu_driver(void)
+{
+ /* Avoid spurious interrupt if any */
+ scorpion_l2_get_reset_pmovsr();
+
+ return platform_driver_register(&scorpion_l2_pmu_driver);
+}
+device_initcall(register_scorpion_l2_pmu_driver);
diff --git a/arch/arm/mach-msm/pmu.c b/arch/arm/mach-msm/pmu.c
index 1f82468..5e339da 100644
--- a/arch/arm/mach-msm/pmu.c
+++ b/arch/arm/mach-msm/pmu.c
@@ -33,7 +33,7 @@
static struct platform_device l2_pmu_device = {
.name = "l2-arm-pmu",
- .id = ARM_PMU_DEVICE_L2,
+ .id = ARM_PMU_DEVICE_L2CC,
.resource = l2_pmu_resource,
.num_resources = ARRAY_SIZE(l2_pmu_resource),
};
diff --git a/drivers/gpu/ion/ion_cp_heap.c b/drivers/gpu/ion/ion_cp_heap.c
index a857988a..6edc30b 100644
--- a/drivers/gpu/ion/ion_cp_heap.c
+++ b/drivers/gpu/ion/ion_cp_heap.c
@@ -97,6 +97,7 @@
int iommu_map_all;
int iommu_2x_map_domain;
unsigned int has_outer_cache;
+ atomic_t protect_cnt;
};
enum {
@@ -131,7 +132,7 @@
container_of(heap, struct ion_cp_heap, heap);
int ret_value = 0;
- if (cp_heap->heap_protected == HEAP_NOT_PROTECTED) {
+ if (atomic_inc_return(&cp_heap->protect_cnt) == 1) {
/* Make sure we are in C state when the heap is protected. */
if (cp_heap->reusable && !cp_heap->allocated_bytes) {
ret_value = fmem_set_state(FMEM_C_STATE);
@@ -150,6 +151,7 @@
pr_err("%s: unable to transition heap to T-state\n",
__func__);
}
+ atomic_dec(&cp_heap->protect_cnt);
} else {
cp_heap->heap_protected = HEAP_PROTECTED;
pr_debug("Protected heap %s @ 0x%lx\n",
@@ -157,6 +159,9 @@
}
}
out:
+ pr_debug("%s: protect count is %d\n", __func__,
+ atomic_read(&cp_heap->protect_cnt));
+ BUG_ON(atomic_read(&cp_heap->protect_cnt) < 0);
return ret_value;
}
@@ -170,7 +175,7 @@
struct ion_cp_heap *cp_heap =
container_of(heap, struct ion_cp_heap, heap);
- if (cp_heap->heap_protected == HEAP_PROTECTED) {
+ if (atomic_dec_and_test(&cp_heap->protect_cnt)) {
int error_code = ion_cp_unprotect_mem(
cp_heap->secure_base, cp_heap->secure_size,
cp_heap->permission_type);
@@ -189,6 +194,9 @@
}
}
}
+ pr_debug("%s: protect count is %d\n", __func__,
+ atomic_read(&cp_heap->protect_cnt));
+ BUG_ON(atomic_read(&cp_heap->protect_cnt) < 0);
}
ion_phys_addr_t ion_cp_allocate(struct ion_heap *heap,
@@ -925,6 +933,7 @@
cp_heap->secure_base = cp_heap->base;
cp_heap->secure_size = heap_data->size;
cp_heap->has_outer_cache = heap_data->has_outer_cache;
+ atomic_set(&cp_heap->protect_cnt, 0);
if (heap_data->extra_data) {
struct ion_cp_heap_pdata *extra_data =
heap_data->extra_data;
diff --git a/drivers/gpu/ion/ion_iommu_heap.c b/drivers/gpu/ion/ion_iommu_heap.c
index 621144b..9ea6f2b 100644
--- a/drivers/gpu/ion/ion_iommu_heap.c
+++ b/drivers/gpu/ion/ion_iommu_heap.c
@@ -196,7 +196,7 @@
data->mapped_size, align,
&data->iova_addr);
- if (!data->iova_addr)
+ if (ret)
goto out;
domain = msm_get_iommu_domain(domain_num);
diff --git a/drivers/gpu/ion/msm/Makefile b/drivers/gpu/ion/msm/Makefile
index bedd8d2..1893405 100644
--- a/drivers/gpu/ion/msm/Makefile
+++ b/drivers/gpu/ion/msm/Makefile
@@ -1 +1 @@
-obj-y += msm_ion.o
+obj-y += msm_ion.o ion_cp_common.o
diff --git a/drivers/gpu/ion/msm/ion_cp_common.c b/drivers/gpu/ion/msm/ion_cp_common.c
new file mode 100644
index 0000000..b274ba2
--- /dev/null
+++ b/drivers/gpu/ion/msm/ion_cp_common.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2011 Google, Inc
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <mach/scm.h>
+
+#include "ion_cp_common.h"
+
+#define MEM_PROTECT_LOCK_ID 0x05
+
+struct cp2_mem_chunks {
+ unsigned int *chunk_list;
+ unsigned int chunk_list_size;
+ unsigned int chunk_size;
+} __attribute__ ((__packed__));
+
+struct cp2_lock_req {
+ struct cp2_mem_chunks chunks;
+ unsigned int mem_usage;
+ unsigned int lock;
+} __attribute__ ((__packed__));
+
+int ion_cp_change_chunks_state(unsigned long chunks, unsigned int nchunks,
+ unsigned int chunk_size,
+ enum cp_mem_usage usage,
+ int lock)
+{
+ struct cp2_lock_req request;
+
+ request.mem_usage = usage;
+ request.lock = lock;
+
+ request.chunks.chunk_list = (unsigned int *)chunks;
+ request.chunks.chunk_list_size = nchunks;
+ request.chunks.chunk_size = chunk_size;
+
+ return scm_call(SCM_SVC_CP, MEM_PROTECT_LOCK_ID,
+ &request, sizeof(request), NULL, 0);
+
+}
+
diff --git a/drivers/gpu/ion/msm/ion_cp_common.h b/drivers/gpu/ion/msm/ion_cp_common.h
new file mode 100644
index 0000000..ae66128
--- /dev/null
+++ b/drivers/gpu/ion/msm/ion_cp_common.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ION_CP_COMMON_H
+#define ION_CP_COMMON_H
+
+#include <asm-generic/errno-base.h>
+#include <linux/ion.h>
+
+#if defined(CONFIG_ION_MSM)
+/*
+ * ion_cp2_protect_mem - secures memory via trustzone
+ *
+ * @chunks - physical address of the array containing the chunks to
+ * be locked down
+ * @nchunks - number of entries in the array
+ * @chunk_size - size of each memory chunk
+ * @usage - usage hint
+ * @lock - 1 for lock, 0 for unlock
+ *
+ * return value is the result of the scm call
+ */
+int ion_cp_change_chunks_state(unsigned long chunks, unsigned int nchunks,
+ unsigned int chunk_size, enum cp_mem_usage usage,
+ int lock);
+
+#else
+static inline int ion_cp_change_chunks_state(unsigned long chunks,
+ unsigned int nchunks, unsigned int chunk_size,
+ enum cp_mem_usage usage, int lock)
+{
+ return -ENODEV;
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 3de3af9..4991a2e 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -1592,10 +1592,17 @@
adreno_dev->gpudev->irq_control(adreno_dev, state);
}
-static unsigned int adreno_gpuid(struct kgsl_device *device)
+static unsigned int adreno_gpuid(struct kgsl_device *device,
+ unsigned int *chipid)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ /* Some applications need to know the chip ID too, so pass
+ * that as a parameter */
+
+ if (chipid != NULL)
+ *chipid = adreno_dev->chip_id;
+
/* Standard KGSL gpuid format:
* top word is 0x0002 for 2D or 0x0003 for 3D
* Bottom word is core specific identifer
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index c3c266e..d846d3d 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -1450,43 +1450,55 @@
return ret;
}
-static void a2xx_drawctxt_draw_workaround(struct adreno_device *adreno_dev)
+static void a2xx_drawctxt_workaround(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int cmd[11];
unsigned int *cmds = &cmd[0];
- adreno_dev->gpudev->ctx_switches_since_last_draw++;
- /* If there have been > than ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW
- * calls to context switches w/o gmem being saved then we need to
- * execute this workaround */
- if (adreno_dev->gpudev->ctx_switches_since_last_draw >
- ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW)
- adreno_dev->gpudev->ctx_switches_since_last_draw = 0;
- else
- return;
- /*
- * Issue an empty draw call to avoid possible hangs due to
- * repeated idles without intervening draw calls.
- * On adreno 225 the PC block has a cache that is only
- * flushed on draw calls and repeated idles can make it
- * overflow. The gmem save path contains draw calls so
- * this workaround isn't needed there.
- */
- *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
- *cmds++ = (0x4 << 16) | (REG_PA_SU_SC_MODE_CNTL - 0x2000);
- *cmds++ = 0;
- *cmds++ = cp_type3_packet(CP_DRAW_INDX, 5);
- *cmds++ = 0;
- *cmds++ = 1<<14;
- *cmds++ = 0;
- *cmds++ = device->mmu.setstate_memory.gpuaddr;
- *cmds++ = 0;
- *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
- *cmds++ = 0x00000000;
+ if (adreno_is_a225(adreno_dev)) {
+ adreno_dev->gpudev->ctx_switches_since_last_draw++;
+ /* If there have been > than
+ * ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW calls to context
+ * switches w/o gmem being saved then we need to execute
+ * this workaround */
+ if (adreno_dev->gpudev->ctx_switches_since_last_draw >
+ ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW)
+ adreno_dev->gpudev->ctx_switches_since_last_draw = 0;
+ else
+ return;
+ /*
+ * Issue an empty draw call to avoid possible hangs due to
+ * repeated idles without intervening draw calls.
+ * On adreno 225 the PC block has a cache that is only
+ * flushed on draw calls and repeated idles can make it
+ * overflow. The gmem save path contains draw calls so
+ * this workaround isn't needed there.
+ */
+ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
+ *cmds++ = (0x4 << 16) | (REG_PA_SU_SC_MODE_CNTL - 0x2000);
+ *cmds++ = 0;
+ *cmds++ = cp_type3_packet(CP_DRAW_INDX, 5);
+ *cmds++ = 0;
+ *cmds++ = 1<<14;
+ *cmds++ = 0;
+ *cmds++ = device->mmu.setstate_memory.gpuaddr;
+ *cmds++ = 0;
+ *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
+ *cmds++ = 0x00000000;
+ } else {
+ /* On Adreno 20x/220, if the events for shader space reuse
+ * gets dropped, the CP block would wait indefinitely.
+ * Sending CP_SET_SHADER_BASES packet unblocks the CP from
+ * this wait.
+ */
+ *cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
+ *cmds++ = adreno_encode_istore_size(adreno_dev)
+ | adreno_dev->pix_shader_start;
+ }
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
- &cmd[0], 11);
+ &cmd[0], cmds - cmd);
}
static void a2xx_drawctxt_save(struct adreno_device *adreno_dev,
@@ -1540,8 +1552,8 @@
adreno_dev->gpudev->ctx_switches_since_last_draw = 0;
context->flags |= CTXT_FLAGS_GMEM_RESTORE;
- } else if (adreno_is_a225(adreno_dev))
- a2xx_drawctxt_draw_workaround(adreno_dev);
+ } else if (adreno_is_a2xx(adreno_dev))
+ a2xx_drawctxt_workaround(adreno_dev);
}
static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
@@ -1999,7 +2011,7 @@
.ctxt_create = a2xx_drawctxt_create,
.ctxt_save = a2xx_drawctxt_save,
.ctxt_restore = a2xx_drawctxt_restore,
- .ctxt_draw_workaround = a2xx_drawctxt_draw_workaround,
+ .ctxt_draw_workaround = a2xx_drawctxt_workaround,
.irq_handler = a2xx_irq_handler,
.irq_control = a2xx_irq_control,
.snapshot = a2xx_snapshot,
diff --git a/drivers/gpu/msm/adreno_a3xx_snapshot.c b/drivers/gpu/msm/adreno_a3xx_snapshot.c
index c8c7c44..60aab64 100644
--- a/drivers/gpu/msm/adreno_a3xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a3xx_snapshot.c
@@ -19,6 +19,29 @@
#define DEBUG_SECTION_SZ(_dwords) (((_dwords) * sizeof(unsigned int)) \
+ sizeof(struct kgsl_snapshot_debug))
+#define SHADER_MEMORY_SIZE 0x4000
+
+static int a3xx_snapshot_shader_memory(struct kgsl_device *device,
+ void *snapshot, int remain, void *priv)
+{
+ struct kgsl_snapshot_debug *header = snapshot;
+ unsigned int *data = snapshot + sizeof(*header);
+ int i;
+
+ if (remain < DEBUG_SECTION_SZ(SHADER_MEMORY_SIZE)) {
+ SNAPSHOT_ERR_NOMEM(device, "SHADER MEMORY");
+ return 0;
+ }
+
+ header->type = SNAPSHOT_DEBUG_SHADER_MEMORY;
+ header->size = SHADER_MEMORY_SIZE;
+
+ for (i = 0; i < SHADER_MEMORY_SIZE; i++)
+ adreno_regread(device, 0x4000 + i, &data[i]);
+
+ return DEBUG_SECTION_SZ(SHADER_MEMORY_SIZE);
+}
+
#define VPC_MEMORY_BANKS 4
#define VPC_MEMORY_SIZE 512
@@ -272,6 +295,12 @@
KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain,
a3xx_snapshot_cp_meq, NULL);
+ /* Shader working/shadow memory */
+ snapshot = kgsl_snapshot_add_section(device,
+ KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain,
+ a3xx_snapshot_shader_memory, NULL);
+
+
/* CP PFP and PM4 */
/* Reading these will hang the GPU if it isn't already hung */
diff --git a/drivers/gpu/msm/adreno_drawctxt.c b/drivers/gpu/msm/adreno_drawctxt.c
index 49d035f..267fd45 100644
--- a/drivers/gpu/msm/adreno_drawctxt.c
+++ b/drivers/gpu/msm/adreno_drawctxt.c
@@ -199,7 +199,7 @@
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_context *drawctxt;
- if (context == NULL)
+ if (context == NULL || context->devctxt == NULL)
return;
drawctxt = context->devctxt;
diff --git a/drivers/gpu/msm/adreno_pm4types.h b/drivers/gpu/msm/adreno_pm4types.h
index fb44b25..016862b 100644
--- a/drivers/gpu/msm/adreno_pm4types.h
+++ b/drivers/gpu/msm/adreno_pm4types.h
@@ -203,7 +203,14 @@
#define type0_pkt_size(pkt) ((((pkt) >> 16) & 0x3FFF) + 1)
#define type0_pkt_offset(pkt) ((pkt) & 0x7FFF)
-#define pkt_is_type3(pkt) (((pkt) & 0xC0000000) == CP_TYPE3_PKT)
+/*
+ * Check both for the type3 opcode and make sure that the reserved bits [1:7]
+ * and 15 are 0
+ */
+
+#define pkt_is_type3(pkt) \
+ ((((pkt) & 0xC0000000) == CP_TYPE3_PKT) && \
+ (((pkt) & 0x80FE) == 0))
#define cp_type3_opcode(pkt) (((pkt) >> 8) & 0xFF)
#define type3_pkt_size(pkt) ((((pkt) >> 16) & 0x3FFF) + 1)
diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c
index 5572695..08a01b0 100644
--- a/drivers/gpu/msm/adreno_snapshot.c
+++ b/drivers/gpu/msm/adreno_snapshot.c
@@ -161,6 +161,22 @@
static unsigned int sp_vs_pvt_mem_addr;
static unsigned int sp_fs_pvt_mem_addr;
+/*
+ * Each load state block has two possible types. Each type has a different
+ * number of dwords per unit. Use this handy lookup table to make sure
+ * we dump the right amount of data from the indirect buffer
+ */
+
+static int load_state_unit_sizes[7][2] = {
+ { 2, 4 },
+ { 0, 1 },
+ { 2, 4 },
+ { 0, 1 },
+ { 8, 2 },
+ { 8, 2 },
+ { 8, 2 },
+};
+
static void ib_parse_load_state(struct kgsl_device *device, unsigned int *pkt,
unsigned int ptbase)
{
@@ -170,11 +186,9 @@
* The object here is to find indirect shaders i.e - shaders loaded from
* GPU memory instead of directly in the command. These should be added
* to the list of memory objects to dump. So look at the load state
- * call and see if 1) the shader block is a shader (block = 4, 5 or 6)
- * 2) that the block is indirect (source = 4). If these all match then
- * add the memory address to the list. The size of the object will
- * differ depending on the type. Type 0 (instructions) are 8 dwords per
- * unit and type 1 (constants) are 2 dwords per unit.
+ * if the block is indirect (source = 4). If so then add the memory
+ * address to the list. The size of the object differs depending on the
+ * type per the load_state_unit_sizes array above.
*/
if (type3_pkt_size(pkt[0]) < 2)
@@ -192,9 +206,13 @@
source = (pkt[1] >> 16) & 0x07;
type = pkt[2] & 0x03;
- if ((block == 4 || block == 5 || block == 6) && source == 4) {
- int unitsize = (type == 0) ? 8 : 2;
- int ret;
+ if (source == 4) {
+ int unitsize, ret;
+
+ if (type == 0)
+ unitsize = load_state_unit_sizes[block][0];
+ else
+ unitsize = load_state_unit_sizes[block][1];
/* Freeze the GPU buffer containing the shader */
@@ -528,7 +546,6 @@
unsigned int ptbase, rptr, *rbptr, ibbase;
int index, size, i;
int parse_ibs = 0, ib_parse_start;
- int skip_pktsize = 1;
/* Get the physical address of the MMU pagetable */
ptbase = kgsl_mmu_get_current_ptbase(&device->mmu);
@@ -541,13 +558,14 @@
/*
* Figure out the window of ringbuffer data to dump. First we need to
- * find where the last processed IB ws submitted
+ * find where the last processed IB ws submitted. Start walking back
+ * from the rptr
*/
index = rptr;
rbptr = rb->buffer_desc.hostptr;
- while (index != rb->wptr) {
+ do {
index--;
if (index < 0) {
@@ -563,7 +581,7 @@
if (adreno_cmd_is_ib(rbptr[index]) &&
rbptr[index + 1] == ibbase)
break;
- }
+ } while (index != rb->wptr);
/*
* index points at the last submitted IB. We can only trust that the
@@ -636,18 +654,15 @@
* try to adust for that by modifying the rptr to match a
* packet boundary. Unfortunately for us, it is hard to tell
* which dwords are legitimate type0 header and which are just
- * random data so just walk over type0 packets until we get
- * to the first type3, and from that point on start checking the
- * size of the packet and adjusting accordingly
+ * random data so only do the adjustments for type3 packets
*/
- if (skip_pktsize && pkt_is_type3(rbptr[index]))
- skip_pktsize = 0;
-
- if (skip_pktsize == 0) {
- unsigned int pktsize = type3_pkt_size(rbptr[index]);
+ if (pkt_is_type3(rbptr[index])) {
+ unsigned int pktsize =
+ type3_pkt_size(rbptr[index]);
if (index + pktsize > rptr)
- rptr = (index + pktsize) % rb->sizedwords;
+ rptr = (index + pktsize) %
+ rb->sizedwords;
}
/*
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 81de64f..5883f08 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -2598,9 +2598,17 @@
kgsl_drm_exit();
kgsl_cffdump_destroy();
kgsl_core_debugfs_close();
- kgsl_sharedmem_uninit_sysfs();
- device_unregister(&kgsl_driver.virtdev);
+ /*
+ * We call kgsl_sharedmem_uninit_sysfs() and device_unregister()
+ * only if kgsl_driver.virtdev has been populated.
+ * We check at least one member of kgsl_driver.virtdev to
+ * see if it is not NULL (and thus, has been populated).
+ */
+ if (kgsl_driver.virtdev.class) {
+ kgsl_sharedmem_uninit_sysfs();
+ device_unregister(&kgsl_driver.virtdev);
+ }
if (kgsl_driver.class) {
class_destroy(kgsl_driver.class);
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index 64acff8..932c995 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -90,7 +90,7 @@
void (*power_stats)(struct kgsl_device *device,
struct kgsl_power_stats *stats);
void (*irqctrl)(struct kgsl_device *device, int state);
- unsigned int (*gpuid)(struct kgsl_device *device);
+ unsigned int (*gpuid)(struct kgsl_device *device, unsigned int *chipid);
void * (*snapshot)(struct kgsl_device *device, void *snapshot,
int *remain, int hang);
irqreturn_t (*irq_handler)(struct kgsl_device *device);
@@ -287,9 +287,10 @@
return device->ftbl->idle(device, timeout);
}
-static inline unsigned int kgsl_gpuid(struct kgsl_device *device)
+static inline unsigned int kgsl_gpuid(struct kgsl_device *device,
+ unsigned int *chipid)
{
- return device->ftbl->gpuid(device);
+ return device->ftbl->gpuid(device, chipid);
}
static inline unsigned int kgsl_readtimestamp(struct kgsl_device *device,
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index b3f2d1e..e42c7b6 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -837,6 +837,10 @@
{
unsigned int pt_base;
struct kgsl_iommu *iommu = mmu->priv;
+ /* We cannot enable or disable the clocks in interrupt context, this
+ function is called from interrupt context if there is an axi error */
+ if (in_interrupt())
+ return 0;
/* Return the current pt base by reading IOMMU pt_base register */
kgsl_iommu_enable_clk(mmu, KGSL_IOMMU_CONTEXT_USER);
pt_base = readl_relaxed(iommu->iommu_units[0].reg_map.hostptr +
diff --git a/drivers/gpu/msm/kgsl_snapshot.c b/drivers/gpu/msm/kgsl_snapshot.c
index 8935b29..824d806 100644
--- a/drivers/gpu/msm/kgsl_snapshot.c
+++ b/drivers/gpu/msm/kgsl_snapshot.c
@@ -35,6 +35,56 @@
struct list_head node;
};
+struct snapshot_obj_itr {
+ void *buf; /* Buffer pointer to write to */
+ int pos; /* Current position in the sequence */
+ loff_t offset; /* file offset to start writing from */
+ size_t remain; /* Bytes remaining in buffer */
+ size_t write; /* Bytes written so far */
+};
+
+static void obj_itr_init(struct snapshot_obj_itr *itr, void *buf,
+ loff_t offset, size_t remain)
+{
+ itr->buf = buf;
+ itr->offset = offset;
+ itr->remain = remain;
+ itr->pos = 0;
+ itr->write = 0;
+}
+
+static int obj_itr_out(struct snapshot_obj_itr *itr, void *src, int size)
+{
+ if (itr->remain == 0)
+ return 0;
+
+ if ((itr->pos + size) <= itr->offset)
+ goto done;
+
+ /* Handle the case that offset is in the middle of the buffer */
+
+ if (itr->offset > itr->pos) {
+ src += (itr->offset - itr->pos);
+ size -= (itr->offset - itr->pos);
+
+ /* Advance pos to the offset start */
+ itr->pos = itr->offset;
+ }
+
+ if (size > itr->remain)
+ size = itr->remain;
+
+ memcpy(itr->buf, src, size);
+
+ itr->buf += size;
+ itr->write += size;
+ itr->remain -= size;
+
+done:
+ itr->pos += size;
+ return size;
+}
+
/* idr_for_each function to count the number of contexts */
static int snapshot_context_count(int id, void *ptr, void *data)
@@ -182,76 +232,46 @@
(sizeof(struct kgsl_snapshot_section_header) + \
sizeof(struct kgsl_snapshot_gpu_object))
-#define GPU_OBJ_SECTION_SIZE(_o) \
- (GPU_OBJ_HEADER_SZ + ((_o)->size))
-
static int kgsl_snapshot_dump_object(struct kgsl_device *device,
- struct kgsl_snapshot_object *obj, void *buf,
- unsigned int off, unsigned int count)
+ struct kgsl_snapshot_object *obj, struct snapshot_obj_itr *itr)
{
- unsigned char headers[GPU_OBJ_HEADER_SZ];
- struct kgsl_snapshot_section_header *sect =
- (struct kgsl_snapshot_section_header *) headers;
- struct kgsl_snapshot_gpu_object *header =
- (struct kgsl_snapshot_gpu_object *) (headers + sizeof(*sect));
- int ret = 0;
+ struct kgsl_snapshot_section_header sect;
+ struct kgsl_snapshot_gpu_object header;
+ int ret;
- /* Construct a local copy of the headers */
+ sect.magic = SNAPSHOT_SECTION_MAGIC;
+ sect.id = KGSL_SNAPSHOT_SECTION_GPU_OBJECT;
- sect->magic = SNAPSHOT_SECTION_MAGIC;
- sect->id = KGSL_SNAPSHOT_SECTION_GPU_OBJECT;
- sect->size = GPU_OBJ_SECTION_SIZE(obj);
+ /*
+ * Header size is in dwords, object size is in bytes -
+ * round up if the object size isn't dword aligned
+ */
- header->type = obj->type;
+ sect.size = GPU_OBJ_HEADER_SZ + ALIGN(obj->size, 4);
- /* Header size is in dwords, object size is in bytes */
- header->size = obj->size >> 2;
- header->gpuaddr = obj->gpuaddr;
- header->ptbase = obj->ptbase;
+ ret = obj_itr_out(itr, §, sizeof(sect));
+ if (ret == 0)
+ return 0;
- /* Copy out any part of the header block that is needed */
+ header.size = ALIGN(obj->size, 4) >> 2;
+ header.gpuaddr = obj->gpuaddr;
+ header.ptbase = obj->ptbase;
+ header.type = obj->type;
- if (off < GPU_OBJ_HEADER_SZ) {
- int size = count < GPU_OBJ_HEADER_SZ - off ?
- count : GPU_OBJ_HEADER_SZ - off;
+ ret = obj_itr_out(itr, &header, sizeof(header));
+ if (ret == 0)
+ return 0;
- memcpy(buf, headers + off, size);
+ ret = obj_itr_out(itr, obj->entry->memdesc.hostptr + obj->offset,
+ obj->size);
+ if (ret == 0)
+ return 0;
- count -= size;
- ret += size;
- }
+ /* Pad the end to a dword boundary if we need to */
- /* Now copy whatever part of the data is needed */
-
- if (off < (GPU_OBJ_HEADER_SZ + obj->size)) {
- int offset;
- int size = count < obj->size ? count : obj->size;
-
- /*
- * If the desired gpuaddr isn't at the beginning of the region,
- * then offset the source pointer
- */
-
- offset = obj->offset;
-
- /*
- * Then adjust it to account for the offset for the output
- * buffer.
- */
-
- if (off > GPU_OBJ_HEADER_SZ) {
- int loff = (off - GPU_OBJ_HEADER_SZ);
-
- /* Adjust the size so we don't walk off the end */
-
- if ((loff + size) > obj->size)
- size = obj->size - loff;
-
- offset += loff;
- }
-
- memcpy(buf + ret, obj->entry->memdesc.hostptr + offset, size);
- ret += size;
+ if (obj->size % 4) {
+ unsigned int dummy = 0;
+ ret = obj_itr_out(itr, &dummy, obj->size % 4);
}
return ret;
@@ -488,7 +508,7 @@
header->magic = SNAPSHOT_MAGIC;
- header->gpuid = kgsl_gpuid(device);
+ header->gpuid = kgsl_gpuid(device, &header->chipid);
/* Get a pointer to the first section (right after the header) */
snapshot = ((void *) device->snapshot) + sizeof(*header);
@@ -539,7 +559,9 @@
{
struct kgsl_device *device = kobj_to_device(kobj);
struct kgsl_snapshot_object *obj, *tmp;
- unsigned int size, src, dst = 0;
+ struct kgsl_snapshot_section_header head;
+ struct snapshot_obj_itr itr;
+ int ret;
if (device == NULL)
return 0;
@@ -551,80 +573,46 @@
/* Get the mutex to keep things from changing while we are dumping */
mutex_lock(&device->mutex);
- if (off < device->snapshot_size) {
- size = count < (device->snapshot_size - off) ?
- count : device->snapshot_size - off;
+ obj_itr_init(&itr, buf, off, count);
- memcpy(buf, device->snapshot + off, size);
+ ret = obj_itr_out(&itr, device->snapshot, device->snapshot_size);
- count -= size;
- dst += size;
- }
-
- if (count == 0)
+ if (ret == 0)
goto done;
- src = device->snapshot_size;
+ list_for_each_entry(obj, &device->snapshot_obj_list, node)
+ kgsl_snapshot_dump_object(device, obj, &itr);
- list_for_each_entry(obj, &device->snapshot_obj_list, node) {
+ {
+ head.magic = SNAPSHOT_SECTION_MAGIC;
+ head.id = KGSL_SNAPSHOT_SECTION_END;
+ head.size = sizeof(head);
- int objsize = GPU_OBJ_SECTION_SIZE(obj);
- int offset;
-
- /* If the offset is beyond this object, then move on */
-
- if (off >= (src + objsize)) {
- src += objsize;
- continue;
- }
-
- /* Adjust the offset to be relative to the object */
- offset = (off >= src) ? (off - src) : 0;
-
- size = kgsl_snapshot_dump_object(device, obj, buf + dst,
- offset, count);
-
- count -= size;
- dst += size;
-
- if (count == 0)
- goto done;
-
- /* Move on to the next object - update src accordingly */
- src += objsize;
+ obj_itr_out(&itr, &head, sizeof(head));
}
- /* Add the end section */
+ /*
+ * Make sure everything has been written out before destroying things.
+ * The best way to confirm this is to go all the way through without
+ * writing any bytes - so only release if we get this far and
+ * itr->write is 0
+ */
- if (off < (src + sizeof(struct kgsl_snapshot_section_header))) {
- if (count >= sizeof(struct kgsl_snapshot_section_header)) {
- struct kgsl_snapshot_section_header *head =
- (void *) (buf + dst);
+ if (itr.write == 0) {
+ list_for_each_entry_safe(obj, tmp, &device->snapshot_obj_list,
+ node)
+ kgsl_snapshot_put_object(device, obj);
- head->magic = SNAPSHOT_SECTION_MAGIC;
- head->id = KGSL_SNAPSHOT_SECTION_END;
- head->size = sizeof(*head);
+ if (device->snapshot_frozen)
+ KGSL_DRV_ERR(device, "Snapshot objects released\n");
- dst += sizeof(*head);
- } else {
- goto done;
- }
+ device->snapshot_frozen = 0;
}
- /* Release the buffers and unfreeze the snapshot */
-
- list_for_each_entry_safe(obj, tmp, &device->snapshot_obj_list, node)
- kgsl_snapshot_put_object(device, obj);
-
- if (device->snapshot_frozen)
- KGSL_DRV_ERR(device, "Snapshot objects released\n");
-
- device->snapshot_frozen = 0;
-
done:
mutex_unlock(&device->mutex);
- return dst;
+ return itr.write;
}
/* Show the timestamp of the last collected snapshot */
diff --git a/drivers/gpu/msm/kgsl_snapshot.h b/drivers/gpu/msm/kgsl_snapshot.h
index 304f4bb..d54afcf 100644
--- a/drivers/gpu/msm/kgsl_snapshot.h
+++ b/drivers/gpu/msm/kgsl_snapshot.h
@@ -18,7 +18,8 @@
/* Snapshot header */
-#define SNAPSHOT_MAGIC 0x504D0001
+/* High word is static, low word is snapshot version ID */
+#define SNAPSHOT_MAGIC 0x504D0002
/* GPU ID scheme:
* [16:31] - core identifer (0x0002 for 2D or 0x0003 for 3D)
@@ -28,6 +29,8 @@
struct kgsl_snapshot_header {
__u32 magic; /* Magic identifier */
__u32 gpuid; /* GPU ID - see above */
+ /* Added in snapshot version 2 */
+ __u32 chipid; /* Chip ID from the GPU */
} __packed;
/* Section header */
@@ -140,6 +143,7 @@
#define SNAPSHOT_DEBUG_CP_PM4_RAM 8
#define SNAPSHOT_DEBUG_CP_PFP_RAM 9
#define SNAPSHOT_DEBUG_CP_ROQ 10
+#define SNAPSHOT_DEBUG_SHADER_MEMORY 11
struct kgsl_snapshot_debug {
int type; /* Type identifier for the attached tata */
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index f4bbf69..bc2685c 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -896,8 +896,11 @@
}
}
-static unsigned int z180_gpuid(struct kgsl_device *device)
+static unsigned int z180_gpuid(struct kgsl_device *device, unsigned int *chipid)
{
+ if (chipid != NULL)
+ *chipid = 0;
+
/* Standard KGSL gpuid format:
* top word is 0x0002 for 2D or 0x0003 for 3D
* Bottom word is core specific identifer
diff --git a/drivers/i2c/busses/i2c-msm.c b/drivers/i2c/busses/i2c-msm.c
index b753fd0..4b48a69 100644
--- a/drivers/i2c/busses/i2c-msm.c
+++ b/drivers/i2c/busses/i2c-msm.c
@@ -636,7 +636,7 @@
spin_lock_init(&dev->lock);
platform_set_drvdata(pdev, dev);
- clk_enable(clk);
+ clk_prepare_enable(clk);
if (pdata->rmutex) {
struct remote_mutex_id rmid;
@@ -697,7 +697,8 @@
/* Config GPIOs for primary and secondary lines */
pdata->msm_i2c_config_gpio(dev->adap_pri.nr, 1);
pdata->msm_i2c_config_gpio(dev->adap_aux.nr, 1);
- clk_disable(dev->clk);
+ clk_disable_unprepare(dev->clk);
+ clk_prepare(dev->clk);
setup_timer(&dev->pwr_timer, msm_i2c_pwr_timer, (unsigned long) dev);
return 0;
@@ -706,7 +707,7 @@
i2c_del_adapter(&dev->adap_pri);
i2c_del_adapter(&dev->adap_aux);
err_i2c_add_adapter_failed:
- clk_disable(clk);
+ clk_disable_unprepare(clk);
iounmap(dev->base);
err_ioremap_failed:
kfree(dev);
@@ -736,6 +737,7 @@
free_irq(dev->irq, dev);
i2c_del_adapter(&dev->adap_pri);
i2c_del_adapter(&dev->adap_aux);
+ clk_unprepare(dev->clk);
clk_put(dev->clk);
iounmap(dev->base);
kfree(dev);
@@ -759,6 +761,7 @@
del_timer_sync(&dev->pwr_timer);
if (dev->clk_state != 0)
msm_i2c_pwr_mgmt(dev, 0);
+ clk_unprepare(dev->clk);
}
return 0;
@@ -767,6 +770,7 @@
static int msm_i2c_resume(struct platform_device *pdev)
{
struct msm_i2c_dev *dev = platform_get_drvdata(pdev);
+ clk_prepare(dev->clk);
dev->suspended = 0;
return 0;
}
diff --git a/drivers/input/misc/mpu3050.c b/drivers/input/misc/mpu3050.c
index 5403c57..8b6e172 100644
--- a/drivers/input/misc/mpu3050.c
+++ b/drivers/input/misc/mpu3050.c
@@ -40,6 +40,8 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
+#include <linux/input/mpu3050.h>
+#include <linux/regulator/consumer.h>
#define MPU3050_CHIP_ID 0x69
@@ -112,8 +114,81 @@
struct i2c_client *client;
struct device *dev;
struct input_dev *idev;
+ struct mpu3050_gyro_platform_data *platform_data;
+ struct delayed_work input_work;
+ u32 use_poll;
};
+struct sensor_regulator {
+ struct regulator *vreg;
+ const char *name;
+ u32 min_uV;
+ u32 max_uV;
+};
+
+struct sensor_regulator mpu_vreg[] = {
+ {NULL, "vdd", 2100000, 3600000},
+ {NULL, "vlogic", 1800000, 1800000},
+};
+
+static int mpu3050_config_regulator(struct i2c_client *client, bool on)
+{
+ int rc = 0, i;
+ int num_reg = sizeof(mpu_vreg) / sizeof(struct sensor_regulator);
+
+ if (on) {
+ for (i = 0; i < num_reg; i++) {
+ mpu_vreg[i].vreg = regulator_get(&client->dev,
+ mpu_vreg[i].name);
+ if (IS_ERR(mpu_vreg[i].vreg)) {
+ rc = PTR_ERR(mpu_vreg[i].vreg);
+ pr_err("%s:regulator get failed rc=%d\n",
+ __func__, rc);
+ goto error_vdd;
+ }
+
+ if (regulator_count_voltages(mpu_vreg[i].vreg) > 0) {
+ rc = regulator_set_voltage(mpu_vreg[i].vreg,
+ mpu_vreg[i].min_uV, mpu_vreg[i].max_uV);
+ if (rc) {
+ pr_err("%s:set_voltage failed rc=%d\n",
+ __func__, rc);
+ regulator_put(mpu_vreg[i].vreg);
+ goto error_vdd;
+ }
+ }
+
+ rc = regulator_enable(mpu_vreg[i].vreg);
+ if (rc) {
+ pr_err("%s: regulator_enable failed rc =%d\n",
+ __func__,
+ rc);
+
+ if (regulator_count_voltages(
+ mpu_vreg[i].vreg) > 0) {
+ regulator_set_voltage(mpu_vreg[i].vreg,
+ 0, mpu_vreg[i].max_uV);
+ }
+ regulator_put(mpu_vreg[i].vreg);
+ goto error_vdd;
+ }
+ }
+ return rc;
+ } else {
+ i = num_reg;
+ }
+error_vdd:
+ while (--i >= 0) {
+ if (regulator_count_voltages(mpu_vreg[i].vreg) > 0) {
+ regulator_set_voltage(mpu_vreg[i].vreg, 0,
+ mpu_vreg[i].max_uV);
+ }
+ regulator_disable(mpu_vreg[i].vreg);
+ regulator_put(mpu_vreg[i].vreg);
+ }
+ return rc;
+}
+
/**
* mpu3050_xyz_read_reg - read the axes values
* @buffer: provide register addr and get register
@@ -179,11 +254,21 @@
{
u8 value;
+ if (val) {
+ mpu3050_config_regulator(client, 1);
+ udelay(10);
+ }
+
value = i2c_smbus_read_byte_data(client, MPU3050_PWR_MGM);
value = (value & ~MPU3050_PWR_MGM_MASK) |
(((val << MPU3050_PWR_MGM_POS) & MPU3050_PWR_MGM_MASK) ^
MPU3050_PWR_MGM_MASK);
i2c_smbus_write_byte_data(client, MPU3050_PWR_MGM, value);
+
+ if (!val) {
+ udelay(10);
+ mpu3050_config_regulator(client, 0);
+ }
}
/**
@@ -210,6 +295,9 @@
pm_runtime_put(sensor->dev);
return error;
}
+ if (sensor->use_poll)
+ schedule_delayed_work(&sensor->input_work,
+ msecs_to_jiffies(MPU3050_DEFAULT_POLL_INTERVAL));
return 0;
}
@@ -225,6 +313,9 @@
{
struct mpu3050_sensor *sensor = input_get_drvdata(input);
+ if (sensor->use_poll)
+ cancel_delayed_work_sync(&sensor->input_work);
+
pm_runtime_put(sensor->dev);
}
@@ -252,6 +343,33 @@
}
/**
+ * mpu3050_input_work_fn - polling work
+ * @work: the work struct
+ *
+ * Called by the work queue; read sensor data and generate an input
+ * event
+ */
+static void mpu3050_input_work_fn(struct work_struct *work)
+{
+ struct mpu3050_sensor *sensor;
+ struct axis_data axis;
+
+ sensor = container_of((struct delayed_work *)work,
+ struct mpu3050_sensor, input_work);
+
+ mpu3050_read_xyz(sensor->client, &axis);
+
+ input_report_abs(sensor->idev, ABS_X, axis.x);
+ input_report_abs(sensor->idev, ABS_Y, axis.y);
+ input_report_abs(sensor->idev, ABS_Z, axis.z);
+ input_sync(sensor->idev);
+
+ if (sensor->use_poll)
+ schedule_delayed_work(&sensor->input_work,
+ msecs_to_jiffies(MPU3050_DEFAULT_POLL_INTERVAL));
+}
+
+/**
* mpu3050_hw_init - initialize hardware
* @sensor: the sensor
*
@@ -325,6 +443,7 @@
sensor->client = client;
sensor->dev = &client->dev;
sensor->idev = idev;
+ sensor->platform_data = client->dev.platform_data;
mpu3050_set_power_mode(client, 1);
msleep(10);
@@ -365,14 +484,22 @@
if (error)
goto err_pm_set_suspended;
- error = request_threaded_irq(client->irq,
+ if (client->irq == 0) {
+ INIT_DELAYED_WORK(&sensor->input_work, mpu3050_input_work_fn);
+ sensor->use_poll = 1;
+ } else {
+ sensor->use_poll = 0;
+
+ error = request_threaded_irq(client->irq,
NULL, mpu3050_interrupt_thread,
IRQF_TRIGGER_RISING,
"mpu3050", sensor);
- if (error) {
- dev_err(&client->dev,
- "can't get IRQ %d, error %d\n", client->irq, error);
- goto err_pm_set_suspended;
+ if (error) {
+ dev_err(&client->dev,
+ "can't get IRQ %d, error %d\n",
+ client->irq, error);
+ goto err_pm_set_suspended;
+ }
}
error = input_register_device(idev);
@@ -387,7 +514,8 @@
return 0;
err_free_irq:
- free_irq(client->irq, sensor);
+ if (client->irq > 0)
+ free_irq(client->irq, sensor);
err_pm_set_suspended:
pm_runtime_set_suspended(&client->dev);
err_free_mem:
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index 09ff05d..23317d6 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -2296,6 +2296,7 @@
__set_bit(EV_ABS, input_dev->evbit);
__set_bit(EV_KEY, input_dev->evbit);
__set_bit(BTN_TOUCH, input_dev->keybit);
+ __set_bit(INPUT_PROP_DIRECT, input_dev->propbit);
/* For single touch */
input_set_abs_params(input_dev, ABS_X,
diff --git a/drivers/input/touchscreen/cyttsp-i2c-qc.c b/drivers/input/touchscreen/cyttsp-i2c-qc.c
index e82dd13..5af4534 100644
--- a/drivers/input/touchscreen/cyttsp-i2c-qc.c
+++ b/drivers/input/touchscreen/cyttsp-i2c-qc.c
@@ -2510,6 +2510,8 @@
set_bit(EV_ABS, input_device->evbit);
set_bit(BTN_TOUCH, input_device->keybit);
set_bit(BTN_2, input_device->keybit);
+ set_bit(INPUT_PROP_DIRECT, input_device->propbit);
+
if (ts->platform_data->use_gestures)
set_bit(BTN_3, input_device->keybit);
diff --git a/drivers/iommu/msm_iommu-v2.c b/drivers/iommu/msm_iommu-v2.c
index 10d0b66..2ae9f28 100644
--- a/drivers/iommu/msm_iommu-v2.c
+++ b/drivers/iommu/msm_iommu-v2.c
@@ -23,6 +23,8 @@
#include <linux/iommu.h>
#include <linux/clk.h>
#include <linux/scatterlist.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <asm/sizes.h>
@@ -70,6 +72,7 @@
struct msm_priv *priv = domain->priv;
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
+ int ret = 0;
int asid;
list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
@@ -78,15 +81,21 @@
iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
BUG_ON(!iommu_drvdata);
+
+ ret = __enable_clocks(iommu_drvdata);
+ if (ret)
+ goto fail;
+
asid = GET_CB_CONTEXTIDR_ASID(iommu_drvdata->base,
ctx_drvdata->num);
SET_TLBIVA(iommu_drvdata->base, ctx_drvdata->num,
asid | (va & CB_TLBIVA_VA));
mb();
+ __disable_clocks(iommu_drvdata);
}
-
- return 0;
+fail:
+ return ret;
}
static int __flush_iotlb(struct iommu_domain *domain)
@@ -94,6 +103,7 @@
struct msm_priv *priv = domain->priv;
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
+ int ret = 0;
int asid;
list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
@@ -102,14 +112,56 @@
iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
BUG_ON(!iommu_drvdata);
+ ret = __enable_clocks(iommu_drvdata);
+ if (ret)
+ goto fail;
+
asid = GET_CB_CONTEXTIDR_ASID(iommu_drvdata->base,
ctx_drvdata->num);
SET_TLBIASID(iommu_drvdata->base, ctx_drvdata->num, asid);
mb();
+ __disable_clocks(iommu_drvdata);
}
- return 0;
+fail:
+ return ret;
+}
+
+static void __reset_iommu(void __iomem *base)
+{
+ int i;
+
+ SET_ACR(base, 0);
+ SET_NSACR(base, 0);
+ SET_CR2(base, 0);
+ SET_NSCR2(base, 0);
+ SET_GFAR(base, 0);
+ SET_GFSRRESTORE(base, 0);
+ SET_TLBIALLNSNH(base, 0);
+ SET_PMCR(base, 0);
+ SET_SCR1(base, 0);
+ SET_SSDR_N(base, 0, 0);
+
+ for (i = 0; i < MAX_NUM_SMR; i++)
+ SET_SMR_VALID(base, i, 0);
+
+ mb();
+}
+
+static void __program_iommu(void __iomem *base)
+{
+ __reset_iommu(base);
+
+ SET_CR0_SMCFCFG(base, 1);
+ SET_CR0_USFCFG(base, 1);
+ SET_CR0_STALLD(base, 1);
+ SET_CR0_GCFGFIE(base, 1);
+ SET_CR0_GCFGFRE(base, 1);
+ SET_CR0_GFIE(base, 1);
+ SET_CR0_GFRE(base, 1);
+ SET_CR0_CLIENTPD(base, 0);
+ mb(); /* Make sure writes complete before returning */
}
static void __reset_context(void __iomem *base, int ctx)
@@ -129,11 +181,12 @@
}
static void __program_context(void __iomem *base, int ctx, int ncb,
- phys_addr_t pgtable, int redirect)
+ phys_addr_t pgtable, int redirect,
+ u32 *sids, int len)
{
unsigned int prrr, nmrr;
unsigned int pn;
- int i, j, found;
+ int i, j, found, num = 0;
__reset_context(base, ctx);
@@ -172,6 +225,30 @@
SET_CB_TTBR0_RGN(base, ctx, 1); /* WB, WA */
}
+ /* Program the M2V tables for this context */
+ for (i = 0; i < len / sizeof(*sids); i++) {
+ for (; num < MAX_NUM_SMR; num++)
+ if (GET_SMR_VALID(base, num) == 0)
+ break;
+ BUG_ON(num >= MAX_NUM_SMR);
+
+ SET_SMR_VALID(base, num, 1);
+ SET_SMR_MASK(base, num, 0);
+ SET_SMR_ID(base, num, sids[i]);
+
+ /* Set VMID = 0 */
+ SET_S2CR_N(base, num, 0);
+ SET_S2CR_CBNDX(base, num, ctx);
+ /* Set security bit override to be Non-secure */
+ SET_S2CR_NSCFG(base, sids[i], 3);
+
+ SET_CBAR_N(base, ctx, 0);
+ /* Stage 1 Context with Stage 2 bypass */
+ SET_CBAR_TYPE(base, ctx, 1);
+ /* Route page faults to the non-secure interrupt */
+ SET_CBAR_IRPTNDX(base, ctx, 1);
+ }
+
/* Find if this page table is used elsewhere, and re-use ASID */
found = 0;
for (i = 0; i < ncb; i++)
@@ -244,13 +321,33 @@
mutex_unlock(&msm_iommu_lock);
}
+static int msm_iommu_ctx_attached(struct device *dev)
+{
+ struct platform_device *pdev;
+ struct device_node *child;
+ struct msm_iommu_ctx_drvdata *ctx;
+
+ for_each_child_of_node(dev->of_node, child) {
+ pdev = of_find_device_by_node(child);
+
+ ctx = dev_get_drvdata(&pdev->dev);
+ if (ctx->attached_domain) {
+ of_node_put(child);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
{
struct msm_priv *priv;
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
struct msm_iommu_ctx_drvdata *tmp_drvdata;
- int ret = 0;
+ u32 sids[MAX_NUM_SMR];
+ int len = 0, ret;
mutex_lock(&msm_iommu_lock);
@@ -278,15 +375,26 @@
goto fail;
}
+ of_get_property(dev->of_node, "qcom,iommu-ctx-sids", &len);
+ BUG_ON(len >= sizeof(sids));
+ if (of_property_read_u32_array(dev->of_node, "qcom,iommu-ctx-sids",
+ sids, len / sizeof(*sids))) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
ret = __enable_clocks(iommu_drvdata);
if (ret)
goto fail;
+ if (!msm_iommu_ctx_attached(dev->parent))
+ __program_iommu(iommu_drvdata->base);
+
__program_context(iommu_drvdata->base, ctx_drvdata->num,
iommu_drvdata->ncb, __pa(priv->pt.fl_table),
- priv->pt.redirect);
-
+ priv->pt.redirect, sids, len);
__disable_clocks(iommu_drvdata);
+
list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
ctx_drvdata->attached_domain = domain;
@@ -322,6 +430,7 @@
__reset_context(iommu_drvdata->base, ctx_drvdata->num);
__disable_clocks(iommu_drvdata);
+
list_del_init(&ctx_drvdata->attached_elm);
ctx_drvdata->attached_domain = NULL;
@@ -427,7 +536,7 @@
struct msm_iommu_ctx_drvdata *ctx_drvdata;
unsigned int par;
void __iomem *base;
- phys_addr_t pa = 0;
+ phys_addr_t ret = 0;
int ctx;
mutex_lock(&msm_iommu_lock);
@@ -443,25 +552,33 @@
base = iommu_drvdata->base;
ctx = ctx_drvdata->num;
+ ret = __enable_clocks(iommu_drvdata);
+ if (ret) {
+ ret = 0; /* 0 indicates translation failed */
+ goto fail;
+ }
+
SET_ATS1PR(base, ctx, va & CB_ATS1PR_ADDR);
mb();
while (GET_CB_ATSR_ACTIVE(base, ctx))
cpu_relax();
par = GET_PAR(base, ctx);
+ __disable_clocks(iommu_drvdata);
+
if (par & CB_PAR_F) {
- pa = 0;
+ ret = 0;
} else {
/* We are dealing with a supersection */
- if (par & CB_PAR_SS)
- pa = (par & 0xFF000000) | (va & 0x00FFFFFF);
+ if (ret & CB_PAR_SS)
+ ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
else /* Upper 20 bits from PAR, lower 12 from VA */
- pa = (par & 0xFFFFF000) | (va & 0x00000FFF);
+ ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
}
fail:
mutex_unlock(&msm_iommu_lock);
- return pa;
+ return ret;
}
static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
@@ -501,7 +618,7 @@
struct msm_iommu_drvdata *drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
unsigned int fsr;
- int ret = IRQ_NONE;
+ int ret;
mutex_lock(&msm_iommu_lock);
@@ -513,6 +630,12 @@
ctx_drvdata = dev_get_drvdata(&pdev->dev);
BUG_ON(!ctx_drvdata);
+ ret = __enable_clocks(drvdata);
+ if (ret) {
+ ret = IRQ_NONE;
+ goto fail;
+ }
+
fsr = GET_FSR(drvdata->base, ctx_drvdata->num);
if (fsr) {
if (!ctx_drvdata->attached_domain) {
@@ -537,6 +660,8 @@
} else
ret = IRQ_NONE;
+ __disable_clocks(drvdata);
+fail:
mutex_unlock(&msm_iommu_lock);
return ret;
}
diff --git a/drivers/iommu/msm_iommu_dev-v2.c b/drivers/iommu/msm_iommu_dev-v2.c
index e690ada..d6858de 100644
--- a/drivers/iommu/msm_iommu_dev-v2.c
+++ b/drivers/iommu/msm_iommu_dev-v2.c
@@ -29,27 +29,6 @@
#include <mach/iommu_hw-v2.h>
#include <mach/iommu.h>
-static void msm_iommu_reset(void __iomem *base)
-{
- int i;
-
- SET_ACR(base, 0);
- SET_NSACR(base, 0);
- SET_CR2(base, 0);
- SET_NSCR2(base, 0);
- SET_GFAR(base, 0);
- SET_GFSRRESTORE(base, 0);
- SET_TLBIALLNSNH(base, 0);
- SET_PMCR(base, 0);
- SET_SCR1(base, 0);
- SET_SSDR_N(base, 0, 0);
-
- for (i = 0; i < MAX_NUM_SMR; i++)
- SET_SMR_VALID(base, i, 0);
-
- mb();
-}
-
static int msm_iommu_parse_dt(struct platform_device *pdev,
struct msm_iommu_drvdata *drvdata)
{
@@ -119,17 +98,6 @@
} else
drvdata->clk = NULL;
- msm_iommu_reset(drvdata->base);
-
- SET_CR0_SMCFCFG(drvdata->base, 1);
- SET_CR0_USFCFG(drvdata->base, 1);
- SET_CR0_STALLD(drvdata->base, 1);
- SET_CR0_GCFGFIE(drvdata->base, 1);
- SET_CR0_GCFGFRE(drvdata->base, 1);
- SET_CR0_GFIE(drvdata->base, 1);
- SET_CR0_GFRE(drvdata->base, 1);
- SET_CR0_CLIENTPD(drvdata->base, 0);
-
ret = msm_iommu_parse_dt(pdev, drvdata);
if (ret)
goto fail_clk;
@@ -173,13 +141,10 @@
}
static int msm_iommu_ctx_parse_dt(struct platform_device *pdev,
- struct msm_iommu_drvdata *drvdata,
struct msm_iommu_ctx_drvdata *ctx_drvdata)
{
struct resource *r, rp;
- u32 sids[MAX_NUM_SMR];
- int num = 0;
- int irq, i, ret, len = 0;
+ int irq, ret;
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
@@ -212,53 +177,17 @@
&ctx_drvdata->name))
ctx_drvdata->name = dev_name(&pdev->dev);
- of_get_property(pdev->dev.of_node, "qcom,iommu-ctx-sids", &len);
- BUG_ON(len >= sizeof(sids));
- if (of_property_read_u32_array(pdev->dev.of_node, "qcom,iommu-ctx-sids",
- sids, len / sizeof(*sids)))
- return -EINVAL;
-
- /* Program the M2V tables for this context */
- for (i = 0; i < len / sizeof(*sids); i++) {
- for (; num < MAX_NUM_SMR; num++)
- if (GET_SMR_VALID(drvdata->base, num) == 0)
- break;
- BUG_ON(num >= MAX_NUM_SMR);
-
- SET_SMR_VALID(drvdata->base, num, 1);
- SET_SMR_MASK(drvdata->base, num, 0);
- SET_SMR_ID(drvdata->base, num, sids[i]);
-
- /* Set VMID = 0 */
- SET_S2CR_N(drvdata->base, num, 0);
- SET_S2CR_CBNDX(drvdata->base, num, ctx_drvdata->num);
- /* Set security bit override to be Non-secure */
- SET_S2CR_NSCFG(drvdata->base, sids[i], 3);
-
- SET_CBAR_N(drvdata->base, ctx_drvdata->num, 0);
- /* Stage 1 Context with Stage 2 bypass */
- SET_CBAR_TYPE(drvdata->base, ctx_drvdata->num, 1);
- /* Route page faults to the non-secure interrupt */
- SET_CBAR_IRPTNDX(drvdata->base, ctx_drvdata->num, 1);
- }
- mb();
-
return 0;
}
static int __devinit msm_iommu_ctx_probe(struct platform_device *pdev)
{
- struct msm_iommu_drvdata *drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
int ret;
if (!pdev->dev.parent)
return -EINVAL;
- drvdata = dev_get_drvdata(pdev->dev.parent);
- if (!drvdata)
- return -ENODEV;
-
ctx_drvdata = devm_kzalloc(&pdev->dev, sizeof(*ctx_drvdata),
GFP_KERNEL);
if (!ctx_drvdata)
@@ -268,27 +197,11 @@
INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
platform_set_drvdata(pdev, ctx_drvdata);
- ret = clk_prepare_enable(drvdata->pclk);
- if (ret)
- return ret;
-
- if (drvdata->clk) {
- ret = clk_prepare_enable(drvdata->clk);
- if (ret) {
- clk_disable_unprepare(drvdata->pclk);
- return ret;
- }
- }
-
- ret = msm_iommu_ctx_parse_dt(pdev, drvdata, ctx_drvdata);
+ ret = msm_iommu_ctx_parse_dt(pdev, ctx_drvdata);
if (!ret)
dev_info(&pdev->dev, "context %s using bank %d\n",
dev_name(&pdev->dev), ctx_drvdata->num);
- if (drvdata->clk)
- clk_disable_unprepare(drvdata->clk);
- clk_disable_unprepare(drvdata->pclk);
-
return ret;
}
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index c15609f..971cf10 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -120,6 +120,8 @@
/*PS repeatcount for PS Tx */
int ps_repeatcount;
int enable_optimized_srch_alg;
+ unsigned char spur_table_size;
+ struct fm_spur_data spur_data;
};
/**************************************************************************
@@ -147,6 +149,10 @@
enum radio_state_t state);
static int tavarua_request_irq(struct tavarua_device *radio);
static void start_pending_xfr(struct tavarua_device *radio);
+static int update_spur_table(struct tavarua_device *radio);
+static int xfr_rdwr_data(struct tavarua_device *radio, int op, int size,
+ unsigned long offset, unsigned char *buf);
+
/* work function */
static void read_int_stat(struct work_struct *work);
@@ -1025,6 +1031,35 @@
FMDBG("write PHY_TXGAIN is successful");
complete(&radio->sync_req_done);
break;
+ case (XFR_POKE_COMPLETE | LSH_DATA(ONE_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(TWO_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(THREE_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(FOUR_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(FIVE_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(SIX_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(SEVEN_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(EIGHT_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(NINE_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(TEN_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(ELEVEN_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(TWELVE_BYTE, 1)):
+ case (XFR_POKE_COMPLETE | LSH_DATA(THIRTEEN_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(ONE_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(TWO_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(THREE_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(FOUR_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(FIVE_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(SIX_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(SEVEN_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(EIGHT_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(NINE_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(TEN_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(ELEVEN_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(TWELVE_BYTE, 1)):
+ case (XFR_PEEK_COMPLETE | LSH_DATA(THIRTEEN_BYTE, 1)):
+ FMDBG("XFR interrupt for PEEK/POKE complete\n");
+ complete(&radio->sync_req_done);
+ break;
default:
FMDERR("UNKNOWN XFR = %d\n", xfr_status);
}
@@ -2158,6 +2193,7 @@
wait_for_completion(&radio->shutdown_done);
radio->handle_irq = 1;
radio->lp_mode = 1;
+ radio->spur_table_size = 0;
atomic_inc(&radio->users);
radio->marimba->mod_id = SLAVE_ID_BAHAMA;
flush_workqueue(radio->wqueue);
@@ -2481,6 +2517,135 @@
return retval;
}
+
+static int update_spur_table(struct tavarua_device *radio)
+{
+ unsigned char xfr_buf[XFR_REG_NUM];
+ unsigned char size = 0, tbl_size = 0;
+ int index = 0, offset = 0, addr = 0x0, val = 0;
+ int retval = 0, temp = 0, cnt = 0, j = 0;
+
+ memset(xfr_buf, 0x0, XFR_REG_NUM);
+
+ /* Read the SPUR Table Size */
+ retval = xfr_rdwr_data(radio, XFR_READ, 1, SPUR_TABLE_ADDR, &tbl_size);
+ if (retval < 0) {
+ FMDERR("%s: Failed to read SPUR table size\n", __func__);
+ return retval;
+ }
+
+ /* Calculate the new SPUR Register address */
+ val = addr = (SPUR_TABLE_START_ADDR + (tbl_size * 3));
+
+ /* Save the SPUR Table length configured by user*/
+ temp = radio->spur_table_size;
+
+ /* COnfigure the new spur table length */
+ size = (radio->spur_table_size + tbl_size);
+ retval = xfr_rdwr_data(radio, XFR_WRITE, 1, SPUR_TABLE_ADDR, &size);
+ if (retval < 0) {
+ FMDERR("%s: Failed to configure SPUR table size\n", __func__);
+ return retval;
+ }
+
+ /* Program the spur table entries */
+ for (cnt = 0; cnt < (temp / 4); cnt++) {
+ offset = 0;
+ for (j = 0; j < 4; j++) {
+ xfr_buf[offset++] = GET_FREQ(COMPUTE_SPUR(
+ radio->spur_data.freq[index]), 1);
+ xfr_buf[offset++] = GET_FREQ(COMPUTE_SPUR(
+ radio->spur_data.freq[index]), 0);
+ xfr_buf[offset++] =
+ radio->spur_data.rmssi[index];
+ index++;
+ }
+ retval = xfr_rdwr_data(radio, XFR_WRITE, (SPUR_DATA_SIZE * 4),
+ addr, xfr_buf);
+ if (retval < 0) {
+ FMDERR("%s: Failed to program SPUR frequencies\n",
+ __func__);
+ return retval;
+ }
+ addr += (SPUR_DATA_SIZE * 4);
+ }
+
+ /* Program the additional SPUR Frequencies */
+ temp = radio->spur_table_size;
+ temp = (temp % 4);
+ if (temp > 0) {
+ offset = 0;
+ for (j = 0; j < temp; j++) {
+ xfr_buf[offset++] = GET_FREQ(COMPUTE_SPUR(
+ radio->spur_data.freq[index]), 1);
+ xfr_buf[offset++] = GET_FREQ(COMPUTE_SPUR(
+ radio->spur_data.freq[index]), 0);
+ xfr_buf[offset++] =
+ radio->spur_data.rmssi[index];
+ index++;
+ }
+ size = (temp * SPUR_DATA_SIZE);
+ retval = xfr_rdwr_data(radio, XFR_WRITE, size, addr, xfr_buf);
+ if (retval < 0) {
+ FMDERR("%s: Failed to program SPUR frequencies\n",
+ __func__);
+ return retval;
+ }
+ }
+
+ return retval;
+}
+
+static int xfr_rdwr_data(struct tavarua_device *radio, int op, int size,
+ unsigned long offset, unsigned char *buf) {
+
+ unsigned char xfr_buf[XFR_REG_NUM];
+ int retval = 0, temp = 0;
+
+ memset(xfr_buf, 0x0, XFR_REG_NUM);
+ temp = size;
+
+ xfr_buf[XFR_MODE_OFFSET] = (size << 1);
+ xfr_buf[XFR_ADDR_MSB_OFFSET] = GET_FREQ(offset, 1);
+ xfr_buf[XFR_ADDR_LSB_OFFSET] = GET_FREQ(offset, 0);
+
+ if (op == XFR_READ) {
+ xfr_buf[XFR_MODE_OFFSET] |= (XFR_PEEK_MODE);
+ size = 3;
+ } else if (op == XFR_WRITE) {
+ xfr_buf[XFR_MODE_OFFSET] |= (XFR_POKE_MODE);
+ memcpy(&xfr_buf[XFR_DATA_OFFSET], buf, size);
+ size += 3;
+ }
+
+ retval = tavarua_write_registers(radio, XFRCTRL, xfr_buf, size);
+ if (retval < 0) {
+ FMDERR("%s: Failed to performXFR operation\n", __func__);
+ return retval;
+ }
+
+ size = temp;
+
+ /*Wait for the XFR interrupt */
+ init_completion(&radio->sync_req_done);
+ if (!wait_for_completion_timeout(&radio->sync_req_done,
+ msecs_to_jiffies(WAIT_TIMEOUT))) {
+ FMDERR("Timeout: No XFR interrupt");
+ }
+
+ if (op == XFR_READ) {
+ retval = tavarua_read_registers(radio, XFRDAT0, size);
+ if (retval < 0) {
+ FMDERR("%s: Failed to read the XFR data\n", __func__);
+ return retval;
+ }
+ if (buf != NULL)
+ memcpy(buf, &radio->registers[XFRDAT0], size);
+ }
+
+ return retval;
+}
+
static int peek_MPX_DCC(struct tavarua_device *radio)
{
int retval = 0;
@@ -3001,6 +3166,7 @@
}
/* check if off */
else if ((ctrl->value == FM_OFF) && radio->registers[RDCTRL]) {
+ radio->spur_table_size = 0;
FMDBG("%s: turning off...\n", __func__);
tavarua_write_register(radio, RDCTRL, ctrl->value);
/* flush the event and work queues */
@@ -3299,8 +3465,20 @@
case V4L2_CID_PRIVATE_TAVARUA_DO_CALIBRATION:
case V4L2_CID_PRIVATE_SINR_THRESHOLD:
case V4L2_CID_PRIVATE_SINR_SAMPLES:
+ case V4L2_CID_PRIVATE_SPUR_SELECTION:
retval = 0;
break;
+ case V4L2_CID_PRIVATE_SPUR_FREQ:
+ radio->spur_data.freq[radio->spur_table_size] =
+ ctrl->value;
+ break;
+ case V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI:
+ radio->spur_data.rmssi[radio->spur_table_size++] =
+ ctrl->value;
+ break;
+ case V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE:
+ retval = update_spur_table(radio);
+ break;
default:
retval = -EINVAL;
}
diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c
index 3416c91..d7dc67d 100644
--- a/drivers/media/rc/gpio-ir-recv.c
+++ b/drivers/media/rc/gpio-ir-recv.c
@@ -28,6 +28,7 @@
struct rc_dev *rcdev;
unsigned int gpio_nr;
bool active_low;
+ int can_sleep;
};
static irqreturn_t gpio_ir_recv_irq(int irq, void *dev_id)
@@ -37,7 +38,10 @@
int rc = 0;
enum raw_event_type type = IR_SPACE;
- gval = gpio_get_value_cansleep(gpio_dev->gpio_nr);
+ if (gpio_dev->can_sleep)
+ gval = gpio_get_value_cansleep(gpio_dev->gpio_nr);
+ else
+ gval = gpio_get_value(gpio_dev->gpio_nr);
if (gval < 0)
goto err_get_value;
@@ -96,6 +100,9 @@
rc = gpio_request(pdata->gpio_nr, "gpio-ir-recv");
if (rc < 0)
goto err_gpio_request;
+
+ gpio_dev->can_sleep = gpio_cansleep(pdata->gpio_nr);
+
rc = gpio_direction_input(pdata->gpio_nr);
if (rc < 0)
goto err_gpio_direction_input;
diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c
index 3c9431a..a3fe1c8 100644
--- a/drivers/media/rc/ir-nec-decoder.c
+++ b/drivers/media/rc/ir-nec-decoder.c
@@ -149,6 +149,10 @@
break;
data->state = STATE_TRAILER_SPACE;
+
+ if (data->is_nec_x)
+ goto rc_data;
+
return 0;
case STATE_TRAILER_SPACE:
@@ -157,7 +161,7 @@
if (!geq_margin(ev.duration, NEC_TRAILER_SPACE, NEC_UNIT / 2))
break;
-
+rc_data:
address = bitrev8((data->bits >> 24) & 0xff);
not_address = bitrev8((data->bits >> 16) & 0xff);
command = bitrev8((data->bits >> 8) & 0xff);
diff --git a/drivers/media/rc/keymaps/rc-samsung-necx.c b/drivers/media/rc/keymaps/rc-samsung-necx.c
index 6cf837f..1a3d6be 100644
--- a/drivers/media/rc/keymaps/rc-samsung-necx.c
+++ b/drivers/media/rc/keymaps/rc-samsung-necx.c
@@ -32,7 +32,7 @@
{ 0x70707, KEY_VOLUMEUP},
{ 0x7070b, KEY_VOLUMEDOWN},
{ 0x70760, KEY_UP},
- { 0x70768, KEY_ENTER}, /* ok */
+ { 0x70768, KEY_ENTER},
{ 0x70761, KEY_DOWN},
{ 0x70765, KEY_LEFT},
{ 0x70762, KEY_RIGHT},
@@ -44,15 +44,18 @@
{ 0x70748, KEY_FORWARD},
{ 0x7074a, KEY_PAUSE},
{ 0x70703, KEY_SLEEP},
- { 0x7076c, KEY_A}, /* search */
- { 0x70714, KEY_B}, /* camera */
- { 0x70715, KEY_C},
- { 0x70716, KEY_D},
+ { 0x7076c, KEY_RED},
+ { 0x70714, KEY_GREEN},
+ { 0x70715, KEY_YELLOW},
+ { 0x70716, KEY_BLUE},
{ 0x70758, KEY_BACK},
{ 0x7071a, KEY_MENU},
{ 0x7076b, KEY_LIST},
- { 0x70701, KEY_SCREENLOCK},
- { 0x7071f, KEY_HOME},
+ { 0x70701, KEY_TV2},
+ { 0x7071f, KEY_INFO},
+ { 0x7071b, KEY_TV},
+ { 0x7078b, KEY_AUX},
+ { 0x7078c, KEY_MEDIA},
};
diff --git a/drivers/media/rc/keymaps/rc-ue-rf4ce.c b/drivers/media/rc/keymaps/rc-ue-rf4ce.c
index 71c5505..ea982a8 100644
--- a/drivers/media/rc/keymaps/rc-ue-rf4ce.c
+++ b/drivers/media/rc/keymaps/rc-ue-rf4ce.c
@@ -25,7 +25,7 @@
{ 0x0d, KEY_EXIT },
{ 0x72, KEY_TV },
{ 0x73, KEY_VIDEO },
- { 0x74, KEY_COMPOSE },
+ { 0x74, KEY_PC },
{ 0x71, KEY_AUX },
{ 0x45, KEY_STOP },
{ 0x0b, KEY_LIST },
@@ -43,18 +43,20 @@
{ 0x30, KEY_CHANNELUP },
{ 0x31, KEY_CHANNELDOWN },
- { 0x20, KEY_NUMERIC_0 },
- { 0x21, KEY_NUMERIC_1 },
- { 0x22, KEY_NUMERIC_2 },
- { 0x23, KEY_NUMERIC_3 },
- { 0x24, KEY_NUMERIC_4 },
- { 0x25, KEY_NUMERIC_5 },
- { 0x26, KEY_NUMERIC_6 },
- { 0x27, KEY_NUMERIC_7 },
- { 0x28, KEY_NUMERIC_8 },
- { 0x29, KEY_NUMERIC_9 },
- { 0x34, KEY_INSERT },
+ { 0x20, KEY_0 },
+ { 0x21, KEY_1 },
+ { 0x22, KEY_2 },
+ { 0x23, KEY_3 },
+ { 0x24, KEY_4 },
+ { 0x25, KEY_5 },
+ { 0x26, KEY_6 },
+ { 0x27, KEY_7 },
+ { 0x28, KEY_8 },
+ { 0x29, KEY_9 },
+ { 0x34, KEY_TV2 },
{ 0x2b, KEY_ENTER },
+ { 0x35, KEY_INFO },
+ { 0x09, KEY_MENU },
};
static struct rc_map_list ue_rf4ce_map = {
diff --git a/drivers/media/video/msm/msm.h b/drivers/media/video/msm/msm.h
index 7bc6cff..1f1f329 100644
--- a/drivers/media/video/msm/msm.h
+++ b/drivers/media/video/msm/msm.h
@@ -129,6 +129,7 @@
struct msm_free_buf {
uint8_t num_planes;
+ int32_t image_mode;
uint32_t ch_paddr[VIDEO_MAX_PLANES];
uint32_t vb;
};
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index fab0095..834c9b0 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -146,7 +146,7 @@
static int msm_isp_notify_VFE_BUF_EVT(struct v4l2_subdev *sd, void *arg)
{
- int rc = -EINVAL, image_mode;
+ int rc = -EINVAL;
struct msm_vfe_resp *vdata = (struct msm_vfe_resp *)arg;
struct msm_free_buf free_buf, temp_free_buf;
struct msm_camvfe_params vfe_params;
@@ -154,16 +154,22 @@
struct msm_cam_media_controller *pmctl =
(struct msm_cam_media_controller *)v4l2_get_subdev_hostdata(sd);
struct msm_cam_v4l2_device *pcam = pmctl->pcam_ptr;
-
- int vfe_id = vdata->evt_msg.msg_id;
+ struct msm_frame_info *frame_info =
+ (struct msm_frame_info *)vdata->evt_msg.data;
+ uint32_t vfe_id, image_mode;
if (!pcam) {
pr_debug("%s pcam is null. return\n", __func__);
msm_isp_sync_free(vdata);
return rc;
}
- /* Convert the vfe msg to the image mode */
- image_mode = msm_isp_vfe_msg_to_img_mode(pmctl, vfe_id);
- BUG_ON(image_mode < 0);
+ if (frame_info) {
+ vfe_id = frame_info->path;
+ image_mode = frame_info->image_mode;
+ } else {
+ vfe_id = vdata->evt_msg.msg_id;
+ image_mode = msm_isp_vfe_msg_to_img_mode(pmctl, vfe_id);
+ }
+
switch (vdata->type) {
case VFE_MSG_V32_START:
case VFE_MSG_V32_START_RECORDING:
@@ -302,45 +308,49 @@
}
case NOTIFY_VFE_MSG_OUT: {
uint8_t msgid;
+ int32_t image_mode = -1;
struct isp_msg_output *isp_output =
(struct isp_msg_output *)arg;
- switch (isp_output->output_id) {
- case MSG_ID_OUTPUT_P:
- msgid = VFE_MSG_OUTPUT_P;
- break;
- case MSG_ID_OUTPUT_V:
- msgid = VFE_MSG_OUTPUT_V;
- break;
- case MSG_ID_OUTPUT_T:
- msgid = VFE_MSG_OUTPUT_T;
- break;
- case MSG_ID_OUTPUT_S:
- msgid = VFE_MSG_OUTPUT_S;
- break;
- case MSG_ID_OUTPUT_PRIMARY:
- msgid = VFE_MSG_OUTPUT_PRIMARY;
- break;
- case MSG_ID_OUTPUT_SECONDARY:
- msgid = VFE_MSG_OUTPUT_SECONDARY;
- break;
- default:
- pr_err("%s: Invalid VFE output id: %d\n",
- __func__, isp_output->output_id);
- rc = -EINVAL;
- break;
+ if (isp_output->buf.image_mode < 0) {
+ switch (isp_output->output_id) {
+ case MSG_ID_OUTPUT_P:
+ msgid = VFE_MSG_OUTPUT_P;
+ break;
+ case MSG_ID_OUTPUT_V:
+ msgid = VFE_MSG_OUTPUT_V;
+ break;
+ case MSG_ID_OUTPUT_T:
+ msgid = VFE_MSG_OUTPUT_T;
+ break;
+ case MSG_ID_OUTPUT_S:
+ msgid = VFE_MSG_OUTPUT_S;
+ break;
+ case MSG_ID_OUTPUT_PRIMARY:
+ msgid = VFE_MSG_OUTPUT_PRIMARY;
+ break;
+ case MSG_ID_OUTPUT_SECONDARY:
+ msgid = VFE_MSG_OUTPUT_SECONDARY;
+ break;
+ default:
+ pr_err("%s: Invalid VFE output id: %d\n",
+ __func__, isp_output->output_id);
+ rc = -EINVAL;
+ break;
+ }
+ if (!rc)
+ image_mode =
+ msm_isp_vfe_msg_to_img_mode(pmctl, msgid);
+ } else {
+ image_mode = isp_output->buf.image_mode;
}
-
- if (!rc) {
- isp_event->isp_data.isp_msg.msg_id =
- isp_output->output_id;
- isp_event->isp_data.isp_msg.frame_id =
- isp_output->frameCounter;
- buf = isp_output->buf;
- msgid = msm_isp_vfe_msg_to_img_mode(pmctl, msgid);
- BUG_ON(msgid < 0);
- msm_mctl_buf_done(pmctl, msgid,
- &buf, isp_output->frameCounter);
- }
+ isp_event->isp_data.isp_msg.msg_id =
+ isp_output->output_id;
+ isp_event->isp_data.isp_msg.frame_id =
+ isp_output->frameCounter;
+ buf = isp_output->buf;
+ BUG_ON(image_mode < 0);
+ msm_mctl_buf_done(pmctl, image_mode,
+ &buf, isp_output->frameCounter);
}
break;
case NOTIFY_VFE_MSG_COMP_STATS: {
diff --git a/drivers/media/video/msm/msm_vfe31_v4l2.c b/drivers/media/video/msm/msm_vfe31_v4l2.c
index 7a2670c..a6cc06e 100644
--- a/drivers/media/video/msm/msm_vfe31_v4l2.c
+++ b/drivers/media/video/msm/msm_vfe31_v4l2.c
@@ -420,15 +420,18 @@
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
-static void vfe31_subdev_notify(int id, int path)
+static void vfe31_subdev_notify(int id, int path, int image_mode)
{
struct msm_vfe_resp rp;
+ struct msm_frame_info frame_info;
unsigned long flags;
spin_lock_irqsave(&vfe31_ctrl->sd_notify_lock, flags);
memset(&rp, 0, sizeof(struct msm_vfe_resp));
CDBG("vfe31_subdev_notify : msgId = %d\n", id);
rp.evt_msg.type = MSM_CAMERA_MSG;
- rp.evt_msg.msg_id = path;
+ frame_info.image_mode = image_mode;
+ frame_info.path = path;
+ rp.evt_msg.data = &frame_info;
rp.type = id;
v4l2_subdev_notify(&vfe31_ctrl->subdev, NOTIFY_VFE_BUF_EVT, &rp);
spin_unlock_irqrestore(&vfe31_ctrl->sd_notify_lock, flags);
@@ -442,10 +445,12 @@
ch_info = axi_cfg + V31_AXI_CFG_LEN;
vfe31_ctrl->outpath.out0.ch0 = 0x0000FFFF & *ch_info;
vfe31_ctrl->outpath.out0.ch1 = 0x0000FFFF & (*ch_info++ >> 16);
- vfe31_ctrl->outpath.out0.ch2 = 0x0000FFFF & *ch_info++;
+ vfe31_ctrl->outpath.out0.ch2 = 0x0000FFFF & *ch_info;
+ vfe31_ctrl->outpath.out0.image_mode = 0x0000FFFF & (*ch_info++ >> 16);
vfe31_ctrl->outpath.out1.ch0 = 0x0000FFFF & *ch_info;
vfe31_ctrl->outpath.out1.ch1 = 0x0000FFFF & (*ch_info++ >> 16);
- vfe31_ctrl->outpath.out1.ch2 = 0x0000FFFF & *ch_info++;
+ vfe31_ctrl->outpath.out1.ch2 = 0x0000FFFF & *ch_info;
+ vfe31_ctrl->outpath.out1.image_mode = 0x0000FFFF & (*ch_info++ >> 16);
vfe31_ctrl->outpath.out2.ch0 = 0x0000FFFF & *ch_info;
vfe31_ctrl->outpath.out2.ch1 = 0x0000FFFF & (*ch_info++ >> 16);
vfe31_ctrl->outpath.out2.ch2 = 0x0000FFFF & *ch_info++;
@@ -1168,7 +1173,14 @@
{
struct vfe31_output_ch *outch = NULL;
struct msm_free_buf *b = NULL;
- vfe31_subdev_notify(id, path);
+ uint32_t image_mode = 0;
+
+ if (path == VFE_MSG_OUTPUT_PRIMARY)
+ image_mode = vfe31_ctrl->outpath.out0.image_mode;
+ else
+ image_mode = vfe31_ctrl->outpath.out1.image_mode;
+
+ vfe31_subdev_notify(id, path, image_mode);
outch = vfe31_get_ch(path);
if (outch->free_buf.ch_paddr[0])
b = &outch->free_buf;
@@ -1178,7 +1190,14 @@
{
struct vfe31_output_ch *outch = NULL;
int rc = 0;
- vfe31_subdev_notify(id, path);
+ uint32_t image_mode = 0;
+
+ if (path == VFE_MSG_OUTPUT_PRIMARY)
+ image_mode = vfe31_ctrl->outpath.out0.image_mode;
+ else
+ image_mode = vfe31_ctrl->outpath.out1.image_mode;
+
+ vfe31_subdev_notify(id, path, image_mode);
outch = vfe31_get_ch(path);
if (outch->ping.ch_paddr[0] && outch->pong.ch_paddr[0]) {
/* Configure Preview Ping Pong */
@@ -2595,11 +2614,13 @@
}
}
static void vfe_send_outmsg(struct v4l2_subdev *sd, uint8_t msgid,
- uint32_t ch0_paddr, uint32_t ch1_paddr, uint32_t ch2_paddr)
+ uint32_t ch0_paddr, uint32_t ch1_paddr,
+ uint32_t ch2_paddr, uint32_t image_mode)
{
struct isp_msg_output msg;
msg.output_id = msgid;
+ msg.buf.image_mode = image_mode;
msg.buf.ch_paddr[0] = ch0_paddr;
msg.buf.ch_paddr[1] = ch1_paddr;
msg.buf.ch_paddr[2] = ch2_paddr;
@@ -2681,7 +2702,8 @@
vfe_send_outmsg(&vfe31_ctrl->subdev,
MSG_ID_OUTPUT_PRIMARY, ch0_paddr,
- ch1_paddr, ch2_paddr);
+ ch1_paddr, ch2_paddr,
+ vfe31_ctrl->outpath.out0.image_mode);
if (vfe31_ctrl->liveshot_state == VFE_STATE_STOPPED)
vfe31_ctrl->liveshot_state = VFE_STATE_IDLE;
@@ -2753,7 +2775,8 @@
vfe_send_outmsg(&vfe31_ctrl->subdev,
MSG_ID_OUTPUT_SECONDARY, ch0_paddr,
- ch1_paddr, ch2_paddr);
+ ch1_paddr, ch2_paddr,
+ vfe31_ctrl->outpath.out1.image_mode);
} else {
vfe31_ctrl->outpath.out1.frame_drop_cnt++;
CDBG("path_irq_1 - no free buffer!\n");
diff --git a/drivers/media/video/msm/msm_vfe31_v4l2.h b/drivers/media/video/msm/msm_vfe31_v4l2.h
index e94f286..739d157 100644
--- a/drivers/media/video/msm/msm_vfe31_v4l2.h
+++ b/drivers/media/video/msm/msm_vfe31_v4l2.h
@@ -695,7 +695,7 @@
struct vfe31_output_ch {
struct list_head free_buf_queue;
spinlock_t free_buf_lock;
- uint16_t output_fmt;
+ uint16_t image_mode;
int8_t ch0;
int8_t ch1;
int8_t ch2;
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 3611656..9544ce5 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -389,16 +389,19 @@
vfe32_ctrl->share_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
-static void vfe32_subdev_notify(int id, int path,
+static void vfe32_subdev_notify(int id, int path, int image_mode,
struct v4l2_subdev *sd, struct vfe_share_ctrl_t *share_ctrl)
{
struct msm_vfe_resp rp;
+ struct msm_frame_info frame_info;
unsigned long flags = 0;
spin_lock_irqsave(&share_ctrl->sd_notify_lock, flags);
CDBG("vfe32_subdev_notify : msgId = %d\n", id);
memset(&rp, 0, sizeof(struct msm_vfe_resp));
rp.evt_msg.type = MSM_CAMERA_MSG;
- rp.evt_msg.msg_id = path;
+ frame_info.image_mode = image_mode;
+ frame_info.path = path;
+ rp.evt_msg.data = &frame_info;
rp.type = id;
v4l2_subdev_notify(sd, NOTIFY_VFE_BUF_EVT, &rp);
spin_unlock_irqrestore(&share_ctrl->sd_notify_lock, flags);
@@ -415,11 +418,15 @@
axi_ctrl->share_ctrl->outpath.out0.ch0 = 0x0000FFFF & *ch_info;
axi_ctrl->share_ctrl->outpath.out0.ch1 =
0x0000FFFF & (*ch_info++ >> 16);
- axi_ctrl->share_ctrl->outpath.out0.ch2 = 0x0000FFFF & *ch_info++;
+ axi_ctrl->share_ctrl->outpath.out0.ch2 = 0x0000FFFF & *ch_info;
+ axi_ctrl->share_ctrl->outpath.out0.image_mode =
+ 0x0000FFFF & (*ch_info++ >> 16);
axi_ctrl->share_ctrl->outpath.out1.ch0 = 0x0000FFFF & *ch_info;
axi_ctrl->share_ctrl->outpath.out1.ch1 =
0x0000FFFF & (*ch_info++ >> 16);
- axi_ctrl->share_ctrl->outpath.out1.ch2 = 0x0000FFFF & *ch_info++;
+ axi_ctrl->share_ctrl->outpath.out1.ch2 = 0x0000FFFF & *ch_info;
+ axi_ctrl->share_ctrl->outpath.out1.image_mode =
+ 0x0000FFFF & (*ch_info++ >> 16);
axi_ctrl->share_ctrl->outpath.out2.ch0 = 0x0000FFFF & *ch_info;
axi_ctrl->share_ctrl->outpath.out2.ch1 =
0x0000FFFF & (*ch_info++ >> 16);
@@ -1239,7 +1246,14 @@
{
struct vfe32_output_ch *outch = NULL;
struct msm_free_buf *b = NULL;
- vfe32_subdev_notify(id, path,
+ uint32_t image_mode = 0;
+
+ if (path == VFE_MSG_OUTPUT_PRIMARY)
+ image_mode = axi_ctrl->share_ctrl->outpath.out0.image_mode;
+ else
+ image_mode = axi_ctrl->share_ctrl->outpath.out1.image_mode;
+
+ vfe32_subdev_notify(id, path, image_mode,
&axi_ctrl->subdev, axi_ctrl->share_ctrl);
outch = vfe32_get_ch(path, axi_ctrl->share_ctrl);
if (outch->free_buf.ch_paddr[0])
@@ -1251,7 +1265,13 @@
{
struct vfe32_output_ch *outch = NULL;
int rc = 0;
- vfe32_subdev_notify(id, path,
+ uint32_t image_mode = 0;
+ if (path == VFE_MSG_OUTPUT_PRIMARY)
+ image_mode = vfe32_ctrl->share_ctrl->outpath.out0.image_mode;
+ else
+ image_mode = vfe32_ctrl->share_ctrl->outpath.out1.image_mode;
+
+ vfe32_subdev_notify(id, path, image_mode,
&vfe32_ctrl->subdev, vfe32_ctrl->share_ctrl);
outch = vfe32_get_ch(path, vfe32_ctrl->share_ctrl);
if (outch->ping.ch_paddr[0] && outch->pong.ch_paddr[0]) {
@@ -3163,11 +3183,13 @@
static void vfe_send_outmsg(
struct axi_ctrl_t *axi_ctrl, uint8_t msgid,
- uint32_t ch0_paddr, uint32_t ch1_paddr, uint32_t ch2_paddr)
+ uint32_t ch0_paddr, uint32_t ch1_paddr,
+ uint32_t ch2_paddr, uint32_t image_mode)
{
struct isp_msg_output msg;
msg.output_id = msgid;
+ msg.buf.image_mode = image_mode;
msg.buf.ch_paddr[0] = ch0_paddr;
msg.buf.ch_paddr[1] = ch1_paddr;
msg.buf.ch_paddr[2] = ch2_paddr;
@@ -3268,7 +3290,8 @@
vfe_send_outmsg(axi_ctrl,
MSG_ID_OUTPUT_PRIMARY, ch0_paddr,
- ch1_paddr, ch2_paddr);
+ ch1_paddr, ch2_paddr,
+ axi_ctrl->share_ctrl->outpath.out0.image_mode);
if (axi_ctrl->share_ctrl->liveshot_state == VFE_STATE_STOPPED)
axi_ctrl->share_ctrl->liveshot_state = VFE_STATE_IDLE;
@@ -3348,7 +3371,9 @@
vfe_send_outmsg(axi_ctrl,
MSG_ID_OUTPUT_SECONDARY, ch0_paddr,
- ch1_paddr, ch2_paddr);
+ ch1_paddr, ch2_paddr,
+ axi_ctrl->share_ctrl->outpath.out1.image_mode);
+
} else {
axi_ctrl->share_ctrl->outpath.out1.frame_drop_cnt++;
CDBG("path_irq_1 - no free buffer!\n");
diff --git a/drivers/media/video/msm/msm_vfe32.h b/drivers/media/video/msm/msm_vfe32.h
index 086600a..d5da432 100644
--- a/drivers/media/video/msm/msm_vfe32.h
+++ b/drivers/media/video/msm/msm_vfe32.h
@@ -741,7 +741,7 @@
struct vfe32_output_ch {
struct list_head free_buf_queue;
spinlock_t free_buf_lock;
- uint16_t output_fmt;
+ uint16_t image_mode;
int8_t ch0;
int8_t ch1;
int8_t ch2;
diff --git a/drivers/media/video/msm/msm_vfe7x27a_v4l2.c b/drivers/media/video/msm/msm_vfe7x27a_v4l2.c
index 893fc06..7369f6f 100644
--- a/drivers/media/video/msm/msm_vfe7x27a_v4l2.c
+++ b/drivers/media/video/msm/msm_vfe7x27a_v4l2.c
@@ -370,6 +370,7 @@
struct isp_msg_output msg;
msg.output_id = msgid;
+ msg.buf.image_mode = -1;
msg.buf.ch_paddr[0] = ch0_paddr;
msg.buf.ch_paddr[1] = ch1_paddr;
msg.frameCounter = vfe2x_ctrl->vfeFrameId;
@@ -859,6 +860,7 @@
CDBG("vfe2x_subdev_notify : msgId = %d\n", id);
rp.evt_msg.type = MSM_CAMERA_MSG;
rp.evt_msg.msg_id = path;
+ rp.evt_msg.data = NULL;
rp.type = id;
v4l2_subdev_notify(&vfe2x_ctrl->subdev, NOTIFY_VFE_BUF_EVT, &rp);
spin_unlock_irqrestore(&vfe2x_ctrl->sd_notify_lock, flags);
diff --git a/drivers/media/video/msm/server/msm_cam_server.c b/drivers/media/video/msm/server/msm_cam_server.c
index fc1e713..65893c1 100644
--- a/drivers/media/video/msm/server/msm_cam_server.c
+++ b/drivers/media/video/msm/server/msm_cam_server.c
@@ -1760,16 +1760,20 @@
struct v4l2_event v4l2_evt;
struct msm_isp_event_ctrl *isp_event;
- isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl), GFP_KERNEL);
- if (!isp_event) {
- pr_err("%s Insufficient memory. return", __func__);
- return -ENOMEM;
- }
+ void *ctrlcmd_data;
+
event_qcmd = kzalloc(sizeof(struct msm_queue_cmd), GFP_KERNEL);
if (!event_qcmd) {
pr_err("%s Insufficient memory. return", __func__);
- kfree(isp_event);
- return -ENOMEM;
+ rc = -ENOMEM;
+ goto event_qcmd_alloc_fail;
+ }
+
+ isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl), GFP_KERNEL);
+ if (!isp_event) {
+ pr_err("%s Insufficient memory. return", __func__);
+ rc = -ENOMEM;
+ goto isp_event_alloc_fail;
}
D("%s\n", __func__);
@@ -1782,12 +1786,23 @@
server_dev->server_queue[out->queue_idx].evt_id =
server_dev->server_evt_id;
v4l2_evt.type = V4L2_EVENT_PRIVATE_START + ctrl_id;
+ v4l2_evt.id = 0;
v4l2_evt.u.data[0] = out->queue_idx;
/* setup event object to transfer the command; */
isp_event->resptype = MSM_CAM_RESP_V4L2;
isp_event->isp_data.ctrl = *out;
isp_event->isp_data.ctrl.evt_id = server_dev->server_evt_id;
+ if (out->value != NULL && out->length != 0) {
+ ctrlcmd_data = kzalloc(out->length, GFP_KERNEL);
+ if (!ctrlcmd_data) {
+ rc = -ENOMEM;
+ goto ctrlcmd_alloc_fail;
+ }
+ memcpy(ctrlcmd_data, out->value, out->length);
+ isp_event->isp_data.ctrl.value = ctrlcmd_data;
+ }
+
atomic_set(&event_qcmd->on_heap, 1);
event_qcmd->command = isp_event;
@@ -1811,7 +1826,8 @@
if (!rc)
rc = -ETIMEDOUT;
if (rc < 0) {
- kfree(isp_event);
+ if (++server_dev->server_evt_id == 0)
+ server_dev->server_evt_id++;
pr_err("%s: wait_event error %d\n", __func__, rc);
return rc;
}
@@ -1832,7 +1848,6 @@
kfree(ctrlcmd);
free_qcmd(rcmd);
- kfree(isp_event);
D("%s: rc %d\n", __func__, rc);
/* rc is the time elapsed. */
if (rc >= 0) {
@@ -1845,6 +1860,13 @@
rc = -EINVAL;
}
return rc;
+
+ctrlcmd_alloc_fail:
+ kfree(isp_event);
+isp_event_alloc_fail:
+ kfree(event_qcmd);
+event_qcmd_alloc_fail:
+ return rc;
}
int msm_server_close_client(int idx)
diff --git a/drivers/mfd/pm8038-core.c b/drivers/mfd/pm8038-core.c
index 4271a2a..8fef786 100644
--- a/drivers/mfd/pm8038-core.c
+++ b/drivers/mfd/pm8038-core.c
@@ -36,6 +36,9 @@
#define REG_SPK_BASE 0x253
#define REG_SPK_REGISTERS 3
+#define REG_TEMP_ALARM_CTRL 0x01B
+#define REG_TEMP_ALARM_PWM 0x09B
+
#define PM8038_VERSION_MASK 0xFFF0
#define PM8038_VERSION_VALUE 0x09F0
#define PM8038_REVISION_MASK 0x000F
@@ -300,6 +303,30 @@
.pdata_size = sizeof("pm8038-dbg"),
};
+static const struct resource thermal_alarm_cell_resources[] __devinitconst = {
+ SINGLE_IRQ_RESOURCE("pm8038_tempstat_irq", PM8038_TEMPSTAT_IRQ),
+ SINGLE_IRQ_RESOURCE("pm8038_overtemp_irq", PM8038_OVERTEMP_IRQ),
+};
+
+static struct pm8xxx_tm_core_data thermal_alarm_cdata = {
+ .adc_channel = CHANNEL_DIE_TEMP,
+ .adc_type = PM8XXX_TM_ADC_PM8XXX_ADC,
+ .reg_addr_temp_alarm_ctrl = REG_TEMP_ALARM_CTRL,
+ .reg_addr_temp_alarm_pwm = REG_TEMP_ALARM_PWM,
+ .tm_name = "pm8038_tz",
+ .irq_name_temp_stat = "pm8038_tempstat_irq",
+ .irq_name_over_temp = "pm8038_overtemp_irq",
+};
+
+static struct mfd_cell thermal_alarm_cell __devinitdata = {
+ .name = PM8XXX_TM_DEV_NAME,
+ .id = -1,
+ .resources = thermal_alarm_cell_resources,
+ .num_resources = ARRAY_SIZE(thermal_alarm_cell_resources),
+ .platform_data = &thermal_alarm_cdata,
+ .pdata_size = sizeof(struct pm8xxx_tm_core_data),
+};
+
static struct pm8xxx_vreg regulator_data[] = {
/* name pc_name ctrl test hpm_min */
NLDO1200("8038_l1", 0x0AE, 0x0AF, LDO_1200),
@@ -606,6 +633,14 @@
goto bail;
}
}
+
+ ret = mfd_add_devices(pmic->dev, 0, &thermal_alarm_cell, 1, NULL,
+ irq_base);
+ if (ret) {
+ pr_err("Failed to add thermal alarm subdevice ret=%d\n", ret);
+ goto bail;
+ }
+
return 0;
bail:
if (pmic->irq_chip) {
diff --git a/drivers/net/usb/rmnet_usb_data.c b/drivers/net/usb/rmnet_usb_data.c
index ee9737a..9e1e252 100644
--- a/drivers/net/usb/rmnet_usb_data.c
+++ b/drivers/net/usb/rmnet_usb_data.c
@@ -505,6 +505,7 @@
{
struct usbnet *unet;
struct driver_info *info;
+ struct usb_device *udev;
unsigned int iface_num;
static int first_rmnet_iface_num = -EINVAL;
int status = 0;
@@ -555,8 +556,17 @@
if (status)
dev_dbg(&iface->dev, "mode debugfs file is not available\n");
+ udev = unet->udev;
+
/* allow modem to wake up suspended system */
- device_set_wakeup_enable(&unet->udev->dev, 1);
+ device_set_wakeup_enable(&udev->dev, 1);
+
+ /* set default autosuspend timeout for modem and roothub */
+ if (udev->parent && !udev->parent->parent) {
+ pm_runtime_set_autosuspend_delay(&udev->dev, 1000);
+ pm_runtime_set_autosuspend_delay(&udev->parent->dev, 200);
+ }
+
out:
return status;
}
diff --git a/drivers/usb/gadget/ci13xxx_msm.c b/drivers/usb/gadget/ci13xxx_msm.c
index 1cbaa8e..e3c1216 100644
--- a/drivers/usb/gadget/ci13xxx_msm.c
+++ b/drivers/usb/gadget/ci13xxx_msm.c
@@ -56,7 +56,7 @@
if (_udc_ctxt.wake_irq && _udc_ctxt.wake_irq_state) {
disable_irq_wake(_udc_ctxt.wake_irq);
- disable_irq(_udc_ctxt.wake_irq);
+ disable_irq_nosync(_udc_ctxt.wake_irq);
_udc_ctxt.wake_irq_state = false;
}
}
@@ -134,7 +134,7 @@
dev_dbg(&pdev->dev, "_udc_ctxt.gpio_irq = %d and irq = %d\n",
_udc_ctxt.wake_gpio, wake_irq);
ret = request_irq(wake_irq, ci13xxx_msm_resume_irq,
- IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "usb resume", NULL);
+ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "usb resume", NULL);
if (ret < 0) {
dev_err(&pdev->dev, "could not register USB_RESUME IRQ.\n");
goto gpio_free;
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 5cc70e0..caf86ca 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -313,7 +313,7 @@
if (!ehci->susp_sof_bug)
ehci_halt(ehci); /* turn off now-idle HC */
- hcd->state = HC_STATE_SUSPENDED;
+ ehci->rh_state = EHCI_RH_SUSPENDED;
if (ehci->reclaim)
end_unlink_async(ehci);
@@ -562,6 +562,10 @@
unsigned long flags;
u32 ppcd = 0;
+ /* if !USB_SUSPEND, root hub timers won't get shut down ... */
+ if (ehci->rh_state != EHCI_RH_RUNNING)
+ return 0;
+
/* init status to no-changes */
buf [0] = 0;
ports = HCS_N_PORTS (ehci->hcs_params);
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index fe31f93..9174bc5 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -239,15 +239,8 @@
mdp_footswitch_ctrl(TRUE);
mdp4_overlay_panel_mode(MDP4_MIXER1, MDP4_PANEL_DTV);
-
- /* Allocate dtv_pipe at dtv_on*/
- if (dtv_pipe == NULL) {
- if (mdp4_overlay_dtv_set(mfd, NULL)) {
- pr_warn("%s: dtv_pipe is NULL, dtv_set failed\n",
- __func__);
- return -EINVAL;
- }
- }
+ if (dtv_pipe != NULL)
+ ret = mdp4_dtv_start(mfd);
ret = panel_next_on(pdev);
if (ret != 0)
@@ -708,6 +701,14 @@
return;
}
mutex_lock(&mfd->dma->ov_mutex);
+ if (dtv_pipe == NULL) {
+ if (mdp4_overlay_dtv_set(mfd, NULL)) {
+ pr_warn("%s: dtv_pipe == NULL\n", __func__);
+ mutex_unlock(&mfd->dma->ov_mutex);
+ return;
+ }
+ }
+
pipe = dtv_pipe;
if (hdmi_prim_display && (pipe->pipe_used == 0 ||
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
index 3827bc1..ab4d51c 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
@@ -294,6 +294,11 @@
}
}
break;
+ case VCD_I_SET_TURBO_CLK:
+ {
+ vcd_status = VCD_S_SUCCESS;
+ }
+ break;
case VCD_I_BUFFER_FORMAT:
{
struct vcd_property_buffer_format *tile =
diff --git a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
index 5b22b21..45430e8 100644
--- a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
@@ -536,6 +536,9 @@
u32 bus_clk_index, client_type = 0;
int rc = 0;
+ if (dev_ctxt->turbo_mode_set)
+ return rc;
+
cctxt_itr = dev_ctxt->cctxt_list_head;
while (cctxt_itr) {
if (cctxt_itr->decoding)
@@ -565,6 +568,9 @@
bus_clk_index = 2;
}
+ if (bus_clk_index == 3)
+ dev_ctxt->turbo_mode_set = 1;
+
bus_clk_index = (bus_clk_index << 1) + (client_type + 1);
VCDRES_MSG_LOW("%s(), bus_clk_index = %d", __func__, bus_clk_index);
VCDRES_MSG_LOW("%s(),context.pcl = %x", __func__, resource_context.pcl);
diff --git a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.h b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.h
index d5e656b..01999a4 100644
--- a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.h
+++ b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.h
@@ -75,4 +75,8 @@
#define VCDRES_MSG_ERROR(xx_fmt...) printk(KERN_ERR "\n err: " xx_fmt)
#define VCDRES_MSG_FATAL(xx_fmt...) printk(KERN_ERR "\n<FATAL> " xx_fmt)
+#ifdef CONFIG_MSM_BUS_SCALING
+int res_trk_update_bus_perf_level(struct vcd_dev_ctxt *dev_ctxt,
+ u32 perf_level);
+#endif
#endif
diff --git a/drivers/video/msm/vidc/common/dec/vdec.c b/drivers/video/msm/vidc/common/dec/vdec.c
index 11177b8..3076aa1 100644
--- a/drivers/video/msm/vidc/common/dec/vdec.c
+++ b/drivers/video/msm/vidc/common/dec/vdec.c
@@ -636,6 +636,26 @@
return true;
}
+static u32 vid_dec_set_turbo_clk(struct video_client_ctx *client_ctx)
+{
+ struct vcd_property_hdr vcd_property_hdr;
+ u32 vcd_status = VCD_ERR_FAIL;
+ u32 dummy = 0;
+
+ if (!client_ctx)
+ return false;
+ vcd_property_hdr.prop_id = VCD_I_SET_TURBO_CLK;
+ vcd_property_hdr.sz = sizeof(struct vcd_property_frame_size);
+
+ vcd_status = vcd_set_property(client_ctx->vcd_handle,
+ &vcd_property_hdr, &dummy);
+
+ if (vcd_status)
+ return false;
+ else
+ return true;
+}
+
static u32 vid_dec_get_frame_resolution(struct video_client_ctx *client_ctx,
struct vdec_picsize *video_resoultion)
{
@@ -1682,6 +1702,11 @@
}
break;
}
+ case VDEC_IOCTL_SET_PERF_CLK:
+ {
+ vid_dec_set_turbo_clk(client_ctx);
+ break;
+ }
case VDEC_IOCTL_FILL_OUTPUT_BUFFER:
{
struct vdec_fillbuffer_cmd fill_buffer_cmd;
diff --git a/drivers/video/msm/vidc/common/vcd/vcd.h b/drivers/video/msm/vidc/common/vcd/vcd.h
index 3e02030..8f44a56 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd.h
+++ b/drivers/video/msm/vidc/common/vcd/vcd.h
@@ -397,4 +397,5 @@
u32 vcd_update_decoder_perf_level(struct vcd_dev_ctxt *dev_ctxt, u32 perf_lvl);
+u32 vcd_set_perf_turbo_level(struct vcd_clnt_ctxt *cctxt);
#endif
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_client_sm.c b/drivers/video/msm/vidc/common/vcd/vcd_client_sm.c
index 5019d31..7c0d9fe 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_client_sm.c
+++ b/drivers/video/msm/vidc/common/vcd/vcd_client_sm.c
@@ -541,6 +541,12 @@
}
break;
}
+ case VCD_I_SET_TURBO_CLK:
+ {
+ if (cctxt->sched_clnt_hdl)
+ rc = vcd_set_perf_turbo_level(cctxt);
+ break;
+ }
case VCD_I_INTRA_PERIOD:
{
struct vcd_property_i_period *iperiod =
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_core.h b/drivers/video/msm/vidc/common/vcd/vcd_core.h
index 7ae4f45..5351589 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_core.h
+++ b/drivers/video/msm/vidc/common/vcd/vcd_core.h
@@ -146,7 +146,7 @@
u32 reqd_perf_lvl;
u32 curr_perf_lvl;
u32 set_perf_lvl_pending;
-
+ u32 turbo_mode_set;
};
struct vcd_clnt_status {
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_device_sm.c b/drivers/video/msm/vidc/common/vcd/vcd_device_sm.c
index d517028..2b534f1 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_device_sm.c
+++ b/drivers/video/msm/vidc/common/vcd/vcd_device_sm.c
@@ -219,6 +219,7 @@
VCD_DEVICE_STATE_INITING,
ev_code);
}
+ dev_ctxt->turbo_mode_set = 0;
return rc;
}
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_power_sm.c b/drivers/video/msm/vidc/common/vcd/vcd_power_sm.c
index beaa872..80e03ba 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_power_sm.c
+++ b/drivers/video/msm/vidc/common/vcd/vcd_power_sm.c
@@ -15,6 +15,7 @@
#include "vcd_power_sm.h"
#include "vcd_core.h"
#include "vcd.h"
+#include "vcd_res_tracker.h"
u32 vcd_power_event(
struct vcd_dev_ctxt *dev_ctxt,
@@ -297,6 +298,24 @@
return rc;
}
+u32 vcd_set_perf_turbo_level(struct vcd_clnt_ctxt *cctxt)
+{
+ u32 rc = VCD_S_SUCCESS;
+#ifdef CONFIG_MSM_BUS_SCALING
+ struct vcd_dev_ctxt *dev_ctxt = cctxt->dev_ctxt;
+ pr_err("\n Setting Turbo mode !!");
+
+ if (res_trk_update_bus_perf_level(dev_ctxt,
+ RESTRK_1080P_TURBO_PERF_LEVEL) < 0) {
+ pr_err("\n %s(): update buf perf level failed\n",
+ __func__);
+ return false;
+ }
+ dev_ctxt->curr_perf_lvl = RESTRK_1080P_TURBO_PERF_LEVEL;
+#endif
+ return rc;
+}
+
u32 vcd_update_decoder_perf_level(struct vcd_dev_ctxt *dev_ctxt, u32 perf_lvl)
{
u32 rc = VCD_S_SUCCESS;
diff --git a/include/linux/input/mpu3050.h b/include/linux/input/mpu3050.h
new file mode 100644
index 0000000..6006abb
--- /dev/null
+++ b/include/linux/input/mpu3050.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __MPU3050_H__
+#define __MPU3050_H__
+
+struct mpu3050_gyro_platform_data {
+ int poll_interval;
+ int min_interval;
+
+ int (*init)(void);
+ void (*exit)(void);
+ int (*power_on)(void);
+ int (*power_off)(void);
+
+ int gpio_int;
+ int gpio_fsync;
+};
+
+#endif /* __MPU3050_H__ */
diff --git a/include/linux/ion.h b/include/linux/ion.h
index d9443ff..591f146 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -86,6 +86,14 @@
FIXED_HIGH,
};
+enum cp_mem_usage {
+ VIDEO_BITSTREAM = 0x1,
+ VIDEO_PIXEL = 0x2,
+ VIDEO_NONPIXEL = 0x3,
+ MAX_USAGE = 0x4,
+ UNKNOWN = 0x7FFFFFFF,
+};
+
/**
* Flag to use when allocating to indicate that a heap is secure.
*/
diff --git a/include/linux/mfd/pm8xxx/pm8038.h b/include/linux/mfd/pm8xxx/pm8038.h
index 90557b9..682abc8 100644
--- a/include/linux/mfd/pm8xxx/pm8038.h
+++ b/include/linux/mfd/pm8xxx/pm8038.h
@@ -33,6 +33,7 @@
#include <linux/leds-pm8xxx.h>
#include <linux/mfd/pm8xxx/ccadc.h>
#include <linux/mfd/pm8xxx/spk.h>
+#include <linux/mfd/pm8xxx/tm.h>
#define PM8038_CORE_DEV_NAME "pm8038-core"
@@ -64,6 +65,9 @@
#define PM8038_RESOUT_IRQ PM8038_IRQ_BLOCK_BIT(6, 4)
+#define PM8038_OVERTEMP_IRQ PM8038_IRQ_BLOCK_BIT(4, 2)
+#define PM8038_TEMPSTAT_IRQ PM8038_IRQ_BLOCK_BIT(6, 7)
+
struct pm8038_platform_data {
int irq_base;
struct pm8xxx_gpio_platform_data *gpio_pdata;
diff --git a/include/linux/msm_vidc_dec.h b/include/linux/msm_vidc_dec.h
index 0c03e13..3d8907a 100644
--- a/include/linux/msm_vidc_dec.h
+++ b/include/linux/msm_vidc_dec.h
@@ -207,6 +207,9 @@
#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \
_IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_SET_PERF_CLK \
+ _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg)
+
enum vdec_picture {
PICTURE_TYPE_I,
PICTURE_TYPE_P,
diff --git a/include/media/msm/vcd_property.h b/include/media/msm/vcd_property.h
index 37d2343..acd0fa3 100644
--- a/include/media/msm/vcd_property.h
+++ b/include/media/msm/vcd_property.h
@@ -54,6 +54,7 @@
#define VCD_REQ_PERF_LEVEL (VCD_START_BASE + 0x26)
#define VCD_I_SLICE_DELIVERY_MODE (VCD_START_BASE + 0x27)
#define VCD_I_VOP_TIMING_CONSTANT_DELTA (VCD_START_BASE + 0x28)
+#define VCD_I_SET_TURBO_CLK (VCD_START_BASE + 0x29)
#define VCD_START_REQ (VCD_START_BASE + 0x1000)
#define VCD_I_REQ_IFRAME (VCD_START_REQ + 0x1)
diff --git a/include/media/msm_isp.h b/include/media/msm_isp.h
index cb728a0..333d0df 100644
--- a/include/media/msm_isp.h
+++ b/include/media/msm_isp.h
@@ -327,5 +327,10 @@
#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
+struct msm_frame_info {
+ uint32_t image_mode;
+ uint32_t path;
+};
+
#endif /*__MSM_ISP_H__*/
diff --git a/include/media/tavarua.h b/include/media/tavarua.h
index 52194f9..9943287 100644
--- a/include/media/tavarua.h
+++ b/include/media/tavarua.h
@@ -172,6 +172,10 @@
V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, /* 0x800002E */
V4L2_CID_PRIVATE_SINR_THRESHOLD, /* 0x800002F : IRIS */
V4L2_CID_PRIVATE_SINR_SAMPLES, /* 0x8000030 : IRIS */
+ V4L2_CID_PRIVATE_SPUR_FREQ,
+ V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI,
+ V4L2_CID_PRIVATE_SPUR_SELECTION,
+ V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE,
};
@@ -484,4 +488,47 @@
TAVARUA_REGION_OTHER
};
+enum {
+ ONE_BYTE = 1,
+ TWO_BYTE,
+ THREE_BYTE,
+ FOUR_BYTE,
+ FIVE_BYTE,
+ SIX_BYTE,
+ SEVEN_BYTE,
+ EIGHT_BYTE,
+ NINE_BYTE,
+ TEN_BYTE,
+ ELEVEN_BYTE,
+ TWELVE_BYTE,
+ THIRTEEN_BYTE
+};
+#define XFR_READ (0)
+#define XFR_WRITE (1)
+#define XFR_MODE_OFFSET (0)
+#define XFR_ADDR_MSB_OFFSET (1)
+#define XFR_ADDR_LSB_OFFSET (2)
+#define XFR_DATA_OFFSET (3)
+#define SPUR_DATA_SIZE (3)
+#define MAX_SPUR_FREQ_LIMIT (30)
+#define READ_COMPLETE (0x20)
+#define SPUR_TABLE_ADDR (0x0BB7)
+#define SPUR_TABLE_START_ADDR (SPUR_TABLE_ADDR + 1)
+#define XFR_PEEK_COMPLETE (XFR_PEEK_MODE | READ_COMPLETE)
+#define XFR_POKE_COMPLETE (XFR_POKE_MODE)
+
+#define COMPUTE_SPUR(val) ((((val) - (76000)) / (50)))
+#define GET_FREQ(val, bit) ((bit == 1) ? ((val) >> 8) : ((val) & 0xFF))
+
+struct fm_spur_data {
+ int freq[MAX_SPUR_FREQ_LIMIT];
+ __s8 rmssi[MAX_SPUR_FREQ_LIMIT];
+} __packed;
+
+struct fm_def_data_wr_req {
+ __u8 mode;
+ __u8 length;
+ __u8 data[XFR_REG_NUM];
+} __packed;
+
#endif /* __LINUX_TAVARUA_H */
diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
index 4676a02..17fef15 100644
--- a/include/sound/soc-dai.h
+++ b/include/sound/soc-dai.h
@@ -241,7 +241,7 @@
struct snd_soc_dai_driver *driver;
/* DAI runtime info */
- unsigned int capture_active:1; /* stream is in use */
+ unsigned int capture_active; /* stream is in use */
unsigned int playback_active:1; /* stream is in use */
unsigned int symmetric_rates:1;
struct snd_pcm_runtime *runtime;
diff --git a/sound/soc/codecs/wcd9304.c b/sound/soc/codecs/wcd9304.c
index 4193e12..9ade172 100644
--- a/sound/soc/codecs/wcd9304.c
+++ b/sound/soc/codecs/wcd9304.c
@@ -4642,7 +4642,7 @@
/* Initialize current threshold to 350MA
* number of wait and run cycles to 4096
*/
- {SITAR_A_RX_HPH_OCP_CTL, 0xF8, 0x60},
+ {SITAR_A_RX_HPH_OCP_CTL, 0xE0, 0x60},
{SITAR_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
{SITAR_A_QFUSE_CTL, 0xFF, 0x03},
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 7eefe97..e85e9f5 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -4256,7 +4256,8 @@
continue;
if (!strncmp(w->sname,
tabla_dai[j].playback.stream_name, 13)) {
- --tabla_p->dai[j].ch_act;
+ if (tabla_p->dai[j].ch_act)
+ --tabla_p->dai[j].ch_act;
break;
}
}
diff --git a/sound/soc/msm/msm-dai-fe.c b/sound/soc/msm/msm-dai-fe.c
index 6e190b2..56e83d5 100644
--- a/sound/soc/msm/msm-dai-fe.c
+++ b/sound/soc/msm/msm-dai-fe.c
@@ -426,6 +426,30 @@
.ops = &msm_fe_dai_ops,
.name = "SEC_I2S_RX_HOSTLESS",
},
+ {
+ .playback = {
+ .stream_name = "SGLTE Playback",
+ .aif_name = "SGLTE_DL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .capture = {
+ .stream_name = "SGLTE Capture",
+ .aif_name = "SGLTE_UL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_dai_ops,
+ .name = "SGLTE",
+ },
};
static __devinit int msm_fe_dai_dev_probe(struct platform_device *pdev)
diff --git a/sound/soc/msm/msm-pcm-lpa.c b/sound/soc/msm/msm-pcm-lpa.c
index 66a8854..269b49b 100644
--- a/sound/soc/msm/msm-pcm-lpa.c
+++ b/sound/soc/msm/msm-pcm-lpa.c
@@ -109,15 +109,16 @@
break;
} else
atomic_set(&prtd->pending_buffer, 0);
+
+ buf = prtd->audio_client->port[IN].buf;
if (runtime->status->hw_ptr >= runtime->control->appl_ptr) {
- memset((void *)buf[0].phys +
+ memset((void *)buf[0].data +
(prtd->out_head * prtd->pcm_count),
0, prtd->pcm_count);
}
pr_debug("%s:writing %d bytes of buffer to dsp 2\n",
__func__, prtd->pcm_count);
- buf = prtd->audio_client->port[IN].buf;
param.paddr = (unsigned long)buf[0].phys
+ (prtd->out_head * prtd->pcm_count);
param.len = prtd->pcm_count;
diff --git a/sound/soc/msm/msm-pcm-routing.c b/sound/soc/msm/msm-pcm-routing.c
index 4e1ce52..bd900b3 100644
--- a/sound/soc/msm/msm-pcm-routing.c
+++ b/sound/soc/msm/msm-pcm-routing.c
@@ -505,6 +505,8 @@
session_id = voc_get_session_id(VOICE_SESSION_NAME);
else if (val == MSM_FRONTEND_DAI_VOLTE)
session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ else if (val == MSM_FRONTEND_DAI_SGLTE)
+ session_id = voc_get_session_id(SGLTE_SESSION_NAME);
else
session_id = voc_get_session_id(VOIP_SESSION_NAME);
@@ -1303,6 +1305,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_PRI_I2S_RX,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_PRI_I2S_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new sec_i2s_rx_voice_mixer_controls[] = {
@@ -1315,6 +1320,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_SEC_I2S_RX,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new slimbus_rx_voice_mixer_controls[] = {
@@ -1327,6 +1335,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_SLIMBUS_0_RX ,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_SLIMBUS_0_RX ,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new bt_sco_rx_voice_mixer_controls[] = {
@@ -1342,6 +1353,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_INT_BT_SCO_RX ,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_INT_BT_SCO_RX ,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new mi2s_rx_voice_mixer_controls[] = {
@@ -1354,6 +1368,9 @@
SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_MI2S_RX,
MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer,
msm_routing_put_voice_stub_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new afe_pcm_rx_voice_mixer_controls[] = {
@@ -1369,6 +1386,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_AFE_PCM_RX,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_AFE_PCM_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new aux_pcm_rx_voice_mixer_controls[] = {
@@ -1384,6 +1404,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_AUXPCM_RX,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_AUXPCM_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new sec_aux_pcm_rx_voice_mixer_controls[] = {
@@ -1396,6 +1419,9 @@
SOC_SINGLE_EXT("VoLTE", MSM_BACKEND_DAI_SEC_AUXPCM_RX,
MSM_FRONTEND_DAI_VOLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_SEC_AUXPCM_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new hdmi_rx_voice_mixer_controls[] = {
@@ -1411,6 +1437,9 @@
SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_HDMI_RX,
MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer,
msm_routing_put_voice_stub_mixer),
+ SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new stub_rx_mixer_controls[] = {
@@ -1476,6 +1505,29 @@
msm_routing_put_voice_mixer),
};
+static const struct snd_kcontrol_new tx_sglte_mixer_controls[] = {
+ SOC_SINGLE_EXT("PRI_TX_SGLTE", MSM_BACKEND_DAI_PRI_I2S_TX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("MI2S_TX_SGLTE", MSM_BACKEND_DAI_MI2S_TX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SLIM_0_TX_SGLTE", MSM_BACKEND_DAI_SLIMBUS_0_TX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX_SGLTE",
+ MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_SGLTE, 1, 0,
+ msm_routing_get_voice_mixer, msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("AFE_PCM_TX_SGLTE", MSM_BACKEND_DAI_AFE_PCM_TX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("AUX_PCM_TX_SGLTE", MSM_BACKEND_DAI_AUXPCM_TX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("SEC_AUX_PCM_TX_SGLTE", MSM_BACKEND_DAI_SEC_AUXPCM_TX,
+ MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
+};
static const struct snd_kcontrol_new tx_voip_mixer_controls[] = {
SOC_SINGLE_EXT("PRI_TX_Voip", MSM_BACKEND_DAI_PRI_I2S_TX,
MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer,
@@ -1878,6 +1930,8 @@
SND_SOC_DAPM_AIF_OUT("CS-VOICE_UL1", "CS-VOICE Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("VoLTE_DL", "VoLTE Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("VoLTE_UL", "VoLTE Capture", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SGLTE_DL", "SGLTE Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SGLTE_UL", "SGLTE Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("VOIP_UL", "VoIP Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIM0_DL_HL", "SLIMBUS0_HOSTLESS Playback",
0, 0, 0, 0),
@@ -2025,6 +2079,9 @@
SND_SOC_DAPM_MIXER("VoLTE_Tx Mixer",
SND_SOC_NOPM, 0, 0, tx_volte_mixer_controls,
ARRAY_SIZE(tx_volte_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SGLTE_Tx Mixer",
+ SND_SOC_NOPM, 0, 0, tx_sglte_mixer_controls,
+ ARRAY_SIZE(tx_sglte_mixer_controls)),
SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
int_bt_sco_rx_mixer_controls, ARRAY_SIZE(int_bt_sco_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("INTERNAL_FM_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
@@ -2175,41 +2232,49 @@
{"PRI_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"PRI_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"PRI_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"PRI_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"PRI_I2S_RX", NULL, "PRI_RX_Voice Mixer"},
{"SEC_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"SEC_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"SEC_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"SEC_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"SEC_I2S_RX", NULL, "SEC_RX_Voice Mixer"},
{"SLIM_0_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"SLIM_0_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"SLIM_0_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"SLIM_0_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"SLIMBUS_0_RX", NULL, "SLIM_0_RX_Voice Mixer"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"INTERNAL_BT_SCO_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX_Voice Mixer"},
{"AFE_PCM_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"AFE_PCM_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"AFE_PCM_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"AFE_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"PCM_RX", NULL, "AFE_PCM_RX_Voice Mixer"},
{"AUX_PCM_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"AUX_PCM_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"AUX_PCM_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"AUX_PCM_RX", NULL, "AUX_PCM_RX_Voice Mixer"},
{"SEC_AUX_PCM_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"SEC_AUX_PCM_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"SEC_AUX_PCM_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"SEC_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"SEC_AUX_PCM_RX", NULL, "SEC_AUX_PCM_RX_Voice Mixer"},
{"HDMI_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"HDMI_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
+ {"HDMI_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"HDMI_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"HDMI", NULL, "HDMI_RX_Voice Mixer"},
{"HDMI", NULL, "HDMI_DL_HL"},
@@ -2229,6 +2294,14 @@
{"VoLTE_Tx Mixer", "AUX_PCM_TX_VoLTE", "AUX_PCM_TX"},
{"VoLTE_Tx Mixer", "SEC_AUX_PCM_TX_VoLTE", "SEC_AUX_PCM_TX"},
{"VoLTE_UL", NULL, "VoLTE_Tx Mixer"},
+ {"SGLTE_Tx Mixer", "PRI_TX_SGLTE", "PRI_I2S_TX"},
+ {"SGLTE_Tx Mixer", "MI2S_TX_SGLTE", "MI2S_TX"},
+ {"SGLTE_Tx Mixer", "SLIM_0_TX_SGLTE", "SLIMBUS_0_TX"},
+ {"SGLTE_Tx Mixer", "INTERNAL_BT_SCO_TX_SGLTE", "INT_BT_SCO_TX"},
+ {"SGLTE_Tx Mixer", "AFE_PCM_TX_SGLTE", "PCM_TX"},
+ {"SGLTE_Tx Mixer", "AUX_PCM_TX_SGLTE", "AUX_PCM_TX"},
+ {"SGLTE_Tx Mixer", "SEC_AUX_PCM_TX_SGLTE", "SEC_AUX_PCM_TX"},
+ {"SGLTE_UL", NULL, "SGLTE_Tx Mixer"},
{"Voip_Tx Mixer", "PRI_TX_Voip", "PRI_I2S_TX"},
{"Voip_Tx Mixer", "MI2S_TX_Voip", "MI2S_TX"},
{"Voip_Tx Mixer", "SLIM_0_TX_Voip", "SLIMBUS_0_TX"},
diff --git a/sound/soc/msm/msm-pcm-routing.h b/sound/soc/msm/msm-pcm-routing.h
index d1230ad..2f213e7 100644
--- a/sound/soc/msm/msm-pcm-routing.h
+++ b/sound/soc/msm/msm-pcm-routing.h
@@ -66,6 +66,7 @@
MSM_FRONTEND_DAI_AFE_TX,
MSM_FRONTEND_DAI_VOICE_STUB,
MSM_FRONTEND_DAI_VOLTE,
+ MSM_FRONTEND_DAI_SGLTE,
MSM_FRONTEND_DAI_MAX,
};
diff --git a/sound/soc/msm/msm-pcm-voice.c b/sound/soc/msm/msm-pcm-voice.c
index 7bdb4f0..633973e 100644
--- a/sound/soc/msm/msm-pcm-voice.c
+++ b/sound/soc/msm/msm-pcm-voice.c
@@ -59,6 +59,14 @@
return false;
}
+static int is_sglte(struct msm_voice *psglte)
+{
+ if (psglte == &voice_info[SGLTE_SESSION_INDEX])
+ return true;
+ else
+ return false;
+}
+
static int msm_pcm_playback_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
@@ -93,6 +101,10 @@
voice = &voice_info[VOLTE_SESSION_INDEX];
pr_debug("%s: Open VoLTE Substream Id=%s\n",
__func__, substream->pcm->id);
+ } else if (!strncmp("SGLTE", substream->pcm->id, 5)) {
+ voice = &voice_info[SGLTE_SESSION_INDEX];
+ pr_debug("%s: Open SGLTE Substream Id=%s\n",
+ __func__, substream->pcm->id);
} else {
voice = &voice_info[VOICE_SESSION_INDEX];
pr_debug("%s: Open VOICE Substream Id=%s\n",
@@ -162,6 +174,8 @@
pr_debug("end voice call\n");
if (is_volte(prtd))
session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ else if (is_sglte(prtd))
+ session_id = voc_get_session_id(SGLTE_SESSION_NAME);
else
session_id = voc_get_session_id(VOICE_SESSION_NAME);
voc_end_voice_call(session_id);
@@ -187,6 +201,8 @@
if (prtd->playback_start && prtd->capture_start) {
if (is_volte(prtd))
session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ else if (is_sglte(prtd))
+ session_id = voc_get_session_id(SGLTE_SESSION_NAME);
else
session_id = voc_get_session_id(VOICE_SESSION_NAME);
voc_start_voice_call(session_id);
@@ -217,6 +233,8 @@
pr_debug("%s: cmd = %d\n", __func__, cmd);
if (is_volte(prtd))
session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ else if (is_sglte(prtd))
+ session_id = voc_get_session_id(SGLTE_SESSION_NAME);
else
session_id = voc_get_session_id(VOICE_SESSION_NAME);
@@ -290,6 +308,23 @@
return 0;
}
+static int msm_sglte_volume_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = 0;
+ return 0;
+}
+
+static int msm_sglte_volume_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int volume = ucontrol->value.integer.value[0];
+ pr_debug("%s: volume: %d\n", __func__, volume);
+ voc_set_rx_vol_index(voc_get_session_id(SGLTE_SESSION_NAME),
+ RX_PATH, volume);
+ return 0;
+}
+
static int msm_voice_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -328,6 +363,25 @@
return 0;
}
+static int msm_sglte_mute_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = 0;
+ return 0;
+}
+
+static int msm_sglte_mute_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = ucontrol->value.integer.value[0];
+
+ pr_debug("%s: mute=%d\n", __func__, mute);
+
+ voc_set_tx_mute(voc_get_session_id(SGLTE_SESSION_NAME), TX_PATH, mute);
+
+ return 0;
+}
+
static int msm_voice_rx_device_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -368,6 +422,26 @@
return 0;
}
+static int msm_sglte_rx_device_mute_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] =
+ voc_get_rx_device_mute(voc_get_session_id(SGLTE_SESSION_NAME));
+ return 0;
+}
+
+static int msm_sglte_rx_device_mute_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = ucontrol->value.integer.value[0];
+
+ pr_debug("%s: mute=%d\n", __func__, mute);
+
+ voc_set_rx_device_mute(voc_get_session_id(SGLTE_SESSION_NAME), mute);
+
+ return 0;
+}
+
static const char const *tty_mode[] = {"OFF", "HCO", "VCO", "FULL"};
static const struct soc_enum msm_tty_mode_enum[] = {
SOC_ENUM_SINGLE_EXT(4, tty_mode),
@@ -481,6 +555,13 @@
msm_volte_mute_get, msm_volte_mute_put),
SOC_SINGLE_EXT("VoLTE Rx Volume", SND_SOC_NOPM, 0, 5, 0,
msm_volte_volume_get, msm_volte_volume_put),
+ SOC_SINGLE_EXT("SGLTE Rx Device Mute", SND_SOC_NOPM, 0, 1, 0,
+ msm_sglte_rx_device_mute_get,
+ msm_sglte_rx_device_mute_put),
+ SOC_SINGLE_EXT("SGLTE Tx Mute", SND_SOC_NOPM, 0, 1, 0,
+ msm_sglte_mute_get, msm_sglte_mute_put),
+ SOC_SINGLE_EXT("SGLTE Rx Volume", SND_SOC_NOPM, 0, 5, 0,
+ msm_sglte_volume_get, msm_sglte_volume_put),
};
static struct snd_pcm_ops msm_pcm_ops = {
@@ -543,6 +624,7 @@
memset(&voice_info, 0, sizeof(voice_info));
mutex_init(&voice_info[VOICE_SESSION_INDEX].lock);
mutex_init(&voice_info[VOLTE_SESSION_INDEX].lock);
+ mutex_init(&voice_info[SGLTE_SESSION_INDEX].lock);
return platform_driver_register(&msm_pcm_driver);
}
diff --git a/sound/soc/msm/msm-pcm-voice.h b/sound/soc/msm/msm-pcm-voice.h
index aa00577..41aca89 100644
--- a/sound/soc/msm/msm-pcm-voice.h
+++ b/sound/soc/msm/msm-pcm-voice.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011,2012 Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -16,6 +16,7 @@
enum {
VOICE_SESSION_INDEX,
VOLTE_SESSION_INDEX,
+ SGLTE_SESSION_INDEX,
VOICE_SESSION_INDEX_MAX,
};
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 98cfa6d..2c44b46 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -1321,6 +1321,21 @@
.codec_name = "snd-soc-dummy",
.be_id = MSM_FRONTEND_DAI_VOLTE,
},
+ {
+ .name = "SGLTE",
+ .stream_name = "SGLTE",
+ .cpu_dai_name = "SGLTE",
+ .platform_name = "msm-pcm-voice",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1,/* this dainlink has playback support */
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .be_id = MSM_FRONTEND_DAI_SGLTE,
+ },
/* Backend BT/FM DAI Links */
{
.name = LPASS_BE_INT_BT_SCO_RX,
diff --git a/sound/soc/msm/qdsp6/q6voice.c b/sound/soc/msm/qdsp6/q6voice.c
index 0c30dc9..f66a01c 100644
--- a/sound/soc/msm/qdsp6/q6voice.c
+++ b/sound/soc/msm/qdsp6/q6voice.c
@@ -34,6 +34,7 @@
#define VOC_PATH_PASSIVE 0
#define VOC_PATH_FULL 1
#define VOC_PATH_VOLTE_PASSIVE 2
+#define VOC_PATH_SGLTE_PASSIVE 3
/* CVP CAL Size: 245760 = 240 * 1024 */
#define CVP_CAL_SIZE 245760
@@ -149,6 +150,9 @@
else if (!strncmp(name, "VoLTE session", 13))
session_id =
common.voice[VOC_PATH_VOLTE_PASSIVE].session_id;
+ else if (!strncmp(name, "SGLTE session", 13))
+ session_id =
+ common.voice[VOC_PATH_SGLTE_PASSIVE].session_id;
else
session_id = common.voice[VOC_PATH_FULL].session_id;
@@ -189,6 +193,11 @@
return (session_id == common.voice[VOC_PATH_VOLTE_PASSIVE].session_id);
}
+static bool is_sglte_session(u16 session_id)
+{
+ return (session_id == common.voice[VOC_PATH_SGLTE_PASSIVE].session_id);
+}
+
static int voice_apr_register(void)
{
pr_debug("%s\n", __func__);
@@ -275,8 +284,10 @@
pr_err("%s: apr_mvm is NULL.\n", __func__);
return -EINVAL;
}
- pr_debug("%s: VoLTE command to MVM\n", __func__);
- if (is_volte_session(v->session_id)) {
+ pr_debug("%s: VoLTE/SGLTE command to MVM\n", __func__);
+ if (is_volte_session(v->session_id) ||
+ is_sglte_session(v->session_id)) {
+
mvm_handle = voice_get_mvm_handle(v);
mvm_voice_ctl_cmd.hdr.hdr_field = APR_HDR_FIELD(
APR_MSG_TYPE_SEQ_CMD,
@@ -350,7 +361,8 @@
if (!mvm_handle) {
if (is_voice_session(v->session_id) ||
- is_volte_session(v->session_id)) {
+ is_volte_session(v->session_id) ||
+ is_sglte_session(v->session_id)) {
mvm_session_cmd.hdr.hdr_field = APR_HDR_FIELD(
APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
@@ -369,11 +381,15 @@
if (is_volte_session(v->session_id)) {
strlcpy(mvm_session_cmd.mvm_session.name,
"default volte voice",
+ sizeof(mvm_session_cmd.mvm_session.name) - 1);
+ } else if (is_sglte_session(v->session_id)) {
+ strlcpy(mvm_session_cmd.mvm_session.name,
+ "default modem voice2",
sizeof(mvm_session_cmd.mvm_session.name));
} else {
- strlcpy(mvm_session_cmd.mvm_session.name,
+ strlcpy(mvm_session_cmd.mvm_session.name,
"default modem voice",
- sizeof(mvm_session_cmd.mvm_session.name));
+ sizeof(mvm_session_cmd.mvm_session.name) - 1);
}
v->mvm_state = CMD_STATUS_FAIL;
@@ -432,7 +448,8 @@
/* send cmd to create cvs session */
if (!cvs_handle) {
if (is_voice_session(v->session_id) ||
- is_volte_session(v->session_id)) {
+ is_volte_session(v->session_id) ||
+ is_sglte_session(v->session_id)) {
pr_debug("%s: creating CVS passive session\n",
__func__);
@@ -452,11 +469,15 @@
if (is_volte_session(v->session_id)) {
strlcpy(mvm_session_cmd.mvm_session.name,
"default volte voice",
- sizeof(mvm_session_cmd.mvm_session.name));
- } else {
- strlcpy(cvs_session_cmd.cvs_session.name,
- "default modem voice",
+ sizeof(mvm_session_cmd.mvm_session.name) - 1);
+ } else if (is_sglte_session(v->session_id)) {
+ strlcpy(cvs_session_cmd.cvs_session.name,
+ "default modem voice2",
sizeof(cvs_session_cmd.cvs_session.name));
+ } else {
+ strlcpy(cvs_session_cmd.cvs_session.name,
+ "default modem voice",
+ sizeof(cvs_session_cmd.cvs_session.name) - 1);
}
v->cvs_state = CMD_STATUS_FAIL;
diff --git a/sound/soc/msm/qdsp6/q6voice.h b/sound/soc/msm/qdsp6/q6voice.h
index 88ab0d5..468aba8 100644
--- a/sound/soc/msm/qdsp6/q6voice.h
+++ b/sound/soc/msm/qdsp6/q6voice.h
@@ -16,7 +16,7 @@
#include <linux/ion.h>
#define MAX_VOC_PKT_SIZE 642
-#define SESSION_NAME_LEN 20
+#define SESSION_NAME_LEN 21
#define VOC_REC_UPLINK 0x00
#define VOC_REC_DOWNLINK 0x01
@@ -918,7 +918,7 @@
void *buf;
};
-#define MAX_VOC_SESSIONS 3
+#define MAX_VOC_SESSIONS 4
#define SESSION_ID_BASE 0xFFF0
struct common_data {
@@ -990,6 +990,7 @@
#define VOICE_SESSION_NAME "Voice session"
#define VOIP_SESSION_NAME "VoIP session"
#define VOLTE_SESSION_NAME "VoLTE session"
+#define SGLTE_SESSION_NAME "SGLTE session"
uint16_t voc_get_session_id(char *name);
int voc_start_playback(uint32_t set);
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 3a9fbe1..fd3fe6a 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -236,11 +236,24 @@
}
if (codec_dai->driver->ops->startup) {
- ret = codec_dai->driver->ops->startup(substream, codec_dai);
- if (ret < 0) {
- printk(KERN_ERR "asoc: can't open codec %s\n",
- codec_dai->name);
- goto codec_dai_err;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = codec_dai->driver->ops->startup(substream,
+ codec_dai);
+ if (ret < 0) {
+ printk(KERN_ERR "asoc: can't open codec %s\n",
+ codec_dai->name);
+ goto codec_dai_err;
+ }
+ } else {
+ if (!codec_dai->capture_active) {
+ ret = codec_dai->driver->ops->startup(substream,
+ codec_dai);
+ if (ret < 0) {
+ printk(KERN_ERR "can't open codec %s\n",
+ codec_dai->name);
+ goto codec_dai_err;
+ }
+ }
}
}
@@ -456,8 +469,15 @@
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_dai_digital_mute(codec_dai, 1);
- if (cpu_dai->driver->ops->shutdown)
- cpu_dai->driver->ops->shutdown(substream, cpu_dai);
+ if (cpu_dai->driver->ops->shutdown) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ codec_dai->driver->ops->shutdown(substream, codec_dai);
+ } else {
+ if (!codec_dai->capture_active)
+ codec_dai->driver->ops->shutdown(substream,
+ codec_dai);
+ }
+ }
if (codec_dai->driver->ops->shutdown)
codec_dai->driver->ops->shutdown(substream, codec_dai);
@@ -485,7 +505,8 @@
}
} else {
/* capture streams can be powered down now */
- snd_soc_dapm_stream_event(rtd,
+ if (!codec_dai->capture_active)
+ snd_soc_dapm_stream_event(rtd,
codec_dai->driver->capture.stream_name,
SND_SOC_DAPM_STREAM_STOP);
}
@@ -557,11 +578,12 @@
snd_soc_dapm_stream_event(rtd,
codec_dai->driver->playback.stream_name,
SND_SOC_DAPM_STREAM_START);
- else
- snd_soc_dapm_stream_event(rtd,
+ else {
+ if (codec_dai->capture_active == 1)
+ snd_soc_dapm_stream_event(rtd,
codec_dai->driver->capture.stream_name,
SND_SOC_DAPM_STREAM_START);
-
+ }
snd_soc_dai_digital_mute(codec_dai, 0);
out:
@@ -594,11 +616,24 @@
}
if (codec_dai->driver->ops->hw_params) {
- ret = codec_dai->driver->ops->hw_params(substream, params, codec_dai);
- if (ret < 0) {
- printk(KERN_ERR "asoc: can't set codec %s hw params\n",
- codec_dai->name);
- goto codec_err;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = codec_dai->driver->ops->hw_params(substream,
+ params, codec_dai);
+ if (ret < 0) {
+ printk(KERN_ERR "not set codec %s hw params\n",
+ codec_dai->name);
+ goto codec_err;
+ }
+ } else {
+ if (codec_dai->capture_active == 1) {
+ ret = codec_dai->driver->ops->hw_params(
+ substream, params, codec_dai);
+ if (ret < 0) {
+ printk(KERN_ERR "fail: %s hw params\n",
+ codec_dai->name);
+ goto codec_err;
+ }
+ }
}
}
@@ -706,9 +741,19 @@
int ret;
if (codec_dai->driver->ops->trigger) {
- ret = codec_dai->driver->ops->trigger(substream, cmd, codec_dai);
- if (ret < 0)
- return ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = codec_dai->driver->ops->trigger(substream,
+ cmd, codec_dai);
+ if (ret < 0)
+ return ret;
+ } else {
+ if (codec_dai->capture_active == 1) {
+ ret = codec_dai->driver->ops->trigger(
+ substream, cmd, codec_dai);
+ if (ret < 0)
+ return ret;
+ }
+ }
}
if (platform->driver->ops && platform->driver->ops->trigger) {
diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l
index 1fcf1bb..28e5548 100644
--- a/tools/perf/util/parse-events.l
+++ b/tools/perf/util/parse-events.l
@@ -30,6 +30,17 @@
return __value(parse_events_text + 1, 16, PE_RAW);
}
+static int sh_raw(void)
+{
+ return __value(parse_events_text + 2, 16, PE_SH_RAW);
+}
+
+static int fab_raw(void)
+{
+ return __value(parse_events_text + 2, 16, PE_FAB_RAW);
+}
+
+
static int str(int token)
{
parse_events_lval.str = strdup(parse_events_text);
@@ -107,6 +118,8 @@
mem: { return PE_PREFIX_MEM; }
r{num_raw_hex} { return raw(); }
+rs{num_raw_hex} { return sh_raw(); }
+rm{num_raw_hex} { return fab_raw(); }
{num_dec} { return value(10); }
{num_hex} { return value(16); }
diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y
index d9637da..07b292d 100644
--- a/tools/perf/util/parse-events.y
+++ b/tools/perf/util/parse-events.y
@@ -24,7 +24,7 @@
%}
-%token PE_VALUE PE_VALUE_SYM PE_RAW PE_TERM
+%token PE_VALUE PE_VALUE_SYM PE_RAW PE_SH_RAW PE_FAB_RAW PE_TERM
%token PE_NAME
%token PE_MODIFIER_EVENT PE_MODIFIER_BP
%token PE_NAME_CACHE_TYPE PE_NAME_CACHE_OP_RESULT
@@ -33,6 +33,8 @@
%type <num> PE_VALUE
%type <num> PE_VALUE_SYM
%type <num> PE_RAW
+%type <num> PE_SH_RAW
+%type <num> PE_FAB_RAW
%type <num> PE_TERM
%type <str> PE_NAME
%type <str> PE_NAME_CACHE_TYPE
@@ -77,7 +79,9 @@
event_legacy_mem |
event_legacy_tracepoint sep_dc |
event_legacy_numeric sep_dc |
- event_legacy_raw sep_dc
+ event_legacy_raw sep_dc |
+ event_legacy_shared_raw sep_dc |
+ event_legacy_fabric_raw sep_dc
event_pmu:
PE_NAME '/' event_config '/'
@@ -149,6 +153,18 @@
ABORT_ON(parse_events_add_numeric(list_event, idx, PERF_TYPE_RAW, $1, NULL));
}
+event_legacy_shared_raw:
+PE_SH_RAW
+{
+ ABORT_ON(parse_events_add_numeric(list_event, idx, 6, $1, NULL));
+}
+
+event_legacy_fabric_raw:
+PE_FAB_RAW
+{
+ ABORT_ON(parse_events_add_numeric(list_event, idx, 7, $1, NULL));
+}
+
event_config:
event_config ',' event_term
{