Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
diff --git a/drivers/char/ip2/fip_firm.h b/drivers/char/ip2/fip_firm.h
new file mode 100644
index 0000000..4c525fa
--- /dev/null
+++ b/drivers/char/ip2/fip_firm.h
@@ -0,0 +1,2149 @@
+/* fip_firm.h - Intelliport II loadware */
+/* -31232 bytes read from ff.lod */
+
+static unsigned char fip_firm[] __initdata = {
+0x3C,0x42,0x37,0x18,0x02,0x01,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+};
diff --git a/drivers/char/ip2/i2cmd.c b/drivers/char/ip2/i2cmd.c
new file mode 100644
index 0000000..fd299d6
--- /dev/null
+++ b/drivers/char/ip2/i2cmd.c
@@ -0,0 +1,209 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Definition table for In-line and Bypass commands. Applicable
+* only when the standard loadware is active. (This is included
+* source code, not a separate compilation module.)
+*
+*******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Revision History:
+//
+// 10 October 1991 MAG First Draft
+// 7 November 1991 MAG Reflects additional commands.
+// 24 February 1992 MAG Additional commands for 1.4.x loadware
+// 11 March 1992 MAG Additional commands
+// 30 March 1992 MAG Additional command: CMD_DSS_NOW
+// 18 May 1992 MAG Discovered commands 39 & 40 must be at the end of a
+// packet: affects implementation.
+//------------------------------------------------------------------------------
+
+//************
+//* Includes *
+//************
+
+#include "i2cmd.h" /* To get some bit-defines */
+
+//------------------------------------------------------------------------------
+// Here is the table of global arrays which represent each type of command
+// supported in the IntelliPort standard loadware. See also i2cmd.h
+// for a more complete explanation of what is going on.
+//------------------------------------------------------------------------------
+
+// Here are the various globals: note that the names are not used except through
+// the macros defined in i2cmd.h. Also note that although they are character
+// arrays here (for extendability) they are cast to structure pointers in the
+// i2cmd.h macros. See i2cmd.h for flags definitions.
+
+// Length Flags Command
+static UCHAR ct02[] = { 1, BTH, 0x02 }; // DTR UP
+static UCHAR ct03[] = { 1, BTH, 0x03 }; // DTR DN
+static UCHAR ct04[] = { 1, BTH, 0x04 }; // RTS UP
+static UCHAR ct05[] = { 1, BTH, 0x05 }; // RTS DN
+static UCHAR ct06[] = { 1, BYP, 0x06 }; // START FL
+static UCHAR ct07[] = { 2, BTH, 0x07,0 }; // BAUD
+static UCHAR ct08[] = { 2, BTH, 0x08,0 }; // BITS
+static UCHAR ct09[] = { 2, BTH, 0x09,0 }; // STOP
+static UCHAR ct10[] = { 2, BTH, 0x0A,0 }; // PARITY
+static UCHAR ct11[] = { 2, BTH, 0x0B,0 }; // XON
+static UCHAR ct12[] = { 2, BTH, 0x0C,0 }; // XOFF
+static UCHAR ct13[] = { 1, BTH, 0x0D }; // STOP FL
+static UCHAR ct14[] = { 1, BYP|VIP, 0x0E }; // ACK HOTK
+//static UCHAR ct15[]={ 2, BTH|VIP, 0x0F,0 }; // IRQ SET
+static UCHAR ct16[] = { 2, INL, 0x10,0 }; // IXONOPTS
+static UCHAR ct17[] = { 2, INL, 0x11,0 }; // OXONOPTS
+static UCHAR ct18[] = { 1, INL, 0x12 }; // CTSENAB
+static UCHAR ct19[] = { 1, BTH, 0x13 }; // CTSDSAB
+static UCHAR ct20[] = { 1, INL, 0x14 }; // DCDENAB
+static UCHAR ct21[] = { 1, BTH, 0x15 }; // DCDDSAB
+static UCHAR ct22[] = { 1, BTH, 0x16 }; // DSRENAB
+static UCHAR ct23[] = { 1, BTH, 0x17 }; // DSRDSAB
+static UCHAR ct24[] = { 1, BTH, 0x18 }; // RIENAB
+static UCHAR ct25[] = { 1, BTH, 0x19 }; // RIDSAB
+static UCHAR ct26[] = { 2, BTH, 0x1A,0 }; // BRKENAB
+static UCHAR ct27[] = { 1, BTH, 0x1B }; // BRKDSAB
+//static UCHAR ct28[]={ 2, BTH, 0x1C,0 }; // MAXBLOKSIZE
+//static UCHAR ct29[]={ 2, 0, 0x1D,0 }; // reserved
+static UCHAR ct30[] = { 1, INL, 0x1E }; // CTSFLOWENAB
+static UCHAR ct31[] = { 1, INL, 0x1F }; // CTSFLOWDSAB
+static UCHAR ct32[] = { 1, INL, 0x20 }; // RTSFLOWENAB
+static UCHAR ct33[] = { 1, INL, 0x21 }; // RTSFLOWDSAB
+static UCHAR ct34[] = { 2, BTH, 0x22,0 }; // ISTRIPMODE
+static UCHAR ct35[] = { 2, BTH|END, 0x23,0 }; // SENDBREAK
+static UCHAR ct36[] = { 2, BTH, 0x24,0 }; // SETERRMODE
+//static UCHAR ct36a[]={ 3, INL, 0x24,0,0 }; // SET_REPLACE
+
+// The following is listed for completeness, but should never be sent directly
+// by user-level code. It is sent only by library routines in response to data
+// movement.
+//static UCHAR ct37[]={ 5, BYP|VIP, 0x25,0,0,0,0 }; // FLOW PACKET
+
+// Back to normal
+//static UCHAR ct38[] = {11, BTH|VAR, 0x26,0,0,0,0,0,0,0,0,0,0 }; // DEF KEY SEQ
+//static UCHAR ct39[]={ 3, BTH|END, 0x27,0,0 }; // OPOSTON
+//static UCHAR ct40[]={ 1, BTH|END, 0x28 }; // OPOSTOFF
+static UCHAR ct41[] = { 1, BYP, 0x29 }; // RESUME
+//static UCHAR ct42[]={ 2, BTH, 0x2A,0 }; // TXBAUD
+//static UCHAR ct43[]={ 2, BTH, 0x2B,0 }; // RXBAUD
+//static UCHAR ct44[]={ 2, BTH, 0x2C,0 }; // MS PING
+//static UCHAR ct45[]={ 1, BTH, 0x2D }; // HOTENAB
+//static UCHAR ct46[]={ 1, BTH, 0x2E }; // HOTDSAB
+static UCHAR ct47[] = { 7, BTH, 0x2F,0,0,0,0,0,0 }; // UNIX FLAGS
+//static UCHAR ct48[]={ 1, BTH, 0x30 }; // DSRFLOWENAB
+//static UCHAR ct49[]={ 1, BTH, 0x31 }; // DSRFLOWDSAB
+//static UCHAR ct50[]={ 1, BTH, 0x32 }; // DTRFLOWENAB
+//static UCHAR ct51[]={ 1, BTH, 0x33 }; // DTRFLOWDSAB
+//static UCHAR ct52[]={ 1, BTH, 0x34 }; // BAUDTABRESET
+//static UCHAR ct53[] = { 3, BTH, 0x35,0,0 }; // BAUDREMAP
+static UCHAR ct54[] = { 3, BTH, 0x36,0,0 }; // CUSTOMBAUD1
+static UCHAR ct55[] = { 3, BTH, 0x37,0,0 }; // CUSTOMBAUD2
+static UCHAR ct56[] = { 2, BTH|END, 0x38,0 }; // PAUSE
+static UCHAR ct57[] = { 1, BYP, 0x39 }; // SUSPEND
+static UCHAR ct58[] = { 1, BYP, 0x3A }; // UNSUSPEND
+static UCHAR ct59[] = { 2, BTH, 0x3B,0 }; // PARITYCHK
+static UCHAR ct60[] = { 1, INL|VIP, 0x3C }; // BOOKMARKREQ
+//static UCHAR ct61[]={ 2, BTH, 0x3D,0 }; // INTERNALLOOP
+//static UCHAR ct62[]={ 2, BTH, 0x3E,0 }; // HOTKTIMEOUT
+static UCHAR ct63[] = { 2, INL, 0x3F,0 }; // SETTXON
+static UCHAR ct64[] = { 2, INL, 0x40,0 }; // SETTXOFF
+//static UCHAR ct65[]={ 2, BTH, 0x41,0 }; // SETAUTORTS
+//static UCHAR ct66[]={ 2, BTH, 0x42,0 }; // SETHIGHWAT
+//static UCHAR ct67[]={ 2, BYP, 0x43,0 }; // STARTSELFL
+//static UCHAR ct68[]={ 2, INL, 0x44,0 }; // ENDSELFL
+//static UCHAR ct69[]={ 1, BYP, 0x45 }; // HWFLOW_OFF
+//static UCHAR ct70[]={ 1, BTH, 0x46 }; // ODSRFL_ENAB
+//static UCHAR ct71[]={ 1, BTH, 0x47 }; // ODSRFL_DSAB
+//static UCHAR ct72[]={ 1, BTH, 0x48 }; // ODCDFL_ENAB
+//static UCHAR ct73[]={ 1, BTH, 0x49 }; // ODCDFL_DSAB
+//static UCHAR ct74[]={ 2, BTH, 0x4A,0 }; // LOADLEVEL
+//static UCHAR ct75[]={ 2, BTH, 0x4B,0 }; // STATDATA
+//static UCHAR ct76[]={ 1, BYP, 0x4C }; // BREAK_ON
+//static UCHAR ct77[]={ 1, BYP, 0x4D }; // BREAK_OFF
+//static UCHAR ct78[]={ 1, BYP, 0x4E }; // GETFC
+static UCHAR ct79[] = { 2, BYP, 0x4F,0 }; // XMIT_NOW
+//static UCHAR ct80[]={ 4, BTH, 0x50,0,0,0 }; // DIVISOR_LATCH
+//static UCHAR ct81[]={ 1, BYP, 0x51 }; // GET_STATUS
+//static UCHAR ct82[]={ 1, BYP, 0x52 }; // GET_TXCNT
+//static UCHAR ct83[]={ 1, BYP, 0x53 }; // GET_RXCNT
+//static UCHAR ct84[]={ 1, BYP, 0x54 }; // GET_BOXIDS
+//static UCHAR ct85[]={10, BYP, 0x55,0,0,0,0,0,0,0,0,0 }; // ENAB_MULT
+//static UCHAR ct86[]={ 2, BTH, 0x56,0 }; // RCV_ENABLE
+static UCHAR ct87[] = { 1, BYP, 0x57 }; // HW_TEST
+//static UCHAR ct88[]={ 3, BTH, 0x58,0,0 }; // RCV_THRESHOLD
+static UCHAR ct89[]={ 1, BYP, 0x59 }; // DSS_NOW
+//static UCHAR ct90[]={ 3, BYP, 0x5A,0,0 }; // Set SILO
+//static UCHAR ct91[]={ 2, BYP, 0x5B,0 }; // timed break
+
+// Some composite commands as well
+//static UCHAR cc01[]={ 2, BTH, 0x02,0x04 }; // DTR & RTS UP
+//static UCHAR cc02[]={ 2, BTH, 0x03,0x05 }; // DTR & RTS DN
+
+//********
+//* Code *
+//********
+
+//******************************************************************************
+// Function: i2cmdUnixFlags(iflag, cflag, lflag)
+// Parameters: Unix tty flags
+//
+// Returns: Pointer to command structure
+//
+// Description:
+//
+// This routine sets the parameters of command 47 and returns a pointer to the
+// appropriate structure.
+//******************************************************************************
+cmdSyntaxPtr
+i2cmdUnixFlags(unsigned short iflag,unsigned short cflag,unsigned short lflag)
+{
+ cmdSyntaxPtr pCM = (cmdSyntaxPtr) ct47;
+
+ pCM->cmd[1] = (unsigned char) iflag;
+ pCM->cmd[2] = (unsigned char) (iflag >> 8);
+ pCM->cmd[3] = (unsigned char) cflag;
+ pCM->cmd[4] = (unsigned char) (cflag >> 8);
+ pCM->cmd[5] = (unsigned char) lflag;
+ pCM->cmd[6] = (unsigned char) (lflag >> 8);
+ return pCM;
+}
+
+//******************************************************************************
+// Function: i2cmdBaudDef(which, rate)
+// Parameters: ?
+//
+// Returns: Pointer to command structure
+//
+// Description:
+//
+// This routine sets the parameters of commands 54 or 55 (according to the
+// argument which), and returns a pointer to the appropriate structure.
+//******************************************************************************
+cmdSyntaxPtr
+i2cmdBaudDef(int which, unsigned short rate)
+{
+ cmdSyntaxPtr pCM;
+
+ switch(which)
+ {
+ case 1:
+ pCM = (cmdSyntaxPtr) ct54;
+ break;
+ default:
+ case 2:
+ pCM = (cmdSyntaxPtr) ct55;
+ break;
+ }
+ pCM->cmd[1] = (unsigned char) rate;
+ pCM->cmd[2] = (unsigned char) (rate >> 8);
+ return pCM;
+}
+
diff --git a/drivers/char/ip2/i2cmd.h b/drivers/char/ip2/i2cmd.h
new file mode 100644
index 0000000..c41728a
--- /dev/null
+++ b/drivers/char/ip2/i2cmd.h
@@ -0,0 +1,643 @@
+/*******************************************************************************
+*
+* (c) 1999 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Definitions and support for In-line and Bypass commands.
+* Applicable only when the standard loadware is active.
+*
+*******************************************************************************/
+//------------------------------------------------------------------------------
+// Revision History:
+//
+// 10 October 1991 MAG First Draft
+// 7 November 1991 MAG Reflects some new commands
+// 20 February 1992 MAG CMD_HOTACK corrected: no argument.
+// 24 February 1992 MAG Support added for new commands for 1.4.x loadware.
+// 11 March 1992 MAG Additional commands.
+// 16 March 1992 MAG Additional commands.
+// 30 March 1992 MAG Additional command: CMD_DSS_NOW
+// 18 May 1992 MAG Changed CMD_OPOST
+//
+//------------------------------------------------------------------------------
+#ifndef I2CMD_H // To prevent multiple includes
+#define I2CMD_H 1
+
+#include "ip2types.h"
+
+// This module is designed to provide a uniform method of sending commands to
+// the board through command packets. The difficulty is, some commands take
+// parameters, others do not. Furthermore, it is often useful to send several
+// commands to the same channel as part of the same packet. (See also i2pack.h.)
+//
+// This module is designed so that the caller should not be responsible for
+// remembering the exact syntax of each command, or at least so that the
+// compiler could check things somewhat. I'll explain as we go...
+//
+// First, a structure which can embody the syntax of each type of command.
+//
+typedef struct _cmdSyntax
+{
+ UCHAR length; // Number of bytes in the command
+ UCHAR flags; // Information about the command (see below)
+
+ // The command and its parameters, which may be of arbitrary length. Don't
+ // worry yet how the parameters will be initialized; macros later take care
+ // of it. Also, don't worry about the arbitrary length issue; this structure
+ // is never used to allocate space (see i2cmd.c).
+ UCHAR cmd[2];
+} cmdSyntax, *cmdSyntaxPtr;
+
+// Bit assignments for flags
+
+#define INL 1 // Set if suitable for inline commands
+#define BYP 2 // Set if suitable for bypass commands
+#define BTH (INL|BYP) // suitable for either!
+#define END 4 // Set if this must be the last command in a block
+#define VIP 8 // Set if this command is special in some way and really
+ // should only be sent from the library-level and not
+ // directly from user-level
+#define VAR 0x10 // This command is of variable length!
+
+//-----------------------------------
+// External declarations for i2cmd.c
+//-----------------------------------
+// Routine to set up parameters for the "define hot-key sequence" command. Since
+// there is more than one parameter to assign, we must use a function rather
+// than a macro (used usually).
+//
+extern cmdSyntaxPtr i2cmdUnixFlags(USHORT iflag,USHORT cflag,USHORT lflag);
+extern cmdSyntaxPtr i2cmdBaudDef(int which, USHORT rate);
+
+// Declarations for the global arrays used to bear the commands and their
+// arguments.
+//
+// Note: Since these are globals and the arguments might change, it is important
+// that the library routine COPY these into buffers from whence they would be
+// sent, rather than merely storing the pointers. In multi-threaded
+// environments, important that the copy should obtain before any context switch
+// is allowed. Also, for parameterized commands, DO NOT ISSUE THE SAME COMMAND
+// MORE THAN ONCE WITH THE SAME PARAMETERS in the same call.
+//
+static UCHAR ct02[];
+static UCHAR ct03[];
+static UCHAR ct04[];
+static UCHAR ct05[];
+static UCHAR ct06[];
+static UCHAR ct07[];
+static UCHAR ct08[];
+static UCHAR ct09[];
+static UCHAR ct10[];
+static UCHAR ct11[];
+static UCHAR ct12[];
+static UCHAR ct13[];
+static UCHAR ct14[];
+static UCHAR ct15[];
+static UCHAR ct16[];
+static UCHAR ct17[];
+static UCHAR ct18[];
+static UCHAR ct19[];
+static UCHAR ct20[];
+static UCHAR ct21[];
+static UCHAR ct22[];
+static UCHAR ct23[];
+static UCHAR ct24[];
+static UCHAR ct25[];
+static UCHAR ct26[];
+static UCHAR ct27[];
+static UCHAR ct28[];
+static UCHAR ct29[];
+static UCHAR ct30[];
+static UCHAR ct31[];
+static UCHAR ct32[];
+static UCHAR ct33[];
+static UCHAR ct34[];
+static UCHAR ct35[];
+static UCHAR ct36[];
+static UCHAR ct36a[];
+static UCHAR ct41[];
+static UCHAR ct42[];
+static UCHAR ct43[];
+static UCHAR ct44[];
+static UCHAR ct45[];
+static UCHAR ct46[];
+static UCHAR ct48[];
+static UCHAR ct49[];
+static UCHAR ct50[];
+static UCHAR ct51[];
+static UCHAR ct52[];
+static UCHAR ct56[];
+static UCHAR ct57[];
+static UCHAR ct58[];
+static UCHAR ct59[];
+static UCHAR ct60[];
+static UCHAR ct61[];
+static UCHAR ct62[];
+static UCHAR ct63[];
+static UCHAR ct64[];
+static UCHAR ct65[];
+static UCHAR ct66[];
+static UCHAR ct67[];
+static UCHAR ct68[];
+static UCHAR ct69[];
+static UCHAR ct70[];
+static UCHAR ct71[];
+static UCHAR ct72[];
+static UCHAR ct73[];
+static UCHAR ct74[];
+static UCHAR ct75[];
+static UCHAR ct76[];
+static UCHAR ct77[];
+static UCHAR ct78[];
+static UCHAR ct79[];
+static UCHAR ct80[];
+static UCHAR ct81[];
+static UCHAR ct82[];
+static UCHAR ct83[];
+static UCHAR ct84[];
+static UCHAR ct85[];
+static UCHAR ct86[];
+static UCHAR ct87[];
+static UCHAR ct88[];
+static UCHAR ct89[];
+static UCHAR ct90[];
+static UCHAR ct91[];
+static UCHAR cc01[];
+static UCHAR cc02[];
+
+// Now, refer to i2cmd.c, and see the character arrays defined there. They are
+// cast here to cmdSyntaxPtr.
+//
+// There are library functions for issuing bypass or inline commands. These
+// functions take one or more arguments of the type cmdSyntaxPtr. The routine
+// then can figure out how long each command is supposed to be and easily add it
+// to the list.
+//
+// For ease of use, we define manifests which return pointers to appropriate
+// cmdSyntaxPtr things. But some commands also take arguments. If a single
+// argument is used, we define a macro which performs the single assignment and
+// (through the expedient of a comma expression) references the appropriate
+// pointer. For commands requiring several arguments, we actually define a
+// function to perform the assignments.
+
+#define CMD_DTRUP (cmdSyntaxPtr)(ct02) // Raise DTR
+#define CMD_DTRDN (cmdSyntaxPtr)(ct03) // Lower DTR
+#define CMD_RTSUP (cmdSyntaxPtr)(ct04) // Raise RTS
+#define CMD_RTSDN (cmdSyntaxPtr)(ct05) // Lower RTS
+#define CMD_STARTFL (cmdSyntaxPtr)(ct06) // Start Flushing Data
+
+#define CMD_DTRRTS_UP (cmdSyntaxPtr)(cc01) // Raise DTR and RTS
+#define CMD_DTRRTS_DN (cmdSyntaxPtr)(cc02) // Lower DTR and RTS
+
+// Set Baud Rate for transmit and receive
+#define CMD_SETBAUD(arg) \
+ (((cmdSyntaxPtr)(ct07))->cmd[1] = (arg),(cmdSyntaxPtr)(ct07))
+
+#define CBR_50 1
+#define CBR_75 2
+#define CBR_110 3
+#define CBR_134 4
+#define CBR_150 5
+#define CBR_200 6
+#define CBR_300 7
+#define CBR_600 8
+#define CBR_1200 9
+#define CBR_1800 10
+#define CBR_2400 11
+#define CBR_4800 12
+#define CBR_9600 13
+#define CBR_19200 14
+#define CBR_38400 15
+#define CBR_2000 16
+#define CBR_3600 17
+#define CBR_7200 18
+#define CBR_56000 19
+#define CBR_57600 20
+#define CBR_64000 21
+#define CBR_76800 22
+#define CBR_115200 23
+#define CBR_C1 24 // Custom baud rate 1
+#define CBR_C2 25 // Custom baud rate 2
+#define CBR_153600 26
+#define CBR_230400 27
+#define CBR_307200 28
+#define CBR_460800 29
+#define CBR_921600 30
+
+// Set Character size
+//
+#define CMD_SETBITS(arg) \
+ (((cmdSyntaxPtr)(ct08))->cmd[1] = (arg),(cmdSyntaxPtr)(ct08))
+
+#define CSZ_5 0
+#define CSZ_6 1
+#define CSZ_7 2
+#define CSZ_8 3
+
+// Set number of stop bits
+//
+#define CMD_SETSTOP(arg) \
+ (((cmdSyntaxPtr)(ct09))->cmd[1] = (arg),(cmdSyntaxPtr)(ct09))
+
+#define CST_1 0
+#define CST_15 1 // 1.5 stop bits
+#define CST_2 2
+
+// Set parity option
+//
+#define CMD_SETPAR(arg) \
+ (((cmdSyntaxPtr)(ct10))->cmd[1] = (arg),(cmdSyntaxPtr)(ct10))
+
+#define CSP_NP 0 // no parity
+#define CSP_OD 1 // odd parity
+#define CSP_EV 2 // Even parity
+#define CSP_SP 3 // Space parity
+#define CSP_MK 4 // Mark parity
+
+// Define xon char for transmitter flow control
+//
+#define CMD_DEF_IXON(arg) \
+ (((cmdSyntaxPtr)(ct11))->cmd[1] = (arg),(cmdSyntaxPtr)(ct11))
+
+// Define xoff char for transmitter flow control
+//
+#define CMD_DEF_IXOFF(arg) \
+ (((cmdSyntaxPtr)(ct12))->cmd[1] = (arg),(cmdSyntaxPtr)(ct12))
+
+#define CMD_STOPFL (cmdSyntaxPtr)(ct13) // Stop Flushing data
+
+// Acknowledge receipt of hotkey signal
+//
+#define CMD_HOTACK (cmdSyntaxPtr)(ct14)
+
+// Define irq level to use. Should actually be sent by library-level code, not
+// directly from user...
+//
+#define CMDVALUE_IRQ 15 // For library use at initialization. Until this command
+ // is sent, board processing doesn't really start.
+#define CMD_SET_IRQ(arg) \
+ (((cmdSyntaxPtr)(ct15))->cmd[1] = (arg),(cmdSyntaxPtr)(ct15))
+
+#define CIR_POLL 0 // No IRQ - Poll
+#define CIR_3 3 // IRQ 3
+#define CIR_4 4 // IRQ 4
+#define CIR_5 5 // IRQ 5
+#define CIR_7 7 // IRQ 7
+#define CIR_10 10 // IRQ 10
+#define CIR_11 11 // IRQ 11
+#define CIR_12 12 // IRQ 12
+#define CIR_15 15 // IRQ 15
+
+// Select transmit flow xon/xoff options
+//
+#define CMD_IXON_OPT(arg) \
+ (((cmdSyntaxPtr)(ct16))->cmd[1] = (arg),(cmdSyntaxPtr)(ct16))
+
+#define CIX_NONE 0 // Incoming Xon/Xoff characters not special
+#define CIX_XON 1 // Xoff disable, Xon enable
+#define CIX_XANY 2 // Xoff disable, any key enable
+
+// Select receive flow xon/xoff options
+//
+#define CMD_OXON_OPT(arg) \
+ (((cmdSyntaxPtr)(ct17))->cmd[1] = (arg),(cmdSyntaxPtr)(ct17))
+
+#define COX_NONE 0 // Don't send Xon/Xoff
+#define COX_XON 1 // Send xon/xoff to start/stop incoming data
+
+
+#define CMD_CTS_REP (cmdSyntaxPtr)(ct18) // Enable CTS reporting
+#define CMD_CTS_NREP (cmdSyntaxPtr)(ct19) // Disable CTS reporting
+
+#define CMD_DCD_REP (cmdSyntaxPtr)(ct20) // Enable DCD reporting
+#define CMD_DCD_NREP (cmdSyntaxPtr)(ct21) // Disable DCD reporting
+
+#define CMD_DSR_REP (cmdSyntaxPtr)(ct22) // Enable DSR reporting
+#define CMD_DSR_NREP (cmdSyntaxPtr)(ct23) // Disable DSR reporting
+
+#define CMD_RI_REP (cmdSyntaxPtr)(ct24) // Enable RI reporting
+#define CMD_RI_NREP (cmdSyntaxPtr)(ct25) // Disable RI reporting
+
+// Enable break reporting and select style
+//
+#define CMD_BRK_REP(arg) \
+ (((cmdSyntaxPtr)(ct26))->cmd[1] = (arg),(cmdSyntaxPtr)(ct26))
+
+#define CBK_STAT 0x00 // Report breaks as a status (exception,irq)
+#define CBK_NULL 0x01 // Report breaks as a good null
+#define CBK_STAT_SEQ 0x02 // Report breaks as a status AND as in-band character
+ // sequence FFh, 01h, 10h
+#define CBK_SEQ 0x03 // Report breaks as the in-band
+ //sequence FFh, 01h, 10h ONLY.
+#define CBK_FLSH 0x04 // if this bit set also flush input data
+#define CBK_POSIX 0x08 // if this bit set report as FF,0,0 sequence
+#define CBK_SINGLE 0x10 // if this bit set with CBK_SEQ or CBK_STAT_SEQ
+ //then reports single null instead of triple
+
+#define CMD_BRK_NREP (cmdSyntaxPtr)(ct27) // Disable break reporting
+
+// Specify maximum block size for received data
+//
+#define CMD_MAX_BLOCK(arg) \
+ (((cmdSyntaxPtr)(ct28))->cmd[1] = (arg),(cmdSyntaxPtr)(ct28))
+
+// -- COMMAND 29 is reserved --
+
+#define CMD_CTSFL_ENAB (cmdSyntaxPtr)(ct30) // Enable CTS flow control
+#define CMD_CTSFL_DSAB (cmdSyntaxPtr)(ct31) // Disable CTS flow control
+#define CMD_RTSFL_ENAB (cmdSyntaxPtr)(ct32) // Enable RTS flow control
+#define CMD_RTSFL_DSAB (cmdSyntaxPtr)(ct33) // Disable RTS flow control
+
+// Specify istrip option
+//
+#define CMD_ISTRIP_OPT(arg) \
+ (((cmdSyntaxPtr)(ct34))->cmd[1] = (arg),(cmdSyntaxPtr)(ct34))
+
+#define CIS_NOSTRIP 0 // Strip characters to character size
+#define CIS_STRIP 1 // Strip any 8-bit characters to 7 bits
+
+// Send a break of arg milliseconds
+//
+#define CMD_SEND_BRK(arg) \
+ (((cmdSyntaxPtr)(ct35))->cmd[1] = (arg),(cmdSyntaxPtr)(ct35))
+
+// Set error reporting mode
+//
+#define CMD_SET_ERROR(arg) \
+ (((cmdSyntaxPtr)(ct36))->cmd[1] = (arg),(cmdSyntaxPtr)(ct36))
+
+#define CSE_ESTAT 0 // Report error in a status packet
+#define CSE_NOREP 1 // Treat character as though it were good
+#define CSE_DROP 2 // Discard the character
+#define CSE_NULL 3 // Replace with a null
+#define CSE_MARK 4 // Replace with a 3-character sequence (as Unix)
+
+#define CMD_SET_REPLACEMENT(arg,ch) \
+ (((cmdSyntaxPtr)(ct36a))->cmd[1] = (arg), \
+ (((cmdSyntaxPtr)(ct36a))->cmd[2] = (ch), \
+ (cmdSyntaxPtr)(ct36a))
+
+#define CSE_REPLACE 0x8 // Replace the errored character with the
+ // replacement character defined here
+
+#define CSE_STAT_REPLACE 0x18 // Replace the errored character with the
+ // replacement character defined here AND
+ // report the error as a status packet (as in
+ // CSE_ESTAT).
+
+
+// COMMAND 37, to send flow control packets, is handled only by low-level
+// library code in response to data movement and shouldn't ever be sent by the
+// user code. See i2pack.h and the body of i2lib.c for details.
+
+// Enable on-board post-processing, using options given in oflag argument.
+// Formerly, this command was automatically preceded by a CMD_OPOST_OFF command
+// because the loadware does not permit sending back-to-back CMD_OPOST_ON
+// commands without an intervening CMD_OPOST_OFF. BUT, WE LEARN 18 MAY 92, that
+// CMD_OPOST_ON and CMD_OPOST_OFF must each be at the end of a packet (or in a
+// solo packet). This means the caller must specify separately CMD_OPOST_OFF,
+// CMD_OPOST_ON(parm) when he calls i2QueueCommands(). That function will ensure
+// each gets a separate packet. Extra CMD_OPOST_OFF's are always ok.
+//
+#define CMD_OPOST_ON(oflag) \
+ (*(USHORT *)(((cmdSyntaxPtr)(ct39))->cmd[1]) = (oflag), \
+ (cmdSyntaxPtr)(ct39))
+
+#define CMD_OPOST_OFF (cmdSyntaxPtr)(ct40) // Disable on-board post-proc
+
+#define CMD_RESUME (cmdSyntaxPtr)(ct41) // Resume: behave as though an XON
+ // were received;
+
+// Set Transmit baud rate (see command 7 for arguments)
+//
+#define CMD_SETBAUD_TX(arg) \
+ (((cmdSyntaxPtr)(ct42))->cmd[1] = (arg),(cmdSyntaxPtr)(ct42))
+
+// Set Receive baud rate (see command 7 for arguments)
+//
+#define CMD_SETBAUD_RX(arg) \
+ (((cmdSyntaxPtr)(ct43))->cmd[1] = (arg),(cmdSyntaxPtr)(ct43))
+
+// Request interrupt from board each arg milliseconds. Interrupt will specify
+// "received data", even though there may be no data present. If arg == 0,
+// disables any such interrupts.
+//
+#define CMD_PING_REQ(arg) \
+ (((cmdSyntaxPtr)(ct44))->cmd[1] = (arg),(cmdSyntaxPtr)(ct44))
+
+#define CMD_HOT_ENAB (cmdSyntaxPtr)(ct45) // Enable Hot-key checking
+#define CMD_HOT_DSAB (cmdSyntaxPtr)(ct46) // Disable Hot-key checking
+
+// COMMAND 47: Send Protocol info via Unix flags:
+// iflag = Unix tty t_iflag
+// cflag = Unix tty t_cflag
+// lflag = Unix tty t_lflag
+// See System V Unix/Xenix documentation for the meanings of the bit fields
+// within these flags
+//
+#define CMD_UNIX_FLAGS(iflag,cflag,lflag) i2cmdUnixFlags(iflag,cflag,lflag)
+
+#define CMD_DSRFL_ENAB (cmdSyntaxPtr)(ct48) // Enable DSR receiver ctrl
+#define CMD_DSRFL_DSAB (cmdSyntaxPtr)(ct49) // Disable DSR receiver ctrl
+#define CMD_DTRFL_ENAB (cmdSyntaxPtr)(ct50) // Enable DTR flow control
+#define CMD_DTRFL_DSAB (cmdSyntaxPtr)(ct51) // Disable DTR flow control
+#define CMD_BAUD_RESET (cmdSyntaxPtr)(ct52) // Reset baudrate table
+
+// COMMAND 54: Define custom rate #1
+// rate = (short) 1/10 of the desired baud rate
+//
+#define CMD_BAUD_DEF1(rate) i2cmdBaudDef(1,rate)
+
+// COMMAND 55: Define custom rate #2
+// rate = (short) 1/10 of the desired baud rate
+//
+#define CMD_BAUD_DEF2(rate) i2cmdBaudDef(2,rate)
+
+// Pause arg hundredths of seconds. (Note, this is NOT milliseconds.)
+//
+#define CMD_PAUSE(arg) \
+ (((cmdSyntaxPtr)(ct56))->cmd[1] = (arg),(cmdSyntaxPtr)(ct56))
+
+#define CMD_SUSPEND (cmdSyntaxPtr)(ct57) // Suspend output
+#define CMD_UNSUSPEND (cmdSyntaxPtr)(ct58) // Un-Suspend output
+
+// Set parity-checking options
+//
+#define CMD_PARCHK(arg) \
+ (((cmdSyntaxPtr)(ct59))->cmd[1] = (arg),(cmdSyntaxPtr)(ct59))
+
+#define CPK_ENAB 0 // Enable parity checking on input
+#define CPK_DSAB 1 // Disable parity checking on input
+
+#define CMD_BMARK_REQ (cmdSyntaxPtr)(ct60) // Bookmark request
+
+
+// Enable/Disable internal loopback mode
+//
+#define CMD_INLOOP(arg) \
+ (((cmdSyntaxPtr)(ct61))->cmd[1] = (arg),(cmdSyntaxPtr)(ct61))
+
+#define CIN_DISABLE 0 // Normal operation (default)
+#define CIN_ENABLE 1 // Internal (local) loopback
+#define CIN_REMOTE 2 // Remote loopback
+
+// Specify timeout for hotkeys: Delay will be (arg x 10) milliseconds, arg == 0
+// --> no timeout: wait forever.
+//
+#define CMD_HOT_TIME(arg) \
+ (((cmdSyntaxPtr)(ct62))->cmd[1] = (arg),(cmdSyntaxPtr)(ct62))
+
+
+// Define (outgoing) xon for receive flow control
+//
+#define CMD_DEF_OXON(arg) \
+ (((cmdSyntaxPtr)(ct63))->cmd[1] = (arg),(cmdSyntaxPtr)(ct63))
+
+// Define (outgoing) xoff for receiver flow control
+//
+#define CMD_DEF_OXOFF(arg) \
+ (((cmdSyntaxPtr)(ct64))->cmd[1] = (arg),(cmdSyntaxPtr)(ct64))
+
+// Enable/Disable RTS on transmit (1/2 duplex-style)
+//
+#define CMD_RTS_XMIT(arg) \
+ (((cmdSyntaxPtr)(ct65))->cmd[1] = (arg),(cmdSyntaxPtr)(ct65))
+
+#define CHD_DISABLE 0
+#define CHD_ENABLE 1
+
+// Set high-water-mark level (debugging use only)
+//
+#define CMD_SETHIGHWAT(arg) \
+ (((cmdSyntaxPtr)(ct66))->cmd[1] = (arg),(cmdSyntaxPtr)(ct66))
+
+// Start flushing tagged data (tag = 0-14)
+//
+#define CMD_START_SELFL(tag) \
+ (((cmdSyntaxPtr)(ct67))->cmd[1] = (tag),(cmdSyntaxPtr)(ct67))
+
+// End flushing tagged data (tag = 0-14)
+//
+#define CMD_END_SELFL(tag) \
+ (((cmdSyntaxPtr)(ct68))->cmd[1] = (tag),(cmdSyntaxPtr)(ct68))
+
+#define CMD_HWFLOW_OFF (cmdSyntaxPtr)(ct69) // Disable HW TX flow control
+#define CMD_ODSRFL_ENAB (cmdSyntaxPtr)(ct70) // Enable DSR output f/c
+#define CMD_ODSRFL_DSAB (cmdSyntaxPtr)(ct71) // Disable DSR output f/c
+#define CMD_ODCDFL_ENAB (cmdSyntaxPtr)(ct72) // Enable DCD output f/c
+#define CMD_ODCDFL_DSAB (cmdSyntaxPtr)(ct73) // Disable DCD output f/c
+
+// Set transmit interrupt load level. Count should be an even value 2-12
+//
+#define CMD_LOADLEVEL(count) \
+ (((cmdSyntaxPtr)(ct74))->cmd[1] = (count),(cmdSyntaxPtr)(ct74))
+
+// If reporting DSS changes, map to character sequence FFh, 2, MSR
+//
+#define CMD_STATDATA(arg) \
+ (((cmdSyntaxPtr)(ct75))->cmd[1] = (arg),(cmdSyntaxPtr)(ct75))
+
+#define CSTD_DISABLE// Report DSS changes as status packets only (default)
+#define CSTD_ENABLE // Report DSS changes as in-band data sequence as well as
+ // by status packet.
+
+#define CMD_BREAK_ON (cmdSyntaxPtr)(ct76)// Set break and stop xmit
+#define CMD_BREAK_OFF (cmdSyntaxPtr)(ct77)// End break and restart xmit
+#define CMD_GETFC (cmdSyntaxPtr)(ct78)// Request for flow control packet
+ // from board.
+
+// Transmit this character immediately
+//
+#define CMD_XMIT_NOW(ch) \
+ (((cmdSyntaxPtr)(ct79))->cmd[1] = (ch),(cmdSyntaxPtr)(ct79))
+
+// Set baud rate via "divisor latch"
+//
+#define CMD_DIVISOR_LATCH(which,value) \
+ (((cmdSyntaxPtr)(ct80))->cmd[1] = (which), \
+ *(USHORT *)(((cmdSyntaxPtr)(ct80))->cmd[2]) = (value), \
+ (cmdSyntaxPtr)(ct80))
+
+#define CDL_RX 1 // Set receiver rate
+#define CDL_TX 2 // Set transmit rate
+ // (CDL_TX | CDL_RX) Set both rates
+
+// Request for special diagnostic status pkt from the board.
+//
+#define CMD_GET_STATUS (cmdSyntaxPtr)(ct81)
+
+// Request time-stamped transmit character count packet.
+//
+#define CMD_GET_TXCNT (cmdSyntaxPtr)(ct82)
+
+// Request time-stamped receive character count packet.
+//
+#define CMD_GET_RXCNT (cmdSyntaxPtr)(ct83)
+
+// Request for box/board I.D. packet.
+#define CMD_GET_BOXIDS (cmdSyntaxPtr)(ct84)
+
+// Enable or disable multiple channels according to bit-mapped ushorts box 1-4
+//
+#define CMD_ENAB_MULT(enable, box1, box2, box3, box4) \
+ (((cmdSytaxPtr)(ct85))->cmd[1] = (enable), \
+ *(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[2]) = (box1), \
+ *(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[4]) = (box2), \
+ *(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[6]) = (box3), \
+ *(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[8]) = (box4), \
+ (cmdSyntaxPtr)(ct85))
+
+#define CEM_DISABLE 0
+#define CEM_ENABLE 1
+
+// Enable or disable receiver or receiver interrupts (default both enabled)
+//
+#define CMD_RCV_ENABLE(ch) \
+ (((cmdSyntaxPtr)(ct86))->cmd[1] = (ch),(cmdSyntaxPtr)(ct86))
+
+#define CRE_OFF 0 // Disable the receiver
+#define CRE_ON 1 // Enable the receiver
+#define CRE_INTOFF 2 // Disable receiver interrupts (to loadware)
+#define CRE_INTON 3 // Enable receiver interrupts (to loadware)
+
+// Starts up a hardware test process, which runs transparently, and sends a
+// STAT_HWFAIL packet in case a hardware failure is detected.
+//
+#define CMD_HW_TEST (cmdSyntaxPtr)(ct87)
+
+// Change receiver threshold and timeout value:
+// Defaults: timeout = 20mS
+// threshold count = 8 when DTRflow not in use,
+// threshold count = 5 when DTRflow in use.
+//
+#define CMD_RCV_THRESHOLD(count,ms) \
+ (((cmdSyntaxPtr)(ct88))->cmd[1] = (count), \
+ ((cmdSyntaxPtr)(ct88))->cmd[2] = (ms), \
+ (cmdSyntaxPtr)(ct88))
+
+// Makes the loadware report DSS signals for this channel immediately.
+//
+#define CMD_DSS_NOW (cmdSyntaxPtr)(ct89)
+
+// Set the receive silo parameters
+// timeout is ms idle wait until delivery (~VTIME)
+// threshold is max characters cause interrupt (~VMIN)
+//
+#define CMD_SET_SILO(timeout,threshold) \
+ (((cmdSyntaxPtr)(ct90))->cmd[1] = (timeout), \
+ ((cmdSyntaxPtr)(ct90))->cmd[2] = (threshold), \
+ (cmdSyntaxPtr)(ct90))
+
+// Set timed break in decisecond (1/10s)
+//
+#define CMD_LBREAK(ds) \
+ (((cmdSyntaxPtr)(ct91))->cmd[1] = (ds),(cmdSyntaxPtr)(ct66))
+
+
+
+#endif // I2CMD_H
diff --git a/drivers/char/ip2/i2ellis.c b/drivers/char/ip2/i2ellis.c
new file mode 100644
index 0000000..f834d05
--- /dev/null
+++ b/drivers/char/ip2/i2ellis.c
@@ -0,0 +1,1487 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Low-level interface code for the device driver
+* (This is included source code, not a separate compilation
+* module.)
+*
+*******************************************************************************/
+//---------------------------------------------
+// Function declarations private to this module
+//---------------------------------------------
+// Functions called only indirectly through i2eBordStr entries.
+
+static int iiWriteBuf16(i2eBordStrPtr, unsigned char *, int);
+static int iiWriteBuf8(i2eBordStrPtr, unsigned char *, int);
+static int iiReadBuf16(i2eBordStrPtr, unsigned char *, int);
+static int iiReadBuf8(i2eBordStrPtr, unsigned char *, int);
+
+static unsigned short iiReadWord16(i2eBordStrPtr);
+static unsigned short iiReadWord8(i2eBordStrPtr);
+static void iiWriteWord16(i2eBordStrPtr, unsigned short);
+static void iiWriteWord8(i2eBordStrPtr, unsigned short);
+
+static int iiWaitForTxEmptyII(i2eBordStrPtr, int);
+static int iiWaitForTxEmptyIIEX(i2eBordStrPtr, int);
+static int iiTxMailEmptyII(i2eBordStrPtr);
+static int iiTxMailEmptyIIEX(i2eBordStrPtr);
+static int iiTrySendMailII(i2eBordStrPtr, unsigned char);
+static int iiTrySendMailIIEX(i2eBordStrPtr, unsigned char);
+
+static unsigned short iiGetMailII(i2eBordStrPtr);
+static unsigned short iiGetMailIIEX(i2eBordStrPtr);
+
+static void iiEnableMailIrqII(i2eBordStrPtr);
+static void iiEnableMailIrqIIEX(i2eBordStrPtr);
+static void iiWriteMaskII(i2eBordStrPtr, unsigned char);
+static void iiWriteMaskIIEX(i2eBordStrPtr, unsigned char);
+
+static void ii2DelayTimer(unsigned int);
+static void ii2DelayWakeup(unsigned long id);
+static void ii2Nop(void);
+
+//***************
+//* Static Data *
+//***************
+
+static int ii2Safe; // Safe I/O address for delay routine
+
+static int iiDelayed; // Set when the iiResetDelay function is
+ // called. Cleared when ANY board is reset.
+static struct timer_list * pDelayTimer; // Used by iiDelayTimer
+static wait_queue_head_t pDelayWait; // Used by iiDelayTimer
+static rwlock_t Dl_spinlock;
+
+//********
+//* Code *
+//********
+
+//=======================================================
+// Initialization Routines
+//
+// iiSetAddress
+// iiReset
+// iiResetDelay
+// iiInitialize
+//=======================================================
+
+//******************************************************************************
+// Function: iiEllisInit()
+// Parameters: None
+//
+// Returns: Nothing
+//
+// Description:
+//
+// This routine performs any required initialization of the iiEllis subsystem.
+//
+//******************************************************************************
+static void
+iiEllisInit(void)
+{
+ pDelayTimer = kmalloc ( sizeof (struct timer_list), GFP_KERNEL );
+ init_timer(pDelayTimer);
+ init_waitqueue_head(&pDelayWait);
+ LOCK_INIT(&Dl_spinlock);
+}
+
+//******************************************************************************
+// Function: iiEllisCleanup()
+// Parameters: None
+//
+// Returns: Nothing
+//
+// Description:
+//
+// This routine performs any required cleanup of the iiEllis subsystem.
+//
+//******************************************************************************
+static void
+iiEllisCleanup(void)
+{
+ if ( pDelayTimer != NULL ) {
+ kfree ( pDelayTimer );
+ }
+}
+
+//******************************************************************************
+// Function: iiSetAddress(pB, address, delay)
+// Parameters: pB - pointer to the board structure
+// address - the purported I/O address of the board
+// delay - pointer to the 1-ms delay function to use
+// in this and any future operations to this board
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// This routine (roughly) checks for address validity, sets the i2eValid OK and
+// sets the state to II_STATE_COLD which means that we haven't even sent a reset
+// yet.
+//
+//******************************************************************************
+static int
+iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay )
+{
+ // Should any failure occur before init is finished...
+ pB->i2eValid = I2E_INCOMPLETE;
+
+ // Cannot check upper limit except extremely: Might be microchannel
+ // Address must be on an 8-byte boundary
+
+ if ((unsigned int)address <= 0x100
+ || (unsigned int)address >= 0xfff8
+ || (address & 0x7)
+ )
+ {
+ COMPLETE(pB,I2EE_BADADDR);
+ }
+
+ // Initialize accelerators
+ pB->i2eBase = address;
+ pB->i2eData = address + FIFO_DATA;
+ pB->i2eStatus = address + FIFO_STATUS;
+ pB->i2ePointer = address + FIFO_PTR;
+ pB->i2eXMail = address + FIFO_MAIL;
+ pB->i2eXMask = address + FIFO_MASK;
+
+ // Initialize i/o address for ii2DelayIO
+ ii2Safe = address + FIFO_NOP;
+
+ // Initialize the delay routine
+ pB->i2eDelay = ((delay != (delayFunc_t)NULL) ? delay : (delayFunc_t)ii2Nop);
+
+ pB->i2eValid = I2E_MAGIC;
+ pB->i2eState = II_STATE_COLD;
+
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiReset(pB)
+// Parameters: pB - pointer to the board structure
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Attempts to reset the board (see also i2hw.h). Normally, we would use this to
+// reset a board immediately after iiSetAddress(), but it is valid to reset a
+// board from any state, say, in order to change or re-load loadware. (Under
+// such circumstances, no reason to re-run iiSetAddress(), which is why it is a
+// separate routine and not included in this routine.
+//
+//******************************************************************************
+static int
+iiReset(i2eBordStrPtr pB)
+{
+ // Magic number should be set, else even the address is suspect
+ if (pB->i2eValid != I2E_MAGIC)
+ {
+ COMPLETE(pB, I2EE_BADMAGIC);
+ }
+
+ OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do
+ iiDelay(pB, 50); // Pause between resets
+ OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset
+
+ // We must wait before even attempting to read anything from the FIFO: the
+ // board's P.O.S.T may actually attempt to read and write its end of the
+ // FIFO in order to check flags, loop back (where supported), etc. On
+ // completion of this testing it would reset the FIFO, and on completion
+ // of all // P.O.S.T., write the message. We must not mistake data which
+ // might have been sent for testing as part of the reset message. To
+ // better utilize time, say, when resetting several boards, we allow the
+ // delay to be performed externally; in this way the caller can reset
+ // several boards, delay a single time, then call the initialization
+ // routine for all.
+
+ pB->i2eState = II_STATE_RESET;
+
+ iiDelayed = 0; // i.e., the delay routine hasn't been called since the most
+ // recent reset.
+
+ // Ensure anything which would have been of use to standard loadware is
+ // blanked out, since board has now forgotten everything!.
+
+ pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet
+ pB->i2eWaitingForEmptyFifo = 0;
+ pB->i2eOutMailWaiting = 0;
+ pB->i2eChannelPtr = NULL;
+ pB->i2eChannelCnt = 0;
+
+ pB->i2eLeadoffWord[0] = 0;
+ pB->i2eFifoInInts = 0;
+ pB->i2eFifoOutInts = 0;
+ pB->i2eFatalTrap = NULL;
+ pB->i2eFatal = 0;
+
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiResetDelay(pB)
+// Parameters: pB - pointer to the board structure
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Using the delay defined in board structure, waits two seconds (for board to
+// reset).
+//
+//******************************************************************************
+static int
+iiResetDelay(i2eBordStrPtr pB)
+{
+ if (pB->i2eValid != I2E_MAGIC) {
+ COMPLETE(pB, I2EE_BADMAGIC);
+ }
+ if (pB->i2eState != II_STATE_RESET) {
+ COMPLETE(pB, I2EE_BADSTATE);
+ }
+ iiDelay(pB,2000); /* Now we wait for two seconds. */
+ iiDelayed = 1; /* Delay has been called: ok to initialize */
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiInitialize(pB)
+// Parameters: pB - pointer to the board structure
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Attempts to read the Power-on reset message. Initializes any remaining fields
+// in the pB structure.
+//
+// This should be called as the third step of a process beginning with
+// iiReset(), then iiResetDelay(). This routine checks to see that the structure
+// is "valid" and in the reset state, also confirms that the delay routine has
+// been called since the latest reset (to any board! overly strong!).
+//
+//******************************************************************************
+static int
+iiInitialize(i2eBordStrPtr pB)
+{
+ int itemp;
+ unsigned char c;
+ unsigned short utemp;
+ unsigned int ilimit;
+
+ if (pB->i2eValid != I2E_MAGIC)
+ {
+ COMPLETE(pB, I2EE_BADMAGIC);
+ }
+
+ if (pB->i2eState != II_STATE_RESET || !iiDelayed)
+ {
+ COMPLETE(pB, I2EE_BADSTATE);
+ }
+
+ // In case there is a failure short of our completely reading the power-up
+ // message.
+ pB->i2eValid = I2E_INCOMPLETE;
+
+
+ // Now attempt to read the message.
+
+ for (itemp = 0; itemp < sizeof(porStr); itemp++)
+ {
+ // We expect the entire message is ready.
+ if (HAS_NO_INPUT(pB))
+ {
+ pB->i2ePomSize = itemp;
+ COMPLETE(pB, I2EE_PORM_SHORT);
+ }
+
+ pB->i2ePom.c[itemp] = c = BYTE_FROM(pB);
+
+ // We check the magic numbers as soon as they are supposed to be read
+ // (rather than after) to minimize effect of reading something we
+ // already suspect can't be "us".
+ if ( (itemp == POR_1_INDEX && c != POR_MAGIC_1) ||
+ (itemp == POR_2_INDEX && c != POR_MAGIC_2))
+ {
+ pB->i2ePomSize = itemp+1;
+ COMPLETE(pB, I2EE_BADMAGIC);
+ }
+ }
+
+ pB->i2ePomSize = itemp;
+
+ // Ensure that this was all the data...
+ if (HAS_INPUT(pB))
+ COMPLETE(pB, I2EE_PORM_LONG);
+
+ // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper:
+ // Implying we will not be able to download any code either: That's ok: the
+ // condition is pretty explicit.
+ if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER)
+ {
+ COMPLETE(pB, I2EE_POSTERR);
+ }
+
+ // Determine anything which must be done differently depending on the family
+ // of boards!
+ switch (pB->i2ePom.e.porID & POR_ID_FAMILY)
+ {
+ case POR_ID_FII: // IntelliPort-II
+
+ pB->i2eFifoStyle = FIFO_II;
+ pB->i2eFifoSize = 512; // 512 bytes, always
+ pB->i2eDataWidth16 = NO;
+
+ pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit
+ // slot, we do allow it to be done (documentation!)
+
+ pB->i2eGoodMap[1] =
+ pB->i2eGoodMap[2] =
+ pB->i2eGoodMap[3] =
+ pB->i2eChannelMap[1] =
+ pB->i2eChannelMap[2] =
+ pB->i2eChannelMap[3] = 0;
+
+ switch (pB->i2ePom.e.porID & POR_ID_SIZE)
+ {
+ case POR_ID_II_4:
+ pB->i2eGoodMap[0] =
+ pB->i2eChannelMap[0] = 0x0f; // four-port
+
+ // Since porPorts1 is based on the Hardware ID register, the numbers
+ // should always be consistent for IntelliPort-II. Ditto below...
+ if (pB->i2ePom.e.porPorts1 != 4)
+ {
+ COMPLETE(pB, I2EE_INCONSIST);
+ }
+ break;
+
+ case POR_ID_II_8:
+ case POR_ID_II_8R:
+ pB->i2eGoodMap[0] =
+ pB->i2eChannelMap[0] = 0xff; // Eight port
+ if (pB->i2ePom.e.porPorts1 != 8)
+ {
+ COMPLETE(pB, I2EE_INCONSIST);
+ }
+ break;
+
+ case POR_ID_II_6:
+ pB->i2eGoodMap[0] =
+ pB->i2eChannelMap[0] = 0x3f; // Six Port
+ if (pB->i2ePom.e.porPorts1 != 6)
+ {
+ COMPLETE(pB, I2EE_INCONSIST);
+ }
+ break;
+ }
+
+ // Fix up the "good channel list based on any errors reported.
+ if (pB->i2ePom.e.porDiag1 & POR_BAD_UART1)
+ {
+ pB->i2eGoodMap[0] &= ~0x0f;
+ }
+
+ if (pB->i2ePom.e.porDiag1 & POR_BAD_UART2)
+ {
+ pB->i2eGoodMap[0] &= ~0xf0;
+ }
+
+ break; // POR_ID_FII case
+
+ case POR_ID_FIIEX: // IntelliPort-IIEX
+
+ pB->i2eFifoStyle = FIFO_IIEX;
+
+ itemp = pB->i2ePom.e.porFifoSize;
+
+ // Implicit assumption that fifo would not grow beyond 32k,
+ // nor would ever be less than 256.
+
+ if (itemp < 8 || itemp > 15)
+ {
+ COMPLETE(pB, I2EE_INCONSIST);
+ }
+ pB->i2eFifoSize = (1 << itemp);
+
+ // These are based on what P.O.S.T thinks should be there, based on
+ // box ID registers
+ ilimit = pB->i2ePom.e.porNumBoxes;
+ if (ilimit > ABS_MAX_BOXES)
+ {
+ ilimit = ABS_MAX_BOXES;
+ }
+
+ // For as many boxes as EXIST, gives the type of box.
+ // Added 8/6/93: check for the ISA-4 (asic) which looks like an
+ // expandable but for whom "8 or 16?" is not the right question.
+
+ utemp = pB->i2ePom.e.porFlags;
+ if (utemp & POR_CEX4)
+ {
+ pB->i2eChannelMap[0] = 0x000f;
+ } else {
+ utemp &= POR_BOXES;
+ for (itemp = 0; itemp < ilimit; itemp++)
+ {
+ pB->i2eChannelMap[itemp] =
+ ((utemp & POR_BOX_16) ? 0xffff : 0x00ff);
+ utemp >>= 1;
+ }
+ }
+
+ // These are based on what P.O.S.T actually found.
+
+ utemp = (pB->i2ePom.e.porPorts2 << 8) + pB->i2ePom.e.porPorts1;
+
+ for (itemp = 0; itemp < ilimit; itemp++)
+ {
+ pB->i2eGoodMap[itemp] = 0;
+ if (utemp & 1) pB->i2eGoodMap[itemp] |= 0x000f;
+ if (utemp & 2) pB->i2eGoodMap[itemp] |= 0x00f0;
+ if (utemp & 4) pB->i2eGoodMap[itemp] |= 0x0f00;
+ if (utemp & 8) pB->i2eGoodMap[itemp] |= 0xf000;
+ utemp >>= 4;
+ }
+
+ // Now determine whether we should transfer in 8 or 16-bit mode.
+ switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) )
+ {
+ case POR_BUS_SLOT16 | POR_BUS_DIP16:
+ pB->i2eDataWidth16 = YES;
+ pB->i2eMaxIrq = 15;
+ break;
+
+ case POR_BUS_SLOT16:
+ pB->i2eDataWidth16 = NO;
+ pB->i2eMaxIrq = 15;
+ break;
+
+ case 0:
+ case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care.
+ default:
+ pB->i2eDataWidth16 = NO;
+ pB->i2eMaxIrq = 7;
+ break;
+ }
+ break; // POR_ID_FIIEX case
+
+ default: // Unknown type of board
+ COMPLETE(pB, I2EE_BAD_FAMILY);
+ break;
+ } // End the switch based on family
+
+ // Temporarily, claim there is no room in the outbound fifo.
+ // We will maintain this whenever we check for an empty outbound FIFO.
+ pB->i2eFifoRemains = 0;
+
+ // Now, based on the bus type, should we expect to be able to re-configure
+ // interrupts (say, for testing purposes).
+ switch (pB->i2ePom.e.porBus & POR_BUS_TYPE)
+ {
+ case POR_BUS_T_ISA:
+ case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok.
+ pB->i2eChangeIrq = YES;
+ break;
+ case POR_BUS_T_MCA:
+ case POR_BUS_T_EISA:
+ pB->i2eChangeIrq = NO;
+ break;
+ default:
+ COMPLETE(pB, I2EE_BADBUS);
+ }
+
+ if (pB->i2eDataWidth16 == YES)
+ {
+ pB->i2eWriteBuf = iiWriteBuf16;
+ pB->i2eReadBuf = iiReadBuf16;
+ pB->i2eWriteWord = iiWriteWord16;
+ pB->i2eReadWord = iiReadWord16;
+ } else {
+ pB->i2eWriteBuf = iiWriteBuf8;
+ pB->i2eReadBuf = iiReadBuf8;
+ pB->i2eWriteWord = iiWriteWord8;
+ pB->i2eReadWord = iiReadWord8;
+ }
+
+ switch(pB->i2eFifoStyle)
+ {
+ case FIFO_II:
+ pB->i2eWaitForTxEmpty = iiWaitForTxEmptyII;
+ pB->i2eTxMailEmpty = iiTxMailEmptyII;
+ pB->i2eTrySendMail = iiTrySendMailII;
+ pB->i2eGetMail = iiGetMailII;
+ pB->i2eEnableMailIrq = iiEnableMailIrqII;
+ pB->i2eWriteMask = iiWriteMaskII;
+
+ break;
+
+ case FIFO_IIEX:
+ pB->i2eWaitForTxEmpty = iiWaitForTxEmptyIIEX;
+ pB->i2eTxMailEmpty = iiTxMailEmptyIIEX;
+ pB->i2eTrySendMail = iiTrySendMailIIEX;
+ pB->i2eGetMail = iiGetMailIIEX;
+ pB->i2eEnableMailIrq = iiEnableMailIrqIIEX;
+ pB->i2eWriteMask = iiWriteMaskIIEX;
+
+ break;
+
+ default:
+ COMPLETE(pB, I2EE_INCONSIST);
+ }
+
+ // Initialize state information.
+ pB->i2eState = II_STATE_READY; // Ready to load loadware.
+
+ // Some Final cleanup:
+ // For some boards, the bootstrap firmware may perform some sort of test
+ // resulting in a stray character pending in the incoming mailbox. If one is
+ // there, it should be read and discarded, especially since for the standard
+ // firmware, it's the mailbox that interrupts the host.
+
+ pB->i2eStartMail = iiGetMail(pB);
+
+ // Throw it away and clear the mailbox structure element
+ pB->i2eStartMail = NO_MAIL_HERE;
+
+ // Everything is ok now, return with good status/
+
+ pB->i2eValid = I2E_MAGIC;
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//=======================================================
+// Delay Routines
+//
+// iiDelayIO
+// iiNop
+//=======================================================
+
+static void
+ii2DelayWakeup(unsigned long id)
+{
+ wake_up_interruptible ( &pDelayWait );
+}
+
+//******************************************************************************
+// Function: ii2DelayTimer(mseconds)
+// Parameters: mseconds - number of milliseconds to delay
+//
+// Returns: Nothing
+//
+// Description:
+//
+// This routine delays for approximately mseconds milliseconds and is intended
+// to be called indirectly through i2Delay field in i2eBordStr. It uses the
+// Linux timer_list mechanism.
+//
+// The Linux timers use a unit called "jiffies" which are 10mS in the Intel
+// architecture. This function rounds the delay period up to the next "jiffy".
+// In the Alpha architecture the "jiffy" is 1mS, but this driver is not intended
+// for Alpha platforms at this time.
+//
+//******************************************************************************
+static void
+ii2DelayTimer(unsigned int mseconds)
+{
+ wait_queue_t wait;
+
+ init_waitqueue_entry(&wait, current);
+
+ init_timer ( pDelayTimer );
+
+ add_wait_queue(&pDelayWait, &wait);
+
+ set_current_state( TASK_INTERRUPTIBLE );
+
+ pDelayTimer->expires = jiffies + ( mseconds + 9 ) / 10;
+ pDelayTimer->function = ii2DelayWakeup;
+ pDelayTimer->data = 0;
+
+ add_timer ( pDelayTimer );
+
+ schedule();
+
+ set_current_state( TASK_RUNNING );
+ remove_wait_queue(&pDelayWait, &wait);
+
+ del_timer ( pDelayTimer );
+}
+
+#if 0
+//static void ii2DelayIO(unsigned int);
+//******************************************************************************
+// !!! Not Used, this is DOS crap, some of you young folks may be interested in
+// in how things were done in the stone age of caculating machines !!!
+// Function: ii2DelayIO(mseconds)
+// Parameters: mseconds - number of milliseconds to delay
+//
+// Returns: Nothing
+//
+// Description:
+//
+// This routine delays for approximately mseconds milliseconds and is intended
+// to be called indirectly through i2Delay field in i2eBordStr. It is intended
+// for use where a clock-based function is impossible: for example, DOS drivers.
+//
+// This function uses the IN instruction to place bounds on the timing and
+// assumes that ii2Safe has been set. This is because I/O instructions are not
+// subject to caching and will therefore take a certain minimum time. To ensure
+// the delay is at least long enough on fast machines, it is based on some
+// fastest-case calculations. On slower machines this may cause VERY long
+// delays. (3 x fastest case). In the fastest case, everything is cached except
+// the I/O instruction itself.
+//
+// Timing calculations:
+// The fastest bus speed for I/O operations is likely to be 10 MHz. The I/O
+// operation in question is a byte operation to an odd address. For 8-bit
+// operations, the architecture generally enforces two wait states. At 10 MHz, a
+// single cycle time is 100nS. A read operation at two wait states takes 6
+// cycles for a total time of 600nS. Therefore approximately 1666 iterations
+// would be required to generate a single millisecond delay. The worst
+// (reasonable) case would be an 8MHz system with no cacheing. In this case, the
+// I/O instruction would take 125nS x 6 cyles = 750 nS. More importantly, code
+// fetch of other instructions in the loop would take time (zero wait states,
+// however) and would be hard to estimate. This is minimized by using in-line
+// assembler for the in inner loop of IN instructions. This consists of just a
+// few bytes. So we'll guess about four code fetches per loop. Each code fetch
+// should take four cycles, so we have 125nS * 8 = 1000nS. Worst case then is
+// that what should have taken 1 mS takes instead 1666 * (1750) = 2.9 mS.
+//
+// So much for theoretical timings: results using 1666 value on some actual
+// machines:
+// IBM 286 6MHz 3.15 mS
+// Zenith 386 33MHz 2.45 mS
+// (brandX) 386 33MHz 1.90 mS (has cache)
+// (brandY) 486 33MHz 2.35 mS
+// NCR 486 ?? 1.65 mS (microchannel)
+//
+// For most machines, it is probably safe to scale this number back (remember,
+// for robust operation use an actual timed delay if possible), so we are using
+// a value of 1190. This yields 1.17 mS for the fastest machine in our sample,
+// 1.75 mS for typical 386 machines, and 2.25 mS the absolute slowest machine.
+//
+// 1/29/93:
+// The above timings are too slow. Actual cycle times might be faster. ISA cycle
+// times could approach 500 nS, and ...
+// The IBM model 77 being microchannel has no wait states for 8-bit reads and
+// seems to be accessing the I/O at 440 nS per access (from start of one to
+// start of next). This would imply we need 1000/.440 = 2272 iterations to
+// guarantee we are fast enough. In actual testing, we see that 2 * 1190 are in
+// fact enough. For diagnostics, we keep the level at 1190, but developers note
+// this needs tuning.
+//
+// Safe assumption: 2270 i/o reads = 1 millisecond
+//
+//******************************************************************************
+
+
+static int ii2DelValue = 1190; // See timing calculations below
+ // 1666 for fastest theoretical machine
+ // 1190 safe for most fast 386 machines
+ // 1000 for fastest machine tested here
+ // 540 (sic) for AT286/6Mhz
+static void
+ii2DelayIO(unsigned int mseconds)
+{
+ if (!ii2Safe)
+ return; /* Do nothing if this variable uninitialized */
+
+ while(mseconds--) {
+ int i = ii2DelValue;
+ while ( i-- ) {
+ INB ( ii2Safe );
+ }
+ }
+}
+#endif
+
+//******************************************************************************
+// Function: ii2Nop()
+// Parameters: None
+//
+// Returns: Nothing
+//
+// Description:
+//
+// iiInitialize will set i2eDelay to this if the delay parameter is NULL. This
+// saves checking for a NULL pointer at every call.
+//******************************************************************************
+static void
+ii2Nop(void)
+{
+ return; // no mystery here
+}
+
+//=======================================================
+// Routines which are available in 8/16-bit versions, or
+// in different fifo styles. These are ALL called
+// indirectly through the board structure.
+//=======================================================
+
+//******************************************************************************
+// Function: iiWriteBuf16(pB, address, count)
+// Parameters: pB - pointer to board structure
+// address - address of data to write
+// count - number of data bytes to write
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Writes 'count' bytes from 'address' to the data fifo specified by the board
+// structure pointer pB. Should count happen to be odd, an extra pad byte is
+// sent (identity unknown...). Uses 16-bit (word) operations. Is called
+// indirectly through pB->i2eWriteBuf.
+//
+//******************************************************************************
+static int
+iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
+{
+ // Rudimentary sanity checking here.
+ if (pB->i2eValid != I2E_MAGIC)
+ COMPLETE(pB, I2EE_INVALID);
+
+ OUTSW ( pB->i2eData, address, count);
+
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiWriteBuf8(pB, address, count)
+// Parameters: pB - pointer to board structure
+// address - address of data to write
+// count - number of data bytes to write
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Writes 'count' bytes from 'address' to the data fifo specified by the board
+// structure pointer pB. Should count happen to be odd, an extra pad byte is
+// sent (identity unknown...). This is to be consistent with the 16-bit version.
+// Uses 8-bit (byte) operations. Is called indirectly through pB->i2eWriteBuf.
+//
+//******************************************************************************
+static int
+iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
+{
+ /* Rudimentary sanity checking here */
+ if (pB->i2eValid != I2E_MAGIC)
+ COMPLETE(pB, I2EE_INVALID);
+
+ OUTSB ( pB->i2eData, address, count );
+
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiReadBuf16(pB, address, count)
+// Parameters: pB - pointer to board structure
+// address - address to put data read
+// count - number of data bytes to read
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Reads 'count' bytes into 'address' from the data fifo specified by the board
+// structure pointer pB. Should count happen to be odd, an extra pad byte is
+// received (identity unknown...). Uses 16-bit (word) operations. Is called
+// indirectly through pB->i2eReadBuf.
+//
+//******************************************************************************
+static int
+iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
+{
+ // Rudimentary sanity checking here.
+ if (pB->i2eValid != I2E_MAGIC)
+ COMPLETE(pB, I2EE_INVALID);
+
+ INSW ( pB->i2eData, address, count);
+
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiReadBuf8(pB, address, count)
+// Parameters: pB - pointer to board structure
+// address - address to put data read
+// count - number of data bytes to read
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Reads 'count' bytes into 'address' from the data fifo specified by the board
+// structure pointer pB. Should count happen to be odd, an extra pad byte is
+// received (identity unknown...). This to match the 16-bit behaviour. Uses
+// 8-bit (byte) operations. Is called indirectly through pB->i2eReadBuf.
+//
+//******************************************************************************
+static int
+iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
+{
+ // Rudimentary sanity checking here.
+ if (pB->i2eValid != I2E_MAGIC)
+ COMPLETE(pB, I2EE_INVALID);
+
+ INSB ( pB->i2eData, address, count);
+
+ COMPLETE(pB, I2EE_GOOD);
+}
+
+//******************************************************************************
+// Function: iiReadWord16(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Returns the word read from the data fifo specified by the board-structure
+// pointer pB. Uses a 16-bit operation. Is called indirectly through
+// pB->i2eReadWord.
+//
+//******************************************************************************
+static unsigned short
+iiReadWord16(i2eBordStrPtr pB)
+{
+ return (unsigned short)( INW(pB->i2eData) );
+}
+
+//******************************************************************************
+// Function: iiReadWord8(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Returns the word read from the data fifo specified by the board-structure
+// pointer pB. Uses two 8-bit operations. Bytes are assumed to be LSB first. Is
+// called indirectly through pB->i2eReadWord.
+//
+//******************************************************************************
+static unsigned short
+iiReadWord8(i2eBordStrPtr pB)
+{
+ unsigned short urs;
+
+ urs = INB ( pB->i2eData );
+
+ return ( ( INB ( pB->i2eData ) << 8 ) | urs );
+}
+
+//******************************************************************************
+// Function: iiWriteWord16(pB, value)
+// Parameters: pB - pointer to board structure
+// value - data to write
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Writes the word 'value' to the data fifo specified by the board-structure
+// pointer pB. Uses 16-bit operation. Is called indirectly through
+// pB->i2eWriteWord.
+//
+//******************************************************************************
+static void
+iiWriteWord16(i2eBordStrPtr pB, unsigned short value)
+{
+ WORD_TO(pB, (int)value);
+}
+
+//******************************************************************************
+// Function: iiWriteWord8(pB, value)
+// Parameters: pB - pointer to board structure
+// value - data to write
+//
+// Returns: True if everything appears copacetic.
+// False if there is any error: the pB->i2eError field has the error
+//
+// Description:
+//
+// Writes the word 'value' to the data fifo specified by the board-structure
+// pointer pB. Uses two 8-bit operations (writes LSB first). Is called
+// indirectly through pB->i2eWriteWord.
+//
+//******************************************************************************
+static void
+iiWriteWord8(i2eBordStrPtr pB, unsigned short value)
+{
+ BYTE_TO(pB, (char)value);
+ BYTE_TO(pB, (char)(value >> 8) );
+}
+
+//******************************************************************************
+// Function: iiWaitForTxEmptyII(pB, mSdelay)
+// Parameters: pB - pointer to board structure
+// mSdelay - period to wait before returning
+//
+// Returns: True if the FIFO is empty.
+// False if it not empty in the required time: the pB->i2eError
+// field has the error.
+//
+// Description:
+//
+// Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if
+// not empty by the required time, returns false and error in pB->i2eError,
+// otherwise returns true.
+//
+// mSdelay == 0 is taken to mean must be empty on the first test.
+//
+// This version operates on IntelliPort-II - style FIFO's
+//
+// Note this routine is organized so that if status is ok there is no delay at
+// all called either before or after the test. Is called indirectly through
+// pB->i2eWaitForTxEmpty.
+//
+//******************************************************************************
+static int
+iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay)
+{
+ unsigned long flags;
+ int itemp;
+
+ for (;;)
+ {
+ // This routine hinges on being able to see the "other" status register
+ // (as seen by the local processor). His incoming fifo is our outgoing
+ // FIFO.
+ //
+ // By the nature of this routine, you would be using this as part of a
+ // larger atomic context: i.e., you would use this routine to ensure the
+ // fifo empty, then act on this information. Between these two halves,
+ // you will generally not want to service interrupts or in any way
+ // disrupt the assumptions implicit in the larger context.
+ //
+ // Even worse, however, this routine "shifts" the status register to
+ // point to the local status register which is not the usual situation.
+ // Therefore for extra safety, we force the critical section to be
+ // completely atomic, and pick up after ourselves before allowing any
+ // interrupts of any kind.
+
+
+ WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags)
+ OUTB(pB->i2ePointer, SEL_COMMAND);
+ OUTB(pB->i2ePointer, SEL_CMD_SH);
+
+ itemp = INB(pB->i2eStatus);
+
+ OUTB(pB->i2ePointer, SEL_COMMAND);
+ OUTB(pB->i2ePointer, SEL_CMD_UNSH);
+
+ if (itemp & ST_IN_EMPTY)
+ {
+ UPDATE_FIFO_ROOM(pB);
+ WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
+ COMPLETE(pB, I2EE_GOOD);
+ }
+
+ WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
+
+ if (mSdelay-- == 0)
+ break;
+
+ iiDelay(pB, 1); /* 1 mS granularity on checking condition */
+ }
+ COMPLETE(pB, I2EE_TXE_TIME);
+}
+
+//******************************************************************************
+// Function: iiWaitForTxEmptyIIEX(pB, mSdelay)
+// Parameters: pB - pointer to board structure
+// mSdelay - period to wait before returning
+//
+// Returns: True if the FIFO is empty.
+// False if it not empty in the required time: the pB->i2eError
+// field has the error.
+//
+// Description:
+//
+// Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if
+// not empty by the required time, returns false and error in pB->i2eError,
+// otherwise returns true.
+//
+// mSdelay == 0 is taken to mean must be empty on the first test.
+//
+// This version operates on IntelliPort-IIEX - style FIFO's
+//
+// Note this routine is organized so that if status is ok there is no delay at
+// all called either before or after the test. Is called indirectly through
+// pB->i2eWaitForTxEmpty.
+//
+//******************************************************************************
+static int
+iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay)
+{
+ unsigned long flags;
+
+ for (;;)
+ {
+ // By the nature of this routine, you would be using this as part of a
+ // larger atomic context: i.e., you would use this routine to ensure the
+ // fifo empty, then act on this information. Between these two halves,
+ // you will generally not want to service interrupts or in any way
+ // disrupt the assumptions implicit in the larger context.
+
+ WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags)
+
+ if (INB(pB->i2eStatus) & STE_OUT_MT) {
+ UPDATE_FIFO_ROOM(pB);
+ WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
+ COMPLETE(pB, I2EE_GOOD);
+ }
+ WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
+
+ if (mSdelay-- == 0)
+ break;
+
+ iiDelay(pB, 1); // 1 mS granularity on checking condition
+ }
+ COMPLETE(pB, I2EE_TXE_TIME);
+}
+
+//******************************************************************************
+// Function: iiTxMailEmptyII(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: True if the transmit mailbox is empty.
+// False if it not empty.
+//
+// Description:
+//
+// Returns true or false according to whether the transmit mailbox is empty (and
+// therefore able to accept more mail)
+//
+// This version operates on IntelliPort-II - style FIFO's
+//
+//******************************************************************************
+static int
+iiTxMailEmptyII(i2eBordStrPtr pB)
+{
+ int port = pB->i2ePointer;
+ OUTB ( port, SEL_OUTMAIL );
+ return ( INB(port) == 0 );
+}
+
+//******************************************************************************
+// Function: iiTxMailEmptyIIEX(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: True if the transmit mailbox is empty.
+// False if it not empty.
+//
+// Description:
+//
+// Returns true or false according to whether the transmit mailbox is empty (and
+// therefore able to accept more mail)
+//
+// This version operates on IntelliPort-IIEX - style FIFO's
+//
+//******************************************************************************
+static int
+iiTxMailEmptyIIEX(i2eBordStrPtr pB)
+{
+ return !(INB(pB->i2eStatus) & STE_OUT_MAIL);
+}
+
+//******************************************************************************
+// Function: iiTrySendMailII(pB,mail)
+// Parameters: pB - pointer to board structure
+// mail - value to write to mailbox
+//
+// Returns: True if the transmit mailbox is empty, and mail is sent.
+// False if it not empty.
+//
+// Description:
+//
+// If outgoing mailbox is empty, sends mail and returns true. If outgoing
+// mailbox is not empty, returns false.
+//
+// This version operates on IntelliPort-II - style FIFO's
+//
+//******************************************************************************
+static int
+iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail)
+{
+ int port = pB->i2ePointer;
+
+ OUTB(port, SEL_OUTMAIL);
+ if (INB(port) == 0) {
+ OUTB(port, SEL_OUTMAIL);
+ OUTB(port, mail);
+ return 1;
+ }
+ return 0;
+}
+
+//******************************************************************************
+// Function: iiTrySendMailIIEX(pB,mail)
+// Parameters: pB - pointer to board structure
+// mail - value to write to mailbox
+//
+// Returns: True if the transmit mailbox is empty, and mail is sent.
+// False if it not empty.
+//
+// Description:
+//
+// If outgoing mailbox is empty, sends mail and returns true. If outgoing
+// mailbox is not empty, returns false.
+//
+// This version operates on IntelliPort-IIEX - style FIFO's
+//
+//******************************************************************************
+static int
+iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail)
+{
+ if(INB(pB->i2eStatus) & STE_OUT_MAIL) {
+ return 0;
+ }
+ OUTB(pB->i2eXMail, mail);
+ return 1;
+}
+
+//******************************************************************************
+// Function: iiGetMailII(pB,mail)
+// Parameters: pB - pointer to board structure
+//
+// Returns: Mailbox data or NO_MAIL_HERE.
+//
+// Description:
+//
+// If no mail available, returns NO_MAIL_HERE otherwise returns the data from
+// the mailbox, which is guaranteed != NO_MAIL_HERE.
+//
+// This version operates on IntelliPort-II - style FIFO's
+//
+//******************************************************************************
+static unsigned short
+iiGetMailII(i2eBordStrPtr pB)
+{
+ if (HAS_MAIL(pB)) {
+ OUTB(pB->i2ePointer, SEL_INMAIL);
+ return INB(pB->i2ePointer);
+ } else {
+ return NO_MAIL_HERE;
+ }
+}
+
+//******************************************************************************
+// Function: iiGetMailIIEX(pB,mail)
+// Parameters: pB - pointer to board structure
+//
+// Returns: Mailbox data or NO_MAIL_HERE.
+//
+// Description:
+//
+// If no mail available, returns NO_MAIL_HERE otherwise returns the data from
+// the mailbox, which is guaranteed != NO_MAIL_HERE.
+//
+// This version operates on IntelliPort-IIEX - style FIFO's
+//
+//******************************************************************************
+static unsigned short
+iiGetMailIIEX(i2eBordStrPtr pB)
+{
+ if (HAS_MAIL(pB)) {
+ return INB(pB->i2eXMail);
+ } else {
+ return NO_MAIL_HERE;
+ }
+}
+
+//******************************************************************************
+// Function: iiEnableMailIrqII(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: Nothing
+//
+// Description:
+//
+// Enables board to interrupt host (only) by writing to host's in-bound mailbox.
+//
+// This version operates on IntelliPort-II - style FIFO's
+//
+//******************************************************************************
+static void
+iiEnableMailIrqII(i2eBordStrPtr pB)
+{
+ OUTB(pB->i2ePointer, SEL_MASK);
+ OUTB(pB->i2ePointer, ST_IN_MAIL);
+}
+
+//******************************************************************************
+// Function: iiEnableMailIrqIIEX(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: Nothing
+//
+// Description:
+//
+// Enables board to interrupt host (only) by writing to host's in-bound mailbox.
+//
+// This version operates on IntelliPort-IIEX - style FIFO's
+//
+//******************************************************************************
+static void
+iiEnableMailIrqIIEX(i2eBordStrPtr pB)
+{
+ OUTB(pB->i2eXMask, MX_IN_MAIL);
+}
+
+//******************************************************************************
+// Function: iiWriteMaskII(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: Nothing
+//
+// Description:
+//
+// Writes arbitrary value to the mask register.
+//
+// This version operates on IntelliPort-II - style FIFO's
+//
+//******************************************************************************
+static void
+iiWriteMaskII(i2eBordStrPtr pB, unsigned char value)
+{
+ OUTB(pB->i2ePointer, SEL_MASK);
+ OUTB(pB->i2ePointer, value);
+}
+
+//******************************************************************************
+// Function: iiWriteMaskIIEX(pB)
+// Parameters: pB - pointer to board structure
+//
+// Returns: Nothing
+//
+// Description:
+//
+// Writes arbitrary value to the mask register.
+//
+// This version operates on IntelliPort-IIEX - style FIFO's
+//
+//******************************************************************************
+static void
+iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value)
+{
+ OUTB(pB->i2eXMask, value);
+}
+
+//******************************************************************************
+// Function: iiDownloadBlock(pB, pSource, isStandard)
+// Parameters: pB - pointer to board structure
+// pSource - loadware block to download
+// isStandard - True if "standard" loadware, else false.
+//
+// Returns: Success or Failure
+//
+// Description:
+//
+// Downloads a single block (at pSource)to the board referenced by pB. Caller
+// sets isStandard to true/false according to whether the "standard" loadware is
+// what's being loaded. The normal process, then, is to perform an iiInitialize
+// to the board, then perform some number of iiDownloadBlocks using the returned
+// state to determine when download is complete.
+//
+// Possible return values: (see I2ELLIS.H)
+// II_DOWN_BADVALID
+// II_DOWN_BADFILE
+// II_DOWN_CONTINUING
+// II_DOWN_GOOD
+// II_DOWN_BAD
+// II_DOWN_BADSTATE
+// II_DOWN_TIMEOUT
+//
+// Uses the i2eState and i2eToLoad fields (initialized at iiInitialize) to
+// determine whether this is the first block, whether to check for magic
+// numbers, how many blocks there are to go...
+//
+//******************************************************************************
+static int
+iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard)
+{
+ int itemp;
+ int loadedFirst;
+
+ if (pB->i2eValid != I2E_MAGIC) return II_DOWN_BADVALID;
+
+ switch(pB->i2eState)
+ {
+ case II_STATE_READY:
+
+ // Loading the first block after reset. Must check the magic number of the
+ // loadfile, store the number of blocks we expect to load.
+ if (pSource->e.loadMagic != MAGIC_LOADFILE)
+ {
+ return II_DOWN_BADFILE;
+ }
+
+ // Next we store the total number of blocks to load, including this one.
+ pB->i2eToLoad = 1 + pSource->e.loadBlocksMore;
+
+ // Set the state, store the version numbers. ('Cause this may have come
+ // from a file - we might want to report these versions and revisions in
+ // case of an error!
+ pB->i2eState = II_STATE_LOADING;
+ pB->i2eLVersion = pSource->e.loadVersion;
+ pB->i2eLRevision = pSource->e.loadRevision;
+ pB->i2eLSub = pSource->e.loadSubRevision;
+
+ // The time and date of compilation is also available but don't bother
+ // storing it for normal purposes.
+ loadedFirst = 1;
+ break;
+
+ case II_STATE_LOADING:
+ loadedFirst = 0;
+ break;
+
+ default:
+ return II_DOWN_BADSTATE;
+ }
+
+ // Now we must be in the II_STATE_LOADING state, and we assume i2eToLoad
+ // must be positive still, because otherwise we would have cleaned up last
+ // time and set the state to II_STATE_LOADED.
+ if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) {
+ return II_DOWN_TIMEOUT;
+ }
+
+ if (!iiWriteBuf(pB, pSource->c, LOADWARE_BLOCK_SIZE)) {
+ return II_DOWN_BADVALID;
+ }
+
+ // If we just loaded the first block, wait for the fifo to empty an extra
+ // long time to allow for any special startup code in the firmware, like
+ // sending status messages to the LCD's.
+
+ if (loadedFirst) {
+ if (!iiWaitForTxEmpty(pB, MAX_DLOAD_START_TIME)) {
+ return II_DOWN_TIMEOUT;
+ }
+ }
+
+ // Determine whether this was our last block!
+ if (--(pB->i2eToLoad)) {
+ return II_DOWN_CONTINUING; // more to come...
+ }
+
+ // It WAS our last block: Clean up operations...
+ // ...Wait for last buffer to drain from the board...
+ if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) {
+ return II_DOWN_TIMEOUT;
+ }
+ // If there were only a single block written, this would come back
+ // immediately and be harmless, though not strictly necessary.
+ itemp = MAX_DLOAD_ACK_TIME/10;
+ while (--itemp) {
+ if (HAS_INPUT(pB)) {
+ switch(BYTE_FROM(pB))
+ {
+ case LOADWARE_OK:
+ pB->i2eState =
+ isStandard ? II_STATE_STDLOADED :II_STATE_LOADED;
+
+ // Some revisions of the bootstrap firmware (e.g. ISA-8 1.0.2)
+ // will, // if there is a debug port attached, require some
+ // time to send information to the debug port now. It will do
+ // this before // executing any of the code we just downloaded.
+ // It may take up to 700 milliseconds.
+ if (pB->i2ePom.e.porDiag2 & POR_DEBUG_PORT) {
+ iiDelay(pB, 700);
+ }
+
+ return II_DOWN_GOOD;
+
+ case LOADWARE_BAD:
+ default:
+ return II_DOWN_BAD;
+ }
+ }
+
+ iiDelay(pB, 10); // 10 mS granularity on checking condition
+ }
+
+ // Drop-through --> timed out waiting for firmware confirmation
+
+ pB->i2eState = II_STATE_BADLOAD;
+ return II_DOWN_TIMEOUT;
+}
+
+//******************************************************************************
+// Function: iiDownloadAll(pB, pSource, isStandard, size)
+// Parameters: pB - pointer to board structure
+// pSource - loadware block to download
+// isStandard - True if "standard" loadware, else false.
+// size - size of data to download (in bytes)
+//
+// Returns: Success or Failure
+//
+// Description:
+//
+// Given a pointer to a board structure, a pointer to the beginning of some
+// loadware, whether it is considered the "standard loadware", and the size of
+// the array in bytes loads the entire array to the board as loadware.
+//
+// Assumes the board has been freshly reset and the power-up reset message read.
+// (i.e., in II_STATE_READY). Complains if state is bad, or if there seems to be
+// too much or too little data to load, or if iiDownloadBlock complains.
+//******************************************************************************
+static int
+iiDownloadAll(i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard, int size)
+{
+ int status;
+
+ // We know (from context) board should be ready for the first block of
+ // download. Complain if not.
+ if (pB->i2eState != II_STATE_READY) return II_DOWN_BADSTATE;
+
+ while (size > 0) {
+ size -= LOADWARE_BLOCK_SIZE; // How much data should there be left to
+ // load after the following operation ?
+
+ // Note we just bump pSource by "one", because its size is actually that
+ // of an entire block, same as LOADWARE_BLOCK_SIZE.
+ status = iiDownloadBlock(pB, pSource++, isStandard);
+
+ switch(status)
+ {
+ case II_DOWN_GOOD:
+ return ( (size > 0) ? II_DOWN_OVER : II_DOWN_GOOD);
+
+ case II_DOWN_CONTINUING:
+ break;
+
+ default:
+ return status;
+ }
+ }
+
+ // We shouldn't drop out: it means "while" caught us with nothing left to
+ // download, yet the previous DownloadBlock did not return complete. Ergo,
+ // not enough data to match the size byte in the header.
+ return II_DOWN_UNDER;
+}
diff --git a/drivers/char/ip2/i2ellis.h b/drivers/char/ip2/i2ellis.h
new file mode 100644
index 0000000..510b026
--- /dev/null
+++ b/drivers/char/ip2/i2ellis.h
@@ -0,0 +1,615 @@
+/*******************************************************************************
+*
+* (c) 1999 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Mainline code for the device driver
+*
+*******************************************************************************/
+//------------------------------------------------------------------------------
+// i2ellis.h
+//
+// IntelliPort-II and IntelliPort-IIEX
+//
+// Extremely
+// Low
+// Level
+// Interface
+// Services
+//
+// Structure Definitions and declarations for "ELLIS" service routines found in
+// i2ellis.c
+//
+// These routines are based on properties of the IntelliPort-II and -IIEX
+// hardware and bootstrap firmware, and are not sensitive to particular
+// conventions of any particular loadware.
+//
+// Unlike i2hw.h, which provides IRONCLAD hardware definitions, the material
+// here and in i2ellis.c is intended to provice a useful, but not required,
+// layer of insulation from the hardware specifics.
+//------------------------------------------------------------------------------
+#ifndef I2ELLIS_H /* To prevent multiple includes */
+#define I2ELLIS_H 1
+//------------------------------------------------
+// Revision History:
+//
+// 30 September 1991 MAG First Draft Started
+// 12 October 1991 ...continued...
+//
+// 20 December 1996 AKM Linux version
+//-------------------------------------------------
+
+//----------------------
+// Mandatory Includes:
+//----------------------
+#include <linux/config.h>
+#include "ip2types.h"
+#include "i2hw.h" // The hardware definitions
+
+//------------------------------------------
+// STAT_BOXIDS packets
+//------------------------------------------
+#define MAX_BOX 4
+
+typedef struct _bidStat
+{
+ unsigned char bid_value[MAX_BOX];
+} bidStat, *bidStatPtr;
+
+// This packet is sent in response to a CMD_GET_BOXIDS bypass command. For -IIEX
+// boards, reports the hardware-specific "asynchronous resource register" on
+// each expansion box. Boxes not present report 0xff. For -II boards, the first
+// element contains 0x80 for 8-port, 0x40 for 4-port boards.
+
+// Box IDs aka ARR or Async Resource Register (more than you want to know)
+// 7 6 5 4 3 2 1 0
+// F F N N L S S S
+// =============================
+// F F - Product Family Designator
+// =====+++++++++++++++++++++++++++++++
+// 0 0 - Intelliport II EX / ISA-8
+// 1 0 - IntelliServer
+// 0 1 - SAC - Port Device (Intelliport III ??? )
+// =====+++++++++++++++++++++++++++++++++++++++
+// N N - Number of Ports
+// 0 0 - 8 (eight)
+// 0 1 - 4 (four)
+// 1 0 - 12 (twelve)
+// 1 1 - 16 (sixteen)
+// =++++++++++++++++++++++++++++++++++
+// L - LCD Display Module Present
+// 0 - No
+// 1 - LCD module present
+// =========+++++++++++++++++++++++++++++++++++++
+// S S S - Async Signals Supported Designator
+// 0 0 0 - 8dss, Mod DCE DB25 Female
+// 0 0 1 - 6dss, RJ-45
+// 0 1 0 - RS-232/422 dss, DB25 Female
+// 0 1 1 - RS-232/422 dss, separate 232/422 DB25 Female
+// 1 0 0 - 6dss, 921.6 I/F with ST654's
+// 1 0 1 - RS-423/232 8dss, RJ-45 10Pin
+// 1 1 0 - 6dss, Mod DCE DB25 Female
+// 1 1 1 - NO BOX PRESENT
+
+#define FF(c) ((c & 0xC0) >> 6)
+#define NN(c) ((c & 0x30) >> 4)
+#define L(c) ((c & 0x08) >> 3)
+#define SSS(c) (c & 0x07)
+
+#define BID_HAS_654(x) (SSS(x) == 0x04)
+#define BID_NO_BOX 0xff /* no box */
+#define BID_8PORT 0x80 /* IP2-8 port */
+#define BID_4PORT 0x81 /* IP2-4 port */
+#define BID_EXP_MASK 0x30 /* IP2-EX */
+#define BID_EXP_8PORT 0x00 /* 8, */
+#define BID_EXP_4PORT 0x10 /* 4, */
+#define BID_EXP_UNDEF 0x20 /* UNDEF, */
+#define BID_EXP_16PORT 0x30 /* 16, */
+#define BID_LCD_CTRL 0x08 /* LCD Controller */
+#define BID_LCD_NONE 0x00 /* - no controller present */
+#define BID_LCD_PRES 0x08 /* - controller present */
+#define BID_CON_MASK 0x07 /* - connector pinouts */
+#define BID_CON_DB25 0x00 /* - DB-25 F */
+#define BID_CON_RJ45 0x01 /* - rj45 */
+
+//------------------------------------------------------------------------------
+// i2eBordStr
+//
+// This structure contains all the information the ELLIS routines require in
+// dealing with a particular board.
+//------------------------------------------------------------------------------
+// There are some queues here which are guaranteed to never contain the entry
+// for a single channel twice. So they must be slightly larger to allow
+// unambiguous full/empty management
+//
+#define CH_QUEUE_SIZE ABS_MOST_PORTS+2
+
+typedef struct _i2eBordStr
+{
+ porStr i2ePom; // Structure containing the power-on message.
+
+ unsigned short i2ePomSize;
+ // The number of bytes actually read if
+ // different from sizeof i2ePom, indicates
+ // there is an error!
+
+ unsigned short i2eStartMail;
+ // Contains whatever inbound mailbox data
+ // present at startup. NO_MAIL_HERE indicates
+ // nothing was present. No special
+ // significance as of this writing, but may be
+ // useful for diagnostic reasons.
+
+ unsigned short i2eValid;
+ // Indicates validity of the structure; if
+ // i2eValid == I2E_MAGIC, then we can trust
+ // the other fields. Some (especially
+ // initialization) functions are good about
+ // checking for validity. Many functions do
+ // not, it being assumed that the larger
+ // context assures we are using a valid
+ // i2eBordStrPtr.
+
+ unsigned short i2eError;
+ // Used for returning an error condition from
+ // several functions which use i2eBordStrPtr
+ // as an argument.
+
+ // Accelerators to characterize separate features of a board, derived from a
+ // number of sources.
+
+ unsigned short i2eFifoSize;
+ // Always, the size of the FIFO. For
+ // IntelliPort-II, always the same, for -IIEX
+ // taken from the Power-On reset message.
+
+ volatile
+ unsigned short i2eFifoRemains;
+ // Used during normal operation to indicate a
+ // lower bound on the amount of data which
+ // might be in the outbound fifo.
+
+ unsigned char i2eFifoStyle;
+ // Accelerator which tells which style (-II or
+ // -IIEX) FIFO we are using.
+
+ unsigned char i2eDataWidth16;
+ // Accelerator which tells whether we should
+ // do 8 or 16-bit data transfers.
+
+ unsigned char i2eMaxIrq;
+ // The highest allowable IRQ, based on the
+ // slot size.
+
+ unsigned char i2eChangeIrq;
+ // Whether tis valid to change IRQ's
+ // ISA = ok, EISA, MicroChannel, no
+
+ // Accelerators for various addresses on the board
+ int i2eBase; // I/O Address of the Board
+ int i2eData; // From here data transfers happen
+ int i2eStatus; // From here status reads happen
+ int i2ePointer; // (IntelliPort-II: pointer/commands)
+ int i2eXMail; // (IntelliPOrt-IIEX: mailboxes
+ int i2eXMask; // (IntelliPort-IIEX: mask write
+
+ //-------------------------------------------------------
+ // Information presented in a common format across boards
+ // For each box, bit map of the channels present. Box closest to
+ // the host is box 0. LSB is channel 0. IntelliPort-II (non-expandable)
+ // is taken to be box 0. These are derived from product i.d. registers.
+
+ unsigned short i2eChannelMap[ABS_MAX_BOXES];
+
+ // Same as above, except each is derived from firmware attempting to detect
+ // the uart presence (by reading a valid GFRCR register). If bits are set in
+ // i2eChannelMap and not in i2eGoodMap, there is a potential problem.
+
+ unsigned short i2eGoodMap[ABS_MAX_BOXES];
+
+ // ---------------------------
+ // For indirect function calls
+
+ // Routine to cause an N-millisecond delay: Patched by the ii2Initialize
+ // function.
+
+ void (*i2eDelay)(unsigned int);
+
+ // Routine to write N bytes to the board through the FIFO. Returns true if
+ // all copacetic, otherwise returns false and error is in i2eError field.
+ // IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER.
+
+ int (*i2eWriteBuf)(struct _i2eBordStr *, unsigned char *, int);
+
+ // Routine to read N bytes from the board through the FIFO. Returns true if
+ // copacetic, otherwise returns false and error in i2eError.
+ // IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER.
+
+ int (*i2eReadBuf)(struct _i2eBordStr *, unsigned char *, int);
+
+ // Returns a word from FIFO. Will use 2 byte operations if needed.
+
+ unsigned short (*i2eReadWord)(struct _i2eBordStr *);
+
+ // Writes a word to FIFO. Will use 2 byte operations if needed.
+
+ void (*i2eWriteWord)(struct _i2eBordStr *, unsigned short);
+
+ // Waits specified time for the Transmit FIFO to go empty. Returns true if
+ // ok, otherwise returns false and error in i2eError.
+
+ int (*i2eWaitForTxEmpty)(struct _i2eBordStr *, int);
+
+ // Returns true or false according to whether the outgoing mailbox is empty.
+
+ int (*i2eTxMailEmpty)(struct _i2eBordStr *);
+
+ // Checks whether outgoing mailbox is empty. If so, sends mail and returns
+ // true. Otherwise returns false.
+
+ int (*i2eTrySendMail)(struct _i2eBordStr *, unsigned char);
+
+ // If no mail available, returns NO_MAIL_HERE, else returns the value in the
+ // mailbox (guaranteed can't be NO_MAIL_HERE).
+
+ unsigned short (*i2eGetMail)(struct _i2eBordStr *);
+
+ // Enables the board to interrupt the host when it writes to the mailbox.
+ // Irqs will not occur, however, until the loadware separately enables
+ // interrupt generation to the host. The standard loadware does this in
+ // response to a command packet sent by the host. (Also, disables
+ // any other potential interrupt sources from the board -- other than the
+ // inbound mailbox).
+
+ void (*i2eEnableMailIrq)(struct _i2eBordStr *);
+
+ // Writes an arbitrary value to the mask register.
+
+ void (*i2eWriteMask)(struct _i2eBordStr *, unsigned char);
+
+
+ // State information
+
+ // During downloading, indicates the number of blocks remaining to download
+ // to the board.
+
+ short i2eToLoad;
+
+ // State of board (see manifests below) (e.g., whether in reset condition,
+ // whether standard loadware is installed, etc.
+
+ unsigned char i2eState;
+
+ // These three fields are only valid when there is loadware running on the
+ // board. (i2eState == II_STATE_LOADED or i2eState == II_STATE_STDLOADED )
+
+ unsigned char i2eLVersion; // Loadware version
+ unsigned char i2eLRevision; // Loadware revision
+ unsigned char i2eLSub; // Loadware subrevision
+
+ // Flags which only have meaning in the context of the standard loadware.
+ // Somewhat violates the layering concept, but there is so little additional
+ // needed at the board level (while much additional at the channel level),
+ // that this beats maintaining two different per-board structures.
+
+ // Indicates which IRQ the board has been initialized (from software) to use
+ // For MicroChannel boards, any value different from IRQ_UNDEFINED means
+ // that the software command has been sent to enable interrupts (or specify
+ // they are disabled). Special value: IRQ_UNDEFINED indicates that the
+ // software command to select the interrupt has not yet been sent, therefore
+ // (since the standard loadware insists that it be sent before any other
+ // packets are sent) no other packets should be sent yet.
+
+ unsigned short i2eUsingIrq;
+
+ // This is set when we hit the MB_OUT_STUFFED mailbox, which prevents us
+ // putting more in the mailbox until an appropriate mailbox message is
+ // received.
+
+ unsigned char i2eWaitingForEmptyFifo;
+
+ // Any mailbox bits waiting to be sent to the board are OR'ed in here.
+
+ unsigned char i2eOutMailWaiting;
+
+ // The head of any incoming packet is read into here, is then examined and
+ // we dispatch accordingly.
+
+ unsigned short i2eLeadoffWord[1];
+
+ // Running counter of interrupts where the mailbox indicated incoming data.
+
+ unsigned short i2eFifoInInts;
+
+ // Running counter of interrupts where the mailbox indicated outgoing data
+ // had been stripped.
+
+ unsigned short i2eFifoOutInts;
+
+ // If not void, gives the address of a routine to call if fatal board error
+ // is found (only applies to standard l/w).
+
+ void (*i2eFatalTrap)(struct _i2eBordStr *);
+
+ // Will point to an array of some sort of channel structures (whose format
+ // is unknown at this level, being a function of what loadware is
+ // installed and the code configuration (max sizes of buffers, etc.)).
+
+ void *i2eChannelPtr;
+
+ // Set indicates that the board has gone fatal.
+
+ unsigned short i2eFatal;
+
+ // The number of elements pointed to by i2eChannelPtr.
+
+ unsigned short i2eChannelCnt;
+
+ // Ring-buffers of channel structures whose channels have particular needs.
+
+ rwlock_t Fbuf_spinlock;
+ volatile
+ unsigned short i2Fbuf_strip; // Strip index
+ volatile
+ unsigned short i2Fbuf_stuff; // Stuff index
+ void *i2Fbuf[CH_QUEUE_SIZE]; // An array of channel pointers
+ // of channels who need to send
+ // flow control packets.
+ rwlock_t Dbuf_spinlock;
+ volatile
+ unsigned short i2Dbuf_strip; // Strip index
+ volatile
+ unsigned short i2Dbuf_stuff; // Stuff index
+ void *i2Dbuf[CH_QUEUE_SIZE]; // An array of channel pointers
+ // of channels who need to send
+ // data or in-line command packets.
+ rwlock_t Bbuf_spinlock;
+ volatile
+ unsigned short i2Bbuf_strip; // Strip index
+ volatile
+ unsigned short i2Bbuf_stuff; // Stuff index
+ void *i2Bbuf[CH_QUEUE_SIZE]; // An array of channel pointers
+ // of channels who need to send
+ // bypass command packets.
+
+ /*
+ * A set of flags to indicate that certain events have occurred on at least
+ * one of the ports on this board. We use this to decide whether to spin
+ * through the channels looking for breaks, etc.
+ */
+ int got_input;
+ int status_change;
+ bidStat channelBtypes;
+
+ /*
+ * Debugging counters, etc.
+ */
+ unsigned long debugFlowQueued;
+ unsigned long debugInlineQueued;
+ unsigned long debugDataQueued;
+ unsigned long debugBypassQueued;
+ unsigned long debugFlowCount;
+ unsigned long debugInlineCount;
+ unsigned long debugBypassCount;
+
+ rwlock_t read_fifo_spinlock;
+ rwlock_t write_fifo_spinlock;
+
+// For queuing interrupt bottom half handlers. /\/\|=mhw=|\/\/
+ struct work_struct tqueue_interrupt;
+
+ struct timer_list SendPendingTimer; // Used by iiSendPending
+ unsigned int SendPendingRetry;
+} i2eBordStr, *i2eBordStrPtr;
+
+//-------------------------------------------------------------------
+// Macro Definitions for the indirect calls defined in the i2eBordStr
+//-------------------------------------------------------------------
+//
+#define iiDelay(a,b) (*(a)->i2eDelay)(b)
+#define iiWriteBuf(a,b,c) (*(a)->i2eWriteBuf)(a,b,c)
+#define iiReadBuf(a,b,c) (*(a)->i2eReadBuf)(a,b,c)
+
+#define iiWriteWord(a,b) (*(a)->i2eWriteWord)(a,b)
+#define iiReadWord(a) (*(a)->i2eReadWord)(a)
+
+#define iiWaitForTxEmpty(a,b) (*(a)->i2eWaitForTxEmpty)(a,b)
+
+#define iiTxMailEmpty(a) (*(a)->i2eTxMailEmpty)(a)
+#define iiTrySendMail(a,b) (*(a)->i2eTrySendMail)(a,b)
+
+#define iiGetMail(a) (*(a)->i2eGetMail)(a)
+#define iiEnableMailIrq(a) (*(a)->i2eEnableMailIrq)(a)
+#define iiDisableMailIrq(a) (*(a)->i2eWriteMask)(a,0)
+#define iiWriteMask(a,b) (*(a)->i2eWriteMask)(a,b)
+
+//-------------------------------------------
+// Manifests for i2eBordStr:
+//-------------------------------------------
+
+#define YES 1
+#define NO 0
+
+#define NULLFUNC (void (*)(void))0
+#define NULLPTR (void *)0
+
+typedef void (*delayFunc_t)(unsigned int);
+
+// i2eValid
+//
+#define I2E_MAGIC 0x4251 // Structure is valid.
+#define I2E_INCOMPLETE 0x1122 // Structure failed during init.
+
+
+// i2eError
+//
+#define I2EE_GOOD 0 // Operation successful
+#define I2EE_BADADDR 1 // Address out of range
+#define I2EE_BADSTATE 2 // Attempt to perform a function when the board
+ // structure was in the incorrect state
+#define I2EE_BADMAGIC 3 // Bad magic number from Power On test (i2ePomSize
+ // reflects what was read
+#define I2EE_PORM_SHORT 4 // Power On message too short
+#define I2EE_PORM_LONG 5 // Power On message too long
+#define I2EE_BAD_FAMILY 6 // Un-supported board family type
+#define I2EE_INCONSIST 7 // Firmware reports something impossible,
+ // e.g. unexpected number of ports... Almost no
+ // excuse other than bad FIFO...
+#define I2EE_POSTERR 8 // Power-On self test reported a bad error
+#define I2EE_BADBUS 9 // Unknown Bus type declared in message
+#define I2EE_TXE_TIME 10 // Timed out waiting for TX Fifo to empty
+#define I2EE_INVALID 11 // i2eValid field does not indicate a valid and
+ // complete board structure (for functions which
+ // require this be so.)
+#define I2EE_BAD_PORT 12 // Discrepancy between channels actually found and
+ // what the product is supposed to have. Check
+ // i2eGoodMap vs i2eChannelMap for details.
+#define I2EE_BAD_IRQ 13 // Someone specified an unsupported IRQ
+#define I2EE_NOCHANNELS 14 // No channel structures have been defined (for
+ // functions requiring this).
+
+// i2eFifoStyle
+//
+#define FIFO_II 0 /* IntelliPort-II style: see also i2hw.h */
+#define FIFO_IIEX 1 /* IntelliPort-IIEX style */
+
+// i2eGetMail
+//
+#define NO_MAIL_HERE 0x1111 // Since mail is unsigned char, cannot possibly
+ // promote to 0x1111.
+// i2eState
+//
+#define II_STATE_COLD 0 // Addresses have been defined, but board not even
+ // reset yet.
+#define II_STATE_RESET 1 // Board,if it exists, has just been reset
+#define II_STATE_READY 2 // Board ready for its first block
+#define II_STATE_LOADING 3 // Board continuing load
+#define II_STATE_LOADED 4 // Board has finished load: status ok
+#define II_STATE_BADLOAD 5 // Board has finished load: failed!
+#define II_STATE_STDLOADED 6 // Board has finished load: standard firmware
+
+// i2eUsingIrq
+//
+#define IRQ_UNDEFINED 0x1352 // No valid irq (or polling = 0) can ever
+ // promote to this!
+//------------------------------------------
+// Handy Macros for i2ellis.c and others
+// Note these are common to -II and -IIEX
+//------------------------------------------
+
+// Given a pointer to the board structure, does the input FIFO have any data or
+// not?
+//
+#define HAS_INPUT(pB) !(INB(pB->i2eStatus) & ST_IN_EMPTY)
+#define HAS_NO_INPUT(pB) (INB(pB->i2eStatus) & ST_IN_EMPTY)
+
+// Given a pointer to board structure, read a byte or word from the fifo
+//
+#define BYTE_FROM(pB) (unsigned char)INB(pB->i2eData)
+#define WORD_FROM(pB) (unsigned short)INW(pB->i2eData)
+
+// Given a pointer to board structure, is there room for any data to be written
+// to the data fifo?
+//
+#define HAS_OUTROOM(pB) !(INB(pB->i2eStatus) & ST_OUT_FULL)
+#define HAS_NO_OUTROOM(pB) (INB(pB->i2eStatus) & ST_OUT_FULL)
+
+// Given a pointer to board structure, write a single byte to the fifo
+// structure. Note that for 16-bit interfaces, the high order byte is undefined
+// and unknown.
+//
+#define BYTE_TO(pB, c) OUTB(pB->i2eData,(c))
+
+// Write a word to the fifo structure. For 8-bit interfaces, this may have
+// unknown results.
+//
+#define WORD_TO(pB, c) OUTW(pB->i2eData,(c))
+
+// Given a pointer to the board structure, is there anything in the incoming
+// mailbox?
+//
+#define HAS_MAIL(pB) (INB(pB->i2eStatus) & ST_IN_MAIL)
+
+#define UPDATE_FIFO_ROOM(pB) (pB)->i2eFifoRemains=(pB)->i2eFifoSize
+
+// Handy macro to round up a number (like the buffer write and read routines do)
+//
+#define ROUNDUP(number) (((number)+1) & (~1))
+
+//------------------------------------------
+// Function Declarations for i2ellis.c
+//------------------------------------------
+//
+// Functions called directly
+//
+// Initialization of a board & structure is in four (five!) parts:
+//
+// 0) iiEllisInit() - Initialize iiEllis subsystem.
+// 1) iiSetAddress() - Define the board address & delay function for a board.
+// 2) iiReset() - Reset the board (provided it exists)
+// -- Note you may do this to several boards --
+// 3) iiResetDelay() - Delay for 2 seconds (once for all boards)
+// 4) iiInitialize() - Attempt to read Power-up message; further initialize
+// accelerators
+//
+// Then you may use iiDownloadAll() or iiDownloadFile() (in i2file.c) to write
+// loadware. To change loadware, you must begin again with step 2, resetting
+// the board again (step 1 not needed).
+
+static void iiEllisInit(void);
+static int iiSetAddress(i2eBordStrPtr, int, delayFunc_t );
+static int iiReset(i2eBordStrPtr);
+static int iiResetDelay(i2eBordStrPtr);
+static int iiInitialize(i2eBordStrPtr);
+
+// Routine to validate that all channels expected are there.
+//
+extern int iiValidateChannels(i2eBordStrPtr);
+
+// Routine used to download a block of loadware.
+//
+static int iiDownloadBlock(i2eBordStrPtr, loadHdrStrPtr, int);
+
+// Return values given by iiDownloadBlock, iiDownloadAll, iiDownloadFile:
+//
+#define II_DOWN_BADVALID 0 // board structure is invalid
+#define II_DOWN_CONTINUING 1 // So far, so good, firmware expects more
+#define II_DOWN_GOOD 2 // Download complete, CRC good
+#define II_DOWN_BAD 3 // Download complete, but CRC bad
+#define II_DOWN_BADFILE 4 // Bad magic number in loadware file
+#define II_DOWN_BADSTATE 5 // Board is in an inappropriate state for
+ // downloading loadware. (see i2eState)
+#define II_DOWN_TIMEOUT 6 // Timeout waiting for firmware
+#define II_DOWN_OVER 7 // Too much data
+#define II_DOWN_UNDER 8 // Not enough data
+#define II_DOWN_NOFILE 9 // Loadware file not found
+
+// Routine to download an entire loadware module: Return values are a subset of
+// iiDownloadBlock's, excluding, of course, II_DOWN_CONTINUING
+//
+static int iiDownloadAll(i2eBordStrPtr, loadHdrStrPtr, int, int);
+
+// Called indirectly always. Needed externally so the routine might be
+// SPECIFIED as an argument to iiReset()
+//
+//static void ii2DelayIO(unsigned int); // N-millisecond delay using
+ //hardware spin
+//static void ii2DelayTimer(unsigned int); // N-millisecond delay using Linux
+ //timer
+
+// Many functions defined here return True if good, False otherwise, with an
+// error code in i2eError field. Here is a handy macro for setting the error
+// code and returning.
+//
+#define COMPLETE(pB,code) \
+ if(1){ \
+ pB->i2eError = code; \
+ return (code == I2EE_GOOD);\
+ }
+
+#endif // I2ELLIS_H
diff --git a/drivers/char/ip2/i2hw.h b/drivers/char/ip2/i2hw.h
new file mode 100644
index 0000000..15fe04e
--- /dev/null
+++ b/drivers/char/ip2/i2hw.h
@@ -0,0 +1,648 @@
+/*******************************************************************************
+*
+* (c) 1999 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Definitions limited to properties of the hardware or the
+* bootstrap firmware. As such, they are applicable regardless of
+* operating system or loadware (standard or diagnostic).
+*
+*******************************************************************************/
+#ifndef I2HW_H
+#define I2HW_H 1
+//------------------------------------------------------------------------------
+// Revision History:
+//
+// 23 September 1991 MAG First Draft Started...through...
+// 11 October 1991 ... Continuing development...
+// 6 August 1993 Added support for ISA-4 (asic) which is architected
+// as an ISA-CEX with a single 4-port box.
+//
+// 20 December 1996 AKM Version for Linux
+//
+//------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+
+HARDWARE DESCRIPTION:
+
+Introduction:
+
+The IntelliPort-II and IntelliPort-IIEX products occupy a block of eight (8)
+addresses in the host's I/O space.
+
+Some addresses are used to transfer data to/from the board, some to transfer
+so-called "mailbox" messages, and some to read bit-mapped status information.
+While all the products in the line are functionally similar, some use a 16-bit
+data path to transfer data while others use an 8-bit path. Also, the use of
+command /status/mailbox registers differs slightly between the II and IIEX
+branches of the family.
+
+The host determines what type of board it is dealing with by reading a string of
+sixteen characters from the board. These characters are always placed in the
+fifo by the board's local processor whenever the board is reset (either from
+power-on or under software control) and are known as the "Power-on Reset
+Message." In order that this message can be read from either type of board, the
+hardware registers used in reading this message are the same. Once this message
+has been read by the host, then it has the information required to operate.
+
+General Differences between boards:
+
+The greatest structural difference is between the -II and -IIEX families of
+product. The -II boards use the Am4701 dual 512x8 bidirectional fifo to support
+the data path, mailbox registers, and status registers. This chip contains some
+features which are not used in the IntelliPort-II products; a description of
+these is omitted here. Because of these many features, it contains many
+registers, too many to access directly within a small address space. They are
+accessed by first writing a value to a "pointer" register. This value selects
+the register to be accessed. The next read or write to that address accesses
+the selected register rather than the pointer register.
+
+The -IIEX boards use a proprietary design similar to the Am4701 in function. But
+because of a simpler, more streamlined design it doesn't require so many
+registers. This means they can be accessed directly in single operations rather
+than through a pointer register.
+
+Besides these differences, there are differences in whether 8-bit or 16-bit
+transfers are used to move data to the board.
+
+The -II boards are capable only of 8-bit data transfers, while the -IIEX boards
+may be configured for either 8-bit or 16-bit data transfers. If the on-board DIP
+switch #8 is ON, and the card has been installed in a 16-bit slot, 16-bit
+transfers are supported (and will be expected by the standard loadware). The
+on-board firmware can determine the position of the switch, and whether the
+board is installed in a 16-bit slot; it supplies this information to the host as
+part of the power-up reset message.
+
+The configuration switch (#8) and slot selection do not directly configure the
+hardware. It is up to the on-board loadware and host-based drivers to act
+according to the selected options. That is, loadware and drivers could be
+written to perform 8-bit transfers regardless of the state of the DIP switch or
+slot (and in a diagnostic environment might well do so). Likewise, 16-bit
+transfers could be performed as long as the card is in a 16-bit slot.
+
+Note the slot selection and DIP switch selection are provided separately: a
+board running in 8-bit mode in a 16-bit slot has a greater range of possible
+interrupts to choose from; information of potential use to the host.
+
+All 8-bit data transfers are done in the same way, regardless of whether on a
+-II board or a -IIEX board.
+
+The host must consider two things then: 1) whether a -II or -IIEX product is
+being used, and 2) whether an 8-bit or 16-bit data path is used.
+
+A further difference is that -II boards always have a 512-byte fifo operating in
+each direction. -IIEX boards may use fifos of varying size; this size is
+reported as part of the power-up message.
+
+I/O Map Of IntelliPort-II and IntelliPort-IIEX boards:
+(Relative to the chosen base address)
+
+Addr R/W IntelliPort-II IntelliPort-IIEX
+---- --- -------------- ----------------
+0 R/W Data Port (byte) Data Port (byte or word)
+1 R/W (Not used) (MSB of word-wide data written to Data Port)
+2 R Status Register Status Register
+2 W Pointer Register Interrupt Mask Register
+3 R/W (Not used) Mailbox Registers (6 bits: 11111100)
+4,5 -- Reserved for future products
+6 -- Reserved for future products
+7 R Guaranteed to have no effect
+7 W Hardware reset of board.
+
+
+Rules:
+All data transfers are performed using the even i/o address. If byte-wide data
+transfers are being used, do INB/OUTB operations on the data port. If word-wide
+transfers are used, do INW/OUTW operations. In some circumstances (such as
+reading the power-up message) you will do INB from the data port, but in this
+case the MSB of each word read is lost. When accessing all other unreserved
+registers, use byte operations only.
+------------------------------------------------------------------------------*/
+
+//------------------------------------------------
+// Mandatory Includes:
+//------------------------------------------------
+//
+#include "ip2types.h"
+#include "i2os.h" /* For any o.s., compiler, or host-related issues */
+
+//-------------------------------------------------------------------------
+// Manifests for the I/O map:
+//-------------------------------------------------------------------------
+// R/W: Data port (byte) for IntelliPort-II,
+// R/W: Data port (byte or word) for IntelliPort-IIEX
+// Incoming or outgoing data passes through a FIFO, the status of which is
+// available in some of the bits in FIFO_STATUS. This (bidirectional) FIFO is
+// the primary means of transferring data, commands, flow-control, and status
+// information between the host and board.
+//
+#define FIFO_DATA 0
+
+// Another way of passing information between the board and the host is
+// through "mailboxes". Unlike a FIFO, a mailbox holds only a single byte of
+// data. Writing data to the mailbox causes a status bit to be set, and
+// potentially interrupting the intended receiver. The sender has some way to
+// determine whether the data has been read yet; as soon as it has, it may send
+// more. The mailboxes are handled differently on -II and -IIEX products, as
+// suggested below.
+//------------------------------------------------------------------------------
+// Read: Status Register for IntelliPort-II or -IIEX
+// The presence of any bit set here will cause an interrupt to the host,
+// provided the corresponding bit has been unmasked in the interrupt mask
+// register. Furthermore, interrupts to the host are disabled globally until the
+// loadware selects the irq line to use. With the exception of STN_MR, the bits
+// remain set so long as the associated condition is true.
+//
+#define FIFO_STATUS 2
+
+// Bit map of status bits which are identical for -II and -IIEX
+//
+#define ST_OUT_FULL 0x40 // Outbound FIFO full
+#define ST_IN_EMPTY 0x20 // Inbound FIFO empty
+#define ST_IN_MAIL 0x04 // Inbound Mailbox full
+
+// The following exists only on the Intelliport-IIEX, and indicates that the
+// board has not read the last outgoing mailbox data yet. In the IntelliPort-II,
+// the outgoing mailbox may be read back: a zero indicates the board has read
+// the data.
+//
+#define STE_OUT_MAIL 0x80 // Outbound mailbox full (!)
+
+// The following bits are defined differently for -II and -IIEX boards. Code
+// which relies on these bits will need to be functionally different for the two
+// types of boards and should be generally avoided because of the additional
+// complexity this creates:
+
+// Bit map of status bits only on -II
+
+// Fifo has been RESET (cleared when the status register is read). Note that
+// this condition cannot be masked and would always interrupt the host, except
+// that the hardware reset also disables interrupts globally from the board
+// until re-enabled by loadware. This could also arise from the
+// Am4701-supported command to reset the chip, but this command is generally not
+// used here.
+//
+#define STN_MR 0x80
+
+// See the AMD Am4701 data sheet for details on the following four bits. They
+// are not presently used by Computone drivers.
+//
+#define STN_OUT_AF 0x10 // Outbound FIFO almost full (programmable)
+#define STN_IN_AE 0x08 // Inbound FIFO almost empty (programmable)
+#define STN_BD 0x02 // Inbound byte detected
+#define STN_PE 0x01 // Parity/Framing condition detected
+
+// Bit-map of status bits only on -IIEX
+//
+#define STE_OUT_HF 0x10 // Outbound FIFO half full
+#define STE_IN_HF 0x08 // Inbound FIFO half full
+#define STE_IN_FULL 0x02 // Inbound FIFO full
+#define STE_OUT_MT 0x01 // Outbound FIFO empty
+
+//------------------------------------------------------------------------------
+
+// Intelliport-II -- Write Only: the pointer register.
+// Values are written to this register to select the Am4701 internal register to
+// be accessed on the next operation.
+//
+#define FIFO_PTR 0x02
+
+// Values for the pointer register
+//
+#define SEL_COMMAND 0x1 // Selects the Am4701 command register
+
+// Some possible commands:
+//
+#define SEL_CMD_MR 0x80 // Am4701 command to reset the chip
+#define SEL_CMD_SH 0x40 // Am4701 command to map the "other" port into the
+ // status register.
+#define SEL_CMD_UNSH 0 // Am4701 command to "unshift": port maps into its
+ // own status register.
+#define SEL_MASK 0x2 // Selects the Am4701 interrupt mask register. The
+ // interrupt mask register is bit-mapped to match
+ // the status register (FIFO_STATUS) except for
+ // STN_MR. (See above.)
+#define SEL_BYTE_DET 0x3 // Selects the Am4701 byte-detect register. (Not
+ // normally used except in diagnostics.)
+#define SEL_OUTMAIL 0x4 // Selects the outbound mailbox (R/W). Reading back
+ // a value of zero indicates that the mailbox has
+ // been read by the board and is available for more
+ // data./ Writing to the mailbox optionally
+ // interrupts the board, depending on the loadware's
+ // setting of its interrupt mask register.
+#define SEL_AEAF 0x5 // Selects AE/AF threshold register.
+#define SEL_INMAIL 0x6 // Selects the inbound mailbox (Read)
+
+//------------------------------------------------------------------------------
+// IntelliPort-IIEX -- Write Only: interrupt mask (and misc flags) register:
+// Unlike IntelliPort-II, bit assignments do NOT match those of the status
+// register.
+//
+#define FIFO_MASK 0x2
+
+// Mailbox readback select:
+// If set, reads to FIFO_MAIL will read the OUTBOUND mailbox (host to board). If
+// clear (default on reset) reads to FIFO_MAIL will read the INBOUND mailbox.
+// This is the normal situation. The clearing of a mailbox is determined on
+// -IIEX boards by waiting for the STE_OUT_MAIL bit to clear. Readback
+// capability is provided for diagnostic purposes only.
+//
+#define MX_OUTMAIL_RSEL 0x80
+
+#define MX_IN_MAIL 0x40 // Enables interrupts when incoming mailbox goes
+ // full (ST_IN_MAIL set).
+#define MX_IN_FULL 0x20 // Enables interrupts when incoming FIFO goes full
+ // (STE_IN_FULL).
+#define MX_IN_MT 0x08 // Enables interrupts when incoming FIFO goes empty
+ // (ST_IN_MT).
+#define MX_OUT_FULL 0x04 // Enables interrupts when outgoing FIFO goes full
+ // (ST_OUT_FULL).
+#define MX_OUT_MT 0x01 // Enables interrupts when outgoing FIFO goes empty
+ // (STE_OUT_MT).
+
+// Any remaining bits are reserved, and should be written to ZERO for
+// compatibility with future Computone products.
+
+//------------------------------------------------------------------------------
+// IntelliPort-IIEX: -- These are only 6-bit mailboxes !!! -- 11111100 (low two
+// bits always read back 0).
+// Read: One of the mailboxes, usually Inbound.
+// Inbound Mailbox (MX_OUTMAIL_RSEL = 0)
+// Outbound Mailbox (MX_OUTMAIL_RSEL = 1)
+// Write: Outbound Mailbox
+// For the IntelliPort-II boards, the outbound mailbox is read back to determine
+// whether the board has read the data (0 --> data has been read). For the
+// IntelliPort-IIEX, this is done by reading a status register. To determine
+// whether mailbox is available for more outbound data, use the STE_OUT_MAIL bit
+// in FIFO_STATUS. Moreover, although the Outbound Mailbox can be read back by
+// setting MX_OUTMAIL_RSEL, it is NOT cleared when the board reads it, as is the
+// case with the -II boards. For this reason, FIFO_MAIL is normally used to read
+// the inbound FIFO, and MX_OUTMAIL_RSEL kept clear. (See above for
+// MX_OUTMAIL_RSEL description.)
+//
+#define FIFO_MAIL 0x3
+
+//------------------------------------------------------------------------------
+// WRITE ONLY: Resets the board. (Data doesn't matter).
+//
+#define FIFO_RESET 0x7
+
+//------------------------------------------------------------------------------
+// READ ONLY: Will have no effect. (Data is undefined.)
+// Actually, there will be an effect, in that the operation is sure to generate
+// a bus cycle: viz., an I/O byte Read. This fact can be used to enforce short
+// delays when no comparable time constant is available.
+//
+#define FIFO_NOP 0x7
+
+//------------------------------------------------------------------------------
+// RESET & POWER-ON RESET MESSAGE
+/*------------------------------------------------------------------------------
+RESET:
+
+The IntelliPort-II and -IIEX boards are reset in three ways: Power-up, channel
+reset, and via a write to the reset register described above. For products using
+the ISA bus, these three sources of reset are equvalent. For MCA and EISA buses,
+the Power-up and channel reset sources cause additional hardware initialization
+which should only occur at system startup time.
+
+The third type of reset, called a "command reset", is done by writing any data
+to the FIFO_RESET address described above. This resets the on-board processor,
+FIFO, UARTS, and associated hardware.
+
+This passes control of the board to the bootstrap firmware, which performs a
+Power-On Self Test and which detects its current configuration. For example,
+-IIEX products determine the size of FIFO which has been installed, and the
+number and type of expansion boxes attached.
+
+This and other information is then written to the FIFO in a 16-byte data block
+to be read by the host. This block is guaranteed to be present within two (2)
+seconds of having received the command reset. The firmware is now ready to
+receive loadware from the host.
+
+It is good practice to perform a command reset to the board explicitly as part
+of your software initialization. This allows your code to properly restart from
+a soft boot. (Many systems do not issue channel reset on soft boot).
+
+Because of a hardware reset problem on some of the Cirrus Logic 1400's which are
+used on the product, it is recommended that you reset the board twice, separated
+by an approximately 50 milliseconds delay. (VERY approximately: probably ok to
+be off by a factor of five. The important point is that the first command reset
+in fact generates a reset pulse on the board. This pulse is guaranteed to last
+less than 10 milliseconds. The additional delay ensures the 1400 has had the
+chance to respond sufficiently to the first reset. Why not a longer delay? Much
+more than 50 milliseconds gets to be noticable, but the board would still work.
+
+Once all 16 bytes of the Power-on Reset Message have been read, the bootstrap
+firmware is ready to receive loadware.
+
+Note on Power-on Reset Message format:
+The various fields have been designed with future expansion in view.
+Combinations of bitfields and values have been defined which define products
+which may not currently exist. This has been done to allow drivers to anticipate
+the possible introduction of products in a systematic fashion. This is not
+intended to suggest that each potential product is actually under consideration.
+------------------------------------------------------------------------------*/
+
+//----------------------------------------
+// Format of Power-on Reset Message
+//----------------------------------------
+
+typedef union _porStr // "por" stands for Power On Reset
+{
+ unsigned char c[16]; // array used when considering the message as a
+ // string of undifferentiated characters
+
+ struct // Elements used when considering values
+ {
+ // The first two bytes out of the FIFO are two magic numbers. These are
+ // intended to establish that there is indeed a member of the
+ // IntelliPort-II(EX) family present. The remaining bytes may be
+ // expected // to be valid. When reading the Power-on Reset message,
+ // if the magic numbers do not match it is probably best to stop
+ // reading immediately. You are certainly not reading our board (unless
+ // hardware is faulty), and may in fact be reading some other piece of
+ // hardware.
+
+ unsigned char porMagic1; // magic number: first byte == POR_MAGIC_1
+ unsigned char porMagic2; // magic number: second byte == POR_MAGIC_2
+
+ // The Version, Revision, and Subrevision are stored as absolute numbers
+ // and would normally be displayed in the format V.R.S (e.g. 1.0.2)
+
+ unsigned char porVersion; // Bootstrap firmware version number
+ unsigned char porRevision; // Bootstrap firmware revision number
+ unsigned char porSubRev; // Bootstrap firmware sub-revision number
+
+ unsigned char porID; // Product ID: Bit-mapped according to
+ // conventions described below. Among other
+ // things, this allows us to distinguish
+ // IntelliPort-II boards from IntelliPort-IIEX
+ // boards.
+
+ unsigned char porBus; // IntelliPort-II: Unused
+ // IntelliPort-IIEX: Bus Information:
+ // Bit-mapped below
+
+ unsigned char porMemory; // On-board DRAM size: in 32k blocks
+
+ // porPorts1 (and porPorts2) are used to determine the ports which are
+ // available to the board. For non-expandable product, a single number
+ // is sufficient. For expandable product, the board may be connected
+ // to as many as four boxes. Each box may be (so far) either a 16-port
+ // or an 8-port size. Whenever an 8-port box is used, the remaining 8
+ // ports leave gaps between existing channels. For that reason,
+ // expandable products must report a MAP of available channels. Since
+ // each UART supports four ports, we represent each UART found by a
+ // single bit. Using two bytes to supply the mapping information we
+ // report the presense or absense of up to 16 UARTS, or 64 ports in
+ // steps of 4 ports. For -IIEX products, the ports are numbered
+ // starting at the box closest to the controller in the "chain".
+
+ // Interpreted Differently for IntelliPort-II and -IIEX.
+ // -II: Number of ports (Derived actually from product ID). See
+ // Diag1&2 to indicate if uart was actually detected.
+ // -IIEX: Bit-map of UARTS found, LSB (see below for MSB of this). This
+ // bitmap is based on detecting the uarts themselves;
+ // see porFlags for information from the box i.d's.
+ unsigned char porPorts1;
+
+ unsigned char porDiag1; // Results of on-board P.O.S.T, 1st byte
+ unsigned char porDiag2; // Results of on-board P.O.S.T, 2nd byte
+ unsigned char porSpeed; // Speed of local CPU: given as MHz x10
+ // e.g., 16.0 MHz CPU is reported as 160
+ unsigned char porFlags; // Misc information (see manifests below)
+ // Bit-mapped: CPU type, UART's present
+
+ unsigned char porPorts2; // -II: Undefined
+ // -IIEX: Bit-map of UARTS found, MSB (see
+ // above for LSB)
+
+ // IntelliPort-II: undefined
+ // IntelliPort-IIEX: 1 << porFifoSize gives the size, in bytes, of the
+ // host interface FIFO, in each direction. When running the -IIEX in
+ // 8-bit mode, fifo capacity is halved. The bootstrap firmware will
+ // have already accounted for this fact in generating this number.
+ unsigned char porFifoSize;
+
+ // IntelliPort-II: undefined
+ // IntelliPort-IIEX: The number of boxes connected. (Presently 1-4)
+ unsigned char porNumBoxes;
+ } e;
+} porStr, *porStrPtr;
+
+//--------------------------
+// Values for porStr fields
+//--------------------------
+
+//---------------------
+// porMagic1, porMagic2
+//----------------------
+//
+#define POR_MAGIC_1 0x96 // The only valid value for porMagic1
+#define POR_MAGIC_2 0x35 // The only valid value for porMagic2
+#define POR_1_INDEX 0 // Byte position of POR_MAGIC_1
+#define POR_2_INDEX 1 // Ditto for POR_MAGIC_2
+
+//----------------------
+// porID
+//----------------------
+//
+#define POR_ID_FAMILY 0xc0 // These bits indicate the general family of
+ // product.
+#define POR_ID_FII 0x00 // Family is "IntelliPort-II"
+#define POR_ID_FIIEX 0x40 // Family is "IntelliPort-IIEX"
+
+// These bits are reserved, presently zero. May be used at a later date to
+// convey other product information.
+//
+#define POR_ID_RESERVED 0x3c
+
+#define POR_ID_SIZE 0x03 // Remaining bits indicate number of ports &
+ // Connector information.
+#define POR_ID_II_8 0x00 // For IntelliPort-II, indicates 8-port using
+ // standard brick.
+#define POR_ID_II_8R 0x01 // For IntelliPort-II, indicates 8-port using
+ // RJ11's (no CTS)
+#define POR_ID_II_6 0x02 // For IntelliPort-II, indicates 6-port using
+ // RJ45's
+#define POR_ID_II_4 0x03 // For IntelliPort-II, indicates 4-port using
+ // 4xRJ45 connectors
+#define POR_ID_EX 0x00 // For IntelliPort-IIEX, indicates standard
+ // expandable controller (other values reserved)
+
+//----------------------
+// porBus
+//----------------------
+
+// IntelliPort-IIEX only: Board is installed in a 16-bit slot
+//
+#define POR_BUS_SLOT16 0x20
+
+// IntelliPort-IIEX only: DIP switch #8 is on, selecting 16-bit host interface
+// operation.
+//
+#define POR_BUS_DIP16 0x10
+
+// Bits 0-2 indicate type of bus: This information is stored in the bootstrap
+// loadware, different loadware being used on different products for different
+// buses. For most situations, the drivers do not need this information; but it
+// is handy in a diagnostic environment. For example, on microchannel boards,
+// you would not want to try to test several interrupts, only the one for which
+// you were configured.
+//
+#define POR_BUS_TYPE 0x07
+
+// Unknown: this product doesn't know what bus it is running in. (e.g. if same
+// bootstrap firmware were wanted for two different buses.)
+//
+#define POR_BUS_T_UNK 0
+
+// Note: existing firmware for ISA-8 and MC-8 currently report the POR_BUS_T_UNK
+// state, since the same bootstrap firmware is used for each.
+
+#define POR_BUS_T_MCA 1 // MCA BUS */
+#define POR_BUS_T_EISA 2 // EISA BUS */
+#define POR_BUS_T_ISA 3 // ISA BUS */
+
+// Values 4-7 Reserved
+
+// Remaining bits are reserved
+
+//----------------------
+// porDiag1
+//----------------------
+
+#define POR_BAD_MAPPER 0x80 // HW failure on P.O.S.T: Chip mapper failed
+
+// These two bits valid only for the IntelliPort-II
+//
+#define POR_BAD_UART1 0x01 // First 1400 bad
+#define POR_BAD_UART2 0x02 // Second 1400 bad
+
+//----------------------
+// porDiag2
+//----------------------
+
+#define POR_DEBUG_PORT 0x80 // debug port was detected by the P.O.S.T
+#define POR_DIAG_OK 0x00 // Indicates passage: Failure codes not yet
+ // available.
+ // Other bits undefined.
+//----------------------
+// porFlags
+//----------------------
+
+#define POR_CPU 0x03 // These bits indicate supposed CPU type
+#define POR_CPU_8 0x01 // Board uses an 80188 (no such thing yet)
+#define POR_CPU_6 0x02 // Board uses an 80186 (all existing products)
+#define POR_CEX4 0x04 // If set, this is an ISA-CEX/4: An ISA-4 (asic)
+ // which is architected like an ISA-CEX connected
+ // to a (hitherto impossible) 4-port box.
+#define POR_BOXES 0xf0 // Valid for IntelliPort-IIEX only: Map of Box
+ // sizes based on box I.D.
+#define POR_BOX_16 0x10 // Set indicates 16-port, clear 8-port
+
+//-------------------------------------
+// LOADWARE and DOWNLOADING CODE
+//-------------------------------------
+
+/*
+Loadware may be sent to the board in two ways:
+1) It may be read from a (binary image) data file block by block as each block
+ is sent to the board. This is only possible when the initialization is
+ performed by code which can access your file system. This is most suitable
+ for diagnostics and appications which use the interface library directly.
+
+2) It may be hard-coded into your source by including a .h file (typically
+ supplied by Computone), which declares a data array and initializes every
+ element. This acheives the same result as if an entire loadware file had
+ been read into the array.
+
+ This requires more data space in your program, but access to the file system
+ is not required. This method is more suited to driver code, which typically
+ is running at a level too low to access the file system directly.
+
+At present, loadware can only be generated at Computone.
+
+All Loadware begins with a header area which has a particular format. This
+includes a magic number which identifies the file as being (purportedly)
+loadware, CRC (for the loader), and version information.
+*/
+
+
+//-----------------------------------------------------------------------------
+// Format of loadware block
+//
+// This is defined as a union so we can pass a pointer to one of these items
+// and (if it is the first block) pick out the version information, etc.
+//
+// Otherwise, to deal with this as a simple character array
+//------------------------------------------------------------------------------
+
+#define LOADWARE_BLOCK_SIZE 512 // Number of bytes in each block of loadware
+
+typedef union _loadHdrStr
+{
+ unsigned char c[LOADWARE_BLOCK_SIZE]; // Valid for every block
+
+ struct // These fields are valid for only the first block of loadware.
+ {
+ unsigned char loadMagic; // Magic number: see below
+ unsigned char loadBlocksMore; // How many more blocks?
+ unsigned char loadCRC[2]; // Two CRC bytes: used by loader
+ unsigned char loadVersion; // Version number
+ unsigned char loadRevision; // Revision number
+ unsigned char loadSubRevision; // Sub-revision number
+ unsigned char loadSpares[9]; // Presently unused
+ unsigned char loadDates[32]; // Null-terminated string which can give
+ // date and time of compilation
+ } e;
+} loadHdrStr, *loadHdrStrPtr;
+
+//------------------------------------
+// Defines for downloading code:
+//------------------------------------
+
+// The loadMagic field in the first block of the loadfile must be this, else the
+// file is not valid.
+//
+#define MAGIC_LOADFILE 0x3c
+
+// How do we know the load was successful? On completion of the load, the
+// bootstrap firmware returns a code to indicate whether it thought the download
+// was valid and intends to execute it. These are the only possible valid codes:
+//
+#define LOADWARE_OK 0xc3 // Download was ok
+#define LOADWARE_BAD 0x5a // Download was bad (CRC error)
+
+// Constants applicable to writing blocks of loadware:
+// The first block of loadware might take 600 mS to load, in extreme cases.
+// (Expandable board: worst case for sending startup messages to the LCD's).
+// The 600mS figure is not really a calculation, but a conservative
+// guess/guarantee. Usually this will be within 100 mS, like subsequent blocks.
+//
+#define MAX_DLOAD_START_TIME 1000 // 1000 mS
+#define MAX_DLOAD_READ_TIME 100 // 100 mS
+
+// Firmware should respond with status (see above) within this long of host
+// having sent the final block.
+//
+#define MAX_DLOAD_ACK_TIME 100 // 100 mS, again!
+
+//------------------------------------------------------
+// MAXIMUM NUMBER OF PORTS PER BOARD:
+// This is fixed for now (with the expandable), but may
+// be expanding according to even newer products.
+//------------------------------------------------------
+//
+#define ABS_MAX_BOXES 4 // Absolute most boxes per board
+#define ABS_BIGGEST_BOX 16 // Absolute the most ports per box
+#define ABS_MOST_PORTS (ABS_MAX_BOXES * ABS_BIGGEST_BOX)
+
+#endif // I2HW_H
+
diff --git a/drivers/char/ip2/i2lib.c b/drivers/char/ip2/i2lib.c
new file mode 100644
index 0000000..82c5f30
--- /dev/null
+++ b/drivers/char/ip2/i2lib.c
@@ -0,0 +1,2219 @@
+/*******************************************************************************
+*
+* (c) 1999 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: High-level interface code for the device driver. Uses the
+* Extremely Low Level Interface Support (i2ellis.c). Provides an
+* interface to the standard loadware, to support drivers or
+* application code. (This is included source code, not a separate
+* compilation module.)
+*
+*******************************************************************************/
+//------------------------------------------------------------------------------
+// Note on Strategy:
+// Once the board has been initialized, it will interrupt us when:
+// 1) It has something in the fifo for us to read (incoming data, flow control
+// packets, or whatever).
+// 2) It has stripped whatever we have sent last time in the FIFO (and
+// consequently is ready for more).
+//
+// Note also that the buffer sizes declared in i2lib.h are VERY SMALL. This
+// worsens performance considerably, but is done so that a great many channels
+// might use only a little memory.
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Revision History:
+//
+// 0.00 - 4/16/91 --- First Draft
+// 0.01 - 4/29/91 --- 1st beta release
+// 0.02 - 6/14/91 --- Changes to allow small model compilation
+// 0.03 - 6/17/91 MAG Break reporting protected from interrupts routines with
+// in-line asm added for moving data to/from ring buffers,
+// replacing a variety of methods used previously.
+// 0.04 - 6/21/91 MAG Initial flow-control packets not queued until
+// i2_enable_interrupts time. Former versions would enqueue
+// them at i2_init_channel time, before we knew how many
+// channels were supposed to exist!
+// 0.05 - 10/12/91 MAG Major changes: works through the ellis.c routines now;
+// supports new 16-bit protocol and expandable boards.
+// - 10/24/91 MAG Most changes in place and stable.
+// 0.06 - 2/20/92 MAG Format of CMD_HOTACK corrected: the command takes no
+// argument.
+// 0.07 -- 3/11/92 MAG Support added to store special packet types at interrupt
+// level (mostly responses to specific commands.)
+// 0.08 -- 3/30/92 MAG Support added for STAT_MODEM packet
+// 0.09 -- 6/24/93 MAG i2Link... needed to update number of boards BEFORE
+// turning on the interrupt.
+// 0.10 -- 6/25/93 MAG To avoid gruesome death from a bad board, we sanity check
+// some incoming.
+//
+// 1.1 - 12/25/96 AKM Linux version.
+// - 10/09/98 DMC Revised Linux version.
+//------------------------------------------------------------------------------
+
+//************
+//* Includes *
+//************
+
+#include <linux/sched.h>
+#include "i2lib.h"
+
+
+//***********************
+//* Function Prototypes *
+//***********************
+static void i2QueueNeeds(i2eBordStrPtr, i2ChanStrPtr, int);
+static i2ChanStrPtr i2DeQueueNeeds(i2eBordStrPtr, int );
+static void i2StripFifo(i2eBordStrPtr);
+static void i2StuffFifoBypass(i2eBordStrPtr);
+static void i2StuffFifoFlow(i2eBordStrPtr);
+static void i2StuffFifoInline(i2eBordStrPtr);
+static int i2RetryFlushOutput(i2ChanStrPtr);
+
+// Not a documented part of the library routines (careful...) but the Diagnostic
+// i2diag.c finds them useful to help the throughput in certain limited
+// single-threaded operations.
+static void iiSendPendingMail(i2eBordStrPtr);
+static void serviceOutgoingFifo(i2eBordStrPtr);
+
+// Functions defined in ip2.c as part of interrupt handling
+static void do_input(void *);
+static void do_status(void *);
+
+//***************
+//* Debug Data *
+//***************
+#ifdef DEBUG_FIFO
+
+unsigned char DBGBuf[0x4000];
+unsigned short I = 0;
+
+static void
+WriteDBGBuf(char *s, unsigned char *src, unsigned short n )
+{
+ char *p = src;
+
+ // XXX: We need a spin lock here if we ever use this again
+
+ while (*s) { // copy label
+ DBGBuf[I] = *s++;
+ I = I++ & 0x3fff;
+ }
+ while (n--) { // copy data
+ DBGBuf[I] = *p++;
+ I = I++ & 0x3fff;
+ }
+}
+
+static void
+fatality(i2eBordStrPtr pB )
+{
+ int i;
+
+ for (i=0;i<sizeof(DBGBuf);i++) {
+ if ((i%16) == 0)
+ printk("\n%4x:",i);
+ printk("%02x ",DBGBuf[i]);
+ }
+ printk("\n");
+ for (i=0;i<sizeof(DBGBuf);i++) {
+ if ((i%16) == 0)
+ printk("\n%4x:",i);
+ if (DBGBuf[i] >= ' ' && DBGBuf[i] <= '~') {
+ printk(" %c ",DBGBuf[i]);
+ } else {
+ printk(" . ");
+ }
+ }
+ printk("\n");
+ printk("Last index %x\n",I);
+}
+#endif /* DEBUG_FIFO */
+
+//********
+//* Code *
+//********
+
+static inline int
+i2Validate ( i2ChanStrPtr pCh )
+{
+ //ip2trace(pCh->port_index, ITRC_VERIFY,ITRC_ENTER,2,pCh->validity,
+ // (CHANNEL_MAGIC | CHANNEL_SUPPORT));
+ return ((pCh->validity & (CHANNEL_MAGIC_BITS | CHANNEL_SUPPORT))
+ == (CHANNEL_MAGIC | CHANNEL_SUPPORT));
+}
+
+//******************************************************************************
+// Function: iiSendPendingMail(pB)
+// Parameters: Pointer to a board structure
+// Returns: Nothing
+//
+// Description:
+// If any outgoing mail bits are set and there is outgoing mailbox is empty,
+// send the mail and clear the bits.
+//******************************************************************************
+static inline void
+iiSendPendingMail(i2eBordStrPtr pB)
+{
+ if (pB->i2eOutMailWaiting && (!pB->i2eWaitingForEmptyFifo) )
+ {
+ if (iiTrySendMail(pB, pB->i2eOutMailWaiting))
+ {
+ /* If we were already waiting for fifo to empty,
+ * or just sent MB_OUT_STUFFED, then we are
+ * still waiting for it to empty, until we should
+ * receive an MB_IN_STRIPPED from the board.
+ */
+ pB->i2eWaitingForEmptyFifo |=
+ (pB->i2eOutMailWaiting & MB_OUT_STUFFED);
+ pB->i2eOutMailWaiting = 0;
+ pB->SendPendingRetry = 0;
+ } else {
+/* The only time we hit this area is when "iiTrySendMail" has
+ failed. That only occurs when the outbound mailbox is
+ still busy with the last message. We take a short breather
+ to let the board catch up with itself and then try again.
+ 16 Retries is the limit - then we got a borked board.
+ /\/\|=mhw=|\/\/ */
+
+ if( ++pB->SendPendingRetry < 16 ) {
+
+ init_timer( &(pB->SendPendingTimer) );
+ pB->SendPendingTimer.expires = jiffies + 1;
+ pB->SendPendingTimer.function = (void*)(unsigned long)iiSendPendingMail;
+ pB->SendPendingTimer.data = (unsigned long)pB;
+ add_timer( &(pB->SendPendingTimer) );
+ } else {
+ printk( KERN_ERR "IP2: iiSendPendingMail unable to queue outbound mail\n" );
+ }
+ }
+ }
+}
+
+//******************************************************************************
+// Function: i2InitChannels(pB, nChannels, pCh)
+// Parameters: Pointer to Ellis Board structure
+// Number of channels to initialize
+// Pointer to first element in an array of channel structures
+// Returns: Success or failure
+//
+// Description:
+//
+// This function patches pointers, back-pointers, and initializes all the
+// elements in the channel structure array.
+//
+// This should be run after the board structure is initialized, through having
+// loaded the standard loadware (otherwise it complains).
+//
+// In any case, it must be done before any serious work begins initializing the
+// irq's or sending commands...
+//
+//******************************************************************************
+static int
+i2InitChannels ( i2eBordStrPtr pB, int nChannels, i2ChanStrPtr pCh)
+{
+ int index, stuffIndex;
+ i2ChanStrPtr *ppCh;
+
+ if (pB->i2eValid != I2E_MAGIC) {
+ COMPLETE(pB, I2EE_BADMAGIC);
+ }
+ if (pB->i2eState != II_STATE_STDLOADED) {
+ COMPLETE(pB, I2EE_BADSTATE);
+ }
+
+ LOCK_INIT(&pB->read_fifo_spinlock);
+ LOCK_INIT(&pB->write_fifo_spinlock);
+ LOCK_INIT(&pB->Dbuf_spinlock);
+ LOCK_INIT(&pB->Bbuf_spinlock);
+ LOCK_INIT(&pB->Fbuf_spinlock);
+
+ // NO LOCK needed yet - this is init
+
+ pB->i2eChannelPtr = pCh;
+ pB->i2eChannelCnt = nChannels;
+
+ pB->i2Fbuf_strip = pB->i2Fbuf_stuff = 0;
+ pB->i2Dbuf_strip = pB->i2Dbuf_stuff = 0;
+ pB->i2Bbuf_strip = pB->i2Bbuf_stuff = 0;
+
+ pB->SendPendingRetry = 0;
+
+ memset ( pCh, 0, sizeof (i2ChanStr) * nChannels );
+
+ for (index = stuffIndex = 0, ppCh = (i2ChanStrPtr *)(pB->i2Fbuf);
+ nChannels && index < ABS_MOST_PORTS;
+ index++)
+ {
+ if ( !(pB->i2eChannelMap[index >> 4] & (1 << (index & 0xf)) ) ) {
+ continue;
+ }
+ LOCK_INIT(&pCh->Ibuf_spinlock);
+ LOCK_INIT(&pCh->Obuf_spinlock);
+ LOCK_INIT(&pCh->Cbuf_spinlock);
+ LOCK_INIT(&pCh->Pbuf_spinlock);
+ // NO LOCK needed yet - this is init
+ // Set up validity flag according to support level
+ if (pB->i2eGoodMap[index >> 4] & (1 << (index & 0xf)) ) {
+ pCh->validity = CHANNEL_MAGIC | CHANNEL_SUPPORT;
+ } else {
+ pCh->validity = CHANNEL_MAGIC;
+ }
+ pCh->pMyBord = pB; /* Back-pointer */
+
+ // Prepare an outgoing flow-control packet to send as soon as the chance
+ // occurs.
+ if ( pCh->validity & CHANNEL_SUPPORT ) {
+ pCh->infl.hd.i2sChannel = index;
+ pCh->infl.hd.i2sCount = 5;
+ pCh->infl.hd.i2sType = PTYPE_BYPASS;
+ pCh->infl.fcmd = 37;
+ pCh->infl.asof = 0;
+ pCh->infl.room = IBUF_SIZE - 1;
+
+ pCh->whenSendFlow = (IBUF_SIZE/5)*4; // when 80% full
+
+ // The following is similar to calling i2QueueNeeds, except that this
+ // is done in longhand, since we are setting up initial conditions on
+ // many channels at once.
+ pCh->channelNeeds = NEED_FLOW; // Since starting from scratch
+ pCh->sinceLastFlow = 0; // No bytes received since last flow
+ // control packet was queued
+ stuffIndex++;
+ *ppCh++ = pCh; // List this channel as needing
+ // initial flow control packet sent
+ }
+
+ // Don't allow anything to be sent until the status packets come in from
+ // the board.
+
+ pCh->outfl.asof = 0;
+ pCh->outfl.room = 0;
+
+ // Initialize all the ring buffers
+
+ pCh->Ibuf_stuff = pCh->Ibuf_strip = 0;
+ pCh->Obuf_stuff = pCh->Obuf_strip = 0;
+ pCh->Cbuf_stuff = pCh->Cbuf_strip = 0;
+
+ memset( &pCh->icount, 0, sizeof (struct async_icount) );
+ pCh->hotKeyIn = HOT_CLEAR;
+ pCh->channelOptions = 0;
+ pCh->bookMarks = 0;
+ init_waitqueue_head(&pCh->pBookmarkWait);
+
+ init_waitqueue_head(&pCh->open_wait);
+ init_waitqueue_head(&pCh->close_wait);
+ init_waitqueue_head(&pCh->delta_msr_wait);
+
+ // Set base and divisor so default custom rate is 9600
+ pCh->BaudBase = 921600; // MAX for ST654, changed after we get
+ pCh->BaudDivisor = 96; // the boxids (UART types) later
+
+ pCh->dataSetIn = 0;
+ pCh->dataSetOut = 0;
+
+ pCh->wopen = 0;
+ pCh->throttled = 0;
+
+ pCh->speed = CBR_9600;
+
+ pCh->flags = 0;
+
+ pCh->ClosingDelay = 5*HZ/10;
+ pCh->ClosingWaitTime = 30*HZ;
+
+ // Initialize task queue objects
+ INIT_WORK(&pCh->tqueue_input, do_input, pCh);
+ INIT_WORK(&pCh->tqueue_status, do_status, pCh);
+
+#ifdef IP2DEBUG_TRACE
+ pCh->trace = ip2trace;
+#endif
+
+ ++pCh;
+ --nChannels;
+ }
+ // No need to check for wrap here; this is initialization.
+ pB->i2Fbuf_stuff = stuffIndex;
+ COMPLETE(pB, I2EE_GOOD);
+
+}
+
+//******************************************************************************
+// Function: i2DeQueueNeeds(pB, type)
+// Parameters: Pointer to a board structure
+// type bit map: may include NEED_INLINE, NEED_BYPASS, or NEED_FLOW
+// Returns:
+// Pointer to a channel structure
+//
+// Description: Returns pointer struct of next channel that needs service of
+// the type specified. Otherwise returns a NULL reference.
+//
+//******************************************************************************
+static i2ChanStrPtr
+i2DeQueueNeeds(i2eBordStrPtr pB, int type)
+{
+ unsigned short queueIndex;
+ unsigned long flags;
+
+ i2ChanStrPtr pCh = NULL;
+
+ switch(type) {
+
+ case NEED_INLINE:
+
+ WRITE_LOCK_IRQSAVE(&pB->Dbuf_spinlock,flags);
+ if ( pB->i2Dbuf_stuff != pB->i2Dbuf_strip)
+ {
+ queueIndex = pB->i2Dbuf_strip;
+ pCh = pB->i2Dbuf[queueIndex];
+ queueIndex++;
+ if (queueIndex >= CH_QUEUE_SIZE) {
+ queueIndex = 0;
+ }
+ pB->i2Dbuf_strip = queueIndex;
+ pCh->channelNeeds &= ~NEED_INLINE;
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->Dbuf_spinlock,flags);
+ break;
+
+ case NEED_BYPASS:
+
+ WRITE_LOCK_IRQSAVE(&pB->Bbuf_spinlock,flags);
+ if (pB->i2Bbuf_stuff != pB->i2Bbuf_strip)
+ {
+ queueIndex = pB->i2Bbuf_strip;
+ pCh = pB->i2Bbuf[queueIndex];
+ queueIndex++;
+ if (queueIndex >= CH_QUEUE_SIZE) {
+ queueIndex = 0;
+ }
+ pB->i2Bbuf_strip = queueIndex;
+ pCh->channelNeeds &= ~NEED_BYPASS;
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->Bbuf_spinlock,flags);
+ break;
+
+ case NEED_FLOW:
+
+ WRITE_LOCK_IRQSAVE(&pB->Fbuf_spinlock,flags);
+ if (pB->i2Fbuf_stuff != pB->i2Fbuf_strip)
+ {
+ queueIndex = pB->i2Fbuf_strip;
+ pCh = pB->i2Fbuf[queueIndex];
+ queueIndex++;
+ if (queueIndex >= CH_QUEUE_SIZE) {
+ queueIndex = 0;
+ }
+ pB->i2Fbuf_strip = queueIndex;
+ pCh->channelNeeds &= ~NEED_FLOW;
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->Fbuf_spinlock,flags);
+ break;
+ default:
+ printk(KERN_ERR "i2DeQueueNeeds called with bad type:%x\n",type);
+ break;
+ }
+ return pCh;
+}
+
+//******************************************************************************
+// Function: i2QueueNeeds(pB, pCh, type)
+// Parameters: Pointer to a board structure
+// Pointer to a channel structure
+// type bit map: may include NEED_INLINE, NEED_BYPASS, or NEED_FLOW
+// Returns: Nothing
+//
+// Description:
+// For each type of need selected, if the given channel is not already in the
+// queue, adds it, and sets the flag indicating it is in the queue.
+//******************************************************************************
+static void
+i2QueueNeeds(i2eBordStrPtr pB, i2ChanStrPtr pCh, int type)
+{
+ unsigned short queueIndex;
+ unsigned long flags;
+
+ // We turn off all the interrupts during this brief process, since the
+ // interrupt-level code might want to put things on the queue as well.
+
+ switch (type) {
+
+ case NEED_INLINE:
+
+ WRITE_LOCK_IRQSAVE(&pB->Dbuf_spinlock,flags);
+ if ( !(pCh->channelNeeds & NEED_INLINE) )
+ {
+ pCh->channelNeeds |= NEED_INLINE;
+ queueIndex = pB->i2Dbuf_stuff;
+ pB->i2Dbuf[queueIndex++] = pCh;
+ if (queueIndex >= CH_QUEUE_SIZE)
+ queueIndex = 0;
+ pB->i2Dbuf_stuff = queueIndex;
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->Dbuf_spinlock,flags);
+ break;
+
+ case NEED_BYPASS:
+
+ WRITE_LOCK_IRQSAVE(&pB->Bbuf_spinlock,flags);
+ if ((type & NEED_BYPASS) && !(pCh->channelNeeds & NEED_BYPASS))
+ {
+ pCh->channelNeeds |= NEED_BYPASS;
+ queueIndex = pB->i2Bbuf_stuff;
+ pB->i2Bbuf[queueIndex++] = pCh;
+ if (queueIndex >= CH_QUEUE_SIZE)
+ queueIndex = 0;
+ pB->i2Bbuf_stuff = queueIndex;
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->Bbuf_spinlock,flags);
+ break;
+
+ case NEED_FLOW:
+
+ WRITE_LOCK_IRQSAVE(&pB->Fbuf_spinlock,flags);
+ if ((type & NEED_FLOW) && !(pCh->channelNeeds & NEED_FLOW))
+ {
+ pCh->channelNeeds |= NEED_FLOW;
+ queueIndex = pB->i2Fbuf_stuff;
+ pB->i2Fbuf[queueIndex++] = pCh;
+ if (queueIndex >= CH_QUEUE_SIZE)
+ queueIndex = 0;
+ pB->i2Fbuf_stuff = queueIndex;
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->Fbuf_spinlock,flags);
+ break;
+
+ case NEED_CREDIT:
+ pCh->channelNeeds |= NEED_CREDIT;
+ break;
+ default:
+ printk(KERN_ERR "i2QueueNeeds called with bad type:%x\n",type);
+ break;
+ }
+ return;
+}
+
+//******************************************************************************
+// Function: i2QueueCommands(type, pCh, timeout, nCommands, pCs,...)
+// Parameters: type - PTYPE_BYPASS or PTYPE_INLINE
+// pointer to the channel structure
+// maximum period to wait
+// number of commands (n)
+// n commands
+// Returns: Number of commands sent, or -1 for error
+//
+// get board lock before calling
+//
+// Description:
+// Queues up some commands to be sent to a channel. To send possibly several
+// bypass or inline commands to the given channel. The timeout parameter
+// indicates how many HUNDREDTHS OF SECONDS to wait until there is room:
+// 0 = return immediately if no room, -ive = wait forever, +ive = number of
+// 1/100 seconds to wait. Return values:
+// -1 Some kind of nasty error: bad channel structure or invalid arguments.
+// 0 No room to send all the commands
+// (+) Number of commands sent
+//******************************************************************************
+static int
+i2QueueCommands(int type, i2ChanStrPtr pCh, int timeout, int nCommands,
+ cmdSyntaxPtr pCs0,...)
+{
+ int totalsize = 0;
+ int blocksize;
+ int lastended;
+ cmdSyntaxPtr *ppCs;
+ cmdSyntaxPtr pCs;
+ int count;
+ int flag;
+ i2eBordStrPtr pB;
+
+ unsigned short maxBlock;
+ unsigned short maxBuff;
+ short bufroom;
+ unsigned short stuffIndex;
+ unsigned char *pBuf;
+ unsigned char *pInsert;
+ unsigned char *pDest, *pSource;
+ unsigned short channel;
+ int cnt;
+ unsigned long flags = 0;
+ rwlock_t *lock_var_p = NULL;
+
+ // Make sure the channel exists, otherwise do nothing
+ if ( !i2Validate ( pCh ) ) {
+ return -1;
+ }
+
+ ip2trace (CHANN, ITRC_QUEUE, ITRC_ENTER, 0 );
+
+ pB = pCh->pMyBord;
+
+ // Board must also exist, and THE INTERRUPT COMMAND ALREADY SENT
+ if (pB->i2eValid != I2E_MAGIC || pB->i2eUsingIrq == IRQ_UNDEFINED) {
+ return -2;
+ }
+ // If the board has gone fatal, return bad, and also hit the trap routine if
+ // it exists.
+ if (pB->i2eFatal) {
+ if ( pB->i2eFatalTrap ) {
+ (*(pB)->i2eFatalTrap)(pB);
+ }
+ return -3;
+ }
+ // Set up some variables, Which buffers are we using? How big are they?
+ switch(type)
+ {
+ case PTYPE_INLINE:
+ flag = INL;
+ maxBlock = MAX_OBUF_BLOCK;
+ maxBuff = OBUF_SIZE;
+ pBuf = pCh->Obuf;
+ break;
+ case PTYPE_BYPASS:
+ flag = BYP;
+ maxBlock = MAX_CBUF_BLOCK;
+ maxBuff = CBUF_SIZE;
+ pBuf = pCh->Cbuf;
+ break;
+ default:
+ return -4;
+ }
+ // Determine the total size required for all the commands
+ totalsize = blocksize = sizeof(i2CmdHeader);
+ lastended = 0;
+ ppCs = &pCs0;
+ for ( count = nCommands; count; count--, ppCs++)
+ {
+ pCs = *ppCs;
+ cnt = pCs->length;
+ // Will a new block be needed for this one?
+ // Two possible reasons: too
+ // big or previous command has to be at the end of a packet.
+ if ((blocksize + cnt > maxBlock) || lastended) {
+ blocksize = sizeof(i2CmdHeader);
+ totalsize += sizeof(i2CmdHeader);
+ }
+ totalsize += cnt;
+ blocksize += cnt;
+
+ // If this command had to end a block, then we will make sure to
+ // account for it should there be any more blocks.
+ lastended = pCs->flags & END;
+ }
+ for (;;) {
+ // Make sure any pending flush commands go out before we add more data.
+ if ( !( pCh->flush_flags && i2RetryFlushOutput( pCh ) ) ) {
+ // How much room (this time through) ?
+ switch(type) {
+ case PTYPE_INLINE:
+ lock_var_p = &pCh->Obuf_spinlock;
+ WRITE_LOCK_IRQSAVE(lock_var_p,flags);
+ stuffIndex = pCh->Obuf_stuff;
+ bufroom = pCh->Obuf_strip - stuffIndex;
+ break;
+ case PTYPE_BYPASS:
+ lock_var_p = &pCh->Cbuf_spinlock;
+ WRITE_LOCK_IRQSAVE(lock_var_p,flags);
+ stuffIndex = pCh->Cbuf_stuff;
+ bufroom = pCh->Cbuf_strip - stuffIndex;
+ break;
+ default:
+ return -5;
+ }
+ if (--bufroom < 0) {
+ bufroom += maxBuff;
+ }
+
+ ip2trace (CHANN, ITRC_QUEUE, 2, 1, bufroom );
+
+ // Check for overflow
+ if (totalsize <= bufroom) {
+ // Normal Expected path - We still hold LOCK
+ break; /* from for()- Enough room: goto proceed */
+ }
+ }
+
+ ip2trace (CHANN, ITRC_QUEUE, 3, 1, totalsize );
+
+ // Prepare to wait for buffers to empty
+ WRITE_UNLOCK_IRQRESTORE(lock_var_p,flags);
+ serviceOutgoingFifo(pB); // Dump what we got
+
+ if (timeout == 0) {
+ return 0; // Tired of waiting
+ }
+ if (timeout > 0)
+ timeout--; // So negative values == forever
+
+ if (!in_interrupt()) {
+ current->state = TASK_INTERRUPTIBLE;
+ schedule_timeout(1); // short nap
+ } else {
+ // we cannot sched/sleep in interrrupt silly
+ return 0;
+ }
+ if (signal_pending(current)) {
+ return 0; // Wake up! Time to die!!!
+ }
+
+ ip2trace (CHANN, ITRC_QUEUE, 4, 0 );
+
+ } // end of for(;;)
+
+ // At this point we have room and the lock - stick them in.
+ channel = pCh->infl.hd.i2sChannel;
+ pInsert = &pBuf[stuffIndex]; // Pointer to start of packet
+ pDest = CMD_OF(pInsert); // Pointer to start of command
+
+ // When we start counting, the block is the size of the header
+ for (blocksize = sizeof(i2CmdHeader), count = nCommands,
+ lastended = 0, ppCs = &pCs0;
+ count;
+ count--, ppCs++)
+ {
+ pCs = *ppCs; // Points to command protocol structure
+
+ // If this is a bookmark request command, post the fact that a bookmark
+ // request is pending. NOTE THIS TRICK ONLY WORKS BECAUSE CMD_BMARK_REQ
+ // has no parameters! The more general solution would be to reference
+ // pCs->cmd[0].
+ if (pCs == CMD_BMARK_REQ) {
+ pCh->bookMarks++;
+
+ ip2trace (CHANN, ITRC_DRAIN, 30, 1, pCh->bookMarks );
+
+ }
+ cnt = pCs->length;
+
+ // If this command would put us over the maximum block size or
+ // if the last command had to be at the end of a block, we end
+ // the existing block here and start a new one.
+ if ((blocksize + cnt > maxBlock) || lastended) {
+
+ ip2trace (CHANN, ITRC_QUEUE, 5, 0 );
+
+ PTYPE_OF(pInsert) = type;
+ CHANNEL_OF(pInsert) = channel;
+ // count here does not include the header
+ CMD_COUNT_OF(pInsert) = blocksize - sizeof(i2CmdHeader);
+ stuffIndex += blocksize;
+ if(stuffIndex >= maxBuff) {
+ stuffIndex = 0;
+ pInsert = pBuf;
+ }
+ pInsert = &pBuf[stuffIndex]; // Pointer to start of next pkt
+ pDest = CMD_OF(pInsert);
+ blocksize = sizeof(i2CmdHeader);
+ }
+ // Now we know there is room for this one in the current block
+
+ blocksize += cnt; // Total bytes in this command
+ pSource = pCs->cmd; // Copy the command into the buffer
+ while (cnt--) {
+ *pDest++ = *pSource++;
+ }
+ // If this command had to end a block, then we will make sure to account
+ // for it should there be any more blocks.
+ lastended = pCs->flags & END;
+ } // end for
+ // Clean up the final block by writing header, etc
+
+ PTYPE_OF(pInsert) = type;
+ CHANNEL_OF(pInsert) = channel;
+ // count here does not include the header
+ CMD_COUNT_OF(pInsert) = blocksize - sizeof(i2CmdHeader);
+ stuffIndex += blocksize;
+ if(stuffIndex >= maxBuff) {
+ stuffIndex = 0;
+ pInsert = pBuf;
+ }
+ // Updates the index, and post the need for service. When adding these to
+ // the queue of channels, we turn off the interrupt while doing so,
+ // because at interrupt level we might want to push a channel back to the
+ // end of the queue.
+ switch(type)
+ {
+ case PTYPE_INLINE:
+ pCh->Obuf_stuff = stuffIndex; // Store buffer pointer
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags);
+
+ pB->debugInlineQueued++;
+ // Add the channel pointer to list of channels needing service (first
+ // come...), if it's not already there.
+ i2QueueNeeds(pB, pCh, NEED_INLINE);
+ break;
+
+ case PTYPE_BYPASS:
+ pCh->Cbuf_stuff = stuffIndex; // Store buffer pointer
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Cbuf_spinlock,flags);
+
+ pB->debugBypassQueued++;
+ // Add the channel pointer to list of channels needing service (first
+ // come...), if it's not already there.
+ i2QueueNeeds(pB, pCh, NEED_BYPASS);
+ break;
+ }
+
+ ip2trace (CHANN, ITRC_QUEUE, ITRC_RETURN, 1, nCommands );
+
+ return nCommands; // Good status: number of commands sent
+}
+
+//******************************************************************************
+// Function: i2GetStatus(pCh,resetBits)
+// Parameters: Pointer to a channel structure
+// Bit map of status bits to clear
+// Returns: Bit map of current status bits
+//
+// Description:
+// Returns the state of data set signals, and whether a break has been received,
+// (see i2lib.h for bit-mapped result). resetBits is a bit-map of any status
+// bits to be cleared: I2_BRK, I2_PAR, I2_FRA, I2_OVR,... These are cleared
+// AFTER the condition is passed. If pCh does not point to a valid channel,
+// returns -1 (which would be impossible otherwise.
+//******************************************************************************
+static int
+i2GetStatus(i2ChanStrPtr pCh, int resetBits)
+{
+ unsigned short status;
+ i2eBordStrPtr pB;
+
+ ip2trace (CHANN, ITRC_STATUS, ITRC_ENTER, 2, pCh->dataSetIn, resetBits );
+
+ // Make sure the channel exists, otherwise do nothing */
+ if ( !i2Validate ( pCh ) )
+ return -1;
+
+ pB = pCh->pMyBord;
+
+ status = pCh->dataSetIn;
+
+ // Clear any specified error bits: but note that only actual error bits can
+ // be cleared, regardless of the value passed.
+ if (resetBits)
+ {
+ pCh->dataSetIn &= ~(resetBits & (I2_BRK | I2_PAR | I2_FRA | I2_OVR));
+ pCh->dataSetIn &= ~(I2_DDCD | I2_DCTS | I2_DDSR | I2_DRI);
+ }
+
+ ip2trace (CHANN, ITRC_STATUS, ITRC_RETURN, 1, pCh->dataSetIn );
+
+ return status;
+}
+
+//******************************************************************************
+// Function: i2Input(pChpDest,count)
+// Parameters: Pointer to a channel structure
+// Pointer to data buffer
+// Number of bytes to read
+// Returns: Number of bytes read, or -1 for error
+//
+// Description:
+// Strips data from the input buffer and writes it to pDest. If there is a
+// collosal blunder, (invalid structure pointers or the like), returns -1.
+// Otherwise, returns the number of bytes read.
+//******************************************************************************
+static int
+i2Input(i2ChanStrPtr pCh)
+{
+ int amountToMove;
+ unsigned short stripIndex;
+ int count;
+ unsigned long flags = 0;
+
+ ip2trace (CHANN, ITRC_INPUT, ITRC_ENTER, 0);
+
+ // Ensure channel structure seems real
+ if ( !i2Validate( pCh ) ) {
+ count = -1;
+ goto i2Input_exit;
+ }
+ WRITE_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags);
+
+ // initialize some accelerators and private copies
+ stripIndex = pCh->Ibuf_strip;
+
+ count = pCh->Ibuf_stuff - stripIndex;
+
+ // If buffer is empty or requested data count was 0, (trivial case) return
+ // without any further thought.
+ if ( count == 0 ) {
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags);
+ goto i2Input_exit;
+ }
+ // Adjust for buffer wrap
+ if ( count < 0 ) {
+ count += IBUF_SIZE;
+ }
+ // Don't give more than can be taken by the line discipline
+ amountToMove = pCh->pTTY->ldisc.receive_room( pCh->pTTY );
+ if (count > amountToMove) {
+ count = amountToMove;
+ }
+ // How much could we copy without a wrap?
+ amountToMove = IBUF_SIZE - stripIndex;
+
+ if (amountToMove > count) {
+ amountToMove = count;
+ }
+ // Move the first block
+ pCh->pTTY->ldisc.receive_buf( pCh->pTTY,
+ &(pCh->Ibuf[stripIndex]), NULL, amountToMove );
+ // If we needed to wrap, do the second data move
+ if (count > amountToMove) {
+ pCh->pTTY->ldisc.receive_buf( pCh->pTTY,
+ pCh->Ibuf, NULL, count - amountToMove );
+ }
+ // Bump and wrap the stripIndex all at once by the amount of data read. This
+ // method is good regardless of whether the data was in one or two pieces.
+ stripIndex += count;
+ if (stripIndex >= IBUF_SIZE) {
+ stripIndex -= IBUF_SIZE;
+ }
+ pCh->Ibuf_strip = stripIndex;
+
+ // Update our flow control information and possibly queue ourselves to send
+ // it, depending on how much data has been stripped since the last time a
+ // packet was sent.
+ pCh->infl.asof += count;
+
+ if ((pCh->sinceLastFlow += count) >= pCh->whenSendFlow) {
+ pCh->sinceLastFlow -= pCh->whenSendFlow;
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags);
+ i2QueueNeeds(pCh->pMyBord, pCh, NEED_FLOW);
+ } else {
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags);
+ }
+
+i2Input_exit:
+
+ ip2trace (CHANN, ITRC_INPUT, ITRC_RETURN, 1, count);
+
+ return count;
+}
+
+//******************************************************************************
+// Function: i2InputFlush(pCh)
+// Parameters: Pointer to a channel structure
+// Returns: Number of bytes stripped, or -1 for error
+//
+// Description:
+// Strips any data from the input buffer. If there is a collosal blunder,
+// (invalid structure pointers or the like), returns -1. Otherwise, returns the
+// number of bytes stripped.
+//******************************************************************************
+static int
+i2InputFlush(i2ChanStrPtr pCh)
+{
+ int count;
+ unsigned long flags;
+
+ // Ensure channel structure seems real
+ if ( !i2Validate ( pCh ) )
+ return -1;
+
+ ip2trace (CHANN, ITRC_INPUT, 10, 0);
+
+ WRITE_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags);
+ count = pCh->Ibuf_stuff - pCh->Ibuf_strip;
+
+ // Adjust for buffer wrap
+ if (count < 0) {
+ count += IBUF_SIZE;
+ }
+
+ // Expedient way to zero out the buffer
+ pCh->Ibuf_strip = pCh->Ibuf_stuff;
+
+
+ // Update our flow control information and possibly queue ourselves to send
+ // it, depending on how much data has been stripped since the last time a
+ // packet was sent.
+
+ pCh->infl.asof += count;
+
+ if ( (pCh->sinceLastFlow += count) >= pCh->whenSendFlow )
+ {
+ pCh->sinceLastFlow -= pCh->whenSendFlow;
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags);
+ i2QueueNeeds(pCh->pMyBord, pCh, NEED_FLOW);
+ } else {
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags);
+ }
+
+ ip2trace (CHANN, ITRC_INPUT, 19, 1, count);
+
+ return count;
+}
+
+//******************************************************************************
+// Function: i2InputAvailable(pCh)
+// Parameters: Pointer to a channel structure
+// Returns: Number of bytes available, or -1 for error
+//
+// Description:
+// If there is a collosal blunder, (invalid structure pointers or the like),
+// returns -1. Otherwise, returns the number of bytes stripped. Otherwise,
+// returns the number of bytes available in the buffer.
+//******************************************************************************
+#if 0
+static int
+i2InputAvailable(i2ChanStrPtr pCh)
+{
+ int count;
+
+ // Ensure channel structure seems real
+ if ( !i2Validate ( pCh ) ) return -1;
+
+
+ // initialize some accelerators and private copies
+ READ_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags);
+ count = pCh->Ibuf_stuff - pCh->Ibuf_strip;
+ READ_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags);
+
+ // Adjust for buffer wrap
+ if (count < 0)
+ {
+ count += IBUF_SIZE;
+ }
+
+ return count;
+}
+#endif
+
+//******************************************************************************
+// Function: i2Output(pCh, pSource, count)
+// Parameters: Pointer to channel structure
+// Pointer to source data
+// Number of bytes to send
+// Returns: Number of bytes sent, or -1 for error
+//
+// Description:
+// Queues the data at pSource to be sent as data packets to the board. If there
+// is a collosal blunder, (invalid structure pointers or the like), returns -1.
+// Otherwise, returns the number of bytes written. What if there is not enough
+// room for all the data? If pCh->channelOptions & CO_NBLOCK_WRITE is set, then
+// we transfer as many characters as we can now, then return. If this bit is
+// clear (default), routine will spin along until all the data is buffered.
+// Should this occur, the 1-ms delay routine is called while waiting to avoid
+// applications that one cannot break out of.
+//******************************************************************************
+static int
+i2Output(i2ChanStrPtr pCh, const char *pSource, int count, int user )
+{
+ i2eBordStrPtr pB;
+ unsigned char *pInsert;
+ int amountToMove;
+ int countOriginal = count;
+ unsigned short channel;
+ unsigned short stuffIndex;
+ unsigned long flags;
+ int rc = 0;
+
+ int bailout = 10;
+
+ ip2trace (CHANN, ITRC_OUTPUT, ITRC_ENTER, 2, count, user );
+
+ // Ensure channel structure seems real
+ if ( !i2Validate ( pCh ) )
+ return -1;
+
+ // initialize some accelerators and private copies
+ pB = pCh->pMyBord;
+ channel = pCh->infl.hd.i2sChannel;
+
+ // If the board has gone fatal, return bad, and also hit the trap routine if
+ // it exists.
+ if (pB->i2eFatal) {
+ if (pB->i2eFatalTrap) {
+ (*(pB)->i2eFatalTrap)(pB);
+ }
+ return -1;
+ }
+ // Proceed as though we would do everything
+ while ( count > 0 ) {
+
+ // How much room in output buffer is there?
+ READ_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags);
+ amountToMove = pCh->Obuf_strip - pCh->Obuf_stuff - 1;
+ READ_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags);
+ if (amountToMove < 0) {
+ amountToMove += OBUF_SIZE;
+ }
+ // Subtract off the headers size and see how much room there is for real
+ // data. If this is negative, we will discover later.
+ amountToMove -= sizeof (i2DataHeader);
+
+ // Don't move more (now) than can go in a single packet
+ if ( amountToMove > (int)(MAX_OBUF_BLOCK - sizeof(i2DataHeader)) ) {
+ amountToMove = MAX_OBUF_BLOCK - sizeof(i2DataHeader);
+ }
+ // Don't move more than the count we were given
+ if (amountToMove > count) {
+ amountToMove = count;
+ }
+ // Now we know how much we must move: NB because the ring buffers have
+ // an overflow area at the end, we needn't worry about wrapping in the
+ // middle of a packet.
+
+// Small WINDOW here with no LOCK but I can't call Flush with LOCK
+// We would be flushing (or ending flush) anyway
+
+ ip2trace (CHANN, ITRC_OUTPUT, 10, 1, amountToMove );
+
+ if ( !(pCh->flush_flags && i2RetryFlushOutput(pCh) )
+ && amountToMove > 0 )
+ {
+ WRITE_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags);
+ stuffIndex = pCh->Obuf_stuff;
+
+ // Had room to move some data: don't know whether the block size,
+ // buffer space, or what was the limiting factor...
+ pInsert = &(pCh->Obuf[stuffIndex]);
+
+ // Set up the header
+ CHANNEL_OF(pInsert) = channel;
+ PTYPE_OF(pInsert) = PTYPE_DATA;
+ TAG_OF(pInsert) = 0;
+ ID_OF(pInsert) = ID_ORDINARY_DATA;
+ DATA_COUNT_OF(pInsert) = amountToMove;
+
+ // Move the data
+ if ( user ) {
+ rc = copy_from_user((char*)(DATA_OF(pInsert)), pSource,
+ amountToMove );
+ } else {
+ memcpy( (char*)(DATA_OF(pInsert)), pSource, amountToMove );
+ }
+ // Adjust pointers and indices
+ pSource += amountToMove;
+ pCh->Obuf_char_count += amountToMove;
+ stuffIndex += amountToMove + sizeof(i2DataHeader);
+ count -= amountToMove;
+
+ if (stuffIndex >= OBUF_SIZE) {
+ stuffIndex = 0;
+ }
+ pCh->Obuf_stuff = stuffIndex;
+
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags);
+
+ ip2trace (CHANN, ITRC_OUTPUT, 13, 1, stuffIndex );
+
+ } else {
+
+ // Cannot move data
+ // becuz we need to stuff a flush
+ // or amount to move is <= 0
+
+ ip2trace(CHANN, ITRC_OUTPUT, 14, 3,
+ amountToMove, pB->i2eFifoRemains,
+ pB->i2eWaitingForEmptyFifo );
+
+ // Put this channel back on queue
+ // this ultimatly gets more data or wakes write output
+ i2QueueNeeds(pB, pCh, NEED_INLINE);
+
+ if ( pB->i2eWaitingForEmptyFifo ) {
+
+ ip2trace (CHANN, ITRC_OUTPUT, 16, 0 );
+
+ // or schedule
+ if (!in_interrupt()) {
+
+ ip2trace (CHANN, ITRC_OUTPUT, 61, 0 );
+
+ current->state = TASK_INTERRUPTIBLE;
+ schedule_timeout(2);
+ if (signal_pending(current)) {
+ break;
+ }
+ continue;
+ } else {
+
+ ip2trace (CHANN, ITRC_OUTPUT, 62, 0 );
+
+ // let interrupt in = WAS restore_flags()
+ // We hold no lock nor is irq off anymore???
+
+ break;
+ }
+ break; // from while(count)
+ }
+ else if ( pB->i2eFifoRemains < 32 && !pB->i2eTxMailEmpty ( pB ) )
+ {
+ ip2trace (CHANN, ITRC_OUTPUT, 19, 2,
+ pB->i2eFifoRemains,
+ pB->i2eTxMailEmpty );
+
+ break; // from while(count)
+ } else if ( pCh->channelNeeds & NEED_CREDIT ) {
+
+ ip2trace (CHANN, ITRC_OUTPUT, 22, 0 );
+
+ break; // from while(count)
+ } else if ( --bailout) {
+
+ // Try to throw more things (maybe not us) in the fifo if we're
+ // not already waiting for it.
+
+ ip2trace (CHANN, ITRC_OUTPUT, 20, 0 );
+
+ serviceOutgoingFifo(pB);
+ //break; CONTINUE;
+ } else {
+ ip2trace (CHANN, ITRC_OUTPUT, 21, 3,
+ pB->i2eFifoRemains,
+ pB->i2eOutMailWaiting,
+ pB->i2eWaitingForEmptyFifo );
+
+ break; // from while(count)
+ }
+ }
+ } // End of while(count)
+
+ i2QueueNeeds(pB, pCh, NEED_INLINE);
+
+ // We drop through either when the count expires, or when there is some
+ // count left, but there was a non-blocking write.
+ if (countOriginal > count) {
+
+ ip2trace (CHANN, ITRC_OUTPUT, 17, 2, countOriginal, count );
+
+ serviceOutgoingFifo( pB );
+ }
+
+ ip2trace (CHANN, ITRC_OUTPUT, ITRC_RETURN, 2, countOriginal, count );
+
+ return countOriginal - count;
+}
+
+//******************************************************************************
+// Function: i2FlushOutput(pCh)
+// Parameters: Pointer to a channel structure
+// Returns: Nothing
+//
+// Description:
+// Sends bypass command to start flushing (waiting possibly forever until there
+// is room), then sends inline command to stop flushing output, (again waiting
+// possibly forever).
+//******************************************************************************
+static inline void
+i2FlushOutput(i2ChanStrPtr pCh)
+{
+
+ ip2trace (CHANN, ITRC_FLUSH, 1, 1, pCh->flush_flags );
+
+ if (pCh->flush_flags)
+ return;
+
+ if ( 1 != i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_STARTFL) ) {
+ pCh->flush_flags = STARTFL_FLAG; // Failed - flag for later
+
+ ip2trace (CHANN, ITRC_FLUSH, 2, 0 );
+
+ } else if ( 1 != i2QueueCommands(PTYPE_INLINE, pCh, 0, 1, CMD_STOPFL) ) {
+ pCh->flush_flags = STOPFL_FLAG; // Failed - flag for later
+
+ ip2trace (CHANN, ITRC_FLUSH, 3, 0 );
+ }
+}
+
+static int
+i2RetryFlushOutput(i2ChanStrPtr pCh)
+{
+ int old_flags = pCh->flush_flags;
+
+ ip2trace (CHANN, ITRC_FLUSH, 14, 1, old_flags );
+
+ pCh->flush_flags = 0; // Clear flag so we can avoid recursion
+ // and queue the commands
+
+ if ( old_flags & STARTFL_FLAG ) {
+ if ( 1 == i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_STARTFL) ) {
+ old_flags = STOPFL_FLAG; //Success - send stop flush
+ } else {
+ old_flags = STARTFL_FLAG; //Failure - Flag for retry later
+ }
+
+ ip2trace (CHANN, ITRC_FLUSH, 15, 1, old_flags );
+
+ }
+ if ( old_flags & STOPFL_FLAG ) {
+ if (1 == i2QueueCommands(PTYPE_INLINE, pCh, 0, 1, CMD_STOPFL)) {
+ old_flags = 0; // Success - clear flags
+ }
+
+ ip2trace (CHANN, ITRC_FLUSH, 16, 1, old_flags );
+ }
+ pCh->flush_flags = old_flags;
+
+ ip2trace (CHANN, ITRC_FLUSH, 17, 1, old_flags );
+
+ return old_flags;
+}
+
+//******************************************************************************
+// Function: i2DrainOutput(pCh,timeout)
+// Parameters: Pointer to a channel structure
+// Maximum period to wait
+// Returns: ?
+//
+// Description:
+// Uses the bookmark request command to ask the board to send a bookmark back as
+// soon as all the data is completely sent.
+//******************************************************************************
+static void
+i2DrainWakeup(i2ChanStrPtr pCh)
+{
+ ip2trace (CHANN, ITRC_DRAIN, 10, 1, pCh->BookmarkTimer.expires );
+
+ pCh->BookmarkTimer.expires = 0;
+ wake_up_interruptible( &pCh->pBookmarkWait );
+}
+
+static void
+i2DrainOutput(i2ChanStrPtr pCh, int timeout)
+{
+ wait_queue_t wait;
+ i2eBordStrPtr pB;
+
+ ip2trace (CHANN, ITRC_DRAIN, ITRC_ENTER, 1, pCh->BookmarkTimer.expires);
+
+ pB = pCh->pMyBord;
+ // If the board has gone fatal, return bad,
+ // and also hit the trap routine if it exists.
+ if (pB->i2eFatal) {
+ if (pB->i2eFatalTrap) {
+ (*(pB)->i2eFatalTrap)(pB);
+ }
+ return;
+ }
+ if ((timeout > 0) && (pCh->BookmarkTimer.expires == 0 )) {
+ // One per customer (channel)
+ init_timer( &(pCh->BookmarkTimer) );
+ pCh->BookmarkTimer.expires = jiffies + timeout;
+ pCh->BookmarkTimer.function = (void*)(unsigned long)i2DrainWakeup;
+ pCh->BookmarkTimer.data = (unsigned long)pCh;
+
+ ip2trace (CHANN, ITRC_DRAIN, 1, 1, pCh->BookmarkTimer.expires );
+
+ add_timer( &(pCh->BookmarkTimer) );
+ }
+
+ i2QueueCommands( PTYPE_INLINE, pCh, -1, 1, CMD_BMARK_REQ );
+
+ init_waitqueue_entry(&wait, current);
+ add_wait_queue(&(pCh->pBookmarkWait), &wait);
+ set_current_state( TASK_INTERRUPTIBLE );
+
+ serviceOutgoingFifo( pB );
+
+ schedule(); // Now we take our interruptible sleep on
+
+ // Clean up the queue
+ set_current_state( TASK_RUNNING );
+ remove_wait_queue(&(pCh->pBookmarkWait), &wait);
+
+ // if expires == 0 then timer poped, then do not need to del_timer
+ if ((timeout > 0) && pCh->BookmarkTimer.expires &&
+ time_before(jiffies, pCh->BookmarkTimer.expires)) {
+ del_timer( &(pCh->BookmarkTimer) );
+ pCh->BookmarkTimer.expires = 0;
+
+ ip2trace (CHANN, ITRC_DRAIN, 3, 1, pCh->BookmarkTimer.expires );
+
+ }
+ ip2trace (CHANN, ITRC_DRAIN, ITRC_RETURN, 1, pCh->BookmarkTimer.expires );
+ return;
+}
+
+//******************************************************************************
+// Function: i2OutputFree(pCh)
+// Parameters: Pointer to a channel structure
+// Returns: Space in output buffer
+//
+// Description:
+// Returns -1 if very gross error. Otherwise returns the amount of bytes still
+// free in the output buffer.
+//******************************************************************************
+static int
+i2OutputFree(i2ChanStrPtr pCh)
+{
+ int amountToMove;
+ unsigned long flags;
+
+ // Ensure channel structure seems real
+ if ( !i2Validate ( pCh ) ) {
+ return -1;
+ }
+ READ_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags);
+ amountToMove = pCh->Obuf_strip - pCh->Obuf_stuff - 1;
+ READ_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags);
+
+ if (amountToMove < 0) {
+ amountToMove += OBUF_SIZE;
+ }
+ // If this is negative, we will discover later
+ amountToMove -= sizeof(i2DataHeader);
+
+ return (amountToMove < 0) ? 0 : amountToMove;
+}
+static void
+
+ip2_owake( PTTY tp)
+{
+ i2ChanStrPtr pCh;
+
+ if (tp == NULL) return;
+
+ pCh = tp->driver_data;
+
+ ip2trace (CHANN, ITRC_SICMD, 10, 2, tp->flags,
+ (1 << TTY_DO_WRITE_WAKEUP) );
+
+ wake_up_interruptible ( &tp->write_wait );
+ if ( ( tp->flags & (1 << TTY_DO_WRITE_WAKEUP) )
+ && tp->ldisc.write_wakeup )
+ {
+ (tp->ldisc.write_wakeup) ( tp );
+
+ ip2trace (CHANN, ITRC_SICMD, 11, 0 );
+
+ }
+}
+
+static inline void
+set_baud_params(i2eBordStrPtr pB)
+{
+ int i,j;
+ i2ChanStrPtr *pCh;
+
+ pCh = (i2ChanStrPtr *) pB->i2eChannelPtr;
+
+ for (i = 0; i < ABS_MAX_BOXES; i++) {
+ if (pB->channelBtypes.bid_value[i]) {
+ if (BID_HAS_654(pB->channelBtypes.bid_value[i])) {
+ for (j = 0; j < ABS_BIGGEST_BOX; j++) {
+ if (pCh[i*16+j] == NULL)
+ break;
+ (pCh[i*16+j])->BaudBase = 921600; // MAX for ST654
+ (pCh[i*16+j])->BaudDivisor = 96;
+ }
+ } else { // has cirrus cd1400
+ for (j = 0; j < ABS_BIGGEST_BOX; j++) {
+ if (pCh[i*16+j] == NULL)
+ break;
+ (pCh[i*16+j])->BaudBase = 115200; // MAX for CD1400
+ (pCh[i*16+j])->BaudDivisor = 12;
+ }
+ }
+ }
+ }
+}
+
+//******************************************************************************
+// Function: i2StripFifo(pB)
+// Parameters: Pointer to a board structure
+// Returns: ?
+//
+// Description:
+// Strips all the available data from the incoming FIFO, identifies the type of
+// packet, and either buffers the data or does what needs to be done.
+//
+// Note there is no overflow checking here: if the board sends more data than it
+// ought to, we will not detect it here, but blindly overflow...
+//******************************************************************************
+
+// A buffer for reading in blocks for unknown channels
+static unsigned char junkBuffer[IBUF_SIZE];
+
+// A buffer to read in a status packet. Because of the size of the count field
+// for these things, the maximum packet size must be less than MAX_CMD_PACK_SIZE
+static unsigned char cmdBuffer[MAX_CMD_PACK_SIZE + 4];
+
+// This table changes the bit order from MSR order given by STAT_MODEM packet to
+// status bits used in our library.
+static char xlatDss[16] = {
+0 | 0 | 0 | 0 ,
+0 | 0 | 0 | I2_CTS ,
+0 | 0 | I2_DSR | 0 ,
+0 | 0 | I2_DSR | I2_CTS ,
+0 | I2_RI | 0 | 0 ,
+0 | I2_RI | 0 | I2_CTS ,
+0 | I2_RI | I2_DSR | 0 ,
+0 | I2_RI | I2_DSR | I2_CTS ,
+I2_DCD | 0 | 0 | 0 ,
+I2_DCD | 0 | 0 | I2_CTS ,
+I2_DCD | 0 | I2_DSR | 0 ,
+I2_DCD | 0 | I2_DSR | I2_CTS ,
+I2_DCD | I2_RI | 0 | 0 ,
+I2_DCD | I2_RI | 0 | I2_CTS ,
+I2_DCD | I2_RI | I2_DSR | 0 ,
+I2_DCD | I2_RI | I2_DSR | I2_CTS };
+
+static inline void
+i2StripFifo(i2eBordStrPtr pB)
+{
+ i2ChanStrPtr pCh;
+ int channel;
+ int count;
+ unsigned short stuffIndex;
+ int amountToRead;
+ unsigned char *pc, *pcLimit;
+ unsigned char uc;
+ unsigned char dss_change;
+ unsigned long bflags,cflags;
+
+// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, ITRC_ENTER, 0 );
+
+ while (HAS_INPUT(pB)) {
+// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 2, 0 );
+
+ // Process packet from fifo a one atomic unit
+ WRITE_LOCK_IRQSAVE(&pB->read_fifo_spinlock,bflags);
+
+ // The first word (or two bytes) will have channel number and type of
+ // packet, possibly other information
+ pB->i2eLeadoffWord[0] = iiReadWord(pB);
+
+ switch(PTYPE_OF(pB->i2eLeadoffWord))
+ {
+ case PTYPE_DATA:
+ pB->got_input = 1;
+
+// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 3, 0 );
+
+ channel = CHANNEL_OF(pB->i2eLeadoffWord); /* Store channel */
+ count = iiReadWord(pB); /* Count is in the next word */
+
+// NEW: Check the count for sanity! Should the hardware fail, our death
+// is more pleasant. While an oversize channel is acceptable (just more
+// than the driver supports), an over-length count clearly means we are
+// sick!
+ if ( ((unsigned int)count) > IBUF_SIZE ) {
+ pB->i2eFatal = 2;
+ WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags);
+ return; /* Bail out ASAP */
+ }
+ // Channel is illegally big ?
+ if ((channel >= pB->i2eChannelCnt) ||
+ (NULL==(pCh = ((i2ChanStrPtr*)pB->i2eChannelPtr)[channel])))
+ {
+ iiReadBuf(pB, junkBuffer, count);
+ WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags);
+ break; /* From switch: ready for next packet */
+ }
+
+ // Channel should be valid, then
+
+ // If this is a hot-key, merely post its receipt for now. These are
+ // always supposed to be 1-byte packets, so we won't even check the
+ // count. Also we will post an acknowledgement to the board so that
+ // more data can be forthcoming. Note that we are not trying to use
+ // these sequences in this driver, merely to robustly ignore them.
+ if(ID_OF(pB->i2eLeadoffWord) == ID_HOT_KEY)
+ {
+ pCh->hotKeyIn = iiReadWord(pB) & 0xff;
+ WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags);
+ i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_HOTACK);
+ break; /* From the switch: ready for next packet */
+ }
+
+ // Normal data! We crudely assume there is room for the data in our
+ // buffer because the board wouldn't have exceeded his credit limit.
+ WRITE_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,cflags);
+ // We have 2 locks now
+ stuffIndex = pCh->Ibuf_stuff;
+ amountToRead = IBUF_SIZE - stuffIndex;
+ if (amountToRead > count)
+ amountToRead = count;
+
+ // stuffIndex would have been already adjusted so there would
+ // always be room for at least one, and count is always at least
+ // one.
+
+ iiReadBuf(pB, &(pCh->Ibuf[stuffIndex]), amountToRead);
+ pCh->icount.rx += amountToRead;
+
+ // Update the stuffIndex by the amount of data moved. Note we could
+ // never ask for more data than would just fit. However, we might
+ // have read in one more byte than we wanted because the read
+ // rounds up to even bytes. If this byte is on the end of the
+ // packet, and is padding, we ignore it. If the byte is part of
+ // the actual data, we need to move it.
+
+ stuffIndex += amountToRead;
+
+ if (stuffIndex >= IBUF_SIZE) {
+ if ((amountToRead & 1) && (count > amountToRead)) {
+ pCh->Ibuf[0] = pCh->Ibuf[IBUF_SIZE];
+ amountToRead++;
+ stuffIndex = 1;
+ } else {
+ stuffIndex = 0;
+ }
+ }
+
+ // If there is anything left over, read it as well
+ if (count > amountToRead) {
+ amountToRead = count - amountToRead;
+ iiReadBuf(pB, &(pCh->Ibuf[stuffIndex]), amountToRead);
+ pCh->icount.rx += amountToRead;
+ stuffIndex += amountToRead;
+ }
+
+ // Update stuff index
+ pCh->Ibuf_stuff = stuffIndex;
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,cflags);
+ WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags);
+
+#ifdef USE_IQ
+ schedule_work(&pCh->tqueue_input);
+#else
+ do_input(pCh);
+#endif
+
+ // Note we do not need to maintain any flow-control credits at this
+ // time: if we were to increment .asof and decrement .room, there
+ // would be no net effect. Instead, when we strip data, we will
+ // increment .asof and leave .room unchanged.
+
+ break; // From switch: ready for next packet
+
+ case PTYPE_STATUS:
+ ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 4, 0 );
+
+ count = CMD_COUNT_OF(pB->i2eLeadoffWord);
+
+ iiReadBuf(pB, cmdBuffer, count);
+ // We can release early with buffer grab
+ WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags);
+
+ pc = cmdBuffer;
+ pcLimit = &(cmdBuffer[count]);
+
+ while (pc < pcLimit) {
+ channel = *pc++;
+
+ ip2trace (channel, ITRC_SFIFO, 7, 2, channel, *pc );
+
+ /* check for valid channel */
+ if (channel < pB->i2eChannelCnt
+ &&
+ (pCh = (((i2ChanStrPtr*)pB->i2eChannelPtr)[channel])) != NULL
+ )
+ {
+ dss_change = 0;
+
+ switch (uc = *pc++)
+ {
+ /* Breaks and modem signals are easy: just update status */
+ case STAT_CTS_UP:
+ if ( !(pCh->dataSetIn & I2_CTS) )
+ {
+ pCh->dataSetIn |= I2_DCTS;
+ pCh->icount.cts++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn |= I2_CTS;
+ break;
+
+ case STAT_CTS_DN:
+ if ( pCh->dataSetIn & I2_CTS )
+ {
+ pCh->dataSetIn |= I2_DCTS;
+ pCh->icount.cts++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn &= ~I2_CTS;
+ break;
+
+ case STAT_DCD_UP:
+ ip2trace (channel, ITRC_MODEM, 1, 1, pCh->dataSetIn );
+
+ if ( !(pCh->dataSetIn & I2_DCD) )
+ {
+ ip2trace (CHANN, ITRC_MODEM, 2, 0 );
+ pCh->dataSetIn |= I2_DDCD;
+ pCh->icount.dcd++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn |= I2_DCD;
+
+ ip2trace (channel, ITRC_MODEM, 3, 1, pCh->dataSetIn );
+ break;
+
+ case STAT_DCD_DN:
+ ip2trace (channel, ITRC_MODEM, 4, 1, pCh->dataSetIn );
+ if ( pCh->dataSetIn & I2_DCD )
+ {
+ ip2trace (channel, ITRC_MODEM, 5, 0 );
+ pCh->dataSetIn |= I2_DDCD;
+ pCh->icount.dcd++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn &= ~I2_DCD;
+
+ ip2trace (channel, ITRC_MODEM, 6, 1, pCh->dataSetIn );
+ break;
+
+ case STAT_DSR_UP:
+ if ( !(pCh->dataSetIn & I2_DSR) )
+ {
+ pCh->dataSetIn |= I2_DDSR;
+ pCh->icount.dsr++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn |= I2_DSR;
+ break;
+
+ case STAT_DSR_DN:
+ if ( pCh->dataSetIn & I2_DSR )
+ {
+ pCh->dataSetIn |= I2_DDSR;
+ pCh->icount.dsr++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn &= ~I2_DSR;
+ break;
+
+ case STAT_RI_UP:
+ if ( !(pCh->dataSetIn & I2_RI) )
+ {
+ pCh->dataSetIn |= I2_DRI;
+ pCh->icount.rng++;
+ dss_change = 1;
+ }
+ pCh->dataSetIn |= I2_RI ;
+ break;
+
+ case STAT_RI_DN:
+ // to be compat with serial.c
+ //if ( pCh->dataSetIn & I2_RI )
+ //{
+ // pCh->dataSetIn |= I2_DRI;
+ // pCh->icount.rng++;
+ // dss_change = 1;
+ //}
+ pCh->dataSetIn &= ~I2_RI ;
+ break;
+
+ case STAT_BRK_DET:
+ pCh->dataSetIn |= I2_BRK;
+ pCh->icount.brk++;
+ dss_change = 1;
+ break;
+
+ // Bookmarks? one less request we're waiting for
+ case STAT_BMARK:
+ pCh->bookMarks--;
+ if (pCh->bookMarks <= 0 ) {
+ pCh->bookMarks = 0;
+ wake_up_interruptible( &pCh->pBookmarkWait );
+
+ ip2trace (channel, ITRC_DRAIN, 20, 1, pCh->BookmarkTimer.expires );
+ }
+ break;
+
+ // Flow control packets? Update the new credits, and if
+ // someone was waiting for output, queue him up again.
+ case STAT_FLOW:
+ pCh->outfl.room =
+ ((flowStatPtr)pc)->room -
+ (pCh->outfl.asof - ((flowStatPtr)pc)->asof);
+
+ ip2trace (channel, ITRC_STFLW, 1, 1, pCh->outfl.room );
+
+ if (pCh->channelNeeds & NEED_CREDIT)
+ {
+ ip2trace (channel, ITRC_STFLW, 2, 1, pCh->channelNeeds);
+
+ pCh->channelNeeds &= ~NEED_CREDIT;
+ i2QueueNeeds(pB, pCh, NEED_INLINE);
+ if ( pCh->pTTY )
+ ip2_owake(pCh->pTTY);
+ }
+
+ ip2trace (channel, ITRC_STFLW, 3, 1, pCh->channelNeeds);
+
+ pc += sizeof(flowStat);
+ break;
+
+ /* Special packets: */
+ /* Just copy the information into the channel structure */
+
+ case STAT_STATUS:
+
+ pCh->channelStatus = *((debugStatPtr)pc);
+ pc += sizeof(debugStat);
+ break;
+
+ case STAT_TXCNT:
+
+ pCh->channelTcount = *((cntStatPtr)pc);
+ pc += sizeof(cntStat);
+ break;
+
+ case STAT_RXCNT:
+
+ pCh->channelRcount = *((cntStatPtr)pc);
+ pc += sizeof(cntStat);
+ break;
+
+ case STAT_BOXIDS:
+ pB->channelBtypes = *((bidStatPtr)pc);
+ pc += sizeof(bidStat);
+ set_baud_params(pB);
+ break;
+
+ case STAT_HWFAIL:
+ i2QueueCommands (PTYPE_INLINE, pCh, 0, 1, CMD_HW_TEST);
+ pCh->channelFail = *((failStatPtr)pc);
+ pc += sizeof(failStat);
+ break;
+
+ /* No explicit match? then
+ * Might be an error packet...
+ */
+ default:
+ switch (uc & STAT_MOD_ERROR)
+ {
+ case STAT_ERROR:
+ if (uc & STAT_E_PARITY) {
+ pCh->dataSetIn |= I2_PAR;
+ pCh->icount.parity++;
+ }
+ if (uc & STAT_E_FRAMING){
+ pCh->dataSetIn |= I2_FRA;
+ pCh->icount.frame++;
+ }
+ if (uc & STAT_E_OVERRUN){
+ pCh->dataSetIn |= I2_OVR;
+ pCh->icount.overrun++;
+ }
+ break;
+
+ case STAT_MODEM:
+ // the answer to DSS_NOW request (not change)
+ pCh->dataSetIn = (pCh->dataSetIn
+ & ~(I2_RI | I2_CTS | I2_DCD | I2_DSR) )
+ | xlatDss[uc & 0xf];
+ wake_up_interruptible ( &pCh->dss_now_wait );
+ default:
+ break;
+ }
+ } /* End of switch on status type */
+ if (dss_change) {
+#ifdef USE_IQ
+ schedule_work(&pCh->tqueue_status);
+#else
+ do_status(pCh);
+#endif
+ }
+ }
+ else /* Or else, channel is invalid */
+ {
+ // Even though the channel is invalid, we must test the
+ // status to see how much additional data it has (to be
+ // skipped)
+ switch (*pc++)
+ {
+ case STAT_FLOW:
+ pc += 4; /* Skip the data */
+ break;
+
+ default:
+ break;
+ }
+ }
+ } // End of while (there is still some status packet left)
+ break;
+
+ default: // Neither packet? should be impossible
+ ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 5, 1,
+ PTYPE_OF(pB->i2eLeadoffWord) );
+
+ break;
+ } // End of switch on type of packets
+ } //while(board HAS_INPUT)
+
+ ip2trace (ITRC_NO_PORT, ITRC_SFIFO, ITRC_RETURN, 0 );
+
+ // Send acknowledgement to the board even if there was no data!
+ pB->i2eOutMailWaiting |= MB_IN_STRIPPED;
+ return;
+}
+
+//******************************************************************************
+// Function: i2Write2Fifo(pB,address,count)
+// Parameters: Pointer to a board structure, source address, byte count
+// Returns: bytes written
+//
+// Description:
+// Writes count bytes to board io address(implied) from source
+// Adjusts count, leaves reserve for next time around bypass cmds
+//******************************************************************************
+static int
+i2Write2Fifo(i2eBordStrPtr pB, unsigned char *source, int count,int reserve)
+{
+ int rc = 0;
+ unsigned long flags;
+ WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags);
+ if (!pB->i2eWaitingForEmptyFifo) {
+ if (pB->i2eFifoRemains > (count+reserve)) {
+ pB->i2eFifoRemains -= count;
+ iiWriteBuf(pB, source, count);
+ pB->i2eOutMailWaiting |= MB_OUT_STUFFED;
+ rc = count;
+ }
+ }
+ WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags);
+ return rc;
+}
+//******************************************************************************
+// Function: i2StuffFifoBypass(pB)
+// Parameters: Pointer to a board structure
+// Returns: Nothing
+//
+// Description:
+// Stuffs as many bypass commands into the fifo as possible. This is simpler
+// than stuffing data or inline commands to fifo, since we do not have
+// flow-control to deal with.
+//******************************************************************************
+static inline void
+i2StuffFifoBypass(i2eBordStrPtr pB)
+{
+ i2ChanStrPtr pCh;
+ unsigned char *pRemove;
+ unsigned short stripIndex;
+ unsigned short packetSize;
+ unsigned short paddedSize;
+ unsigned short notClogged = 1;
+ unsigned long flags;
+
+ int bailout = 1000;
+
+ // Continue processing so long as there are entries, or there is room in the
+ // fifo. Each entry represents a channel with something to do.
+ while ( --bailout && notClogged &&
+ (NULL != (pCh = i2DeQueueNeeds(pB,NEED_BYPASS))))
+ {
+ WRITE_LOCK_IRQSAVE(&pCh->Cbuf_spinlock,flags);
+ stripIndex = pCh->Cbuf_strip;
+
+ // as long as there are packets for this channel...
+
+ while (stripIndex != pCh->Cbuf_stuff) {
+ pRemove = &(pCh->Cbuf[stripIndex]);
+ packetSize = CMD_COUNT_OF(pRemove) + sizeof(i2CmdHeader);
+ paddedSize = ROUNDUP(packetSize);
+
+ if (paddedSize > 0) {
+ if ( 0 == i2Write2Fifo(pB, pRemove, paddedSize,0)) {
+ notClogged = 0; /* fifo full */
+ i2QueueNeeds(pB, pCh, NEED_BYPASS); // Put back on queue
+ break; // Break from the channel
+ }
+ }
+#ifdef DEBUG_FIFO
+WriteDBGBuf("BYPS", pRemove, paddedSize);
+#endif /* DEBUG_FIFO */
+ pB->debugBypassCount++;
+
+ pRemove += packetSize;
+ stripIndex += packetSize;
+ if (stripIndex >= CBUF_SIZE) {
+ stripIndex = 0;
+ pRemove = pCh->Cbuf;
+ }
+ }
+ // Done with this channel. Move to next, removing this one from
+ // the queue of channels if we cleaned it out (i.e., didn't get clogged.
+ pCh->Cbuf_strip = stripIndex;
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Cbuf_spinlock,flags);
+ } // Either clogged or finished all the work
+
+#ifdef IP2DEBUG_TRACE
+ if ( !bailout ) {
+ ip2trace (ITRC_NO_PORT, ITRC_ERROR, 1, 0 );
+ }
+#endif
+}
+
+//******************************************************************************
+// Function: i2StuffFifoFlow(pB)
+// Parameters: Pointer to a board structure
+// Returns: Nothing
+//
+// Description:
+// Stuffs as many flow control packets into the fifo as possible. This is easier
+// even than doing normal bypass commands, because there is always at most one
+// packet, already assembled, for each channel.
+//******************************************************************************
+static inline void
+i2StuffFifoFlow(i2eBordStrPtr pB)
+{
+ i2ChanStrPtr pCh;
+ unsigned short paddedSize = ROUNDUP(sizeof(flowIn));
+
+ ip2trace (ITRC_NO_PORT, ITRC_SFLOW, ITRC_ENTER, 2,
+ pB->i2eFifoRemains, paddedSize );
+
+ // Continue processing so long as there are entries, or there is room in the
+ // fifo. Each entry represents a channel with something to do.
+ while ( (NULL != (pCh = i2DeQueueNeeds(pB,NEED_FLOW)))) {
+ pB->debugFlowCount++;
+
+ // NO Chan LOCK needed ???
+ if ( 0 == i2Write2Fifo(pB,(unsigned char *)&(pCh->infl),paddedSize,0)) {
+ break;
+ }
+#ifdef DEBUG_FIFO
+ WriteDBGBuf("FLOW",(unsigned char *) &(pCh->infl), paddedSize);
+#endif /* DEBUG_FIFO */
+
+ } // Either clogged or finished all the work
+
+ ip2trace (ITRC_NO_PORT, ITRC_SFLOW, ITRC_RETURN, 0 );
+}
+
+//******************************************************************************
+// Function: i2StuffFifoInline(pB)
+// Parameters: Pointer to a board structure
+// Returns: Nothing
+//
+// Description:
+// Stuffs as much data and inline commands into the fifo as possible. This is
+// the most complex fifo-stuffing operation, since there if now the channel
+// flow-control issue to deal with.
+//******************************************************************************
+static inline void
+i2StuffFifoInline(i2eBordStrPtr pB)
+{
+ i2ChanStrPtr pCh;
+ unsigned char *pRemove;
+ unsigned short stripIndex;
+ unsigned short packetSize;
+ unsigned short paddedSize;
+ unsigned short notClogged = 1;
+ unsigned short flowsize;
+ unsigned long flags;
+
+ int bailout = 1000;
+ int bailout2;
+
+ ip2trace (ITRC_NO_PORT, ITRC_SICMD, ITRC_ENTER, 3, pB->i2eFifoRemains,
+ pB->i2Dbuf_strip, pB->i2Dbuf_stuff );
+
+ // Continue processing so long as there are entries, or there is room in the
+ // fifo. Each entry represents a channel with something to do.
+ while ( --bailout && notClogged &&
+ (NULL != (pCh = i2DeQueueNeeds(pB,NEED_INLINE))) )
+ {
+ WRITE_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags);
+ stripIndex = pCh->Obuf_strip;
+
+ ip2trace (CHANN, ITRC_SICMD, 3, 2, stripIndex, pCh->Obuf_stuff );
+
+ // as long as there are packets for this channel...
+ bailout2 = 1000;
+ while ( --bailout2 && stripIndex != pCh->Obuf_stuff) {
+ pRemove = &(pCh->Obuf[stripIndex]);
+
+ // Must determine whether this be a data or command packet to
+ // calculate correctly the header size and the amount of
+ // flow-control credit this type of packet will use.
+ if (PTYPE_OF(pRemove) == PTYPE_DATA) {
+ flowsize = DATA_COUNT_OF(pRemove);
+ packetSize = flowsize + sizeof(i2DataHeader);
+ } else {
+ flowsize = CMD_COUNT_OF(pRemove);
+ packetSize = flowsize + sizeof(i2CmdHeader);
+ }
+ flowsize = CREDIT_USAGE(flowsize);
+ paddedSize = ROUNDUP(packetSize);
+
+ ip2trace (CHANN, ITRC_SICMD, 4, 2, pB->i2eFifoRemains, paddedSize );
+
+ // If we don't have enough credits from the board to send the data,
+ // flag the channel that we are waiting for flow control credit, and
+ // break out. This will clean up this channel and remove us from the
+ // queue of hot things to do.
+
+ ip2trace (CHANN, ITRC_SICMD, 5, 2, pCh->outfl.room, flowsize );
+
+ if (pCh->outfl.room <= flowsize) {
+ // Do Not have the credits to send this packet.
+ i2QueueNeeds(pB, pCh, NEED_CREDIT);
+ notClogged = 0;
+ break; // So to do next channel
+ }
+ if ( (paddedSize > 0)
+ && ( 0 == i2Write2Fifo(pB, pRemove, paddedSize, 128))) {
+ // Do Not have room in fifo to send this packet.
+ notClogged = 0;
+ i2QueueNeeds(pB, pCh, NEED_INLINE);
+ break; // Break from the channel
+ }
+#ifdef DEBUG_FIFO
+WriteDBGBuf("DATA", pRemove, paddedSize);
+#endif /* DEBUG_FIFO */
+ pB->debugInlineCount++;
+
+ pCh->icount.tx += flowsize;
+ // Update current credits
+ pCh->outfl.room -= flowsize;
+ pCh->outfl.asof += flowsize;
+ if (PTYPE_OF(pRemove) == PTYPE_DATA) {
+ pCh->Obuf_char_count -= DATA_COUNT_OF(pRemove);
+ }
+ pRemove += packetSize;
+ stripIndex += packetSize;
+
+ ip2trace (CHANN, ITRC_SICMD, 6, 2, stripIndex, pCh->Obuf_strip);
+
+ if (stripIndex >= OBUF_SIZE) {
+ stripIndex = 0;
+ pRemove = pCh->Obuf;
+
+ ip2trace (CHANN, ITRC_SICMD, 7, 1, stripIndex );
+
+ }
+ } /* while */
+ if ( !bailout2 ) {
+ ip2trace (CHANN, ITRC_ERROR, 3, 0 );
+ }
+ // Done with this channel. Move to next, removing this one from the
+ // queue of channels if we cleaned it out (i.e., didn't get clogged.
+ pCh->Obuf_strip = stripIndex;
+ WRITE_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags);
+ if ( notClogged )
+ {
+
+ ip2trace (CHANN, ITRC_SICMD, 8, 0 );
+
+ if ( pCh->pTTY ) {
+ ip2_owake(pCh->pTTY);
+ }
+ }
+ } // Either clogged or finished all the work
+
+ if ( !bailout ) {
+ ip2trace (ITRC_NO_PORT, ITRC_ERROR, 4, 0 );
+ }
+
+ ip2trace (ITRC_NO_PORT, ITRC_SICMD, ITRC_RETURN, 1,pB->i2Dbuf_strip);
+}
+
+//******************************************************************************
+// Function: serviceOutgoingFifo(pB)
+// Parameters: Pointer to a board structure
+// Returns: Nothing
+//
+// Description:
+// Helper routine to put data in the outgoing fifo, if we aren't already waiting
+// for something to be there. If the fifo has only room for a very little data,
+// go head and hit the board with a mailbox hit immediately. Otherwise, it will
+// have to happen later in the interrupt processing. Since this routine may be
+// called both at interrupt and foreground time, we must turn off interrupts
+// during the entire process.
+//******************************************************************************
+static void
+serviceOutgoingFifo(i2eBordStrPtr pB)
+{
+ // If we aren't currently waiting for the board to empty our fifo, service
+ // everything that is pending, in priority order (especially, Bypass before
+ // Inline).
+ if ( ! pB->i2eWaitingForEmptyFifo )
+ {
+ i2StuffFifoFlow(pB);
+ i2StuffFifoBypass(pB);
+ i2StuffFifoInline(pB);
+
+ iiSendPendingMail(pB);
+ }
+}
+
+//******************************************************************************
+// Function: i2ServiceBoard(pB)
+// Parameters: Pointer to a board structure
+// Returns: Nothing
+//
+// Description:
+// Normally this is called from interrupt level, but there is deliberately
+// nothing in here specific to being called from interrupt level. All the
+// hardware-specific, interrupt-specific things happen at the outer levels.
+//
+// For example, a timer interrupt could drive this routine for some sort of
+// polled operation. The only requirement is that the programmer deal with any
+// atomiticity/concurrency issues that result.
+//
+// This routine responds to the board's having sent mailbox information to the
+// host (which would normally cause an interrupt). This routine reads the
+// incoming mailbox. If there is no data in it, this board did not create the
+// interrupt and/or has nothing to be done to it. (Except, if we have been
+// waiting to write mailbox data to it, we may do so.
+//
+// Based on the value in the mailbox, we may take various actions.
+//
+// No checking here of pB validity: after all, it shouldn't have been called by
+// the handler unless pB were on the list.
+//******************************************************************************
+static inline int
+i2ServiceBoard ( i2eBordStrPtr pB )
+{
+ unsigned inmail;
+ unsigned long flags;
+
+
+ /* This should be atomic because of the way we are called... */
+ if (NO_MAIL_HERE == ( inmail = pB->i2eStartMail ) ) {
+ inmail = iiGetMail(pB);
+ }
+ pB->i2eStartMail = NO_MAIL_HERE;
+
+ ip2trace (ITRC_NO_PORT, ITRC_INTR, 2, 1, inmail );
+
+ if (inmail != NO_MAIL_HERE) {
+ // If the board has gone fatal, nothing to do but hit a bit that will
+ // alert foreground tasks to protest!
+ if ( inmail & MB_FATAL_ERROR ) {
+ pB->i2eFatal = 1;
+ goto exit_i2ServiceBoard;
+ }
+
+ /* Assuming no fatal condition, we proceed to do work */
+ if ( inmail & MB_IN_STUFFED ) {
+ pB->i2eFifoInInts++;
+ i2StripFifo(pB); /* There might be incoming packets */
+ }
+
+ if (inmail & MB_OUT_STRIPPED) {
+ pB->i2eFifoOutInts++;
+ WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags);
+ pB->i2eFifoRemains = pB->i2eFifoSize;
+ pB->i2eWaitingForEmptyFifo = 0;
+ WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags);
+
+ ip2trace (ITRC_NO_PORT, ITRC_INTR, 30, 1, pB->i2eFifoRemains );
+
+ }
+ serviceOutgoingFifo(pB);
+ }
+
+ ip2trace (ITRC_NO_PORT, ITRC_INTR, 8, 0 );
+
+exit_i2ServiceBoard:
+
+ return 0;
+}
diff --git a/drivers/char/ip2/i2lib.h b/drivers/char/ip2/i2lib.h
new file mode 100644
index 0000000..952e113
--- /dev/null
+++ b/drivers/char/ip2/i2lib.h
@@ -0,0 +1,351 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Header file for high level library functions
+*
+*******************************************************************************/
+#ifndef I2LIB_H
+#define I2LIB_H 1
+//------------------------------------------------------------------------------
+// I2LIB.H
+//
+// IntelliPort-II and IntelliPort-IIEX
+//
+// Defines, structure definitions, and external declarations for i2lib.c
+//------------------------------------------------------------------------------
+//--------------------------------------
+// Mandatory Includes:
+//--------------------------------------
+#include "ip2types.h"
+#include "i2ellis.h"
+#include "i2pack.h"
+#include "i2cmd.h"
+#include <linux/workqueue.h>
+
+//------------------------------------------------------------------------------
+// i2ChanStr -- Channel Structure:
+// Used to track per-channel information for the library routines using standard
+// loadware. Note also, a pointer to an array of these structures is patched
+// into the i2eBordStr (see i2ellis.h)
+//------------------------------------------------------------------------------
+//
+// If we make some limits on the maximum block sizes, we can avoid dealing with
+// buffer wrap. The wrapping of the buffer is based on where the start of the
+// packet is. Then there is always room for the packet contiguously.
+//
+// Maximum total length of an outgoing data or in-line command block. The limit
+// of 36 on data is quite arbitrary and based more on DOS memory limitations
+// than the board interface. However, for commands, the maximum packet length is
+// MAX_CMD_PACK_SIZE, because the field size for the count is only a few bits
+// (see I2PACK.H) in such packets. For data packets, the count field size is not
+// the limiting factor. As of this writing, MAX_OBUF_BLOCK < MAX_CMD_PACK_SIZE,
+// but be careful if wanting to modify either.
+//
+#define MAX_OBUF_BLOCK 36
+
+// Another note on maximum block sizes: we are buffering packets here. Data is
+// put into the buffer (if there is room) regardless of the credits from the
+// board. The board sends new credits whenever it has removed from his buffers a
+// number of characters equal to 80% of total buffer size. (Of course, the total
+// buffer size is what is reported when the very first set of flow control
+// status packets are received from the board. Therefore, to be robust, you must
+// always fill the board to at least 80% of the current credit limit, else you
+// might not give it enough to trigger a new report. These conditions are
+// obtained here so long as the maximum output block size is less than 20% the
+// size of the board's output buffers. This is true at present by "coincidence"
+// or "infernal knowledge": the board's output buffers are at least 700 bytes
+// long (20% = 140 bytes, at least). The 80% figure is "official", so the safest
+// strategy might be to trap the first flow control report and guarantee that
+// the effective maxObufBlock is the minimum of MAX_OBUF_BLOCK and 20% of first
+// reported buffer credit.
+//
+#define MAX_CBUF_BLOCK 6 // Maximum total length of a bypass command block
+
+#define IBUF_SIZE 512 // character capacity of input buffer per channel
+#define OBUF_SIZE 1024// character capacity of output buffer per channel
+#define CBUF_SIZE 10 // character capacity of output bypass buffer
+
+typedef struct _i2ChanStr
+{
+ // First, back-pointers so that given a pointer to this structure, you can
+ // determine the correct board and channel number to reference, (say, when
+ // issuing commands, etc. (Note, channel number is in infl.hd.i2sChannel.)
+
+ int port_index; // Index of port in channel structure array attached
+ // to board structure.
+ PTTY pTTY; // Pointer to tty structure for port (OS specific)
+ USHORT validity; // Indicates whether the given channel has been
+ // initialized, really exists (or is a missing
+ // channel, e.g. channel 9 on an 8-port box.)
+
+ i2eBordStrPtr pMyBord; // Back-pointer to this channel's board structure
+
+ int wopen; // waiting fer carrier
+
+ int throttled; // Set if upper layer can take no data
+
+ int flags; // Defined in tty.h
+
+ PWAITQ open_wait; // Pointer for OS sleep function.
+ PWAITQ close_wait; // Pointer for OS sleep function.
+ PWAITQ delta_msr_wait;// Pointer for OS sleep function.
+ PWAITQ dss_now_wait; // Pointer for OS sleep function.
+
+ struct timer_list BookmarkTimer; // Used by i2DrainOutput
+ wait_queue_head_t pBookmarkWait; // Used by i2DrainOutput
+
+ int BaudBase;
+ int BaudDivisor;
+
+ USHORT ClosingDelay;
+ USHORT ClosingWaitTime;
+
+ volatile
+ flowIn infl; // This structure is initialized as a completely
+ // formed flow-control command packet, and as such
+ // has the channel number, also the capacity and
+ // "as-of" data needed continuously.
+
+ USHORT sinceLastFlow; // Counts the number of characters read from input
+ // buffers, since the last time flow control info
+ // was sent.
+
+ USHORT whenSendFlow; // Determines when new flow control is to be sent to
+ // the board. Note unlike earlier manifestations of
+ // the driver, these packets can be sent from
+ // in-place.
+
+ USHORT channelNeeds; // Bit map of important things which must be done
+ // for this channel. (See bits below )
+
+ volatile
+ flowStat outfl; // Same type of structure is used to hold current
+ // flow control information used to control our
+ // output. "asof" is kept updated as data is sent,
+ // and "room" never goes to zero.
+
+ // The incoming ring buffer
+ // Unlike the outgoing buffers, this holds raw data, not packets. The two
+ // extra bytes are used to hold the byte-padding when there is room for an
+ // odd number of bytes before we must wrap.
+ //
+ UCHAR Ibuf[IBUF_SIZE + 2];
+ volatile
+ USHORT Ibuf_stuff; // Stuffing index
+ volatile
+ USHORT Ibuf_strip; // Stripping index
+
+ // The outgoing ring-buffer: Holds Data and command packets. N.B., even
+ // though these are in the channel structure, the channel is also written
+ // here, the easier to send it to the fifo when ready. HOWEVER, individual
+ // packets here are NOT padded to even length: the routines for writing
+ // blocks to the fifo will pad to even byte counts.
+ //
+ UCHAR Obuf[OBUF_SIZE+MAX_OBUF_BLOCK+4];
+ volatile
+ USHORT Obuf_stuff; // Stuffing index
+ volatile
+ USHORT Obuf_strip; // Stripping index
+ int Obuf_char_count;
+
+ // The outgoing bypass-command buffer. Unlike earlier manifestations, the
+ // flow control packets are sent directly from the structures. As above, the
+ // channel number is included in the packet, but they are NOT padded to even
+ // size.
+ //
+ UCHAR Cbuf[CBUF_SIZE+MAX_CBUF_BLOCK+2];
+ volatile
+ USHORT Cbuf_stuff; // Stuffing index
+ volatile
+ USHORT Cbuf_strip; // Stripping index
+
+ // The temporary buffer for the Linux tty driver PutChar entry.
+ //
+ UCHAR Pbuf[MAX_OBUF_BLOCK - sizeof (i2DataHeader)];
+ volatile
+ USHORT Pbuf_stuff; // Stuffing index
+
+ // The state of incoming data-set signals
+ //
+ USHORT dataSetIn; // Bit-mapped according to below. Also indicates
+ // whether a break has been detected since last
+ // inquiry.
+
+ // The state of outcoming data-set signals (as far as we can tell!)
+ //
+ USHORT dataSetOut; // Bit-mapped according to below.
+
+ // Most recent hot-key identifier detected
+ //
+ USHORT hotKeyIn; // Hot key as sent by the board, HOT_CLEAR indicates
+ // no hot key detected since last examined.
+
+ // Counter of outstanding requests for bookmarks
+ //
+ short bookMarks; // Number of outstanding bookmark requests, (+ive
+ // whenever a bookmark request if queued up, -ive
+ // whenever a bookmark is received).
+
+ // Misc options
+ //
+ USHORT channelOptions; // See below
+
+ // To store various incoming special packets
+ //
+ debugStat channelStatus;
+ cntStat channelRcount;
+ cntStat channelTcount;
+ failStat channelFail;
+
+ // To store the last values for line characteristics we sent to the board.
+ //
+ int speed;
+
+ int flush_flags;
+
+ void (*trace)(unsigned short,unsigned char,unsigned char,unsigned long,...);
+
+ /*
+ * Kernel counters for the 4 input interrupts
+ */
+ struct async_icount icount;
+
+ /*
+ * Task queues for processing input packets from the board.
+ */
+ struct work_struct tqueue_input;
+ struct work_struct tqueue_status;
+ struct work_struct tqueue_hangup;
+
+ rwlock_t Ibuf_spinlock;
+ rwlock_t Obuf_spinlock;
+ rwlock_t Cbuf_spinlock;
+ rwlock_t Pbuf_spinlock;
+
+} i2ChanStr, *i2ChanStrPtr;
+
+//---------------------------------------------------
+// Manifests and bit-maps for elements in i2ChanStr
+//---------------------------------------------------
+//
+// flush flags
+//
+#define STARTFL_FLAG 1
+#define STOPFL_FLAG 2
+
+// validity
+//
+#define CHANNEL_MAGIC_BITS 0xff00
+#define CHANNEL_MAGIC 0x5300 // (validity & CHANNEL_MAGIC_BITS) ==
+ // CHANNEL_MAGIC --> structure good
+
+#define CHANNEL_SUPPORT 0x0001 // Indicates channel is supported, exists,
+ // and passed P.O.S.T.
+
+// channelNeeds
+//
+#define NEED_FLOW 1 // Indicates flow control has been queued
+#define NEED_INLINE 2 // Indicates inline commands or data queued
+#define NEED_BYPASS 4 // Indicates bypass commands queued
+#define NEED_CREDIT 8 // Indicates would be sending except has not sufficient
+ // credit. The data is still in the channel structure,
+ // but the channel is not enqueued in the board
+ // structure again until there is a credit received from
+ // the board.
+
+// dataSetIn (Also the bits for i2GetStatus return value)
+//
+#define I2_DCD 1
+#define I2_CTS 2
+#define I2_DSR 4
+#define I2_RI 8
+
+// dataSetOut (Also the bits for i2GetStatus return value)
+//
+#define I2_DTR 1
+#define I2_RTS 2
+
+// i2GetStatus() can optionally clear these bits
+//
+#define I2_BRK 0x10 // A break was detected
+#define I2_PAR 0x20 // A parity error was received
+#define I2_FRA 0x40 // A framing error was received
+#define I2_OVR 0x80 // An overrun error was received
+
+// i2GetStatus() automatically clears these bits */
+//
+#define I2_DDCD 0x100 // DCD changed from its former value
+#define I2_DCTS 0x200 // CTS changed from its former value
+#define I2_DDSR 0x400 // DSR changed from its former value
+#define I2_DRI 0x800 // RI changed from its former value
+
+// hotKeyIn
+//
+#define HOT_CLEAR 0x1322 // Indicates that no hot-key has been detected
+
+// channelOptions
+//
+#define CO_NBLOCK_WRITE 1 // Writes don't block waiting for buffer. (Default
+ // is, they do wait.)
+
+// fcmodes
+//
+#define I2_OUTFLOW_CTS 0x0001
+#define I2_INFLOW_RTS 0x0002
+#define I2_INFLOW_DSR 0x0004
+#define I2_INFLOW_DTR 0x0008
+#define I2_OUTFLOW_DSR 0x0010
+#define I2_OUTFLOW_DTR 0x0020
+#define I2_OUTFLOW_XON 0x0040
+#define I2_OUTFLOW_XANY 0x0080
+#define I2_INFLOW_XON 0x0100
+
+#define I2_CRTSCTS (I2_OUTFLOW_CTS|I2_INFLOW_RTS)
+#define I2_IXANY_MODE (I2_OUTFLOW_XON|I2_OUTFLOW_XANY)
+
+//-------------------------------------------
+// Macros used from user level like functions
+//-------------------------------------------
+
+// Macros to set and clear channel options
+//
+#define i2SetOption(pCh, option) pCh->channelOptions |= option
+#define i2ClrOption(pCh, option) pCh->channelOptions &= ~option
+
+// Macro to set fatal-error trap
+//
+#define i2SetFatalTrap(pB, routine) pB->i2eFatalTrap = routine
+
+//--------------------------------------------
+// Declarations and prototypes for i2lib.c
+//--------------------------------------------
+//
+static int i2InitChannels(i2eBordStrPtr, int, i2ChanStrPtr);
+static int i2QueueCommands(int, i2ChanStrPtr, int, int, cmdSyntaxPtr,...);
+static int i2GetStatus(i2ChanStrPtr, int);
+static int i2Input(i2ChanStrPtr);
+static int i2InputFlush(i2ChanStrPtr);
+static int i2Output(i2ChanStrPtr, const char *, int, int);
+static int i2OutputFree(i2ChanStrPtr);
+static int i2ServiceBoard(i2eBordStrPtr);
+static void i2DrainOutput(i2ChanStrPtr, int);
+
+#ifdef IP2DEBUG_TRACE
+void ip2trace(unsigned short,unsigned char,unsigned char,unsigned long,...);
+#else
+#define ip2trace(a,b,c,d...) do {} while (0)
+#endif
+
+// Argument to i2QueueCommands
+//
+#define C_IN_LINE 1
+#define C_BYPASS 0
+
+#endif // I2LIB_H
diff --git a/drivers/char/ip2/i2os.h b/drivers/char/ip2/i2os.h
new file mode 100644
index 0000000..eff9b54
--- /dev/null
+++ b/drivers/char/ip2/i2os.h
@@ -0,0 +1,127 @@
+/*******************************************************************************
+*
+* (c) 1999 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Defines, definitions and includes which are heavily dependent
+* on O/S, host, compiler, etc. This file is tailored for:
+* Linux v2.0.0 and later
+* Gnu gcc c2.7.2
+* 80x86 architecture
+*
+*******************************************************************************/
+
+#ifndef I2OS_H /* To prevent multiple includes */
+#define I2OS_H 1
+
+//-------------------------------------------------
+// Required Includes
+//-------------------------------------------------
+
+#include "ip2types.h"
+#include <asm/io.h> /* For inb, etc */
+
+//------------------------------------
+// Defines for I/O instructions:
+//------------------------------------
+
+#define INB(port) inb(port)
+#define OUTB(port,value) outb((value),(port))
+#define INW(port) inw(port)
+#define OUTW(port,value) outw((value),(port))
+#define OUTSW(port,addr,count) outsw((port),(addr),(((count)+1)/2))
+#define OUTSB(port,addr,count) outsb((port),(addr),(((count)+1))&-2)
+#define INSW(port,addr,count) insw((port),(addr),(((count)+1)/2))
+#define INSB(port,addr,count) insb((port),(addr),(((count)+1))&-2)
+
+//--------------------------------------------
+// Interrupt control
+//--------------------------------------------
+
+#define LOCK_INIT(a) rwlock_init(a)
+
+#define SAVE_AND_DISABLE_INTS(a,b) { \
+ /* printk("get_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
+ spin_lock_irqsave(a,b); \
+}
+
+#define RESTORE_INTS(a,b) { \
+ /* printk("rel_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
+ spin_unlock_irqrestore(a,b); \
+}
+
+#define READ_LOCK_IRQSAVE(a,b) { \
+ /* printk("get_read_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
+ read_lock_irqsave(a,b); \
+}
+
+#define READ_UNLOCK_IRQRESTORE(a,b) { \
+ /* printk("rel_read_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
+ read_unlock_irqrestore(a,b); \
+}
+
+#define WRITE_LOCK_IRQSAVE(a,b) { \
+ /* printk("get_write_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
+ write_lock_irqsave(a,b); \
+}
+
+#define WRITE_UNLOCK_IRQRESTORE(a,b) { \
+ /* printk("rel_write_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
+ write_unlock_irqrestore(a,b); \
+}
+
+
+//------------------------------------------------------------------------------
+// Hardware-delay loop
+//
+// Probably used in only one place (see i2ellis.c) but this helps keep things
+// together. Note we have unwound the IN instructions. On machines with a
+// reasonable cache, the eight instructions (1 byte each) should fit in cache
+// nicely, and on un-cached machines, the code-fetch would tend not to dominate.
+// Note that cx is shifted so that "count" still reflects the total number of
+// iterations assuming no unwinding.
+//------------------------------------------------------------------------------
+
+//#define DELAY1MS(port,count,label)
+
+//------------------------------------------------------------------------------
+// Macros to switch to a new stack, saving stack pointers, and to restore the
+// old stack (Used, for example, in i2lib.c) "heap" is the address of some
+// buffer which will become the new stack (working down from highest address).
+// The two words at the two lowest addresses in this stack are for storing the
+// SS and SP.
+//------------------------------------------------------------------------------
+
+//#define TO_NEW_STACK(heap,size)
+//#define TO_OLD_STACK(heap)
+
+//------------------------------------------------------------------------------
+// Macros to save the original IRQ vectors and masks, and to patch in new ones.
+//------------------------------------------------------------------------------
+
+//#define SAVE_IRQ_MASKS(dest)
+//#define WRITE_IRQ_MASKS(src)
+//#define SAVE_IRQ_VECTOR(value,dest)
+//#define WRITE_IRQ_VECTOR(value,src)
+
+//------------------------------------------------------------------------------
+// Macro to copy data from one far pointer to another.
+//------------------------------------------------------------------------------
+
+#define I2_MOVE_DATA(fpSource,fpDest,count) memmove(fpDest,fpSource,count);
+
+//------------------------------------------------------------------------------
+// Macros to issue eoi's to host interrupt control (IBM AT 8259-style).
+//------------------------------------------------------------------------------
+
+//#define MASTER_EOI
+//#define SLAVE_EOI
+
+#endif /* I2OS_H */
+
+
diff --git a/drivers/char/ip2/i2pack.h b/drivers/char/ip2/i2pack.h
new file mode 100644
index 0000000..e9b87a7
--- /dev/null
+++ b/drivers/char/ip2/i2pack.h
@@ -0,0 +1,364 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Definitions of the packets used to transfer data and commands
+* Host <--> Board. Information provided here is only applicable
+* when the standard loadware is active.
+*
+*******************************************************************************/
+#ifndef I2PACK_H
+#define I2PACK_H 1
+
+//-----------------------------------------------
+// Revision History:
+//
+// 10 October 1991 MAG First draft
+// 24 February 1992 MAG Additions for 1.4.x loadware
+// 11 March 1992 MAG New status packets
+//
+//-----------------------------------------------
+
+//------------------------------------------------------------------------------
+// Packet Formats:
+//
+// Information passes between the host and board through the FIFO in packets.
+// These have headers which indicate the type of packet. Because the fifo data
+// path may be 16-bits wide, the protocol is constrained such that each packet
+// is always padded to an even byte count. (The lower-level interface routines
+// -- i2ellis.c -- are designed to do this).
+//
+// The sender (be it host or board) must place some number of complete packets
+// in the fifo, then place a message in the mailbox that packets are available.
+// Placing such a message interrupts the "receiver" (be it board or host), who
+// reads the mailbox message and determines that there are incoming packets
+// ready. Since there are no partial packets, and the length of a packet is
+// given in the header, the remainder of the packet can be read without checking
+// for FIFO empty condition. The process is repeated, packet by packet, until
+// the incoming FIFO is empty. Then the receiver uses the outbound mailbox to
+// signal the board that it has read the data. Only then can the sender place
+// additional data in the fifo.
+//------------------------------------------------------------------------------
+//
+//------------------------------------------------
+// Definition of Packet Header Area
+//------------------------------------------------
+//
+// Caution: these only define header areas. In actual use the data runs off
+// beyond the end of these structures.
+//
+// Since these structures are based on sequences of bytes which go to the board,
+// there cannot be ANY padding between the elements.
+#pragma pack(1)
+
+//----------------------------
+// DATA PACKETS
+//----------------------------
+
+typedef struct _i2DataHeader
+{
+ unsigned char i2sChannel; /* The channel number: 0-255 */
+
+ // -- Bitfields are allocated LSB first --
+
+ // For incoming data, indicates whether this is an ordinary packet or a
+ // special one (e.g., hot key hit).
+ unsigned i2sId : 2 __attribute__ ((__packed__));
+
+ // For tagging data packets. There are flush commands which flush only data
+ // packets bearing a particular tag. (used in implementing IntelliView and
+ // IntelliPrint). THE TAG VALUE 0xf is RESERVED and must not be used (it has
+ // meaning internally to the loadware).
+ unsigned i2sTag : 4;
+
+ // These two bits determine the type of packet sent/received.
+ unsigned i2sType : 2;
+
+ // The count of data to follow: does not include the possible additional
+ // padding byte. MAXIMUM COUNT: 4094. The top four bits must be 0.
+ unsigned short i2sCount;
+
+} i2DataHeader, *i2DataHeaderPtr;
+
+// Structure is immediately followed by the data, proper.
+
+//----------------------------
+// NON-DATA PACKETS
+//----------------------------
+
+typedef struct _i2CmdHeader
+{
+ unsigned char i2sChannel; // The channel number: 0-255 (Except where noted
+ // - see below
+
+ // Number of bytes of commands, status or whatever to follow
+ unsigned i2sCount : 6;
+
+ // These two bits determine the type of packet sent/received.
+ unsigned i2sType : 2;
+
+} i2CmdHeader, *i2CmdHeaderPtr;
+
+// Structure is immediately followed by the applicable data.
+
+//---------------------------------------
+// Flow Control Packets (Outbound)
+//---------------------------------------
+
+// One type of outbound command packet is so important that the entire structure
+// is explicitly defined here. That is the flow-control packet. This is never
+// sent by user-level code (as would be the commands to raise/lower DTR, for
+// example). These are only sent by the library routines in response to reading
+// incoming data into the buffers.
+//
+// The parameters inside the command block are maintained in place, then the
+// block is sent at the appropriate time.
+
+typedef struct _flowIn
+{
+ i2CmdHeader hd; // Channel #, count, type (see above)
+ unsigned char fcmd; // The flow control command (37)
+ unsigned short asof; // As of byte number "asof" (LSB first!) I have room
+ // for "room" bytes
+ unsigned short room;
+} flowIn, *flowInPtr;
+
+//----------------------------------------
+// (Incoming) Status Packets
+//----------------------------------------
+
+// Incoming packets which are non-data packets are status packets. In this case,
+// the channel number in the header is unimportant. What follows are one or more
+// sub-packets, the first word of which consists of the channel (first or low
+// byte) and the status indicator (second or high byte), followed by possibly
+// more data.
+
+#define STAT_CTS_UP 0 /* CTS raised (no other bytes) */
+#define STAT_CTS_DN 1 /* CTS dropped (no other bytes) */
+#define STAT_DCD_UP 2 /* DCD raised (no other bytes) */
+#define STAT_DCD_DN 3 /* DCD dropped (no other bytes) */
+#define STAT_DSR_UP 4 /* DSR raised (no other bytes) */
+#define STAT_DSR_DN 5 /* DSR dropped (no other bytes) */
+#define STAT_RI_UP 6 /* RI raised (no other bytes) */
+#define STAT_RI_DN 7 /* RI dropped (no other bytes) */
+#define STAT_BRK_DET 8 /* BRK detect (no other bytes) */
+#define STAT_FLOW 9 /* Flow control(-- more: see below */
+#define STAT_BMARK 10 /* Bookmark (no other bytes)
+ * Bookmark is sent as a response to
+ * a command 60: request for bookmark
+ */
+#define STAT_STATUS 11 /* Special packet: see below */
+#define STAT_TXCNT 12 /* Special packet: see below */
+#define STAT_RXCNT 13 /* Special packet: see below */
+#define STAT_BOXIDS 14 /* Special packet: see below */
+#define STAT_HWFAIL 15 /* Special packet: see below */
+
+#define STAT_MOD_ERROR 0xc0
+#define STAT_MODEM 0xc0/* If status & STAT_MOD_ERROR:
+ * == STAT_MODEM, then this is a modem
+ * status packet, given in response to a
+ * CMD_DSS_NOW command.
+ * The low nibble has each data signal:
+ */
+#define STAT_MOD_DCD 0x8
+#define STAT_MOD_RI 0x4
+#define STAT_MOD_DSR 0x2
+#define STAT_MOD_CTS 0x1
+
+#define STAT_ERROR 0x80/* If status & STAT_MOD_ERROR
+ * == STAT_ERROR, then
+ * sort of error on the channel.
+ * The remaining seven bits indicate
+ * what sort of error it is.
+ */
+/* The low three bits indicate parity, framing, or overrun errors */
+
+#define STAT_E_PARITY 4 /* Parity error */
+#define STAT_E_FRAMING 2 /* Framing error */
+#define STAT_E_OVERRUN 1 /* (uxart) overrun error */
+
+//---------------------------------------
+// STAT_FLOW packets
+//---------------------------------------
+
+typedef struct _flowStat
+{
+ unsigned short asof;
+ unsigned short room;
+}flowStat, *flowStatPtr;
+
+// flowStat packets are received from the board to regulate the flow of outgoing
+// data. A local copy of this structure is also kept to track the amount of
+// credits used and credits remaining. "room" is the amount of space in the
+// board's buffers, "as of" having received a certain byte number. When sending
+// data to the fifo, you must calculate how much buffer space your packet will
+// use. Add this to the current "asof" and subtract it from the current "room".
+//
+// The calculation for the board's buffer is given by CREDIT_USAGE, where size
+// is the un-rounded count of either data characters or command characters.
+// (Which is to say, the count rounded up, plus two).
+
+#define CREDIT_USAGE(size) (((size) + 3) & ~1)
+
+//---------------------------------------
+// STAT_STATUS packets
+//---------------------------------------
+
+typedef struct _debugStat
+{
+ unsigned char d_ccsr;
+ unsigned char d_txinh;
+ unsigned char d_stat1;
+ unsigned char d_stat2;
+} debugStat, *debugStatPtr;
+
+// debugStat packets are sent to the host in response to a CMD_GET_STATUS
+// command. Each byte is bit-mapped as described below:
+
+#define D_CCSR_XON 2 /* Has received XON, ready to transmit */
+#define D_CCSR_XOFF 4 /* Has received XOFF, not transmitting */
+#define D_CCSR_TXENAB 8 /* Transmitter is enabled */
+#define D_CCSR_RXENAB 0x80 /* Receiver is enabled */
+
+#define D_TXINH_BREAK 1 /* We are sending a break */
+#define D_TXINH_EMPTY 2 /* No data to send */
+#define D_TXINH_SUSP 4 /* Output suspended via command 57 */
+#define D_TXINH_CMD 8 /* We are processing an in-line command */
+#define D_TXINH_LCD 0x10 /* LCD diagnostics are running */
+#define D_TXINH_PAUSE 0x20 /* We are processing a PAUSE command */
+#define D_TXINH_DCD 0x40 /* DCD is low, preventing transmission */
+#define D_TXINH_DSR 0x80 /* DSR is low, preventing transmission */
+
+#define D_STAT1_TXEN 1 /* Transmit INTERRUPTS enabled */
+#define D_STAT1_RXEN 2 /* Receiver INTERRUPTS enabled */
+#define D_STAT1_MDEN 4 /* Modem (data set sigs) interrupts enabled */
+#define D_STAT1_RLM 8 /* Remote loopback mode selected */
+#define D_STAT1_LLM 0x10 /* Local internal loopback mode selected */
+#define D_STAT1_CTS 0x20 /* CTS is low, preventing transmission */
+#define D_STAT1_DTR 0x40 /* DTR is low, to stop remote transmission */
+#define D_STAT1_RTS 0x80 /* RTS is low, to stop remote transmission */
+
+#define D_STAT2_TXMT 1 /* Transmit buffers are all empty */
+#define D_STAT2_RXMT 2 /* Receive buffers are all empty */
+#define D_STAT2_RXINH 4 /* Loadware has tried to inhibit remote
+ * transmission: dropped DTR, sent XOFF,
+ * whatever...
+ */
+#define D_STAT2_RXFLO 8 /* Loadware can send no more data to host
+ * until it receives a flow-control packet
+ */
+//-----------------------------------------
+// STAT_TXCNT and STAT_RXCNT packets
+//----------------------------------------
+
+typedef struct _cntStat
+{
+ unsigned short cs_time; // (Assumes host is little-endian!)
+ unsigned short cs_count;
+} cntStat, *cntStatPtr;
+
+// These packets are sent in response to a CMD_GET_RXCNT or a CMD_GET_TXCNT
+// bypass command. cs_time is a running 1 Millisecond counter which acts as a
+// time stamp. cs_count is a running counter of data sent or received from the
+// uxarts. (Not including data added by the chip itself, as with CRLF
+// processing).
+//------------------------------------------
+// STAT_HWFAIL packets
+//------------------------------------------
+
+typedef struct _failStat
+{
+ unsigned char fs_written;
+ unsigned char fs_read;
+ unsigned short fs_address;
+} failStat, *failStatPtr;
+
+// This packet is sent whenever the on-board diagnostic process detects an
+// error. At startup, this process is dormant. The host can wake it up by
+// issuing the bypass command CMD_HW_TEST. The process runs at low priority and
+// performs continuous hardware verification; writing data to certain on-board
+// registers, reading it back, and comparing. If it detects an error, this
+// packet is sent to the host, and the process goes dormant again until the host
+// sends another CMD_HW_TEST. It then continues with the next register to be
+// tested.
+
+//------------------------------------------------------------------------------
+// Macros to deal with the headers more easily! Note that these are defined so
+// they may be used as "left" as well as "right" expressions.
+//------------------------------------------------------------------------------
+
+// Given a pointer to the packet, reference the channel number
+//
+#define CHANNEL_OF(pP) ((i2DataHeaderPtr)(pP))->i2sChannel
+
+// Given a pointer to the packet, reference the Packet type
+//
+#define PTYPE_OF(pP) ((i2DataHeaderPtr)(pP))->i2sType
+
+// The possible types of packets
+//
+#define PTYPE_DATA 0 /* Host <--> Board */
+#define PTYPE_BYPASS 1 /* Host ---> Board */
+#define PTYPE_INLINE 2 /* Host ---> Board */
+#define PTYPE_STATUS 2 /* Host <--- Board */
+
+// Given a pointer to a Data packet, reference the Tag
+//
+#define TAG_OF(pP) ((i2DataHeaderPtr)(pP))->i2sTag
+
+// Given a pointer to a Data packet, reference the data i.d.
+//
+#define ID_OF(pP) ((i2DataHeaderPtr)(pP))->i2sId
+
+// The possible types of ID's
+//
+#define ID_ORDINARY_DATA 0
+#define ID_HOT_KEY 1
+
+// Given a pointer to a Data packet, reference the count
+//
+#define DATA_COUNT_OF(pP) ((i2DataHeaderPtr)(pP))->i2sCount
+
+// Given a pointer to a Data packet, reference the beginning of data
+//
+#define DATA_OF(pP) &((unsigned char *)(pP))[4] // 4 = size of header
+
+// Given a pointer to a Non-Data packet, reference the count
+//
+#define CMD_COUNT_OF(pP) ((i2CmdHeaderPtr)(pP))->i2sCount
+
+#define MAX_CMD_PACK_SIZE 62 // Maximum size of such a count
+
+// Given a pointer to a Non-Data packet, reference the beginning of data
+//
+#define CMD_OF(pP) &((unsigned char *)(pP))[2] // 2 = size of header
+
+//--------------------------------
+// MailBox Bits:
+//--------------------------------
+
+//--------------------------
+// Outgoing (host to board)
+//--------------------------
+//
+#define MB_OUT_STUFFED 0x80 // Host has placed output in fifo
+#define MB_IN_STRIPPED 0x40 // Host has read in all input from fifo
+
+//--------------------------
+// Incoming (board to host)
+//--------------------------
+//
+#define MB_IN_STUFFED 0x80 // Board has placed input in fifo
+#define MB_OUT_STRIPPED 0x40 // Board has read all output from fifo
+#define MB_FATAL_ERROR 0x20 // Board has encountered a fatal error
+
+#pragma pack(4) // Reset padding to command-line default
+
+#endif // I2PACK_H
+
diff --git a/drivers/char/ip2/ip2.h b/drivers/char/ip2/ip2.h
new file mode 100644
index 0000000..936ccc5
--- /dev/null
+++ b/drivers/char/ip2/ip2.h
@@ -0,0 +1,107 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Driver constants for configuration and tuning
+*
+* NOTES:
+*
+*******************************************************************************/
+#ifndef IP2_H
+#define IP2_H
+
+#include "ip2types.h"
+#include "i2cmd.h"
+
+/*************/
+/* Constants */
+/*************/
+
+/* Device major numbers - since version 2.0.26. */
+#define IP2_TTY_MAJOR 71
+#define IP2_CALLOUT_MAJOR 72
+#define IP2_IPL_MAJOR 73
+
+/* Board configuration array.
+ * This array defines the hardware irq and address for up to IP2_MAX_BOARDS
+ * (4 supported per ip2_types.h) ISA board addresses and irqs MUST be specified,
+ * PCI and EISA boards are probed for and automagicly configed
+ * iff the addresses are set to 1 and 2 respectivily.
+ * 0x0100 - 0x03f0 == ISA
+ * 1 == PCI
+ * 2 == EISA
+ * 0 == (skip this board)
+ * This array defines the hardware addresses for them. Special
+ * addresses are EISA and PCI which go sniffing for boards.
+
+ * In a multiboard system the position in the array determines which port
+ * devices are assigned to each board:
+ * board 0 is assigned ttyF0.. to ttyF63,
+ * board 1 is assigned ttyF64 to ttyF127,
+ * board 2 is assigned ttyF128 to ttyF191,
+ * board 3 is assigned ttyF192 to ttyF255.
+ *
+ * In PCI and EISA bus systems each range is mapped to card in
+ * monotonically increasing slot number order, ISA position is as specified
+ * here.
+
+ * If the irqs are ALL set to 0,0,0,0 all boards operate in
+ * polled mode. For interrupt operation ISA boards require that the IRQ be
+ * specified, while PCI and EISA boards any nonzero entry
+ * will enable interrupts using the BIOS configured irq for the board.
+ * An invalid irq entry will default to polled mode for that card and print
+ * console warning.
+
+ * When the driver is loaded as a module these setting can be overridden on the
+ * modprobe command line or on an option line in /etc/modprobe.conf.
+ * If the driver is built-in the configuration must be
+ * set here for ISA cards and address set to 1 and 2 for PCI and EISA.
+ *
+ * Here is an example that shows most if not all possibe combinations:
+
+ *static ip2config_t ip2config =
+ *{
+ * {11,1,0,0}, // irqs
+ * { // Addresses
+ * 0x0308, // Board 0, ttyF0 - ttyF63// ISA card at io=0x308, irq=11
+ * 0x0001, // Board 1, ttyF64 - ttyF127//PCI card configured by BIOS
+ * 0x0000, // Board 2, ttyF128 - ttyF191// Slot skipped
+ * 0x0002 // Board 3, ttyF192 - ttyF255//EISA card configured by BIOS
+ * // but polled not irq driven
+ * }
+ *};
+ */
+
+ /* this structure is zeroed out because the suggested method is to configure
+ * the driver as a module, set up the parameters with an options line in
+ * /etc/modprobe.conf and load with modprobe or kmod, the kernel
+ * module loader
+ */
+
+ /* This structure is NOW always initialized when the driver is initialized.
+ * Compiled in defaults MUST be added to the io and irq arrays in
+ * ip2.c. Those values are configurable from insmod parameters in the
+ * case of modules or from command line parameters (ip2=io,irq) when
+ * compiled in.
+ */
+
+static ip2config_t ip2config =
+{
+ {0,0,0,0}, // irqs
+ { // Addresses
+ /* Do NOT set compile time defaults HERE! Use the arrays in
+ ip2.c! These WILL be overwritten! =mhw= */
+ 0x0000, // Board 0, ttyF0 - ttyF63
+ 0x0000, // Board 1, ttyF64 - ttyF127
+ 0x0000, // Board 2, ttyF128 - ttyF191
+ 0x0000 // Board 3, ttyF192 - ttyF255
+ }
+};
+
+#endif
diff --git a/drivers/char/ip2/ip2ioctl.h b/drivers/char/ip2/ip2ioctl.h
new file mode 100644
index 0000000..aa0a9da
--- /dev/null
+++ b/drivers/char/ip2/ip2ioctl.h
@@ -0,0 +1,35 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Driver constants for configuration and tuning
+*
+* NOTES:
+*
+*******************************************************************************/
+
+#ifndef IP2IOCTL_H
+#define IP2IOCTL_H
+
+//*************
+//* Constants *
+//*************
+
+// High baud rates (if not defined elsewhere.
+#ifndef B153600
+# define B153600 0010005
+#endif
+#ifndef B307200
+# define B307200 0010006
+#endif
+#ifndef B921600
+# define B921600 0010007
+#endif
+
+#endif
diff --git a/drivers/char/ip2/ip2trace.h b/drivers/char/ip2/ip2trace.h
new file mode 100644
index 0000000..da20435
--- /dev/null
+++ b/drivers/char/ip2/ip2trace.h
@@ -0,0 +1,42 @@
+
+//
+union ip2breadcrumb
+{
+ struct {
+ unsigned char port, cat, codes, label;
+ } __attribute__ ((packed)) hdr;
+ unsigned long value;
+};
+
+#define ITRC_NO_PORT 0xFF
+#define CHANN (pCh->port_index)
+
+#define ITRC_ERROR '!'
+#define ITRC_INIT 'A'
+#define ITRC_OPEN 'B'
+#define ITRC_CLOSE 'C'
+#define ITRC_DRAIN 'D'
+#define ITRC_IOCTL 'E'
+#define ITRC_FLUSH 'F'
+#define ITRC_STATUS 'G'
+#define ITRC_HANGUP 'H'
+#define ITRC_INTR 'I'
+#define ITRC_SFLOW 'J'
+#define ITRC_SBCMD 'K'
+#define ITRC_SICMD 'L'
+#define ITRC_MODEM 'M'
+#define ITRC_INPUT 'N'
+#define ITRC_OUTPUT 'O'
+#define ITRC_PUTC 'P'
+#define ITRC_QUEUE 'Q'
+#define ITRC_STFLW 'R'
+#define ITRC_SFIFO 'S'
+#define ITRC_VERIFY 'V'
+#define ITRC_WRITE 'W'
+
+#define ITRC_ENTER 0x00
+#define ITRC_RETURN 0xFF
+
+#define ITRC_QUEUE_ROOM 2
+#define ITRC_QUEUE_CMD 6
+
diff --git a/drivers/char/ip2/ip2types.h b/drivers/char/ip2/ip2types.h
new file mode 100644
index 0000000..9d67b26
--- /dev/null
+++ b/drivers/char/ip2/ip2types.h
@@ -0,0 +1,57 @@
+/*******************************************************************************
+*
+* (c) 1998 by Computone Corporation
+*
+********************************************************************************
+*
+*
+* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
+* serial I/O controllers.
+*
+* DESCRIPTION: Driver constants and type definitions.
+*
+* NOTES:
+*
+*******************************************************************************/
+#ifndef IP2TYPES_H
+#define IP2TYPES_H
+
+//*************
+//* Constants *
+//*************
+
+// Define some limits for this driver. Ports per board is a hardware limitation
+// that will not change. Current hardware limits this to 64 ports per board.
+// Boards per driver is a self-imposed limit.
+//
+#define IP2_MAX_BOARDS 4
+#define IP2_PORTS_PER_BOARD ABS_MOST_PORTS
+#define IP2_MAX_PORTS (IP2_MAX_BOARDS*IP2_PORTS_PER_BOARD)
+
+#define ISA 0
+#define PCI 1
+#define EISA 2
+
+//********************
+//* Type Definitions *
+//********************
+
+typedef struct tty_struct * PTTY;
+typedef wait_queue_head_t PWAITQ;
+
+typedef unsigned char UCHAR;
+typedef unsigned int UINT;
+typedef unsigned short USHORT;
+typedef unsigned long ULONG;
+
+typedef struct
+{
+ short irq[IP2_MAX_BOARDS];
+ unsigned short addr[IP2_MAX_BOARDS];
+ int type[IP2_MAX_BOARDS];
+#ifdef CONFIG_PCI
+ struct pci_dev *pci_dev[IP2_MAX_BOARDS];
+#endif
+} ip2config_t;
+
+#endif