drm/nv50: initial work to allow multiple evo channels
This doesn't work yet for unknown reasons.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index 211f5fb..dbad233 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -29,22 +29,26 @@
#include "nouveau_ramht.h"
static void
-nv50_evo_channel_del(struct nouveau_channel **pchan)
+nv50_evo_channel_del(struct nouveau_channel **pevo)
{
- struct nouveau_channel *chan = *pchan;
+ struct drm_nouveau_private *dev_priv;
+ struct nouveau_channel *evo = *pevo;
- if (!chan)
+ if (!evo)
return;
- *pchan = NULL;
+ *pevo = NULL;
- nouveau_gpuobj_channel_takedown(chan);
- nouveau_bo_unmap(chan->pushbuf_bo);
- nouveau_bo_ref(NULL, &chan->pushbuf_bo);
+ dev_priv = evo->dev->dev_private;
+ dev_priv->evo_alloc &= ~(1 << evo->id);
- if (chan->user)
- iounmap(chan->user);
+ nouveau_gpuobj_channel_takedown(evo);
+ nouveau_bo_unmap(evo->pushbuf_bo);
+ nouveau_bo_ref(NULL, &evo->pushbuf_bo);
- kfree(chan);
+ if (evo->user)
+ iounmap(evo->user);
+
+ kfree(evo);
}
int
@@ -56,7 +60,7 @@
struct nouveau_gpuobj *obj = NULL;
int ret;
- ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
+ ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
if (ret)
return ret;
obj->engine = NVOBJ_ENGINE_DISPLAY;
@@ -82,101 +86,63 @@
}
static int
-nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
+nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_gpuobj *ramht = NULL;
- struct nouveau_channel *chan;
+ struct nouveau_channel *evo;
int ret;
- chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
- if (!chan)
+ evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
+ if (!evo)
return -ENOMEM;
- *pchan = chan;
+ *pevo = evo;
- chan->id = -1;
- chan->dev = dev;
- chan->user_get = 4;
- chan->user_put = 0;
+ for (evo->id = 0; evo->id < 5; evo->id++) {
+ if (dev_priv->evo_alloc & (1 << evo->id))
+ continue;
- ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
- if (ret) {
- NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
- nv50_evo_channel_del(pchan);
- return ret;
+ dev_priv->evo_alloc |= (1 << evo->id);
+ break;
}
- ret = drm_mm_init(&chan->ramin_heap, 0, 32768);
- if (ret) {
- NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
- nv50_evo_channel_del(pchan);
- return ret;
+ if (evo->id == 5) {
+ kfree(evo);
+ return -ENODEV;
}
- ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
- if (ret) {
- NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
- nv50_evo_channel_del(pchan);
- return ret;
- }
-
- ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
- nouveau_gpuobj_ref(NULL, &ramht);
- if (ret) {
- nv50_evo_channel_del(pchan);
- return ret;
- }
-
- if (dev_priv->chipset != 0x50) {
- ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
- 0, 0xffffffff);
- if (ret) {
- nv50_evo_channel_del(pchan);
- return ret;
- }
-
-
- ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
- 0, 0xffffffff);
- if (ret) {
- nv50_evo_channel_del(pchan);
- return ret;
- }
- }
-
- ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
- 0, dev_priv->vram_size);
- if (ret) {
- nv50_evo_channel_del(pchan);
- return ret;
- }
+ evo->dev = dev;
+ evo->user_get = 4;
+ evo->user_put = 0;
ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
- false, true, &chan->pushbuf_bo);
+ false, true, &evo->pushbuf_bo);
if (ret == 0)
- ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
+ ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
if (ret) {
NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
- nv50_evo_channel_del(pchan);
+ nv50_evo_channel_del(pevo);
return ret;
}
- ret = nouveau_bo_map(chan->pushbuf_bo);
+ ret = nouveau_bo_map(evo->pushbuf_bo);
if (ret) {
NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
- nv50_evo_channel_del(pchan);
+ nv50_evo_channel_del(pevo);
return ret;
}
- chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
- NV50_PDISPLAY_USER(0), PAGE_SIZE);
- if (!chan->user) {
+ evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
+ NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
+ if (!evo->user) {
NV_ERROR(dev, "Error mapping EVO control regs.\n");
- nv50_evo_channel_del(pchan);
+ nv50_evo_channel_del(pevo);
return -ENOMEM;
}
+ /* bind primary evo channel's ramht to the channel */
+ if (dev_priv->evo && evo != dev_priv->evo)
+ nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);
+
return 0;
}
@@ -186,7 +152,7 @@
struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
struct drm_device *dev = evo->dev;
- int ret, i;
+ int id = evo->id, ret, i;
u64 start;
u32 tmp;
@@ -194,13 +160,13 @@
* stuck in some unspecified state
*/
start = ptimer->read(dev);
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x2b00);
- while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0))) & 0x1e0000) {
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x2b00);
+ while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))) & 0x1e0000) {
if ((tmp & 0x9f0000) == 0x20000)
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), tmp | 0x800000);
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x800000);
if ((tmp & 0x3f0000) == 0x30000)
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), tmp | 0x200000);
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x200000);
if (ptimer->read(dev) - start > 1000000000ULL) {
NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
@@ -209,36 +175,37 @@
}
}
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x1000b03);
- if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(0),
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x1000b03);
+ if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id),
0x40000000, 0x40000000)) {
NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
NV_ERROR(dev, "0x610200 = 0x%08x\n",
- nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0)));
+ nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
return -EBUSY;
}
/* initialise fifo */
- nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(0),
+ nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id),
((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
NV50_PDISPLAY_EVO_DMA_CB_VALID);
- nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(0), 0x00010000);
- nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(0), 0x00000002);
- if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
+ nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
+ nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
+ if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
- NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
+ NV_ERROR(dev, "0x610200 = 0x%08x\n",
+ nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
return -EBUSY;
}
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0),
- (nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0)) & ~0x00000003) |
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id),
+ (nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)) & ~0x00000003) |
NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
- nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x01000003 |
- NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
+ nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0);
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
+ NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
/* enable error reporting on the channel */
- nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << 0);
+ nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
evo->dma.max = (4096/4) - 2;
evo->dma.put = 0;
@@ -260,14 +227,91 @@
{
struct drm_device *dev = evo->dev;
- nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0);
- if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x1e0000, 0)) {
+ nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0);
+ if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0x1e0000, 0)) {
NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
NV_ERROR(dev, "0x610200 = 0x%08x\n",
- nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0)));
+ nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id)));
}
}
+static int
+nv50_evo_create(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *ramht = NULL;
+ struct nouveau_channel *evo;
+ int ret;
+
+ /* create primary evo channel, the one we use for modesetting
+ * purporses
+ */
+ ret = nv50_evo_channel_new(dev, &dev_priv->evo);
+ if (ret)
+ return ret;
+ evo = dev_priv->evo;
+
+ /* setup object management on it, any other evo channel will
+ * use this also as there's no per-channel support on the
+ * hardware
+ */
+ ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
+ if (ret) {
+ NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+
+ ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
+ if (ret) {
+ NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+
+ ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
+ if (ret) {
+ NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+
+ ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
+ nouveau_gpuobj_ref(NULL, &ramht);
+ if (ret) {
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+
+ /* create some default objects for the scanout memtypes we support */
+ if (dev_priv->chipset != 0x50) {
+ ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
+ 0, 0xffffffff);
+ if (ret) {
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+
+
+ ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
+ 0, 0xffffffff);
+ if (ret) {
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+ }
+
+ ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
+ 0, dev_priv->vram_size);
+ if (ret) {
+ nv50_evo_channel_del(&dev_priv->evo);
+ return ret;
+ }
+
+ return 0;
+}
+
int
nv50_evo_init(struct drm_device *dev)
{
@@ -275,7 +319,7 @@
int ret;
if (!dev_priv->evo) {
- ret = nv50_evo_channel_new(dev, &dev_priv->evo);
+ ret = nv50_evo_create(dev);
if (ret)
return ret;
}