commit 2745932495ca3634b11a8662b464d2bf0325ae78
author Rafał Miłecki <zajec5@gmail.com> Thu Feb 11 22:16:36 2010 +0000
committer Dave Airlie <airlied@redhat.com> Thu Feb 18 14:25:08 2010 +1000
tree 86194330d087c59c87a872a73eae82ff72da45e0
parent 5230aea62c0d8f53edcc3e014c3404132afcfeb4

drm/radeon/kms: accept slightly overclocked power modes

Fixes fdo bug #26329

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Tested-by: Tobias Jakobi <liquid.acid@gmx.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/gpu/drm/radeon/radeon_atombios.c

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 4f7dbce..731210b 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1463,9 +1463,9 @@
 						continue;
 					/* skip overclock modes for now */
 					if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
-					     rdev->clock.default_mclk) ||
+					     rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
 					    (rdev->pm.power_state[state_index].clock_info[0].sclk >
-					     rdev->clock.default_sclk))
+					     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
 						continue;
 					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
 						power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
@@ -1528,9 +1528,9 @@
 						continue;
 					/* skip overclock modes for now */
 					if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
-					     rdev->clock.default_mclk) ||
+					     rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
 					    (rdev->pm.power_state[state_index].clock_info[0].sclk >
-					     rdev->clock.default_sclk))
+					     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
 						continue;
 					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
 						power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
@@ -1597,9 +1597,9 @@
 						continue;
 					/* skip overclock modes for now */
 					if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
-					     rdev->clock.default_mclk) ||
+					     rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
 					    (rdev->pm.power_state[state_index].clock_info[0].sclk >
-					     rdev->clock.default_sclk))
+					     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
 						continue;
 					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
 						power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
@@ -1693,7 +1693,7 @@
 							continue;
 						/* skip overclock modes for now */
 						if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
-						    rdev->clock.default_sclk)
+						    rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
 							continue;
 						rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
 							VOLTAGE_SW;
@@ -1720,9 +1720,9 @@
 							continue;
 						/* skip overclock modes for now */
 						if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
-						     rdev->clock.default_mclk) ||
+						     rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
 						    (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
-						     rdev->clock.default_sclk))
+						     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
 							continue;
 						rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
 							VOLTAGE_SW;