| commit | 27a5bd6457c8ce38151250530152e15f76b697a8 | [log] [tgz] |
|---|---|---|
| author | David Daney <ddaney@caviumnetworks.com> | Wed Feb 10 15:12:49 2010 -0800 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Sat Feb 27 12:53:26 2010 +0100 |
| tree | 97c50c1773a1ebe7604b8a8c4f046718941fc504 | |
| parent | 6f329468f3086e9d8f3832930fdb09ab3769176b [diff] [blame] |
MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 425e708..bbf0540 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,6 +58,9 @@ #define cpu_has_vint 0 #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 + +#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) + #define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1