mm-camera: configure the mipi csi based on lanecount
The mipi phy control is configured based on the number of lanes
used by the sensor.The mipi reset is placed in a seperate
function.
CRs-Fixed: 311858
Change-Id: I3e8c47196a25ebb9eddc83ed8d8bb17e004cb6ff
Signed-off-by: Jeyaprakash Soundrapandian <jsound@codeaurora.org>
diff --git a/drivers/media/video/msm/msm_io_8x60.c b/drivers/media/video/msm/msm_io_8x60.c
index 5de800f..2262aa4 100644
--- a/drivers/media/video/msm/msm_io_8x60.c
+++ b/drivers/media/video/msm/msm_io_8x60.c
@@ -573,8 +573,6 @@
int rc = 0;
struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- uint32_t val;
-
camio_dev = pdev;
camio_ext = camdev->ioext;
camio_clk = camdev->ioclk;
@@ -606,22 +604,6 @@
if (rc < 0)
goto csi_irq_fail;
- msleep(10);
- val = (20 <<
- MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
- (0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
- (0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
- CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
-
- val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
- CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
return 0;
csi_irq_fail:
@@ -642,30 +624,17 @@
return rc;
}
-void msm_camio_disable(struct platform_device *pdev)
+static void msm_camio_csi_disable(void)
{
uint32_t val;
- val = (0x0 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
- (0x0 <<
- MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
- (0x0 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
- (0x0 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
- CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
- val = (20 <<
- MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
- (0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
- (0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
+ val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
- val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
@@ -681,8 +650,12 @@
csi_free_irq();
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
+}
+void msm_camio_disable(struct platform_device *pdev)
+{
+ CDBG("disable mipi\n");
+ msm_camio_csi_disable();
CDBG("disable clocks\n");
-
msm_camio_clk_disable(CAMIO_CSI0_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI0_CLK);
msm_camio_clk_disable(CAMIO_CSI1_VFE_CLK);
@@ -755,8 +728,9 @@
{
int rc = 0;
uint32_t val = 0;
+ int i;
- CDBG("msm_camio_csi_config \n");
+ CDBG("msm_camio_csi_config\n");
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
@@ -776,15 +750,6 @@
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
- /* SW CAL EN */
- val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
- (0x1 <<
- MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
- (0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
- (0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
- CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
-
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
val = (csi_params->settle_cnt <<
@@ -793,11 +758,8 @@
(0x1 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
-
+ for (i = 0; i < csi_params->lane_cnt; i++)
+ msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);