tree 9f132fd63c08266901f3427d624891ac7e2da7b7
parent 002ea9eefec98dada56fd5f8e432a4e8570c2a26
author Will Deacon <will.deacon@arm.com> 1317663053 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1318673062 +0100

ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9

Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.

Reported-by: Alasdair Grant <alasdair.grant@arm.com>
Reported-by: Matt Horsnell <matt.horsnell@arm.com>
Reported-by: Michael Williams <michael.williams@arm.com>
Cc: stable@kernel.org
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>