Merge "Merge remote-tracking branch 'common/android-3.0' into msm-3.0" into msm-3.0
diff --git a/Documentation/devicetree/bindings/mmc/msm_sdcc.txt b/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
new file mode 100644
index 0000000..4fb653e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
@@ -0,0 +1,40 @@
+Qualcomm Secure Digital Card Controller (SDCC)
+
+Secure Digital Card Controller provides host interface to
+SD/MMC/SDIO cards.
+
+Required properties:
+  - compatible : should be "qcom,msm-sdcc"
+  - reg : should contain SDCC, BAM register map.
+  - interrupts : should contain SDCC core interrupt.
+  - qcom,sdcc-clk-rates : specifies supported SDCC clock frequencies, Units - Hz.
+  - qcom,sdcc-sup-voltages: specifies supported voltage ranges for card. Should always be
+			specified in pairs (min, max), Units - mV.
+
+Optional Properties:
+	- cell-index - defines slot ID.
+	- qcom,sdcc-bus-width - defines the bus I/O width that controller supports.
+	- qcom,sdcc-wp-gpio - defines write protect switch gpio.
+	- qcom,sdcc-wp-polarity - specifies the polarity of wp switch.
+	- qcom,sdcc-cd-gpio - defines card detect gpio number.
+	- qcom,sdcc-cd-polarity - specifies the polarity of cd gpio.
+	- qcom,sdcc-nonremovable - specifies whether the card in slot is
+				hot pluggable or hard wired.
+	- qcom,sdcc-disable_cmd23 - disable sending CMD23 to card when controller can't support it.
+
+Example:
+
+	qcom,sdcc@F9600000 {
+	/* SDC1 used as eMMC slot */
+	cell-index = <1>;
+	compatible = "qcom,msm-sdcc";
+	reg = <0xF9600000 0x800   // SDCC register interface
+		0xF9600800 0x1800  // DML register interface
+		0xF9602000 0x2000> // BAM register interface
+
+	interrupts = <123>;
+	qcom,sdcc-clk-rates = <400000 24000000 48000000>;
+	qcom,sdcc-sup-voltages = <2700 3300>;
+	qcom,sdcc-bus-width = <8>; //8-bit wide
+	qcom,sdcc-nonremovable;
+};
diff --git a/arch/arm/boot/dts/msmcopper.dts b/arch/arm/boot/dts/msmcopper.dts
index 74fc5a9..e72f4dc 100644
--- a/arch/arm/boot/dts/msmcopper.dts
+++ b/arch/arm/boot/dts/msmcopper.dts
@@ -30,4 +30,29 @@
 		qcom,hsusb-otg-mode = <1>;
 		qcom,hsusb-otg-otg-control = <1>;
 	};
+
+	qcom,sdcc@F9600000 {
+		cell-index = <1>;
+		compatible = "qcom,msm-sdcc";
+		reg = <0xF9600000 0x1000>;
+		interrupts = <123>;
+
+		qcom,sdcc-clk-rates = <400000 24000000 48000000>;
+		qcom,sdcc-sup-voltages = <3300 3300>;
+		qcom,sdcc-bus-width = <8>;
+		qcom,sdcc-nonremovable;
+		qcom,sdcc-disable_cmd23;
+	};
+
+	qcom,sdcc@F9620000 {
+		cell-index = <3>;
+		compatible = "qcom,msm-sdcc";
+		reg = <0xF9620000 0x1000>;
+		interrupts = <127>;
+
+		qcom,sdcc-clk-rates = <400000 24000000 48000000>;
+		qcom,sdcc-sup-voltages = <3300 3300>;
+		qcom,sdcc-bus-width = <4>;
+		qcom,sdcc-disable_cmd23;
+	};
 };
diff --git a/arch/arm/configs/fsm9xxx-perf_defconfig b/arch/arm/configs/fsm9xxx-perf_defconfig
index 5717577..92d401c 100644
--- a/arch/arm/configs/fsm9xxx-perf_defconfig
+++ b/arch/arm/configs/fsm9xxx-perf_defconfig
@@ -26,7 +26,6 @@
 CONFIG_MSM7X00A_USE_DG_TIMER=y
 CONFIG_MSM7X00A_SLEEP_WAIT_FOR_INTERRUPT=y
 CONFIG_MSM7X00A_IDLE_SLEEP_WAIT_FOR_INTERRUPT=y
-CONFIG_MSM_JTAG_V7=y
 CONFIG_MSM_SMD=y
 CONFIG_MSM_SMD_PKG3=y
 # CONFIG_MSM_SMD_DEBUG is not set
@@ -35,6 +34,7 @@
 # CONFIG_MSM_HW3D is not set
 # CONFIG_QSD_AUDIO is not set
 # CONFIG_SURF_FFA_GPIO_KEYPAD is not set
+CONFIG_MSM_JTAG_V7=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_VMSPLIT_2G=y
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 83d0828..90d4c4a 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -31,7 +31,6 @@
 # CONFIG_MACH_MSM7X27_FFA is not set
 # CONFIG_MSM_STACKED_MEMORY is not set
 CONFIG_MSM7X00A_USE_DG_TIMER=y
-# CONFIG_MSM_JTAG_V7 is not set
 # CONFIG_MSM_FIQ_SUPPORT is not set
 CONFIG_MSM_SMD=y
 CONFIG_MSM_SMD_PKG4=y
@@ -45,6 +44,7 @@
 # CONFIG_MSM_HW3D is not set
 CONFIG_MSM7X27A_AUDIO=y
 CONFIG_MSM_DMA_TEST=y
+# CONFIG_MSM_JTAG_V7 is not set
 CONFIG_BT_MSM_PINTEST=y
 CONFIG_MSM_RPC_VIBRATOR=y
 CONFIG_PM8XXX_RPC_VIBRATOR=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index dcbca79..53d6367 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -30,7 +30,6 @@
 # CONFIG_MACH_MSM7X27_FFA is not set
 # CONFIG_MSM_STACKED_MEMORY is not set
 CONFIG_MSM7X00A_USE_DG_TIMER=y
-# CONFIG_MSM_JTAG_V7 is not set
 # CONFIG_MSM_FIQ_SUPPORT is not set
 CONFIG_MSM_SMD=y
 CONFIG_MSM_SMD_PKG4=y
@@ -44,6 +43,7 @@
 # CONFIG_MSM_HW3D is not set
 CONFIG_MSM7X27A_AUDIO=y
 CONFIG_MSM_DMA_TEST=y
+# CONFIG_MSM_JTAG_V7 is not set
 CONFIG_BT_MSM_PINTEST=y
 CONFIG_MSM_RPC_VIBRATOR=y
 CONFIG_PM8XXX_RPC_VIBRATOR=y
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index 042d751..2cd7b97 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -26,7 +26,6 @@
 CONFIG_ARCH_MSM=y
 CONFIG_ARCH_MSM7X30=y
 # CONFIG_MSM_STACKED_MEMORY is not set
-# CONFIG_MSM_JTAG_V7 is not set
 CONFIG_MSM_SMD=y
 CONFIG_MSM_SMD_PKG3=y
 CONFIG_MSM_SDIO_DMUX=y
@@ -41,6 +40,7 @@
 CONFIG_MSM_MEMORY_LOW_POWER_MODE_IDLE_RETENTION=y
 CONFIG_MSM_MEMORY_LOW_POWER_MODE_SUSPEND_DEEP_POWER_DOWN=y
 CONFIG_MSM_IDLE_WAIT_ON_MODEM=2000
+# CONFIG_MSM_JTAG_V7 is not set
 CONFIG_MSM_STANDALONE_POWER_COLLAPSE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index dcdf9e5..d84f64a 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -43,7 +43,6 @@
 CONFIG_MSM7X00A_USE_DG_TIMER=y
 CONFIG_MSM7X00A_SLEEP_MODE_POWER_COLLAPSE=y
 CONFIG_MSM7X00A_IDLE_SLEEP_WAIT_FOR_INTERRUPT=y
-# CONFIG_MSM_JTAG_V7 is not set
 # CONFIG_MSM_FIQ_SUPPORT is not set
 # CONFIG_MSM_PROC_COMM is not set
 CONFIG_MSM_SMD=y
@@ -67,6 +66,7 @@
 CONFIG_MSM_RPM_STATS_LOG=y
 CONFIG_MSM_WATCHDOG=y
 CONFIG_MSM_DLOAD_MODE=y
+# CONFIG_MSM_JTAG_V7 is not set
 CONFIG_MSM_ETM=y
 CONFIG_MSM_SLEEP_STATS=y
 CONFIG_MSM_GSBI9_UART=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 67d0057..83efc02 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -36,7 +36,6 @@
 CONFIG_MACH_MSM9615_MTP=y
 # CONFIG_MSM_STACKED_MEMORY is not set
 CONFIG_CPU_HAS_L2_PMU=y
-# CONFIG_MSM_JTAG_V7 is not set
 # CONFIG_MSM_FIQ_SUPPORT is not set
 # CONFIG_MSM_PROC_COMM is not set
 CONFIG_MSM_SMD=y
@@ -51,6 +50,7 @@
 CONFIG_MSM_DIRECT_SCLK_ACCESS=y
 CONFIG_MSM_WATCHDOG=y
 CONFIG_MSM_DLOAD_MODE=y
+# CONFIG_MSM_JTAG_V7 is not set
 CONFIG_SWP_EMULATE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -118,6 +118,8 @@
 CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_MSM is not set
 CONFIG_I2C_QUP=y
+CONFIG_MSM_BUS_SCALING=y
+CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
 CONFIG_SPI=y
 CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=m
@@ -134,6 +136,8 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_CI13XXX_MSM=y
 CONFIG_USB_G_ANDROID=y
+CONFIG_RMNET_SMD_CTL_CHANNEL="DATA36_CNTL"
+CONFIG_RMNET_SMD_DATA_CHANNEL="DATA36"
 CONFIG_MMC=y
 CONFIG_MMC_PERF_PROFILING=y
 CONFIG_MMC_UNSAFE_RESUME=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 2d681fa..e5f7449 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -712,9 +712,21 @@
 		bool "6.2.20 + New ADSP"
 endchoice
 
+config MSM_HAS_DEBUG_UART_HS
+	bool
+	help
+	  Say Y here if high speed MSM UART is present.
+
+config MSM_HAS_DEBUG_UART_HS_V14
+	bool
+	select MSM_HAS_DEBUG_UART_HS
+	help
+	  Say Y here if high speed MSM UART v1.4 is present.
+
 config DEBUG_MSM8930_UART
 	bool "Kernel low-level debugging messages via MSM 8930 UART"
 	depends on ARCH_MSM8930 && DEBUG_LL
+	select MSM_HAS_DEBUG_UART_HS
 	help
 	  Say Y here if you want the debug print routines to direct
 	  their output to the serial port on MSM 8930 devices.
@@ -747,6 +759,7 @@
 	config DEBUG_MSM8660_UART
 		bool "Kernel low-level debugging messages via MSM 8660 UART"
 		depends on ARCH_MSM8X60
+		select MSM_HAS_DEBUG_UART_HS
 		help
 		  Say Y here if you want the debug print routines to direct
 		  their output to the serial port on MSM 8660 devices.
@@ -755,9 +768,18 @@
 		bool "Kernel low-level debugging messages via MSM 8960 UART"
 		depends on ARCH_MSM8960
 		select DEBUG_MSM8930_UART
+		select MSM_HAS_DEBUG_UART_HS
 		help
 		  Say Y here if you want the debug print routines to direct
 		  their output to the serial port on MSM 8960 devices.
+
+	config DEBUG_MSMCOPPER_UART
+		bool "Kernel low-level debugging messages via MSM Copper UART"
+		depends on ARCH_MSMCOPPER
+		select MSM_HAS_DEBUG_UART_HS_V14
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the serial port on MSM Copper devices.
 endchoice
 
 choice
diff --git a/arch/arm/mach-msm/acpuclock-9615.c b/arch/arm/mach-msm/acpuclock-9615.c
index ebc7f1b..e6206dd 100644
--- a/arch/arm/mach-msm/acpuclock-9615.c
+++ b/arch/arm/mach-msm/acpuclock-9615.c
@@ -27,6 +27,8 @@
 
 #include <mach/board.h>
 #include <mach/msm_iomap.h>
+#include <mach/msm_bus.h>
+#include <mach/msm_bus_board.h>
 #include <mach/rpm-regulator.h>
 
 #include "acpuclock.h"
@@ -68,6 +70,7 @@
 	unsigned int	src_div;
 	unsigned int	vdd_cpu;
 	unsigned int	vdd_mem;
+	unsigned int	bw_level;
 };
 
 struct acpuclk_state {
@@ -79,12 +82,40 @@
 	.current_speed = &(struct clkctl_acpu_speed){ 0 },
 };
 
+/* Instantaneous bandwidth requests in MB/s. */
+#define BW_MBPS(_bw) \
+	{ \
+		.vectors = &(struct msm_bus_vectors){ \
+			.src = MSM_BUS_MASTER_AMPSS_M0, \
+			.dst = MSM_BUS_SLAVE_EBI_CH0, \
+			.ib = (_bw) * 1000000UL, \
+			.ab = 0, \
+		}, \
+		.num_paths = 1, \
+	}
+static struct msm_bus_paths bw_level_tbl[] = {
+	[0] =  BW_MBPS(152), /* At least  19 MHz on bus. */
+	[1] =  BW_MBPS(368), /* At least  46 MHz on bus. */
+	[2] =  BW_MBPS(552), /* At least  69 MHz on bus. */
+	[3] =  BW_MBPS(736), /* At least  92 MHz on bus. */
+	[4] = BW_MBPS(1064), /* At least 133 MHz on bus. */
+};
+
+static struct msm_bus_scale_pdata bus_client_pdata = {
+	.usecase = bw_level_tbl,
+	.num_usecases = ARRAY_SIZE(bw_level_tbl),
+	.active_only = 1,
+	.name = "acpuclock",
+};
+
+static uint32_t bus_perf_client;
+
 static struct clkctl_acpu_speed acpu_freq_tbl[] = {
-	{ 0,  19200, SRC_CXO,  0, 0,  950000, 1050000 },
-	{ 1, 138000, SRC_PLL0, 6, 1,  950000, 1050000 },
-	{ 1, 276000, SRC_PLL0, 6, 0, 1050000, 1050000 },
-	{ 1, 384000, SRC_PLL8, 3, 0, 1150000, 1150000 },
-	{ 1, 440000, SRC_PLL9, 2, 0, 1150000, 1150000 },
+	{ 0,  19200, SRC_CXO,  0, 0,  950000, 1050000, 0 },
+	{ 1, 138000, SRC_PLL0, 6, 1,  950000, 1050000, 2 },
+	{ 1, 276000, SRC_PLL0, 6, 0, 1050000, 1050000, 2 },
+	{ 1, 384000, SRC_PLL8, 3, 0, 1150000, 1150000, 4 },
+	{ 1, 440000, SRC_PLL9, 2, 0, 1150000, 1150000, 4 },
 	{ 0 }
 };
 
@@ -104,6 +135,25 @@
 	udelay(1);
 }
 
+/* Update the bus bandwidth request. */
+static void set_bus_bw(unsigned int bw)
+{
+	int ret;
+
+	/* Bounds check. */
+	if (bw >= ARRAY_SIZE(bw_level_tbl)) {
+		pr_err("invalid bandwidth request (%d)\n", bw);
+		return;
+	}
+
+	/* Update bandwidth if request has changed. This may sleep. */
+	ret = msm_bus_scale_client_update_request(bus_perf_client, bw);
+	if (ret)
+		pr_err("bandwidth request failed (%d)\n", ret);
+
+	return;
+}
+
 /* Apply any per-cpu voltage increases. */
 static int increase_vdd(unsigned int vdd_cpu, unsigned int vdd_mem)
 {
@@ -198,6 +248,9 @@
 	if (reason == SETRATE_SWFI || reason == SETRATE_PC)
 		goto out;
 
+	/* Update bus bandwith request. */
+	set_bus_bw(tgt_s->bw_level);
+
 	/* Drop VDD levels if we can. */
 	if (tgt_s->khz < strt_s->khz)
 		decrease_vdd(tgt_s->vdd_cpu, tgt_s->vdd_mem);
@@ -258,6 +311,13 @@
 	int i;
 
 	mutex_init(&drv_state.lock);
+
+	bus_perf_client = msm_bus_scale_register_client(&bus_client_pdata);
+	if (!bus_perf_client) {
+		pr_err("Unable to register bus client\n");
+		BUG();
+	}
+
 	for (i = 0; i < NUM_SRC; i++) {
 		if (clocks[i].name) {
 			clocks[i].clk = clk_get_sys(NULL, clocks[i].name);
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index d863b5d..eddd4ed 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -27,6 +27,7 @@
 #include <linux/mfd/pm8xxx/pm8xxx-adc.h>
 #include <linux/leds.h>
 #include <linux/leds-pm8xxx.h>
+#include <mach/msm_bus_board.h>
 #include "timer.h"
 #include "devices.h"
 #include "board-9615.h"
@@ -602,6 +603,17 @@
 	return 0;
 }
 
+static void __init msm9615_init_buses(void)
+{
+#ifdef CONFIG_MSM_BUS_SCALING
+	msm_bus_rpm_set_mt_mask();
+	msm_bus_9615_sys_fabric_pdata.rpm_enabled = 1;
+	msm_bus_9615_sys_fabric.dev.platform_data =
+		&msm_bus_9615_sys_fabric_pdata;
+	msm_bus_def_fab.dev.platform_data = &msm_bus_9615_def_fab_pdata;
+#endif
+}
+
 static struct msm_spi_platform_data msm9615_qup_spi_gsbi3_pdata = {
 	.max_clock_speed = 24000000,
 };
@@ -675,6 +687,8 @@
 	&msm9615_qcedev_device,
 #endif
 	&msm9615_device_watchdog,
+	&msm_bus_9615_sys_fabric,
+	&msm_bus_def_fab,
 };
 
 static void __init msm9615_i2c_init(void)
@@ -690,6 +704,8 @@
 	msm9615_i2c_init();
 	regulator_suppress_info_printing();
 	platform_device_register(&msm9615_device_rpm_regulator);
+	msm_clock_init(&msm9615_clock_init_data);
+	msm9615_init_buses();
 	msm9615_device_qup_spi_gsbi3.dev.platform_data =
 				&msm9615_qup_spi_gsbi3_pdata;
 	msm9615_device_ssbi_pmic1.dev.platform_data =
@@ -699,7 +715,6 @@
 	msm_device_otg.dev.platform_data = &msm_otg_pdata;
 	platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
 
-	msm_clock_init(&msm9615_clock_init_data);
 	acpuclk_init(&acpuclk_9615_soc_data);
 
 	/* Ensure ar6000pm device is registered before MMC/SDC */
diff --git a/arch/arm/mach-msm/board-msm8960-regulator.c b/arch/arm/mach-msm/board-msm8960-regulator.c
index c67e100..6aee8e7 100644
--- a/arch/arm/mach-msm/board-msm8960-regulator.c
+++ b/arch/arm/mach-msm/board-msm8960-regulator.c
@@ -32,7 +32,6 @@
 	REGULATOR_SUPPLY("dsi_vdda",		"mipi_dsi.1"),
 	REGULATOR_SUPPLY("mipi_csi_vdd",	"msm_camera_imx074.0"),
 	REGULATOR_SUPPLY("mipi_csi_vdd",	"msm_camera_ov2720.0"),
-	REGULATOR_SUPPLY("mipi_csi_vdd",	"msm_camera_qs_mt9p017.0"),
 };
 VREG_CONSUMERS(L3) = {
 	REGULATOR_SUPPLY("8921_l3",		NULL),
@@ -72,13 +71,11 @@
 	REGULATOR_SUPPLY("8921_l11",		NULL),
 	REGULATOR_SUPPLY("cam_vana",		"msm_camera_imx074.0"),
 	REGULATOR_SUPPLY("cam_vana",		"msm_camera_ov2720.0"),
-	REGULATOR_SUPPLY("cam_vana",		"msm_camera_qs_mt9p017.0"),
 };
 VREG_CONSUMERS(L12) = {
 	REGULATOR_SUPPLY("8921_l12",		NULL),
 	REGULATOR_SUPPLY("cam_vdig",		"msm_camera_imx074.0"),
 	REGULATOR_SUPPLY("cam_vdig",		"msm_camera_ov2720.0"),
-	REGULATOR_SUPPLY("cam_vdig",		"msm_camera_qs_mt9p017.0"),
 };
 VREG_CONSUMERS(L14) = {
 	REGULATOR_SUPPLY("8921_l14",		NULL),
@@ -91,7 +88,6 @@
 	REGULATOR_SUPPLY("8921_l16",		NULL),
 	REGULATOR_SUPPLY("cam_vaf",		"msm_camera_imx074.0"),
 	REGULATOR_SUPPLY("cam_vaf",		"msm_camera_ov2720.0"),
-	REGULATOR_SUPPLY("cam_vaf",		"msm_camera_qs_mt9p017.0"),
 };
 VREG_CONSUMERS(L17) = {
 	REGULATOR_SUPPLY("8921_l17",		NULL),
@@ -201,7 +197,6 @@
 	REGULATOR_SUPPLY("8921_lvs5",		NULL),
 	REGULATOR_SUPPLY("cam_vio",		"msm_camera_imx074.0"),
 	REGULATOR_SUPPLY("cam_vio",		"msm_camera_ov2720.0"),
-	REGULATOR_SUPPLY("cam_vio",		"msm_camera_qs_mt9p017.0"),
 };
 VREG_CONSUMERS(LVS6) = {
 	REGULATOR_SUPPLY("8921_lvs6",		NULL),
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index ece65f3..9813715 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -848,7 +848,7 @@
 #ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
 #define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
 #else
-#define MSM_PMEM_SIZE 0x1800000 /* 24 Mbytes */
+#define MSM_PMEM_SIZE 0x1C00000 /* 28 Mbytes */
 #endif
 
 
@@ -1080,12 +1080,22 @@
 	bank_size = msm8960_memory_bank_size();
 	low = meminfo.bank[0].start;
 	high = mb->start + mb->size;
+
+	/* Check if 32 bit overflow occured */
+	if (high < mb->start)
+		high = ~0UL;
+
 	low &= ~(bank_size - 1);
 
 	if (high - low <= bank_size)
 		return;
 	msm8960_reserve_info.low_unstable_address = low + bank_size;
-	msm8960_reserve_info.max_unstable_size = high - low - bank_size;
+	/* To avoid overflow of u32 compute max_unstable_size
+	 * by first subtracting low from mb->start)
+	 * */
+	msm8960_reserve_info.max_unstable_size = (mb->start - low) +
+						mb->size - bank_size;
+
 	msm8960_reserve_info.bank_size = bank_size;
 	pr_info("low unstable address %lx max size %lx bank size %lx\n",
 		msm8960_reserve_info.low_unstable_address,
@@ -1387,35 +1397,6 @@
 };
 #endif
 
-static struct msm_camera_sensor_flash_data flash_qs_mt9p017 = {
-	.flash_type	= MSM_CAMERA_FLASH_LED,
-};
-
-static struct msm_camera_sensor_platform_info sensor_board_info_qs_mt9p017 = {
-	.mount_angle	= 270,
-	.sensor_reset	= 107,
-	.sensor_pwd	= 85,
-	.vcm_pwd	= 0,
-	.vcm_enable	= 1,
-};
-
-static struct msm_camera_sensor_info msm_camera_sensor_qs_mt9p017_data = {
-	.sensor_name	= "qs_mt9p017",
-	.pdata	= &msm_camera_csi_device_data[0],
-	.flash_data	= &flash_qs_mt9p017,
-	.sensor_platform_info = &sensor_board_info_qs_mt9p017,
-	.gpio_conf = &gpio_conf,
-	.csi_if	= 1,
-	.camera_type = BACK_CAMERA_3D,
-};
-
-struct platform_device msm8960_camera_sensor_qs_mt9p017 = {
-	.name	= "msm_camera_qs_mt9p017",
-	.dev	= {
-		.platform_data = &msm_camera_sensor_qs_mt9p017_data,
-	},
-};
-
 static struct msm8960_privacy_light_cfg privacy_light_info = {
 	.mpp = PM8921_MPP_PM_TO_SYS(12),
 };
@@ -1426,7 +1407,6 @@
 	struct platform_device *cam_dev[] = {
 		&msm8960_camera_sensor_imx074,
 		&msm8960_camera_sensor_ov2720,
-		&msm8960_camera_sensor_qs_mt9p017,
 	};
 
 	if (machine_is_msm8960_liquid()) {
@@ -3603,7 +3583,7 @@
 	/* T6 Object */
 	0, 0, 0, 0, 0, 0,
 	/* T38 Object */
-	11, 1, 0, 20, 10, 11, 0, 0, 0, 0,
+	11, 2, 0, 11, 11, 11, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3613,18 +3593,18 @@
 	/* T7 Object */
 	100, 16, 50,
 	/* T8 Object */
-	8, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	8, 0, 0, 0, 0, 0, 8, 14, 50, 215,
 	/* T9 Object */
-	131, 0, 0, 26, 42, 0, 32, 60, 2, 5,
-	0, 5, 5, 34, 10, 10, 10, 10, 255, 2,
-	85, 5, 18, 18, 18, 18, 0, 0, 5, 20,
-	0, 5, 45, 46,
+	131, 0, 0, 26, 42, 0, 32, 63, 3, 5,
+	0, 2, 1, 113, 10, 10, 8, 10, 255, 2,
+	85, 5, 0, 0, 20, 20, 75, 25, 202, 29,
+	10, 10, 45, 46,
 	/* T15 Object */
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0,
 	/* T22 Object */
-	0, 0, 0, 0, 0, 0, 0, 0, 30, 0,
-	0, 0, 255, 255, 255, 255, 0,
+	5, 0, 0, 0, 0, 0, 0, 0, 30, 0,
+	0, 0, 5, 8, 10, 13, 0,
 	/* T24 Object */
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3634,7 +3614,7 @@
 	/* T27 Object */
 	0, 0, 0, 0, 0, 0, 0,
 	/* T28 Object */
-	0, 0, 0, 8, 8, 60,
+	0, 0, 0, 8, 12, 60,
 	/* T40 Object */
 	0, 0, 0, 0, 0,
 	/* T41 Object */
@@ -4573,9 +4553,6 @@
 	I2C_BOARD_INFO("ov2720", 0x6C),
 	},
 #endif
-	{
-	I2C_BOARD_INFO("qs_mt9p017", 0x6C >> 1),
-	},
 #ifdef CONFIG_MSM_CAMERA_FLASH_SC628A
 	{
 	I2C_BOARD_INFO("sc628a", 0x6E),
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 66c6436..aaf6c83 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -57,6 +57,8 @@
 #define CLK_HALT_SFPB_MISC_STATE_REG		REG(0x2FD8)
 #define CLK_HALT_AFAB_SFAB_STATEB_REG		REG(0x2FC4)
 #define CLK_TEST_REG				REG(0x2FA0)
+#define GPn_MD_REG(n)				REG(0x2D00+(0x20*(n)))
+#define GPn_NS_REG(n)				REG(0x2D24+(0x20*(n)))
 #define GSBIn_HCLK_CTL_REG(n)			REG(0x29C0+(0x20*((n)-1)))
 #define GSBIn_QUP_APPS_MD_REG(n)		REG(0x29C8+(0x20*((n)-1)))
 #define GSBIn_QUP_APPS_NS_REG(n)		REG(0x29CC+(0x20*((n)-1)))
@@ -319,7 +321,7 @@
 
 /* MUX source input identifiers. */
 #define pxo_to_bb_mux		0
-#define cxo_to_bb_mux		pxo_to_bb_mux
+#define cxo_to_bb_mux		5
 #define pll0_to_bb_mux		2
 #define pll8_to_bb_mux		3
 #define pll6_to_bb_mux		4
@@ -1222,6 +1224,55 @@
 /*
  * Peripheral Clocks
  */
+#define CLK_GP(i, n, h_r, h_b) \
+	struct rcg_clk i##_clk = { \
+		.b = { \
+			.ctl_reg = GPn_NS_REG(n), \
+			.en_mask = BIT(9), \
+			.halt_reg = h_r, \
+			.halt_bit = h_b, \
+		}, \
+		.ns_reg = GPn_NS_REG(n), \
+		.md_reg = GPn_MD_REG(n), \
+		.root_en_mask = BIT(11), \
+		.ns_mask = (BM(23, 16) | BM(6, 0)), \
+		.set_rate = set_rate_mnd, \
+		.freq_tbl = clk_tbl_gp, \
+		.current_freq = &rcg_dummy_freq, \
+		.c = { \
+			.dbg_name = #i "_clk", \
+			.ops = &clk_ops_rcg_8960, \
+			VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
+			CLK_INIT(i##_clk.c), \
+		}, \
+	}
+#define F_GP(f, s, d, m, n) \
+	{ \
+		.freq_hz = f, \
+		.src_clk = &s##_clk.c, \
+		.md_val = MD8(16, m, 0, n), \
+		.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
+		.mnd_en_mask = BIT(8) * !!(n), \
+	}
+static struct clk_freq_tbl clk_tbl_gp[] = {
+	F_GP(        0, gnd,  1, 0, 0),
+	F_GP(  9600000, cxo,  2, 0, 0),
+	F_GP( 13500000, pxo,  2, 0, 0),
+	F_GP( 19200000, cxo,  1, 0, 0),
+	F_GP( 27000000, pxo,  1, 0, 0),
+	F_GP( 64000000, pll8, 2, 1, 3),
+	F_GP( 76800000, pll8, 1, 1, 5),
+	F_GP( 96000000, pll8, 4, 0, 0),
+	F_GP(128000000, pll8, 3, 0, 0),
+	F_GP(192000000, pll8, 2, 0, 0),
+	F_GP(384000000, pll8, 1, 0, 0),
+	F_END
+};
+
+static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
+static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
+static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
+
 #define CLK_GSBI_UART(i, n, h_r, h_b) \
 	struct rcg_clk i##_clk = { \
 		.b = { \
@@ -4681,6 +4732,9 @@
 	{ TEST_PER_LS(0x19), &sdc4_clk.c },
 	{ TEST_PER_LS(0x1A), &sdc5_p_clk.c },
 	{ TEST_PER_LS(0x1B), &sdc5_clk.c },
+	{ TEST_PER_LS(0x1F), &gp0_clk.c },
+	{ TEST_PER_LS(0x20), &gp1_clk.c },
+	{ TEST_PER_LS(0x21), &gp2_clk.c },
 	{ TEST_PER_LS(0x25), &dfab_clk.c },
 	{ TEST_PER_LS(0x25), &dfab_a_clk.c },
 	{ TEST_PER_LS(0x26), &pmem_clk.c },
@@ -5070,6 +5124,9 @@
 	CLK_DUMMY("sfpb_clk",		SFPB_CLK,	NULL, 0),
 	CLK_DUMMY("sfpb_a_clk",		SFPB_A_CLK,	NULL, 0),
 
+	CLK_LOOKUP("core_clk",		gp0_clk.c,		NULL),
+	CLK_LOOKUP("core_clk",		gp1_clk.c,		NULL),
+	CLK_LOOKUP("core_clk",		gp2_clk.c,		NULL),
 	CLK_LOOKUP("core_clk",		gsbi1_uart_clk.c,	NULL),
 	CLK_LOOKUP("core_clk",		gsbi2_uart_clk.c,	NULL),
 	CLK_LOOKUP("core_clk",		gsbi3_uart_clk.c,	NULL),
@@ -5298,6 +5355,9 @@
 	CLK_LOOKUP("sfpb_clk",		sfpb_clk.c,	NULL),
 	CLK_LOOKUP("sfpb_a_clk",	sfpb_a_clk.c,	NULL),
 
+	CLK_LOOKUP("core_clk",		gp0_clk.c,		NULL),
+	CLK_LOOKUP("core_clk",		gp1_clk.c,		NULL),
+	CLK_LOOKUP("core_clk",		gp2_clk.c,		NULL),
 	CLK_LOOKUP("core_clk",		gsbi1_uart_clk.c,	NULL),
 	CLK_LOOKUP("core_clk",		gsbi2_uart_clk.c,	NULL),
 	CLK_LOOKUP("core_clk",		gsbi3_uart_clk.c,	NULL),
@@ -5378,7 +5438,6 @@
 	CLK_LOOKUP("cam_clk",		cam1_clk.c,		NULL),
 	CLK_LOOKUP("cam_clk",		cam0_clk.c,	"msm_camera_imx074.0"),
 	CLK_LOOKUP("cam_clk",		cam0_clk.c,	"msm_camera_ov2720.0"),
-	CLK_LOOKUP("cam_clk",	cam0_clk.c,	"msm_camera_qs_mt9p017.0"),
 	CLK_LOOKUP("csi_src_clk",	csi0_src_clk.c,		"msm_csid.0"),
 	CLK_LOOKUP("csi_src_clk",	csi1_src_clk.c,		"msm_csid.1"),
 	CLK_LOOKUP("csi_clk",		csi0_clk.c,		"msm_csid.0"),
@@ -5965,7 +6024,7 @@
 	if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
 			PTR_ERR(mmfpb_a_clk)))
 		return PTR_ERR(mmfpb_a_clk);
-	rc = clk_set_min_rate(mmfpb_a_clk, 76800000);
+	rc = clk_set_rate(mmfpb_a_clk, 76800000);
 	if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
 		return rc;
 	rc = clk_enable(mmfpb_a_clk);
@@ -5976,7 +6035,7 @@
 	if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
 			PTR_ERR(cfpb_a_clk)))
 		return PTR_ERR(cfpb_a_clk);
-	rc = clk_set_min_rate(cfpb_a_clk, 64000000);
+	rc = clk_set_rate(cfpb_a_clk, 64000000);
 	if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
 		return rc;
 	rc = clk_enable(cfpb_a_clk);
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 6707757..17052ae 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -55,6 +55,8 @@
 #define CLK_TEST_REG				REG(0x2FA0)
 #define EBI2_2X_CLK_CTL_REG			REG(0x2660)
 #define EBI2_CLK_CTL_REG			REG(0x2664)
+#define GPn_MD_REG(n)				REG(0x2D00+(0x20*(n)))
+#define GPn_NS_REG(n)				REG(0x2D24+(0x20*(n)))
 #define GSBIn_HCLK_CTL_REG(n)			REG(0x29C0+(0x20*((n)-1)))
 #define GSBIn_QUP_APPS_MD_REG(n)		REG(0x29C8+(0x20*((n)-1)))
 #define GSBIn_QUP_APPS_NS_REG(n)		REG(0x29CC+(0x20*((n)-1)))
@@ -207,7 +209,7 @@
 /* MUX source input identifiers. */
 #define pxo_to_bb_mux		0
 #define mxo_to_bb_mux		1
-#define cxo_to_bb_mux		pxo_to_bb_mux
+#define cxo_to_bb_mux		5
 #define pll0_to_bb_mux		2
 #define pll8_to_bb_mux		3
 #define pll6_to_bb_mux		4
@@ -1050,6 +1052,49 @@
 /*
  * Peripheral Clocks
  */
+#define CLK_GP(i, n, h_r, h_b) \
+	struct rcg_clk i##_clk = { \
+		.b = { \
+			.ctl_reg = GPn_NS_REG(n), \
+			.en_mask = BIT(9), \
+			.halt_reg = h_r, \
+			.halt_bit = h_b, \
+		}, \
+		.ns_reg = GPn_NS_REG(n), \
+		.md_reg = GPn_MD_REG(n), \
+		.root_en_mask = BIT(11), \
+		.ns_mask = (BM(23, 16) | BM(6, 0)), \
+		.set_rate = set_rate_mnd, \
+		.freq_tbl = clk_tbl_gp, \
+		.current_freq = &rcg_dummy_freq, \
+		.c = { \
+			.dbg_name = #i "_clk", \
+			.ops = &clk_ops_rcg_8x60, \
+			VDD_DIG_FMAX_MAP1(LOW, 27000000), \
+			CLK_INIT(i##_clk.c), \
+		}, \
+	}
+#define F_GP(f, s, d, m, n) \
+	{ \
+		.freq_hz = f, \
+		.src_clk = &s##_clk.c, \
+		.md_val = MD8(16, m, 0, n), \
+		.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
+		.mnd_en_mask = BIT(8) * !!(n), \
+	}
+static struct clk_freq_tbl clk_tbl_gp[] = {
+	F_GP(        0, gnd,  1, 0, 0),
+	F_GP(  9600000, cxo,  2, 0, 0),
+	F_GP( 13500000, pxo,  2, 0, 0),
+	F_GP( 19200000, cxo,  1, 0, 0),
+	F_GP( 27000000, pxo,  1, 0, 0),
+	F_END
+};
+
+static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
+static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
+static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
+
 #define CLK_GSBI_UART(i, n, h_r, h_b) \
 	struct rcg_clk i##_clk = { \
 		.b = { \
@@ -3215,6 +3260,9 @@
 	{ TEST_PER_LS(0x1B), &sdc5_clk.c },
 	{ TEST_PER_LS(0x1D), &ebi2_2x_clk.c },
 	{ TEST_PER_LS(0x1E), &ebi2_clk.c },
+	{ TEST_PER_LS(0x1F), &gp0_clk.c },
+	{ TEST_PER_LS(0x20), &gp1_clk.c },
+	{ TEST_PER_LS(0x21), &gp2_clk.c },
 	{ TEST_PER_LS(0x25), &dfab_clk.c },
 	{ TEST_PER_LS(0x25), &dfab_a_clk.c },
 	{ TEST_PER_LS(0x26), &pmem_clk.c },
@@ -3567,6 +3615,9 @@
 	CLK_LOOKUP("smi_clk",		smi_clk.c,	NULL),
 	CLK_LOOKUP("smi_a_clk",		smi_a_clk.c,	NULL),
 
+	CLK_LOOKUP("core_clk",		gp0_clk.c,		NULL),
+	CLK_LOOKUP("core_clk",		gp1_clk.c,		NULL),
+	CLK_LOOKUP("core_clk",		gp2_clk.c,		NULL),
 	CLK_LOOKUP("core_clk",		gsbi1_uart_clk.c,	NULL),
 	CLK_LOOKUP("core_clk",		gsbi2_uart_clk.c,	NULL),
 	CLK_LOOKUP("core_clk",		gsbi3_uart_clk.c, "msm_serial_hsl.2"),
@@ -3910,7 +3961,7 @@
 	if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
 			PTR_ERR(mmfpb_a_clk)))
 		return PTR_ERR(mmfpb_a_clk);
-	rc = clk_set_min_rate(mmfpb_a_clk, 64000000);
+	rc = clk_set_rate(mmfpb_a_clk, 64000000);
 	if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
 		return rc;
 	rc = clk_enable(mmfpb_a_clk);
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index cd028e4..7e163df 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -50,6 +50,8 @@
 #define CLK_HALT_MSS_KPSS_MISC_STATE_REG	REG(0x2FDC)
 #define CLK_HALT_SFPB_MISC_STATE_REG		REG(0x2FD8)
 #define CLK_TEST_REG				REG(0x2FA0)
+#define GPn_MD_REG(n)				REG(0x2D00+(0x20*(n)))
+#define GPn_NS_REG(n)				REG(0x2D24+(0x20*(n)))
 #define GSBIn_HCLK_CTL_REG(n)			REG(0x29C0+(0x20*((n)-1)))
 #define GSBIn_QUP_APPS_MD_REG(n)		REG(0x29C8+(0x20*((n)-1)))
 #define GSBIn_QUP_APPS_NS_REG(n)		REG(0x29CC+(0x20*((n)-1)))
@@ -346,6 +348,47 @@
 /*
  * Peripheral Clocks
  */
+#define CLK_GP(i, n, h_r, h_b) \
+	struct rcg_clk i##_clk = { \
+		.b = { \
+			.ctl_reg = GPn_NS_REG(n), \
+			.en_mask = BIT(9), \
+			.halt_reg = h_r, \
+			.halt_bit = h_b, \
+		}, \
+		.ns_reg = GPn_NS_REG(n), \
+		.md_reg = GPn_MD_REG(n), \
+		.root_en_mask = BIT(11), \
+		.ns_mask = (BM(23, 16) | BM(6, 0)), \
+		.set_rate = set_rate_mnd, \
+		.freq_tbl = clk_tbl_gp, \
+		.current_freq = &rcg_dummy_freq, \
+		.c = { \
+			.dbg_name = #i "_clk", \
+			.ops = &clk_ops_rcg_9615, \
+			VDD_DIG_FMAX_MAP1(LOW, 27000000), \
+			CLK_INIT(i##_clk.c), \
+		}, \
+	}
+#define F_GP(f, s, d, m, n) \
+	{ \
+		.freq_hz = f, \
+		.src_clk = &s##_clk.c, \
+		.md_val = MD8(16, m, 0, n), \
+		.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
+		.mnd_en_mask = BIT(8) * !!(n), \
+	}
+static struct clk_freq_tbl clk_tbl_gp[] = {
+	F_GP(        0, gnd,  1, 0, 0),
+	F_GP(  9600000, cxo,  2, 0, 0),
+	F_GP( 19200000, cxo,  1, 0, 0),
+	F_END
+};
+
+static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
+static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
+static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
+
 #define CLK_GSBI_UART(i, n, h_r, h_b) \
 	struct rcg_clk i##_clk = { \
 		.b = { \
@@ -1298,6 +1341,9 @@
 	{ TEST_PER_LS(0x13), &sdc1_clk.c },
 	{ TEST_PER_LS(0x14), &sdc2_p_clk.c },
 	{ TEST_PER_LS(0x15), &sdc2_clk.c },
+	{ TEST_PER_LS(0x1F), &gp0_clk.c },
+	{ TEST_PER_LS(0x20), &gp1_clk.c },
+	{ TEST_PER_LS(0x21), &gp2_clk.c },
 	{ TEST_PER_LS(0x26), &pmem_clk.c },
 	{ TEST_PER_LS(0x25), &dfab_clk.c },
 	{ TEST_PER_LS(0x25), &dfab_a_clk.c },
@@ -1524,6 +1570,10 @@
 	CLK_LOOKUP("sfpb_clk",		sfpb_clk.c,	NULL),
 	CLK_LOOKUP("sfpb_a_clk",	sfpb_a_clk.c,	NULL),
 
+	CLK_LOOKUP("core_clk",		gp0_clk.c,	NULL),
+	CLK_LOOKUP("core_clk",		gp1_clk.c,	NULL),
+	CLK_LOOKUP("core_clk",		gp2_clk.c,	NULL),
+
 	CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
 	CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
 	CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 2ea1f47..af48067 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -415,13 +415,13 @@
 		.src = MSM_BUS_MASTER_HD_CODEC_PORT0,
 		.dst = MSM_BUS_SLAVE_EBI_CH0,
 		.ab  = 372244480,
-		.ib  = 1861222400,
+		.ib  = 2560000000U,
 	},
 	{
 		.src = MSM_BUS_MASTER_HD_CODEC_PORT1,
 		.dst = MSM_BUS_SLAVE_EBI_CH0,
 		.ab  = 501219328,
-		.ib  = 2004877312,
+		.ib  = 2560000000U,
 	},
 	{
 		.src = MSM_BUS_MASTER_AMPSS_M0,
@@ -441,13 +441,13 @@
 		.src = MSM_BUS_MASTER_HD_CODEC_PORT0,
 		.dst = MSM_BUS_SLAVE_EBI_CH0,
 		.ab  = 222298112,
-		.ib  = 1778384896,
+		.ib  = 2560000000U,
 	},
 	{
 		.src = MSM_BUS_MASTER_HD_CODEC_PORT1,
 		.dst = MSM_BUS_SLAVE_EBI_CH0,
 		.ab  = 330301440,
-		.ib  = 1321205760,
+		.ib  = 2560000000U,
 	},
 	{
 		.src = MSM_BUS_MASTER_AMPSS_M0,
@@ -985,10 +985,6 @@
 #ifdef CONFIG_MSM_CAMERA
 struct resource msm_camera_resources[] = {
 	{
-		.name	= "vid_buf",
-		.flags	= IORESOURCE_DMA,
-	},
-	{
 		.name   = "s3d_rw",
 		.start  = 0x008003E0,
 		.end    = 0x008003E0 + SZ_16 - 1,
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index e5a3f20..47e33d0 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -26,6 +26,7 @@
 #include <mach/irqs.h>
 #include <mach/socinfo.h>
 #include <mach/rpm.h>
+#include <mach/msm_bus_board.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <mach/msm_sps.h>
 #include <mach/dma.h>
@@ -860,3 +861,13 @@
 			irq_set_handler(i, handle_percpu_irq);
 	}
 }
+
+struct platform_device msm_bus_9615_sys_fabric = {
+	.name  = "msm_bus_fabric",
+	.id    =  MSM_BUS_FAB_SYSTEM,
+};
+
+struct platform_device msm_bus_def_fab = {
+	.name  = "msm_bus_fabric",
+	.id    =  MSM_BUS_FAB_DEFAULT,
+};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index b5cadd3..48686f0 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -79,6 +79,8 @@
 extern struct platform_device msm9615_device_qup_spi_gsbi3;
 extern struct platform_device msm9615_device_ssbi_pmic1;
 extern struct platform_device msm9615_device_tsens;
+extern struct platform_device msm_bus_9615_sys_fabric;
+extern struct platform_device msm_bus_def_fab;
 
 extern struct platform_device msm_device_sdc1;
 extern struct platform_device msm_device_sdc2;
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 5112888..deeb883 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -18,6 +18,7 @@
 
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
+#include <mach/msm_serial_hsl_regs.h>
 
 #ifdef MSM_DEBUG_UART_PHYS
        .macro  addruart, rp, rv
@@ -26,17 +27,17 @@
 	.endm
 
 	.macro	senduart,rd,rx
-#ifdef CONFIG_SERIAL_MSM_HSL
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
 	@ Clear TX_READY by writing to the UARTDM_CR register
 	mov	r12, #0x300
-	str	r12, [\rx, #0x10]
+	str	r12, [\rx, #UARTDM_CR_OFFSET]
 	@ Write 0x1 to NCF register
 	mov 	r12, #0x1
-	str	r12, [\rx, #0x40]
+	str	r12, [\rx, #UARTDM_NCF_TX_OFFSET]
 	@ UARTDM reg. Read to induce delay
-	ldr	r12, [\rx, #0x08]
+	ldr	r12, [\rx, #UARTDM_SR_OFFSET]
 	@ Write the 1 character to UARTDM_TF
-	str	\rd, [\rx, #0x70]
+	str	\rd, [\rx, #UARTDM_TF_OFFSET]
 #else
 	teq     \rx, #0
 	strne   \rd, [\rx, #0x0C]
@@ -44,13 +45,13 @@
 	.endm
 
 	.macro	waituart,rd,rx
-#ifdef CONFIG_SERIAL_MSM_HSL
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
 	@ check for TX_EMT in UARTDM_SR
-	ldr	\rd, [\rx, #0x08]
+	ldr	\rd, [\rx, #UARTDM_SR_OFFSET]
 	tst	\rd, #0x08
 	bne	1002f
 	@ wait for TXREADY in UARTDM_ISR
-1001:	ldreq	\rd, [\rx, #0x14]
+1001:	ldreq	\rd, [\rx, #UARTDM_ISR_OFFSET]
 	tst	\rd, #0x80
 	dsb
 	beq 	1001b
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-copper.h b/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
index 3999982..57758c3 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
@@ -38,4 +38,9 @@
 #define COPPER_TMR0_PHYS	0xF908A000
 #define COPPER_TMR0_SIZE	SZ_4K
 
+#ifdef CONFIG_DEBUG_MSMCOPPER_UART
+#define MSM_DEBUG_UART_BASE	IOMEM(0xFA782000)
+#define MSM_DEBUG_UART_PHYS	0xF9682000
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_serial_hsl_regs.h b/arch/arm/mach-msm/include/mach/msm_serial_hsl_regs.h
new file mode 100644
index 0000000..b465b56
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_serial_hsl_regs.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_SERIAL_HSL_REGS_H
+#define __ASM_ARCH_MSM_SERIAL_HSL_REGS_H
+
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS_V14
+#define UARTDM_MR2_OFFSET	0x4
+#define UARTDM_CSR_OFFSET	0xa0
+#define UARTDM_SR_OFFSET	0xa4
+#define UARTDM_CR_OFFSET	0xa8
+#define UARTDM_ISR_OFFSET	0xb4
+#define UARTDM_NCF_TX_OFFSET	0x40
+#define UARTDM_TF_OFFSET	0x100
+#else
+#define UARTDM_MR2_OFFSET	0x4
+#define UARTDM_CSR_OFFSET	0x8
+#define UARTDM_SR_OFFSET	0x8
+#define UARTDM_CR_OFFSET	0x10
+#define UARTDM_ISR_OFFSET	0x14
+#define UARTDM_NCF_TX_OFFSET	0x40
+#define UARTDM_TF_OFFSET	0x70
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index 74cbda1..7560dc2 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -21,6 +21,7 @@
 #include <asm/processor.h>
 
 #include <mach/msm_iomap.h>
+#include <mach/msm_serial_hsl_regs.h>
 
 #ifndef CONFIG_DEBUG_ICEDCC
 static void putc(int c)
@@ -28,18 +29,18 @@
 #if defined(MSM_DEBUG_UART_PHYS)
 	unsigned long base = MSM_DEBUG_UART_PHYS;
 
-#ifdef CONFIG_SERIAL_MSM_HSL
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
 	/*
 	 * Wait for TX_READY to be set; but skip it if we have a
 	 * TX underrun.
 	 */
-	if (__raw_readl(base + 0x08) & 0x08)
-		while (!(__raw_readl(base + 0x14) & 0x80))
+	if (!(__raw_readl(base + UARTDM_SR_OFFSET) & 0x08))
+		while (!(__raw_readl(base + UARTDM_ISR_OFFSET) & 0x80))
 			cpu_relax();
 
-	__raw_writel(0x300, base + 0x10);
-	__raw_writel(0x1, base + 0x40);
-	__raw_writel(c, base + 0x70);
+	__raw_writel(0x300, base + UARTDM_CR_OFFSET);
+	__raw_writel(0x1, base + UARTDM_NCF_TX_OFFSET);
+	__raw_writel(c, base + UARTDM_TF_OFFSET);
 #else
 	/* Wait for TX_READY to be set */
 	while (!(__raw_readl(base + 0x08) & 0x04))
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 8a79af7..f09c6d9 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -286,6 +286,9 @@
 	MSM_CHIP_DEVICE(TLMM, COPPER),
 	MSM_CHIP_DEVICE(TMR, COPPER),
 	MSM_CHIP_DEVICE(TMR0, COPPER),
+#ifdef CONFIG_DEBUG_MSMCOPPER_UART
+	MSM_DEVICE(DEBUG_UART),
+#endif
 };
 
 void __init msm_map_copper_io(void)
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index d1dd3ed..1982082 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -24,7 +24,6 @@
 
 #include <mach/iommu_hw-8xxx.h>
 #include <mach/iommu.h>
-#include <mach/clk.h>
 
 struct iommu_ctx_iter_data {
 	/* input */
@@ -164,8 +163,10 @@
 	iommu_clk = clk_get(&pdev->dev, "core_clk");
 
 	if (!IS_ERR(iommu_clk))	{
-		if (clk_get_rate(iommu_clk) == 0)
-			clk_set_min_rate(iommu_clk, 1);
+		if (clk_get_rate(iommu_clk) == 0) {
+			ret = clk_round_rate(iommu_clk, 1);
+			clk_set_rate(iommu_clk, ret);
+		}
 
 		ret = clk_enable(iommu_clk);
 		if (ret) {
diff --git a/arch/arm/mach-msm/mpm.c b/arch/arm/mach-msm/mpm.c
index 040e126..70ee39b 100644
--- a/arch/arm/mach-msm/mpm.c
+++ b/arch/arm/mach-msm/mpm.c
@@ -260,6 +260,9 @@
 		uint32_t index = MSM_MPM_IRQ_INDEX(mpm_irq);
 		uint32_t mask = MSM_MPM_IRQ_MASK(mpm_irq);
 
+		if (index >= MSM_MPM_REG_WIDTH)
+			return -EFAULT;
+
 		if (flow_type & IRQ_TYPE_EDGE_BOTH)
 			msm_mpm_detect_ctl[index] |= mask;
 		else
diff --git a/arch/arm/mach-msm/msm_rq_stats.c b/arch/arm/mach-msm/msm_rq_stats.c
index 425000d..9daaaba 100644
--- a/arch/arm/mach-msm/msm_rq_stats.c
+++ b/arch/arm/mach-msm/msm_rq_stats.c
@@ -160,20 +160,20 @@
 
 	for (i = 0; i < attr_count - 1 ; i++) {
 		if (!attribs[i])
-			goto rel;
+			goto rel2;
 	}
 
 	rq_info.attr_group = kzalloc(sizeof(struct attribute_group),
 						GFP_KERNEL);
 	if (!rq_info.attr_group)
-		goto rel;
+		goto rel3;
 	rq_info.attr_group->attrs = attribs;
 
 	/* Create /sys/devices/system/cpu/cpu0/rq-stats/... */
 	rq_info.kobj = kobject_create_and_add("rq-stats",
 			&get_cpu_sysdev(0)->kobj);
 	if (!rq_info.kobj)
-		goto rel;
+		goto rel3;
 
 	err = sysfs_create_group(rq_info.kobj, rq_info.attr_group);
 	if (err)
@@ -184,12 +184,14 @@
 	if (!err)
 		return err;
 
-rel:
-	for (i = 0; i < attr_count - 1 ; i++)
-		kfree(attribs[i]);
-	kfree(attribs);
+rel3:
 	kfree(rq_info.attr_group);
 	kfree(rq_info.kobj);
+rel2:
+	for (i = 0; i < attr_count - 1; i++)
+		kfree(attribs[i]);
+rel:
+	kfree(attribs);
 
 	return -ENOMEM;
 }
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index cb5fcff..8db21f9 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -384,6 +384,9 @@
 	else
 		i = CONFIG_MSM_IDLE_STATS_BUCKET_COUNT - 1;
 
+	if (i >= CONFIG_MSM_IDLE_STATS_BUCKET_COUNT)
+		i = CONFIG_MSM_IDLE_STATS_BUCKET_COUNT - 1;
+
 	stats[id].bucket[i]++;
 
 	if (t < stats[id].min_time[i] || !stats[id].max_time[i])
diff --git a/arch/arm/mach-msm/qdsp5/adsp.c b/arch/arm/mach-msm/qdsp5/adsp.c
index d392cce..33c5a53 100644
--- a/arch/arm/mach-msm/qdsp5/adsp.c
+++ b/arch/arm/mach-msm/qdsp5/adsp.c
@@ -55,7 +55,6 @@
 
 #include <linux/io.h>
 #include <mach/msm_iomap.h>
-#include <mach/clk.h>
 #include <mach/msm_adsp.h>
 #include "adsp.h"
 
@@ -1018,7 +1017,7 @@
 int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate)
 {
 	if (module->clk && clk_rate)
-		return clk_set_min_rate(module->clk, clk_rate);
+		return clk_set_rate(module->clk, clk_rate);
 
 	return -EINVAL;
 }
@@ -1196,8 +1195,7 @@
 		else
 			mod->clk = NULL;
 		if (mod->clk && adsp_info.module[i].clk_rate)
-			clk_set_min_rate(mod->clk,
-						adsp_info.module[i].clk_rate);
+			clk_set_rate(mod->clk, adsp_info.module[i].clk_rate);
 		mod->verify_cmd = adsp_info.module[i].verify_cmd;
 		mod->patch_event = adsp_info.module[i].patch_event;
 		INIT_HLIST_HEAD(&mod->pmem_regions);
diff --git a/arch/arm/mach-msm/qdsp5v2/adsp.c b/arch/arm/mach-msm/qdsp5v2/adsp.c
index 6d4d074..b7b56c8 100644
--- a/arch/arm/mach-msm/qdsp5v2/adsp.c
+++ b/arch/arm/mach-msm/qdsp5v2/adsp.c
@@ -34,7 +34,6 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 #include <mach/msm_iomap.h>
-#include <mach/clk.h>
 #include <mach/msm_adsp.h>
 #include "adsp.h"
 #include <mach/debug_mm.h>
@@ -851,7 +850,7 @@
 int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate)
 {
 	if (module->clk && clk_rate)
-		return clk_set_min_rate(module->clk, clk_rate);
+		return clk_set_rate(module->clk, clk_rate);
 
 	return -EINVAL;
 }
@@ -1015,8 +1014,7 @@
 		else
 			mod->clk = NULL;
 		if (mod->clk && adsp_info.module[i].clk_rate)
-			clk_set_min_rate(mod->clk,
-						adsp_info.module[i].clk_rate);
+			clk_set_rate(mod->clk, adsp_info.module[i].clk_rate);
 		mod->verify_cmd = adsp_info.module[i].verify_cmd;
 		mod->patch_event = adsp_info.module[i].patch_event;
 		INIT_HLIST_HEAD(&mod->pmem_regions);
diff --git a/arch/arm/mach-msm/qdsp6v2/q6voice.c b/arch/arm/mach-msm/qdsp6v2/q6voice.c
index 1ab615a..058e281 100644
--- a/arch/arm/mach-msm/qdsp6v2/q6voice.c
+++ b/arch/arm/mach-msm/qdsp6v2/q6voice.c
@@ -2499,17 +2499,6 @@
 
 	pr_debug("%s: session_id 0x%x\n", __func__, data->dest_port);
 
-	v = voice_get_session(data->dest_port);
-	if (v == NULL) {
-		pr_err("%s: v is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	pr_debug("%s: common data 0x%x, session 0x%x\n",
-		 __func__, (unsigned int)c, (unsigned int)v);
-	pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
-				data->payload_size, data->opcode);
-
 	if (data->opcode == RESET_EVENTS) {
 		pr_debug("%s:Reset event received in Voice service\n",
 					__func__);
@@ -2525,6 +2514,17 @@
 		return 0;
 	}
 
+	v = voice_get_session(data->dest_port);
+	if (v == NULL) {
+		pr_err("%s: v is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	pr_debug("%s: common data 0x%x, session 0x%x\n",
+		 __func__, (unsigned int)c, (unsigned int)v);
+	pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
+				data->payload_size, data->opcode);
+
 	if (data->opcode == APR_BASIC_RSP_RESULT) {
 		if (data->payload_size) {
 			ptr = data->payload;
@@ -2614,17 +2614,6 @@
 
 	pr_debug("%s: session_id 0x%x\n", __func__, data->dest_port);
 
-	v = voice_get_session(data->dest_port);
-	if (v == NULL) {
-		pr_err("%s: v is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	pr_debug("%s: common data 0x%x, session 0x%x\n",
-		 __func__, (unsigned int)c, (unsigned int)v);
-	pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
-					data->payload_size, data->opcode);
-
 	if (data->opcode == RESET_EVENTS) {
 		pr_debug("%s:Reset event received in Voice service\n",
 					__func__);
@@ -2640,6 +2629,17 @@
 		return 0;
 	}
 
+	v = voice_get_session(data->dest_port);
+	if (v == NULL) {
+		pr_err("%s: v is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	pr_debug("%s: common data 0x%x, session 0x%x\n",
+		 __func__, (unsigned int)c, (unsigned int)v);
+	pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
+					data->payload_size, data->opcode);
+
 	if (data->opcode == APR_BASIC_RSP_RESULT) {
 		if (data->payload_size) {
 			ptr = data->payload;
@@ -2812,17 +2812,6 @@
 
 	pr_debug("%s: session_id 0x%x\n", __func__, data->dest_port);
 
-	v = voice_get_session(data->dest_port);
-	if (v == NULL) {
-		pr_err("%s: v is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	pr_debug("%s: common data 0x%x, session 0x%x\n",
-		 __func__, (unsigned int)c, (unsigned int)v);
-	pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
-				data->payload_size, data->opcode);
-
 	if (data->opcode == RESET_EVENTS) {
 		pr_debug("%s:Reset event received in Voice service\n",
 					__func__);
@@ -2838,6 +2827,17 @@
 		return 0;
 	}
 
+	v = voice_get_session(data->dest_port);
+	if (v == NULL) {
+		pr_err("%s: v is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	pr_debug("%s: common data 0x%x, session 0x%x\n",
+		 __func__, (unsigned int)c, (unsigned int)v);
+	pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
+				data->payload_size, data->opcode);
+
 	if (data->opcode == APR_BASIC_RSP_RESULT) {
 		if (data->payload_size) {
 			ptr = data->payload;
diff --git a/arch/arm/mach-msm/rpm.c b/arch/arm/mach-msm/rpm.c
index bee3c3d..ef2956a 100644
--- a/arch/arm/mach-msm/rpm.c
+++ b/arch/arm/mach-msm/rpm.c
@@ -264,7 +264,7 @@
 	DECLARE_COMPLETION_ONSTACK(ack);
 	unsigned long flags;
 	uint32_t ctx_mask = msm_rpm_get_ctx_mask(ctx);
-	uint32_t ctx_mask_ack;
+	uint32_t ctx_mask_ack = 0;
 	uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
 	int i;
 
@@ -320,8 +320,9 @@
 	unsigned int irq = msm_rpm_platform->irq_ack;
 	unsigned long flags;
 	uint32_t ctx_mask = msm_rpm_get_ctx_mask(ctx);
-	uint32_t ctx_mask_ack;
+	uint32_t ctx_mask_ack = 0;
 	uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
+	struct irq_chip *irq_chip = NULL;
 	int i;
 
 	msm_rpm_request_poll_mode.req = req;
@@ -331,7 +332,12 @@
 	msm_rpm_request_poll_mode.done = NULL;
 
 	spin_lock_irqsave(&msm_rpm_irq_lock, flags);
-	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
+	irq_chip = irq_get_chip(irq);
+	if (!irq_chip) {
+		spin_unlock_irqrestore(&msm_rpm_irq_lock, flags);
+		return -ENOSPC;
+	}
+	irq_chip->irq_mask(irq_get_irq_data(irq));
 
 	if (msm_rpm_request) {
 		msm_rpm_busy_wait_for_request_completion(true);
@@ -356,7 +362,7 @@
 	msm_rpm_busy_wait_for_request_completion(false);
 	BUG_ON(msm_rpm_request);
 
-	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
+	irq_chip->irq_unmask(irq_get_irq_data(irq));
 	spin_unlock_irqrestore(&msm_rpm_irq_lock, flags);
 
 	BUG_ON((ctx_mask_ack & ~(msm_rpm_get_ctx_mask(MSM_RPM_CTX_REJECTED)))
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 190f707..2c6957d 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1129,3 +1129,5 @@
 msm7627a_qrd1		MACH_MSM7627A_QRD1	MSM7627A_QRD1		3756
 msm7625a_ffa		MACH_MSM7625A_FFA	MSM7625A_FFA		3771
 msm7625a_surf		MACH_MSM7625A_SURF	MSM7625A_SURF		3772
+msm8627_cdp		MACH_MSM8627_CDP	MSM8627_CDP		3861
+msm8627_mtp		MACH_MSM8627_MTP	MSM8627_MTP		3862
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 0693f46..4138e06 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -114,8 +114,10 @@
 	},
 	.pfp_fw = NULL,
 	.pm4_fw = NULL,
+	.wait_timeout = 10000, /* in milliseconds */
 };
 
+
 /*
  * This is the master list of all GPU cores that are supported by this
  * driver.
@@ -435,8 +437,6 @@
 	adreno_dev = ADRENO_DEVICE(device);
 	device->parentdev = &pdev->dev;
 
-	adreno_dev->wait_timeout = 10000; /* default value in milliseconds */
-
 	init_completion(&device->recovery_gate);
 
 	status = adreno_ringbuffer_init(device);
diff --git a/drivers/input/touchscreen/cy8c_ts.c b/drivers/input/touchscreen/cy8c_ts.c
index ac4138e..f708582 100644
--- a/drivers/input/touchscreen/cy8c_ts.c
+++ b/drivers/input/touchscreen/cy8c_ts.c
@@ -197,8 +197,7 @@
 	input_report_abs(ts->input, ABS_MT_TRACKING_ID, id);
 	input_report_abs(ts->input, ABS_MT_POSITION_X, x);
 	input_report_abs(ts->input, ABS_MT_POSITION_Y, y);
-	input_report_abs(ts->input, ABS_MT_TOUCH_MAJOR, pressure);
-	input_report_abs(ts->input, ABS_MT_WIDTH_MAJOR, ts->dd->finger_size);
+	input_report_abs(ts->input, ABS_MT_PRESSURE, pressure);
 	input_mt_sync(ts->input);
 }
 
@@ -227,8 +226,7 @@
 	}
 
 	for (i = 0; i < ts->prev_touches - touches; i++) {
-		input_report_abs(ts->input, ABS_MT_TOUCH_MAJOR, 0);
-		input_report_abs(ts->input, ABS_MT_WIDTH_MAJOR, 0);
+		input_report_abs(ts->input, ABS_MT_PRESSURE, 0);
 		input_mt_sync(ts->input);
 	}
 
@@ -263,8 +261,7 @@
 		}
 	} else {
 		for (i = 0; i < ts->prev_touches; i++) {
-			input_report_abs(ts->input, ABS_MT_TOUCH_MAJOR,	0);
-			input_report_abs(ts->input, ABS_MT_WIDTH_MAJOR,	0);
+			input_report_abs(ts->input, ABS_MT_PRESSURE,	0);
 			input_mt_sync(ts->input);
 		}
 	}
@@ -402,10 +399,8 @@
 			ts->pdata->dis_min_x, ts->pdata->dis_max_x, 0, 0);
 	input_set_abs_params(input_device, ABS_MT_POSITION_Y,
 			ts->pdata->dis_min_y, ts->pdata->dis_max_y, 0, 0);
-	input_set_abs_params(input_device, ABS_MT_TOUCH_MAJOR,
+	input_set_abs_params(input_device, ABS_MT_PRESSURE,
 			ts->pdata->min_touch, ts->pdata->max_touch, 0, 0);
-	input_set_abs_params(input_device, ABS_MT_WIDTH_MAJOR,
-			ts->pdata->min_width, ts->pdata->max_width, 0, 0);
 	input_set_abs_params(input_device, ABS_MT_TRACKING_ID,
 			ts->pdata->min_tid, ts->pdata->max_tid, 0, 0);
 
diff --git a/drivers/input/touchscreen/cyttsp-i2c.c b/drivers/input/touchscreen/cyttsp-i2c.c
index 4aa4796..9df1189 100644
--- a/drivers/input/touchscreen/cyttsp-i2c.c
+++ b/drivers/input/touchscreen/cyttsp-i2c.c
@@ -935,6 +935,7 @@
 	u16 st_x2, st_y2;
 	u8 st_z2;
 	s32 retval;
+	int val;
 
 	cyttsp_xdebug("TTSP handler start 1:\n");
 
@@ -1239,16 +1240,20 @@
 			FLIP_XY(g_xy_data.x4, g_xy_data.y4);
 
 		if (rev_x) {
-			g_xy_data.x4 = INVERT_X(g_xy_data.x4,
-						ts->platform_data->panel_maxx);
-			if (g_xy_data.x4 < 0)
+			val = INVERT_X(g_xy_data.x4,
+					ts->platform_data->panel_maxx);
+			if (val >= 0)
+				g_xy_data.x4 = val;
+			else
 				pr_debug("X value is negative. Please configure"
 					" maxx in platform data structure\n");
 		}
 		if (rev_y) {
-			g_xy_data.y4 = INVERT_X(g_xy_data.y4,
-						ts->platform_data->panel_maxy);
-			if (g_xy_data.y4 < 0)
+			val = INVERT_X(g_xy_data.y4,
+					ts->platform_data->panel_maxy);
+			if (val >= 0)
+				g_xy_data.y4 = val;
+			else
 				pr_debug("Y value is negative. Please configure"
 					" maxy in platform data structure\n");
 
@@ -1293,17 +1298,21 @@
 			FLIP_XY(g_xy_data.x3, g_xy_data.y3);
 
 		if (rev_x) {
-			g_xy_data.x3 = INVERT_X(g_xy_data.x3,
-						ts->platform_data->panel_maxx);
-			if (g_xy_data.x3 < 0)
+			val = INVERT_X(g_xy_data.x3,
+					ts->platform_data->panel_maxx);
+			if (val >= 0)
+				g_xy_data.x3 = val;
+			else
 				pr_debug("X value is negative. Please configure"
 					" maxx in platform data structure\n");
 
 		}
 		if (rev_y) {
-			g_xy_data.y3 = INVERT_X(g_xy_data.y3,
-						ts->platform_data->panel_maxy);
-			if (g_xy_data.y3 < 0)
+			val = INVERT_X(g_xy_data.y3,
+					ts->platform_data->panel_maxy);
+			if (val >= 0)
+				g_xy_data.y3 = val;
+			else
 				pr_debug("Y value is negative. Please configure"
 					" maxy in platform data structure\n");
 
@@ -1348,16 +1357,20 @@
 			FLIP_XY(g_xy_data.x2, g_xy_data.y2);
 
 		if (rev_x) {
-			g_xy_data.x2 = INVERT_X(g_xy_data.x2,
-						ts->platform_data->panel_maxx);
-			if (g_xy_data.x2 < 0)
+			val = INVERT_X(g_xy_data.x2,
+					ts->platform_data->panel_maxx);
+			if (val >= 0)
+				g_xy_data.x2 = val;
+			else
 				pr_debug("X value is negative. Please configure"
 					" maxx in platform data structure\n");
 		}
 		if (rev_y) {
-			g_xy_data.y2 = INVERT_X(g_xy_data.y2,
-						ts->platform_data->panel_maxy);
-			if (g_xy_data.y2 < 0)
+			val = INVERT_X(g_xy_data.y2,
+					ts->platform_data->panel_maxy);
+			if (val >= 0)
+				g_xy_data.y2 = val;
+			else
 				pr_debug("Y value is negative. Please configure"
 					" maxy in platform data structure\n");
 		}
@@ -1401,16 +1414,20 @@
 			FLIP_XY(g_xy_data.x1, g_xy_data.y1);
 
 		if (rev_x) {
-			g_xy_data.x1 = INVERT_X(g_xy_data.x1,
-						ts->platform_data->panel_maxx);
-			if (g_xy_data.x1 < 0)
+			val = INVERT_X(g_xy_data.x1,
+					ts->platform_data->panel_maxx);
+			if (val >= 0)
+				g_xy_data.x1 = val;
+			else
 				pr_debug("X value is negative. Please configure"
 					" maxx in platform data structure\n");
 		}
 		if (rev_y) {
-			g_xy_data.y1 = INVERT_X(g_xy_data.y1,
-						ts->platform_data->panel_maxy);
-			if (g_xy_data.y1 < 0)
+			val = INVERT_X(g_xy_data.y1,
+					ts->platform_data->panel_maxy);
+			if (val >= 0)
+				g_xy_data.y1 = val;
+			else
 				pr_debug("Y value is negative. Please configure"
 					" maxy in platform data structure");
 		}
@@ -2744,7 +2761,7 @@
 	ts = kzalloc(sizeof(struct cyttsp), GFP_KERNEL);
 	if (ts == NULL) {
 		cyttsp_xdebug1("err kzalloc for cyttsp\n");
-		retval = -ENOMEM;
+		return -ENOMEM;
 	}
 
 	/* Enable runtime PM ops, start in ACTIVE mode */
@@ -2779,10 +2796,8 @@
 		error = cyttsp_initialize(client, ts);
 		if (error) {
 			cyttsp_xdebug1("err cyttsp_initialize\n");
-			if (ts != NULL) {
-				/* deallocate memory */
-				kfree(ts);
-			}
+			/* deallocate memory */
+			kfree(ts);
 /*
 			i2c_del_driver(&cyttsp_driver);
 */
@@ -3054,8 +3069,7 @@
 		gpio_free(ts->platform_data->irq_gpio);
 
 	/* housekeeping */
-	if (ts != NULL)
-		kfree(ts);
+	kfree(ts);
 
 	cyttsp_alert("Leaving\n");
 
diff --git a/drivers/media/video/msm/Kconfig b/drivers/media/video/msm/Kconfig
index 9361f5a9..0d822bb 100644
--- a/drivers/media/video/msm/Kconfig
+++ b/drivers/media/video/msm/Kconfig
@@ -168,12 +168,6 @@
 	depends on MSM_CAMERA && ARCH_MSM8960
 	default y
 
-config QS_MT9P017
-	bool "Sensor qs_mt9p017 (Aptina 3D 5M)"
-	depends on MSM_CAMERA
-	---help---
-	  Aptina 3D 5M with Autofocus
-
 config VB6801
 	bool "Sensor vb6801"
 	depends on MSM_CAMERA && !ARCH_MSM8X60 && !MSM_CAMERA_V4L2
diff --git a/drivers/media/video/msm/Makefile b/drivers/media/video/msm/Makefile
index a6b7f48..6f39576 100644
--- a/drivers/media/video/msm/Makefile
+++ b/drivers/media/video/msm/Makefile
@@ -35,7 +35,6 @@
   obj-$(CONFIG_IMX074) += imx074.o imx074_reg.o
 endif
 obj-$(CONFIG_QS_S5K4E1) += qs_s5k4e1.o qs_s5k4e1_reg.o
-obj-$(CONFIG_QS_MT9P017) += qs_mt9p017.o qs_mt9p017_reg.o
 obj-$(CONFIG_VB6801) += vb6801.o
 obj-$(CONFIG_IMX072) += imx072.o imx072_reg.o
 obj-$(CONFIG_WEBCAM_OV9726) += ov9726.o ov9726_reg.o
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index f7a1fa8..251f12d 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -1497,12 +1497,7 @@
 		}
 	}
 	pcam_inst->vbqueue_initialized = 0;
-	/* Initialize the video queue */
-	rc = pcam->mctl.mctl_buf_init(pcam_inst);
-	if (rc < 0) {
-		mutex_unlock(&pcam->vid_lock);
-		return rc;
-	}
+	rc = 0;
 
 	f->private_data = &pcam_inst->eventHandle;
 
@@ -1630,7 +1625,6 @@
 #ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 		ion_client_destroy(pcam->mctl.client);
 #endif
-		dma_release_declared_memory(&pcam->pdev->dev);
 	}
 	mutex_unlock(&pcam->vid_lock);
 	return rc;
diff --git a/drivers/media/video/msm/msm_camera.c b/drivers/media/video/msm/msm_camera.c
index 7f43136..e401a7a 100644
--- a/drivers/media/video/msm/msm_camera.c
+++ b/drivers/media/video/msm/msm_camera.c
@@ -3815,6 +3815,14 @@
 	return rc;
 }
 
+static int msm_open_frame(struct inode *inode, struct file *filep)
+{
+	struct msm_cam_device *pmsm =
+		container_of(inode->i_cdev, struct msm_cam_device, cdev);
+	msm_queue_drain(&pmsm->sync->frame_q, list_frame);
+	return msm_open_common(inode, filep, 1, 0);
+}
+
 static int msm_open(struct inode *inode, struct file *filep)
 {
 	return msm_open_common(inode, filep, 1, 0);
@@ -3863,7 +3871,7 @@
 
 static const struct file_operations msm_fops_frame = {
 	.owner = THIS_MODULE,
-	.open = msm_open,
+	.open = msm_open_frame,
 	.unlocked_ioctl = msm_ioctl_frame,
 	.release = msm_release_frame,
 	.poll = msm_poll_frame,
diff --git a/drivers/media/video/msm/msm_mctl_buf.c b/drivers/media/video/msm/msm_mctl_buf.c
index aed70bc..c7c7cf6 100644
--- a/drivers/media/video/msm/msm_mctl_buf.c
+++ b/drivers/media/video/msm/msm_mctl_buf.c
@@ -319,52 +319,6 @@
 	return 0;
 }
 
-static int msm_buf_init(struct msm_cam_v4l2_dev_inst *pcam_inst)
-{
-	int rc = 0;
-	struct resource *res;
-	struct platform_device *pdev = NULL;
-	struct msm_cam_v4l2_device *pcam = NULL;
-
-	D("%s\n", __func__);
-	pcam = pcam_inst->pcam;
-	if (!pcam) {
-		pr_err("%s error : input is NULL\n", __func__);
-		return -EINVAL;
-	} else
-		pdev = pcam->mctl.sync.pdev;
-
-	if (!pdev) {
-		pr_err("%s error : pdev is NULL\n", __func__);
-		return -EINVAL;
-	}
-	if (pcam->use_count == 1) {
-		/* first check if we have resources */
-		res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-		if (res) {
-			D("res->start = 0x%x\n", (u32)res->start);
-			D("res->size = 0x%x\n", (u32)resource_size(res));
-			D("res->end = 0x%x\n", (u32)res->end);
-			rc = dma_declare_coherent_memory(&pdev->dev, res->start,
-					res->start,
-					resource_size(res),
-					DMA_MEMORY_MAP |
-					DMA_MEMORY_EXCLUSIVE);
-			if (!rc) {
-				pr_err("%s: Unable to declare coherent memory.\n",
-				__func__);
-				rc = -ENXIO;
-				return rc;
-			}
-			D("%s: found DMA capable resource\n", __func__);
-		} else {
-			pr_err("%s: no DMA capable resource\n", __func__);
-			return -ENOMEM;
-		}
-	}
-	return 0;
-}
-
 int msm_mctl_out_type_to_inst_index(struct msm_cam_v4l2_device *pcam,
 					int out_type)
 {
@@ -502,7 +456,6 @@
 
 int msm_mctl_buf_init(struct msm_cam_v4l2_device *pcam)
 {
-	pcam->mctl.mctl_buf_init = msm_buf_init;
 	pcam->mctl.mctl_vbqueue_init = msm_vbqueue_init;
 	return 0;
 }
diff --git a/drivers/media/video/msm/qs_mt9p017.c b/drivers/media/video/msm/qs_mt9p017.c
deleted file mode 100644
index d160af8..0000000
--- a/drivers/media/video/msm/qs_mt9p017.c
+++ /dev/null
@@ -1,1255 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/debugfs.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <linux/slab.h>
-#include <media/msm_camera.h>
-#include <media/v4l2-subdev.h>
-#include <mach/gpio.h>
-#include <mach/camera.h>
-#include "qs_mt9p017.h"
-#include "msm.h"
-/*
-* =============================================================
-*	SENSOR REGISTER DEFINES
-* ==============================================================
-*/
-#define REG_GROUPED_PARAMETER_HOLD		0x0104
-#define GROUPED_PARAMETER_HOLD_OFF		0x00
-#define GROUPED_PARAMETER_HOLD			0x01
-/* Integration Time */
-#define REG_COARSE_INTEGRATION_TIME		0x3012
-/* Gain */
-#define REG_GLOBAL_GAIN					0x305E
-#define REG_GR_GAIN						0x3056
-#define REG_R_GAIN						0x3058
-#define REG_B_GAIN						0x305A
-#define REG_GB_GAIN						0x305C
-
-/* PLL registers */
-#define REG_FRAME_LENGTH_LINES			0x300A
-#define REG_LINE_LENGTH_PCK				0x300C
-/* Test Pattern */
-#define REG_TEST_PATTERN_MODE			0x0601
-#define REG_VCM_NEW_CODE				0x30F2
-#define AF_ADDR							0x18
-#define BRIDGE_ADDR						0x80
-/*
-* ============================================================================
-*							 TYPE DECLARATIONS
-* ============================================================================
-*/
-
-/* 16bit address - 8 bit context register structure */
-#define Q8  0x00000100
-#define Q10 0x00000400
-#define QS_MT9P017_MASTER_CLK_RATE 24000000
-#define QS_MT9P017_OFFSET			8
-
-/* AF Total steps parameters */
-#define QS_MT9P017_TOTAL_STEPS_NEAR_TO_FAR    32
-#define QS_MT9P017_NL_REGION_BOUNDARY 3
-#define QS_MT9P017_NL_REGION_CODE_PER_STEP 30
-#define QS_MT9P017_L_REGION_CODE_PER_STEP 4
-
-#define QS_MT9P017_BRIDGE_DBG 0
-
-static struct i2c_client *qs_mt9p017_client;
-
-struct qs_mt9p017_format {
-	enum v4l2_mbus_pixelcode code;
-	enum v4l2_colorspace colorspace;
-	u16 fmt;
-	u16 order;
-};
-
-struct qs_mt9p017_ctrl_t {
-	const struct  msm_camera_sensor_info *sensordata;
-
-	uint32_t sensormode;
-	uint32_t fps_divider;/* init to 1 * 0x00000400 */
-	uint32_t pict_fps_divider;/* init to 1 * 0x00000400 */
-	uint16_t fps;
-
-	uint16_t curr_lens_pos;
-	uint16_t curr_step_pos;
-	uint16_t my_reg_gain;
-	uint32_t my_reg_line_count;
-	uint16_t total_lines_per_frame;
-
-	enum qs_mt9p017_resolution_t prev_res;
-	enum qs_mt9p017_resolution_t pict_res;
-	enum qs_mt9p017_resolution_t curr_res;
-	enum qs_mt9p017_cam_mode_t cam_mode;
-	struct v4l2_subdev *sensor_dev;
-	struct qs_mt9p017_format *fmt;
-	uint16_t qs_mt9p017_step_position_table
-		[QS_MT9P017_TOTAL_STEPS_NEAR_TO_FAR+1];
-	uint16_t prev_line_length_pck;
-	uint16_t prev_frame_length_lines;
-	uint16_t snap_line_length_pck;
-	uint16_t snap_frame_length_lines;
-};
-
-static bool CSI_CONFIG;
-static struct qs_mt9p017_ctrl_t *qs_mt9p017_ctrl;
-DEFINE_MUTEX(qs_mt9p017_mut);
-/*=============================================================*/
-
-static int qs_mt9p017_i2c_rxdata(unsigned short saddr,
-	unsigned char *rxdata, int length)
-{
-	struct i2c_msg msgs[] = {
-		{
-			.addr  = saddr,
-			.flags = 0,
-			.len   = length,
-			.buf   = rxdata,
-		},
-		{
-			.addr  = saddr,
-			.flags = I2C_M_RD,
-			.len   = length,
-			.buf   = rxdata,
-		},
-	};
-	if (i2c_transfer(qs_mt9p017_client->adapter, msgs, 2) < 0) {
-		CDBG("qs_mt9p017_i2c_rxdata faild 0x%x\n", saddr);
-		return -EIO;
-	}
-	return 0;
-}
-
-static int32_t qs_mt9p017_i2c_txdata(unsigned short saddr,
-				unsigned char *txdata, int length)
-{
-	struct i2c_msg msg[] = {
-		{
-			.addr = saddr,
-			.flags = 0,
-			.len = length,
-			.buf = txdata,
-		 },
-	};
-	if (i2c_transfer(qs_mt9p017_client->adapter, msg, 1) < 0) {
-		CDBG("qs_mt9p017_i2c_txdata faild 0x%x\n", saddr);
-		return -EIO;
-	}
-
-	return 0;
-}
-
-static int32_t qs_mt9p017_i2c_read(unsigned short raddr,
-	unsigned short *rdata, int rlen)
-{
-	int32_t rc = 0;
-	unsigned char buf[] = {
-		raddr >> BITS_PER_BYTE,
-		raddr,
-	};
-	if (!rdata)
-		return -EIO;
-	rc = qs_mt9p017_i2c_rxdata(qs_mt9p017_client->addr, buf, rlen);
-	if (rc < 0) {
-		CDBG("qs_mt9p017_i2c_read 0x%x failed!\n", raddr);
-		return rc;
-	}
-	*rdata = (rlen == 2 ? buf[0] << BITS_PER_BYTE | buf[1] : buf[0]);
-	CDBG("qs_mt9p017_i2c_read 0x%x val = 0x%x!\n", raddr, *rdata);
-	return rc;
-}
-
-static int32_t qs_mt9p017_i2c_write_w_sensor(unsigned short waddr,
-	uint16_t wdata)
-{
-	int32_t rc = -EFAULT;
-	unsigned char buf[] = {
-		waddr >> BITS_PER_BYTE,
-		waddr,
-		wdata >> BITS_PER_BYTE,
-		wdata,
-	};
-	CDBG("i2c_write_b addr = 0x%x, val = 0x%x\n", waddr, wdata);
-	rc = qs_mt9p017_i2c_txdata(qs_mt9p017_client->addr, buf, 4);
-	if (rc < 0) {
-		CDBG("i2c_write_b failed, addr = 0x%x, val = 0x%x!\n",
-			waddr, wdata);
-	}
-	return rc;
-}
-
-static int32_t qs_mt9p017_i2c_write_b_sensor(unsigned short waddr,
-	uint8_t bdata)
-{
-	int32_t rc = -EFAULT;
-	unsigned char buf[] = {
-		waddr >> BITS_PER_BYTE,
-		waddr,
-		bdata,
-	};
-	CDBG("i2c_write_b addr = 0x%x, val = 0x%x\n", waddr, bdata);
-	rc = qs_mt9p017_i2c_txdata(qs_mt9p017_client->addr, buf, 3);
-	if (rc < 0) {
-		CDBG("i2c_write_b failed, addr = 0x%x, val = 0x%x!\n",
-			waddr, bdata);
-	}
-	return rc;
-}
-
-static int32_t qs_mt9p017_i2c_write_seq_sensor(unsigned short waddr,
-		unsigned char *seq_data, int len)
-{
-	int32_t rc = -EFAULT;
-	unsigned char buf[len+2];
-	int i = 0;
-	buf[0] = waddr >> BITS_PER_BYTE;
-	buf[1] = waddr;
-	for (i = 0; i < len; i++)
-		buf[i+2] = seq_data[i];
-	rc = qs_mt9p017_i2c_txdata(qs_mt9p017_client->addr, buf, len+2);
-	return rc;
-}
-
-static int32_t qs_mt9p017_i2c_write_w_table(struct qs_mt9p017_i2c_reg_conf const
-					 *reg_conf_tbl, int num)
-{
-	int i;
-	int32_t rc = -EIO;
-	for (i = 0; i < num; i++) {
-		rc = qs_mt9p017_i2c_write_w_sensor(reg_conf_tbl->waddr,
-			reg_conf_tbl->wdata);
-		if (rc < 0)
-			break;
-		reg_conf_tbl++;
-	}
-	return rc;
-}
-
-static int32_t bridge_i2c_write_w(unsigned short waddr, uint16_t wdata)
-{
-	int32_t rc = -EFAULT;
-	unsigned char buf[] = {
-		waddr >> BITS_PER_BYTE,
-		waddr,
-		wdata >> BITS_PER_BYTE,
-		wdata,
-	};
-	CDBG("bridge_i2c_write_w addr = 0x%x, val = 0x%x\n", waddr, wdata);
-	rc = qs_mt9p017_i2c_txdata(BRIDGE_ADDR>>1, buf, 4);
-	if (rc < 0) {
-		CDBG("bridge_i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
-			waddr, wdata);
-	}
-	return rc;
-}
-
-static int32_t bridge_i2c_read(unsigned short raddr,
-	unsigned short *rdata, int rlen)
-{
-	int32_t rc = 0;
-	unsigned char buf[] = {
-		raddr >> BITS_PER_BYTE,
-		raddr,
-	};
-	if (!rdata)
-		return -EIO;
-	rc = qs_mt9p017_i2c_rxdata(BRIDGE_ADDR>>1, buf, rlen);
-	if (rc < 0) {
-		CDBG("bridge_i2c_read 0x%x failed!\n", raddr);
-		return rc;
-	}
-	*rdata = (rlen == 2 ? buf[0] << BITS_PER_BYTE | buf[1] : buf[0]);
-	CDBG("bridge_i2c_read 0x%x val = 0x%x!\n", raddr, *rdata);
-	return rc;
-}
-
-static int32_t qs_mt9p017_eeprom_i2c_read(unsigned short raddr,
-	unsigned char *rdata, int rlen)
-{
-	int32_t rc = 0;
-	unsigned short i2caddr = 0xA0 >> 1;
-	uint8_t block_num = 0;
-	unsigned char buf[rlen+2];
-	int i = 0;
-	if (!rdata)
-		return -EIO;
-
-	block_num = raddr >> BITS_PER_BYTE;
-	i2caddr |= block_num;
-
-	buf[0] = raddr >> BITS_PER_BYTE;
-	buf[1] = raddr;
-	rc = qs_mt9p017_i2c_rxdata(i2caddr, buf, rlen);
-	if (rc < 0) {
-		CDBG("qs_mt9p017_eeprom_i2c_read 0x%x failed!\n", raddr);
-		return rc;
-	}
-	for (i = 0; i < rlen; i++) {
-		rdata[i] = buf[i];
-		CDBG("qs_mt9p017_eeprom_i2c_read 0x%x index: %d val = 0x%x!\n",
-			raddr, i, buf[i]);
-	}
-	return rc;
-}
-
-static int32_t qs_mt9p017_eeprom_i2c_read_b(unsigned short raddr,
-	unsigned short *rdata, int rlen)
-{
-	int32_t rc = 0;
-	unsigned char buf[2];
-	rc = qs_mt9p017_eeprom_i2c_read(raddr, &buf[0], rlen);
-	*rdata = (rlen == 2 ? buf[0] << BITS_PER_BYTE | buf[1] : buf[0]);
-	CDBG("qs_mt9p017_eeprom_i2c_read 0x%x val = 0x%x!\n", raddr, *rdata);
-	return rc;
-}
-
-static int32_t qs_mt9p017_get_calibration_data(
-	struct sensor_3d_cali_data_t *cdata)
-{
-	struct qs_mt9p017_i2c_read_seq_t eeprom_read_seq_tbl[] = {
-		{0x0, &(cdata->left_p_matrix[0][0][0]), 96},
-		{0x60, &(cdata->right_p_matrix[0][0][0]), 96},
-		{0xC0, &(cdata->square_len[0]), 8},
-		{0xC8, &(cdata->focal_len[0]), 8},
-		{0xD0, &(cdata->pixel_pitch[0]), 8},
-	};
-
-	struct qs_mt9p017_i2c_read_t eeprom_read_tbl[] = {
-		{0x100, &(cdata->left_r), 1},
-		{0x101, &(cdata->right_r), 1},
-		{0x102, &(cdata->left_b), 1},
-		{0x103, &(cdata->right_b), 1},
-		{0x104, &(cdata->left_gb), 1},
-		{0x105, &(cdata->right_gb), 1},
-		{0x110, &(cdata->left_af_far), 2},
-		{0x112, &(cdata->right_af_far), 2},
-		{0x114, &(cdata->left_af_mid), 2},
-		{0x116, &(cdata->right_af_mid), 2},
-		{0x118, &(cdata->left_af_short), 2},
-		{0x11A, &(cdata->right_af_short), 2},
-		{0x11C, &(cdata->left_af_5um), 2},
-		{0x11E, &(cdata->right_af_5um), 2},
-		{0x120, &(cdata->left_af_50up), 2},
-		{0x122, &(cdata->right_af_50up), 2},
-		{0x124, &(cdata->left_af_50down), 2},
-		{0x126, &(cdata->right_af_50down), 2},
-	};
-
-	int i;
-	for (i = 0; i < ARRAY_SIZE(eeprom_read_seq_tbl); i++) {
-		qs_mt9p017_eeprom_i2c_read(
-			eeprom_read_seq_tbl[i].raddr,
-			eeprom_read_seq_tbl[i].rdata,
-			eeprom_read_seq_tbl[i].rlen);
-	}
-
-	for (i = 0; i < ARRAY_SIZE(eeprom_read_tbl); i++) {
-		qs_mt9p017_eeprom_i2c_read_b(
-			eeprom_read_tbl[i].raddr,
-			eeprom_read_tbl[i].rdata,
-			eeprom_read_tbl[i].rlen);
-	}
-	return 0;
-}
-
-static int32_t qs_mt9p017_load_left_lsc(void)
-{
-	int i;
-	unsigned char left_lsc1[210];
-	unsigned short left_origin_c, left_origin_r;
-	struct qs_mt9p017_i2c_reg_conf lsc_conf[] = {
-		{0x37C0, 0x0000},
-		{0x37C2, 0x0000},
-		{0x37C4, 0x0000},
-		{0x37C6, 0x0000},
-		{0x3780, 0x8000},
-	};
-	qs_mt9p017_eeprom_i2c_read(0x200, &left_lsc1[0], 126);
-	qs_mt9p017_eeprom_i2c_read_b(0x27E, &left_origin_c, 2);
-	qs_mt9p017_eeprom_i2c_read_b(0x280, &left_origin_r, 2);
-	bridge_i2c_write_w(0x06, 0x01);
-	qs_mt9p017_i2c_write_seq_sensor(0x3600, left_lsc1, 126);
-	qs_mt9p017_i2c_write_w_sensor(0x3782, left_origin_c);
-	qs_mt9p017_i2c_write_w_sensor(0x3784, left_origin_r);
-	for (i = 0; i < ARRAY_SIZE(lsc_conf); i++) {
-		qs_mt9p017_i2c_write_w_sensor(
-			lsc_conf[i].waddr, lsc_conf[i].wdata);
-	}
-	return 0;
-}
-
-static int32_t qs_mt9p017_load_right_lsc(void)
-{
-	int i;
-	unsigned char right_lsc1[210];
-	unsigned short right_origin_c, right_origin_r;
-	struct qs_mt9p017_i2c_reg_conf lsc_conf[] = {
-		{0x37C0, 0x0000},
-		{0x37C2, 0x0000},
-		{0x37C4, 0x0000},
-		{0x37C6, 0x0000},
-		{0x3780, 0x8000},
-	};
-	qs_mt9p017_eeprom_i2c_read(0x2D2, &right_lsc1[0], 126);
-	qs_mt9p017_eeprom_i2c_read_b(0x350, &right_origin_c, 2);
-	qs_mt9p017_eeprom_i2c_read_b(0x352, &right_origin_r, 2);
-	bridge_i2c_write_w(0x06, 0x02);
-	qs_mt9p017_i2c_write_seq_sensor(0x3600, right_lsc1, 126);
-	qs_mt9p017_i2c_write_w_sensor(0x3782, right_origin_c);
-	qs_mt9p017_i2c_write_w_sensor(0x3784, right_origin_r);
-
-	for (i = 0; i < ARRAY_SIZE(lsc_conf); i++) {
-		qs_mt9p017_i2c_write_w_sensor(
-			lsc_conf[i].waddr, lsc_conf[i].wdata);
-	}
-	return 0;
-}
-
-static int32_t qs_mt9p017_load_lsc(void)
-{
-	qs_mt9p017_load_left_lsc();
-	qs_mt9p017_load_right_lsc();
-	return 0;
-}
-
-static int32_t af_i2c_write_b_sensor(unsigned short baddr, uint8_t bdata)
-{
-	int32_t rc = -EFAULT;
-	unsigned char buf[2];
-	buf[0] = baddr;
-	buf[1] = bdata;
-	CDBG("af i2c_write_b addr = 0x%x, val = 0x%x\n", baddr, bdata);
-	rc = qs_mt9p017_i2c_txdata(AF_ADDR>>1, buf, 2);
-	if (rc < 0) {
-		CDBG("af i2c_write_b failed, addr = 0x%x, val = 0x%x!\n",
-			baddr, bdata);
-	}
-	return rc;
-}
-
-static void qs_mt9p017_bridge_reset(void){
-	unsigned short rstl_state = 0, gpio_state = 0;
-	bridge_i2c_write_w(0x50, 0x00);
-	bridge_i2c_write_w(0x53, 0x00);
-	msleep(30);
-	bridge_i2c_write_w(0x53, 0x01);
-	msleep(30);
-	bridge_i2c_write_w(0x14, 0x0C);
-	bridge_i2c_write_w(0x0E, 0xFFFF);
-
-	bridge_i2c_read(0x54, &rstl_state, 2);
-	bridge_i2c_write_w(0x54, (rstl_state | 0x1));
-	msleep(30);
-	bridge_i2c_write_w(0x54, (rstl_state | 0x3));
-	bridge_i2c_read(0x54, &rstl_state, 2);
-	bridge_i2c_write_w(0x54, (rstl_state | 0x4));
-	bridge_i2c_write_w(0x54, (rstl_state | 0xC));
-
-	bridge_i2c_read(0x55, &gpio_state, 2);
-	bridge_i2c_write_w(0x55, (gpio_state | 0x1));
-	msleep(30);
-	bridge_i2c_write_w(0x55, (gpio_state | 0x3));
-
-	bridge_i2c_read(0x55, &gpio_state, 2);
-	bridge_i2c_write_w(0x55, (gpio_state | 0x4));
-	msleep(30);
-	bridge_i2c_write_w(0x55, (gpio_state | 0xC));
-	bridge_i2c_read(0x55, &gpio_state, 2);
-}
-
-static void qs_mt9p017_bridge_config(int mode, int rt)
-{
-	if (mode == MODE_3D) {
-		bridge_i2c_write_w(0x16, 0x00);
-		bridge_i2c_write_w(0x51, 0x3);
-		bridge_i2c_write_w(0x52, 0x1);
-		bridge_i2c_write_w(0x06, 0x03);
-		bridge_i2c_write_w(0x04, 0x6C18);
-		bridge_i2c_write_w(0x50, 0x00);
-	} else if (mode == MODE_2D_LEFT) {
-		bridge_i2c_write_w(0x06, 0x01);
-		bridge_i2c_write_w(0x04, 0x6C18);
-		bridge_i2c_write_w(0x50, 0x01);
-	} else if (mode == MODE_2D_RIGHT) {
-		bridge_i2c_write_w(0x06, 0x02);
-		bridge_i2c_write_w(0x04, 0x6C18);
-		bridge_i2c_write_w(0x50, 0x02);
-	}
-}
-
-static void qs_mt9p017_group_hold_on(void)
-{
-	qs_mt9p017_i2c_write_b_sensor(REG_GROUPED_PARAMETER_HOLD,
-						GROUPED_PARAMETER_HOLD);
-}
-
-static void qs_mt9p017_group_hold_off(void)
-{
-	qs_mt9p017_i2c_write_b_sensor(REG_GROUPED_PARAMETER_HOLD,
-						GROUPED_PARAMETER_HOLD_OFF);
-}
-
-static void qs_mt9p017_start_stream(void)
-{
-	qs_mt9p017_i2c_write_w_sensor(0x301A, 0x065C|0x2);
-}
-
-static void qs_mt9p017_stop_stream(void)
-{
-	qs_mt9p017_i2c_write_b_sensor(0x0100, 0x00);
-}
-
-static void qs_mt9p017_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
-	/* input fps is preview fps in Q8 format */
-	uint32_t divider, d1, d2;
-
-	d1 = qs_mt9p017_ctrl->prev_frame_length_lines * 0x400
-		/ qs_mt9p017_ctrl->snap_frame_length_lines;
-	d2 = qs_mt9p017_ctrl->prev_line_length_pck * 0x400
-		/ qs_mt9p017_ctrl->snap_line_length_pck;
-	divider = d1 * d2 / 0x400;
-
-	/*Verify PCLK settings and frame sizes.*/
-	*pfps = (uint16_t) (fps * divider / 0x400);
-	/* 2 is the ratio of no.of snapshot channels
-	to number of preview channels */
-}
-
-static int32_t qs_mt9p017_set_fps(struct fps_cfg   *fps)
-{
-	uint16_t total_lines_per_frame;
-	int32_t rc = 0;
-	total_lines_per_frame = (uint16_t)
-		((qs_mt9p017_ctrl->prev_frame_length_lines) *
-		qs_mt9p017_ctrl->fps_divider/0x400);
-	qs_mt9p017_ctrl->fps_divider = fps->fps_div;
-	qs_mt9p017_ctrl->pict_fps_divider = fps->pict_fps_div;
-
-	qs_mt9p017_group_hold_on();
-	rc = qs_mt9p017_i2c_write_w_sensor(REG_FRAME_LENGTH_LINES,
-							total_lines_per_frame);
-	qs_mt9p017_group_hold_off();
-	return rc;
-}
-
-static int32_t qs_mt9p017_write_exp_gain(struct sensor_3d_exp_cfg exp_cfg)
-{
-	uint16_t max_legal_gain = 0xE7F;
-	uint16_t gain = exp_cfg.gain;
-	uint32_t line = exp_cfg.line;
-	int32_t rc = 0;
-	if (gain > max_legal_gain) {
-		CDBG("Max legal gain Line:%d\n", __LINE__);
-		gain = max_legal_gain;
-	}
-	qs_mt9p017_group_hold_on();
-	rc = qs_mt9p017_i2c_write_w_sensor(REG_GLOBAL_GAIN, gain|0x1000);
-	rc = qs_mt9p017_i2c_write_w_sensor(REG_COARSE_INTEGRATION_TIME, line);
-	if (qs_mt9p017_ctrl->cam_mode == MODE_3D) {
-		bridge_i2c_write_w(0x06, 0x02);
-		rc = qs_mt9p017_i2c_write_w_sensor(REG_GR_GAIN, gain|0x1000);
-		rc = qs_mt9p017_i2c_write_w_sensor(REG_R_GAIN,
-				exp_cfg.r_gain|0x1000);
-		rc = qs_mt9p017_i2c_write_w_sensor(REG_B_GAIN,
-				exp_cfg.b_gain|0x1000);
-		rc = qs_mt9p017_i2c_write_w_sensor(REG_GB_GAIN,
-				exp_cfg.gb_gain|0x1000);
-		bridge_i2c_write_w(0x06, 0x03);
-	}
-	qs_mt9p017_group_hold_off();
-	return rc;
-}
-
-static int32_t qs_mt9p017_set_pict_exp_gain(struct sensor_3d_exp_cfg exp_cfg)
-{
-	int32_t rc = 0;
-	rc = qs_mt9p017_write_exp_gain(exp_cfg);
-	qs_mt9p017_i2c_write_w_sensor(0x301A, 0x065C|0x2);
-	return rc;
-}
-
-static int32_t qs_mt9p017_move_focus(int direction,
-	int32_t num_steps)
-{
-	int16_t step_direction, actual_step, next_position;
-	uint8_t code_val_msb, code_val_lsb;
-	if (direction == MOVE_NEAR)
-		step_direction = 16;
-	else
-		step_direction = -16;
-
-	actual_step = (int16_t) (step_direction * (int16_t) num_steps);
-	next_position = (int16_t) (qs_mt9p017_ctrl->curr_lens_pos+actual_step);
-
-	if (next_position > 1023)
-		next_position = 1023;
-	else if (next_position < 0)
-		next_position = 0;
-
-	code_val_msb = next_position >> 8;
-	code_val_lsb = (next_position & 0x00FF);
-	af_i2c_write_b_sensor(0x4, code_val_msb);
-	af_i2c_write_b_sensor(0x5, code_val_lsb);
-
-	qs_mt9p017_ctrl->curr_lens_pos = next_position;
-	return 0;
-}
-
-static int32_t qs_mt9p017_set_default_focus(uint8_t af_step)
-{
-	int32_t rc = 0;
-	if (qs_mt9p017_ctrl->curr_step_pos != 0) {
-		rc = qs_mt9p017_move_focus(MOVE_FAR,
-		qs_mt9p017_ctrl->curr_step_pos);
-	} else {
-		af_i2c_write_b_sensor(0x4, 0);
-		af_i2c_write_b_sensor(0x5, 0);
-	}
-
-	qs_mt9p017_ctrl->curr_lens_pos = 0;
-	qs_mt9p017_ctrl->curr_step_pos = 0;
-
-	return rc;
-}
-
-static void qs_mt9p017_init_focus(void)
-{
-	uint8_t i;
-	qs_mt9p017_ctrl->qs_mt9p017_step_position_table[0] = 0;
-	for (i = 1; i <= QS_MT9P017_TOTAL_STEPS_NEAR_TO_FAR; i++) {
-		if (i <= QS_MT9P017_NL_REGION_BOUNDARY) {
-			qs_mt9p017_ctrl->qs_mt9p017_step_position_table[i] =
-			qs_mt9p017_ctrl->qs_mt9p017_step_position_table[i-1]
-				+ QS_MT9P017_NL_REGION_CODE_PER_STEP;
-		} else {
-			qs_mt9p017_ctrl->qs_mt9p017_step_position_table[i] =
-			qs_mt9p017_ctrl->qs_mt9p017_step_position_table[i-1]
-				+ QS_MT9P017_L_REGION_CODE_PER_STEP;
-		}
-
-		if (qs_mt9p017_ctrl->qs_mt9p017_step_position_table[i] > 255)
-			qs_mt9p017_ctrl->
-			qs_mt9p017_step_position_table[i] = 255;
-	}
-}
-
-static int32_t qs_mt9p017_sensor_setting(int update_type, int rt)
-{
-
-	int32_t rc = 0, i;
-	uint16_t read_data;
-	struct msm_camera_csid_params qs_mt9p017_csid_params;
-	struct msm_camera_csiphy_params qs_mt9p017_csiphy_params;
-	qs_mt9p017_stop_stream();
-	msleep(30);
-	bridge_i2c_write_w(0x53, 0x00);
-	msleep(30);
-	if (update_type == REG_INIT) {
-		CSI_CONFIG = 0;
-		qs_mt9p017_bridge_config(qs_mt9p017_ctrl->cam_mode, rt);
-		qs_mt9p017_i2c_write_w_table(qs_mt9p017_regs.rec_settings,
-			qs_mt9p017_regs.rec_size);
-		if (qs_mt9p017_ctrl->cam_mode == MODE_3D)
-			qs_mt9p017_i2c_write_w_table(qs_mt9p017_regs.reg_3d_pll,
-			qs_mt9p017_regs.reg_3d_pll_size);
-		else
-			qs_mt9p017_i2c_write_w_table(qs_mt9p017_regs.reg_pll,
-			qs_mt9p017_regs.reg_pll_size);
-		qs_mt9p017_i2c_write_w_table(qs_mt9p017_regs.reg_lens,
-			qs_mt9p017_regs.reg_lens_size);
-		qs_mt9p017_i2c_read(0x31BE, &read_data, 2);
-		qs_mt9p017_i2c_write_w_sensor(0x31BE, read_data | 0x4);
-	} else if (update_type == UPDATE_PERIODIC) {
-		qs_mt9p017_i2c_write_w_table(
-			qs_mt9p017_regs.conf_array[rt].conf,
-			qs_mt9p017_regs.conf_array[rt].size);
-
-		msleep(20);
-		bridge_i2c_write_w(0x53, 0x01);
-		msleep(30);
-		if (!CSI_CONFIG) {
-			if (qs_mt9p017_ctrl->cam_mode == MODE_3D) {
-				struct msm_camera_csid_vc_cfg
-					qs_mt9p017_vccfg[] = {
-					{0, CSI_RAW10, CSI_DECODE_10BIT},
-					{1, CSI_EMBED_DATA, CSI_DECODE_8BIT},
-				};
-				qs_mt9p017_csid_params.lane_cnt = 4;
-				qs_mt9p017_csiphy_params.lane_cnt = 4;
-				qs_mt9p017_csid_params.lut_params.num_cid =
-					ARRAY_SIZE(qs_mt9p017_vccfg);
-				qs_mt9p017_csid_params.lut_params.vc_cfg =
-					&qs_mt9p017_vccfg[0];
-			} else {
-				struct msm_camera_csid_vc_cfg
-					qs_mt9p017_vccfg[] = {
-					{0, CSI_RAW10, CSI_DECODE_10BIT},
-					{1, CSI_EMBED_DATA, CSI_DECODE_8BIT},
-				};
-				qs_mt9p017_csid_params.lane_cnt = 2;
-				qs_mt9p017_csiphy_params.lane_cnt = 2;
-				qs_mt9p017_csid_params.lut_params.num_cid =
-					ARRAY_SIZE(qs_mt9p017_vccfg);
-				qs_mt9p017_csid_params.lut_params.vc_cfg =
-					&qs_mt9p017_vccfg[0];
-			}
-			qs_mt9p017_csid_params.lane_assign = 0xe4;
-			qs_mt9p017_csiphy_params.settle_cnt = 0x18;
-			rc = msm_camio_csid_config(&qs_mt9p017_csid_params);
-			rc = msm_camio_csiphy_config
-				(&qs_mt9p017_csiphy_params);
-			v4l2_subdev_notify(qs_mt9p017_ctrl->sensor_dev,
-					NOTIFY_CID_CHANGE, NULL);
-			msleep(100);
-			CSI_CONFIG = 1;
-		}
-		qs_mt9p017_start_stream();
-		msleep(30);
-
-		for (i = 0; i < QS_MT9P017_BRIDGE_DBG; i++) {
-			bridge_i2c_read(0x10, &read_data, 2);
-			CDBG("IRQ Status: 0x%x\n", read_data);
-			bridge_i2c_read(0x0A, &read_data, 2);
-			CDBG("Skew Value: 0x%x\n", read_data);
-		}
-	}
-	return rc;
-}
-
-static int32_t qs_mt9p017_video_config(int mode)
-{
-
-	int32_t rc = 0;
-	/* change sensor resolution if needed */
-	rc = qs_mt9p017_sensor_setting(UPDATE_PERIODIC,
-		qs_mt9p017_ctrl->prev_res);
-	if (rc < 0)
-		return rc;
-
-	qs_mt9p017_ctrl->curr_res = qs_mt9p017_ctrl->prev_res;
-	qs_mt9p017_ctrl->sensormode = mode;
-	return rc;
-}
-
-static int32_t qs_mt9p017_snapshot_config(int mode)
-{
-	int32_t rc = 0;
-	/*change sensor resolution if needed */
-	if (qs_mt9p017_ctrl->curr_res != qs_mt9p017_ctrl->pict_res) {
-		rc = qs_mt9p017_sensor_setting(UPDATE_PERIODIC,
-					qs_mt9p017_ctrl->pict_res);
-		if (rc < 0)
-			return rc;
-	}
-
-	qs_mt9p017_ctrl->curr_res = qs_mt9p017_ctrl->pict_res;
-	qs_mt9p017_ctrl->sensormode = mode;
-	return rc;
-} /*end of qs_mt9p017_snapshot_config*/
-
-static int32_t qs_mt9p017_raw_snapshot_config(int mode)
-{
-	int32_t rc = 0;
-	/* change sensor resolution if needed */
-	if (qs_mt9p017_ctrl->curr_res != qs_mt9p017_ctrl->pict_res) {
-		rc = qs_mt9p017_sensor_setting(UPDATE_PERIODIC,
-					qs_mt9p017_ctrl->pict_res);
-		if (rc < 0)
-			return rc;
-	}
-
-	qs_mt9p017_ctrl->curr_res = qs_mt9p017_ctrl->pict_res;
-	qs_mt9p017_ctrl->sensormode = mode;
-	return rc;
-} /*end of qs_mt9p017_raw_snapshot_config*/
-
-static int32_t qs_mt9p017_mode_init(int mode, struct sensor_init_cfg init_info)
-{
-	int32_t rc = 0;
-	if (mode == qs_mt9p017_ctrl->cam_mode)
-		return rc;
-
-	qs_mt9p017_ctrl->prev_res = init_info.prev_res;
-	qs_mt9p017_ctrl->pict_res = init_info.pict_res;
-	qs_mt9p017_ctrl->cam_mode = mode;
-
-	qs_mt9p017_ctrl->prev_frame_length_lines =
-		qs_mt9p017_regs.conf_array[qs_mt9p017_ctrl->prev_res].
-		conf[QS_MT9P017_FRAME_LENGTH_LINES].wdata;
-	qs_mt9p017_ctrl->prev_line_length_pck =
-		qs_mt9p017_regs.conf_array[qs_mt9p017_ctrl->prev_res].
-		conf[QS_MT9P017_LINE_LENGTH_PCK].wdata;
-	qs_mt9p017_ctrl->snap_frame_length_lines =
-		qs_mt9p017_regs.conf_array[qs_mt9p017_ctrl->pict_res].
-		conf[QS_MT9P017_FRAME_LENGTH_LINES].wdata;
-	qs_mt9p017_ctrl->snap_line_length_pck =
-		qs_mt9p017_regs.conf_array[qs_mt9p017_ctrl->pict_res].
-		conf[QS_MT9P017_LINE_LENGTH_PCK].wdata;
-
-	if (mode == MODE_2D_LEFT)
-		qs_mt9p017_load_left_lsc();
-	else if (mode == MODE_2D_RIGHT)
-		qs_mt9p017_load_right_lsc();
-	else
-		qs_mt9p017_load_lsc();
-
-	rc = qs_mt9p017_sensor_setting(REG_INIT,
-		qs_mt9p017_ctrl->prev_res);
-	return rc;
-}
-
-static int32_t qs_mt9p017_set_sensor_mode(int mode, int res)
-{
-	int32_t rc = 0;
-
-	switch (mode) {
-	case SENSOR_PREVIEW_MODE:
-		qs_mt9p017_ctrl->prev_res = res;
-		rc = qs_mt9p017_video_config(mode);
-		break;
-	case SENSOR_SNAPSHOT_MODE:
-		qs_mt9p017_ctrl->pict_res = res;
-		rc = qs_mt9p017_snapshot_config(mode);
-		break;
-	case SENSOR_RAW_SNAPSHOT_MODE:
-		qs_mt9p017_ctrl->pict_res = res;
-		rc = qs_mt9p017_raw_snapshot_config(mode);
-		break;
-	default:
-		rc = -EINVAL;
-		break;
-	}
-	return rc;
-}
-
-static int32_t qs_mt9p017_check_id(void){
-	int rc;
-	uint16_t chipid = 0x0;
-
-	rc = qs_mt9p017_i2c_read(0x0000, &chipid, 2);
-	if (rc < 0)
-		return rc;
-
-	CDBG(KERN_ERR "qs_mt9p017 model_id = 0x%x\n", chipid);
-	if (chipid != 0x4800) {
-		rc = -ENODEV;
-		CDBG("qs_mt9p017 fail chip id doesnot match\n");
-	}
-	return rc;
-}
-
-static int32_t qs_mt9p017_power_up(const struct msm_camera_sensor_info *data)
-{
-	int32_t rc = 0;
-	rc = gpio_request(data->sensor_platform_info->sensor_reset,
-		"qs_mt9p017");
-	CDBG("%s\n", __func__);
-	if (!rc) {
-		CDBG("sensor_reset = %d\n", rc);
-		gpio_direction_output(data->sensor_platform_info->sensor_reset
-			, 0);
-		msleep(50);
-		gpio_set_value_cansleep(data->sensor_platform_info->
-			sensor_reset, 1);
-		msleep(20);
-	} else {
-		CDBG("sensor reset fail");
-	}
-	qs_mt9p017_bridge_reset();
-	qs_mt9p017_bridge_config(MODE_3D, RES_PREVIEW);
-	msleep(30);
-	return rc;
-}
-
-static int32_t qs_mt9p017_power_down(const struct msm_camera_sensor_info *data)
-{
-	gpio_set_value_cansleep(data->sensor_platform_info->sensor_reset, 0);
-	gpio_free(data->sensor_platform_info->sensor_reset);
-	return 0;
-}
-
-static int qs_mt9p017_sensor_open_init
-	(const struct msm_camera_sensor_info *data)
-{
-	int32_t rc = 0;
-	CDBG("%s: %d\n", __func__, __LINE__);
-	qs_mt9p017_ctrl->fps_divider = 1 * 0x00000400;
-	qs_mt9p017_ctrl->pict_fps_divider = 1 * 0x00000400;
-	qs_mt9p017_ctrl->cam_mode = MODE_INVALID;
-	qs_mt9p017_ctrl->fps = 30*Q8;
-
-	if (data)
-		qs_mt9p017_ctrl->sensordata = data;
-
-	msm_camio_clk_rate_set(QS_MT9P017_MASTER_CLK_RATE);
-	msleep(20);
-
-	rc = qs_mt9p017_power_up(data);
-	if (rc < 0) {
-		CDBG("Calling qs_mt9p017_sensor_open_init fail\n");
-		return rc;
-	}
-
-	qs_mt9p017_init_focus();
-	return rc;
-}
-
-static const struct i2c_device_id qs_mt9p017_i2c_id[] = {
-	{"qs_mt9p017", 0},
-	{ }
-};
-
-static int qs_mt9p017_i2c_probe(struct i2c_client *client,
-	const struct i2c_device_id *id)
-{
-	int rc = 0;
-	CDBG("qs_mt9p017_probe called!\n");
-
-	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
-		CDBG("i2c_check_functionality failed\n");
-		rc = -1;
-		goto probe_failure;
-	}
-
-	qs_mt9p017_client = client;
-	CDBG("qs_mt9p017_probe successed! rc = %d\n", rc);
-	return rc;
-
-probe_failure:
-	CDBG("qs_mt9p017_probe failed! rc = %d\n", rc);
-	return rc;
-}
-
-static int __exit qs_mt9p017_i2c_remove(struct i2c_client *client)
-{
-	qs_mt9p017_client = NULL;
-	return 0;
-}
-
-static struct i2c_driver qs_mt9p017_i2c_driver = {
-	.id_table = qs_mt9p017_i2c_id,
-	.probe  = qs_mt9p017_i2c_probe,
-	.remove = __exit_p(qs_mt9p017_i2c_remove),
-	.driver = {
-		.name = "qs_mt9p017",
-	},
-};
-
-static int qs_mt9p017_3D_sensor_config(void __user *argp)
-{
-	struct sensor_large_data cdata;
-	int rc;
-	if (copy_from_user(&cdata,
-		(void *)argp,
-		sizeof(struct sensor_large_data)))
-		return -EFAULT;
-	mutex_lock(&qs_mt9p017_mut);
-	rc = qs_mt9p017_get_calibration_data
-		(&cdata.data.sensor_3d_cali_data);
-	if (copy_to_user((void *)argp,
-		&cdata,
-		sizeof(struct sensor_large_data)))
-		rc = -EFAULT;
-	mutex_unlock(&qs_mt9p017_mut);
-	return rc;
-}
-
-static int qs_mt9p017_2D_sensor_config(void __user *argp)
-{
-	struct sensor_cfg_data cdata;
-	long   rc = 0;
-	if (copy_from_user(&cdata,
-		(void *)argp,
-		sizeof(struct sensor_cfg_data)))
-		return -EFAULT;
-	mutex_lock(&qs_mt9p017_mut);
-	CDBG("qs_mt9p017_sensor_config: cfgtype = %d\n",
-	cdata.cfgtype);
-	switch (cdata.cfgtype) {
-	case CFG_GET_PICT_FPS:
-		qs_mt9p017_get_pict_fps(
-			cdata.cfg.gfps.prevfps,
-			&(cdata.cfg.gfps.pictfps));
-
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_GET_PREV_L_PF:
-		cdata.cfg.prevl_pf =
-			qs_mt9p017_ctrl->prev_frame_length_lines;
-
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_GET_PREV_P_PL:
-		cdata.cfg.prevp_pl =
-			qs_mt9p017_ctrl->prev_line_length_pck;
-
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_GET_PICT_L_PF:
-		cdata.cfg.pictl_pf =
-			qs_mt9p017_ctrl->snap_frame_length_lines;
-
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_GET_PICT_P_PL:
-		cdata.cfg.pictp_pl =
-			qs_mt9p017_ctrl->snap_line_length_pck;
-
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_GET_PICT_MAX_EXP_LC:
-		cdata.cfg.pict_max_exp_lc =
-			qs_mt9p017_ctrl->snap_frame_length_lines * 24;
-
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_SET_FPS:
-	case CFG_SET_PICT_FPS:
-		rc = qs_mt9p017_set_fps(&(cdata.cfg.fps));
-		break;
-
-	case CFG_SET_EXP_GAIN:
-		rc =
-			qs_mt9p017_write_exp_gain(
-				cdata.cfg.sensor_3d_exp);
-		break;
-
-	case CFG_SET_PICT_EXP_GAIN:
-		rc =
-			qs_mt9p017_set_pict_exp_gain(
-			cdata.cfg.sensor_3d_exp);
-		break;
-
-	case CFG_SET_MODE:
-		rc = qs_mt9p017_set_sensor_mode(cdata.mode,
-				cdata.rs);
-		break;
-
-	case CFG_PWR_DOWN:
-		rc = qs_mt9p017_power_down(qs_mt9p017_ctrl->sensordata);
-		break;
-
-	case CFG_MOVE_FOCUS:
-		rc =
-			qs_mt9p017_move_focus(
-			cdata.cfg.focus.dir,
-			cdata.cfg.focus.steps);
-		break;
-
-	case CFG_SET_DEFAULT_FOCUS:
-		rc =
-			qs_mt9p017_set_default_focus(
-			cdata.cfg.focus.steps);
-		break;
-
-	case CFG_GET_AF_MAX_STEPS:
-		cdata.max_steps = QS_MT9P017_TOTAL_STEPS_NEAR_TO_FAR;
-		if (copy_to_user((void *)argp,
-			&cdata,
-			sizeof(struct sensor_cfg_data)))
-			rc = -EFAULT;
-		break;
-
-	case CFG_SET_EFFECT:
-		rc = qs_mt9p017_set_default_focus(
-			cdata.cfg.effect);
-		break;
-
-	case CFG_SENSOR_INIT:
-		rc = qs_mt9p017_mode_init(cdata.mode,
-				cdata.cfg.init_info);
-		break;
-
-	default:
-		rc = -EFAULT;
-		break;
-	}
-
-	mutex_unlock(&qs_mt9p017_mut);
-
-	return rc;
-}
-
-static int qs_mt9p017_sensor_config(void __user *argp)
-{
-	int cfgtype;
-	if (copy_from_user(&cfgtype,
-		(void *)argp,
-		sizeof(int)))
-		return -EFAULT;
-	if (cfgtype != CFG_GET_3D_CALI_DATA)
-		qs_mt9p017_2D_sensor_config(argp);
-	else
-		qs_mt9p017_3D_sensor_config(argp);
-	return 0;
-}
-
-static int qs_mt9p017_sensor_release(void)
-{
-	int rc = -EBADF;
-	mutex_lock(&qs_mt9p017_mut);
-	qs_mt9p017_power_down(qs_mt9p017_ctrl->sensordata);
-	mutex_unlock(&qs_mt9p017_mut);
-	return rc;
-}
-
-static int qs_mt9p017_sensor_probe(const struct msm_camera_sensor_info *info,
-		struct msm_sensor_ctrl *s)
-{
-	int rc = 0;
-	rc = i2c_add_driver(&qs_mt9p017_i2c_driver);
-	if (rc < 0 || qs_mt9p017_client == NULL) {
-		rc = -ENOTSUPP;
-		CDBG("I2C add driver failed");
-		goto i2c_probe_fail;
-	}
-	msm_camio_clk_rate_set(QS_MT9P017_MASTER_CLK_RATE);
-	rc = qs_mt9p017_power_up(info);
-	if (rc < 0)
-		goto gpio_request_fail;
-
-	rc = qs_mt9p017_check_id();
-	if (rc < 0) {
-		qs_mt9p017_power_down(info);
-		goto i2c_probe_fail;
-	}
-	s->s_init = qs_mt9p017_sensor_open_init;
-	s->s_release = qs_mt9p017_sensor_release;
-	s->s_config  = qs_mt9p017_sensor_config;
-	s->s_mount_angle = 270;
-	s->s_camera_type = info->camera_type;
-	qs_mt9p017_power_down(info);
-	return rc;
-
-gpio_request_fail:
-	pr_err("%s: gpio request fail\n", __func__);
-i2c_probe_fail:
-	CDBG("qs_mt9p017_sensor_probe: probe failed!\n");
-	i2c_del_driver(&qs_mt9p017_i2c_driver);
-	return rc;
-}
-
-static struct qs_mt9p017_format qs_mt9p017_subdev_info[] = {
-	{
-		.code   = V4L2_MBUS_FMT_YUYV8_2X8,
-		.colorspace = V4L2_COLORSPACE_JPEG,
-		.fmt    = 1,
-		.order    = 0,
-	},
-};
-
-static int qs_mt9p017_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
-			   enum v4l2_mbus_pixelcode *code)
-{
-	CDBG(KERN_DEBUG "Index is %d\n", index);
-	if (index >= ARRAY_SIZE(qs_mt9p017_subdev_info))
-		return -EINVAL;
-
-	*code = qs_mt9p017_subdev_info[index].code;
-	return 0;
-}
-
-static struct v4l2_subdev_core_ops qs_mt9p017_subdev_core_ops;
-static struct v4l2_subdev_video_ops qs_mt9p017_subdev_video_ops = {
-	.enum_mbus_fmt = qs_mt9p017_enum_fmt,
-};
-
-static struct v4l2_subdev_ops qs_mt9p017_subdev_ops = {
-	.core = &qs_mt9p017_subdev_core_ops,
-	.video  = &qs_mt9p017_subdev_video_ops,
-};
-
-
-static int qs_mt9p017_sensor_probe_cb(const struct msm_camera_sensor_info *info,
-	struct v4l2_subdev *sdev, struct msm_sensor_ctrl *s)
-{
-	int rc = 0;
-	qs_mt9p017_ctrl = kzalloc(sizeof(struct qs_mt9p017_ctrl_t), GFP_KERNEL);
-	if (!qs_mt9p017_ctrl) {
-		CDBG("qs_mt9p017_sensor_probe failed!\n");
-		return -ENOMEM;
-	}
-
-	rc = qs_mt9p017_sensor_probe(info, s);
-	if (rc < 0) {
-		kfree(qs_mt9p017_ctrl);
-		return rc;
-	}
-
-	/* probe is successful, init a v4l2 subdevice */
-	CDBG(KERN_DEBUG "going into v4l2_i2c_subdev_init\n");
-	if (sdev) {
-		v4l2_i2c_subdev_init(sdev, qs_mt9p017_client,
-						&qs_mt9p017_subdev_ops);
-		qs_mt9p017_ctrl->sensor_dev = sdev;
-	}
-	return rc;
-}
-
-static int __qs_mt9p017_probe(struct platform_device *pdev)
-{
-	return msm_sensor_register(pdev, qs_mt9p017_sensor_probe_cb);
-}
-
-static struct platform_driver msm_camera_driver = {
-	.probe = __qs_mt9p017_probe,
-	.driver = {
-		.name = "msm_camera_qs_mt9p017",
-		.owner = THIS_MODULE,
-	},
-};
-
-static int __init qs_mt9p017_init(void)
-{
-	return platform_driver_register(&msm_camera_driver);
-}
-
-static void __exit qs_mt9p017_exit(void)
-{
-	platform_driver_unregister(&msm_camera_driver);
-}
-module_init(qs_mt9p017_init);
-module_exit(qs_mt9p017_exit);
-MODULE_DESCRIPTION("Aptina 8 MP Bayer sensor driver");
-MODULE_LICENSE("GPL v2");
-
diff --git a/drivers/media/video/msm/qs_mt9p017.h b/drivers/media/video/msm/qs_mt9p017.h
deleted file mode 100644
index 8ac1cc1..0000000
--- a/drivers/media/video/msm/qs_mt9p017.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef QS_MT9P017_H
-#define QS_MT9P017_H
-#include <linux/types.h>
-#include <linux/kernel.h>
-extern struct qs_mt9p017_reg qs_mt9p017_regs;
-
-struct qs_mt9p017_i2c_reg_conf {
-	unsigned short waddr;
-	unsigned short wdata;
-};
-
-struct qs_mt9p017_i2c_conf_array {
-	struct qs_mt9p017_i2c_reg_conf *conf;
-	unsigned short size;
-};
-
-struct qs_mt9p017_i2c_read_t {
-	unsigned short raddr;
-	unsigned short *rdata;
-	int rlen;
-};
-
-struct qs_mt9p017_i2c_read_seq_t {
-	unsigned short raddr;
-	unsigned char *rdata;
-	int rlen;
-};
-
-enum qs_mt9p017_test_mode_t {
-	TEST_OFF,
-	TEST_1,
-	TEST_2,
-	TEST_3
-};
-
-enum qs_mt9p017_resolution_t {
-	QTR_2D_SIZE,
-	FULL_2D_SIZE,
-	QTR_3D_SIZE,
-	FULL_3D_SIZE,
-	INVALID_SIZE
-};
-enum qs_mt9p017_setting {
-	RES_PREVIEW,
-	RES_CAPTURE,
-	RES_3D_PREVIEW,
-	RES_3D_CAPTURE
-};
-enum qs_mt9p017_cam_mode_t {
-	MODE_2D_RIGHT,
-	MODE_2D_LEFT,
-	MODE_3D,
-	MODE_INVALID
-};
-enum qs_mt9p017_reg_update {
-	/* Sensor egisters that need to be updated during initialization */
-	REG_INIT,
-	/* Sensor egisters that needs periodic I2C writes */
-	UPDATE_PERIODIC,
-	/* All the sensor Registers will be updated */
-	UPDATE_ALL,
-	/* Not valid update */
-	UPDATE_INVALID
-};
-
-enum qs_mt9p017_reg_mode {
-	QS_MT9P017_LINE_LENGTH_PCK = 7,
-	QS_MT9P017_FRAME_LENGTH_LINES,
-};
-
-struct qs_mt9p017_reg {
-	const struct qs_mt9p017_i2c_reg_conf *rec_settings;
-	const unsigned short rec_size;
-	const struct qs_mt9p017_i2c_reg_conf *reg_pll;
-	const unsigned short reg_pll_size;
-	const struct qs_mt9p017_i2c_reg_conf *reg_3d_pll;
-	const unsigned short reg_3d_pll_size;
-	const struct qs_mt9p017_i2c_reg_conf *reg_lens;
-	const unsigned short reg_lens_size;
-	const struct qs_mt9p017_i2c_conf_array *conf_array;
-};
-#endif /* QS_MT9P017_H */
diff --git a/drivers/media/video/msm/qs_mt9p017_reg.c b/drivers/media/video/msm/qs_mt9p017_reg.c
deleted file mode 100644
index 04715a2..0000000
--- a/drivers/media/video/msm/qs_mt9p017_reg.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "qs_mt9p017.h"
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_pll_settings[] = {
-	{0x301A, 0x0018},/*reset_register*/
-	{0x3064, 0x7800},/*smia_test_2lane_mipi*/
-	{0x31AE, 0x0202},/*dual_lane_MIPI_interface*/
-	{0x0300, 0x0005},/*vt_pix_clk_div*/
-	{0x0302, 0x0001},/*vt_sys_clk_div*/
-	{0x0304, 0x0002},/*pre_pll_clk_div*/
-	{0x0306, 0x002C},/*pll_multipler*/
-	{0x0308, 0x000A},/*op_pix_clk_div*/
-	{0x030A, 0x0001} /*op_sys_clk_div*/
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_3d_pll_settings[] = {
-	{0x301A, 0x0018},/*reset_register*/
-	{0x3064, 0x7800},/*smia_test_2lane_mipi*/
-	{0x31AE, 0x0202},/*dual_lane_MIPI_interface*/
-	{0x0300, 0x0005},/*vt_pix_clk_div*/
-	{0x0302, 0x0001},/*vt_sys_clk_div*/
-	{0x0304, 0x0002},/*pre_pll_clk_div*/
-	{0x0306, 0x0018},/*pll_multipler*/
-	{0x0308, 0x000A},/*op_pix_clk_div*/
-	{0x030A, 0x0001},/*op_sys_clk_div*/
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_recommend_settings[] = {
-	{0x316A, 0x8200},
-	{0x3ED2, 0xD965},
-	{0x3ED8, 0x7F1B},
-	{0x3EDA, 0xAF11},
-	{0x3EDE, 0xCA00},
-	{0x3EE2, 0x0068},
-	{0x3EF2, 0xD965},
-	{0x3EF8, 0x797F},
-	{0x3EFC, 0xAFEF},
-	{0x3EFE, 0x1308},
-	{0x31E0, 0x1F01},
-	{0x3e00, 0x0429},/*[REV3_pixel_timing]*/
-	{0x3e02, 0xFFFF},
-	{0x3e04, 0xFFFF},
-	{0x3e06, 0xFFFF},
-	{0x3e08, 0x8080},
-	{0x3e0a, 0x7180},
-	{0x3e0c, 0x7200},
-	{0x3e0e, 0x4353},
-	{0x3e10, 0x1300},
-	{0x3e12, 0x8710},
-	{0x3e14, 0x6085},
-	{0x3e16, 0x40A2},
-	{0x3e18, 0x0018},
-	{0x3e1a, 0x9057},
-	{0x3e1c, 0xA049},
-	{0x3e1e, 0xA649},
-	{0x3e20, 0x8846},
-	{0x3e22, 0x8142},
-	{0x3e24, 0x0082},
-	{0x3e26, 0x8B49},
-	{0x3e28, 0x9C49},
-	{0x3e2a, 0x8E47},
-	{0x3e2c, 0x884D},
-	{0x3e2e, 0x8010},
-	{0x3e30, 0x0C04},
-	{0x3e32, 0x0691},
-	{0x3e34, 0x100C},
-	{0x3e36, 0x8C4D},
-	{0x3e38, 0xB94A},
-	{0x3e3a, 0x4283},
-	{0x3e3c, 0x4181},
-	{0x3e3e, 0x4BB2},
-	{0x3e40, 0x4B80},
-	{0x3e42, 0x5680},
-	{0x3e44, 0x001C},
-	{0x3e46, 0x8110},
-	{0x3e48, 0xE080},
-	{0x3e4a, 0x1300},
-	{0x3e4c, 0x1C00},
-	{0x3e4e, 0x827C},
-	{0x3e50, 0x0970},
-	{0x3e52, 0x8082},
-	{0x3e54, 0x7281},
-	{0x3e56, 0x4C40},
-	{0x3e58, 0x8E4D},
-	{0x3e5a, 0x8110},
-	{0x3e5c, 0x0CAF},
-	{0x3e5e, 0x4D80},
-	{0x3e60, 0x100C},
-	{0x3e62, 0x8440},
-	{0x3e64, 0x4C81},
-	{0x3e66, 0x7C53},
-	{0x3e68, 0x7000},
-	{0x3e6a, 0x0000},
-	{0x3e6c, 0x0000},
-	{0x3e6e, 0x0000},
-	{0x3e70, 0x0000},
-	{0x3e72, 0x0000},
-	{0x3e74, 0x0000},
-	{0x3e76, 0x0000},
-	{0x3e78, 0x7000},
-	{0x3e7a, 0x0000},
-	{0x3e7c, 0x0000},
-	{0x3e7e, 0x0000},
-	{0x3e80, 0x0000},
-	{0x3e82, 0x0000},
-	{0x3e84, 0x0000},
-	{0x3e86, 0x0000},
-	{0x3e88, 0x0000},
-	{0x3e8a, 0x0000},
-	{0x3e8c, 0x0000},
-	{0x3e8e, 0x0000},
-	{0x3e90, 0x0000},
-	{0x3e92, 0x0000},
-	{0x3e94, 0x0000},
-	{0x3e96, 0x0000},
-	{0x3e98, 0x0000},
-	{0x3e9a, 0x0000},
-	{0x3e9c, 0x0000},
-	{0x3e9e, 0x0000},
-	{0x3ea0, 0x0000},
-	{0x3ea2, 0x0000},
-	{0x3ea4, 0x0000},
-	{0x3ea6, 0x0000},
-	{0x3ea8, 0x0000},
-	{0x3eaa, 0x0000},
-	{0x3eac, 0x0000},
-	{0x3eae, 0x0000},
-	{0x3eb0, 0x0000},
-	{0x3eb2, 0x0000},
-	{0x3eb4, 0x0000},
-	{0x3eb6, 0x0000},
-	{0x3eb8, 0x0000},
-	{0x3eba, 0x0000},
-	{0x3ebc, 0x0000},
-	{0x3ebe, 0x0000},
-	{0x3ec0, 0x0000},
-	{0x3ec2, 0x0000},
-	{0x3ec4, 0x0000},
-	{0x3ec6, 0x0000},
-	{0x3ec8, 0x0000},
-	{0x3eca, 0x0000},
-	{0x3ec0, 0x0000},
-	{0x3ec2, 0x0000},
-	{0x3ec4, 0x0000},
-	{0x3ec6, 0x0000},
-	{0x3ec8, 0x0000},
-	{0x3eca, 0x0000}
-
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_prev_settings[] = {
-	{0x3004, 0x0008},/*x_addr_start*/
-	{0x3008, 0x0A25},/*x_addr_end*/
-	{0x3002, 0x0008},/*y_start_addr*/
-	{0x3006, 0x079D},/*y_addr_end*/
-	{0x3040, 0x04C3},/*read_mode*/
-	{0x034C, 0x0510},/*x_output_size*/
-	{0x034E, 0x03CC},/*y_output_size*/
-	{0x300C, 0x0D66},/*line_length_pck*/
-	{0x300A, 0x0415},/*frame_length_lines*/
-	{0x3012, 0x0414},/*coarse_integration_time*/
-	{0x3014, 0x0A22},/*fine_integration_time*/
-	{0x3010, 0x0184} /*fine_correction*/
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_snap_settings[] = {
-	{0x3004, 0x0000},/*x_addr_start*/
-	{0x3008, 0x0A2F},/*x_addr_end*/
-	{0x3002, 0x0000},/*y_start_addr*/
-	{0x3006, 0x07A7},/*y_addr_end*/
-	{0x3040, 0x0041},/*read_mode*/
-	{0x034C, 0x0A30},/*x_output_size*/
-	{0x034E, 0x07A8},/*y_output_size*/
-	{0x300C, 0x0E7E},/*line_length_pck*/
-	{0x300A, 0x07F5},/*frame_length_lines*/
-	{0x3012, 0x07F4},/*coarse_integration_time*/
-	{0x3014, 0x0C9C},/*fine_integration_time*/
-	{0x3010, 0x00A0},/*fine_correction*/
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_3d_prev_settings[] = {
-	{0x3004, 0x0008},/*x_addr_start*/
-	{0x3008, 0x0785},/*x_addr_end*/
-	{0x3002, 0x0008},/*y_start_addr*/
-	{0x3006, 0x043F},/*y_addr_end*/
-	{0x3040, 0x00C1},/*read_mode*/
-	{0x034C, 0x03C0},/*x_output_size*/
-	{0x034E, 0x0438},/*y_output_size*/
-	{0x300C, 0x0BCE},/*line_length_pck*/
-	{0x300A, 0x04A6},/*frame_length_lines*/
-	{0x3012, 0x04A5},/*coarse_integration_time*/
-	{0x3014, 0x062C},/*fine_integration_time*/
-	{0x3010, 0x00A0} /*fine_correction*/
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_3d_snap_settings[] = {
-	{0x3004, 0x0008},/*x_addr_start*/
-	{0x3008, 0x0787},/*x_addr_end*/
-	{0x3002, 0x0008},/*y_start_addr*/
-	{0x3006, 0x043F},/*y_addr_end*/
-	{0x3040, 0x0041},/*read_mode*/
-	{0x034C, 0x0780},/*x_output_size*/
-	{0x034E, 0x0438},/*y_output_size*/
-	{0x300C, 0x0BCE},/*line_length_pck*/
-	{0x300A, 0x04A6},/*frame_length_lines*/
-	{0x3012, 0x04A5},/*coarse_integration_time*/
-	{0x3014, 0x09EC},/*fine_integration_time*/
-	{0x3010, 0x00A0} /*fine_correction*/
-};
-
-struct qs_mt9p017_i2c_reg_conf qs_mt9p017_lens_settings[] = {
-	{0x3600, 0x0650},
-	{0x3602, 0x564D},
-	{0x3604, 0x6730},
-	{0x3606, 0x49CC},
-	{0x3608, 0xC790},
-	{0x360A, 0x0350},
-	{0x360C, 0xF7ED},
-	{0x360E, 0x5970},
-	{0x3610, 0x378F},
-	{0x3612, 0xDCD0},
-	{0x3614, 0x0290},
-	{0x3616, 0x4C2D},
-	{0x3618, 0x35AF},
-	{0x361A, 0xA5ED},
-	{0x361C, 0xC1CE},
-	{0x361E, 0x0310},
-	{0x3620, 0x83EE},
-	{0x3622, 0x79B0},
-	{0x3624, 0x0F2F},
-	{0x3626, 0xEEF0},
-	{0x3640, 0x86AD},
-	{0x3642, 0xAE8D},
-	{0x3644, 0x9D4E},
-	{0x3646, 0x782B},
-	{0x3648, 0x216F},
-	{0x364A, 0xAC6C},
-	{0x364C, 0x33CD},
-	{0x364E, 0x922C},
-	{0x3650, 0xA12D},
-	{0x3652, 0x3DCB},
-	{0x3654, 0x506C},
-	{0x3656, 0x306D},
-	{0x3658, 0x934B},
-	{0x365A, 0xC5CD},
-	{0x365C, 0x6568},
-	{0x365E, 0x0CEC},
-	{0x3660, 0xEE8D},
-	{0x3662, 0x0A8E},
-	{0x3664, 0x104E},
-	{0x3666, 0xECCE},
-	{0x3680, 0x0FF1},
-	{0x3682, 0x1B8F},
-	{0x3684, 0x92D3},
-	{0x3686, 0x8910},
-	{0x3688, 0x1FF4},
-	{0x368A, 0x1BD1},
-	{0x368C, 0x5A0D},
-	{0x368E, 0x89B3},
-	{0x3690, 0xFF10},
-	{0x3692, 0x1994},
-	{0x3694, 0x2DD0},
-	{0x3696, 0x796C},
-	{0x3698, 0xC912},
-	{0x369A, 0x194F},
-	{0x369C, 0x7633},
-	{0x369E, 0x06B1},
-	{0x36A0, 0x018E},
-	{0x36A2, 0x8F13},
-	{0x36A4, 0xF110},
-	{0x36A6, 0x2014},
-	{0x36C0, 0xA089},
-	{0x36C2, 0x44AD},
-	{0x36C4, 0x3C4B},
-	{0x36C6, 0x658C},
-	{0x36C8, 0xDF10},
-	{0x36CA, 0x2D2E},
-	{0x36CC, 0xAC8A},
-	{0x36CE, 0xD450},
-	{0x36D0, 0x742E},
-	{0x36D2, 0x4E4F},
-	{0x36D4, 0xE86D},
-	{0x36D6, 0xE1AD},
-	{0x36D8, 0x6CAF},
-	{0x36DA, 0x2D8F},
-	{0x36DC, 0x9B71},
-	{0x36DE, 0x9C8D},
-	{0x36E0, 0x55CE},
-	{0x36E2, 0xC28F},
-	{0x36E4, 0xED4F},
-	{0x36E6, 0x23F0},
-	{0x3700, 0xECF1},
-	{0x3702, 0x9130},
-	{0x3704, 0x31F4},
-	{0x3706, 0xED2F},
-	{0x3708, 0xB8B4},
-	{0x370A, 0xE4D1},
-	{0x370C, 0x220B},
-	{0x370E, 0x2394},
-	{0x3710, 0xEED1},
-	{0x3712, 0xD4B3},
-	{0x3714, 0x9431},
-	{0x3716, 0x428E},
-	{0x3718, 0x1894},
-	{0x371A, 0xBCF2},
-	{0x371C, 0x9C94},
-	{0x371E, 0xD271},
-	{0x3720, 0xE56B},
-	{0x3722, 0x1E54},
-	{0x3724, 0xEA10},
-	{0x3726, 0x8EF4},
-	{0x3782, 0x04A4},
-	{0x3784, 0x03B4},
-	{0x37C0, 0x0000},
-	{0x37C2, 0x0000},
-	{0x37C4, 0x0000},
-	{0x37C6, 0x0000},
-	{0x3780, 0x8000}
-};
-
-struct qs_mt9p017_i2c_conf_array qs_mt9p017_confs[] = {
-	{&qs_mt9p017_prev_settings[0], ARRAY_SIZE(qs_mt9p017_prev_settings)},
-	{&qs_mt9p017_snap_settings[0], ARRAY_SIZE(qs_mt9p017_snap_settings)},
-	{&qs_mt9p017_3d_prev_settings[0],
-		ARRAY_SIZE(qs_mt9p017_3d_prev_settings)},
-	{&qs_mt9p017_3d_snap_settings[0],
-		ARRAY_SIZE(qs_mt9p017_3d_snap_settings)},
-};
-
-struct qs_mt9p017_reg qs_mt9p017_regs = {
-	.rec_settings = &qs_mt9p017_recommend_settings[0],
-	.rec_size = ARRAY_SIZE(qs_mt9p017_recommend_settings),
-	.reg_pll = &qs_mt9p017_pll_settings[0],
-	.reg_pll_size = ARRAY_SIZE(qs_mt9p017_pll_settings),
-	.reg_3d_pll = &qs_mt9p017_3d_pll_settings[0],
-	.reg_3d_pll_size = ARRAY_SIZE(qs_mt9p017_3d_pll_settings),
-	.reg_lens = &qs_mt9p017_lens_settings[0],
-	.reg_lens_size = ARRAY_SIZE(qs_mt9p017_lens_settings),
-	.conf_array = &qs_mt9p017_confs[0],
-};
diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
index d9411ed..a4edb24 100644
--- a/drivers/mmc/core/core.h
+++ b/drivers/mmc/core/core.h
@@ -49,6 +49,8 @@
 	if (ms < 1000 / HZ) {
 		cond_resched();
 		mdelay(ms);
+	} else if (ms < jiffies_to_msecs(2)) {
+		usleep_range(ms * 1000, (ms + 1) * 1000);
 	} else {
 		msleep(ms);
 	}
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 1ce089d..4c6c8b8 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -19,6 +19,7 @@
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
+#include <linux/of.h>
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -966,6 +967,9 @@
 	void __iomem *base = host->base;
 	unsigned int pio_irqmask = 0;
 
+	BUG_ON(!data->sg);
+	BUG_ON(!data->sg_len);
+
 	host->curr.data = data;
 	host->curr.xfer_size = data->blksz * data->blocks;
 	host->curr.xfer_remain = host->curr.xfer_size;
@@ -3505,10 +3509,112 @@
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
+static struct mmc_platform_data *msmsdcc_populate_pdata(struct device *dev)
+{
+	int i, ret;
+	struct mmc_platform_data *pdata;
+	struct device_node *np = dev->of_node;
+	u32 bus_width = 0;
+	u32 *clk_table;
+	int clk_table_len;
+	u32 *sup_voltages;
+	int sup_volt_len;
+
+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata) {
+		dev_err(dev, "could not allocate memory for platform data\n");
+		goto err;
+	}
+
+	of_property_read_u32(np, "qcom,sdcc-bus-width", &bus_width);
+	if (bus_width == 8) {
+		pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA;
+	} else if (bus_width == 4) {
+		pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA;
+	} else {
+		dev_notice(dev, "Invalid bus width, default to 1 bit mode\n");
+		pdata->mmc_bus_width = 0;
+	}
+
+	if (of_get_property(np, "qcom,sdcc-sup-voltages", &sup_volt_len)) {
+		size_t sz;
+		sz = sup_volt_len / sizeof(*sup_voltages);
+		if (sz > 0) {
+			sup_voltages = devm_kzalloc(dev,
+					sz * sizeof(*sup_voltages), GFP_KERNEL);
+			if (!sup_voltages) {
+				dev_err(dev, "No memory for supported voltage\n");
+				goto err;
+			}
+
+			ret = of_property_read_u32_array(np,
+				"qcom,sdcc-sup-voltages", sup_voltages, sz);
+			if (ret < 0) {
+				dev_err(dev, "error while reading voltage"
+						"ranges %d\n", ret);
+				goto err;
+			}
+		} else {
+			dev_err(dev, "No supported voltages\n");
+			goto err;
+		}
+		for (i = 0; i < sz; i += 2) {
+			u32 mask;
+
+			mask = mmc_vddrange_to_ocrmask(sup_voltages[i],
+					sup_voltages[i + 1]);
+			if (!mask)
+				dev_err(dev, "Invalide voltage range %d\n", i);
+			pdata->ocr_mask |= mask;
+		}
+		dev_dbg(dev, "OCR mask=0x%x\n", pdata->ocr_mask);
+	} else {
+		dev_err(dev, "Supported voltage range not specified\n");
+	}
+
+	if (of_get_property(np, "qcom,sdcc-clk-rates", &clk_table_len)) {
+		size_t sz;
+		sz = clk_table_len / sizeof(*clk_table);
+
+		if (sz > 0) {
+			clk_table = devm_kzalloc(dev, sz * sizeof(*clk_table),
+					GFP_KERNEL);
+			if (!clk_table) {
+				dev_err(dev, "No memory for clock table\n");
+				goto err;
+			}
+
+			ret = of_property_read_u32_array(np,
+				"qcom,sdcc-clk-rates", clk_table, sz);
+			if (ret < 0) {
+				dev_err(dev, "error while reading clk"
+						"table %d\n", ret);
+				goto err;
+			}
+		} else {
+			dev_err(dev, "clk_table not specified\n");
+			goto err;
+		}
+		pdata->sup_clk_table = clk_table;
+		pdata->sup_clk_cnt = sz;
+	} else {
+		dev_err(dev, "Supported clock rates not specified\n");
+	}
+
+	if (of_get_property(np, "qcom,sdcc-nonremovable", NULL))
+		pdata->nonremovable = true;
+	if (of_get_property(np, "qcom,sdcc-disable_cmd23", NULL))
+		pdata->disable_cmd23 = true;
+
+	return pdata;
+err:
+	return NULL;
+}
+
 static int
 msmsdcc_probe(struct platform_device *pdev)
 {
-	struct mmc_platform_data *plat = pdev->dev.platform_data;
+	struct mmc_platform_data *plat;
 	struct msmsdcc_host *host;
 	struct mmc_host *mmc;
 	unsigned long flags;
@@ -3522,6 +3628,14 @@
 	int ret = 0;
 	int i;
 
+	if (pdev->dev.of_node) {
+		plat = msmsdcc_populate_pdata(&pdev->dev);
+		of_property_read_u32((&pdev->dev)->of_node,
+				"cell-index", &pdev->id);
+	} else {
+		plat = pdev->dev.platform_data;
+	}
+
 	/* must have platform data */
 	if (!plat) {
 		pr_err("%s: Platform data not available\n", __func__);
@@ -3541,35 +3655,54 @@
 		pr_err("%s: Invalid resource\n", __func__);
 		return -ENXIO;
 	}
+	if (pdev->dev.of_node) {
+		/*
+		 * Device tree iomem resources are only accessible by index.
+		 * index = 0 -> SDCC register interface
+		 * index = 1 -> DML register interface
+		 * index = 2 -> BAM register interface
+		 * IRQ resources:
+		 * index = 0 -> SDCC IRQ
+		 * index = 1 -> BAM IRQ
+		 */
+		core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		dml_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		bam_memres = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+		core_irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+		bam_irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	} else {
+		for (i = 0; i < pdev->num_resources; i++) {
+			if (pdev->resource[i].flags & IORESOURCE_MEM) {
+				if (!strncmp(pdev->resource[i].name,
+						"sdcc_dml_addr",
+						sizeof("sdcc_dml_addr")))
+					dml_memres = &pdev->resource[i];
+				else if (!strncmp(pdev->resource[i].name,
+						"sdcc_bam_addr",
+						sizeof("sdcc_bam_addr")))
+					bam_memres = &pdev->resource[i];
+				else
+					core_memres = &pdev->resource[i];
 
-	for (i = 0; i < pdev->num_resources; i++) {
-		if (pdev->resource[i].flags & IORESOURCE_MEM) {
-			if (!strcmp(pdev->resource[i].name,
-					"sdcc_dml_addr"))
-				dml_memres = &pdev->resource[i];
-			else if (!strcmp(pdev->resource[i].name,
-					"sdcc_bam_addr"))
-				bam_memres = &pdev->resource[i];
-			else
-				core_memres = &pdev->resource[i];
-
-		}
-		if (pdev->resource[i].flags & IORESOURCE_IRQ) {
-			if (!strcmp(pdev->resource[i].name,
-					"sdcc_bam_irq"))
-				bam_irqres = &pdev->resource[i];
-			else
-				core_irqres = &pdev->resource[i];
-		}
-		if (pdev->resource[i].flags & IORESOURCE_DMA) {
-			if (!strncmp(pdev->resource[i].name,
-					"sdcc_dma_chnl",
-					sizeof("sdcc_dma_chnl")))
-				dmares = &pdev->resource[i];
-			else if (!strncmp(pdev->resource[i].name,
-					"sdcc_dma_crci",
-					sizeof("sdcc_dma_crci")))
-				dma_crci_res = &pdev->resource[i];
+			}
+			if (pdev->resource[i].flags & IORESOURCE_IRQ) {
+				if (!strncmp(pdev->resource[i].name,
+						"sdcc_bam_irq",
+						sizeof("sdcc_bam_irq")))
+					bam_irqres = &pdev->resource[i];
+				else
+					core_irqres = &pdev->resource[i];
+			}
+			if (pdev->resource[i].flags & IORESOURCE_DMA) {
+				if (!strncmp(pdev->resource[i].name,
+						"sdcc_dma_chnl",
+						sizeof("sdcc_dma_chnl")))
+					dmares = &pdev->resource[i];
+				else if (!strncmp(pdev->resource[i].name,
+						"sdcc_dma_crci",
+						sizeof("sdcc_dma_crci")))
+					dma_crci_res = &pdev->resource[i];
+			}
 		}
 	}
 
@@ -4378,12 +4511,19 @@
 	.resume		 = msmsdcc_pm_resume,
 };
 
+static const struct of_device_id msmsdcc_dt_match[] = {
+	{.compatible = "qcom,msm-sdcc"},
+
+};
+MODULE_DEVICE_TABLE(of, msmsdcc_dt_match);
+
 static struct platform_driver msmsdcc_driver = {
 	.probe		= msmsdcc_probe,
 	.remove		= msmsdcc_remove,
 	.driver		= {
 		.name	= "msm_sdcc",
 		.pm	= &msmsdcc_dev_pm_ops,
+		.of_match_table = msmsdcc_dt_match,
 	},
 };
 
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index cccb317..148a5e5 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -368,6 +368,19 @@
 				enable ? CHG_EN_BIT : 0);
 }
 
+#define CHG_FAILED_CLEAR	BIT(0)
+#define ATC_FAILED_CLEAR	BIT(1)
+static int pm_chg_failed_clear(struct pm8921_chg_chip *chip, int clear)
+{
+	int rc;
+
+	rc = pm_chg_masked_write(chip, CHG_CNTRL_3, ATC_FAILED_CLEAR,
+				clear ? ATC_FAILED_CLEAR : 0);
+	rc |= pm_chg_masked_write(chip, CHG_CNTRL_3, CHG_FAILED_CLEAR,
+				clear ? CHG_FAILED_CLEAR : 0);
+	return rc;
+}
+
 #define CHG_CHARGE_DIS_BIT	BIT(1)
 static int pm_chg_charge_dis(struct pm8921_chg_chip *chip, int disable)
 {
@@ -1525,8 +1538,17 @@
 static irqreturn_t chgfail_irq_handler(int irq, void *data)
 {
 	struct pm8921_chg_chip *chip = data;
+	int ret;
 
-	pr_debug("state_changed_to=%d\n", pm_chg_get_fsm_state(data));
+	ret = pm_chg_failed_clear(chip, 1);
+	if (ret)
+		pr_err("Failed to write CHG_FAILED_CLEAR bit\n");
+
+	pr_err("batt_present = %d, batt_temp_ok = %d, state_changed_to=%d\n",
+			get_prop_batt_present(chip),
+			pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ),
+			pm_chg_get_fsm_state(data));
+
 	power_supply_changed(&chip->batt_psy);
 	power_supply_changed(&chip->usb_psy);
 	power_supply_changed(&chip->dc_psy);
@@ -2047,6 +2069,7 @@
 	pm8921_chg_enable_irq(chip, USBIN_UV_IRQ);
 	pm8921_chg_enable_irq(chip, DCIN_OV_IRQ);
 	pm8921_chg_enable_irq(chip, DCIN_UV_IRQ);
+	pm8921_chg_enable_irq(chip, CHGFAIL_IRQ);
 	pm8921_chg_enable_irq(chip, FASTCHG_IRQ);
 	pm8921_chg_enable_irq(chip, VBATDET_LOW_IRQ);
 
diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile
index f5a7c9e..dc02da4 100644
--- a/drivers/video/msm/Makefile
+++ b/drivers/video/msm/Makefile
@@ -10,6 +10,7 @@
 
 ifeq ($(CONFIG_FB_MSM_MDP40),y)
 obj-y += mdp4_util.o
+obj-y += mdp4_hsic.o
 else
 obj-y += mdp_hw_init.o
 obj-y += mdp_ppp.o
diff --git a/drivers/video/msm/external_common.c b/drivers/video/msm/external_common.c
index 1d87de6..5d9795a 100644
--- a/drivers/video/msm/external_common.c
+++ b/drivers/video/msm/external_common.c
@@ -18,7 +18,6 @@
 /* #define DEBUG */
 #define DEV_DBG_PREFIX "EXT_COMMON: "
 
-/* #define CEC_COMPLIANCE_TESTING */
 #include "msm_fb.h"
 #include "hdmi_msm.h"
 #include "external_common.h"
@@ -370,7 +369,7 @@
 	struct device_attribute *attr, const char *buf, size_t count)
 {
 
-#ifdef CEC_COMPLIANCE_TESTING
+#ifdef DRVR_ONLY_CECT_NO_DAEMON
 	/*
 	 * Only for testing
 	 */
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index 4b34969..4ef0da6 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -16,7 +16,7 @@
 /* #define REG_DUMP */
 
 #define CEC_MSG_PRINT
-/* #define CEC_COMPLIANCE_TESTING */
+#define TOGGLE_CEC_HARDWARE_FSM
 
 #include <linux/types.h>
 #include <linux/bitops.h>
@@ -69,6 +69,11 @@
 
 #ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
 
+#ifdef TOGGLE_CEC_HARDWARE_FSM
+static boolean msg_send_complete = TRUE;
+static boolean msg_recv_complete = TRUE;
+#endif
+
 #define HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE	BIT(16)
 #define HDMI_MSM_CEC_REFTIMER_REFTIMER(___t)	(((___t)&0xFFFF) << 0)
 
@@ -97,10 +102,9 @@
 #define HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT		BIT(0)
 
 #define HDMI_MSM_CEC_FRAME_WR_SUCCESS(___st)         (((___st)&0xF) ==\
-		(HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT &&\
-			HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK &&\
-			(HDMI_MSM_CEC_INT_FRAME_ERROR_MASK &&\
-				!(HDMI_MSM_CEC_INT_FRAME_ERROR_INT))))
+		(HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT |\
+			HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK |\
+			HDMI_MSM_CEC_INT_FRAME_ERROR_MASK))
 
 #define HDMI_MSM_CEC_RETRANSMIT_NUM(___num)		(((___num)&0xF) << 4)
 #define HDMI_MSM_CEC_RETRANSMIT_ENABLE		BIT(0)
@@ -193,6 +197,10 @@
 
 	boolean frameType = (msg->recvr_id == 15 ? BIT(0) : 0);
 
+#ifdef TOGGLE_CEC_HARDWARE_FSM
+	msg_send_complete = FALSE;
+#endif
+
 	INIT_COMPLETION(hdmi_msm_state->cec_frame_wr_done);
 	hdmi_msm_state->cec_frame_wr_status = 0;
 
@@ -251,13 +259,23 @@
 			msg->frame_size);
 		hdmi_msm_dump_cec_msg(msg);
 	}
+
+#ifdef TOGGLE_CEC_HARDWARE_FSM
+	if (!msg_recv_complete) {
+		/* Toggle CEC hardware FSM */
+		HDMI_OUTP(0x028C, 0x0);
+		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+		msg_recv_complete = TRUE;
+	}
+	msg_send_complete = TRUE;
+#endif
 }
 
 void hdmi_msm_cec_msg_recv(void)
 {
 	uint32 data;
 	int i;
-#ifdef CEC_COMPLIANCE_TESTING
+#ifdef DRVR_ONLY_CECT_NO_DAEMON
 	struct hdmi_msm_cec_msg temp_msg;
 #endif
 	mutex_lock(&hdmi_msm_state_mutex);
@@ -265,7 +283,7 @@
 		&& hdmi_msm_state->cec_queue_full) {
 		mutex_unlock(&hdmi_msm_state_mutex);
 		DEV_ERR("CEC message queue is overflowing\n");
-#ifdef CEC_COMPLIANCE_TESTING
+#ifdef DRVR_ONLY_CECT_NO_DAEMON
 		/*
 		 * Without CEC daemon:
 		 * Compliance tests fail once the queue gets filled up.
@@ -325,7 +343,7 @@
 	hdmi_msm_dump_cec_msg(hdmi_msm_state->cec_queue_wr);
 	DEV_DBG("=======================================\n");
 
-#ifdef CEC_COMPLIANCE_TESTING
+#ifdef DRVR_ONLY_CECT_NO_DAEMON
 	switch (hdmi_msm_state->cec_queue_wr->opcode) {
 	case 0x64:
 		/* Set OSD String */
@@ -490,7 +508,7 @@
 #endif /* __SEND_ABORT__ */
 	}
 
-#endif /* CEC_COMPLIANCE_TESTING */
+#endif /* DRVR_ONLY_CECT_NO_DAEMON */
 	mutex_lock(&hdmi_msm_state_mutex);
 	hdmi_msm_state->cec_queue_wr++;
 	if (hdmi_msm_state->cec_queue_wr == CEC_QUEUE_END)
@@ -1099,9 +1117,11 @@
 	}
 	if ((cec_intr_status & (1 << 2)) && (cec_intr_status & (1 << 3))) {
 		DEV_DBG("CEC_IRQ_FRAME_ERROR\n");
+#ifdef TOGGLE_CEC_HARDWARE_FSM
 		/* Toggle CEC hardware FSM */
 		HDMI_OUTP(0x028C, 0x0);
 		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+#endif
 		HDMI_OUTP(0x029C, cec_intr_status);
 		mutex_lock(&hdmi_msm_state_mutex);
 		hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_ERROR;
@@ -1119,9 +1139,15 @@
 			HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK);
 		hdmi_msm_cec_msg_recv();
 
-		/* Toggle CEC hardware FSM */
-		HDMI_OUTP(0x028C, 0x0);
-		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+#ifdef TOGGLE_CEC_HARDWARE_FSM
+		if (!msg_send_complete)
+			msg_recv_complete = FALSE;
+		else {
+			/* Toggle CEC hardware FSM */
+			HDMI_OUTP(0x028C, 0x0);
+			HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+		}
+#endif
 
 		return IRQ_HANDLED;
 	}
@@ -3321,8 +3347,6 @@
 		MSM_HDMI_SAMPLE_RATE_48KHZ, channels);
 	hdmi_msm_audio_info_setup(TRUE, channels, 0, FALSE);
 
-	hdmi_msm_audio_ctrl_setup(FALSE, 1);
-
 	/* Turn on Audio FIFO and SAM DROP ISR */
 	HDMI_OUTP(0x02CC, HDMI_INP(0x02CC) | BIT(1) | BIT(3));
 	DEV_INFO("HDMI Audio: Enabled\n");
diff --git a/drivers/video/msm/lcdc.c b/drivers/video/msm/lcdc.c
index cf8a5ff..135bf68 100644
--- a/drivers/video/msm/lcdc.c
+++ b/drivers/video/msm/lcdc.c
@@ -29,7 +29,6 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
-#include <mach/clk.h>
 
 #include "msm_fb.h"
 
@@ -78,7 +77,7 @@
 #ifndef CONFIG_MSM_BUS_SCALING
 	if (mfd->ebi1_clk) {
 		if (mdp_rev == MDP_REV_303) {
-			if (clk_set_min_rate(mfd->ebi1_clk, 0))
+			if (clk_set_rate(mfd->ebi1_clk, 0))
 				pr_err("%s: ebi1_lcdc_clk set rate failed\n",
 					__func__);
 		}
@@ -117,7 +116,7 @@
 
 	if (mfd->ebi1_clk) {
 		if (mdp_rev == MDP_REV_303) {
-			if (clk_set_min_rate(mfd->ebi1_clk, 65000000))
+			if (clk_set_rate(mfd->ebi1_clk, 65000000))
 				pr_err("%s: ebi1_lcdc_clk set rate failed\n",
 					__func__);
 		} else {
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 0aeb91e..ad7fc04 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -138,11 +138,10 @@
 	OVERLAY_PIPE_MAX
 };
 
-/* 2 VG pipes can be shared by RGB and VIDEO */
-#define MDP4_MAX_PIPE (OVERLAY_PIPE_MAX + 2)
-
-#define OVERLAY_TYPE_RGB	0x01
-#define	OVERLAY_TYPE_VIDEO	0x02
+enum {
+	OVERLAY_TYPE_RGB,
+	OVERLAY_TYPE_VIDEO
+};
 
 enum {
 	MDP4_MIXER0,
@@ -150,8 +149,6 @@
 	MDP4_MIXER_MAX
 };
 
-#define MDP4_MAX_MIXER	2
-
 enum {
 	OVERLAY_PLANE_INTERLEAVED,
 	OVERLAY_PLANE_PLANAR,
@@ -222,6 +219,15 @@
 
 #define MDP4_MAX_PLANE		4
 
+struct mdp4_hsic_regs {
+	int32_t params[NUM_HSIC_PARAM];
+	int32_t conv_matrix[3][3];
+	int32_t	pre_limit[6];
+	int32_t post_limit[6];
+	int32_t pre_bias[3];
+	int32_t post_bias[3];
+	int32_t dirty;
+};
 
 struct mdp4_overlay_pipe {
 	uint32 pipe_used;
@@ -298,19 +304,11 @@
 	uint32 dmap_cnt;
 	uint32 blt_end;
 	uint32 luma_align_size;
+	struct mdp4_hsic_regs hsic_regs;
 	struct completion dmas_comp;
 	struct mdp_overlay req_data;
 };
 
-#define MDP4_MAX_SHARE	2
-
-struct mdp4_pipe_desc {
-	int share;
-	int ref_cnt;
-	int ndx_list[MDP4_MAX_SHARE];
-	struct mdp4_overlay_pipe *player;
-};
-
 struct mdp4_statistic {
 	ulong intr_tot;
 	ulong intr_dma_p;
@@ -331,7 +329,7 @@
 	ulong overlay_set[MDP4_MIXER_MAX];
 	ulong overlay_unset[MDP4_MIXER_MAX];
 	ulong overlay_play[MDP4_MIXER_MAX];
-	ulong pipe[MDP4_MAX_PIPE];
+	ulong pipe[OVERLAY_PIPE_MAX];
 	ulong dsi_clkoff;
 	ulong err_mixer;
 	ulong err_zorder;
@@ -430,8 +428,7 @@
 int mdp4_overlay_play_wait(struct fb_info *info,
 	struct msmfb_overlay_data *req);
 int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req);
-struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(int ptype, int mixer,
-				int req_share);
+struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(int ptype, int mixer);
 void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe);
 void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc);
 void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe);
@@ -637,4 +634,6 @@
 int mdp4_writeback_init(struct fb_info *info);
 int mdp4_writeback_terminate(struct fb_info *info);
 
+void mdp4_hsic_set(struct mdp4_overlay_pipe *pipe, struct dpp_ctrl *ctrl);
+void mdp4_hsic_update(struct mdp4_overlay_pipe *pipe);
 #endif /* MDP_H */
diff --git a/drivers/video/msm/mdp4_hsic.c b/drivers/video/msm/mdp4_hsic.c
new file mode 100644
index 0000000..5735f45
--- /dev/null
+++ b/drivers/video/msm/mdp4_hsic.c
@@ -0,0 +1,534 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/msm_mdp.h>
+#include "mdp.h"
+#include "mdp4.h"
+
+/* Definitions */
+#define MDP4_CSC_MV_OFF		0x4400
+#define MDP4_CSC_PRE_BV_OFF	0x4500
+#define MDP4_CSC_POST_BV_OFF	0x4580
+#define MDP4_CSC_PRE_LV_OFF	0x4600
+#define MDP4_CSC_POST_LV_OFF	0x4680
+#define MDP_VG1_BASE	(MDP_BASE + MDP4_VIDEO_BASE)
+
+#define MDP_VG1_CSC_MVn(n)	(MDP_VG1_BASE + MDP4_CSC_MV_OFF + 4 * (n))
+#define MDP_VG1_CSC_PRE_LVn(n)	(MDP_VG1_BASE + MDP4_CSC_PRE_LV_OFF + 4 * (n))
+#define MDP_VG1_CSC_POST_LVn(n)	(MDP_VG1_BASE + MDP4_CSC_POST_LV_OFF + 4 * (n))
+#define MDP_VG1_CSC_PRE_BVn(n)	(MDP_VG1_BASE + MDP4_CSC_PRE_BV_OFF + 4 * (n))
+#define MDP_VG1_CSC_POST_BVn(n)	(MDP_VG1_BASE + MDP4_CSC_POST_BV_OFF + 4 * (n))
+
+#define Q16	(16)
+#define Q16_ONE	(1 << Q16)
+
+#define Q16_VALUE(x)	((int32_t)((uint32_t)x << Q16))
+#define Q16_PERCENT_VALUE(x, n)	((int32_t)( \
+				div_s64(((int64_t)x * (int64_t)Q16_ONE), n)))
+
+#define Q16_WHOLE(x)	((int32_t)(x >> 16))
+#define Q16_FRAC(x)	((int32_t)(x & 0xFFFF))
+#define Q16_S1Q16_MUL(x, y)	(((x >> 1) * (y >> 1)) >> 14)
+
+#define Q16_MUL(x, y)	((int32_t)((((int64_t)x) * ((int64_t)y)) >> Q16))
+#define Q16_NEGATE(x)	(0 - (x))
+
+/*
+ * HSIC Control min/max values
+ *    These settings are based on the maximum/minimum allowed modifications to
+ *    HSIC controls for layer and display color.  Allowing too much variation in
+ *    the CSC block will result in color clipping resulting in unwanted color
+ *    shifts.
+ */
+#define TRIG_MAX	Q16_VALUE(128)
+#define CON_SAT_MAX	Q16_VALUE(128)
+#define INTENSITY_MAX	(Q16_VALUE(2047) >> 12)
+
+#define HUE_MAX	Q16_VALUE(100)
+#define HUE_MIN	Q16_VALUE(-100)
+#define HUE_DEF	Q16_VALUE(0)
+
+#define SAT_MAX	Q16_VALUE(100)
+#define SAT_MIN	Q16_VALUE(-100)
+#define SAT_DEF	CON_SAT_MAX
+
+#define CON_MAX	Q16_VALUE(100)
+#define CON_MIN	Q16_VALUE(-100)
+#define CON_DEF	CON_SAT_MAX
+
+#define INTEN_MAX	Q16_VALUE(100)
+#define INTEN_MIN	Q16_VALUE(-100)
+#define INTEN_DEF	Q16_VALUE(0)
+
+enum {
+	DIRTY,
+	GENERATED,
+	CLEAN
+};
+
+/* local vars*/
+static int32_t csc_matrix_tab[3][3] = {
+	{0x00012a00, 0x00000000, 0x00019880},
+	{0x00012a00, 0xffff9b80, 0xffff3000},
+	{0x00012a00, 0x00020480, 0x00000000}
+};
+
+static int32_t csc_yuv2rgb_conv_tab[3][3] = {
+	{0x00010000, 0x00000000, 0x000123cb},
+	{0x00010000, 0xffff9af9, 0xffff6b5e},
+	{0x00010000, 0x00020838, 0x00000000}
+};
+
+static int32_t csc_rgb2yuv_conv_tab[3][3] = {
+	{0x00004c8b, 0x00009645, 0x00001d2f},
+	{0xffffda56, 0xffffb60e, 0x00006f9d},
+	{0x00009d70, 0xffff7c2a, 0xffffe666}
+};
+
+static uint32_t csc_pre_bv_tab[3]  = {0xfffff800, 0xffffc000, 0xffffc000};
+static uint32_t csc_post_bv_tab[3] = {0x00000000, 0x00000000, 0x00000000};
+
+static uint32_t csc_pre_lv_tab[6] =  {0x00000000, 0x00007f80, 0x00000000,
+					0x00007f80, 0x00000000, 0x00007f80};
+static uint32_t csc_post_lv_tab[6] = {0x00000000, 0x00007f80, 0x00000000,
+					0x00007f80, 0x00000000, 0x00007f80};
+
+/* Lookup table for Sin/Cos lookup - Q16*/
+static const int32_t  trig_lut[65] = {
+	0x00000000, /* sin((2*M_PI/256) * 0x00);*/
+	0x00000648, /* sin((2*M_PI/256) * 0x01);*/
+	0x00000C90, /* sin((2*M_PI/256) * 0x02);*/
+	0x000012D5,
+	0x00001918,
+	0x00001F56,
+	0x00002590,
+	0x00002BC4,
+	0x000031F1,
+	0x00003817,
+	0x00003E34,
+	0x00004447,
+	0x00004A50,
+	0x0000504D,
+	0x0000563E,
+	0x00005C22,
+	0x000061F8,
+	0x000067BE,
+	0x00006D74,
+	0x0000731A,
+	0x000078AD,
+	0x00007E2F,
+	0x0000839C,
+	0x000088F6,
+	0x00008E3A,
+	0x00009368,
+	0x00009880,
+	0x00009D80,
+	0x0000A268,
+	0x0000A736,
+	0x0000ABEB,
+	0x0000B086,
+	0x0000B505,
+	0x0000B968,
+	0x0000BDAF,
+	0x0000C1D8,
+	0x0000C5E4,
+	0x0000C9D1,
+	0x0000CD9F,
+	0x0000D14D,
+	0x0000D4DB,
+	0x0000D848,
+	0x0000DB94,
+	0x0000DEBE,
+	0x0000E1C6,
+	0x0000E4AA,
+	0x0000E768,
+	0x0000EA0A,
+	0x0000EC83,
+	0x0000EED9,
+	0x0000F109,
+	0x0000F314,
+	0x0000F4FA,
+	0x0000F6BA,
+	0x0000F854,
+	0x0000F9C8,
+	0x0000FB15,
+	0x0000FC3B,
+	0x0000FD3B,
+	0x0000FE13,
+	0x0000FEC4,
+	0x0000FF4E,
+	0x0000FFB1,
+	0x0000FFEC,
+	0x00010000, /* sin((2*M_PI/256) * 0x40);*/
+};
+
+void trig_values_q16(int32_t deg, int32_t *cos, int32_t *sin)
+{
+	int32_t   angle;
+	int32_t   quad, anglei, anglef;
+	int32_t   v0 = 0, v1 = 0;
+	int32_t   t1, t2;
+
+	/*
+	 * Scale the angle so that 256 is one complete revolution and mask it
+	 * to this domain
+	 * NOTE: 0xB60B == 256/360
+	 */
+	angle = Q16_MUL(deg, 0xB60B) & 0x00FFFFFF;
+
+	/* Obtain a quadrant number, integer, and fractional part */
+	quad   =  angle >> 22;
+	anglei = (angle >> 16) & 0x3F;
+	anglef =  angle & 0xFFFF;
+
+	/*
+	 * Using the integer part, obtain the lookup table entry and its
+	 * complement. Using the quadrant, swap and negate these as
+	 * necessary.
+	 * (The values and all derivatives of sine and cosine functions
+	 * can be derived from these values)
+	 */
+	switch (quad) {
+	case 0x0:
+		v0 += trig_lut[anglei];
+		v1 += trig_lut[0x40-anglei];
+		break;
+
+	case 0x1:
+		v0 += trig_lut[0x40-anglei];
+		v1 -= trig_lut[anglei];
+		break;
+
+	case 0x2:
+		v0 -= trig_lut[anglei];
+		v1 -= trig_lut[0x40-anglei];
+		break;
+
+	case 0x3:
+		v0 -= trig_lut[0x40-anglei];
+		v1 += trig_lut[anglei];
+		break;
+	}
+
+	/*
+	 * Multiply the fractional part by 2*PI/256 to move it from lookup
+	 *  table units to radians, giving us the coefficient for first
+	 *  derivatives.
+	 */
+	t1 = Q16_S1Q16_MUL(anglef, 0x0648);
+
+	/*
+	 * Square this and divide by 2 to get the coefficient for second
+	 *   derivatives
+	 */
+	t2 = Q16_S1Q16_MUL(t1, t1) >> 1;
+
+	*sin = v0 + Q16_S1Q16_MUL(v1, t1) - Q16_S1Q16_MUL(v0, t2);
+
+	*cos = v1 - Q16_S1Q16_MUL(v0, t1) - Q16_S1Q16_MUL(v1, t2);
+}
+
+/* Convert input Q16 value to s4.9 */
+int16_t convert_q16_s49(int32_t q16Value)
+{	/* Top half is the whole number, Bottom half is fractional portion*/
+	int16_t whole = Q16_WHOLE(q16Value);
+	int32_t fraction  = Q16_FRAC(q16Value);
+
+	/* Clamp whole to 3 bits */
+	if (whole > 7)
+		whole = 7;
+	else if (whole < -7)
+		whole = -7;
+
+	/* Reduce fraction to 9 bits. */
+	fraction = (fraction<<9)>>Q16;
+
+	return (int16_t) ((int16_t)whole<<9) | ((int16_t)fraction);
+}
+
+/* Convert input Q16 value to uint16 */
+int16_t convert_q16_int16(int32_t val)
+{
+	int32_t rounded;
+
+	if (val >= 0) {
+		/* Add 0.5 */
+		rounded = val + (Q16_ONE>>1);
+	} else {
+		/* Subtract 0.5 */
+		rounded = val - (Q16_ONE>>1);
+	}
+
+	/* Truncate rounded value */
+	return (int16_t)(rounded>>Q16);
+}
+
+/*
+ * norm_q16
+ *              Return a Q16 value represeting a normalized value
+ *
+ * value       -100%                 0%               +100%
+ *                 |-----------------|----------------|
+ *                 ^                 ^                ^
+ *             q16MinValue     q16DefaultValue       q16MaxValue
+ *
+ */
+int32_t norm_q16(int32_t value, int32_t min, int32_t default_val, int32_t max,
+								int32_t range)
+{
+	int32_t diff, perc, mul, result;
+
+	if (0 == value) {
+		result = default_val;
+	} else if (value > 0) {
+		/* value is between 0% and +100% represent 1.0 -> QRange Max */
+		diff = range;
+		perc = Q16_PERCENT_VALUE(value, max);
+		mul = Q16_MUL(perc, diff);
+		result = default_val + mul;
+	} else {
+		/* if (value <= 0) */
+		diff = -range;
+		perc = Q16_PERCENT_VALUE(-value, -min);
+		mul = Q16_MUL(perc, diff);
+		result = default_val + mul;
+	}
+	return result;
+}
+
+void matrix_mul_3x3(int32_t dest[][3], int32_t a[][3], int32_t b[][3])
+{
+	int32_t i, j, k;
+	int32_t tmp[3][3];
+
+	for (i = 0; i < 3; i++) {
+		for (j = 0; j < 3; j++) {
+			tmp[i][j] = 0;
+			for (k = 0; k < 3; k++)
+				tmp[i][j] += Q16_MUL(a[i][k], b[k][j]);
+		}
+	}
+
+	/* in case dest = a or b*/
+	for (i = 0; i < 3; i++) {
+		for (j = 0; j < 3; j++)
+			dest[i][j] = tmp[i][j];
+	}
+}
+
+#define CONVERT(x)	(x)/*convert_q16_s49((x))*/
+void pr_params(struct mdp4_hsic_regs *regs)
+{
+	int i;
+	if (regs) {
+		for (i = 0; i < NUM_HSIC_PARAM; i++) {
+			pr_info("\t: hsic->params[%d] =	0x%08x [raw = 0x%08x]\n",
+			i, CONVERT(regs->params[i]), regs->params[i]);
+		}
+	}
+}
+
+void pr_3x3_matrix(int32_t in[][3])
+{
+	pr_info("\t[0x%08x\t0x%08x\t0x%08x]\n", CONVERT(in[0][0]),
+	CONVERT(in[0][1]), CONVERT(in[0][2]));
+	pr_info("\t[0x%08x\t0x%08x\t0x%08x]\n", CONVERT(in[1][0]),
+	CONVERT(in[1][1]), CONVERT(in[1][2]));
+	pr_info("\t[0x%08x\t0x%08x\t0x%08x]\n", CONVERT(in[2][0]),
+	CONVERT(in[2][1]), CONVERT(in[2][2]));
+}
+
+void _hsic_get(struct mdp4_hsic_regs *regs, int32_t type, int8_t *val)
+{
+	if (type < 0 || type >= NUM_HSIC_PARAM)
+		BUG_ON(-EINVAL);
+	*val = regs->params[type];
+	pr_info("%s: getting params[%d] = %d\n", __func__, type, *val);
+}
+
+void _hsic_set(struct mdp4_hsic_regs *regs, int32_t type, int8_t val)
+{
+	if (type < 0 || type >= NUM_HSIC_PARAM)
+		BUG_ON(-EINVAL);
+
+	if (regs->params[type] != Q16_VALUE(val)) {
+		regs->params[type] = Q16_VALUE(val);
+		regs->dirty = DIRTY;
+	}
+}
+
+void _hsic_generate_csc_matrix(struct mdp4_overlay_pipe *pipe)
+{
+	int i, j;
+	int32_t sin, cos;
+
+	int32_t hue_matrix[3][3];
+	int32_t con_sat_matrix[3][3];
+	struct mdp4_hsic_regs *regs = &(pipe->hsic_regs);
+
+	memset(con_sat_matrix, 0x0, sizeof(con_sat_matrix));
+	memset(hue_matrix, 0x0, sizeof(hue_matrix));
+
+	/*
+	 * HSIC control require matrix multiplication of these two tables
+	 *  [T 0 0][1 0  0]   T = Contrast       C=Cos(Hue)
+	 *  [0 S 0][0 C -N]   S = Saturation     N=Sin(Hue)
+	 *  [0 0 S][0 N  C]
+	 */
+
+	con_sat_matrix[0][0] = norm_q16(regs->params[HSIC_CON], CON_MIN,
+						CON_DEF, CON_MAX, CON_SAT_MAX);
+	con_sat_matrix[1][1] = norm_q16(regs->params[HSIC_SAT], SAT_MIN,
+						SAT_DEF, SAT_MAX, CON_SAT_MAX);
+	con_sat_matrix[2][2] = con_sat_matrix[1][1];
+
+	hue_matrix[0][0] = TRIG_MAX;
+
+	trig_values_q16(norm_q16(regs->params[HSIC_HUE], HUE_MIN, HUE_DEF,
+					 HUE_MAX, TRIG_MAX), &cos, &sin);
+
+	cos = Q16_MUL(cos, TRIG_MAX);
+	sin = Q16_MUL(sin, TRIG_MAX);
+
+	hue_matrix[1][1] = cos;
+	hue_matrix[2][2] = cos;
+	hue_matrix[2][1] = sin;
+	hue_matrix[1][2] = Q16_NEGATE(sin);
+
+	/* Generate YUV CSC matrix */
+	matrix_mul_3x3(regs->conv_matrix, con_sat_matrix, hue_matrix);
+
+	if (!(pipe->op_mode & MDP4_OP_SRC_DATA_YCBCR)) {
+		/* Convert input RGB to YUV then apply CSC matrix */
+		pr_info("Pipe %d, has RGB input\n", pipe->pipe_num);
+		matrix_mul_3x3(regs->conv_matrix, regs->conv_matrix,
+							csc_rgb2yuv_conv_tab);
+	}
+
+	/* Normalize the matrix */
+	for (i = 0; i < 3; i++) {
+		for (j = 0; j < 3; j++)
+			regs->conv_matrix[i][j] = (regs->conv_matrix[i][j]>>14);
+	}
+
+	/* Multiply above result by current csc table */
+	matrix_mul_3x3(regs->conv_matrix, regs->conv_matrix, csc_matrix_tab);
+
+	if (!(pipe->op_mode & MDP4_OP_SRC_DATA_YCBCR)) {
+		/*HACK:only "works"for src side*/
+		/* Convert back to RGB */
+		pr_info("Pipe %d, has RGB output\n", pipe->pipe_num);
+		matrix_mul_3x3(regs->conv_matrix, csc_yuv2rgb_conv_tab,
+							regs->conv_matrix);
+	}
+
+	/* Update clamps pre and post. */
+	/* TODO: different tables for different color formats? */
+	for (i = 0; i < 6; i++) {
+		regs->pre_limit[i] = csc_pre_lv_tab[i];
+		regs->post_limit[i] = csc_post_lv_tab[i];
+	}
+
+	/* update bias values, pre and post */
+	for (i = 0; i < 3; i++) {
+		regs->pre_bias[i] = csc_pre_bv_tab[i];
+		regs->post_bias[i] = csc_post_bv_tab[i] +
+				norm_q16(regs->params[HSIC_INT],
+				INTEN_MIN, INTEN_DEF, INTEN_MAX, INTENSITY_MAX);
+	}
+
+	regs->dirty = GENERATED;
+}
+
+void _hsic_update_mdp(struct mdp4_overlay_pipe *pipe)
+{
+	struct mdp4_hsic_regs *regs = &(pipe->hsic_regs);
+	int i, j, k;
+
+	uint32_t *csc_mv;
+	uint32_t *pre_lv;
+	uint32_t *post_lv;
+	uint32_t *pre_bv;
+	uint32_t *post_bv;
+
+	switch (pipe->pipe_num) {
+	case OVERLAY_PIPE_VG2:
+		csc_mv = (uint32_t *) (MDP_VG1_CSC_MVn(0) +
+					MDP4_VIDEO_OFF);
+		pre_lv = (uint32_t *) (MDP_VG1_CSC_PRE_LVn(0) +
+					MDP4_VIDEO_OFF);
+		post_lv = (uint32_t *) (MDP_VG1_CSC_POST_LVn(0) +
+					MDP4_VIDEO_OFF);
+		pre_bv = (uint32_t *) (MDP_VG1_CSC_PRE_BVn(0) +
+					MDP4_VIDEO_OFF);
+		post_bv = (uint32_t *) (MDP_VG1_CSC_POST_BVn(0) +
+					MDP4_VIDEO_OFF);
+		break;
+	case OVERLAY_PIPE_VG1:
+	default:
+			csc_mv = (uint32_t *) MDP_VG1_CSC_MVn(0);
+			pre_lv = (uint32_t *) MDP_VG1_CSC_PRE_LVn(0);
+			post_lv = (uint32_t *) MDP_VG1_CSC_POST_LVn(0);
+			pre_bv = (uint32_t *) MDP_VG1_CSC_PRE_BVn(0);
+			post_bv = (uint32_t *) MDP_VG1_CSC_POST_BVn(0);
+		break;
+	}
+
+	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
+
+	for (i = 0; i < 3; i++) {
+		for (j = 0; j < 3; j++) {
+			k = (3*i) + j;
+			MDP_OUTP(csc_mv + k, convert_q16_s49(
+						regs->conv_matrix[i][j]));
+		}
+	}
+
+	for (i = 0; i < 6; i++) {
+		MDP_OUTP(pre_lv + i, convert_q16_s49(regs->pre_limit[i]));
+		MDP_OUTP(post_lv + i, convert_q16_s49(regs->post_limit[i]));
+	}
+
+	for (i = 0; i < 3; i++) {
+		MDP_OUTP(pre_bv + i, convert_q16_s49(regs->pre_bias[i]));
+		MDP_OUTP(post_bv + i, convert_q16_s49(regs->post_bias[i]));
+	}
+	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+
+	regs->dirty = CLEAN;
+}
+
+void mdp4_hsic_get(struct mdp4_overlay_pipe *pipe, struct dpp_ctrl *ctrl)
+{
+	int i;
+	for (i = 0; i < NUM_HSIC_PARAM; i++)
+		_hsic_get(&(pipe->hsic_regs), i, &(ctrl->hsic_params[i]));
+}
+
+void mdp4_hsic_set(struct mdp4_overlay_pipe *pipe, struct dpp_ctrl *ctrl)
+{
+	int i;
+	for (i = 0; i < NUM_HSIC_PARAM; i++)
+		_hsic_set(&(pipe->hsic_regs), i, ctrl->hsic_params[i]);
+
+	if (pipe->hsic_regs.dirty == DIRTY)
+		_hsic_generate_csc_matrix(pipe);
+}
+
+void mdp4_hsic_update(struct mdp4_overlay_pipe *pipe)
+{
+	if (pipe->hsic_regs.dirty == GENERATED)
+		_hsic_update_mdp(pipe);
+}
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index dbed160..1b80d4c 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -41,28 +41,13 @@
 #define VERSION_KEY_MASK	0xFFFFFF00
 
 struct mdp4_overlay_ctrl {
-	struct mdp4_pipe_desc ov_pipe[OVERLAY_PIPE_MAX];/* 4 */
-	struct mdp4_overlay_pipe plist[MDP4_MAX_PIPE];	/* 4 + 2 */
-	struct mdp4_overlay_pipe *stage[MDP4_MAX_MIXER][MDP4_MIXER_STAGE_MAX];
+	struct mdp4_overlay_pipe plist[OVERLAY_PIPE_MAX];
+	struct mdp4_overlay_pipe *stage[MDP4_MIXER_MAX][MDP4_MIXER_STAGE_MAX];
 	uint32 panel_3d;
 	uint32 panel_mode;
 	uint32 mixer0_played;
 	uint32 mixer1_played;
 } mdp4_overlay_db = {
-	.ov_pipe = {
-			{
-				.share = 0,	/* RGB 1 */
-			},
-			{
-				.share = 0,	/* RGB 2 */
-			},
-			{
-				.share = 1,	/* VG 1 */
-			},
-			{
-				.share = 1,	/* VG 2 */
-			},
-		},
 	.plist = {
 		{
 			.pipe_type = OVERLAY_TYPE_RGB,
@@ -75,25 +60,15 @@
 			.pipe_ndx = 2,
 		},
 		{
-			.pipe_type = OVERLAY_TYPE_RGB, /* shared */
+			.pipe_type = OVERLAY_TYPE_VIDEO,
 			.pipe_num = OVERLAY_PIPE_VG1,
 			.pipe_ndx = 3,
 		},
 		{
-			.pipe_type = OVERLAY_TYPE_RGB, /* shared */
+			.pipe_type = OVERLAY_TYPE_VIDEO,
 			.pipe_num = OVERLAY_PIPE_VG2,
 			.pipe_ndx = 4,
 		},
-		{
-			.pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
-			.pipe_num = OVERLAY_PIPE_VG1,
-			.pipe_ndx = 5,
-		},
-		{
-			.pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
-			.pipe_num = OVERLAY_PIPE_VG2,
-			.pipe_ndx = 6,
-		},
 	},
 };
 
@@ -1198,7 +1173,7 @@
 	struct mdp4_overlay_pipe *spipe;
 
 	spipe = mdp4_overlay_stage_pipe(pipe->mixer_num, pipe->mixer_stage);
-	if ((spipe != NULL) && (spipe != pipe)) {
+	if ((spipe != NULL) && (spipe->pipe_num != pipe->pipe_num)) {
 		pr_err("%s: unable to stage pipe=%d at mixer_stage=%d\n",
 				__func__, pipe->pipe_ndx, pipe->mixer_stage);
 		return;
@@ -1421,7 +1396,7 @@
 {
 	struct mdp4_overlay_pipe *pipe;
 
-	if (ndx <= 0 || ndx > MDP4_MAX_PIPE)
+	if (ndx <= 0 || ndx > OVERLAY_PIPE_MAX)
 		return NULL;
 
 	pipe = &ctrl->plist[ndx - 1];	/* ndx start from 1 */
@@ -1432,65 +1407,25 @@
 	return pipe;
 }
 
-struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(
-		int ptype, int mixer, int req_share)
+struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(int ptype, int mixer)
 {
-	int i, j, ndx, found;
-	struct mdp4_overlay_pipe *pipe, *opipe;
-	struct mdp4_pipe_desc  *pd;
+	int i;
+	struct mdp4_overlay_pipe *pipe;
 
-	found = 0;
-	pipe = &ctrl->plist[0];
-
-	for (i = 0; i < MDP4_MAX_PIPE; i++) {
-		if (pipe->pipe_type == ptype && pipe->pipe_used == 0) {
-			pd = &ctrl->ov_pipe[pipe->pipe_num];
-			if (pd->share) { /* pipe can be shared */
-				if (pd->ref_cnt == 0) {
-					/* not yet been used */
-					found++;
-					break;
-				}
-				/* pipe occupied already */
-				if (req_share && pd->ref_cnt < MDP4_MAX_SHARE) {
-					for (j = 0; j < MDP4_MAX_SHARE; j++) {
-						ndx = pd->ndx_list[j];
-						if (ndx != 0)
-							break;
-					}
-					/* ndx satrt from 1 */
-					opipe = &ctrl->plist[ndx - 1];
-					/*
-					 * occupied pipe willing to share and
-					 * same mixer
-					 */
-					if (opipe->pipe_share &&
-						opipe->mixer_num == mixer) {
-						found++;
-						break;
-					}
-				}
-			} else {	/* not a shared pipe */
-				if (req_share == 0  && pd->ref_cnt == 0) {
-					found++;
-					break;
-				}
-			}
+	for (i = 0; i < OVERLAY_PIPE_MAX; i++) {
+		pipe = &ctrl->plist[i];
+		if ((pipe->pipe_used == 0) && ((pipe->pipe_type == ptype) ||
+		    (ptype == OVERLAY_TYPE_RGB &&
+		     pipe->pipe_type == OVERLAY_TYPE_VIDEO))) {
+			init_completion(&pipe->comp);
+			init_completion(&pipe->dmas_comp);
+			pr_info("%s: pipe=%x ndx=%d num=%d\n", __func__,
+				(int)pipe, pipe->pipe_ndx, pipe->pipe_num);
+			return pipe;
 		}
-		pipe++;
 	}
 
-	if (found) {
-		init_completion(&pipe->comp);
-		init_completion(&pipe->dmas_comp);
-		pr_info("%s: pipe=%x ndx=%d num=%d share=%d cnt=%d\n",
-			__func__, (int)pipe, pipe->pipe_ndx, pipe->pipe_num,
-			pd->share, pd->ref_cnt);
-		return pipe;
-	}
-
-	pr_debug("%s: ptype=%d mixer=%d req_share=%d FAILED\n",
-			__func__, ptype, mixer, req_share);
+	pr_err("%s: ptype=%d FAILED\n", __func__, ptype);
 
 	return NULL;
 }
@@ -1498,24 +1433,9 @@
 
 void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe)
 {
-	int i;
 	uint32 ptype, num, ndx;
-	struct mdp4_pipe_desc  *pd;
 
-	pr_info("%s: pipe=%x ndx=%d\n", __func__,
-				(int)pipe, pipe->pipe_ndx);
-	pd = &ctrl->ov_pipe[pipe->pipe_num];
-	if (pd->ref_cnt) {
-		pd->ref_cnt--;
-		for (i = 0; i < MDP4_MAX_SHARE; i++) {
-			if (pd->ndx_list[i] == pipe->pipe_ndx) {
-				pd->ndx_list[i] = 0;
-				break;
-			}
-		}
-	}
-
-	pd->player = NULL;
+	pr_info("%s: pipe=%x ndx=%d\n", __func__, (int)pipe, pipe->pipe_ndx);
 
 	ptype = pipe->pipe_type;
 	num = pipe->pipe_num;
@@ -1627,16 +1547,14 @@
 			struct msm_fb_data_type *mfd)
 {
 	struct mdp4_overlay_pipe *pipe;
-	struct mdp4_pipe_desc  *pd;
-	int ret, ptype, req_share;
-	int j;
+	int ret, ptype;
 
 	if (mfd == NULL) {
 		pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
 		return -ENODEV;
 	}
 
-	if (mixer >= MDP4_MAX_MIXER) {
+	if (mixer >= MDP4_MIXER_MAX) {
 		pr_err("%s: mixer out of range!\n", __func__);
 		mdp4_stat.err_mixer++;
 		return -ERANGE;
@@ -1729,10 +1647,11 @@
 		return ptype;
 	}
 
-	req_share = (req->flags & MDP_OV_PIPE_SHARE);
+	if (req->flags & MDP_OV_PIPE_SHARE)
+		ptype = OVERLAY_TYPE_VIDEO; /* VG pipe supports both RGB+YUV */
 
 	if (req->id == MSMFB_NEW_REQUEST)  /* new request */
-		pipe = mdp4_overlay_pipe_alloc(ptype, mixer, req_share);
+		pipe = mdp4_overlay_pipe_alloc(ptype, mixer);
 	else
 		pipe = mdp4_overlay_ndx2pipe(req->id);
 
@@ -1764,15 +1683,6 @@
 	 * zorder 2 == stage 2 == 4
 	 */
 	if (req->id == MSMFB_NEW_REQUEST) {  /* new request */
-		pd = &ctrl->ov_pipe[pipe->pipe_num];
-		for (j = 0; j < MDP4_MAX_SHARE; j++) {
-			if (pd->ndx_list[j] == 0) {
-				pd->ndx_list[j] = pipe->pipe_ndx;
-				break;
-			}
-		}
-		pipe->pipe_share = req_share;
-		pd->ref_cnt++;
 		pipe->pipe_used++;
 		pipe->mixer_num = mixer;
 		pipe->mixer_stage = req->z_order + MDP4_MIXER_STAGE0;
@@ -2004,8 +1914,8 @@
 	else if (mdp4_overlay_is_rgb_type(req->src.format))
 		return OVERLAY_PERF_LEVEL1;
 
-	if (ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt &&
-		ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt)
+	if (ctrl->plist[OVERLAY_PIPE_VG1].pipe_used &&
+		ctrl->plist[OVERLAY_PIPE_VG2].pipe_used)
 		return OVERLAY_PERF_LEVEL1;
 
 	if (req->src.width*req->src.height <= OVERLAY_VGA_SIZE)
@@ -2114,6 +2024,10 @@
 		}
 	}
 
+	/* precompute HSIC matrices */
+	if (req->flags & MDP_DPP_HSIC)
+		mdp4_hsic_set(pipe, &(req->dpp));
+
 	mdp4_stat.overlay_set[pipe->mixer_num]++;
 
 	if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
@@ -2163,6 +2077,8 @@
 	struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
 	struct mdp4_overlay_pipe *pipe;
 	uint32 flags;
+	struct dpp_ctrl dpp;
+	int i;
 
 	if (mfd == NULL)
 		return -ENODEV;
@@ -2247,13 +2163,22 @@
 	}
 #endif
 
+	/* Reset any HSIC settings to default */
+	if (pipe->flags & MDP_DPP_HSIC) {
+		for (i = 0; i < NUM_HSIC_PARAM; i++)
+			dpp.hsic_params[i] = 0;
+
+		mdp4_hsic_set(pipe, &dpp);
+		mdp4_hsic_update(pipe);
+	}
+
 	mdp4_stat.overlay_unset[pipe->mixer_num]++;
 
 	mdp4_overlay_pipe_free(pipe);
 
-	if (!(ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt +
-		ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt))
-			mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
+	if (!(ctrl->plist[OVERLAY_PIPE_VG1].pipe_used +
+	      ctrl->plist[OVERLAY_PIPE_VG2].pipe_used))
+		mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
 
 	mutex_unlock(&mfd->dma->ov_mutex);
 
@@ -2329,7 +2254,6 @@
 	struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
 	struct msmfb_data *img;
 	struct mdp4_overlay_pipe *pipe;
-	struct mdp4_pipe_desc *pd;
 	ulong start, addr;
 	ulong len = 0;
 	struct file *srcp0_file = NULL;
@@ -2354,16 +2278,6 @@
 	if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
 		return -EINTR;
 
-	pd = &ctrl->ov_pipe[pipe->pipe_num];
-	if (pd->player && pipe != pd->player) {
-		if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
-			mutex_unlock(&mfd->dma->ov_mutex);
-			return 0; /* ignore it, kicked out already */
-		}
-	}
-
-	pd->player = pipe;	/* keep */
-
 	img = &req->data;
 	get_img(img, info, &start, &len, &srcp0_file, &srcp0_ihdl);
 	if (len == 0) {
@@ -2533,6 +2447,10 @@
 		}
 	}
 
+	/* write out DPP HSIC registers */
+	if (pipe->flags & MDP_DPP_HSIC)
+		mdp4_hsic_update(pipe);
+
 	mdp4_stat.overlay_play[pipe->mixer_num]++;
 	mutex_unlock(&mfd->dma->ov_mutex);
 end:
diff --git a/drivers/video/msm/mdp4_overlay_atv.c b/drivers/video/msm/mdp4_overlay_atv.c
index 420a9bc..f9951e9 100644
--- a/drivers/video/msm/mdp4_overlay_atv.c
+++ b/drivers/video/msm/mdp4_overlay_atv.c
@@ -62,7 +62,7 @@
 
 	if (atv_pipe == NULL) {
 		ptype = mdp4_overlay_format2type(mfd->fb_imgType);
-		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER1, 0);
+		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER1);
 		if (pipe == NULL)
 			return -EBUSY;
 		pipe->pipe_used++;
diff --git a/drivers/video/msm/mdp4_overlay_dsi_cmd.c b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
index 07322dc..143df46 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_cmd.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
@@ -139,7 +139,7 @@
 		ptype = mdp4_overlay_format2type(mfd->fb_imgType);
 		if (ptype < 0)
 			printk(KERN_INFO "%s: format2type failed\n", __func__);
-		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
+		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
 		if (pipe == NULL)
 			printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
 		pipe->pipe_used++;
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index 4e47093..1a5cb65 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -124,7 +124,7 @@
 		ptype = mdp4_overlay_format2type(mfd->fb_imgType);
 		if (ptype < 0)
 			printk(KERN_INFO "%s: format2type failed\n", __func__);
-		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
+		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
 		if (pipe == NULL) {
 			printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
 			return -EBUSY;
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index 13449d6..636d350 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -127,7 +127,7 @@
 		ptype = mdp4_overlay_format2type(format);
 		if (ptype < 0)
 			printk(KERN_INFO "%s: format2type failed\n", __func__);
-		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER1, 0);
+		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER1);
 		if (pipe == NULL) {
 			printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
 			return -EBUSY;
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index 75264ef..f44a409 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -114,7 +114,7 @@
 		ptype = mdp4_overlay_format2type(mfd->fb_imgType);
 		if (ptype < 0)
 			printk(KERN_INFO "%s: format2type failed\n", __func__);
-		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
+		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
 		if (pipe == NULL)
 			printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
 		pipe->pipe_used++;
diff --git a/drivers/video/msm/mdp4_overlay_mddi.c b/drivers/video/msm/mdp4_overlay_mddi.c
index bd94c56..928ac32 100644
--- a/drivers/video/msm/mdp4_overlay_mddi.c
+++ b/drivers/video/msm/mdp4_overlay_mddi.c
@@ -112,7 +112,7 @@
 		ptype = mdp4_overlay_format2type(mfd->fb_imgType);
 		if (ptype < 0)
 			printk(KERN_INFO "%s: format2type failed\n", __func__);
-		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
+		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
 		if (pipe == NULL)
 			printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
 		pipe->pipe_used++;
diff --git a/drivers/video/msm/msm_dss_io_7x27a.c b/drivers/video/msm/msm_dss_io_7x27a.c
index 5f1abd4..032c9cd 100644
--- a/drivers/video/msm/msm_dss_io_7x27a.c
+++ b/drivers/video/msm/msm_dss_io_7x27a.c
@@ -13,7 +13,6 @@
 #include <linux/clk.h>
 #include "msm_fb.h"
 #include "mipi_dsi.h"
-#include <mach/clk.h>
 
 /* multimedia sub system sfpb */
 char *mmss_sfpb_base;
@@ -313,7 +312,7 @@
 	unsigned data = 0;
 	uint32 pll_ctrl;
 
-	if (clk_set_min_rate(ebi1_dsi_clk, 65000000)) /* 65 MHz */
+	if (clk_set_rate(ebi1_dsi_clk, 65000000)) /* 65 MHz */
 		pr_err("%s: ebi1_dsi_clk set rate failed\n", __func__);
 	clk_enable(ebi1_dsi_clk);
 
@@ -339,7 +338,7 @@
 	clk_disable(mdp_dsi_pclk);
 	/* DSIPHY_PLL_CTRL_0, disable dsi pll */
 	MIPI_OUTP(MIPI_DSI_BASE + 0x0200, 0x40);
-	if (clk_set_min_rate(ebi1_dsi_clk, 0))
+	if (clk_set_rate(ebi1_dsi_clk, 0))
 		pr_err("%s: ebi1_dsi_clk set rate failed\n", __func__);
 	clk_disable(ebi1_dsi_clk);
 }
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index e3fbecb..ec8a176 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -420,6 +420,8 @@
 header-y += msm_audio_wma.h
 header-y += msm_audio_wmapro.h
 header-y += msm_audio_mvs.h
+header-y += msm_audio_qcp.h
+header-y += msm_audio_amrnb.h
 header-y += msm_ipc.h
 header-y += msm_charm.h
 header-y += tzcom.h
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index 5011229..5c67471 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -106,6 +106,14 @@
 	FB_IMG,
 };
 
+enum {
+	HSIC_HUE = 0,
+	HSIC_SAT,
+	HSIC_INT,
+	HSIC_CON,
+	NUM_HSIC_PARAM,
+};
+
 /* mdp_blit_req flag values */
 #define MDP_ROT_NOP 0
 #define MDP_FLIP_LR 0x1
@@ -132,6 +140,7 @@
 #define MDP_OV_PLAY_NOWAIT		0x00200000
 #define MDP_SOURCE_ROTATED_90		0x00100000
 #define MDP_MEMORY_ID_TYPE_FB		0x00001000
+#define MDP_DPP_HSIC			0x00080000
 
 #define MDP_TRANSP_NOP 0xffffffff
 #define MDP_ALPHA_NOP 0xff
@@ -250,6 +259,7 @@
 	 *  smoothed picture.
 	 */
 	int8_t sharp_strength;
+	int8_t hsic_params[NUM_HSIC_PARAM];
 };
 
 struct mdp_overlay {
diff --git a/net/bluetooth/amp.c b/net/bluetooth/amp.c
index cb43a9c..af8ee26 100644
--- a/net/bluetooth/amp.c
+++ b/net/bluetooth/amp.c
@@ -51,20 +51,20 @@
 {
 	BT_DBG("mgr %p", mgr);
 
-	write_lock_bh(&amp_mgr_list_lock);
+	write_lock(&amp_mgr_list_lock);
 	list_del(&mgr->list);
-	write_unlock_bh(&amp_mgr_list_lock);
+	write_unlock(&amp_mgr_list_lock);
 
-	read_lock_bh(&mgr->ctx_list_lock);
+	read_lock(&mgr->ctx_list_lock);
 	while (!list_empty(&mgr->ctx_list)) {
 		struct amp_ctx *ctx;
 		ctx = list_first_entry(&mgr->ctx_list, struct amp_ctx, list);
-		read_unlock_bh(&mgr->ctx_list_lock);
+		read_unlock(&mgr->ctx_list_lock);
 		BT_DBG("kill ctx %p", ctx);
 		kill_ctx(ctx);
-		read_lock_bh(&mgr->ctx_list_lock);
+		read_lock(&mgr->ctx_list_lock);
 	}
-	read_unlock_bh(&mgr->ctx_list_lock);
+	read_unlock(&mgr->ctx_list_lock);
 
 	kfree(mgr->ctrls);
 
@@ -76,14 +76,14 @@
 	struct amp_mgr *mgr;
 	struct amp_mgr *found = NULL;
 
-	read_lock_bh(&amp_mgr_list_lock);
+	read_lock(&amp_mgr_list_lock);
 	list_for_each_entry(mgr, &amp_mgr_list, list) {
 		if ((mgr->a2mp_sock) && (mgr->a2mp_sock->sk == sk)) {
 			found = mgr;
 			break;
 		}
 	}
-	read_unlock_bh(&amp_mgr_list_lock);
+	read_unlock(&amp_mgr_list_lock);
 	return found;
 }
 
@@ -92,17 +92,19 @@
 {
 	struct amp_mgr *mgr;
 
-	write_lock_bh(&amp_mgr_list_lock);
+	write_lock(&amp_mgr_list_lock);
 	list_for_each_entry(mgr, &amp_mgr_list, list) {
 		if (mgr->l2cap_conn == conn) {
 			BT_DBG("conn %p found %p", conn, mgr);
+			write_unlock(&amp_mgr_list_lock);
 			goto gc_finished;
 		}
 	}
+	write_unlock(&amp_mgr_list_lock);
 
 	mgr = kzalloc(sizeof(*mgr), GFP_ATOMIC);
 	if (!mgr)
-		goto gc_finished;
+		return NULL;
 
 	mgr->l2cap_conn = conn;
 	mgr->next_ident = 1;
@@ -113,12 +115,13 @@
 	mgr->a2mp_sock = open_fixed_channel(conn->src, conn->dst);
 	if (!mgr->a2mp_sock) {
 		kfree(mgr);
-		goto gc_finished;
+		return NULL;
 	}
+	write_lock(&amp_mgr_list_lock);
 	list_add(&(mgr->list), &amp_mgr_list);
+	write_unlock(&amp_mgr_list_lock);
 
 gc_finished:
-	write_unlock_bh(&amp_mgr_list_lock);
 	return mgr;
 }
 
@@ -169,9 +172,9 @@
 static inline void start_ctx(struct amp_mgr *mgr, struct amp_ctx *ctx)
 {
 	BT_DBG("ctx %p", ctx);
-	write_lock_bh(&mgr->ctx_list_lock);
+	write_lock(&mgr->ctx_list_lock);
 	list_add(&ctx->list, &mgr->ctx_list);
-	write_unlock_bh(&mgr->ctx_list_lock);
+	write_unlock(&mgr->ctx_list_lock);
 	ctx->mgr = mgr;
 	execute_ctx(ctx, AMP_INIT, 0);
 }
@@ -182,9 +185,9 @@
 
 	BT_DBG("ctx %p deferred %p", ctx, ctx->deferred);
 	del_timer(&ctx->timer);
-	write_lock_bh(&mgr->ctx_list_lock);
+	write_lock(&mgr->ctx_list_lock);
 	list_del(&ctx->list);
-	write_unlock_bh(&mgr->ctx_list_lock);
+	write_unlock(&mgr->ctx_list_lock);
 	if (ctx->deferred)
 		execute_ctx(ctx->deferred, AMP_INIT, 0);
 	kfree(ctx);
@@ -195,14 +198,14 @@
 	struct amp_ctx *fnd = NULL;
 	struct amp_ctx *ctx;
 
-	read_lock_bh(&mgr->ctx_list_lock);
+	read_lock(&mgr->ctx_list_lock);
 	list_for_each_entry(ctx, &mgr->ctx_list, list) {
 		if (ctx->type == type) {
 			fnd = ctx;
 			break;
 		}
 	}
-	read_unlock_bh(&mgr->ctx_list_lock);
+	read_unlock(&mgr->ctx_list_lock);
 	return fnd;
 }
 
@@ -212,14 +215,14 @@
 	struct amp_ctx *fnd = NULL;
 	struct amp_ctx *ctx;
 
-	read_lock_bh(&mgr->ctx_list_lock);
+	read_lock(&mgr->ctx_list_lock);
 	list_for_each_entry(ctx, &mgr->ctx_list, list) {
 		if ((ctx->type == type) && (ctx != cur)) {
 			fnd = ctx;
 			break;
 		}
 	}
-	read_unlock_bh(&mgr->ctx_list_lock);
+	read_unlock(&mgr->ctx_list_lock);
 	return fnd;
 }
 
@@ -228,7 +231,7 @@
 	struct amp_ctx *fnd = NULL;
 	struct amp_ctx *ctx;
 
-	read_lock_bh(&mgr->ctx_list_lock);
+	read_lock(&mgr->ctx_list_lock);
 	list_for_each_entry(ctx, &mgr->ctx_list, list) {
 		if ((ctx->evt_type & AMP_A2MP_RSP) &&
 				(ctx->rsp_ident == ident)) {
@@ -236,7 +239,7 @@
 			break;
 		}
 	}
-	read_unlock_bh(&mgr->ctx_list_lock);
+	read_unlock(&mgr->ctx_list_lock);
 	return fnd;
 }
 
@@ -246,10 +249,10 @@
 	struct amp_mgr *mgr;
 	struct amp_ctx *fnd = NULL;
 
-	read_lock_bh(&amp_mgr_list_lock);
+	read_lock(&amp_mgr_list_lock);
 	list_for_each_entry(mgr, &amp_mgr_list, list) {
 		struct amp_ctx *ctx;
-		read_lock_bh(&mgr->ctx_list_lock);
+		read_lock(&mgr->ctx_list_lock);
 		list_for_each_entry(ctx, &mgr->ctx_list, list) {
 			struct hci_dev *ctx_hdev;
 			ctx_hdev = hci_dev_get(A2MP_HCI_ID(ctx->id));
@@ -272,9 +275,9 @@
 			if (fnd)
 				break;
 		}
-		read_unlock_bh(&mgr->ctx_list_lock);
+		read_unlock(&mgr->ctx_list_lock);
 	}
-	read_unlock_bh(&amp_mgr_list_lock);
+	read_unlock(&amp_mgr_list_lock);
 	return fnd;
 }
 
@@ -371,13 +374,13 @@
 {
 	struct amp_mgr *mgr;
 
-	read_lock_bh(&amp_mgr_list_lock);
+	read_lock(&amp_mgr_list_lock);
 	list_for_each_entry(mgr, &amp_mgr_list, list) {
 		if (mgr->discovered)
 			send_a2mp_cl(mgr, next_ident(mgr),
 					A2MP_CHANGE_NOTIFY, 0, NULL);
 	}
-	read_unlock_bh(&amp_mgr_list_lock);
+	read_unlock(&amp_mgr_list_lock);
 }
 
 static inline int discover_req(struct amp_mgr *mgr, struct sk_buff *skb)
@@ -1517,10 +1520,10 @@
 	struct amp_ctx *ctx = NULL;
 
 	BT_DBG("mgr %p", mgr);
-	read_lock_bh(&mgr->ctx_list_lock);
+	read_lock(&mgr->ctx_list_lock);
 	if (!list_empty(&mgr->ctx_list))
 		ctx = list_first_entry(&mgr->ctx_list, struct amp_ctx, list);
-	read_unlock_bh(&mgr->ctx_list_lock);
+	read_unlock(&mgr->ctx_list_lock);
 	BT_DBG("ctx %p", ctx);
 	if (ctx)
 		execute_ctx(ctx, AMP_INIT, NULL);
@@ -1549,7 +1552,7 @@
 
 /* L2CAP-A2MP interface */
 
-void a2mp_receive(struct sock *sk, struct sk_buff *skb)
+static void a2mp_receive(struct sock *sk, struct sk_buff *skb)
 {
 	struct a2mp_cmd_hdr *hdr = (struct a2mp_cmd_hdr *) skb->data;
 	int len;
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 094bfdb..0e7ff51 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -2608,7 +2608,10 @@
 	loc_mitm = conn->auth_type & 0x01;
 	rem_mitm = conn->remote_auth & 0x01;
 
-	if (loc_cap == 0x01 && (rem_cap == 0x00 || rem_cap == 0x03))
+	if ((conn->auth_type & HCI_AT_DEDICATED_BONDING) &&
+			conn->auth_initiator && rem_cap == 0x03)
+		ev.auto_confirm = 1;
+	else if (loc_cap == 0x01 && (rem_cap == 0x00 || rem_cap == 0x03))
 		goto no_auto_confirm;
 
 
diff --git a/sound/soc/msm/msm-pcm-q6.c b/sound/soc/msm/msm-pcm-q6.c
index 67e342e..738e024 100644
--- a/sound/soc/msm/msm-pcm-q6.c
+++ b/sound/soc/msm/msm-pcm-q6.c
@@ -51,9 +51,9 @@
 	.rate_max =             48000,
 	.channels_min =         1,
 	.channels_max =         2,
-	.buffer_bytes_max =     512 * 8,
-	.period_bytes_min =	512,
-	.period_bytes_max =     512,
+	.buffer_bytes_max =     320 * 8,
+	.period_bytes_min =	320,
+	.period_bytes_max =     320,
 	.periods_min =          8,
 	.periods_max =          8,
 	.fifo_size =            0,