Merge changes Ia45be862,I849d1f1b into msm-3.0
* changes:
msm: acpuclock-9615: Remove CXO voting
msm: clock-9615: Introduce new PLLs for acpuclock
diff --git a/arch/arm/mach-msm/acpuclock-9615.c b/arch/arm/mach-msm/acpuclock-9615.c
index e6206dd..1f112f6 100644
--- a/arch/arm/mach-msm/acpuclock-9615.c
+++ b/arch/arm/mach-msm/acpuclock-9615.c
@@ -56,7 +56,6 @@
};
static struct src_clock clocks[NUM_SRC] = {
- [SRC_CXO].name = "cxo",
[SRC_PLL0].name = "pll0",
[SRC_PLL8].name = "pll8",
[SRC_PLL9].name = "pll9",
@@ -320,7 +319,7 @@
for (i = 0; i < NUM_SRC; i++) {
if (clocks[i].name) {
- clocks[i].clk = clk_get_sys(NULL, clocks[i].name);
+ clocks[i].clk = clk_get_sys("acpu", clocks[i].name);
BUG_ON(IS_ERR(clocks[i].clk));
}
}
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 7e163df..5974300 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -249,19 +249,83 @@
},
};
+static DEFINE_SPINLOCK(soft_vote_lock);
+
+static int pll_acpu_vote_clk_enable(struct clk *clk)
+{
+ int ret = 0;
+ unsigned long flags;
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+ spin_lock_irqsave(&soft_vote_lock, flags);
+
+ if (!*pll->soft_vote)
+ ret = pll_vote_clk_enable(clk);
+ if (ret == 0)
+ *pll->soft_vote |= (pll->soft_vote_mask);
+
+ spin_unlock_irqrestore(&soft_vote_lock, flags);
+ return ret;
+}
+
+static void pll_acpu_vote_clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+ spin_lock_irqsave(&soft_vote_lock, flags);
+
+ *pll->soft_vote &= ~(pll->soft_vote_mask);
+ if (!*pll->soft_vote)
+ pll_vote_clk_disable(clk);
+
+ spin_unlock_irqrestore(&soft_vote_lock, flags);
+}
+
+static struct clk_ops clk_ops_pll_acpu_vote = {
+ .enable = pll_acpu_vote_clk_enable,
+ .disable = pll_acpu_vote_clk_disable,
+ .auto_off = pll_acpu_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+ .get_rate = pll_vote_clk_get_rate,
+ .get_parent = pll_vote_clk_get_parent,
+ .is_local = local_clk_is_local,
+};
+
+#define PLL_SOFT_VOTE_PRIMARY BIT(0)
+#define PLL_SOFT_VOTE_ACPU BIT(1)
+
+static unsigned int soft_vote_pll0;
+
static struct pll_vote_clk pll0_clk = {
.rate = 276000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
.parent = &cxo_clk.c,
+ .soft_vote = &soft_vote_pll0,
+ .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
.dbg_name = "pll0_clk",
- .ops = &clk_ops_pll_vote,
+ .ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll0_clk.c),
},
};
+static struct pll_vote_clk pll0_acpu_clk = {
+ .rate = 276000000,
+ .en_reg = BB_PLL_ENA_SC0_REG,
+ .en_mask = BIT(0),
+ .status_reg = BB_PLL0_STATUS_REG,
+ .soft_vote = &soft_vote_pll0,
+ .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
+ .c = {
+ .dbg_name = "pll0_acpu_clk",
+ .ops = &clk_ops_pll_acpu_vote,
+ CLK_INIT(pll0_acpu_clk.c),
+ },
+};
+
static struct pll_vote_clk pll4_clk = {
.rate = 393216000,
.en_reg = BB_PLL_ENA_SC0_REG,
@@ -275,32 +339,68 @@
},
};
+static unsigned int soft_vote_pll8;
+
static struct pll_vote_clk pll8_clk = {
.rate = 384000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.parent = &cxo_clk.c,
+ .soft_vote = &soft_vote_pll8,
+ .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
.dbg_name = "pll8_clk",
- .ops = &clk_ops_pll_vote,
+ .ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll8_clk.c),
},
};
+static struct pll_vote_clk pll8_acpu_clk = {
+ .rate = 384000000,
+ .en_reg = BB_PLL_ENA_SC0_REG,
+ .en_mask = BIT(8),
+ .status_reg = BB_PLL8_STATUS_REG,
+ .soft_vote = &soft_vote_pll8,
+ .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
+ .c = {
+ .dbg_name = "pll8_acpu_clk",
+ .ops = &clk_ops_pll_acpu_vote,
+ CLK_INIT(pll8_acpu_clk.c),
+ },
+};
+
+static unsigned int soft_vote_pll9;
+
static struct pll_vote_clk pll9_clk = {
.rate = 440000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(9),
.status_reg = SC_PLL0_STATUS_REG,
.parent = &cxo_clk.c,
+ .soft_vote = &soft_vote_pll9,
+ .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
.dbg_name = "pll9_clk",
- .ops = &clk_ops_pll_vote,
+ .ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll9_clk.c),
},
};
+static struct pll_vote_clk pll9_acpu_clk = {
+ .rate = 440000000,
+ .en_reg = BB_PLL_ENA_SC0_REG,
+ .en_mask = BIT(9),
+ .soft_vote = &soft_vote_pll9,
+ .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
+ .status_reg = SC_PLL0_STATUS_REG,
+ .c = {
+ .dbg_name = "pll9_acpu_clk",
+ .ops = &clk_ops_pll_acpu_vote,
+ CLK_INIT(pll9_acpu_clk.c),
+ },
+};
+
static struct pll_vote_clk pll14_clk = {
.rate = 480000000,
.en_reg = BB_PLL_ENA_SC0_REG,
@@ -1557,6 +1657,11 @@
CLK_LOOKUP("pll8", pll8_clk.c, NULL),
CLK_LOOKUP("pll9", pll9_clk.c, NULL),
CLK_LOOKUP("pll14", pll14_clk.c, NULL),
+
+ CLK_LOOKUP("pll0", pll0_acpu_clk.c, "acpu"),
+ CLK_LOOKUP("pll8", pll8_acpu_clk.c, "acpu"),
+ CLK_LOOKUP("pll9", pll9_acpu_clk.c, "acpu"),
+
CLK_LOOKUP("measure", measure_clk.c, "debug"),
CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index c1cfb55..2391f84 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -641,7 +641,7 @@
return 1;
}
-static int pll_vote_clk_enable(struct clk *clk)
+int pll_vote_clk_enable(struct clk *clk)
{
u32 ena;
unsigned long flags;
@@ -660,7 +660,7 @@
return 0;
}
-static void pll_vote_clk_disable(struct clk *clk)
+void pll_vote_clk_disable(struct clk *clk)
{
u32 ena;
unsigned long flags;
@@ -673,19 +673,19 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-static unsigned long pll_vote_clk_get_rate(struct clk *clk)
+unsigned long pll_vote_clk_get_rate(struct clk *clk)
{
struct pll_vote_clk *pll = to_pll_vote_clk(clk);
return pll->rate;
}
-static struct clk *pll_vote_clk_get_parent(struct clk *clk)
+struct clk *pll_vote_clk_get_parent(struct clk *clk)
{
struct pll_vote_clk *pll = to_pll_vote_clk(clk);
return pll->parent;
}
-static int pll_vote_clk_is_enabled(struct clk *clk)
+int pll_vote_clk_is_enabled(struct clk *clk)
{
struct pll_vote_clk *pll = to_pll_vote_clk(clk);
return !!(readl_relaxed(pll->status_reg) & BIT(16));
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index 16a9955..2107567 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -177,6 +177,8 @@
/**
* struct pll_vote_clk - phase locked loop (HW voteable)
* @rate: output rate
+ * @soft_vote: soft voting variable for multiple PLL software instances
+ * @soft_vote_mask: soft voting mask for multiple PLL software instances
* @en_reg: enable register
* @en_mask: ORed with @en_reg to enable the clock
* @status_reg: status register
@@ -186,6 +188,8 @@
struct pll_vote_clk {
unsigned long rate;
+ u32 *soft_vote;
+ const u32 soft_vote_mask;
void __iomem *const en_reg;
const u32 en_mask;
@@ -288,6 +292,15 @@
bool local_clk_is_local(struct clk *clk);
/*
+ * PLL vote clock APIs
+ */
+int pll_vote_clk_enable(struct clk *clk);
+void pll_vote_clk_disable(struct clk *clk);
+unsigned long pll_vote_clk_get_rate(struct clk *clk);
+struct clk *pll_vote_clk_get_parent(struct clk *clk);
+int pll_vote_clk_is_enabled(struct clk *clk);
+
+/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);