Merge "msm: 8960: pmic: Update Lookup table entry for LPG" into msm-3.4
diff --git a/arch/arm/boot/dts/msm9625.dts b/arch/arm/boot/dts/msm9625.dts
index d5aed00..b7b8be2 100644
--- a/arch/arm/boot/dts/msm9625.dts
+++ b/arch/arm/boot/dts/msm9625.dts
@@ -33,9 +33,11 @@
reg = <0xfd510000 0x4000>;
};
- timer {
+ timer: msm-qtimer@f9021000 {
compatible = "qcom,msm-qtimer", "arm,armv7-timer";
+ reg = <0xF9021000 0x1000>;
interrupts = <0 7 0>;
+ irq-is-not-percpu;
clock-frequency = <5000000>;
};
diff --git a/arch/arm/configs/msm-copper_defconfig b/arch/arm/configs/msm-copper_defconfig
index 473a7d5..49fae4a 100644
--- a/arch/arm/configs/msm-copper_defconfig
+++ b/arch/arm/configs/msm-copper_defconfig
@@ -69,10 +69,11 @@
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 7efd66a..a163829 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -228,6 +228,7 @@
CONFIG_BATTERY_MSM=y
CONFIG_SENSORS_MSM_ADC=y
CONFIG_MARIMBA_CORE=y
+CONFIG_REGULATOR_MSM_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index abe46bc..d8e2e3c 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -229,6 +229,7 @@
CONFIG_BATTERY_MSM=y
CONFIG_SENSORS_MSM_ADC=y
CONFIG_MARIMBA_CORE=y
+CONFIG_REGULATOR_MSM_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
diff --git a/arch/arm/configs/msm9625_defconfig b/arch/arm/configs/msm9625_defconfig
index 62369ac..1e45f66 100644
--- a/arch/arm/configs/msm9625_defconfig
+++ b/arch/arm/configs/msm9625_defconfig
@@ -1,3 +1,4 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 2098288..99ee2de 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -4,7 +4,7 @@
#include <linux/ioport.h>
struct arch_timer {
- struct resource res[2];
+ struct resource res[3];
};
#ifdef CONFIG_ARM_ARCH_TIMER
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index 0bdb0f1..a6ec7b2 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -146,7 +146,6 @@
unsigned int msmsdcc_fmid;
unsigned int msmsdcc_fmax;
bool nonremovable;
- bool pclk_src_dfab;
unsigned int mpm_sdiowakeup_int;
unsigned int wpswitch_gpio;
unsigned char wpswitch_polarity;
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 81a9a71..88cf368 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -19,6 +19,7 @@
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
+#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -32,8 +33,43 @@
static unsigned long arch_timer_rate;
static int arch_timer_ppi;
static int arch_timer_ppi2;
+static int is_irq_percpu;
static struct clock_event_device __percpu **arch_timer_evt;
+static void __iomem *timer_base;
+
+static u32 timer_reg_read_cp15(int reg);
+static void timer_reg_write_cp15(int reg, u32 val);
+static inline cycle_t counter_get_cntpct_cp15(void);
+static inline cycle_t counter_get_cntvct_cp15(void);
+
+static u32 timer_reg_read_mem(int reg);
+static void timer_reg_write_mem(int reg, u32 val);
+static inline cycle_t counter_get_cntpct_mem(void);
+static inline cycle_t counter_get_cntvct_mem(void);
+
+struct arch_timer_operations {
+ void (*reg_write)(int, u32);
+ u32 (*reg_read)(int);
+ cycle_t (*get_cntpct)(void);
+ cycle_t (*get_cntvct)(void);
+};
+
+static struct arch_timer_operations arch_timer_ops_cp15 = {
+ .reg_read = &timer_reg_read_cp15,
+ .reg_write = &timer_reg_write_cp15,
+ .get_cntpct = &counter_get_cntpct_cp15,
+ .get_cntvct = &counter_get_cntvct_cp15,
+};
+
+static struct arch_timer_operations arch_timer_ops_mem = {
+ .reg_read = &timer_reg_read_mem,
+ .reg_write = &timer_reg_write_mem,
+ .get_cntpct = &counter_get_cntpct_mem,
+ .get_cntvct = &counter_get_cntvct_mem,
+};
+
+static struct arch_timer_operations *arch_specific_timer = &arch_timer_ops_cp15;
/*
* Architected system timer support.
@@ -47,7 +83,29 @@
#define ARCH_TIMER_REG_FREQ 1
#define ARCH_TIMER_REG_TVAL 2
-static void arch_timer_reg_write(int reg, u32 val)
+/* Iomapped Register Offsets */
+#define QTIMER_CNTP_LOW_REG 0x000
+#define QTIMER_CNTP_HIGH_REG 0x004
+#define QTIMER_CNTV_LOW_REG 0x008
+#define QTIMER_CNTV_HIGH_REG 0x00C
+#define QTIMER_CTRL_REG 0x02C
+#define QTIMER_FREQ_REG 0x010
+#define QTIMER_CNTP_TVAL_REG 0x028
+#define QTIMER_CNTV_TVAL_REG 0x038
+
+static void timer_reg_write_mem(int reg, u32 val)
+{
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ __raw_writel(val, timer_base + QTIMER_CTRL_REG);
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ __raw_writel(val, timer_base + QTIMER_CNTP_TVAL_REG);
+ break;
+ }
+}
+
+static void timer_reg_write_cp15(int reg, u32 val)
{
switch (reg) {
case ARCH_TIMER_REG_CTRL:
@@ -61,7 +119,28 @@
isb();
}
-static u32 arch_timer_reg_read(int reg)
+static u32 timer_reg_read_mem(int reg)
+{
+ u32 val;
+
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ val = __raw_readl(timer_base + QTIMER_CTRL_REG);
+ break;
+ case ARCH_TIMER_REG_FREQ:
+ val = __raw_readl(timer_base + QTIMER_FREQ_REG);
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ val = __raw_readl(timer_base + QTIMER_CNTP_TVAL_REG);
+ break;
+ default:
+ BUG();
+ }
+
+ return val;
+}
+
+static u32 timer_reg_read_cp15(int reg)
{
u32 val;
@@ -87,10 +166,11 @@
struct clock_event_device *evt;
unsigned long ctrl;
- ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+ ctrl = arch_specific_timer->reg_read(ARCH_TIMER_REG_CTRL);
if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
ctrl |= ARCH_TIMER_CTRL_IT_MASK;
- arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+ arch_specific_timer->reg_write(ARCH_TIMER_REG_CTRL,
+ ctrl);
evt = *__this_cpu_ptr(arch_timer_evt);
evt->event_handler(evt);
return IRQ_HANDLED;
@@ -103,9 +183,9 @@
{
unsigned long ctrl;
- ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+ ctrl = arch_specific_timer->reg_read(ARCH_TIMER_REG_CTRL);
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
- arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+ arch_specific_timer->reg_write(ARCH_TIMER_REG_CTRL, ctrl);
}
static void arch_timer_set_mode(enum clock_event_mode mode,
@@ -126,12 +206,12 @@
{
unsigned long ctrl;
- ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+ ctrl = arch_specific_timer->reg_read(ARCH_TIMER_REG_CTRL);
ctrl |= ARCH_TIMER_CTRL_ENABLE;
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
- arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
- arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+ arch_specific_timer->reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+ arch_specific_timer->reg_write(ARCH_TIMER_REG_TVAL, evt);
return 0;
}
@@ -168,19 +248,16 @@
static int local_timer_is_architected(void)
{
return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
- ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
+ ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
}
static int arch_timer_available(void)
{
unsigned long freq;
- if (!local_timer_is_architected())
- return -ENXIO;
-
if (arch_timer_rate == 0) {
- arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
- freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+ arch_specific_timer->reg_write(ARCH_TIMER_REG_CTRL, 0);
+ freq = arch_specific_timer->reg_read(ARCH_TIMER_REG_FREQ);
/* Check the timer frequency. */
if (freq == 0) {
@@ -196,33 +273,57 @@
return 0;
}
-static inline cycle_t arch_counter_get_cntpct(void)
+static inline cycle_t counter_get_cntpct_mem(void)
{
- u32 cvall, cvalh;
+ u32 cvall, cvalh, thigh;
- asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+ do {
+ cvalh = __raw_readl(timer_base + QTIMER_CNTP_HIGH_REG);
+ cvall = __raw_readl(timer_base + QTIMER_CNTP_LOW_REG);
+ thigh = __raw_readl(timer_base + QTIMER_CNTP_HIGH_REG);
+ } while (cvalh != thigh);
return ((cycle_t) cvalh << 32) | cvall;
}
-static inline cycle_t arch_counter_get_cntvct(void)
+static inline cycle_t counter_get_cntpct_cp15(void)
+{
+ u32 cvall, cvalh;
+
+ asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+ return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static inline cycle_t counter_get_cntvct_mem(void)
+{
+ u32 cvall, cvalh, thigh;
+
+ do {
+ cvalh = __raw_readl(timer_base + QTIMER_CNTV_HIGH_REG);
+ cvall = __raw_readl(timer_base + QTIMER_CNTV_LOW_REG);
+ thigh = __raw_readl(timer_base + QTIMER_CNTV_HIGH_REG);
+ } while (cvalh != thigh);
+
+ return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static inline cycle_t counter_get_cntvct_cp15(void)
{
u32 cvall, cvalh;
asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
return ((cycle_t) cvalh << 32) | cvall;
}
static cycle_t arch_counter_read(struct clocksource *cs)
{
- return arch_counter_get_cntpct();
+ return arch_specific_timer->get_cntpct();
}
#ifdef ARCH_HAS_READ_CURRENT_TIMER
int read_current_timer(unsigned long *timer_val)
{
- *timer_val = (unsigned long)arch_counter_get_cntpct();
+ *timer_val = (unsigned long)arch_specific_timer->get_cntpct();
return 0;
}
#endif
@@ -239,7 +340,7 @@
{
cycle_t cntvct;
- cntvct = arch_counter_get_cntvct();
+ cntvct = arch_specific_timer->get_cntvct();
/*
* The sched_clock infrastructure only knows about counters
@@ -273,6 +374,9 @@
{
int err;
+ if (!local_timer_is_architected())
+ arch_specific_timer = &arch_timer_ops_mem;
+
err = arch_timer_available();
if (err)
return err;
@@ -289,8 +393,12 @@
set_delay_fn(read_current_timer_delay_loop);
#endif
- err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
+ if (is_irq_percpu)
+ err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
"arch_timer", arch_timer_evt);
+ else
+ err = request_irq(arch_timer_ppi, arch_timer_handler, 0,
+ "arch_timer", arch_timer_evt);
if (err) {
pr_err("arch_timer: can't register interrupt %d (%d)\n",
arch_timer_ppi, err);
@@ -298,8 +406,13 @@
}
if (arch_timer_ppi2) {
- err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
- "arch_timer", arch_timer_evt);
+ if (is_irq_percpu)
+ err = request_percpu_irq(arch_timer_ppi2,
+ arch_timer_handler, "arch_timer",
+ arch_timer_evt);
+ else
+ err = request_irq(arch_timer_ppi2, arch_timer_handler,
+ 0, "arch_timer", arch_timer_evt);
if (err) {
pr_err("arch_timer: can't register interrupt %d (%d)\n",
arch_timer_ppi2, err);
@@ -336,6 +449,16 @@
if (at->res[1].start > 0 && (at->res[1].flags & IORESOURCE_IRQ))
arch_timer_ppi2 = at->res[1].start;
+ if (at->res[2].start > 0 && at->res[2].end > 0 &&
+ (at->res[2].flags & IORESOURCE_MEM))
+ timer_base = ioremap(at->res[2].start,
+ resource_size(&at->res[2]));
+
+ if (!timer_base) {
+ pr_err("arch_timer: cant map timer base\n");
+ return -ENOMEM;
+ }
+
return arch_timer_common_register();
}
@@ -366,6 +489,18 @@
pr_err("arch_timer: interrupt not specified in timer node\n");
return -ENODEV;
}
+
+ timer_base = of_iomap(np, 0);
+ if (!timer_base) {
+ pr_err("arch_timer: cant map timer base\n");
+ return -ENOMEM;
+ }
+
+ if (of_get_property(np, "irq-is-not-percpu", NULL))
+ is_irq_percpu = 0;
+ else
+ is_irq_percpu = 1;
+
arch_timer_ppi = ret;
ret = irq_of_parse_and_map(np, 1);
if (ret > 0)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 08b65db..3554b56 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -2257,6 +2257,16 @@
separately. This will guarantee that the last acesses for each cpu
will be logged but there will be fewer entries per cpu
+config MSM_EBI_ERP
+ bool "External Bus Interface (EBI) error reporting"
+ help
+ Say 'Y' here to enable reporting of external bus interface errors to
+ the kernel log. Information such as the offending address and
+ transaction type will be logged. This may be useful for debugging
+ seemingly broken memory accesses.
+
+ For production builds, you should probably say 'N' here.
+
config MSM_CACHE_ERP
bool "Cache / CPU error reporting"
depends on ARCH_MSM_KRAIT
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 5cc9471..3043b78 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -364,6 +364,7 @@
obj-$(CONFIG_ARCH_MSM8960) += mdm2.o mdm_common.o
obj-$(CONFIG_MSM_RTB) += msm_rtb.o
obj-$(CONFIG_MSM_CACHE_ERP) += cache_erp.o
+obj-$(CONFIG_MSM_EBI_ERP) += ebi_erp.o
obj-$(CONFIG_MSM_CACHE_DUMP) += msm_cache_dump.o
obj-$(CONFIG_MSM_HSIC_SYSMON) += hsic_sysmon.o
diff --git a/arch/arm/mach-msm/board-8064-display.c b/arch/arm/mach-msm/board-8064-display.c
index 71ad49a..7368f6e 100644
--- a/arch/arm/mach-msm/board-8064-display.c
+++ b/arch/arm/mach-msm/board-8064-display.c
@@ -58,11 +58,15 @@
};
#define LVDS_CHIMEI_PANEL_NAME "lvds_chimei_wxga"
+#define LVDS_FRC_PANEL_NAME "lvds_frc_fhd"
#define MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME "mipi_video_toshiba_wsvga"
#define MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME "mipi_video_chimei_wxga"
#define HDMI_PANEL_NAME "hdmi_msm"
#define TVOUT_PANEL_NAME "tvout_msm"
+#define LVDS_PIXEL_MAP_PATTERN_1 1
+#define LVDS_PIXEL_MAP_PATTERN_2 2
+
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
static unsigned char hdmi_is_primary = 1;
#else
@@ -98,12 +102,18 @@
strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
PANEL_NAME_MAX_LEN)))
return 0;
- } else if (machine_is_apq8064_cdp() ||
- machine_is_mpq8064_dtv()) {
+ } else if (machine_is_apq8064_cdp()) {
if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
strnlen(LVDS_CHIMEI_PANEL_NAME,
PANEL_NAME_MAX_LEN)))
return 0;
+ } else if (machine_is_mpq8064_dtv()) {
+ if (!strncmp(name, LVDS_FRC_PANEL_NAME,
+ strnlen(LVDS_FRC_PANEL_NAME,
+ PANEL_NAME_MAX_LEN))) {
+ set_mdp_clocks_for_wuxga();
+ return 0;
+ }
}
if (!strncmp(name, HDMI_PANEL_NAME,
@@ -599,7 +609,9 @@
u32 ver = socinfo_get_version();
if ((SOCINFO_VERSION_MAJOR(ver) == 1) &&
(SOCINFO_VERSION_MINOR(ver) == 0))
- return 1;
+ return LVDS_PIXEL_MAP_PATTERN_1;
+ } else if (machine_is_mpq8064_dtv()) {
+ return LVDS_PIXEL_MAP_PATTERN_2;
}
return 0;
}
@@ -624,6 +636,23 @@
}
};
+#define FRC_GPIO_UPDATE (SX150X_EXP4_GPIO_BASE + 8)
+#define FRC_GPIO_RESET (SX150X_EXP4_GPIO_BASE + 9)
+#define FRC_GPIO_PWR (SX150X_EXP4_GPIO_BASE + 10)
+
+static int lvds_frc_gpio[] = {FRC_GPIO_UPDATE, FRC_GPIO_RESET, FRC_GPIO_PWR};
+static struct lvds_panel_platform_data lvds_frc_pdata = {
+ .gpio = lvds_frc_gpio,
+};
+
+static struct platform_device lvds_frc_panel_device = {
+ .name = "lvds_frc_fhd",
+ .id = 0,
+ .dev = {
+ .platform_data = &lvds_frc_pdata,
+ }
+};
+
static int dsi2lvds_gpio[2] = {
LPM_CHANNEL,/* Backlight PWM-ID=0 for PMIC-GPIO#24 */
0x1F08 /* DSI2LVDS Bridge GPIO Output, mask=0x1f, out=0x08 */
@@ -921,6 +950,8 @@
platform_device_register(&mipi_dsi2lvds_bridge_device);
if (machine_is_apq8064_mtp())
platform_device_register(&mipi_dsi_toshiba_panel_device);
+ if (machine_is_mpq8064_dtv())
+ platform_device_register(&lvds_frc_panel_device);
msm_fb_register_device("mdp", &mdp_pdata);
msm_fb_register_device("lvds", &lvds_pdata);
diff --git a/arch/arm/mach-msm/board-8064-storage.c b/arch/arm/mach-msm/board-8064-storage.c
index 5f74468..fe4beab 100644
--- a/arch/arm/mach-msm/board-8064-storage.c
+++ b/arch/arm/mach-msm/board-8064-storage.c
@@ -247,7 +247,6 @@
#endif
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
- .pclk_src_dfab = 1,
.nonremovable = 1,
.pin_data = &mmc_slot_pin_data[SDCC1],
.vreg_data = &mmc_slot_vreg_data[SDCC1],
@@ -270,7 +269,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc2_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
- .pclk_src_dfab = 1,
.pin_data = &mmc_slot_pin_data[SDCC2],
.sdiowakeup_irq = MSM_GPIO_TO_INT(61),
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
@@ -290,7 +288,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc3_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
- .pclk_src_dfab = 1,
.pin_data = &mmc_slot_pin_data[SDCC3],
.vreg_data = &mmc_slot_vreg_data[SDCC3],
.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(17),
@@ -322,7 +319,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc4_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
- .pclk_src_dfab = 1,
.pin_data = &mmc_slot_pin_data[SDCC4],
.sdiowakeup_irq = MSM_GPIO_TO_INT(65),
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
diff --git a/arch/arm/mach-msm/board-8930-storage.c b/arch/arm/mach-msm/board-8930-storage.c
index bb35c95..65da578 100644
--- a/arch/arm/mach-msm/board-8930-storage.c
+++ b/arch/arm/mach-msm/board-8930-storage.c
@@ -239,7 +239,6 @@
#endif
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
- .pclk_src_dfab = 1,
.nonremovable = 1,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
.pin_data = &mmc_slot_pin_data[SDCC1],
@@ -254,7 +253,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc3_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
- .pclk_src_dfab = 1,
#ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT
/*TODO: Insert right replacement for PM8038 */
#ifndef MSM8930_PHASE_2
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 712b520..338cb84 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -1202,6 +1202,7 @@
[23] = MSM_GPIO_TO_INT(85),
[24] = MSM_GPIO_TO_INT(83),
[25] = USB1_HS_IRQ,
+ [26] = MSM_GPIO_TO_INT(6),
[27] = HDMI_IRQ,
[29] = MSM_GPIO_TO_INT(10),
[30] = MSM_GPIO_TO_INT(102),
@@ -1215,15 +1216,15 @@
[38] = MSM_GPIO_TO_INT(50),
[39] = MSM_GPIO_TO_INT(42),
[41] = MSM_GPIO_TO_INT(62),
- [42] = MSM_GPIO_TO_INT(76),
- [43] = MSM_GPIO_TO_INT(75),
+ [42] = MSM_GPIO_TO_INT(8),
+ [43] = MSM_GPIO_TO_INT(33),
[44] = MSM_GPIO_TO_INT(70),
[45] = MSM_GPIO_TO_INT(69),
[46] = MSM_GPIO_TO_INT(67),
[47] = MSM_GPIO_TO_INT(65),
- [48] = MSM_GPIO_TO_INT(58),
- [49] = MSM_GPIO_TO_INT(54),
- [50] = MSM_GPIO_TO_INT(52),
+ [48] = MSM_GPIO_TO_INT(55),
+ [49] = MSM_GPIO_TO_INT(74),
+ [50] = MSM_GPIO_TO_INT(98),
[51] = MSM_GPIO_TO_INT(49),
[52] = MSM_GPIO_TO_INT(40),
[53] = MSM_GPIO_TO_INT(37),
diff --git a/arch/arm/mach-msm/board-8960-storage.c b/arch/arm/mach-msm/board-8960-storage.c
index 85785fc..e674e91 100644
--- a/arch/arm/mach-msm/board-8960-storage.c
+++ b/arch/arm/mach-msm/board-8960-storage.c
@@ -290,7 +290,6 @@
#endif
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
- .pclk_src_dfab = 1,
.nonremovable = 1,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
.pin_data = &mmc_slot_pin_data[SDCC1],
@@ -309,7 +308,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc2_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
- .pclk_src_dfab = 1,
.vreg_data = &mmc_slot_vreg_data[SDCC2],
.pin_data = &mmc_slot_pin_data[SDCC2],
.sdiowakeup_irq = MSM_GPIO_TO_INT(90),
@@ -323,7 +321,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc3_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
- .pclk_src_dfab = 1,
#ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT
.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(16),
#endif
@@ -354,7 +351,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc4_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
- .pclk_src_dfab = 1,
.vreg_data = &mmc_slot_vreg_data[SDCC4],
.pin_data = &mmc_slot_pin_data[SDCC4],
.sdiowakeup_irq = MSM_GPIO_TO_INT(85),
diff --git a/arch/arm/mach-msm/board-9615-storage.c b/arch/arm/mach-msm/board-9615-storage.c
index 51e2432..2025bd0 100644
--- a/arch/arm/mach-msm/board-9615-storage.c
+++ b/arch/arm/mach-msm/board-9615-storage.c
@@ -176,7 +176,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
- .pclk_src_dfab = true,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
.pin_data = &mmc_slot_pin_data[SDCC1],
#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
@@ -205,7 +204,6 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc2_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
- .pclk_src_dfab = 1,
.pin_data = &mmc_slot_pin_data[SDCC2],
.sdiowakeup_irq = MSM_GPIO_TO_INT(GPIO_SDC2_DAT1_WAKEUP),
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
diff --git a/arch/arm/mach-msm/board-msm7627a-display.c b/arch/arm/mach-msm/board-msm7627a-display.c
index bd38f30..c2b7b9d 100644
--- a/arch/arm/mach-msm/board-msm7627a-display.c
+++ b/arch/arm/mach-msm/board-msm7627a-display.c
@@ -1140,6 +1140,7 @@
static int mipi_dsi_panel_qrd3_power(int on)
{
int rc = 0;
+ static struct regulator *gpio_reg_2p85v, *gpio_reg_1p8v;
if (!qrd3_dsi_gpio_initialized) {
rc = gpio_request(GPIO_QRD3_LCD_BACKLIGHT_EN,
@@ -1147,47 +1148,21 @@
if (rc < 0)
return rc;
- rc = gpio_request(GPIO_QRD3_LCD_EXT_2V85_EN,
- "qrd3_gpio_ext_2v85_en");
- if (rc < 0)
- return rc;
-
- rc = gpio_tlmm_config(GPIO_CFG(GPIO_QRD3_LCD_EXT_2V85_EN, 0,
- GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
- GPIO_CFG_ENABLE);
- if (rc < 0) {
- pr_err("failed QRD3 GPIO_QRD3_LCD_EXT_2V85_EN tlmm config\n");
- return rc;
+ gpio_reg_2p85v = regulator_get(&msm8625_mipi_dsi_device.dev,
+ "lcd_vdd");
+ if (IS_ERR(gpio_reg_2p85v)) {
+ pr_err("%s:ext_2p85v regulator get failed", __func__);
+ return -EINVAL;
}
- rc = gpio_direction_output(GPIO_QRD3_LCD_EXT_2V85_EN, 1);
- if (rc < 0) {
- pr_err("failed to enable external 2V85\n");
- gpio_free(GPIO_QRD3_LCD_EXT_2V85_EN);
- return rc;
+ gpio_reg_1p8v = regulator_get(&msm8625_mipi_dsi_device.dev,
+ "lcd_vddi");
+ if (IS_ERR(gpio_reg_1p8v)) {
+ pr_err("%s:ext_1p8v regulator get failed", __func__);
+ return -EINVAL;
}
- rc = gpio_request(GPIO_QRD3_LCD_EXT_1V8_EN,
- "qrd3_gpio_ext_1v8_en");
- if (rc < 0)
- return rc;
-
- rc = gpio_tlmm_config(GPIO_CFG(GPIO_QRD3_LCD_EXT_1V8_EN, 0,
- GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
- GPIO_CFG_ENABLE);
- if (rc < 0) {
- pr_err("failed QRD3 GPIO_QRD3_LCD_EXT_1V8_EN tlmm config\n");
- return rc;
- }
-
- rc = gpio_direction_output(GPIO_QRD3_LCD_EXT_1V8_EN, 1);
- if (rc < 0) {
- pr_err("failed to enable external 1v8\n");
- gpio_free(GPIO_QRD3_LCD_EXT_1V8_EN);
- return rc;
- }
-
- qrd3_dsi_gpio_initialized = 1;
+ qrd3_dsi_gpio_initialized = 1;
}
if (on) {
@@ -1204,7 +1179,7 @@
gpio_free(GPIO_QRD3_LCD_BACKLIGHT_EN);
return rc;
}
-
+ /*Toggle Backlight GPIO*/
gpio_set_value_cansleep(GPIO_QRD3_LCD_BACKLIGHT_EN, 1);
udelay(190);
gpio_set_value_cansleep(GPIO_QRD3_LCD_BACKLIGHT_EN, 0);
@@ -1212,18 +1187,17 @@
gpio_set_value_cansleep(GPIO_QRD3_LCD_BACKLIGHT_EN, 1);
/* 1 wire mode starts from this low to high transition */
udelay(50);
- } else {
- gpio_tlmm_config(GPIO_CFG(GPIO_QRD3_LCD_BACKLIGHT_EN, 0,
- GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
- GPIO_CFG_DISABLE);
- }
- gpio_set_value_cansleep(GPIO_QRD3_LCD_EXT_2V85_EN, !!on);
- gpio_set_value_cansleep(GPIO_QRD3_LCD_EXT_1V8_EN, !!on);
+ /*Enable EXT_2.85 and 1.8 regulators*/
+ rc = regulator_enable(gpio_reg_2p85v);
+ if (rc < 0)
+ pr_err("%s: reg enable failed\n", __func__);
+ rc = regulator_enable(gpio_reg_1p8v);
+ if (rc < 0)
+ pr_err("%s: reg enable failed\n", __func__);
- if (on) {
+ /*Configure LCD Bridge reset*/
rc = gpio_tlmm_config(qrd3_mipi_dsi_gpio[0], GPIO_CFG_ENABLE);
-
if (rc < 0) {
pr_err("Failed to enable LCD Bridge reset enable\n");
return rc;
@@ -1237,18 +1211,32 @@
return rc;
}
+ /*Toggle Bridge Reset GPIO*/
msleep(20);
gpio_set_value_cansleep(GPIO_QRD3_LCD_BRDG_RESET_N, 0);
msleep(20);
gpio_set_value_cansleep(GPIO_QRD3_LCD_BRDG_RESET_N, 1);
msleep(20);
+
} else {
+ gpio_tlmm_config(GPIO_CFG(GPIO_QRD3_LCD_BACKLIGHT_EN, 0,
+ GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
+ GPIO_CFG_DISABLE);
+
gpio_tlmm_config(GPIO_CFG(GPIO_QRD3_LCD_BRDG_RESET_N, 0,
GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
GPIO_CFG_DISABLE);
+
+ rc = regulator_disable(gpio_reg_2p85v);
+ if (rc < 0)
+ pr_err("%s: reg disable failed\n", __func__);
+ rc = regulator_disable(gpio_reg_1p8v);
+ if (rc < 0)
+ pr_err("%s: reg disable failed\n", __func__);
+
}
- return rc;
+ return rc;
}
static int mipi_dsi_panel_power(int on)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 73a900c..3488fb3 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -8389,7 +8389,6 @@
.msmsdcc_fmid = 24000000,
.msmsdcc_fmax = 48000000,
.nonremovable = 1,
- .pclk_src_dfab = 1,
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
};
#endif
@@ -8404,7 +8403,6 @@
.msmsdcc_fmid = 24000000,
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
- .pclk_src_dfab = 1,
.register_status_notify = sdc2_register_status_notify,
#ifdef CONFIG_MSM_SDIO_AL
.is_sdio_al_client = 1,
@@ -8429,7 +8427,6 @@
.msmsdcc_fmid = 24000000,
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
- .pclk_src_dfab = 1,
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
};
@@ -8444,7 +8441,6 @@
.msmsdcc_fmid = 24000000,
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
- .pclk_src_dfab = 1,
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC4_DAT1,
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
};
@@ -8460,7 +8456,6 @@
.msmsdcc_fmid = 24000000,
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
- .pclk_src_dfab = 1,
.register_status_notify = sdc5_register_status_notify,
#ifdef CONFIG_MSM_SDIO_AL
.is_sdio_al_client = 1,
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 761a3c9..c8f8b10 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -652,14 +652,16 @@
#define GPIO_VREG_ID_EXT_1P8V 1
static struct regulator_consumer_supply vreg_consumers_EXT_2P85V[] = {
- REGULATOR_SUPPLY("cam0_avdd", "0-006c"),
- REGULATOR_SUPPLY("cam1_avdd", "0-0078"),
+ REGULATOR_SUPPLY("cam_ov5647_avdd", "0-006c"),
+ REGULATOR_SUPPLY("cam_ov7692_avdd", "0-0078"),
+ REGULATOR_SUPPLY("cam_ov8825_avdd", "0-000d"),
REGULATOR_SUPPLY("lcd_vdd", "mipi_dsi.1"),
};
static struct regulator_consumer_supply vreg_consumers_EXT_1P8V[] = {
- REGULATOR_SUPPLY("cam0_vdd", "0-006c"),
- REGULATOR_SUPPLY("cam1_vdd", "0-0078"),
+ REGULATOR_SUPPLY("cam_ov5647_vdd", "0-006c"),
+ REGULATOR_SUPPLY("cam_ov7692_vdd", "0-0078"),
+ REGULATOR_SUPPLY("cam_ov8825_vdd", "0-000d"),
REGULATOR_SUPPLY("lcd_vddi", "mipi_dsi.1"),
};
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 4654606..adc9169 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -1445,7 +1445,7 @@
},
};
-static struct platform_device msm8625_mipi_dsi_device = {
+struct platform_device msm8625_mipi_dsi_device = {
.name = "mipi_dsi",
.id = 1,
.num_resources = ARRAY_SIZE(msm8625_mipi_dsi_resources),
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index f1d7aa0..2b2fcc7 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -300,6 +300,7 @@
extern struct platform_device msm_kgsl_2d1;
extern struct platform_device msm_mipi_dsi1_device;
+extern struct platform_device msm8625_mipi_dsi_device;
extern struct platform_device msm_lvds_device;
extern struct platform_device msm_ebi2_lcdc_device;
diff --git a/arch/arm/mach-msm/ebi_erp.c b/arch/arm/mach-msm/ebi_erp.c
new file mode 100644
index 0000000..cd9119d
--- /dev/null
+++ b/arch/arm/mach-msm/ebi_erp.c
@@ -0,0 +1,194 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/cpu.h>
+
+#define MODULE_NAME "msm_ebi_erp"
+
+#define EBI_ERR_ADDR 0x100
+#define SLV_ERR_APACKET_0 0x108
+#define SLV_ERR_APACKET_1 0x10C
+#define SLV_ERR_CNTL 0x114
+
+#define CNTL_ERR_OCCURRED BIT(4)
+#define CNTL_CLEAR_ERR BIT(8)
+#define CNTL_IRQ_EN BIT(12)
+
+#define AMID_MASK 0xFFFF
+#define ERR_AWRITE BIT(0)
+#define ERR_AOOOWR BIT(1)
+#define ERR_AOOORD BIT(2)
+#define ERR_APTORNS BIT(3)
+#define ERR_ALOCK_SHIFT 6
+#define ERR_ALOCK_MASK 0x3
+#define ERR_ATYPE_SHIFT 8
+#define ERR_ATYPE_MASK 0xF
+#define ERR_ABURST BIT(12)
+#define ERR_ASIZE_SHIFT 13
+#define ERR_ASIZE_MASK 0x7
+#define ERR_ATID_SHIFT 16
+#define ERR_ATID_MASK 0xFF
+#define ERR_ALEN_SHIFT 24
+#define ERR_ALEN_MASK 0xF
+
+#define ERR_CODE_DECODE_ERROR BIT(0)
+#define ERR_CODE_MPU_ERROR BIT(1)
+
+struct msm_ebi_erp_data {
+ void __iomem *base;
+ struct device *dev;
+};
+
+static const char *err_lock_types[4] = {
+ "normal",
+ "exclusive",
+ "locked",
+ "barrier",
+};
+
+static const char *err_sizes[8] = {
+ "byte",
+ "half word",
+ "word",
+ "double word",
+ "reserved_4",
+ "reserved_5",
+ "reserved_6",
+ "reserved_7",
+};
+
+static irqreturn_t msm_ebi_irq(int irq, void *dev_id)
+{
+ struct msm_ebi_erp_data *drvdata = dev_id;
+ void __iomem *base = drvdata->base;
+ unsigned int err_addr, err_apacket0, err_apacket1, err_cntl;
+
+ err_addr = readl_relaxed(base + EBI_ERR_ADDR);
+ err_apacket0 = readl_relaxed(base + SLV_ERR_APACKET_0);
+ err_apacket1 = readl_relaxed(base + SLV_ERR_APACKET_1);
+ err_cntl = readl_relaxed(base + SLV_ERR_CNTL);
+
+ if (!(err_cntl & CNTL_ERR_OCCURRED))
+ return IRQ_NONE;
+
+ pr_alert("EBI error detected!\n");
+ pr_alert("\tDevice = %s\n", dev_name(drvdata->dev));
+ pr_alert("\tERR_ADDR = 0x%08x\n", err_addr);
+ pr_alert("\tAPACKET0 = 0x%08x\n", err_apacket0);
+ pr_alert("\tAPACKET1 = 0x%08x\n", err_apacket1);
+ pr_alert("\tERR_CNTL = 0x%08x\n", err_cntl);
+
+ pr_alert("\tAMID = 0x%08x\n", err_apacket0 & AMID_MASK);
+ pr_alert("\tType = %s, %s, %s\n",
+ err_apacket1 & ERR_AWRITE ? "write" : "read",
+ err_sizes[(err_apacket1 >> ERR_ASIZE_SHIFT) & ERR_ASIZE_MASK],
+ err_apacket1 & ERR_APTORNS ? "non-secure" : "secure");
+
+ pr_alert("\tALOCK = %s\n",
+ err_lock_types[(err_apacket1 >> ERR_ALOCK_SHIFT) & ERR_ALOCK_MASK]);
+
+ pr_alert("\tABURST = %s\n", err_apacket1 & ERR_ABURST ?
+ "increment" : "wrap");
+
+ pr_alert("\tCODE = %s %s\n", err_cntl & ERR_CODE_DECODE_ERROR ?
+ "decode error" : "",
+ err_cntl & ERR_CODE_MPU_ERROR ?
+ "mpu error" : "");
+ err_cntl |= CNTL_CLEAR_ERR;
+ writel_relaxed(err_cntl, base + SLV_ERR_CNTL);
+ mb(); /* Ensure interrupt is cleared before returning */
+ return IRQ_HANDLED;
+}
+
+static int __devinit msm_ebi_erp_probe(struct platform_device *pdev)
+{
+ struct resource *r;
+ struct msm_ebi_erp_data *drvdata;
+ int ret, irq;
+ unsigned int err_cntl;
+
+ drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ drvdata->dev = &pdev->dev;
+ platform_set_drvdata(pdev, drvdata);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!r)
+ return -EINVAL;
+
+ drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+ if (!drvdata->base)
+ return -ENOMEM;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_irq(&pdev->dev, irq, msm_ebi_irq, IRQF_TRIGGER_HIGH,
+ dev_name(&pdev->dev), drvdata);
+ if (ret)
+ return ret;
+
+ /* Enable the interrupt */
+ err_cntl = readl_relaxed(drvdata->base + SLV_ERR_CNTL);
+ err_cntl |= CNTL_IRQ_EN;
+ writel_relaxed(err_cntl, drvdata->base + SLV_ERR_CNTL);
+ mb(); /* Ensure interrupt is enabled before returning */
+ return 0;
+}
+
+static int msm_ebi_erp_remove(struct platform_device *pdev)
+{
+ struct msm_ebi_erp_data *drvdata = platform_get_drvdata(pdev);
+ unsigned int err_cntl;
+
+ /* Disable the interrupt */
+ err_cntl = readl_relaxed(drvdata->base + SLV_ERR_CNTL);
+ err_cntl &= ~CNTL_IRQ_EN;
+ writel_relaxed(err_cntl, drvdata->base + SLV_ERR_CNTL);
+ mb(); /* Ensure interrupt is disabled before returning */
+ return 0;
+}
+
+static struct platform_driver msm_ebi_erp_driver = {
+ .probe = msm_ebi_erp_probe,
+ .remove = __devexit_p(msm_ebi_erp_remove),
+ .driver = {
+ .name = MODULE_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init msm_ebi_erp_init(void)
+{
+ return platform_driver_register(&msm_ebi_erp_driver);
+}
+
+static void __exit msm_ebi_erp_exit(void)
+{
+ platform_driver_unregister(&msm_ebi_erp_driver);
+}
+
+
+module_init(msm_ebi_erp_init);
+module_exit(msm_ebi_erp_exit);
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MSM cache error reporting driver");
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 86e06a4..e35d99b 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -34,7 +34,7 @@
.virtual = (unsigned long) MSM_##name##_BASE, \
.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
.length = chip##_##name##_SIZE, \
- .type = MT_DEVICE_NONSHARED, \
+ .type = MT_DEVICE, \
}
#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 09511b1..c3c09d4 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -108,6 +108,25 @@
return rc;
}
+static int msm_camera_v4l2_private_s_ctrl(struct file *f, void *pctx,
+ struct msm_camera_v4l2_ioctl_t *ioctl_ptr)
+{
+ int rc = -EINVAL;
+ struct msm_cam_v4l2_device *pcam = video_drvdata(f);
+ struct msm_cam_v4l2_dev_inst *pcam_inst;
+ pcam_inst = container_of(f->private_data,
+ struct msm_cam_v4l2_dev_inst, eventHandle);
+ WARN_ON(pctx != f->private_data);
+ mutex_lock(&pcam->vid_lock);
+ switch (ioctl_ptr->id) {
+ case MSM_V4L2_PID_CTRL_CMD:
+ rc = msm_server_proc_ctrl_cmd(pcam, ioctl_ptr, 1);
+ break;
+ }
+ mutex_unlock(&pcam->vid_lock);
+ return rc;
+}
+
static int msm_camera_v4l2_s_ctrl(struct file *f, void *pctx,
struct v4l2_control *ctrl)
{
@@ -127,17 +146,6 @@
__func__, pcam_inst, pcam_inst->my_index);
pcam_inst->is_mem_map_inst = 1;
break;
- case MSM_V4L2_PID_MMAP_ENTRY:
- if (copy_from_user(&pcam_inst->mem_map,
- (void *)ctrl->value,
- sizeof(struct msm_mem_map_info))) {
- rc = -EFAULT;
- } else
- D("%s:mmap entry:cookie=0x%x,mem_type=%d,len=%d\n",
- __func__, pcam_inst->mem_map.cookie,
- pcam_inst->mem_map.mem_type,
- pcam_inst->mem_map.length);
- break;
default:
if (ctrl->id == MSM_V4L2_PID_CAM_MODE)
pcam->op_mode = ctrl->value;
@@ -685,6 +693,22 @@
return rc;
}
+static long msm_camera_v4l2_private_ioctl(struct file *file, void *fh,
+ bool valid_prio, int cmd,
+ void *arg)
+{
+ int rc = -EINVAL;
+ struct msm_camera_v4l2_ioctl_t *ioctl_ptr = arg;
+ D("%s: cmd %d\n", __func__, _IOC_NR(cmd));
+
+ switch (cmd) {
+ case MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL:
+ rc = msm_camera_v4l2_private_s_ctrl(file, fh, ioctl_ptr);
+ break;
+ }
+ return rc;
+}
+
/* v4l2_ioctl_ops */
static const struct v4l2_ioctl_ops g_msm_ioctl_ops = {
.vidioc_querycap = msm_camera_v4l2_querycap,
@@ -724,6 +748,7 @@
/* event subscribe/unsubscribe */
.vidioc_subscribe_event = msm_camera_v4l2_subscribe_event,
.vidioc_unsubscribe_event = msm_camera_v4l2_unsubscribe_event,
+ .vidioc_default = msm_camera_v4l2_private_ioctl,
};
/* v4l2_file_operations */
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index c266b85..fab0095 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -661,6 +661,8 @@
case CMD_AXI_CFG_PRIM|CMD_AXI_CFG_SEC:
case CMD_AXI_CFG_PRIM|CMD_AXI_CFG_SEC_ALL_CHNLS:
case CMD_AXI_CFG_PRIM_ALL_CHNLS|CMD_AXI_CFG_SEC:
+ case CMD_AXI_START:
+ case CMD_AXI_STOP:
/* Dont need to pass buffer information.
* subdev will get the buffer from media
* controller free queue.
diff --git a/drivers/media/video/msm/msm_vfe31_v4l2.c b/drivers/media/video/msm/msm_vfe31_v4l2.c
index a010817..7a2670c 100644
--- a/drivers/media/video/msm/msm_vfe31_v4l2.c
+++ b/drivers/media/video/msm/msm_vfe31_v4l2.c
@@ -367,7 +367,7 @@
static void vfe31_stop(void)
{
-
+ uint8_t axiBusyFlag = true;
unsigned long flags;
atomic_set(&vfe31_ctrl->vstate, 0);
@@ -397,52 +397,6 @@
* at any time. stop camif immediately. */
msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
-}
-
-void axi_start(void)
-{
- switch (vfe31_ctrl->operation_mode) {
- case VFE_OUTPUTS_PREVIEW:
- case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
- if (vfe31_ctrl->outpath.output_mode &
- VFE31_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- } else if (vfe31_ctrl->outpath.output_mode &
- VFE31_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
- }
- break;
- default:
- if (vfe31_ctrl->outpath.output_mode &
- VFE31_OUTPUT_MODE_SECONDARY) {
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
- } else if (vfe31_ctrl->outpath.output_mode &
- VFE31_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
- msm_camera_io_w(1, vfe31_ctrl->vfebase +
- vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch2]);
- }
- break;
- }
-}
-
-void axi_stop(void)
-{
- uint8_t axiBusyFlag = true;
/* axi halt command. */
msm_camera_io_w(AXI_HALT,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
@@ -999,6 +953,43 @@
}
msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ switch (vfe31_ctrl->operation_mode) {
+ case VFE_OUTPUTS_PREVIEW:
+ case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
+ if (vfe31_ctrl->outpath.output_mode &
+ VFE31_OUTPUT_MODE_PRIMARY) {
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
+ } else if (vfe31_ctrl->outpath.output_mode &
+ VFE31_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
+ }
+ break;
+ default:
+ if (vfe31_ctrl->outpath.output_mode &
+ VFE31_OUTPUT_MODE_SECONDARY) {
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
+ } else if (vfe31_ctrl->outpath.output_mode &
+ VFE31_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
+ vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch2]);
+ }
+ break;
+ }
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
vfe31_start_common();
@@ -3582,11 +3573,11 @@
break;
case CMD_AXI_START:
- axi_start();
+ /* No need to decouple AXI/VFE for VFE3.1*/
break;
case CMD_AXI_STOP:
- axi_stop();
+ /* No need to decouple AXI/VFE for VFE3.1*/
break;
default:
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 98c1ca0..3611656 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -30,25 +30,24 @@
atomic_t irq_cnt;
#define VFE32_AXI_OFFSET 0x0050
-#define vfe32_get_ch_ping_addr(chn) \
- (msm_camera_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
-#define vfe32_get_ch_pong_addr(chn) \
- (msm_camera_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
-#define vfe32_get_ch_addr(ping_pong, chn) \
- (((ping_pong) & (1 << (chn))) == 0 ? \
- vfe32_get_ch_pong_addr(chn) : vfe32_get_ch_ping_addr(chn))
+#define vfe32_get_ch_ping_addr(base, chn) \
+ (msm_camera_io_r((base) + 0x0050 + 0x18 * (chn)))
+#define vfe32_get_ch_pong_addr(base, chn) \
+ (msm_camera_io_r((base) + 0x0050 + 0x18 * (chn) + 4))
+#define vfe32_get_ch_addr(ping_pong, base, chn) \
+ ((((ping_pong) & (1 << (chn))) == 0) ? \
+ (vfe32_get_ch_pong_addr((base), chn)) : \
+ (vfe32_get_ch_ping_addr((base), chn)))
-#define vfe32_put_ch_ping_addr(chn, addr) \
- (msm_camera_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
-#define vfe32_put_ch_pong_addr(chn, addr) \
- (msm_camera_io_w((addr), \
- vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
-#define vfe32_put_ch_addr(ping_pong, chn, addr) \
+#define vfe32_put_ch_ping_addr(base, chn, addr) \
+ (msm_camera_io_w((addr), (base) + 0x0050 + 0x18 * (chn)))
+#define vfe32_put_ch_pong_addr(base, chn, addr) \
+ (msm_camera_io_w((addr), (base) + 0x0050 + 0x18 * (chn) + 4))
+#define vfe32_put_ch_addr(ping_pong, base, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
- vfe32_put_ch_pong_addr((chn), (addr)) : \
- vfe32_put_ch_ping_addr((chn), (addr)))
+ vfe32_put_ch_pong_addr((base), (chn), (addr)) : \
+ vfe32_put_ch_ping_addr((base), (chn), (addr)))
-static struct vfe32_ctrl_type *vfe32_ctrl;
static uint32_t vfe_clk_rate;
struct vfe32_isr_queue_cmd {
@@ -357,112 +356,117 @@
"DEMOSAICV3_UPDATE",
};
-static void vfe32_stop(void)
+static void vfe32_stop(struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
- atomic_set(&vfe32_ctrl->vstate, 0);
+ atomic_set(&vfe32_ctrl->share_ctrl->vstate, 0);
/* for reset hw modules, and send msg when reset_irq comes.*/
- spin_lock_irqsave(&vfe32_ctrl->stop_flag_lock, flags);
- vfe32_ctrl->stop_ack_pending = TRUE;
- spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
+ spin_lock_irqsave(&vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
+ vfe32_ctrl->share_ctrl->stop_ack_pending = TRUE;
+ spin_unlock_irqrestore(&vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
/* disable all interrupts. */
msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_0);
msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_CLEAR_0);
msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
msm_camera_io_w_mb(1,
- vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_CMD);
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
msm_camera_io_w(CAMIF_COMMAND_STOP_IMMEDIATELY,
- vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
-
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
-static void vfe32_subdev_notify(int id, int path)
+static void vfe32_subdev_notify(int id, int path,
+ struct v4l2_subdev *sd, struct vfe_share_ctrl_t *share_ctrl)
{
struct msm_vfe_resp rp;
unsigned long flags = 0;
- spin_lock_irqsave(&vfe32_ctrl->sd_notify_lock, flags);
+ spin_lock_irqsave(&share_ctrl->sd_notify_lock, flags);
CDBG("vfe32_subdev_notify : msgId = %d\n", id);
memset(&rp, 0, sizeof(struct msm_vfe_resp));
rp.evt_msg.type = MSM_CAMERA_MSG;
rp.evt_msg.msg_id = path;
rp.type = id;
- v4l2_subdev_notify(&vfe32_ctrl->subdev, NOTIFY_VFE_BUF_EVT, &rp);
- spin_unlock_irqrestore(&vfe32_ctrl->sd_notify_lock, flags);
+ v4l2_subdev_notify(sd, NOTIFY_VFE_BUF_EVT, &rp);
+ spin_unlock_irqrestore(&share_ctrl->sd_notify_lock, flags);
}
-static int vfe32_config_axi(int mode, uint32_t *ao)
+static int vfe32_config_axi(
+ struct axi_ctrl_t *axi_ctrl, int mode, uint32_t *ao)
{
uint32_t *ch_info;
uint32_t *axi_cfg = ao+V32_AXI_BUS_FMT_OFF;
/* Update the corresponding write masters for each output*/
ch_info = axi_cfg + V32_AXI_CFG_LEN;
- vfe32_ctrl->outpath.out0.ch0 = 0x0000FFFF & *ch_info;
- vfe32_ctrl->outpath.out0.ch1 = 0x0000FFFF & (*ch_info++ >> 16);
- vfe32_ctrl->outpath.out0.ch2 = 0x0000FFFF & *ch_info++;
- vfe32_ctrl->outpath.out1.ch0 = 0x0000FFFF & *ch_info;
- vfe32_ctrl->outpath.out1.ch1 = 0x0000FFFF & (*ch_info++ >> 16);
- vfe32_ctrl->outpath.out1.ch2 = 0x0000FFFF & *ch_info++;
- vfe32_ctrl->outpath.out2.ch0 = 0x0000FFFF & *ch_info;
- vfe32_ctrl->outpath.out2.ch1 = 0x0000FFFF & (*ch_info++ >> 16);
- vfe32_ctrl->outpath.out2.ch2 = 0x0000FFFF & *ch_info++;
+ axi_ctrl->share_ctrl->outpath.out0.ch0 = 0x0000FFFF & *ch_info;
+ axi_ctrl->share_ctrl->outpath.out0.ch1 =
+ 0x0000FFFF & (*ch_info++ >> 16);
+ axi_ctrl->share_ctrl->outpath.out0.ch2 = 0x0000FFFF & *ch_info++;
+ axi_ctrl->share_ctrl->outpath.out1.ch0 = 0x0000FFFF & *ch_info;
+ axi_ctrl->share_ctrl->outpath.out1.ch1 =
+ 0x0000FFFF & (*ch_info++ >> 16);
+ axi_ctrl->share_ctrl->outpath.out1.ch2 = 0x0000FFFF & *ch_info++;
+ axi_ctrl->share_ctrl->outpath.out2.ch0 = 0x0000FFFF & *ch_info;
+ axi_ctrl->share_ctrl->outpath.out2.ch1 =
+ 0x0000FFFF & (*ch_info++ >> 16);
+ axi_ctrl->share_ctrl->outpath.out2.ch2 = 0x0000FFFF & *ch_info++;
switch (mode) {
case OUTPUT_PRIM:
- vfe32_ctrl->outpath.output_mode =
+ axi_ctrl->share_ctrl->outpath.output_mode =
VFE32_OUTPUT_MODE_PRIMARY;
break;
case OUTPUT_PRIM_ALL_CHNLS:
- vfe32_ctrl->outpath.output_mode =
+ axi_ctrl->share_ctrl->outpath.output_mode =
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS;
break;
case OUTPUT_PRIM|OUTPUT_SEC:
- vfe32_ctrl->outpath.output_mode =
+ axi_ctrl->share_ctrl->outpath.output_mode =
VFE32_OUTPUT_MODE_PRIMARY;
- vfe32_ctrl->outpath.output_mode |=
+ axi_ctrl->share_ctrl->outpath.output_mode |=
VFE32_OUTPUT_MODE_SECONDARY;
break;
case OUTPUT_PRIM|OUTPUT_SEC_ALL_CHNLS:
- vfe32_ctrl->outpath.output_mode =
+ axi_ctrl->share_ctrl->outpath.output_mode =
VFE32_OUTPUT_MODE_PRIMARY;
- vfe32_ctrl->outpath.output_mode |=
+ axi_ctrl->share_ctrl->outpath.output_mode |=
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS;
break;
case OUTPUT_PRIM_ALL_CHNLS|OUTPUT_SEC:
- vfe32_ctrl->outpath.output_mode =
+ axi_ctrl->share_ctrl->outpath.output_mode =
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS;
- vfe32_ctrl->outpath.output_mode |=
+ axi_ctrl->share_ctrl->outpath.output_mode |=
VFE32_OUTPUT_MODE_SECONDARY;
break;
default:
pr_err("%s Invalid AXI mode %d ", __func__, mode);
return -EINVAL;
}
- msm_camera_io_w(*ao, vfe32_ctrl->vfebase +
+ msm_camera_io_w(*ao, axi_ctrl->share_ctrl->vfebase +
VFE_BUS_IO_FORMAT_CFG);
- msm_camera_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(axi_ctrl->share_ctrl->vfebase +
vfe32_cmd[VFE_CMD_AXI_OUT_CFG].offset, axi_cfg,
vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length - V32_AXI_CH_INF_LEN
- V32_AXI_BUS_FMT_LEN);
return 0;
}
-static void vfe32_reset_internal_variables(void)
+static void vfe32_reset_internal_variables(
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
vfe32_ctrl->vfeImaskCompositePacked = 0;
@@ -470,9 +474,9 @@
vfe32_ctrl->start_ack_pending = FALSE;
atomic_set(&irq_cnt, 0);
- spin_lock_irqsave(&vfe32_ctrl->stop_flag_lock, flags);
- vfe32_ctrl->stop_ack_pending = FALSE;
- spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
+ spin_lock_irqsave(&vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
+ vfe32_ctrl->share_ctrl->stop_ack_pending = FALSE;
+ spin_unlock_irqrestore(&vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
vfe32_ctrl->reset_ack_pending = FALSE;
@@ -481,17 +485,17 @@
spin_unlock_irqrestore(&vfe32_ctrl->update_ack_lock, flags);
vfe32_ctrl->recording_state = VFE_STATE_IDLE;
- vfe32_ctrl->liveshot_state = VFE_STATE_IDLE;
+ vfe32_ctrl->share_ctrl->liveshot_state = VFE_STATE_IDLE;
- atomic_set(&vfe32_ctrl->vstate, 0);
+ atomic_set(&vfe32_ctrl->share_ctrl->vstate, 0);
/* 0 for continuous mode, 1 for snapshot mode */
- vfe32_ctrl->operation_mode = 0;
- vfe32_ctrl->outpath.output_mode = 0;
- vfe32_ctrl->vfe_capture_count = 0;
+ vfe32_ctrl->share_ctrl->operation_mode = 0;
+ vfe32_ctrl->share_ctrl->outpath.output_mode = 0;
+ vfe32_ctrl->share_ctrl->vfe_capture_count = 0;
/* this is unsigned 32 bit integer. */
- vfe32_ctrl->vfeFrameId = 0;
+ vfe32_ctrl->share_ctrl->vfeFrameId = 0;
/* Stats control variables. */
memset(&(vfe32_ctrl->afStatsControl), 0,
sizeof(struct vfe_stats_control));
@@ -516,30 +520,30 @@
vfe32_ctrl->snapshot_frame_cnt = 0;
}
-static void vfe32_reset(void)
+static void vfe32_reset(struct vfe32_ctrl_type *vfe32_ctrl)
{
- vfe32_reset_internal_variables();
+ vfe32_reset_internal_variables(vfe32_ctrl);
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_0);
msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_CLEAR_0);
msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
- vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
* is done, hardware interrupt will be generated. VFE ist processes
@@ -549,409 +553,516 @@
/* Ensure the write order while writing
to the command register using the barrier */
msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
- vfe32_ctrl->vfebase + VFE_GLOBAL_RESET);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_GLOBAL_RESET);
}
-static int vfe32_operation_config(uint32_t *cmd)
+static int vfe32_operation_config(uint32_t *cmd,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t *p = cmd;
- vfe32_ctrl->operation_mode = *p;
- vfe32_ctrl->stats_comp = *(++p);
+ vfe32_ctrl->share_ctrl->operation_mode = *p;
+ vfe32_ctrl->share_ctrl->stats_comp = *(++p);
vfe32_ctrl->hfr_mode = *(++p);
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CFG);
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_PIXEL_IF_CFG);
- if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CFG);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_PIXEL_IF_CFG);
+ if (msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
+ V32_GET_HW_VERSION_OFF) ==
VFE33_HW_NUMBER) {
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI0_CFG);
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI1_CFG);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_RDI0_CFG);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_RDI1_CFG);
} else {
++p;
++p;
}
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CHROMA_UP);
- msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p),
+ vfe32_ctrl->share_ctrl->vfebase + VFE_STATS_CFG);
return 0;
}
-static uint32_t vfe_stats_awb_buf_init(struct vfe_cmd_stats_buf *in)
+static uint32_t vfe_stats_awb_buf_init(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_buf *in)
{
uint32_t *ptr = in->statsBuf;
uint32_t addr;
addr = ptr[0];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe32_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static uint32_t vfe_stats_aec_buf_init(struct vfe_cmd_stats_buf *in)
+static uint32_t vfe_stats_aec_buf_init(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_buf *in)
{
uint32_t *ptr = in->statsBuf;
uint32_t addr;
addr = ptr[0];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe32_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static uint32_t vfe_stats_af_buf_init(struct vfe_cmd_stats_buf *in)
+static uint32_t vfe_stats_af_buf_init(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_buf *in)
{
uint32_t *ptr = in->statsBuf;
uint32_t addr;
addr = ptr[0];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe32_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static uint32_t vfe_stats_ihist_buf_init(struct vfe_cmd_stats_buf *in)
+static uint32_t vfe_stats_ihist_buf_init(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_buf *in)
{
uint32_t *ptr = in->statsBuf;
uint32_t addr;
addr = ptr[0];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe32_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static uint32_t vfe_stats_rs_buf_init(struct vfe_cmd_stats_buf *in)
+static uint32_t vfe_stats_rs_buf_init(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_buf *in)
{
uint32_t *ptr = in->statsBuf;
uint32_t addr;
addr = ptr[0];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe32_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static uint32_t vfe_stats_cs_buf_init(struct vfe_cmd_stats_buf *in)
+static uint32_t vfe_stats_cs_buf_init(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_buf *in)
{
uint32_t *ptr = in->statsBuf;
uint32_t addr;
addr = ptr[0];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
msm_camera_io_w(addr,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe32_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static void vfe32_start_common(void)
+static void vfe32_start_common(struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t irq_mask = 0x00E00021;
vfe32_ctrl->start_ack_pending = TRUE;
CDBG("VFE opertaion mode = 0x%x, output mode = 0x%x\n",
- vfe32_ctrl->operation_mode, vfe32_ctrl->outpath.output_mode);
- if (vfe32_ctrl->stats_comp)
+ vfe32_ctrl->share_ctrl->operation_mode,
+ vfe32_ctrl->share_ctrl->outpath.output_mode);
+ if (vfe32_ctrl->share_ctrl->stats_comp)
irq_mask |= VFE_IRQ_STATUS0_STATS_COMPOSIT_MASK;
else
irq_mask |= 0x000FE000;
- msm_camera_io_w(irq_mask, vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(irq_mask,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_0);
msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CAMIF_COMMAND);
-
- atomic_set(&vfe32_ctrl->vstate, 1);
+ atomic_set(&vfe32_ctrl->share_ctrl->vstate, 1);
}
-static int vfe32_start_recording(struct msm_cam_media_controller *pmctl)
+static int vfe32_start_recording(
+ struct msm_cam_media_controller *pmctl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_VIDEO);
vfe32_ctrl->recording_state = VFE_STATE_START_REQUESTED;
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
-static int vfe32_stop_recording(struct msm_cam_media_controller *pmctl)
+static int vfe32_stop_recording(
+ struct msm_cam_media_controller *pmctl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
vfe32_ctrl->recording_state = VFE_STATE_STOP_REQUESTED;
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
return 0;
}
-static void vfe32_start_liveshot(struct msm_cam_media_controller *pmctl)
+static void vfe32_start_liveshot(
+ struct msm_cam_media_controller *pmctl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
/* Hardcode 1 live snapshot for now. */
- vfe32_ctrl->outpath.out0.capture_cnt = 1;
- vfe32_ctrl->vfe_capture_count = vfe32_ctrl->outpath.out0.capture_cnt;
+ vfe32_ctrl->share_ctrl->outpath.out0.capture_cnt = 1;
+ vfe32_ctrl->share_ctrl->vfe_capture_count =
+ vfe32_ctrl->share_ctrl->outpath.out0.capture_cnt;
- vfe32_ctrl->liveshot_state = VFE_STATE_START_REQUESTED;
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ vfe32_ctrl->share_ctrl->liveshot_state = VFE_STATE_START_REQUESTED;
+ msm_camera_io_w_mb(1, vfe32_ctrl->
+ share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
}
-static int vfe32_zsl(struct msm_cam_media_controller *pmctl)
+static int vfe32_zsl(
+ struct msm_cam_media_controller *pmctl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->
+ share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
- vfe32_ctrl->operation_mode, vfe32_ctrl->outpath.output_mode);
+ vfe32_ctrl->share_ctrl->operation_mode,
+ vfe32_ctrl->share_ctrl->outpath.output_mode);
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
- irq_comp_mask |= ((0x1 << (vfe32_ctrl->outpath.out0.ch0)) |
- (0x1 << (vfe32_ctrl->outpath.out0.ch1)));
- } else if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_PRIMARY) {
+ irq_comp_mask |= (
+ (0x1 << (vfe32_ctrl->share_ctrl->outpath.out0.ch0)) |
+ (0x1 << (vfe32_ctrl->share_ctrl->outpath.out0.ch1)));
+ } else if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- irq_comp_mask |= ((0x1 << (vfe32_ctrl->outpath.out0.ch0)) |
- (0x1 << (vfe32_ctrl->outpath.out0.ch1)) |
- (0x1 << (vfe32_ctrl->outpath.out0.ch2)));
+ irq_comp_mask |= (
+ (0x1 << (vfe32_ctrl->share_ctrl->outpath.out0.ch0)) |
+ (0x1 << (vfe32_ctrl->share_ctrl->outpath.out0.ch1)) |
+ (0x1 << (vfe32_ctrl->share_ctrl->outpath.out0.ch2)));
}
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_SECONDARY) {
- irq_comp_mask |= ((0x1 << (vfe32_ctrl->outpath.out1.ch0 + 8)) |
- (0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8)));
- } else if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_SECONDARY) {
+ irq_comp_mask |= ((0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0 + 8)) |
+ (0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1 + 8)));
+ } else if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- irq_comp_mask |= ((0x1 << (vfe32_ctrl->outpath.out1.ch0 + 8)) |
- (0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8)) |
- (0x1 << (vfe32_ctrl->outpath.out1.ch2 + 8)));
+ irq_comp_mask |= (
+ (0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0 + 8)) |
+ (0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1 + 8)) |
+ (0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch2 + 8)));
}
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- } else if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_PRIMARY) {
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ } else if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch2]);
}
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_SECONDARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- } else if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_SECONDARY) {
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1]);
+ } else if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch2]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch2]);
}
- msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- vfe32_start_common();
+ msm_camera_io_w(irq_comp_mask,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ vfe32_start_common(vfe32_ctrl);
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_ZSL);
- msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x18C);
- msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase + 0x188);
return 0;
}
static int vfe32_capture_raw(
struct msm_cam_media_controller *pmctl,
+ struct vfe32_ctrl_type *vfe32_ctrl,
uint32_t num_frames_capture)
{
uint32_t irq_comp_mask = 0;
- vfe32_ctrl->outpath.out0.capture_cnt = num_frames_capture;
- vfe32_ctrl->vfe_capture_count = num_frames_capture;
+ vfe32_ctrl->share_ctrl->outpath.out0.capture_cnt = num_frames_capture;
+ vfe32_ctrl->share_ctrl->vfe_capture_count = num_frames_capture;
irq_comp_mask =
- msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
- irq_comp_mask |= (0x1 << (vfe32_ctrl->outpath.out0.ch0));
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_PRIMARY) {
+ irq_comp_mask |=
+ (0x1 << (vfe32_ctrl->share_ctrl->outpath.out0.ch0));
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
}
- msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
- vfe32_start_common();
+ vfe32_start_common(vfe32_ctrl);
return 0;
}
static int vfe32_capture(
struct msm_cam_media_controller *pmctl,
- uint32_t num_frames_capture)
+ uint32_t num_frames_capture,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
- vfe32_ctrl->outpath.out1.capture_cnt = num_frames_capture;
- if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG) {
- vfe32_ctrl->outpath.out0.capture_cnt =
+ vfe32_ctrl->share_ctrl->outpath.out1.capture_cnt = num_frames_capture;
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_MAIN_AND_THUMB ||
+ vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_MAIN ||
+ vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_JPEG) {
+ vfe32_ctrl->share_ctrl->outpath.out0.capture_cnt =
num_frames_capture;
}
- vfe32_ctrl->vfe_capture_count = num_frames_capture;
+ vfe32_ctrl->share_ctrl->vfe_capture_count = num_frames_capture;
irq_comp_mask = msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN) {
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_MAIN_AND_THUMB ||
+ vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_MAIN) {
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
- 0x1 << vfe32_ctrl->outpath.out0.ch1);
+ irq_comp_mask |= (0x1 << vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0 |
+ 0x1 << vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1);
}
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
irq_comp_mask |=
- (0x1 << (vfe32_ctrl->outpath.out1.ch0 + 8) |
- 0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8));
+ (0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0 + 8) |
+ 0x1 << (vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1 + 8));
}
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
}
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1]);
}
}
- vfe32_ctrl->vfe_capture_count = num_frames_capture;
+ vfe32_ctrl->share_ctrl->vfe_capture_count = num_frames_capture;
- msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
- vfe32_start_common();
+ vfe32_start_common(vfe32_ctrl);
/* for debug */
- msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x18C);
- msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase + 0x188);
return 0;
}
-static int vfe32_start(struct msm_cam_media_controller *pmctl)
+static int vfe32_start(
+ struct msm_cam_media_controller *pmctl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t irq_comp_mask = 0;
irq_comp_mask =
- msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
+ VFE_IRQ_COMP_MASK);
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
- irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
- 0x1 << vfe32_ctrl->outpath.out0.ch1);
- } else if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_PRIMARY) {
+ irq_comp_mask |= (
+ 0x1 << vfe32_ctrl->share_ctrl->outpath.out0.ch0 |
+ 0x1 << vfe32_ctrl->share_ctrl->outpath.out0.ch1);
+ } else if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
- 0x1 << vfe32_ctrl->outpath.out0.ch1 |
- 0x1 << vfe32_ctrl->outpath.out0.ch2);
+ irq_comp_mask |= (
+ 0x1 << vfe32_ctrl->share_ctrl->outpath.out0.ch0 |
+ 0x1 << vfe32_ctrl->share_ctrl->outpath.out0.ch1 |
+ 0x1 << vfe32_ctrl->share_ctrl->outpath.out0.ch2);
}
- if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_SECONDARY) {
- irq_comp_mask |= (0x1 << (vfe32_ctrl->outpath.out1.ch0 + 8) |
- 0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8));
- } else if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
+ VFE32_OUTPUT_MODE_SECONDARY) {
+ irq_comp_mask |= (
+ 0x1 << (vfe32_ctrl->share_ctrl->outpath.out1.ch0 + 8) |
+ 0x1 << (vfe32_ctrl->share_ctrl->outpath.out1.ch1 + 8));
+ } else if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- irq_comp_mask |= (0x1 << (vfe32_ctrl->outpath.out1.ch0 + 8) |
- 0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8) |
- 0x1 << (vfe32_ctrl->outpath.out1.ch2 + 8));
+ irq_comp_mask |= (
+ 0x1 << (vfe32_ctrl->share_ctrl->outpath.out1.ch0 + 8) |
+ 0x1 << (vfe32_ctrl->share_ctrl->outpath.out1.ch1 + 8) |
+ 0x1 << (vfe32_ctrl->share_ctrl->outpath.out1.ch2 + 8));
}
- msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
- vfe32_start_common();
+ vfe32_start_common(vfe32_ctrl);
return 0;
}
-static void vfe32_update(void)
+static void vfe32_update(struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
uint32_t value = 0;
if (vfe32_ctrl->update_linear) {
if (!msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1))
msm_camera_io_w(1,
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1);
else
msm_camera_io_w(0,
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1);
vfe32_ctrl->update_linear = false;
}
if (vfe32_ctrl->update_rolloff) {
- value = msm_camera_io_r(vfe32_ctrl->vfebase +
+ value = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1);
value ^= V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
- msm_camera_io_w(value, vfe32_ctrl->vfebase +
+ msm_camera_io_w(value, vfe32_ctrl->share_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1);
vfe32_ctrl->update_rolloff = false;
}
if (vfe32_ctrl->update_la) {
- if (!msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ if (!msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + V32_LA_OFF))
msm_camera_io_w(1,
- vfe32_ctrl->vfebase + V32_LA_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_LA_OFF);
else
msm_camera_io_w(0,
- vfe32_ctrl->vfebase + V32_LA_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_LA_OFF);
vfe32_ctrl->update_la = false;
}
if (vfe32_ctrl->update_gamma) {
- value = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ value = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + V32_RGB_G_OFF);
value ^= V32_GAMMA_LUT_BANK_SEL_MASK;
- msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ msm_camera_io_w(value,
+ vfe32_ctrl->share_ctrl->vfebase + V32_RGB_G_OFF);
vfe32_ctrl->update_gamma = false;
}
@@ -960,11 +1071,12 @@
spin_unlock_irqrestore(&vfe32_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
-static void vfe32_sync_timer_stop(void)
+static void vfe32_sync_timer_stop(struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t value = 0;
vfe32_ctrl->sync_timer_state = 0;
@@ -976,10 +1088,13 @@
value = 0x40000;
/* Timer Stop */
- msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
+ msm_camera_io_w(value,
+ vfe32_ctrl->share_ctrl->vfebase + V32_SYNC_TIMER_OFF);
}
-static void vfe32_sync_timer_start(const uint32_t *tbl)
+static void vfe32_sync_timer_start(
+ const uint32_t *tbl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
/* set bit 8 for auto increment. */
uint32_t value = 1;
@@ -1001,14 +1116,17 @@
}
/* Timer Start */
- msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
+ msm_camera_io_w(value,
+ vfe32_ctrl->share_ctrl->vfebase + V32_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(value,
+ vfe32_ctrl->share_ctrl->vfebase + V32_SYNC_TIMER_OFF +
4 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(value,
+ vfe32_ctrl->share_ctrl->vfebase + V32_SYNC_TIMER_OFF +
8 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
@@ -1016,87 +1134,99 @@
val = 10000000 / val;
val = value * 10000 / val;
CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
- msm_camera_io_w(val, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(val,
+ vfe32_ctrl->share_ctrl->vfebase + V32_SYNC_TIMER_OFF +
12 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
msm_camera_io_w(value,
- vfe32_ctrl->vfebase + V32_SYNC_TIMER_POLARITY_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_TIMER_SELECT_OFF);
+ msm_camera_io_w(value,
+ vfe32_ctrl->share_ctrl->vfebase + V32_TIMER_SELECT_OFF);
}
-static void vfe32_program_dmi_cfg(enum VFE32_DMI_RAM_SEL bankSel)
+static void vfe32_program_dmi_cfg(
+ enum VFE32_DMI_RAM_SEL bankSel,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
/* set bit 8 for auto increment. */
uint32_t value = VFE_DMI_CFG_DEFAULT;
value += (uint32_t)bankSel;
CDBG("%s: banksel = %d\n", __func__, bankSel);
- msm_camera_io_w(value, vfe32_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w(value, vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_camera_io_w(0, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
}
-static void vfe32_write_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
- const uint32_t *tbl)
+static void vfe32_write_gamma_cfg(
+ enum VFE32_DMI_RAM_SEL channel_sel,
+ const uint32_t *tbl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
int i;
uint32_t value, value1, value2;
- vfe32_program_dmi_cfg(channel_sel);
+ vfe32_program_dmi_cfg(channel_sel, vfe32_ctrl);
for (i = 0 ; i < (VFE32_GAMMA_NUM_ENTRIES/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
msm_camera_io_w((value1),
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
msm_camera_io_w((value2),
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
}
-static void vfe32_read_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
- uint32_t *tbl)
+static void vfe32_read_gamma_cfg(
+ enum VFE32_DMI_RAM_SEL channel_sel,
+ uint32_t *tbl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
int i;
- vfe32_program_dmi_cfg(channel_sel);
+ vfe32_program_dmi_cfg(channel_sel, vfe32_ctrl);
CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
for (i = 0 ; i < VFE32_GAMMA_NUM_ENTRIES ; i++) {
- *tbl = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *tbl = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *tbl);
tbl++;
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
}
-static void vfe32_write_la_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
- const uint32_t *tbl)
+static void vfe32_write_la_cfg(
+ enum VFE32_DMI_RAM_SEL channel_sel,
+ const uint32_t *tbl,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t i;
uint32_t value, value1, value2;
- vfe32_program_dmi_cfg(channel_sel);
+ vfe32_program_dmi_cfg(channel_sel, vfe32_ctrl);
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
msm_camera_io_w((value1),
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
msm_camera_io_w((value2),
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
}
-static struct vfe32_output_ch *vfe32_get_ch(int path)
+static struct vfe32_output_ch *vfe32_get_ch(
+ int path, struct vfe_share_ctrl_t *share_ctrl)
{
struct vfe32_output_ch *ch = NULL;
if (path == VFE_MSG_OUTPUT_PRIMARY)
- ch = &vfe32_ctrl->outpath.out0;
+ ch = &share_ctrl->outpath.out0;
else if (path == VFE_MSG_OUTPUT_SECONDARY)
- ch = &vfe32_ctrl->outpath.out1;
+ ch = &share_ctrl->outpath.out1;
else
pr_err("%s: Invalid path %d\n", __func__,
path);
@@ -1104,44 +1234,54 @@
BUG_ON(ch == NULL);
return ch;
}
-static struct msm_free_buf *vfe32_check_free_buffer(int id, int path)
+static struct msm_free_buf *vfe32_check_free_buffer(
+ int id, int path, struct axi_ctrl_t *axi_ctrl)
{
struct vfe32_output_ch *outch = NULL;
struct msm_free_buf *b = NULL;
- vfe32_subdev_notify(id, path);
- outch = vfe32_get_ch(path);
+ vfe32_subdev_notify(id, path,
+ &axi_ctrl->subdev, axi_ctrl->share_ctrl);
+ outch = vfe32_get_ch(path, axi_ctrl->share_ctrl);
if (outch->free_buf.ch_paddr[0])
b = &outch->free_buf;
return b;
}
-static int vfe32_configure_pingpong_buffers(int id, int path)
+static int vfe32_configure_pingpong_buffers(
+ int id, int path, struct vfe32_ctrl_type *vfe32_ctrl)
{
struct vfe32_output_ch *outch = NULL;
int rc = 0;
- vfe32_subdev_notify(id, path);
- outch = vfe32_get_ch(path);
+ vfe32_subdev_notify(id, path,
+ &vfe32_ctrl->subdev, vfe32_ctrl->share_ctrl);
+ outch = vfe32_get_ch(path, vfe32_ctrl->share_ctrl);
if (outch->ping.ch_paddr[0] && outch->pong.ch_paddr[0]) {
/* Configure Preview Ping Pong */
pr_info("%s Configure ping/pong address for %d",
__func__, path);
- vfe32_put_ch_ping_addr(outch->ch0,
+ vfe32_put_ch_ping_addr(
+ vfe32_ctrl->share_ctrl->vfebase, outch->ch0,
outch->ping.ch_paddr[0]);
- vfe32_put_ch_pong_addr(outch->ch0,
+ vfe32_put_ch_pong_addr(
+ vfe32_ctrl->share_ctrl->vfebase, outch->ch0,
outch->pong.ch_paddr[0]);
- if (vfe32_ctrl->operation_mode !=
+ if (vfe32_ctrl->share_ctrl->operation_mode !=
VFE_OUTPUTS_RAW) {
- vfe32_put_ch_ping_addr(outch->ch1,
+ vfe32_put_ch_ping_addr(
+ vfe32_ctrl->share_ctrl->vfebase, outch->ch1,
outch->ping.ch_paddr[1]);
- vfe32_put_ch_pong_addr(outch->ch1,
+ vfe32_put_ch_pong_addr(
+ vfe32_ctrl->share_ctrl->vfebase, outch->ch1,
outch->pong.ch_paddr[1]);
}
if (outch->ping.num_planes > 2)
- vfe32_put_ch_ping_addr(outch->ch2,
+ vfe32_put_ch_ping_addr(
+ vfe32_ctrl->share_ctrl->vfebase, outch->ch2,
outch->ping.ch_paddr[2]);
if (outch->pong.num_planes > 2)
- vfe32_put_ch_pong_addr(outch->ch2,
+ vfe32_put_ch_pong_addr(
+ vfe32_ctrl->share_ctrl->vfebase, outch->ch2,
outch->pong.ch_paddr[2]);
/* avoid stale info */
@@ -1154,37 +1294,41 @@
return rc;
}
-static void vfe32_write_linear_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
- const uint32_t *tbl)
+static void vfe32_write_linear_cfg(
+ enum VFE32_DMI_RAM_SEL channel_sel,
+ const uint32_t *tbl, struct vfe32_ctrl_type *vfe32_ctrl)
{
uint32_t i;
- vfe32_program_dmi_cfg(channel_sel);
+ vfe32_program_dmi_cfg(channel_sel, vfe32_ctrl);
/* for loop for configuring LUT. */
for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
- msm_camera_io_w(*tbl, vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w(*tbl,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
tbl++;
}
CDBG("done writing to linearization table\n");
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
}
static void vfe32_send_isp_msg(
- struct vfe32_ctrl_type *vctrl,
+ struct v4l2_subdev *sd,
+ uint32_t vfeFrameId,
uint32_t isp_msg_id)
{
struct isp_msg_event isp_msg_evt;
isp_msg_evt.msg_id = isp_msg_id;
- isp_msg_evt.sof_count = vfe32_ctrl->vfeFrameId;
- v4l2_subdev_notify(&vctrl->subdev,
+ isp_msg_evt.sof_count = vfeFrameId;
+ v4l2_subdev_notify(sd,
NOTIFY_ISP_MSG_EVT,
(void *)&isp_msg_evt);
}
static int vfe32_proc_general(
struct msm_cam_media_controller *pmctl,
- struct msm_isp_cmd *cmd)
+ struct msm_isp_cmd *cmd,
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
int i , rc = 0;
uint32_t old_val = 0 , new_val = 0;
@@ -1199,32 +1343,34 @@
case VFE_CMD_RESET:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
- vfe32_reset();
+ vfe32_reset(vfe32_ctrl);
break;
case VFE_CMD_START:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
- if ((vfe32_ctrl->operation_mode ==
+ if ((vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) ||
- (vfe32_ctrl->operation_mode ==
+ (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW))
/* Configure primary channel */
rc = vfe32_configure_pingpong_buffers(
- VFE_MSG_V32_START, VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_V32_START, VFE_MSG_OUTPUT_PRIMARY,
+ vfe32_ctrl);
else
/* Configure secondary channel */
rc = vfe32_configure_pingpong_buffers(
- VFE_MSG_V32_START, VFE_MSG_OUTPUT_SECONDARY);
+ VFE_MSG_V32_START, VFE_MSG_OUTPUT_SECONDARY,
+ vfe32_ctrl);
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
" for preview", __func__);
rc = -EINVAL;
goto proc_general_done;
}
- rc = vfe32_start(pmctl);
+ rc = vfe32_start(pmctl, vfe32_ctrl);
break;
case VFE_CMD_UPDATE:
- vfe32_update();
+ vfe32_update(vfe32_ctrl);
break;
case VFE_CMD_CAPTURE_RAW:
pr_info("%s: cmdID = VFE_CMD_CAPTURE_RAW\n", __func__);
@@ -1233,15 +1379,16 @@
rc = -EFAULT;
goto proc_general_done;
}
- rc = vfe32_configure_pingpong_buffers(VFE_MSG_V32_CAPTURE,
- VFE_MSG_OUTPUT_PRIMARY);
+ rc = vfe32_configure_pingpong_buffers(
+ VFE_MSG_V32_CAPTURE, VFE_MSG_OUTPUT_PRIMARY,
+ vfe32_ctrl);
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
" for snapshot", __func__);
rc = -EINVAL;
goto proc_general_done;
}
- rc = vfe32_capture_raw(pmctl, snapshot_cnt);
+ rc = vfe32_capture_raw(pmctl, vfe32_ctrl, snapshot_cnt);
break;
case VFE_CMD_CAPTURE:
if (copy_from_user(&snapshot_cnt, (void __user *)(cmd->value),
@@ -1250,8 +1397,10 @@
goto proc_general_done;
}
- if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG) {
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_JPEG) {
if (snapshot_cnt != 1) {
pr_err("only support 1 inline snapshot\n");
rc = -EINVAL;
@@ -1260,12 +1409,14 @@
/* Configure primary channel for JPEG */
rc = vfe32_configure_pingpong_buffers(
VFE_MSG_V32_JPEG_CAPTURE,
- VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_OUTPUT_PRIMARY,
+ vfe32_ctrl);
} else {
/* Configure primary channel */
rc = vfe32_configure_pingpong_buffers(
VFE_MSG_V32_CAPTURE,
- VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_OUTPUT_PRIMARY,
+ vfe32_ctrl);
}
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
@@ -1274,41 +1425,44 @@
goto proc_general_done;
}
/* Configure secondary channel */
- rc = vfe32_configure_pingpong_buffers(VFE_MSG_V32_CAPTURE,
- VFE_MSG_OUTPUT_SECONDARY);
+ rc = vfe32_configure_pingpong_buffers(
+ VFE_MSG_V32_CAPTURE, VFE_MSG_OUTPUT_SECONDARY,
+ vfe32_ctrl);
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
" for secondary output", __func__);
rc = -EINVAL;
goto proc_general_done;
}
- rc = vfe32_capture(pmctl, snapshot_cnt);
+ rc = vfe32_capture(pmctl, snapshot_cnt, vfe32_ctrl);
break;
case VFE_CMD_START_RECORDING:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
- if (vfe32_ctrl->operation_mode ==
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO)
rc = vfe32_configure_pingpong_buffers(
VFE_MSG_V32_START_RECORDING,
- VFE_MSG_OUTPUT_SECONDARY);
- else if (vfe32_ctrl->operation_mode ==
+ VFE_MSG_OUTPUT_SECONDARY,
+ vfe32_ctrl);
+ else if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW)
rc = vfe32_configure_pingpong_buffers(
VFE_MSG_V32_START_RECORDING,
- VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_OUTPUT_PRIMARY,
+ vfe32_ctrl);
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
" for video", __func__);
rc = -EINVAL;
goto proc_general_done;
}
- rc = vfe32_start_recording(pmctl);
+ rc = vfe32_start_recording(pmctl, vfe32_ctrl);
break;
case VFE_CMD_STOP_RECORDING:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
- rc = vfe32_stop_recording(pmctl);
+ rc = vfe32_stop_recording(pmctl, vfe32_ctrl);
break;
case VFE_CMD_OPERATION_CFG: {
if (cmd->length != V32_OPERATION_CFG_LEN) {
@@ -1322,7 +1476,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- rc = vfe32_operation_config(cmdp);
+ rc = vfe32_operation_config(cmdp, vfe32_ctrl);
}
break;
@@ -1338,12 +1492,14 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_BG_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1359,12 +1515,14 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
+ VFE_MODULE_CFG);
old_val |= AF_BF_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1380,12 +1538,14 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1402,12 +1562,14 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1426,7 +1588,8 @@
goto proc_general_done;
}
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1444,7 +1607,8 @@
goto proc_general_done;
}
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1454,7 +1618,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1471,21 +1635,22 @@
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
- &new_val, 4);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_CHROMA_SUP_OFF + 4, &new_val, 4);
cmdp_local += 1;
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
- &new_val, 4);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_CHROMA_SUP_OFF + 8, &new_val, 4);
cmdp_local += 1;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1503,31 +1668,31 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF,
- cmdp_local, 4);
+ msm_camera_io_memcpy(vfe32_ctrl->share_ctrl->vfebase +
+ V32_CHROMA_SUP_OFF, cmdp_local, 4);
cmdp_local += 1;
new_val = *cmdp_local;
/* Incrementing with 4 so as to point to the 2nd Register as
* the 2nd register has the mce_enable bit
*/
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 4);
old_val &= ~MCE_EN_MASK;
new_val = new_val | old_val;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
- &new_val, 4);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_CHROMA_SUP_OFF + 4, &new_val, 4);
cmdp_local += 1;
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= ~MCE_Q_K_MASK;
new_val = new_val | old_val;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
- &new_val, 4);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_CHROMA_SUP_OFF + 8, &new_val, 4);
}
break;
case VFE_CMD_BLACK_LEVEL_CFG:
@@ -1547,27 +1712,28 @@
}
cmdp_local = cmdp;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp_local, 16);
cmdp_local += 4;
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0, vfe32_ctrl);
/* for loop for extrcting init table. */
for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
msm_camera_io_w(*cmdp_local ,
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
msm_camera_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
- vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
msm_camera_io_w(*cmdp_local,
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
}
break;
@@ -1584,27 +1750,29 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0, vfe32_ctrl);
CDBG("%s: Mesh Rolloff init Table\n", __func__);
for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
*cmdp_local =
msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
msm_camera_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
- vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
*cmdp_local =
msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
CDBG("done reading delta table\n");
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
if (copy_to_user((void __user *)(cmd->value), cmdp,
temp1)) {
rc = -EFAULT;
@@ -1626,11 +1794,13 @@
}
cmdp_local = cmdp;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
cmdp_local += 1;
- vfe32_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0, cmdp_local);
+ vfe32_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
+ cmdp_local, vfe32_ctrl);
break;
case VFE_CMD_LA_UPDATE: {
@@ -1648,13 +1818,14 @@
}
cmdp_local = cmdp + 1;
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + V32_LA_OFF);
if (old_val != 0x0)
vfe32_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
- cmdp_local);
+ cmdp_local, vfe32_ctrl);
else
vfe32_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK1,
- cmdp_local);
+ cmdp_local, vfe32_ctrl);
}
vfe32_ctrl->update_la = true;
break;
@@ -1671,19 +1842,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
- vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
+ if (msm_camera_io_r(vfe32_ctrl->
+ share_ctrl->vfebase + V32_LA_OFF))
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1,
+ vfe32_ctrl);
else
- vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
+ vfe32_ctrl);
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH / 2) ; i++) {
*cmdp_local =
msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- *cmdp_local |= (msm_camera_io_r(vfe32_ctrl->vfebase +
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase +
VFE_DMI_DATA_LO)) << 16;
cmdp_local++;
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
if (copy_to_user((void __user *)(cmd->value), cmdp,
temp1)) {
rc = -EFAULT;
@@ -1703,22 +1879,23 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_SCE_OFF,
- cmdp, V32_SCE_LEN);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_SCE_OFF,
+ cmdp, V32_SCE_LEN);
}
break;
case VFE_CMD_LIVESHOT:
/* Configure primary channel */
rc = vfe32_configure_pingpong_buffers(VFE_MSG_V32_CAPTURE,
- VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_OUTPUT_PRIMARY, vfe32_ctrl);
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
" for primary output", __func__);
rc = -EINVAL;
goto proc_general_done;
}
- vfe32_start_liveshot(pmctl);
+ vfe32_start_liveshot(pmctl, vfe32_ctrl);
break;
case VFE_CMD_LINEARIZATION_CFG:
@@ -1734,15 +1911,18 @@
}
cmdp_local = cmdp;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1,
cmdp_local, V32_LINEARIZATION_LEN1);
cmdp_local += 4;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF2,
cmdp_local, V32_LINEARIZATION_LEN2);
cmdp_local = cmdp + 17;
- vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
+ vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0,
+ cmdp_local, vfe32_ctrl);
break;
case VFE_CMD_LINEARIZATION_UPDATE:
@@ -1759,21 +1939,26 @@
cmdp_local = cmdp;
cmdp_local++;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1 + 4,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1 + 4,
cmdp_local, (V32_LINEARIZATION_LEN1 - 4));
cmdp_local += 3;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF2,
cmdp_local, V32_LINEARIZATION_LEN2);
cmdp_local = cmdp + 17;
/*extracting the bank select*/
old_val = msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1);
if (old_val != 0x0)
- vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
+ vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0,
+ cmdp_local, vfe32_ctrl);
else
- vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK1, cmdp_local);
+ vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK1,
+ cmdp_local, vfe32_ctrl);
vfe32_ctrl->update_linear = true;
break;
@@ -1790,18 +1975,20 @@
}
cmdp_local = cmdp;
if (msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
- vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1);
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_LINEARIZATION_OFF1))
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1, vfe32_ctrl);
else
- vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0);
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0, vfe32_ctrl);
CDBG("%s: Linearization Table\n", __func__);
for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
*cmdp_local = msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
if (copy_to_user((void __user *)(cmd->value), cmdp,
temp1)) {
rc = -EFAULT;
@@ -1829,15 +2016,17 @@
new_val = *cmdp_local;
old_val = msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
cmdp_local += 1;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
cmdp_local, V32_DEMOSAICV3_1_LEN);
break;
@@ -1862,22 +2051,25 @@
new_val = *cmdp_local;
old_val = msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
/* As the address space is not contiguous increment by 2
* before copying to next address space */
cmdp_local += 1;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
/* As the address space is not contiguous increment by 2
* before copying to next address space */
cmdp_local += 2;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
break;
@@ -1902,17 +2094,19 @@
new_val = *cmdp_local;
old_val = msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
- cmdp_local, 4);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ cmdp_local, 4);
cmdp_local += 1;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1934,16 +2128,18 @@
new_val = *cmdp_local;
old_val = msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DBCC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
- cmdp_local, 4);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ cmdp_local, 4);
cmdp_local += 1;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
break;
@@ -1964,28 +2160,28 @@
new_val = *cmdp_local;
old_val = msm_camera_io_r(
- vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ vfe32_ctrl->share_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DBPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->share_ctrl->vfebase +
V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_LEN);
cmdp_local += 1;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->share_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->share_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF0,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->share_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF1,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_camera_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->share_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF2,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
break;
@@ -2002,13 +2198,14 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_RGB_G_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->share_ctrl->vfebase + V32_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp);
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH1_BANK0, cmdp);
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH2_BANK0, cmdp);
+ vfe32_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp, vfe32_ctrl);
+ vfe32_write_gamma_cfg(RGBLUT_RAM_CH1_BANK0, cmdp, vfe32_ctrl);
+ vfe32_write_gamma_cfg(RGBLUT_RAM_CH2_BANK0, cmdp, vfe32_ctrl);
}
cmdp -= 1;
break;
@@ -2025,16 +2222,23 @@
goto proc_general_done;
}
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + V32_RGB_G_OFF);
cmdp += 1;
if (old_val != 0x0) {
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp);
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH1_BANK0, cmdp);
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH2_BANK0, cmdp);
+ vfe32_write_gamma_cfg(
+ RGBLUT_RAM_CH0_BANK0, cmdp, vfe32_ctrl);
+ vfe32_write_gamma_cfg(
+ RGBLUT_RAM_CH1_BANK0, cmdp, vfe32_ctrl);
+ vfe32_write_gamma_cfg(
+ RGBLUT_RAM_CH2_BANK0, cmdp, vfe32_ctrl);
} else {
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH0_BANK1, cmdp);
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH1_BANK1, cmdp);
- vfe32_write_gamma_cfg(RGBLUT_RAM_CH2_BANK1, cmdp);
+ vfe32_write_gamma_cfg(
+ RGBLUT_RAM_CH0_BANK1, cmdp, vfe32_ctrl);
+ vfe32_write_gamma_cfg(
+ RGBLUT_RAM_CH1_BANK1, cmdp, vfe32_ctrl);
+ vfe32_write_gamma_cfg(
+ RGBLUT_RAM_CH2_BANK1, cmdp, vfe32_ctrl);
}
}
vfe32_ctrl->update_gamma = TRUE;
@@ -2054,12 +2258,14 @@
}
cmdp_local = cmdp;
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + V32_RGB_G_OFF);
temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
RGBLUT_RAM_CH0_BANK0;
for (i = 0; i < 3; i++) {
vfe32_read_gamma_cfg(temp2,
- cmdp_local + (VFE32_GAMMA_NUM_ENTRIES * i));
+ cmdp_local + (VFE32_GAMMA_NUM_ENTRIES * i),
+ vfe32_ctrl);
temp2 += 2;
}
if (copy_to_user((void __user *)(cmd->value), cmdp,
@@ -2070,54 +2276,60 @@
break;
case VFE_CMD_STATS_AWB_STOP: {
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_AE_STOP: {
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_BG_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_AF_STOP: {
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_BF_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_IHIST_STOP: {
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_RS_STOP: {
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_CS_STOP: {
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
msm_camera_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STOP:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
- vfe32_stop();
+ vfe32_stop(vfe32_ctrl);
break;
case VFE_CMD_SYNC_TIMER_SETTING:
@@ -2131,7 +2343,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- vfe32_sync_timer_start(cmdp);
+ vfe32_sync_timer_start(cmdp, vfe32_ctrl);
break;
case VFE_CMD_MODULE_CFG: {
@@ -2147,27 +2359,29 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_ZSL:
rc = vfe32_configure_pingpong_buffers(VFE_MSG_V32_START,
- VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_OUTPUT_PRIMARY, vfe32_ctrl);
if (rc < 0)
goto proc_general_done;
rc = vfe32_configure_pingpong_buffers(VFE_MSG_V32_START,
- VFE_MSG_OUTPUT_SECONDARY);
+ VFE_MSG_OUTPUT_SECONDARY, vfe32_ctrl);
if (rc < 0)
goto proc_general_done;
- rc = vfe32_zsl(pmctl);
+ rc = vfe32_zsl(pmctl, vfe32_ctrl);
break;
case VFE_CMD_ASF_CFG:
@@ -2183,11 +2397,13 @@
goto proc_general_done;
}
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
cmdp_local = cmdp + V32_ASF_LEN/4;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V32_ASF_SPECIAL_EFX_CFG_OFF,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V32_ASF_SPECIAL_EFX_CFG_OFF,
cmdp_local, V32_ASF_SPECIAL_EFX_CFG_LEN);
break;
@@ -2209,37 +2425,44 @@
cmdp_local++;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF1,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V33_PCA_ROLL_OFF_CFG_OFF1,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN1);
cmdp_local += 4;
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF2,
+ vfe32_ctrl->share_ctrl->vfebase +
+ V33_PCA_ROLL_OFF_CFG_OFF2,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN2);
cmdp_local += 3;
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
- msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0, vfe32_ctrl);
+ msm_camera_io_w(temp1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
msm_camera_io_w(*(cmdp_local + 1),
- vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE33_DMI_DATA_HI);
msm_camera_io_w(*cmdp_local,
- vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram0 table\n", __func__);
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0, vfe32_ctrl);
+ msm_camera_io_w(temp1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
msm_camera_io_w(*cmdp_local,
- vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram1 table\n", __func__);
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
break;
case VFE_CMD_PCA_ROLL_OFF_UPDATE:
@@ -2259,41 +2482,46 @@
temp1 = *cmdp_local;
cmdp_local += 8;
- temp2 = msm_camera_io_r(vfe32_ctrl->vfebase +
+ temp2 = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1)
& V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0, vfe32_ctrl);
else
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1, vfe32_ctrl);
- msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
msm_camera_io_w(*(cmdp_local + 1),
- vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE33_DMI_DATA_HI);
msm_camera_io_w(*cmdp_local,
- vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram0 table\n", __func__);
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0, vfe32_ctrl);
else
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1, vfe32_ctrl);
- msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
msm_camera_io_w(*cmdp_local,
- vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram1 table\n", __func__);
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
vfe32_ctrl->update_rolloff = true;
break;
case VFE_CMD_GET_PCA_ROLLOFF_TABLE:
@@ -2308,33 +2536,37 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1) &
V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
if (old_val)
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1, vfe32_ctrl);
else
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0, vfe32_ctrl);
CDBG("%s: PCA Rolloff Ram0\n", __func__);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE * 2; i++) {
temp2 = (i == (V33_PCA_ROLL_OFF_TABLE_SIZE));
if (old_val && temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1,
+ vfe32_ctrl);
else if (!old_val && temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0,
+ vfe32_ctrl);
- *cmdp_local = msm_camera_io_r(vfe32_ctrl->vfebase +
+ *cmdp_local = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase +
VFE33_DMI_DATA_LO);
*(cmdp_local + 1) =
- msm_camera_io_r(vfe32_ctrl->vfebase +
+ msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase +
VFE33_DMI_DATA_HI);
CDBG("%s: %08x%08x\n", __func__,
*(cmdp_local + 1), *cmdp_local);
cmdp_local += 2;
}
- vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED, vfe32_ctrl);
if (copy_to_user((void __user *)(cmd->value), cmdp,
temp1)) {
rc = -EFAULT;
@@ -2352,7 +2584,7 @@
goto proc_general_done;
}
*cmdp = msm_camera_io_r(
- vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
+ vfe32_ctrl->share_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
if (copy_to_user((void __user *)(cmd->value), cmdp,
V32_GET_HW_VERSION_LEN)) {
rc = -EFAULT;
@@ -2360,7 +2592,8 @@
}
break;
case VFE_CMD_GET_REG_DUMP:
- temp1 = sizeof(uint32_t) * vfe32_ctrl->register_total;
+ temp1 = sizeof(uint32_t) *
+ vfe32_ctrl->share_ctrl->register_total;
if (cmd->length != temp1) {
rc = -EINVAL;
goto proc_general_done;
@@ -2370,11 +2603,12 @@
rc = -ENOMEM;
goto proc_general_done;
}
- msm_camera_io_dump(
- vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
+ msm_camera_io_dump(vfe32_ctrl->share_ctrl->vfebase,
+ vfe32_ctrl->share_ctrl->register_total*4);
CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
- vfe32_ctrl->vfebase, temp1);
- memcpy_fromio((void *)cmdp, vfe32_ctrl->vfebase, temp1);
+ vfe32_ctrl->share_ctrl->vfebase, temp1);
+ memcpy_fromio((void *)cmdp,
+ vfe32_ctrl->share_ctrl->vfebase, temp1);
if (copy_to_user((void __user *)(cmd->value), cmdp, temp1)) {
rc = -EFAULT;
goto proc_general_done;
@@ -2399,7 +2633,8 @@
}
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
vfe32_ctrl->frame_skip_cnt = ((uint32_t)
*cmdp & VFE_FRAME_SKIP_PERIOD_MASK) + 1;
@@ -2423,7 +2658,8 @@
goto proc_general_done;
}
msm_camera_io_memcpy(
- vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
break;
@@ -2435,10 +2671,11 @@
return rc;
}
-static void vfe32_stats_af_ack(struct vfe_cmd_stats_ack *pAck)
+static void vfe32_stats_af_ack(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_ack *pAck)
{
unsigned long flags;
- spinlock_t *lock = (vfe32_ctrl->stats_comp ?
+ spinlock_t *lock = (vfe32_ctrl->share_ctrl->stats_comp ?
&vfe32_ctrl->comp_stats_ack_lock :
&vfe32_ctrl->af_ack_lock);
spin_lock_irqsave(lock, flags);
@@ -2447,10 +2684,11 @@
spin_unlock_irqrestore(lock, flags);
}
-static void vfe32_stats_awb_ack(struct vfe_cmd_stats_ack *pAck)
+static void vfe32_stats_awb_ack(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_ack *pAck)
{
unsigned long flags;
- spinlock_t *lock = (vfe32_ctrl->stats_comp ?
+ spinlock_t *lock = (vfe32_ctrl->share_ctrl->stats_comp ?
&vfe32_ctrl->comp_stats_ack_lock :
&vfe32_ctrl->awb_ack_lock);
spin_lock_irqsave(lock, flags);
@@ -2459,10 +2697,11 @@
spin_unlock_irqrestore(lock, flags);
}
-static void vfe32_stats_aec_ack(struct vfe_cmd_stats_ack *pAck)
+static void vfe32_stats_aec_ack(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_ack *pAck)
{
unsigned long flags;
- spinlock_t *lock = (vfe32_ctrl->stats_comp ?
+ spinlock_t *lock = (vfe32_ctrl->share_ctrl->stats_comp ?
&vfe32_ctrl->comp_stats_ack_lock :
&vfe32_ctrl->aec_ack_lock);
spin_lock_irqsave(lock, flags);
@@ -2471,10 +2710,11 @@
spin_unlock_irqrestore(lock, flags);
}
-static void vfe32_stats_ihist_ack(struct vfe_cmd_stats_ack *pAck)
+static void vfe32_stats_ihist_ack(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_ack *pAck)
{
unsigned long flags;
- spinlock_t *lock = (vfe32_ctrl->stats_comp ?
+ spinlock_t *lock = (vfe32_ctrl->share_ctrl->stats_comp ?
&vfe32_ctrl->comp_stats_ack_lock :
&vfe32_ctrl->ihist_ack_lock);
spin_lock_irqsave(lock, flags);
@@ -2482,10 +2722,11 @@
vfe32_ctrl->ihistStatsControl.ackPending = FALSE;
spin_unlock_irqrestore(lock, flags);
}
-static void vfe32_stats_rs_ack(struct vfe_cmd_stats_ack *pAck)
+static void vfe32_stats_rs_ack(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_ack *pAck)
{
unsigned long flags;
- spinlock_t *lock = (vfe32_ctrl->stats_comp ?
+ spinlock_t *lock = (vfe32_ctrl->share_ctrl->stats_comp ?
&vfe32_ctrl->comp_stats_ack_lock :
&vfe32_ctrl->rs_ack_lock);
spin_lock_irqsave(lock, flags);
@@ -2493,10 +2734,11 @@
vfe32_ctrl->rsStatsControl.ackPending = FALSE;
spin_unlock_irqrestore(lock, flags);
}
-static void vfe32_stats_cs_ack(struct vfe_cmd_stats_ack *pAck)
+static void vfe32_stats_cs_ack(
+ struct vfe32_ctrl_type *vfe32_ctrl, struct vfe_cmd_stats_ack *pAck)
{
unsigned long flags;
- spinlock_t *lock = (vfe32_ctrl->stats_comp ?
+ spinlock_t *lock = (vfe32_ctrl->share_ctrl->stats_comp ?
&vfe32_ctrl->comp_stats_ack_lock :
&vfe32_ctrl->cs_ack_lock);
spin_lock_irqsave(lock, flags);
@@ -2505,73 +2747,85 @@
spin_unlock_irqrestore(lock, flags);
}
-static inline void vfe32_read_irq_status(struct vfe32_irq_status *out)
+static inline void vfe32_read_irq_status(
+ struct axi_ctrl_t *axi_ctrl, struct vfe32_irq_status *out)
{
uint32_t *temp;
memset(out, 0, sizeof(struct vfe32_irq_status));
- temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_IRQ_STATUS_0);
+ temp = (uint32_t *)(axi_ctrl->share_ctrl->vfebase + VFE_IRQ_STATUS_0);
out->vfeIrqStatus0 = msm_camera_io_r(temp);
- temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_IRQ_STATUS_1);
+ temp = (uint32_t *)(axi_ctrl->share_ctrl->vfebase + VFE_IRQ_STATUS_1);
out->vfeIrqStatus1 = msm_camera_io_r(temp);
- temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
+ temp = (uint32_t *)(axi_ctrl->share_ctrl->vfebase + VFE_CAMIF_STATUS);
out->camifStatus = msm_camera_io_r(temp);
CDBG("camifStatus = 0x%x\n", out->camifStatus);
/* clear the pending interrupt of the same kind.*/
msm_camera_io_w(out->vfeIrqStatus0,
- vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ axi_ctrl->share_ctrl->vfebase + VFE_IRQ_CLEAR_0);
msm_camera_io_w(out->vfeIrqStatus1,
- vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ axi_ctrl->share_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, axi_ctrl->share_ctrl->vfebase + VFE_IRQ_CMD);
}
-static void vfe32_process_reg_update_irq(void)
+static void vfe32_process_reg_update_irq(
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
if (vfe32_ctrl->recording_state == VFE_STATE_START_REQUESTED) {
- if (vfe32_ctrl->operation_mode ==
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- } else if (vfe32_ctrl->operation_mode ==
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ } else if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1]);
}
vfe32_ctrl->recording_state = VFE_STATE_STARTED;
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe32_ctrl->recording_state ==
VFE_STATE_STOP_REQUESTED) {
- if (vfe32_ctrl->operation_mode ==
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- } else if (vfe32_ctrl->operation_mode ==
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ } else if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out1.ch1]);
}
CDBG("stop video triggered .\n");
}
if (vfe32_ctrl->start_ack_pending == TRUE) {
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_START_ACK);
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId, MSG_ID_START_ACK);
vfe32_ctrl->start_ack_pending = FALSE;
} else {
if (vfe32_ctrl->recording_state ==
@@ -2581,10 +2835,12 @@
* when we process the next reg update irq.
*/
msm_camera_io_w_mb(1,
- vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->recording_state ==
VFE_STATE_STOPPED) {
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_STOP_REC_ACK);
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId,
+ MSG_ID_STOP_REC_ACK);
vfe32_ctrl->recording_state = VFE_STATE_IDLE;
}
spin_lock_irqsave(&vfe32_ctrl->update_ack_lock, flags);
@@ -2592,80 +2848,102 @@
vfe32_ctrl->update_ack_pending = FALSE;
spin_unlock_irqrestore(
&vfe32_ctrl->update_ack_lock, flags);
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_UPDATE_ACK);
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId,
+ MSG_ID_UPDATE_ACK);
} else {
spin_unlock_irqrestore(
&vfe32_ctrl->update_ack_lock, flags);
}
}
- if (vfe32_ctrl->liveshot_state == VFE_STATE_START_REQUESTED) {
+ if (vfe32_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_START_REQUESTED) {
pr_info("%s enabling liveshot output\n", __func__);
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- vfe32_ctrl->liveshot_state = VFE_STATE_STARTED;
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ vfe32_ctrl->share_ctrl->liveshot_state =
+ VFE_STATE_STARTED;
}
}
- if (vfe32_ctrl->liveshot_state == VFE_STATE_STARTED) {
- vfe32_ctrl->vfe_capture_count--;
- if (!vfe32_ctrl->vfe_capture_count)
- vfe32_ctrl->liveshot_state = VFE_STATE_STOP_REQUESTED;
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- } else if (vfe32_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED) {
+ if (vfe32_ctrl->share_ctrl->liveshot_state == VFE_STATE_STARTED) {
+ vfe32_ctrl->share_ctrl->vfe_capture_count--;
+ if (!vfe32_ctrl->share_ctrl->vfe_capture_count)
+ vfe32_ctrl->share_ctrl->liveshot_state =
+ VFE_STATE_STOP_REQUESTED;
+ msm_camera_io_w_mb(1, vfe32_ctrl->
+ share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ } else if (vfe32_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_STOP_REQUESTED) {
CDBG("%s: disabling liveshot output\n", __func__);
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- vfe32_ctrl->liveshot_state = VFE_STATE_STOPPED;
- msm_camera_io_w_mb(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[vfe32_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ vfe32_ctrl->share_ctrl->liveshot_state =
+ VFE_STATE_STOPPED;
+ msm_camera_io_w_mb(1, vfe32_ctrl->share_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
}
- } else if (vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED) {
- vfe32_ctrl->liveshot_state = VFE_STATE_IDLE;
+ } else if (vfe32_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_STOPPED) {
+ vfe32_ctrl->share_ctrl->liveshot_state = VFE_STATE_IDLE;
}
- if ((vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN) ||
- (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB) ||
- (vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG) ||
- (vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB)) {
+ if ((vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_MAIN) ||
+ (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_MAIN_AND_THUMB) ||
+ (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_JPEG) ||
+ (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB)) {
/* in snapshot mode */
/* later we need to add check for live snapshot mode. */
if (vfe32_ctrl->frame_skip_pattern & (0x1 <<
(vfe32_ctrl->snapshot_frame_cnt %
vfe32_ctrl->frame_skip_cnt))) {
- vfe32_ctrl->vfe_capture_count--;
+ vfe32_ctrl->share_ctrl->vfe_capture_count--;
/* if last frame to be captured: */
- if (vfe32_ctrl->vfe_capture_count == 0) {
+ if (vfe32_ctrl->share_ctrl->vfe_capture_count == 0) {
/* stop the bus output:write master enable = 0*/
- if (vfe32_ctrl->outpath.output_mode &
- VFE32_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode
+ & VFE32_OUTPUT_MODE_PRIMARY) {
+ msm_camera_io_w(0,
+ vfe32_ctrl->share_ctrl->vfebase+
vfe32_AXI_WM_CFG[vfe32_ctrl->
- outpath.out0.ch0]);
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(0,
+ vfe32_ctrl->share_ctrl->vfebase+
vfe32_AXI_WM_CFG[vfe32_ctrl->
- outpath.out0.ch1]);
+ share_ctrl->outpath.out0.ch1]);
}
- if (vfe32_ctrl->outpath.output_mode &
+ if (vfe32_ctrl->share_ctrl->outpath.output_mode&
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0,
+ vfe32_ctrl->share_ctrl->vfebase+
vfe32_AXI_WM_CFG[vfe32_ctrl->
- outpath.out1.ch0]);
- msm_camera_io_w(0, vfe32_ctrl->vfebase +
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(0,
+ vfe32_ctrl->share_ctrl->vfebase+
vfe32_AXI_WM_CFG[vfe32_ctrl->
- outpath.out1.ch1]);
+ share_ctrl->outpath.out1.ch1]);
}
msm_camera_io_w_mb
(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
- vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_CAMIF_COMMAND);
vfe32_ctrl->snapshot_frame_cnt = -1;
vfe32_ctrl->frame_skip_cnt = 31;
vfe32_ctrl->frame_skip_pattern = 0xffffffff;
@@ -2673,116 +2951,143 @@
} /*if frame is not being dropped*/
vfe32_ctrl->snapshot_frame_cnt++;
/* then do reg_update. */
- msm_camera_io_w(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
-static void vfe32_set_default_reg_values(void)
+static void vfe32_set_default_reg_values(
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
- msm_camera_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_camera_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0x800080,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_DEMUX_GAIN_1);
/* What value should we program CGC_OVERRIDE to? */
- msm_camera_io_w(0xFFFFF, vfe32_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0xFFFFF,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0x1f,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
msm_camera_io_w(0xFFFFFFFF,
- vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
msm_camera_io_w(0xFFFFFFFF,
- vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_FRAMEDROP_ENC_CBCR_PATTERN);
+ msm_camera_io_w(0x1f,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
msm_camera_io_w(0xFFFFFFFF,
- vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
msm_camera_io_w(0xFFFFFFFF,
- vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_camera_io_w(0, vfe32_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_camera_io_w(0xFFFFFF, vfe32_ctrl->vfebase + VFE_CLAMP_MAX);
+ vfe32_ctrl->share_ctrl->vfebase +
+ VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
+ msm_camera_io_w(0, vfe32_ctrl->share_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
msm_camera_io_w(0x3980007,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
msm_camera_io_w(0x3A00007,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
msm_camera_io_w(0x3A8000F,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
msm_camera_io_w(0x3B80007,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
msm_camera_io_w(0x3C0001F,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
msm_camera_io_w(0x3E0001F,
- vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
-static void vfe32_process_reset_irq(void)
+static void vfe32_process_reset_irq(
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
- atomic_set(&vfe32_ctrl->vstate, 0);
+ atomic_set(&vfe32_ctrl->share_ctrl->vstate, 0);
- spin_lock_irqsave(&vfe32_ctrl->stop_flag_lock, flags);
- if (vfe32_ctrl->stop_ack_pending) {
- vfe32_ctrl->stop_ack_pending = FALSE;
- spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_STOP_ACK);
+ spin_lock_irqsave(&vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
+ if (vfe32_ctrl->share_ctrl->stop_ack_pending) {
+ vfe32_ctrl->share_ctrl->stop_ack_pending = FALSE;
+ spin_unlock_irqrestore(
+ &vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId, MSG_ID_STOP_ACK);
} else {
- spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
+ spin_unlock_irqrestore(
+ &vfe32_ctrl->share_ctrl->stop_flag_lock, flags);
/* this is from reset command. */
- vfe32_set_default_reg_values();
+ vfe32_set_default_reg_values(vfe32_ctrl);
/* reload all write masters. (frame & line)*/
- msm_camera_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_RESET_ACK);
+ msm_camera_io_w(0x7FFF,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_BUS_CMD);
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId, MSG_ID_RESET_ACK);
}
}
-static void vfe32_process_camif_sof_irq(void)
+static void vfe32_process_camif_sof_irq(
+ struct vfe32_ctrl_type *vfe32_ctrl)
{
- if (vfe32_ctrl->operation_mode ==
+ if (vfe32_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_RAW) {
if (vfe32_ctrl->start_ack_pending) {
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_START_ACK);
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId,
+ MSG_ID_START_ACK);
vfe32_ctrl->start_ack_pending = FALSE;
}
- vfe32_ctrl->vfe_capture_count--;
+ vfe32_ctrl->share_ctrl->vfe_capture_count--;
/* if last frame to be captured: */
- if (vfe32_ctrl->vfe_capture_count == 0) {
+ if (vfe32_ctrl->share_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
- vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ vfe32_ctrl->share_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
if ((vfe32_ctrl->hfr_mode != HFR_MODE_OFF) &&
- (vfe32_ctrl->operation_mode == VFE_MODE_OF_OPERATION_VIDEO) &&
- (vfe32_ctrl->vfeFrameId % vfe32_ctrl->hfr_mode != 0)) {
- vfe32_ctrl->vfeFrameId++;
+ (vfe32_ctrl->share_ctrl->operation_mode ==
+ VFE_MODE_OF_OPERATION_VIDEO) &&
+ (vfe32_ctrl->share_ctrl->vfeFrameId %
+ vfe32_ctrl->hfr_mode != 0)) {
+ vfe32_ctrl->share_ctrl->vfeFrameId++;
CDBG("Skip the SOF notification when HFR enabled\n");
return;
}
- vfe32_ctrl->vfeFrameId++;
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_SOF_ACK);
- CDBG("camif_sof_irq, frameId = %d\n", vfe32_ctrl->vfeFrameId);
+ vfe32_ctrl->share_ctrl->vfeFrameId++;
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId, MSG_ID_SOF_ACK);
+ CDBG("camif_sof_irq, frameId = %d\n",
+ vfe32_ctrl->share_ctrl->vfeFrameId);
if (vfe32_ctrl->sync_timer_state) {
if (vfe32_ctrl->sync_timer_repeat_count == 0)
- vfe32_sync_timer_stop();
+ vfe32_sync_timer_stop(vfe32_ctrl);
else
vfe32_ctrl->sync_timer_repeat_count--;
}
}
-static void vfe32_process_error_irq(uint32_t errStatus)
+static void vfe32_process_error_irq(
+ struct axi_ctrl_t *axi_ctrl, uint32_t errStatus)
{
uint32_t reg_value;
if (errStatus & VFE32_IMASK_CAMIF_ERROR) {
pr_err("vfe32_irq: camif errors\n");
reg_value = msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
+ axi_ctrl->share_ctrl->vfebase + VFE_CAMIF_STATUS);
pr_err("camifStatus = 0x%x\n", reg_value);
- vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_CAMIF_ERROR);
+ vfe32_send_isp_msg(&axi_ctrl->subdev,
+ axi_ctrl->share_ctrl->vfeFrameId, MSG_ID_CAMIF_ERROR);
}
if (errStatus & VFE32_IMASK_BHIST_OVWR)
@@ -2806,7 +3111,7 @@
if (errStatus & VFE32_IMASK_VIOLATION) {
pr_err("vfe32_irq: violation interrupt\n");
reg_value = msm_camera_io_r(
- vfe32_ctrl->vfebase + VFE_VIOLATION_STATUS);
+ axi_ctrl->share_ctrl->vfebase + VFE_VIOLATION_STATUS);
pr_err("%s: violationStatus = 0x%x\n", __func__, reg_value);
}
@@ -2856,7 +3161,8 @@
pr_err("vfe32_irq: axi error\n");
}
-static void vfe_send_outmsg(struct v4l2_subdev *sd, uint8_t msgid,
+static void vfe_send_outmsg(
+ struct axi_ctrl_t *axi_ctrl, uint8_t msgid,
uint32_t ch0_paddr, uint32_t ch1_paddr, uint32_t ch2_paddr)
{
struct isp_msg_output msg;
@@ -2865,15 +3171,16 @@
msg.buf.ch_paddr[0] = ch0_paddr;
msg.buf.ch_paddr[1] = ch1_paddr;
msg.buf.ch_paddr[2] = ch2_paddr;
- msg.frameCounter = vfe32_ctrl->vfeFrameId;
+ msg.frameCounter = axi_ctrl->share_ctrl->vfeFrameId;
- v4l2_subdev_notify(&vfe32_ctrl->subdev,
+ v4l2_subdev_notify(&axi_ctrl->subdev,
NOTIFY_VFE_MSG_OUT,
&msg);
return;
}
-static void vfe32_process_output_path_irq_0(void)
+static void vfe32_process_output_path_irq_0(
+ struct axi_ctrl_t *axi_ctrl)
{
uint32_t ping_pong;
uint32_t ch0_paddr, ch1_paddr, ch2_paddr;
@@ -2881,7 +3188,7 @@
struct msm_free_buf *free_buf = NULL;
free_buf = vfe32_check_free_buffer(VFE_MSG_OUTPUT_IRQ,
- VFE_MSG_OUTPUT_PRIMARY);
+ VFE_MSG_OUTPUT_PRIMARY, axi_ctrl);
/* we render frames in the following conditions:
1. Continuous mode and the free buffer is avaialable.
@@ -2889,73 +3196,91 @@
when pending snapshot count is <=1, then no need to use
free buffer.
*/
- out_bool = ((vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_RAW ||
- vfe32_ctrl->liveshot_state == VFE_STATE_STARTED ||
- vfe32_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED ||
- vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED) &&
- (vfe32_ctrl->vfe_capture_count <= 1)) || free_buf;
+ out_bool = (
+ (axi_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_MAIN ||
+ axi_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_MAIN_AND_THUMB ||
+ axi_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_JPEG ||
+ axi_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB ||
+ axi_ctrl->share_ctrl->operation_mode ==
+ VFE_OUTPUTS_RAW ||
+ axi_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_STARTED ||
+ axi_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_STOP_REQUESTED ||
+ axi_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_STOPPED) &&
+ (axi_ctrl->share_ctrl->vfe_capture_count <= 1)) ||
+ free_buf;
if (out_bool) {
- ping_pong = msm_camera_io_r(vfe32_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(axi_ctrl->share_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Channel 0*/
- ch0_paddr = vfe32_get_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out0.ch0);
+ ch0_paddr = vfe32_get_ch_addr(
+ ping_pong, axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out0.ch0);
/* Channel 1*/
- ch1_paddr = vfe32_get_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out0.ch1);
+ ch1_paddr = vfe32_get_ch_addr(
+ ping_pong, axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out0.ch1);
/* Channel 2*/
- ch2_paddr = vfe32_get_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out0.ch2);
+ ch2_paddr = vfe32_get_ch_addr(
+ ping_pong, axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out0.ch2);
CDBG("output path 0, ch0 = 0x%x, ch1 = 0x%x, ch2 = 0x%x\n",
ch0_paddr, ch1_paddr, ch2_paddr);
if (free_buf) {
/* Y channel */
vfe32_put_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out0.ch0,
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out0.ch0,
free_buf->ch_paddr[0]);
/* Chroma channel */
vfe32_put_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out0.ch1,
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out0.ch1,
free_buf->ch_paddr[1]);
if (free_buf->num_planes > 2)
vfe32_put_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out0.ch2,
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out0.ch2,
free_buf->ch_paddr[2]);
}
- if (vfe32_ctrl->operation_mode ==
+ if (axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_THUMB_AND_MAIN ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_THUMB_AND_JPEG ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_JPEG_AND_THUMB ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_RAW ||
- vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED)
- vfe32_ctrl->outpath.out0.capture_cnt--;
+ axi_ctrl->share_ctrl->liveshot_state ==
+ VFE_STATE_STOPPED)
+ axi_ctrl->share_ctrl->outpath.out0.capture_cnt--;
- vfe_send_outmsg(&vfe32_ctrl->subdev,
+ vfe_send_outmsg(axi_ctrl,
MSG_ID_OUTPUT_PRIMARY, ch0_paddr,
ch1_paddr, ch2_paddr);
- if (vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED)
- vfe32_ctrl->liveshot_state = VFE_STATE_IDLE;
+ if (axi_ctrl->share_ctrl->liveshot_state == VFE_STATE_STOPPED)
+ axi_ctrl->share_ctrl->liveshot_state = VFE_STATE_IDLE;
} else {
- vfe32_ctrl->outpath.out0.frame_drop_cnt++;
+ axi_ctrl->share_ctrl->outpath.out0.frame_drop_cnt++;
CDBG("path_irq_0 - no free buffer!\n");
}
}
-static void vfe32_process_output_path_irq_1(void)
+static void vfe32_process_output_path_irq_1(
+ struct axi_ctrl_t *axi_ctrl)
{
uint32_t ping_pong;
uint32_t ch0_paddr, ch1_paddr, ch2_paddr;
@@ -2964,81 +3289,89 @@
struct msm_free_buf *free_buf = NULL;
free_buf = vfe32_check_free_buffer(VFE_MSG_OUTPUT_IRQ,
- VFE_MSG_OUTPUT_SECONDARY);
- out_bool = ((vfe32_ctrl->operation_mode ==
+ VFE_MSG_OUTPUT_SECONDARY, axi_ctrl);
+ out_bool = ((axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_THUMB_AND_MAIN ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_RAW ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_JPEG_AND_THUMB) &&
- (vfe32_ctrl->vfe_capture_count <= 1)) || free_buf;
+ (axi_ctrl->share_ctrl->vfe_capture_count <= 1)) ||
+ free_buf;
if (out_bool) {
- ping_pong = msm_camera_io_r(vfe32_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(axi_ctrl->share_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Y channel */
ch0_paddr = vfe32_get_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out1.ch0);
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out1.ch0);
/* Chroma channel */
ch1_paddr = vfe32_get_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out1.ch1);
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out1.ch1);
ch2_paddr = vfe32_get_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out1.ch2);
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out1.ch2);
CDBG("%s ch0 = 0x%x, ch1 = 0x%x, ch2 = 0x%x\n",
__func__, ch0_paddr, ch1_paddr, ch2_paddr);
if (free_buf) {
/* Y channel */
vfe32_put_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out1.ch0,
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out1.ch0,
free_buf->ch_paddr[0]);
/* Chroma channel */
vfe32_put_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out1.ch1,
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out1.ch1,
free_buf->ch_paddr[1]);
if (free_buf->num_planes > 2)
vfe32_put_ch_addr(ping_pong,
- vfe32_ctrl->outpath.out1.ch2,
+ axi_ctrl->share_ctrl->vfebase,
+ axi_ctrl->share_ctrl->outpath.out1.ch2,
free_buf->ch_paddr[2]);
}
- if (vfe32_ctrl->operation_mode ==
+ if (axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_THUMB_AND_MAIN ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_RAW ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_JPEG_AND_THUMB)
- vfe32_ctrl->outpath.out1.capture_cnt--;
+ axi_ctrl->share_ctrl->outpath.out1.capture_cnt--;
- vfe_send_outmsg(&vfe32_ctrl->subdev,
+ vfe_send_outmsg(axi_ctrl,
MSG_ID_OUTPUT_SECONDARY, ch0_paddr,
ch1_paddr, ch2_paddr);
} else {
- vfe32_ctrl->outpath.out1.frame_drop_cnt++;
+ axi_ctrl->share_ctrl->outpath.out1.frame_drop_cnt++;
CDBG("path_irq_1 - no free buffer!\n");
}
}
-static uint32_t vfe32_process_stats_irq_common(uint32_t statsNum,
- uint32_t newAddr) {
-
+static uint32_t vfe32_process_stats_irq_common(
+ struct vfe32_ctrl_type *vfe32_ctrl,
+ uint32_t statsNum, uint32_t newAddr)
+{
uint32_t pingpongStatus;
uint32_t returnAddr;
uint32_t pingpongAddr;
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_camera_io_r(vfe32_ctrl->vfebase +
+ ((msm_camera_io_r(vfe32_ctrl->share_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
CDBG("statsNum %d, pingpongStatus %d\n", statsNum, pingpongStatus);
pingpongAddr =
- ((uint32_t)(vfe32_ctrl->vfebase +
+ ((uint32_t)(vfe32_ctrl->share_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
@@ -3047,14 +3380,15 @@
}
static void
-vfe_send_stats_msg(uint32_t bufAddress, uint32_t statsNum)
+vfe_send_stats_msg(struct vfe32_ctrl_type *vfe32_ctrl,
+ uint32_t bufAddress, uint32_t statsNum)
{
unsigned long flags;
/* fill message with right content. */
/* @todo This is causing issues, need further investigate */
/* spin_lock_irqsave(&ctrl->state_lock, flags); */
struct isp_msg_stats msgStats;
- msgStats.frameCounter = vfe32_ctrl->vfeFrameId;
+ msgStats.frameCounter = vfe32_ctrl->share_ctrl->vfeFrameId;
msgStats.buffer = bufAddress;
switch (statsNum) {
@@ -3114,12 +3448,13 @@
return;
}
-static void vfe_send_comp_stats_msg(uint32_t status_bits)
+static void vfe_send_comp_stats_msg(
+ struct vfe32_ctrl_type *vfe32_ctrl, uint32_t status_bits)
{
struct msm_stats_buf msgStats;
uint32_t temp;
- msgStats.frame_id = vfe32_ctrl->vfeFrameId;
+ msgStats.frame_id = vfe32_ctrl->share_ctrl->vfeFrameId;
msgStats.status_bits = status_bits;
msgStats.aec.buff = vfe32_ctrl->aecStatsControl.bufToRender;
@@ -3130,7 +3465,8 @@
msgStats.rs.buff = vfe32_ctrl->rsStatsControl.bufToRender;
msgStats.cs.buff = vfe32_ctrl->csStatsControl.bufToRender;
- temp = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(
+ vfe32_ctrl->share_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msgStats.awb_ymin = (0xFF00 & temp) >> 8;
v4l2_subdev_notify(&vfe32_ctrl->subdev,
@@ -3138,18 +3474,18 @@
&msgStats);
}
-static void vfe32_process_stats_ae_irq(void)
+static void vfe32_process_stats_ae_irq(struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
spin_lock_irqsave(&vfe32_ctrl->aec_ack_lock, flags);
if (!(vfe32_ctrl->aecStatsControl.ackPending)) {
spin_unlock_irqrestore(&vfe32_ctrl->aec_ack_lock, flags);
vfe32_ctrl->aecStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsAeNum,
+ vfe32_process_stats_irq_common(vfe32_ctrl, statsAeNum,
vfe32_ctrl->aecStatsControl.nextFrameAddrBuf);
- vfe_send_stats_msg(vfe32_ctrl->aecStatsControl.bufToRender,
- statsAeNum);
+ vfe_send_stats_msg(vfe32_ctrl,
+ vfe32_ctrl->aecStatsControl.bufToRender, statsAeNum);
} else{
spin_unlock_irqrestore(&vfe32_ctrl->aec_ack_lock, flags);
vfe32_ctrl->aecStatsControl.droppedStatsFrameCount++;
@@ -3158,18 +3494,18 @@
}
}
-static void vfe32_process_stats_awb_irq(void)
+static void vfe32_process_stats_awb_irq(struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
spin_lock_irqsave(&vfe32_ctrl->awb_ack_lock, flags);
if (!(vfe32_ctrl->awbStatsControl.ackPending)) {
spin_unlock_irqrestore(&vfe32_ctrl->awb_ack_lock, flags);
vfe32_ctrl->awbStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsAwbNum,
+ vfe32_process_stats_irq_common(vfe32_ctrl, statsAwbNum,
vfe32_ctrl->awbStatsControl.nextFrameAddrBuf);
- vfe_send_stats_msg(vfe32_ctrl->awbStatsControl.bufToRender,
- statsAwbNum);
+ vfe_send_stats_msg(vfe32_ctrl,
+ vfe32_ctrl->awbStatsControl.bufToRender, statsAwbNum);
} else{
spin_unlock_irqrestore(&vfe32_ctrl->awb_ack_lock, flags);
vfe32_ctrl->awbStatsControl.droppedStatsFrameCount++;
@@ -3178,18 +3514,18 @@
}
}
-static void vfe32_process_stats_af_irq(void)
+static void vfe32_process_stats_af_irq(struct vfe32_ctrl_type *vfe32_ctrl)
{
unsigned long flags;
spin_lock_irqsave(&vfe32_ctrl->af_ack_lock, flags);
if (!(vfe32_ctrl->afStatsControl.ackPending)) {
spin_unlock_irqrestore(&vfe32_ctrl->af_ack_lock, flags);
vfe32_ctrl->afStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsAfNum,
+ vfe32_process_stats_irq_common(vfe32_ctrl, statsAfNum,
vfe32_ctrl->afStatsControl.nextFrameAddrBuf);
- vfe_send_stats_msg(vfe32_ctrl->afStatsControl.bufToRender,
- statsAfNum);
+ vfe_send_stats_msg(vfe32_ctrl,
+ vfe32_ctrl->afStatsControl.bufToRender, statsAfNum);
} else{
spin_unlock_irqrestore(&vfe32_ctrl->af_ack_lock, flags);
vfe32_ctrl->afStatsControl.droppedStatsFrameCount++;
@@ -3198,15 +3534,17 @@
}
}
-static void vfe32_process_stats_ihist_irq(void)
+static void vfe32_process_stats_ihist_irq(struct vfe32_ctrl_type *vfe32_ctrl)
{
if (!(vfe32_ctrl->ihistStatsControl.ackPending)) {
vfe32_ctrl->ihistStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsIhistNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsIhistNum,
vfe32_ctrl->ihistStatsControl.nextFrameAddrBuf);
- vfe_send_stats_msg(vfe32_ctrl->ihistStatsControl.bufToRender,
- statsIhistNum);
+ vfe_send_stats_msg(vfe32_ctrl,
+ vfe32_ctrl->ihistStatsControl.bufToRender,
+ statsIhistNum);
} else {
vfe32_ctrl->ihistStatsControl.droppedStatsFrameCount++;
CDBG("%s: droppedStatsFrameCount = %d", __func__,
@@ -3214,15 +3552,15 @@
}
}
-static void vfe32_process_stats_rs_irq(void)
+static void vfe32_process_stats_rs_irq(struct vfe32_ctrl_type *vfe32_ctrl)
{
if (!(vfe32_ctrl->rsStatsControl.ackPending)) {
vfe32_ctrl->rsStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsRsNum,
+ vfe32_process_stats_irq_common(vfe32_ctrl, statsRsNum,
vfe32_ctrl->rsStatsControl.nextFrameAddrBuf);
- vfe_send_stats_msg(vfe32_ctrl->rsStatsControl.bufToRender,
- statsRsNum);
+ vfe_send_stats_msg(vfe32_ctrl,
+ vfe32_ctrl->rsStatsControl.bufToRender, statsRsNum);
} else {
vfe32_ctrl->rsStatsControl.droppedStatsFrameCount++;
CDBG("%s: droppedStatsFrameCount = %d", __func__,
@@ -3230,15 +3568,15 @@
}
}
-static void vfe32_process_stats_cs_irq(void)
+static void vfe32_process_stats_cs_irq(struct vfe32_ctrl_type *vfe32_ctrl)
{
if (!(vfe32_ctrl->csStatsControl.ackPending)) {
vfe32_ctrl->csStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsCsNum,
+ vfe32_process_stats_irq_common(vfe32_ctrl, statsCsNum,
vfe32_ctrl->csStatsControl.nextFrameAddrBuf);
- vfe_send_stats_msg(vfe32_ctrl->csStatsControl.bufToRender,
- statsCsNum);
+ vfe_send_stats_msg(vfe32_ctrl,
+ vfe32_ctrl->csStatsControl.bufToRender, statsCsNum);
} else {
vfe32_ctrl->csStatsControl.droppedStatsFrameCount++;
CDBG("%s: droppedStatsFrameCount = %d", __func__,
@@ -3246,7 +3584,8 @@
}
}
-static void vfe32_process_stats(uint32_t status_bits)
+static void vfe32_process_stats(struct vfe32_ctrl_type *vfe32_ctrl,
+ uint32_t status_bits)
{
unsigned long flags;
int32_t process_stats = false;
@@ -3257,7 +3596,8 @@
if (!vfe32_ctrl->aecStatsControl.ackPending) {
vfe32_ctrl->aecStatsControl.ackPending = TRUE;
vfe32_ctrl->aecStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsAeNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsAeNum,
vfe32_ctrl->aecStatsControl.nextFrameAddrBuf);
process_stats = true;
} else{
@@ -3272,7 +3612,8 @@
if (!vfe32_ctrl->awbStatsControl.ackPending) {
vfe32_ctrl->awbStatsControl.ackPending = TRUE;
vfe32_ctrl->awbStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsAwbNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsAwbNum,
vfe32_ctrl->awbStatsControl.nextFrameAddrBuf);
process_stats = true;
} else{
@@ -3288,7 +3629,8 @@
if (!vfe32_ctrl->afStatsControl.ackPending) {
vfe32_ctrl->afStatsControl.ackPending = TRUE;
vfe32_ctrl->afStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsAfNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsAfNum,
vfe32_ctrl->afStatsControl.nextFrameAddrBuf);
process_stats = true;
} else {
@@ -3303,7 +3645,8 @@
if (!vfe32_ctrl->ihistStatsControl.ackPending) {
vfe32_ctrl->ihistStatsControl.ackPending = TRUE;
vfe32_ctrl->ihistStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsIhistNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsIhistNum,
vfe32_ctrl->ihistStatsControl.nextFrameAddrBuf);
process_stats = true;
} else {
@@ -3318,7 +3661,8 @@
if (!vfe32_ctrl->rsStatsControl.ackPending) {
vfe32_ctrl->rsStatsControl.ackPending = TRUE;
vfe32_ctrl->rsStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsRsNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsRsNum,
vfe32_ctrl->rsStatsControl.nextFrameAddrBuf);
process_stats = true;
} else {
@@ -3329,12 +3673,12 @@
vfe32_ctrl->rsStatsControl.bufToRender = 0;
}
-
if (status_bits & VFE_IRQ_STATUS0_STATS_CS) {
if (!vfe32_ctrl->csStatsControl.ackPending) {
vfe32_ctrl->csStatsControl.ackPending = TRUE;
vfe32_ctrl->csStatsControl.bufToRender =
- vfe32_process_stats_irq_common(statsCsNum,
+ vfe32_process_stats_irq_common(
+ vfe32_ctrl, statsCsNum,
vfe32_ctrl->csStatsControl.nextFrameAddrBuf);
process_stats = true;
} else {
@@ -3347,83 +3691,89 @@
spin_unlock_irqrestore(&vfe32_ctrl->comp_stats_ack_lock, flags);
if (process_stats)
- vfe_send_comp_stats_msg(status_bits);
+ vfe_send_comp_stats_msg(vfe32_ctrl, status_bits);
return;
}
-static void vfe32_process_stats_irq(uint32_t irqstatus)
+static void vfe32_process_stats_irq(
+ struct vfe32_ctrl_type *vfe32_ctrl, uint32_t irqstatus)
{
uint32_t status_bits = VFE_COM_STATUS & irqstatus;
if ((vfe32_ctrl->hfr_mode != HFR_MODE_OFF) &&
- (vfe32_ctrl->vfeFrameId % vfe32_ctrl->hfr_mode != 0)) {
+ (vfe32_ctrl->share_ctrl->vfeFrameId %
+ vfe32_ctrl->hfr_mode != 0)) {
CDBG("Skip the stats when HFR enabled\n");
return;
}
- vfe32_process_stats(status_bits);
+ vfe32_process_stats(vfe32_ctrl, status_bits);
return;
}
-static void vfe32_process_irq(uint32_t irqstatus)
+static void vfe32_process_irq(
+ struct vfe32_ctrl_type *vfe32_ctrl, uint32_t irqstatus)
{
if (irqstatus &
VFE_IRQ_STATUS0_STATS_COMPOSIT_MASK) {
- vfe32_process_stats_irq(irqstatus);
+ vfe32_process_stats_irq(vfe32_ctrl, irqstatus);
return;
}
switch (irqstatus) {
case VFE_IRQ_STATUS0_CAMIF_SOF_MASK:
CDBG("irq camifSofIrq\n");
- vfe32_process_camif_sof_irq();
+ vfe32_process_camif_sof_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_REG_UPDATE_MASK:
CDBG("irq regUpdateIrq\n");
- vfe32_process_reg_update_irq();
+ vfe32_process_reg_update_irq(vfe32_ctrl);
break;
case VFE_IMASK_WHILE_STOPPING_1:
CDBG("irq resetAckIrq\n");
- vfe32_process_reset_irq();
+ vfe32_process_reset_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_STATS_AEC:
CDBG("Stats AEC irq occured.\n");
- vfe32_process_stats_ae_irq();
+ vfe32_process_stats_ae_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_STATS_AWB:
CDBG("Stats AWB irq occured.\n");
- vfe32_process_stats_awb_irq();
+ vfe32_process_stats_awb_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_STATS_AF:
CDBG("Stats AF irq occured.\n");
- vfe32_process_stats_af_irq();
+ vfe32_process_stats_af_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_STATS_IHIST:
CDBG("Stats IHIST irq occured.\n");
- vfe32_process_stats_ihist_irq();
+ vfe32_process_stats_ihist_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_STATS_RS:
CDBG("Stats RS irq occured.\n");
- vfe32_process_stats_rs_irq();
+ vfe32_process_stats_rs_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_STATS_CS:
CDBG("Stats CS irq occured.\n");
- vfe32_process_stats_cs_irq();
+ vfe32_process_stats_cs_irq(vfe32_ctrl);
break;
case VFE_IRQ_STATUS0_SYNC_TIMER0:
CDBG("SYNC_TIMER 0 irq occured.\n");
- vfe32_send_isp_msg(vfe32_ctrl,
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId,
MSG_ID_SYNC_TIMER0_DONE);
break;
case VFE_IRQ_STATUS0_SYNC_TIMER1:
CDBG("SYNC_TIMER 1 irq occured.\n");
- vfe32_send_isp_msg(vfe32_ctrl,
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId,
MSG_ID_SYNC_TIMER1_DONE);
break;
case VFE_IRQ_STATUS0_SYNC_TIMER2:
CDBG("SYNC_TIMER 2 irq occured.\n");
- vfe32_send_isp_msg(vfe32_ctrl,
+ vfe32_send_isp_msg(&vfe32_ctrl->subdev,
+ vfe32_ctrl->share_ctrl->vfeFrameId,
MSG_ID_SYNC_TIMER2_DONE);
break;
default:
@@ -3474,11 +3824,12 @@
NOTIFY_VFE_IRQ,
(void *)VFE_IMASK_WHILE_STOPPING_1);
- if (atomic_read(&vfe32_ctrl->vstate)) {
+ if (atomic_read(&axi_ctrl->share_ctrl->vstate)) {
if (qcmd->vfeInterruptStatus1 &
VFE32_IMASK_ERROR_ONLY_1) {
pr_err("irq errorIrq\n");
vfe32_process_error_irq(
+ axi_ctrl,
qcmd->vfeInterruptStatus1 &
VFE32_IMASK_ERROR_ONLY_1);
}
@@ -3487,7 +3838,7 @@
(void *)qcmd->vfeInterruptStatus0);
/* then process stats irq. */
- if (vfe32_ctrl->stats_comp) {
+ if (axi_ctrl->share_ctrl->stats_comp) {
/* process stats comb interrupt. */
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_STATS_COMPOSIT_MASK) {
@@ -3567,7 +3918,7 @@
CDBG("vfe_parse_irq\n");
- vfe32_read_irq_status(&irq);
+ vfe32_read_irq_status(axi_ctrl, &irq);
if ((irq.vfeIrqStatus0 == 0) && (irq.vfeIrqStatus1 == 0)) {
CDBG("vfe_parse_irq: vfeIrqStatus0 & 1 are both 0!\n");
@@ -3581,12 +3932,12 @@
return IRQ_HANDLED;
}
- spin_lock_irqsave(&vfe32_ctrl->stop_flag_lock, flags);
- if (vfe32_ctrl->stop_ack_pending) {
+ spin_lock_irqsave(&axi_ctrl->share_ctrl->stop_flag_lock, flags);
+ if (axi_ctrl->share_ctrl->stop_ack_pending) {
irq.vfeIrqStatus0 &= VFE_IMASK_WHILE_STOPPING_0;
irq.vfeIrqStatus1 &= VFE_IMASK_WHILE_STOPPING_1;
}
- spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
+ spin_unlock_irqrestore(&axi_ctrl->share_ctrl->stop_flag_lock, flags);
CDBG("vfe_parse_irq: Irq_status0 = 0x%x, Irq_status1 = 0x%x.\n",
irq.vfeIrqStatus0, irq.vfeIrqStatus1);
@@ -3608,6 +3959,8 @@
{
struct msm_cam_media_controller *pmctl =
(struct msm_cam_media_controller *)v4l2_get_subdev_hostdata(sd);
+ struct vfe32_ctrl_type *vfe32_ctrl =
+ (struct vfe32_ctrl_type *)v4l2_get_subdevdata(sd);
struct msm_isp_cmd vfecmd;
struct msm_camvfe_params *vfe_params =
(struct msm_camvfe_params *)arg;
@@ -3619,8 +3972,14 @@
struct vfe_cmd_stats_buf *scfg = NULL;
struct msm_pmem_region *regptr = NULL;
struct vfe_cmd_stats_ack *sack = NULL;
+
+ if (!vfe32_ctrl->share_ctrl->vfebase) {
+ pr_err("%s: base address unmapped\n", __func__);
+ return -EFAULT;
+ }
+
if (cmd->cmd_type == CMD_VFE_PROCESS_IRQ) {
- vfe32_process_irq((uint32_t) data);
+ vfe32_process_irq(vfe32_ctrl, (uint32_t) data);
return rc;
} else if (cmd->cmd_type != CMD_CONFIG_PING_ADDR &&
cmd->cmd_type != CMD_CONFIG_PONG_ADDR &&
@@ -3688,22 +4047,22 @@
/* individual */
switch (cmd->cmd_type) {
case CMD_STATS_AEC_ENABLE:
- rc = vfe_stats_aec_buf_init(scfg);
+ rc = vfe_stats_aec_buf_init(vfe32_ctrl, scfg);
break;
case CMD_STATS_AF_ENABLE:
- rc = vfe_stats_af_buf_init(scfg);
+ rc = vfe_stats_af_buf_init(vfe32_ctrl, scfg);
break;
case CMD_STATS_AWB_ENABLE:
- rc = vfe_stats_awb_buf_init(scfg);
+ rc = vfe_stats_awb_buf_init(vfe32_ctrl, scfg);
break;
case CMD_STATS_IHIST_ENABLE:
- rc = vfe_stats_ihist_buf_init(scfg);
+ rc = vfe_stats_ihist_buf_init(vfe32_ctrl, scfg);
break;
case CMD_STATS_RS_ENABLE:
- rc = vfe_stats_rs_buf_init(scfg);
+ rc = vfe_stats_rs_buf_init(vfe32_ctrl, scfg);
break;
case CMD_STATS_CS_ENABLE:
- rc = vfe_stats_cs_buf_init(scfg);
+ rc = vfe_stats_cs_buf_init(vfe32_ctrl, scfg);
break;
default:
pr_err("%s Unsupported cmd type %d",
@@ -3714,50 +4073,51 @@
}
switch (cmd->cmd_type) {
case CMD_GENERAL:
- rc = vfe32_proc_general(pmctl, &vfecmd);
+ rc = vfe32_proc_general(pmctl, &vfecmd, vfe32_ctrl);
break;
-
case CMD_CONFIG_PING_ADDR: {
int path = *((int *)cmd->value);
- struct vfe32_output_ch *outch = vfe32_get_ch(path);
+ struct vfe32_output_ch *outch =
+ vfe32_get_ch(path, vfe32_ctrl->share_ctrl);
outch->ping = *((struct msm_free_buf *)data);
}
break;
case CMD_CONFIG_PONG_ADDR: {
int path = *((int *)cmd->value);
- struct vfe32_output_ch *outch = vfe32_get_ch(path);
+ struct vfe32_output_ch *outch =
+ vfe32_get_ch(path, vfe32_ctrl->share_ctrl);
outch->pong = *((struct msm_free_buf *)data);
}
break;
case CMD_CONFIG_FREE_BUF_ADDR: {
int path = *((int *)cmd->value);
- struct vfe32_output_ch *outch = vfe32_get_ch(path);
+ struct vfe32_output_ch *outch =
+ vfe32_get_ch(path, vfe32_ctrl->share_ctrl);
outch->free_buf = *((struct msm_free_buf *)data);
}
break;
-
case CMD_SNAP_BUF_RELEASE:
break;
case CMD_STATS_AEC_BUF_RELEASE:
- vfe32_stats_aec_ack(sack);
+ vfe32_stats_aec_ack(vfe32_ctrl, sack);
break;
case CMD_STATS_AF_BUF_RELEASE:
- vfe32_stats_af_ack(sack);
+ vfe32_stats_af_ack(vfe32_ctrl, sack);
break;
case CMD_STATS_AWB_BUF_RELEASE:
- vfe32_stats_awb_ack(sack);
+ vfe32_stats_awb_ack(vfe32_ctrl, sack);
break;
case CMD_STATS_IHIST_BUF_RELEASE:
- vfe32_stats_ihist_ack(sack);
+ vfe32_stats_ihist_ack(vfe32_ctrl, sack);
break;
case CMD_STATS_RS_BUF_RELEASE:
- vfe32_stats_rs_ack(sack);
+ vfe32_stats_rs_ack(vfe32_ctrl, sack);
break;
case CMD_STATS_CS_BUF_RELEASE:
- vfe32_stats_cs_ack(sack);
+ vfe32_stats_cs_ack(vfe32_ctrl, sack);
break;
default:
pr_err("%s Unsupported AXI configuration %x ", __func__,
@@ -3816,17 +4176,16 @@
v4l2_set_subdev_hostdata(sd, mctl);
spin_lock_init(&axi_ctrl->tasklet_lock);
INIT_LIST_HEAD(&axi_ctrl->tasklet_q);
+ spin_lock_init(&axi_ctrl->share_ctrl->sd_notify_lock);
- axi_ctrl->vfebase = ioremap(axi_ctrl->vfemem->start,
+ axi_ctrl->share_ctrl->vfebase = ioremap(axi_ctrl->vfemem->start,
resource_size(axi_ctrl->vfemem));
- if (!axi_ctrl->vfebase) {
+ if (!axi_ctrl->share_ctrl->vfebase) {
rc = -ENOMEM;
pr_err("%s: vfe ioremap failed\n", __func__);
goto remap_failed;
}
- vfe32_ctrl->vfebase = axi_ctrl->vfebase;
-
if (axi_ctrl->fs_vfe == NULL) {
axi_ctrl->fs_vfe =
regulator_get(&axi_ctrl->pdev->dev, "fs_vfe");
@@ -3854,11 +4213,12 @@
msm_camio_bus_scale_cfg(
mctl->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
- if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ if (msm_camera_io_r(
+ axi_ctrl->share_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
VFE32_HW_NUMBER)
- vfe32_ctrl->register_total = VFE32_REGISTER_TOTAL;
+ axi_ctrl->share_ctrl->register_total = VFE32_REGISTER_TOTAL;
else
- vfe32_ctrl->register_total = VFE33_REGISTER_TOTAL;
+ axi_ctrl->share_ctrl->register_total = VFE33_REGISTER_TOTAL;
enable_irq(axi_ctrl->vfeirq->start);
@@ -3868,8 +4228,8 @@
regulator_put(axi_ctrl->fs_vfe);
axi_ctrl->fs_vfe = NULL;
fs_failed:
- iounmap(axi_ctrl->vfebase);
- axi_ctrl->vfebase = NULL;
+ iounmap(axi_ctrl->share_ctrl->vfebase);
+ axi_ctrl->share_ctrl->vfebase = NULL;
remap_failed:
disable_irq(axi_ctrl->vfeirq->start);
return rc;
@@ -3879,9 +4239,11 @@
struct msm_cam_media_controller *mctl)
{
int rc = 0;
+ struct vfe32_ctrl_type *vfe32_ctrl =
+ (struct vfe32_ctrl_type *)v4l2_get_subdevdata(sd);
v4l2_set_subdev_hostdata(sd, mctl);
- spin_lock_init(&vfe32_ctrl->stop_flag_lock);
+ spin_lock_init(&vfe32_ctrl->share_ctrl->stop_flag_lock);
spin_lock_init(&vfe32_ctrl->state_lock);
spin_lock_init(&vfe32_ctrl->io_lock);
spin_lock_init(&vfe32_ctrl->update_ack_lock);
@@ -3893,7 +4255,6 @@
spin_lock_init(&vfe32_ctrl->rs_ack_lock);
spin_lock_init(&vfe32_ctrl->cs_ack_lock);
spin_lock_init(&vfe32_ctrl->comp_stats_ack_lock);
- spin_lock_init(&vfe32_ctrl->sd_notify_lock);
vfe32_ctrl->update_linear = false;
vfe32_ctrl->update_rolloff = false;
@@ -3909,6 +4270,11 @@
struct msm_cam_media_controller *pmctl =
(struct msm_cam_media_controller *)v4l2_get_subdev_hostdata(sd);
struct axi_ctrl_t *axi_ctrl = v4l2_get_subdevdata(sd);
+ if (!axi_ctrl->share_ctrl->vfebase) {
+ pr_err("%s: base address unmapped\n", __func__);
+ return;
+ }
+
CDBG("%s, free_irq\n", __func__);
disable_irq(axi_ctrl->vfeirq->start);
tasklet_kill(&axi_ctrl->vfe32_tasklet);
@@ -3919,8 +4285,8 @@
regulator_put(axi_ctrl->fs_vfe);
axi_ctrl->fs_vfe = NULL;
}
- iounmap(axi_ctrl->vfebase);
- axi_ctrl->vfebase = NULL;
+ iounmap(axi_ctrl->share_ctrl->vfebase);
+ axi_ctrl->share_ctrl->vfebase = NULL;
if (atomic_read(&irq_cnt))
pr_warning("%s, Warning IRQ Count not ZERO\n", __func__);
@@ -3931,78 +4297,92 @@
void msm_vfe_subdev_release(struct v4l2_subdev *sd)
{
- vfe32_ctrl->vfebase = 0;
+ struct vfe32_ctrl_type *vfe32_ctrl =
+ (struct vfe32_ctrl_type *)v4l2_get_subdevdata(sd);
+ if (!vfe32_ctrl->share_ctrl->vfebase)
+ vfe32_ctrl->share_ctrl->vfebase = NULL;
}
-void axi_start(void)
+void axi_start(struct axi_ctrl_t *axi_ctrl)
{
- switch (vfe32_ctrl->operation_mode) {
+ switch (axi_ctrl->share_ctrl->operation_mode) {
case VFE_OUTPUTS_PREVIEW:
case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
- if (vfe32_ctrl->outpath.output_mode &
+ if (axi_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- } else if (vfe32_ctrl->outpath.output_mode &
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ } else if (axi_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out0.ch0]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out0.ch1]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out0.ch2]);
}
break;
default:
- if (vfe32_ctrl->outpath.output_mode &
+ if (axi_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- } else if (vfe32_ctrl->outpath.output_mode &
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out1.ch1]);
+ } else if (axi_ctrl->share_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- msm_camera_io_w(1, vfe32_ctrl->vfebase +
- vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch2]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out1.ch0]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out1.ch1]);
+ msm_camera_io_w(1, axi_ctrl->share_ctrl->vfebase +
+ vfe32_AXI_WM_CFG[axi_ctrl->
+ share_ctrl->outpath.out1.ch2]);
}
break;
}
}
-void axi_stop(void)
+void axi_stop(struct axi_ctrl_t *axi_ctrl)
{
uint8_t axiBusyFlag = true;
- /* axi halt command. */
+ /* axi halt command. */
msm_camera_io_w(AXI_HALT,
- vfe32_ctrl->vfebase + VFE_AXI_CMD);
+ axi_ctrl->share_ctrl->vfebase + VFE_AXI_CMD);
wmb();
while (axiBusyFlag) {
- if (msm_camera_io_r(vfe32_ctrl->vfebase + VFE_AXI_STATUS) & 0x1)
+ if (msm_camera_io_r(
+ axi_ctrl->share_ctrl->vfebase + VFE_AXI_STATUS) & 0x1)
axiBusyFlag = false;
}
/* Ensure the write order while writing
to the command register using the barrier */
msm_camera_io_w_mb(AXI_HALT_CLEAR,
- vfe32_ctrl->vfebase + VFE_AXI_CMD);
+ axi_ctrl->share_ctrl->vfebase + VFE_AXI_CMD);
/* after axi halt, then ok to apply global reset. */
/* enable reset_ack and async timer interrupt only while
stopping the pipeline.*/
msm_camera_io_w(0xf0000000,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
+ axi_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_0);
msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
- vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
+ axi_ctrl->share_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
- vfe32_ctrl->vfebase + VFE_GLOBAL_RESET);
+ axi_ctrl->share_ctrl->vfebase + VFE_GLOBAL_RESET);
}
static int msm_axi_config(struct v4l2_subdev *sd, void __user *arg)
@@ -4010,7 +4390,12 @@
struct msm_vfe_cfg_cmd cfgcmd;
struct msm_isp_cmd vfecmd;
int rc = 0;
+ struct axi_ctrl_t *axi_ctrl = v4l2_get_subdevdata(sd);
+ if (!axi_ctrl->share_ctrl->vfebase) {
+ pr_err("%s: base address unmapped\n", __func__);
+ return -EFAULT;
+ }
if (NULL != arg) {
if (copy_from_user(&cfgcmd, arg, sizeof(cfgcmd))) {
ERR_COPY_FROM_USER();
@@ -4043,7 +4428,7 @@
rc = -EFAULT;
break;
}
- vfe32_config_axi(OUTPUT_PRIM, axio);
+ vfe32_config_axi(axi_ctrl, OUTPUT_PRIM, axio);
kfree(axio);
}
break;
@@ -4062,7 +4447,7 @@
rc = -EFAULT;
break;
}
- vfe32_config_axi(OUTPUT_PRIM_ALL_CHNLS, axio);
+ vfe32_config_axi(axi_ctrl, OUTPUT_PRIM_ALL_CHNLS, axio);
kfree(axio);
}
break;
@@ -4081,7 +4466,7 @@
rc = -EFAULT;
break;
}
- vfe32_config_axi(OUTPUT_PRIM|OUTPUT_SEC, axio);
+ vfe32_config_axi(axi_ctrl, OUTPUT_PRIM|OUTPUT_SEC, axio);
kfree(axio);
}
break;
@@ -4100,7 +4485,8 @@
rc = -EFAULT;
break;
}
- vfe32_config_axi(OUTPUT_PRIM|OUTPUT_SEC_ALL_CHNLS, axio);
+ vfe32_config_axi(axi_ctrl,
+ OUTPUT_PRIM|OUTPUT_SEC_ALL_CHNLS, axio);
kfree(axio);
}
break;
@@ -4119,7 +4505,8 @@
rc = -EFAULT;
break;
}
- vfe32_config_axi(OUTPUT_PRIM_ALL_CHNLS|OUTPUT_SEC, axio);
+ vfe32_config_axi(axi_ctrl,
+ OUTPUT_PRIM_ALL_CHNLS|OUTPUT_SEC, axio);
kfree(axio);
}
break;
@@ -4128,10 +4515,10 @@
__func__, cfgcmd.cmd_type);
break;
case CMD_AXI_START:
- axi_start();
+ axi_start(axi_ctrl);
break;
case CMD_AXI_STOP:
- axi_stop();
+ axi_stop(axi_ctrl);
break;
default:
pr_err("%s Unsupported AXI configuration %x ", __func__,
@@ -4143,43 +4530,95 @@
static void msm_axi_process_irq(struct v4l2_subdev *sd, void *arg)
{
+ struct axi_ctrl_t *axi_ctrl = v4l2_get_subdevdata(sd);
uint32_t irqstatus = (uint32_t) arg;
+
+ if (!axi_ctrl->share_ctrl->vfebase) {
+ pr_err("%s: base address unmapped\n", __func__);
+ return;
+ }
/* next, check output path related interrupts. */
if (irqstatus &
VFE_IRQ_STATUS0_IMAGE_COMPOSIT_DONE0_MASK) {
CDBG("Image composite done 0 irq occured.\n");
- vfe32_process_output_path_irq_0();
+ vfe32_process_output_path_irq_0(axi_ctrl);
}
if (irqstatus &
VFE_IRQ_STATUS0_IMAGE_COMPOSIT_DONE1_MASK) {
CDBG("Image composite done 1 irq occured.\n");
- vfe32_process_output_path_irq_1();
+ vfe32_process_output_path_irq_1(axi_ctrl);
}
/* in snapshot mode if done then send
snapshot done message */
- if (vfe32_ctrl->operation_mode ==
+ if (axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_THUMB_AND_MAIN ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_THUMB_AND_JPEG ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_JPEG_AND_THUMB ||
- vfe32_ctrl->operation_mode ==
+ axi_ctrl->share_ctrl->operation_mode ==
VFE_OUTPUTS_RAW) {
- if ((vfe32_ctrl->outpath.out0.capture_cnt == 0)
- && (vfe32_ctrl->outpath.out1.
+ if ((axi_ctrl->share_ctrl->outpath.out0.capture_cnt == 0)
+ && (axi_ctrl->share_ctrl->outpath.out1.
capture_cnt == 0)) {
msm_camera_io_w_mb(
CAMIF_COMMAND_STOP_IMMEDIATELY,
- vfe32_ctrl->vfebase +
+ axi_ctrl->share_ctrl->vfebase +
VFE_CAMIF_COMMAND);
- vfe32_send_isp_msg(vfe32_ctrl,
+ vfe32_send_isp_msg(&axi_ctrl->subdev,
+ axi_ctrl->share_ctrl->vfeFrameId,
MSG_ID_SNAPSHOT_DONE);
}
}
}
+static int msm_axi_buf_cfg(struct v4l2_subdev *sd, void __user *arg)
+{
+ struct msm_camvfe_params *vfe_params =
+ (struct msm_camvfe_params *)arg;
+ struct msm_vfe_cfg_cmd *cmd = vfe_params->vfe_cfg;
+ struct axi_ctrl_t *axi_ctrl = v4l2_get_subdevdata(sd);
+ void *data = vfe_params->data;
+ int rc = 0;
+
+ if (!axi_ctrl->share_ctrl->vfebase) {
+ pr_err("%s: base address unmapped\n", __func__);
+ return -EFAULT;
+ }
+
+ switch (cmd->cmd_type) {
+ case CMD_CONFIG_PING_ADDR: {
+ int path = *((int *)cmd->value);
+ struct vfe32_output_ch *outch =
+ vfe32_get_ch(path, axi_ctrl->share_ctrl);
+ outch->ping = *((struct msm_free_buf *)data);
+ }
+ break;
+
+ case CMD_CONFIG_PONG_ADDR: {
+ int path = *((int *)cmd->value);
+ struct vfe32_output_ch *outch =
+ vfe32_get_ch(path, axi_ctrl->share_ctrl);
+ outch->pong = *((struct msm_free_buf *)data);
+ }
+ break;
+
+ case CMD_CONFIG_FREE_BUF_ADDR: {
+ int path = *((int *)cmd->value);
+ struct vfe32_output_ch *outch =
+ vfe32_get_ch(path, axi_ctrl->share_ctrl);
+ outch->free_buf = *((struct msm_free_buf *)data);
+ }
+ break;
+ default:
+ pr_err("%s Unsupported AXI Buf config %x ", __func__,
+ cmd->cmd_type);
+ }
+ return rc;
+};
+
static const struct v4l2_subdev_internal_ops msm_vfe_internal_ops;
static long msm_axi_subdev_ioctl(struct v4l2_subdev *sd,
@@ -4198,6 +4637,10 @@
msm_axi_process_irq(sd, arg);
rc = 0;
break;
+ case VIDIOC_MSM_AXI_BUF_CFG:
+ msm_axi_buf_cfg(sd, arg);
+ rc = 0;
+ break;
case VIDIOC_MSM_AXI_RELEASE:
msm_axi_subdev_release(sd);
rc = 0;
@@ -4227,14 +4670,36 @@
{
int rc = 0;
struct axi_ctrl_t *axi_ctrl;
+ struct vfe32_ctrl_type *vfe32_ctrl;
+ struct vfe_share_ctrl_t *share_ctrl;
CDBG("%s: device id = %d\n", __func__, pdev->id);
- vfe32_ctrl = kzalloc(sizeof(struct vfe32_ctrl_type), GFP_KERNEL);
- if (!vfe32_ctrl) {
+
+ share_ctrl = kzalloc(sizeof(struct vfe_share_ctrl_t), GFP_KERNEL);
+ if (!share_ctrl) {
pr_err("%s: no enough memory\n", __func__);
return -ENOMEM;
}
axi_ctrl = kzalloc(sizeof(struct axi_ctrl_t), GFP_KERNEL);
+ if (!axi_ctrl) {
+ pr_err("%s: no enough memory\n", __func__);
+ kfree(share_ctrl);
+ return -ENOMEM;
+ }
+
+ vfe32_ctrl = kzalloc(sizeof(struct vfe32_ctrl_type), GFP_KERNEL);
+ if (!vfe32_ctrl) {
+ pr_err("%s: no enough memory\n", __func__);
+ kfree(share_ctrl);
+ kfree(axi_ctrl);
+ return -ENOMEM;
+ }
+
+ share_ctrl->axi_ctrl = axi_ctrl;
+ share_ctrl->vfe32_ctrl = vfe32_ctrl;
+ axi_ctrl->share_ctrl = share_ctrl;
+ vfe32_ctrl->share_ctrl = share_ctrl;
+
v4l2_subdev_init(&axi_ctrl->subdev, &msm_axi_subdev_ops);
axi_ctrl->subdev.internal_ops = &msm_axi_internal_ops;
axi_ctrl->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
diff --git a/drivers/media/video/msm/msm_vfe32.h b/drivers/media/video/msm/msm_vfe32.h
index d1faded..086600a 100644
--- a/drivers/media/video/msm/msm_vfe32.h
+++ b/drivers/media/video/msm/msm_vfe32.h
@@ -900,6 +900,30 @@
uint32_t droppedStatsFrameCount;
uint32_t bufToRender;
};
+struct axi_ctrl_t;
+struct vfe32_ctrl_type;
+
+struct vfe_share_ctrl_t {
+ void __iomem *vfebase;
+ uint32_t register_total;
+
+ atomic_t vstate;
+ uint32_t vfeFrameId;
+ uint32_t stats_comp;
+ spinlock_t stop_flag_lock;
+ int8_t stop_ack_pending;
+ enum vfe_output_state liveshot_state;
+ uint32_t vfe_capture_count;
+
+ uint16_t operation_mode; /* streaming or snapshot */
+ struct vfe32_output_path outpath;
+
+ uint32_t ref_count;
+ spinlock_t sd_notify_lock;
+
+ struct axi_ctrl_t *axi_ctrl;
+ struct vfe32_ctrl_type *vfe32_ctrl;
+};
struct axi_ctrl_t {
struct v4l2_subdev subdev;
@@ -908,7 +932,6 @@
spinlock_t tasklet_lock;
struct list_head tasklet_q;
- void __iomem *vfebase;
void *syncdata;
struct resource *vfemem;
@@ -916,15 +939,12 @@
struct regulator *fs_vfe;
struct clk *vfe_clk[3];
struct tasklet_struct vfe32_tasklet;
+ struct vfe_share_ctrl_t *share_ctrl;
};
struct vfe32_ctrl_type {
- uint16_t operation_mode; /* streaming or snapshot */
- struct vfe32_output_path outpath;
-
uint32_t vfeImaskCompositePacked;
- spinlock_t stop_flag_lock;
spinlock_t update_ack_lock;
spinlock_t state_lock;
spinlock_t io_lock;
@@ -941,7 +961,6 @@
void *extdata;
int8_t start_ack_pending;
- int8_t stop_ack_pending;
int8_t reset_ack_pending;
int8_t update_ack_pending;
enum vfe_output_state recording_state;
@@ -949,19 +968,13 @@
int8_t update_rolloff;
int8_t update_la;
int8_t update_gamma;
- enum vfe_output_state liveshot_state;
- void __iomem *vfebase;
- uint32_t register_total;
+ struct vfe_share_ctrl_t *share_ctrl;
- uint32_t stats_comp;
- atomic_t vstate;
- uint32_t vfe_capture_count;
uint32_t sync_timer_repeat_count;
uint32_t sync_timer_state;
uint32_t sync_timer_number;
- uint32_t vfeFrameId;
uint32_t output1Pattern;
uint32_t output1Period;
uint32_t output2Pattern;
@@ -978,7 +991,6 @@
/* v4l2 subdev */
struct v4l2_subdev subdev;
struct platform_device *pdev;
- spinlock_t sd_notify_lock;
uint32_t hfr_mode;
uint32_t frame_skip_cnt;
uint32_t frame_skip_pattern;
@@ -1015,4 +1027,7 @@
#define VIDIOC_MSM_AXI_IRQ \
_IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *)
+#define VIDIOC_MSM_AXI_BUF_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *)
+
#endif /* __MSM_VFE32_H__ */
diff --git a/drivers/media/video/msm/server/msm_cam_server.c b/drivers/media/video/msm/server/msm_cam_server.c
index 1f20c8a..cb59737 100644
--- a/drivers/media/video/msm/server/msm_cam_server.c
+++ b/drivers/media/video/msm/server/msm_cam_server.c
@@ -560,55 +560,52 @@
}
int msm_server_proc_ctrl_cmd(struct msm_cam_v4l2_device *pcam,
- struct v4l2_control *ctrl, int is_set_cmd)
+ struct msm_camera_v4l2_ioctl_t *ioctl_ptr, int is_set_cmd)
{
int rc = 0;
- struct msm_ctrl_cmd ctrlcmd, *tmp_cmd;
+ struct msm_ctrl_cmd ctrlcmd, tmp_cmd, *cmd_ptr;
uint8_t *ctrl_data = NULL;
- void __user *uptr_cmd;
- void __user *uptr_value;
uint32_t cmd_len = sizeof(struct msm_ctrl_cmd);
uint32_t value_len;
- tmp_cmd = (struct msm_ctrl_cmd *)ctrl->value;
- uptr_cmd = (void __user *)ctrl->value;
- uptr_value = (void __user *)tmp_cmd->value;
- value_len = tmp_cmd->length;
-
- D("%s: cmd type = %d, up1=0x%x, ulen1=%d, up2=0x%x, ulen2=%d\n",
- __func__, tmp_cmd->type, (uint32_t)uptr_cmd, cmd_len,
- (uint32_t)uptr_value, tmp_cmd->length);
-
- ctrl_data = kzalloc(value_len+cmd_len, GFP_KERNEL);
- if (ctrl_data == 0) {
- pr_err("%s could not allocate memory\n", __func__);
- rc = -ENOMEM;
- goto end;
- }
- tmp_cmd = (struct msm_ctrl_cmd *)ctrl_data;
- if (copy_from_user((void *)ctrl_data, uptr_cmd,
- cmd_len)) {
+ if (copy_from_user(&tmp_cmd,
+ (void __user *)ioctl_ptr->ioctl_ptr, cmd_len)) {
pr_err("%s: copy_from_user failed.\n", __func__);
rc = -EINVAL;
goto end;
}
- tmp_cmd->value = (void *)(ctrl_data+cmd_len);
- if (uptr_value && tmp_cmd->length > 0) {
- if (copy_from_user((void *)tmp_cmd->value, uptr_value,
- value_len)) {
- pr_err("%s: copy_from_user failed, size=%d\n",
- __func__, value_len);
+ value_len = tmp_cmd.length;
+ ctrl_data = kzalloc(value_len+cmd_len, GFP_KERNEL);
+ if (!ctrl_data) {
+ pr_err("%s could not allocate memory\n", __func__);
+ rc = -ENOMEM;
+ goto end;
+ }
+
+ cmd_ptr = (struct msm_ctrl_cmd *) ctrl_data;
+ *cmd_ptr = tmp_cmd;
+ if (tmp_cmd.value && tmp_cmd.length > 0) {
+ cmd_ptr->value = (void *)(ctrl_data+cmd_len);
+ if (copy_from_user((void *)cmd_ptr->value,
+ (void __user *)tmp_cmd.value,
+ value_len)) {
+ pr_err("%s: copy_from_user failed.\n", __func__);
rc = -EINVAL;
goto end;
}
- } else
- tmp_cmd->value = NULL;
+ } else {
+ cmd_ptr->value = NULL;
+ }
+
+ D("%s: cmd type = %d, up1=0x%x, ulen1=%d, up2=0x%x, ulen2=%d\n",
+ __func__, tmp_cmd.type, (uint32_t)ioctl_ptr->ioctl_ptr, cmd_len,
+ (uint32_t)tmp_cmd.value, tmp_cmd.length);
ctrlcmd.type = MSM_V4L2_SET_CTRL_CMD;
ctrlcmd.length = cmd_len + value_len;
ctrlcmd.value = (void *)ctrl_data;
- if (tmp_cmd->timeout_ms > 0)
- ctrlcmd.timeout_ms = tmp_cmd->timeout_ms;
+ if (tmp_cmd.timeout_ms > 0)
+ ctrlcmd.timeout_ms = tmp_cmd.timeout_ms;
else
ctrlcmd.timeout_ms = 1000;
ctrlcmd.vnode_id = pcam->vnode_id;
@@ -618,17 +615,17 @@
rc = msm_server_control(&g_server_dev, &ctrlcmd);
D("%s: msm_server_control rc=%d\n", __func__, rc);
if (rc == 0) {
- if (uptr_value && tmp_cmd->length > 0 &&
- copy_to_user((void __user *)uptr_value,
- (void *)(ctrl_data+cmd_len), tmp_cmd->length)) {
+ if (tmp_cmd.value && tmp_cmd.length > 0 &&
+ copy_to_user((void __user *)tmp_cmd.value,
+ (void *)(ctrl_data+cmd_len), tmp_cmd.length)) {
pr_err("%s: copy_to_user failed, size=%d\n",
- __func__, tmp_cmd->length);
+ __func__, tmp_cmd.length);
rc = -EINVAL;
goto end;
}
- tmp_cmd->value = uptr_value;
- if (copy_to_user((void __user *)uptr_cmd,
- (void *)tmp_cmd, cmd_len)) {
+
+ if (copy_to_user((void __user *)ioctl_ptr->ioctl_ptr,
+ (void *)&tmp_cmd, cmd_len)) {
pr_err("%s: copy_to_user failed in cpy, size=%d\n",
__func__, cmd_len);
rc = -EINVAL;
@@ -637,8 +634,8 @@
}
end:
D("%s: END, type = %d, vaddr = 0x%x, vlen = %d, status = %d, rc = %d\n",
- __func__, tmp_cmd->type, (uint32_t)tmp_cmd->value,
- tmp_cmd->length, tmp_cmd->status, rc);
+ __func__, tmp_cmd.type, (uint32_t)tmp_cmd.value,
+ tmp_cmd.length, tmp_cmd.status, rc);
kfree(ctrl_data);
return rc;
}
@@ -655,8 +652,6 @@
pr_err("%s Invalid control\n", __func__);
return -EINVAL;
}
- if (ctrl->id == MSM_V4L2_PID_CTRL_CMD)
- return msm_server_proc_ctrl_cmd(pcam, ctrl, 1);
memset(ctrl_data, 0, sizeof(ctrl_data));
@@ -687,8 +682,6 @@
pr_err("%s Invalid control\n", __func__);
return -EINVAL;
}
- if (ctrl->id == MSM_V4L2_PID_CTRL_CMD)
- return msm_server_proc_ctrl_cmd(pcam, ctrl, 0);
memset(ctrl_data, 0, sizeof(ctrl_data));
diff --git a/drivers/media/video/msm/server/msm_cam_server.h b/drivers/media/video/msm/server/msm_cam_server.h
index 2fe4c2b..677feaa 100644
--- a/drivers/media/video/msm/server/msm_cam_server.h
+++ b/drivers/media/video/msm/server/msm_cam_server.h
@@ -36,7 +36,7 @@
int msm_server_get_usecount(void);
int32_t msm_find_free_queue(void);
int msm_server_proc_ctrl_cmd(struct msm_cam_v4l2_device *pcam,
- struct v4l2_control *ctrl, int is_set_cmd);
+ struct msm_camera_v4l2_ioctl_t *ioctl_ptr, int is_set_cmd);
int msm_server_s_ctrl(struct msm_cam_v4l2_device *pcam,
struct v4l2_control *ctrl);
int msm_server_g_ctrl(struct msm_cam_v4l2_device *pcam,
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 2558c96..1331aa4 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -1382,6 +1382,7 @@
if (mq->num_of_potential_packed_wr_reqs >
mq->num_wr_reqs_to_start_packing)
mq->wr_packing_enabled = true;
+ mq->num_of_potential_packed_wr_reqs = 0;
return;
}
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 1b4eb61..eba80c5 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -2341,8 +2341,8 @@
static inline void msmsdcc_setup_clocks(struct msmsdcc_host *host, bool enable)
{
if (enable) {
- if (!IS_ERR_OR_NULL(host->dfab_pclk))
- clk_prepare_enable(host->dfab_pclk);
+ if (!IS_ERR_OR_NULL(host->bus_clk))
+ clk_prepare_enable(host->bus_clk);
if (!IS_ERR(host->pclk))
clk_prepare_enable(host->pclk);
clk_prepare_enable(host->clk);
@@ -2354,8 +2354,8 @@
clk_disable_unprepare(host->clk);
if (!IS_ERR(host->pclk))
clk_disable_unprepare(host->pclk);
- if (!IS_ERR_OR_NULL(host->dfab_pclk))
- clk_disable_unprepare(host->dfab_pclk);
+ if (!IS_ERR_OR_NULL(host->bus_clk))
+ clk_disable_unprepare(host->bus_clk);
}
}
@@ -2877,13 +2877,14 @@
DBG(host, "ios->clock = %u\n", ios->clock);
spin_lock_irqsave(&host->lock, flags);
if (!host->sdcc_irq_disabled) {
- spin_unlock_irqrestore(&host->lock, flags);
- disable_irq(host->core_irqres->start);
- spin_lock_irqsave(&host->lock, flags);
+ disable_irq_nosync(host->core_irqres->start);
host->sdcc_irq_disabled = 1;
}
spin_unlock_irqrestore(&host->lock, flags);
+ /* Make sure sdcc core irq is synchronized */
+ synchronize_irq(host->core_irqres->start);
+
pwr = msmsdcc_setup_pwr(host, ios);
spin_lock_irqsave(&host->lock, flags);
@@ -4828,21 +4829,17 @@
}
/*
- * Setup SDCC clock if derived from Dayatona
- * fabric core clock.
+ * Setup SDCC bus voter clock.
*/
- if (plat->pclk_src_dfab) {
- host->dfab_pclk = clk_get(&pdev->dev, "bus_clk");
- if (!IS_ERR(host->dfab_pclk)) {
- /* Set the clock rate to 64MHz for max. performance */
- ret = clk_set_rate(host->dfab_pclk, 64000000);
- if (ret)
- goto dfab_pclk_put;
- ret = clk_prepare_enable(host->dfab_pclk);
- if (ret)
- goto dfab_pclk_put;
- } else
- goto dma_free;
+ host->bus_clk = clk_get(&pdev->dev, "bus_clk");
+ if (!IS_ERR_OR_NULL(host->bus_clk)) {
+ /* Vote for max. clk rate for max. performance */
+ ret = clk_set_rate(host->bus_clk, INT_MAX);
+ if (ret)
+ goto bus_clk_put;
+ ret = clk_prepare_enable(host->bus_clk);
+ if (ret)
+ goto bus_clk_put;
}
/*
@@ -5229,12 +5226,11 @@
pclk_put:
if (!IS_ERR(host->pclk))
clk_put(host->pclk);
- if (!IS_ERR_OR_NULL(host->dfab_pclk))
- clk_disable_unprepare(host->dfab_pclk);
- dfab_pclk_put:
- if (!IS_ERR_OR_NULL(host->dfab_pclk))
- clk_put(host->dfab_pclk);
- dma_free:
+ if (!IS_ERR_OR_NULL(host->bus_clk))
+ clk_disable_unprepare(host->bus_clk);
+ bus_clk_put:
+ if (!IS_ERR_OR_NULL(host->bus_clk))
+ clk_put(host->bus_clk);
if (host->is_dma_mode) {
if (host->dmares)
dma_free_coherent(NULL,
@@ -5291,8 +5287,8 @@
clk_put(host->clk);
if (!IS_ERR(host->pclk))
clk_put(host->pclk);
- if (!IS_ERR_OR_NULL(host->dfab_pclk))
- clk_put(host->dfab_pclk);
+ if (!IS_ERR_OR_NULL(host->bus_clk))
+ clk_put(host->bus_clk);
if (host->cpu_dma_latency)
pm_qos_remove_request(&host->pm_qos_req_dma);
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 1fe5129..2222337 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -350,7 +350,7 @@
struct mmc_host *mmc;
struct clk *clk; /* main MMC bus clock */
struct clk *pclk; /* SDCC peripheral bus clock */
- struct clk *dfab_pclk; /* Daytona Fabric SDCC clock */
+ struct clk *bus_clk; /* SDCC bus voter clock */
unsigned int clks_on; /* set if clocks are enabled */
unsigned int eject; /* eject state */
diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig
index b8d1df8..7777154 100644
--- a/drivers/video/msm/Kconfig
+++ b/drivers/video/msm/Kconfig
@@ -297,6 +297,11 @@
select FB_MSM_LVDS
default n
+config FB_MSM_LVDS_FRC_FHD
+ bool
+ select FB_MSM_LVDS
+ default n
+
config FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
bool
select FB_MSM_MIPI_DSI_TOSHIBA
@@ -490,6 +495,15 @@
---help---
Support for LVDS Chimei WXGA(1366x768) panel
+config FB_MSM_LVDS_FRC_FHD_PANEL
+ bool "LVDS FRC FHD Panel"
+ select FB_MSM_LVDS_FRC_FHD
+ ---help---
+ Support for LVDS Frc FHD(1920x1080) panel
+ FRC(Frame Rate Converter) uses LVDS as input
+ interface. It is treated as a HDMI panel with
+ 1920x1080 resolution.
+
config FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
depends on FB_MSM_LCDC_HW
bool "MDDI Panel Auto Detect + LCDC Prism WVGA"
@@ -568,6 +582,7 @@
config FB_MSM_LVDS_MIPI_PANEL_DETECT
bool "LVDS + MIPI Panel Auto Detect"
select FB_MSM_LVDS_CHIMEI_WXGA
+ select FB_MSM_LVDS_FRC_FHD
select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA
diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile
index b2ecb08..e4a0948 100644
--- a/drivers/video/msm/Makefile
+++ b/drivers/video/msm/Makefile
@@ -165,6 +165,7 @@
obj-$(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) += adv7520.o
obj-$(CONFIG_FB_MSM_LCDC_ST15_WXGA) += lcdc_st15.o
obj-$(CONFIG_FB_MSM_LVDS_CHIMEI_WXGA) += lvds_chimei_wxga.o
+obj-$(CONFIG_FB_MSM_LVDS_FRC_FHD) += lvds_frc_fhd.o
obj-$(CONFIG_FB_MSM_HDMI_MSM_PANEL) += hdmi_msm.o
obj-$(CONFIG_FB_MSM_EXT_INTERFACE_COMMON) += external_common.o
obj-$(CONFIG_FB_MSM_LCDC_TRULY_HVGA_IPS3P2335) += lcdc_truly_ips3p2335.o
diff --git a/drivers/video/msm/lvds.c b/drivers/video/msm/lvds.c
index 6323423..f5d8201 100644
--- a/drivers/video/msm/lvds.c
+++ b/drivers/video/msm/lvds.c
@@ -33,6 +33,9 @@
#include "msm_fb.h"
#include "mdp4.h"
+
+#define LVDS_PIXEL_MAP_PATTERN_2 2
+
static int lvds_probe(struct platform_device *pdev);
static int lvds_remove(struct platform_device *pdev);
@@ -65,14 +68,39 @@
usleep(1000);
/* LVDS PHY PLL configuration */
- MDP_OUTP(MDP_BASE + 0xc3004, 0x62);
- MDP_OUTP(MDP_BASE + 0xc3008, 0x30);
- MDP_OUTP(MDP_BASE + 0xc300c, 0xc4);
- MDP_OUTP(MDP_BASE + 0xc3014, 0x10);
- MDP_OUTP(MDP_BASE + 0xc3018, 0x05);
- MDP_OUTP(MDP_BASE + 0xc301c, 0x62);
- MDP_OUTP(MDP_BASE + 0xc3020, 0x41);
- MDP_OUTP(MDP_BASE + 0xc3024, 0x0d);
+ if (mfd->panel_info.clk_rate == 74250000) {
+ MDP_OUTP(MDP_BASE + 0xc3000, 0x08);
+ MDP_OUTP(MDP_BASE + 0xc3004, 0x4c);
+ MDP_OUTP(MDP_BASE + 0xc3008, 0x30);
+ MDP_OUTP(MDP_BASE + 0xc300c, 0xc3);
+ MDP_OUTP(MDP_BASE + 0xc3014, 0x10);
+ MDP_OUTP(MDP_BASE + 0xc3018, 0x04);
+ MDP_OUTP(MDP_BASE + 0xc301c, 0x62);
+ MDP_OUTP(MDP_BASE + 0xc3020, 0x41);
+ MDP_OUTP(MDP_BASE + 0xc3024, 0x0d);
+ MDP_OUTP(MDP_BASE + 0xc3028, 0x07);
+ MDP_OUTP(MDP_BASE + 0xc302c, 0x00);
+ MDP_OUTP(MDP_BASE + 0xc3030, 0x1c);
+ MDP_OUTP(MDP_BASE + 0xc3034, 0x01);
+ MDP_OUTP(MDP_BASE + 0xc3038, 0x00);
+ MDP_OUTP(MDP_BASE + 0xc3040, 0xC0);
+ MDP_OUTP(MDP_BASE + 0xc3044, 0x00);
+ MDP_OUTP(MDP_BASE + 0xc3048, 0x30);
+ MDP_OUTP(MDP_BASE + 0xc304c, 0x00);
+
+ MDP_OUTP(MDP_BASE + 0xc3000, 0x11);
+ MDP_OUTP(MDP_BASE + 0xc3064, 0x05);
+ MDP_OUTP(MDP_BASE + 0xc3050, 0x20);
+ } else {
+ MDP_OUTP(MDP_BASE + 0xc3004, 0x62);
+ MDP_OUTP(MDP_BASE + 0xc3008, 0x30);
+ MDP_OUTP(MDP_BASE + 0xc300c, 0xc4);
+ MDP_OUTP(MDP_BASE + 0xc3014, 0x10);
+ MDP_OUTP(MDP_BASE + 0xc3018, 0x05);
+ MDP_OUTP(MDP_BASE + 0xc301c, 0x62);
+ MDP_OUTP(MDP_BASE + 0xc3020, 0x41);
+ MDP_OUTP(MDP_BASE + 0xc3024, 0x0d);
+ }
MDP_OUTP(MDP_BASE + 0xc3000, 0x01);
/* Wait until LVDS PLL is locked and ready */
@@ -99,22 +127,42 @@
if (lvds_pdata &&
lvds_pdata->lvds_pixel_remap &&
lvds_pdata->lvds_pixel_remap()) {
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
- MDP_OUTP(MDP_BASE + 0xc2014, 0x05080001);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
- MDP_OUTP(MDP_BASE + 0xc2018, 0x00020304);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
- MDP_OUTP(MDP_BASE + 0xc201c, 0x1011090a);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
- MDP_OUTP(MDP_BASE + 0xc2020, 0x000b0c0d);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
- MDP_OUTP(MDP_BASE + 0xc2024, 0x191a1213);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
- MDP_OUTP(MDP_BASE + 0xc2028, 0x00141518);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
- MDP_OUTP(MDP_BASE + 0xc202c, 0x171b0607);
- /* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
- MDP_OUTP(MDP_BASE + 0xc2030, 0x000e0f16);
+ if (lvds_pdata->lvds_pixel_remap() ==
+ LVDS_PIXEL_MAP_PATTERN_2) {
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc2014, 0x070A1B1B);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2018, 0x00040506);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc201c, 0x12131B1B);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2020, 0x000B0C0D);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc2024, 0x191A1B1B);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2028, 0x00141518);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc202c, 0x171B1B1B);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2030, 0x000e0f16);
+ } else {
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc2014, 0x05080001);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2018, 0x00020304);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc201c, 0x1011090a);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2020, 0x000b0c0d);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc2024, 0x191a1213);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2028, 0x00141518);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
+ MDP_OUTP(MDP_BASE + 0xc202c, 0x171b0607);
+ /* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
+ MDP_OUTP(MDP_BASE + 0xc2030, 0x000e0f16);
+ }
} else {
/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
MDP_OUTP(MDP_BASE + 0xc2014, 0x03040508);
@@ -135,7 +183,7 @@
}
if (mfd->panel_info.lvds.channel_mode ==
LVDS_DUAL_CHANNEL_MODE) {
- lvds_intf = 0x0001ff80;
+ lvds_intf = 0x0003ff80;
lvds_phy_cfg0 = BIT(6) | BIT(7);
if (mfd->panel_info.lvds.channel_swap)
lvds_intf |= BIT(4);
@@ -159,7 +207,7 @@
if (mfd->panel_info.lvds.channel_mode ==
LVDS_DUAL_CHANNEL_MODE) {
- lvds_intf = 0x00017788;
+ lvds_intf = 0x00037788;
lvds_phy_cfg0 = BIT(6) | BIT(7);
if (mfd->panel_info.lvds.channel_swap)
lvds_intf |= BIT(4);
diff --git a/drivers/video/msm/lvds_frc_fhd.c b/drivers/video/msm/lvds_frc_fhd.c
new file mode 100644
index 0000000..7739588
--- /dev/null
+++ b/drivers/video/msm/lvds_frc_fhd.c
@@ -0,0 +1,201 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <mach/gpio.h>
+#include "msm_fb.h"
+
+static struct lvds_panel_platform_data *frc_pdata;
+static struct platform_device *frc_fbpdev;
+static int gpio_update; /* 268 */
+static int gpio_reset; /* 269 */
+static int gpio_pwr; /* 270 */
+
+static int lvds_frc_panel_on(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = gpio_request(gpio_pwr, "frc_pwr");
+ if (ret) {
+ pr_err("%s: gpio_pwr=%d, gpio_request failed\n",
+ __func__, gpio_pwr);
+ goto panel_on_exit;
+ }
+ ret = gpio_request(gpio_update, "frc_update");
+ if (ret) {
+ pr_err("%s: gpio_update=%d, gpio_request failed\n",
+ __func__, gpio_update);
+ goto panel_on_exit1;
+ }
+ ret = gpio_request(gpio_reset, "frc_reset");
+ if (ret) {
+ pr_err("%s: gpio_reset=%d, gpio_request failed\n",
+ __func__, gpio_reset);
+ goto panel_on_exit2;
+ }
+
+ gpio_direction_output(gpio_reset, 1);
+ gpio_direction_output(gpio_pwr, 0);
+ gpio_direction_output(gpio_update, 0);
+ usleep(1000);
+ gpio_direction_output(gpio_reset, 0);
+ usleep(1000);
+ gpio_direction_output(gpio_pwr, 1);
+ usleep(1000);
+ gpio_direction_output(gpio_update, 1);
+ usleep(1000);
+ gpio_direction_output(gpio_reset, 1);
+ usleep(1000);
+ gpio_free(gpio_reset);
+panel_on_exit2:
+ gpio_free(gpio_update);
+panel_on_exit1:
+ gpio_free(gpio_pwr);
+panel_on_exit:
+ return ret;
+}
+
+static int lvds_frc_panel_off(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = gpio_request(gpio_pwr, "frc_pwr");
+ if (ret) {
+ pr_err("%s: gpio_pwr=%d, gpio_request failed\n",
+ __func__, gpio_pwr);
+ goto panel_off_exit;
+ }
+ ret = gpio_request(gpio_update, "frc_update");
+ if (ret) {
+ pr_err("%s: gpio_update=%d, gpio_request failed\n",
+ __func__, gpio_update);
+ goto panel_off_exit1;
+ }
+ ret = gpio_request(gpio_reset, "frc_reset");
+ if (ret) {
+ pr_err("%s: gpio_reset=%d, gpio_request failed\n",
+ __func__, gpio_reset);
+ goto panel_off_exit2;
+ }
+ gpio_direction_output(gpio_reset, 0);
+ usleep(1000);
+ gpio_direction_output(gpio_update, 0);
+ usleep(1000);
+ gpio_direction_output(gpio_pwr, 0);
+ usleep(1000);
+ gpio_free(gpio_reset);
+panel_off_exit2:
+ gpio_free(gpio_update);
+panel_off_exit1:
+ gpio_free(gpio_pwr);
+panel_off_exit:
+ return ret;
+}
+
+static int __devinit lvds_frc_probe(struct platform_device *pdev)
+{
+ int rc = 0;
+
+ if (pdev->id == 0) {
+ frc_pdata = pdev->dev.platform_data;
+ if (frc_pdata != NULL) {
+ gpio_update = frc_pdata->gpio[0];
+ gpio_reset = frc_pdata->gpio[1];
+ gpio_pwr = frc_pdata->gpio[2];
+ pr_info("%s: power=%d update=%d reset=%d\n",
+ __func__, gpio_pwr, gpio_update, gpio_reset);
+ }
+ return 0;
+ }
+
+ frc_fbpdev = msm_fb_add_device(pdev);
+ if (!frc_fbpdev) {
+ dev_err(&pdev->dev, "failed to add msm_fb device\n");
+ rc = -ENODEV;
+ goto probe_exit;
+ }
+
+probe_exit:
+ return rc;
+}
+
+static struct platform_driver this_driver = {
+ .probe = lvds_frc_probe,
+ .driver = {
+ .name = "lvds_frc_fhd",
+ },
+};
+
+static struct msm_fb_panel_data lvds_frc_panel_data = {
+ .on = lvds_frc_panel_on,
+ .off = lvds_frc_panel_off,
+};
+
+static struct platform_device this_device = {
+ .name = "lvds_frc_fhd",
+ .id = 1,
+ .dev = {
+ .platform_data = &lvds_frc_panel_data,
+ }
+};
+
+static int __init lvds_frc_fhd_init(void)
+{
+ int ret;
+ struct msm_panel_info *pinfo;
+
+ if (msm_fb_detect_client("lvds_frc_fhd"))
+ return 0;
+
+ ret = platform_driver_register(&this_driver);
+ if (ret)
+ return ret;
+
+ pinfo = &lvds_frc_panel_data.panel_info;
+ pinfo->xres = 1920;
+ pinfo->yres = 1080;
+ MSM_FB_SINGLE_MODE_PANEL(pinfo);
+ pinfo->type = LVDS_PANEL;
+ pinfo->pdest = DISPLAY_1;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = 24;
+ pinfo->fb_num = 2;
+ pinfo->clk_rate = 74250000;
+ pinfo->bl_max = 255;
+ pinfo->bl_min = 1;
+
+ /*
+ * use hdmi 1080p60 setting, for dual channel mode,
+ * horizontal length is half.
+ */
+ pinfo->lcdc.h_back_porch = 148/2;
+ pinfo->lcdc.h_front_porch = 88/2;
+ pinfo->lcdc.h_pulse_width = 44/2;
+ pinfo->lcdc.v_back_porch = 36;
+ pinfo->lcdc.v_front_porch = 4;
+ pinfo->lcdc.v_pulse_width = 5;
+ pinfo->lcdc.underflow_clr = 0xff;
+ pinfo->lcdc.hsync_skew = 0;
+ pinfo->lvds.channel_mode = LVDS_DUAL_CHANNEL_MODE;
+ pinfo->lcdc.is_sync_active_high = TRUE;
+
+ /* Set border color, padding only for reducing active display region */
+ pinfo->lcdc.border_clr = 0x0;
+ pinfo->lcdc.xres_pad = 0;
+ pinfo->lcdc.yres_pad = 0;
+
+ ret = platform_device_register(&this_device);
+ if (ret)
+ platform_driver_unregister(&this_driver);
+
+ return ret;
+}
+
+module_init(lvds_frc_fhd_init);
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index 18d2107..8410592 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -181,7 +181,12 @@
lcdc_bpp = mfd->panel_info.bpp;
hsync_period =
- hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;
+ hsync_pulse_width + h_back_porch + h_front_porch;
+ if ((mfd->panel_info.type == LVDS_PANEL) &&
+ (mfd->panel_info.lvds.channel_mode == LVDS_DUAL_CHANNEL_MODE))
+ hsync_period += lcdc_width / 2;
+ else
+ hsync_period += lcdc_width;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = hsync_pulse_width + h_back_porch;
hsync_end_x = hsync_period - h_front_porch - 1;
@@ -216,8 +221,13 @@
#ifdef CONFIG_FB_MSM_MDP40
- hsync_polarity = 1;
- vsync_polarity = 1;
+ if (mfd->panel_info.lcdc.is_sync_active_high) {
+ hsync_polarity = 0;
+ vsync_polarity = 0;
+ } else {
+ hsync_polarity = 1;
+ vsync_polarity = 1;
+ }
lcdc_underflow_clr |= 0x80000000; /* enable recovery */
#else
hsync_polarity = 0;
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index 3ed305b..c9642c3 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -1316,7 +1316,7 @@
GEN_POOL,
fbi->fix.smem_len,
SZ_4K,
- 1,
+ 0,
&(mfd->display_iova));
msm_iommu_map_contig_buffer(fbi->fix.smem_start,
@@ -1324,7 +1324,7 @@
GEN_POOL,
fbi->fix.smem_len,
SZ_4K,
- 1,
+ 0,
&(mfd->rotator_iova));
if (!bf_supported || mfd->index == 0)
diff --git a/drivers/video/msm/msm_fb_panel.h b/drivers/video/msm/msm_fb_panel.h
index 8ccc21c..a2c3db1 100644
--- a/drivers/video/msm/msm_fb_panel.h
+++ b/drivers/video/msm/msm_fb_panel.h
@@ -82,6 +82,7 @@
uint32 xres_pad;
/* Pad height */
uint32 yres_pad;
+ boolean is_sync_active_high;
};
struct mddi_panel_info {
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index 7b5e841..271079e 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -1450,19 +1450,19 @@
#define QCAMERA_VNODE_GROUP_ID 2
#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \
- _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t *)
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \
- _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t *)
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \
- _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t *)
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \
- _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t *)
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \
- _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t *)
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
#define MSM_CAM_IOCTL_SEND_EVENT \
_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event)
@@ -1470,8 +1470,13 @@
#define MSM_CAM_V4L2_IOCTL_CFG_VPE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd)
+#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
+
struct msm_camera_v4l2_ioctl_t {
+ uint32_t id;
void __user *ioctl_ptr;
+ uint32_t len;
};
#endif /* __LINUX_MSM_CAMERA_H */
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 4b4dae1..9dcfc1c 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -5265,16 +5265,37 @@
wcd9xxx_unlock_sleep(core);
}
+static u16 tabla_get_cfilt_reg(struct snd_soc_codec *codec, u8 cfilt)
+{
+ u16 reg;
+
+ switch (cfilt) {
+ case TABLA_CFILT1_SEL:
+ reg = TABLA_A_MICB_CFILT_1_CTL;
+ break;
+ case TABLA_CFILT2_SEL:
+ reg = TABLA_A_MICB_CFILT_2_CTL;
+ break;
+ case TABLA_CFILT3_SEL:
+ reg = TABLA_A_MICB_CFILT_3_CTL;
+ break;
+ default:
+ BUG();
+ }
+ return reg;
+}
+
void tabla_mbhc_cal(struct snd_soc_codec *codec)
{
struct tabla_priv *tabla;
struct tabla_mbhc_btn_detect_cfg *btn_det;
- u8 cfilt_mode, bg_mode;
+ u8 cfilt_mode, micbias2_cfilt_mode, bg_mode;
u8 ncic, nmeas, navg;
u32 mclk_rate;
u32 dce_wait, sta_wait;
u8 *n_cic;
void *calibration;
+ u16 bias2_ctl;
tabla = snd_soc_codec_get_drvdata(codec);
calibration = tabla->mbhc_cfg.calibration;
@@ -5303,7 +5324,16 @@
* Need to restore defaults once calculation is done.
*/
cfilt_mode = snd_soc_read(codec, tabla->mbhc_bias_regs.cfilt_ctl);
- snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl, 0x40, 0x00);
+ micbias2_cfilt_mode =
+ snd_soc_read(codec, tabla_get_cfilt_reg(codec,
+ tabla->pdata->micbias.bias2_cfilt_sel));
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl, 0x40,
+ TABLA_CFILT_FAST_MODE);
+ snd_soc_update_bits(codec,
+ tabla_get_cfilt_reg(codec,
+ tabla->pdata->micbias.bias2_cfilt_sel),
+ 0x40, TABLA_CFILT_FAST_MODE);
+
bg_mode = snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x02,
0x02);
@@ -5317,6 +5347,12 @@
snd_soc_write(codec, TABLA_A_TX_7_MBHC_TEST_CTL, 0x78);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x04, 0x04);
+ /* MICBIAS2 routing for calibration */
+ bias2_ctl = snd_soc_read(codec, TABLA_A_MICB_2_CTL);
+ snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC, 0x03, TABLA_MICBIAS2);
+ snd_soc_write(codec, TABLA_A_MICB_2_CTL,
+ snd_soc_read(codec, tabla->mbhc_bias_regs.ctl_reg));
+
/* DCE measurement for 0 volts */
snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x0A);
snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x04);
@@ -5354,7 +5390,15 @@
tabla->mbhc_data.sta_mb = tabla_codec_read_sta_result(codec);
/* Restore default settings. */
+ snd_soc_write(codec, TABLA_A_MICB_2_CTL, bias2_ctl);
+ snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC, 0x03,
+ tabla->mbhc_cfg.micbias);
+
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x04, 0x00);
+ snd_soc_update_bits(codec,
+ tabla_get_cfilt_reg(codec,
+ tabla->pdata->micbias.bias2_cfilt_sel), 0x40,
+ micbias2_cfilt_mode);
snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl, 0x40,
cfilt_mode);
snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x02, bg_mode);
@@ -5538,6 +5582,10 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x02, 0x02);
snd_soc_update_bits(codec, TABLA_A_MBHC_SCALING_MUX_2, 0xF0, 0xF0);
+
+ /* override mbhc's micbias */
+ snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC, 0x03,
+ tabla->mbhc_cfg.micbias);
}
static bool tabla_mbhc_fw_validate(const struct firmware *fw)
diff --git a/sound/soc/msm/apq8064.c b/sound/soc/msm/apq8064.c
index 8c45f8a..a7fd38b 100644
--- a/sound/soc/msm/apq8064.c
+++ b/sound/soc/msm/apq8064.c
@@ -126,6 +126,8 @@
.gpio_level_insert = 1,
};
+static struct mutex cdc_mclk_mutex;
+
static void msm_enable_ext_spk_amp_gpio(u32 spk_amp_gpio)
{
int ret = 0;
@@ -373,35 +375,42 @@
static int msm_enable_codec_ext_clk(struct snd_soc_codec *codec, int enable,
bool dapm)
{
+ int r = 0;
pr_debug("%s: enable = %d\n", __func__, enable);
+
+ mutex_lock(&cdc_mclk_mutex);
if (enable) {
clk_users++;
pr_debug("%s: clk_users = %d\n", __func__, clk_users);
- if (clk_users != 1)
- return 0;
-
- if (codec_clk) {
- clk_set_rate(codec_clk, TABLA_EXT_CLK_RATE);
- clk_prepare_enable(codec_clk);
- tabla_mclk_enable(codec, 1, dapm);
- } else {
- pr_err("%s: Error setting Tabla MCLK\n", __func__);
- clk_users--;
- return -EINVAL;
+ if (clk_users == 1) {
+ if (codec_clk) {
+ clk_set_rate(codec_clk, TABLA_EXT_CLK_RATE);
+ clk_prepare_enable(codec_clk);
+ tabla_mclk_enable(codec, 1, dapm);
+ } else {
+ pr_err("%s: Error setting Tabla MCLK\n",
+ __func__);
+ clk_users--;
+ r = -EINVAL;
+ }
}
} else {
- pr_debug("%s: clk_users = %d\n", __func__, clk_users);
- if (clk_users == 0)
- return 0;
- clk_users--;
- if (!clk_users) {
- pr_debug("%s: disabling MCLK. clk_users = %d\n",
+ if (clk_users > 0) {
+ clk_users--;
+ pr_debug("%s: clk_users = %d\n", __func__, clk_users);
+ if (clk_users == 0) {
+ pr_debug("%s: disabling MCLK. clk_users = %d\n",
__func__, clk_users);
- tabla_mclk_enable(codec, 0, dapm);
- clk_disable_unprepare(codec_clk);
+ tabla_mclk_enable(codec, 0, dapm);
+ clk_disable_unprepare(codec_clk);
+ }
+ } else {
+ pr_err("%s: Error releasing Tabla MCLK\n", __func__);
+ r = -EINVAL;
}
}
- return 0;
+ mutex_unlock(&cdc_mclk_mutex);
+ return r;
}
static int msm_mclk_event(struct snd_soc_dapm_widget *w,
@@ -2008,6 +2017,7 @@
} else
msm_headset_gpios_configured = 1;
+ mutex_init(&cdc_mclk_mutex);
return ret;
}
@@ -2024,6 +2034,7 @@
if (mbhc_cfg.gpio)
gpio_free(mbhc_cfg.gpio);
kfree(mbhc_cfg.calibration);
+ mutex_destroy(&cdc_mclk_mutex);
}
module_exit(msm_audio_exit);
diff --git a/sound/soc/msm/mpq8064.c b/sound/soc/msm/mpq8064.c
index 0995300..9395e8f 100644
--- a/sound/soc/msm/mpq8064.c
+++ b/sound/soc/msm/mpq8064.c
@@ -1110,10 +1110,10 @@
.be_id = MSM_FRONTEND_DAI_VOIP,
},
{
- .name = "MSM8960 LPA",
- .stream_name = "LPA",
+ .name = "MSM8960 Media3",
+ .stream_name = "MultiMedia3",
.cpu_dai_name = "MultiMedia3",
- .platform_name = "msm-pcm-lpa",
+ .platform_name = "msm-pcm-dsp",
.dynamic = 1,
.trigger = {SND_SOC_DPCM_TRIGGER_BESPOKE, SND_SOC_DPCM_TRIGGER_BESPOKE},
.codec_dai_name = "snd-soc-dummy-dai",
@@ -1173,8 +1173,8 @@
.codec_name = "snd-soc-dummy",
},
{
- .name = "MSM8960 Compr",
- .stream_name = "COMPR",
+ .name = "MSM8960 Compr1",
+ .stream_name = "COMPR1",
.cpu_dai_name = "MultiMedia4",
.platform_name = "msm-compr-dsp",
.dynamic = 1,
@@ -1239,6 +1239,62 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
},
+ {
+ .name = "MSM8960 Media5",
+ .stream_name = "MultiMedia5",
+ .cpu_dai_name = "MultiMedia5",
+ .platform_name = "msm-multi-ch-pcm-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_BESPOKE,
+ SND_SOC_DPCM_TRIGGER_BESPOKE},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* this dailink has playback support */
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA5
+ },
+ {
+ .name = "MSM8960 Media6",
+ .stream_name = "MultiMedia6",
+ .cpu_dai_name = "MultiMedia6",
+ .platform_name = "msm-multi-ch-pcm-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_BESPOKE,
+ SND_SOC_DPCM_TRIGGER_BESPOKE},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* this dailink has playback support */
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA6
+ },
+ {
+ .name = "MSM8960 Compr2",
+ .stream_name = "COMPR2",
+ .cpu_dai_name = "MultiMedia7",
+ .platform_name = "msm-compr-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_BESPOKE,
+ SND_SOC_DPCM_TRIGGER_BESPOKE},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* this dailink has playback support */
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA7,
+ },
+ {
+ .name = "MSM8960 Compr3",
+ .stream_name = "COMPR3",
+ .cpu_dai_name = "MultiMedia8",
+ .platform_name = "msm-compr-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_BESPOKE,
+ SND_SOC_DPCM_TRIGGER_BESPOKE},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* this dailink has playback support */
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA8,
+ },
/* Backend DAI Links */
{
.name = LPASS_BE_SLIMBUS_0_RX,
diff --git a/sound/soc/msm/msm-dai-fe.c b/sound/soc/msm/msm-dai-fe.c
index c8d3a71c..6e190b2 100644
--- a/sound/soc/msm/msm-dai-fe.c
+++ b/sound/soc/msm/msm-dai-fe.c
@@ -55,7 +55,7 @@
SNDRV_PCM_RATE_KNOT),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
- .channels_max = 2,
+ .channels_max = 6,
.rate_min = 8000,
.rate_max = 48000,
},
@@ -157,7 +157,7 @@
SNDRV_PCM_RATE_KNOT),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
- .channels_max = 2,
+ .channels_max = 6,
.rate_min = 8000,
.rate_max = 48000,
},
@@ -172,13 +172,69 @@
SNDRV_PCM_RATE_KNOT),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
- .channels_max = 2,
+ .channels_max = 6,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &msm_fe_Multimedia_dai_ops,
.name = "MultiMedia4",
},
+ {
+ .playback = {
+ .stream_name = "MultiMedia5 Playback",
+ .rates = (SNDRV_PCM_RATE_8000_48000 |
+ SNDRV_PCM_RATE_KNOT),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 6,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_Multimedia_dai_ops,
+ .name = "MultiMedia5",
+ },
+ {
+ .playback = {
+ .stream_name = "MultiMedia6 Playback",
+ .rates = (SNDRV_PCM_RATE_8000_48000 |
+ SNDRV_PCM_RATE_KNOT),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 6,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_Multimedia_dai_ops,
+ .name = "MultiMedia6",
+ },
+ {
+ .playback = {
+ .stream_name = "MultiMedia7 Playback",
+ .rates = (SNDRV_PCM_RATE_8000_48000 |
+ SNDRV_PCM_RATE_KNOT),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 6,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_Multimedia_dai_ops,
+ .name = "MultiMedia7",
+ },
+ {
+ .playback = {
+ .stream_name = "MultiMedia8 Playback",
+ .rates = (SNDRV_PCM_RATE_8000_48000 |
+ SNDRV_PCM_RATE_KNOT),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 6,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_Multimedia_dai_ops,
+ .name = "MultiMedia8",
+ },
/* FE DAIs created for hostless operation purpose */
{
.playback = {
diff --git a/sound/soc/msm/msm-pcm-routing.c b/sound/soc/msm/msm-pcm-routing.c
index 357a53b..4219ab6 100644
--- a/sound/soc/msm/msm-pcm-routing.c
+++ b/sound/soc/msm/msm-pcm-routing.c
@@ -191,6 +191,15 @@
{INVALID_SESSION, INVALID_SESSION},
/* MULTIMEDIA4 */
{INVALID_SESSION, INVALID_SESSION},
+ /* MULTIMEDIA5 */
+ {INVALID_SESSION, INVALID_SESSION},
+ /* MULTIMEDIA6 */
+ {INVALID_SESSION, INVALID_SESSION},
+ /* MULTIMEDIA7*/
+ {INVALID_SESSION, INVALID_SESSION},
+ /* MULTIMEDIA8 */
+ {INVALID_SESSION, INVALID_SESSION},
+
};
static uint8_t is_be_dai_extproc(int be_dai)
@@ -1030,6 +1039,18 @@
SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_I2S_RX,
MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
static const struct snd_kcontrol_new sec_i2s_rx_mixer_controls[] = {
@@ -1045,6 +1066,18 @@
SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_I2S_RX,
MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
static const struct snd_kcontrol_new slimbus_rx_mixer_controls[] = {
@@ -1060,6 +1093,18 @@
SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SLIMBUS_0_RX,
MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_0_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SLIMBUS_0_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SLIMBUS_0_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SLIMBUS_0_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
static const struct snd_kcontrol_new mi2s_rx_mixer_controls[] = {
@@ -1075,6 +1120,18 @@
SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_MI2S_RX,
MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
static const struct snd_kcontrol_new hdmi_mixer_controls[] = {
@@ -1090,6 +1147,18 @@
SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_HDMI_RX,
MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
/* incall music delivery mixer */
static const struct snd_kcontrol_new incall_music_delivery_mixer_controls[] = {
@@ -1795,6 +1864,10 @@
SND_SOC_DAPM_AIF_IN("MM_DL2", "MultiMedia2 Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL3", "MultiMedia3 Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL4", "MultiMedia4 Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("MM_DL5", "MultiMedia5 Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("MM_DL6", "MultiMedia6 Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("MM_DL7", "MultiMedia7 Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("MM_DL8", "MultiMedia8 Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("VOIP_DL", "VoIP Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL1", "MultiMedia1 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL2", "MultiMedia2 Capture", 0, 0, 0, 0),
@@ -2001,24 +2074,40 @@
{"PRI_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
{"PRI_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
{"PRI_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
+ {"PRI_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
+ {"PRI_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
+ {"PRI_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
+ {"PRI_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
{"PRI_I2S_RX", NULL, "PRI_RX Audio Mixer"},
{"SEC_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
{"SEC_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
{"SEC_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
{"SEC_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
+ {"SEC_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
+ {"SEC_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
+ {"SEC_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
+ {"SEC_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
{"SEC_I2S_RX", NULL, "SEC_RX Audio Mixer"},
{"SLIMBUS_0_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
{"SLIMBUS_0_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
{"SLIMBUS_0_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
{"SLIMBUS_0_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
+ {"SLIMBUS_0_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
+ {"SLIMBUS_0_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
+ {"SLIMBUS_0_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
+ {"SLIMBUS_0_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
{"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Audio Mixer"},
{"HDMI Mixer", "MultiMedia1", "MM_DL1"},
{"HDMI Mixer", "MultiMedia2", "MM_DL2"},
{"HDMI Mixer", "MultiMedia3", "MM_DL3"},
{"HDMI Mixer", "MultiMedia4", "MM_DL4"},
+ {"HDMI Mixer", "MultiMedia5", "MM_DL5"},
+ {"HDMI Mixer", "MultiMedia6", "MM_DL6"},
+ {"HDMI Mixer", "MultiMedia7", "MM_DL7"},
+ {"HDMI Mixer", "MultiMedia8", "MM_DL8"},
{"HDMI", NULL, "HDMI Mixer"},
/* incall */
diff --git a/sound/soc/msm/msm-pcm-routing.h b/sound/soc/msm/msm-pcm-routing.h
index 3065861..d1230ad 100644
--- a/sound/soc/msm/msm-pcm-routing.h
+++ b/sound/soc/msm/msm-pcm-routing.h
@@ -56,6 +56,10 @@
MSM_FRONTEND_DAI_MULTIMEDIA2,
MSM_FRONTEND_DAI_MULTIMEDIA3,
MSM_FRONTEND_DAI_MULTIMEDIA4,
+ MSM_FRONTEND_DAI_MULTIMEDIA5,
+ MSM_FRONTEND_DAI_MULTIMEDIA6,
+ MSM_FRONTEND_DAI_MULTIMEDIA7,
+ MSM_FRONTEND_DAI_MULTIMEDIA8,
MSM_FRONTEND_DAI_CS_VOICE,
MSM_FRONTEND_DAI_VOIP,
MSM_FRONTEND_DAI_AFE_RX,
@@ -65,8 +69,8 @@
MSM_FRONTEND_DAI_MAX,
};
-#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA4 + 1)
-#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA4
+#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA8 + 1)
+#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA8
enum {
MSM_BACKEND_DAI_PRI_I2S_RX = 0,