| /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &spmi_bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| qcom,pma8084@0 { |
| spmi-slave-container; |
| reg = <0x0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| qcom,revid@100 { |
| compatible = "qcom,qpnp-revid"; |
| reg = <0x100 0x100>; |
| }; |
| |
| qcom,power-on@800 { |
| compatible = "qcom,qpnp-power-on"; |
| reg = <0x800 0x100>; |
| interrupts = <0x0 0x8 0x0>, |
| <0x0 0x8 0x1>, |
| <0x0 0x8 0x4>, |
| <0x0 0x8 0x5>; |
| interrupt-names = "kpdpwr", "resin", |
| "resin-bark", "kpdpwr-resin-bark"; |
| qcom,pon-dbc-delay = <15625>; |
| qcom,system-reset; |
| qcom,s3-debounce = <32>; |
| |
| qcom,pon_1 { |
| qcom,pon-type = <0>; |
| qcom,pull-up = <1>; |
| linux,code = <116>; |
| }; |
| |
| qcom,pon_2 { |
| qcom,pon-type = <1>; |
| qcom,support-reset = <1>; |
| qcom,pull-up = <1>; |
| qcom,s1-timer = <0>; |
| qcom,s2-timer = <2000>; |
| qcom,s2-type = <1>; |
| linux,code = <114>; |
| }; |
| |
| qcom,pon_3 { |
| qcom,pon-type = <3>; |
| qcom,support-reset = <1>; |
| qcom,s1-timer = <6720>; |
| qcom,s2-timer = <2000>; |
| qcom,s2-type = <7>; |
| qcom,pull-up = <1>; |
| }; |
| }; |
| |
| pma8084_misc: qcom,misc@900 { |
| compatible = "qcom,qpnp-misc"; |
| reg = <0x900 0x100>; |
| }; |
| |
| qcom,temp-alarm@2400 { |
| compatible = "qcom,qpnp-temp-alarm"; |
| reg = <0x2400 0x100>; |
| interrupts = <0x0 0x24 0x0>; |
| label = "pma8084_tz"; |
| qcom,threshold-set = <0>; |
| qcom,temp_alarm-vadc = <&pma8084_vadc>; |
| }; |
| |
| qcom,coincell@2800 { |
| compatible = "qcom,qpnp-coincell"; |
| reg = <0x2800 0x100>; |
| }; |
| |
| pma8084_gpios: gpios { |
| spmi-dev-container; |
| compatible = "qcom,qpnp-pin"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| label = "pma8084-gpio"; |
| |
| gpio@c000 { |
| reg = <0xc000 0x100>; |
| qcom,pin-num = <1>; |
| }; |
| |
| gpio@c100 { |
| reg = <0xc100 0x100>; |
| qcom,pin-num = <2>; |
| }; |
| |
| gpio@c200 { |
| reg = <0xc200 0x100>; |
| qcom,pin-num = <3>; |
| }; |
| |
| gpio@c300 { |
| reg = <0xc300 0x100>; |
| qcom,pin-num = <4>; |
| }; |
| |
| gpio@c400 { |
| reg = <0xc400 0x100>; |
| qcom,pin-num = <5>; |
| }; |
| |
| gpio@c500 { |
| reg = <0xc500 0x100>; |
| qcom,pin-num = <6>; |
| }; |
| |
| gpio@c600 { |
| reg = <0xc600 0x100>; |
| qcom,pin-num = <7>; |
| }; |
| |
| gpio@c700 { |
| reg = <0xc700 0x100>; |
| qcom,pin-num = <8>; |
| }; |
| |
| gpio@c800 { |
| reg = <0xc800 0x100>; |
| qcom,pin-num = <9>; |
| }; |
| |
| gpio@c900 { |
| reg = <0xc900 0x100>; |
| qcom,pin-num = <10>; |
| }; |
| |
| gpio@ca00 { |
| reg = <0xca00 0x100>; |
| qcom,pin-num = <11>; |
| }; |
| |
| gpio@cb00 { |
| reg = <0xcb00 0x100>; |
| qcom,pin-num = <12>; |
| }; |
| |
| gpio@cc00 { |
| reg = <0xcc00 0x100>; |
| qcom,pin-num = <13>; |
| }; |
| |
| gpio@cd00 { |
| reg = <0xcd00 0x100>; |
| qcom,pin-num = <14>; |
| }; |
| |
| gpio@ce00 { |
| reg = <0xce00 0x100>; |
| qcom,pin-num = <15>; |
| }; |
| |
| gpio@cf00 { |
| reg = <0xcf00 0x100>; |
| qcom,pin-num = <16>; |
| }; |
| |
| gpio@d000 { |
| reg = <0xd000 0x100>; |
| qcom,pin-num = <17>; |
| }; |
| |
| gpio@d100 { |
| reg = <0xd100 0x100>; |
| qcom,pin-num = <18>; |
| }; |
| |
| gpio@d200 { |
| reg = <0xd200 0x100>; |
| qcom,pin-num = <19>; |
| }; |
| |
| gpio@d300 { |
| reg = <0xd300 0x100>; |
| qcom,pin-num = <20>; |
| }; |
| |
| gpio@d400 { |
| reg = <0xd400 0x100>; |
| qcom,pin-num = <21>; |
| }; |
| |
| gpio@d500 { |
| reg = <0xd500 0x100>; |
| qcom,pin-num = <22>; |
| }; |
| }; |
| |
| pma8084_mpps: mpps { |
| spmi-dev-container; |
| compatible = "qcom,qpnp-pin"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| label = "pma8084-mpp"; |
| |
| mpp@a000 { |
| reg = <0xa000 0x100>; |
| qcom,pin-num = <1>; |
| }; |
| |
| mpp@a100 { |
| reg = <0xa100 0x100>; |
| qcom,pin-num = <2>; |
| }; |
| |
| mpp@a200 { |
| reg = <0xa200 0x100>; |
| qcom,pin-num = <3>; |
| }; |
| |
| mpp@a300 { |
| reg = <0xa300 0x100>; |
| qcom,pin-num = <4>; |
| }; |
| |
| mpp@a400 { |
| reg = <0xa400 0x100>; |
| qcom,pin-num = <5>; |
| }; |
| |
| mpp@a500 { |
| reg = <0xa500 0x100>; |
| qcom,pin-num = <6>; |
| }; |
| |
| mpp@a600 { |
| reg = <0xa600 0x100>; |
| qcom,pin-num = <7>; |
| }; |
| |
| mpp@a700 { |
| reg = <0xa700 0x100>; |
| qcom,pin-num = <8>; |
| }; |
| }; |
| |
| pma8084_vadc: vadc@3100 { |
| compatible = "qcom,qpnp-vadc"; |
| reg = <0x3100 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0x0 0x31 0x0>; |
| interrupt-names = "eoc-int-en-set"; |
| qcom,adc-bit-resolution = <15>; |
| qcom,adc-vdd-reference = <1800>; |
| qcom,vadc-poll-eoc; |
| |
| chan@8 { |
| label = "die_temp"; |
| reg = <8>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <3>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@9 { |
| label = "ref_625mv"; |
| reg = <9>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@a { |
| label = "ref_1250v"; |
| reg = <0xa>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@c { |
| label = "ref_buf_625mv"; |
| reg = <0xc>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| }; |
| |
| pma8084_adc_tm: vadc@3400 { |
| compatible = "qcom,qpnp-adc-tm"; |
| reg = <0x3400 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0x0 0x34 0x0>, |
| <0x0 0x34 0x3>, |
| <0x0 0x34 0x4>; |
| interrupt-names = "eoc-int-en-set", |
| "high-thr-en-set", |
| "low-thr-en-set"; |
| qcom,adc-bit-resolution = <15>; |
| qcom,adc-vdd-reference = <1800>; |
| qcom,adc_tm-vadc = <&pma8084_vadc>; |
| }; |
| |
| qcom,rtc { |
| compatible = "qcom,qpnp-rtc"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| qcom,qpnp-rtc-write = <0>; |
| qcom,qpnp-rtc-alarm-pwrup = <0>; |
| |
| qcom,rtc_rw@6000 { |
| reg = <0x6000 0x100>; |
| }; |
| qcom,rtc_alarm@6100 { |
| reg = <0x6100 0x100>; |
| interrupts = <0x0 0x61 0x1>; |
| }; |
| }; |
| }; |
| |
| qcom,pma8084@1 { |
| spmi-slave-container; |
| reg = <0x1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| regulator@1400 { |
| regulator-name = "8084_s1"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x1400 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@1400 { |
| reg = <0x1400 0x100>; |
| }; |
| qcom,ps@1500 { |
| reg = <0x1500 0x100>; |
| }; |
| qcom,freq@1600 { |
| reg = <0x1600 0x100>; |
| }; |
| }; |
| |
| regulator@1700 { |
| regulator-name = "8084_s2"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x1700 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@1700 { |
| reg = <0x1700 0x100>; |
| }; |
| qcom,ps@1800 { |
| reg = <0x1800 0x100>; |
| }; |
| qcom,freq@1900 { |
| reg = <0x1900 0x100>; |
| }; |
| }; |
| |
| regulator@1a00 { |
| regulator-name = "8084_s3"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x1a00 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@1a00 { |
| reg = <0x1a00 0x100>; |
| }; |
| qcom,ps@1b00 { |
| reg = <0x1b00 0x100>; |
| }; |
| qcom,freq@1c00 { |
| reg = <0x1c00 0x100>; |
| }; |
| }; |
| |
| regulator@1d00 { |
| regulator-name = "8084_s4"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x1d00 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@1d00 { |
| reg = <0x1d00 0x100>; |
| }; |
| qcom,ps@1e00 { |
| reg = <0x1e00 0x100>; |
| }; |
| qcom,freq@1f00 { |
| reg = <0x1f00 0x100>; |
| }; |
| }; |
| |
| regulator@2000 { |
| regulator-name = "8084_s5"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x2000 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@2000 { |
| reg = <0x2000 0x100>; |
| }; |
| qcom,ps@2100 { |
| reg = <0x2100 0x100>; |
| }; |
| qcom,freq@2200 { |
| reg = <0x2200 0x100>; |
| }; |
| }; |
| |
| regulator@2300 { |
| regulator-name = "8084_s6"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x2300 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@2300 { |
| reg = <0x2300 0x100>; |
| }; |
| qcom,ps@2400 { |
| reg = <0x2400 0x100>; |
| }; |
| qcom,freq@2500 { |
| reg = <0x2500 0x100>; |
| }; |
| }; |
| |
| regulator@2600 { |
| regulator-name = "8084_s7"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x2600 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@2600 { |
| reg = <0x2600 0x100>; |
| }; |
| qcom,ps@2700 { |
| reg = <0x2700 0x100>; |
| }; |
| qcom,freq@2800 { |
| reg = <0x2800 0x100>; |
| }; |
| }; |
| |
| regulator@2900 { |
| regulator-name = "8084_s8"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x2900 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@2900 { |
| reg = <0x2900 0x100>; |
| }; |
| qcom,ps@2a00 { |
| reg = <0x2a00 0x100>; |
| }; |
| qcom,freq@2b00 { |
| reg = <0x2b00 0x100>; |
| }; |
| }; |
| |
| regulator@2c00 { |
| regulator-name = "8084_s9"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x2c00 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@2c00 { |
| reg = <0x2c00 0x100>; |
| }; |
| qcom,ps@2d00 { |
| reg = <0x2d00 0x100>; |
| }; |
| qcom,freq@2e00 { |
| reg = <0x2e00 0x100>; |
| }; |
| }; |
| |
| regulator@2f00 { |
| regulator-name = "8084_s10"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x2f00 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@2f00 { |
| reg = <0x2f00 0x100>; |
| }; |
| qcom,ps@3000 { |
| reg = <0x3000 0x100>; |
| }; |
| qcom,freq@3100 { |
| reg = <0x3100 0x100>; |
| }; |
| }; |
| |
| regulator@3200 { |
| regulator-name = "8084_s11"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x3200 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@3200 { |
| reg = <0x3200 0x100>; |
| }; |
| qcom,ps@3300 { |
| reg = <0x3300 0x100>; |
| }; |
| qcom,freq@3400 { |
| reg = <0x3400 0x100>; |
| }; |
| }; |
| |
| regulator@3500 { |
| regulator-name = "8084_s12"; |
| spmi-dev-container; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qpnp-regulator"; |
| reg = <0x3500 0x300>; |
| status = "disabled"; |
| |
| qcom,ctl@3500 { |
| reg = <0x3500 0x100>; |
| }; |
| qcom,ps@3600 { |
| reg = <0x3600 0x100>; |
| }; |
| qcom,freq@3700 { |
| reg = <0x3700 0x100>; |
| }; |
| }; |
| |
| regulator@4000 { |
| regulator-name = "8084_l1"; |
| reg = <0x4000 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4100 { |
| regulator-name = "8084_l2"; |
| reg = <0x4100 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4200 { |
| regulator-name = "8084_l3"; |
| reg = <0x4200 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4300 { |
| regulator-name = "8084_l4"; |
| reg = <0x4300 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4400 { |
| regulator-name = "8084_l5"; |
| reg = <0x4400 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4500 { |
| regulator-name = "8084_l6"; |
| reg = <0x4500 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4600 { |
| regulator-name = "8084_l7"; |
| reg = <0x4600 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4700 { |
| regulator-name = "8084_l8"; |
| reg = <0x4700 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4800 { |
| regulator-name = "8084_l9"; |
| reg = <0x4800 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4900 { |
| regulator-name = "8084_l10"; |
| reg = <0x4900 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4a00 { |
| regulator-name = "8084_l11"; |
| reg = <0x4a00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4b00 { |
| regulator-name = "8084_l12"; |
| reg = <0x4b00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4c00 { |
| regulator-name = "8084_l13"; |
| reg = <0x4c00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4d00 { |
| regulator-name = "8084_l14"; |
| reg = <0x4d00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4e00 { |
| regulator-name = "8084_l15"; |
| reg = <0x4e00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@4f00 { |
| regulator-name = "8084_l16"; |
| reg = <0x4f00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5000 { |
| regulator-name = "8084_l17"; |
| reg = <0x5000 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5100 { |
| regulator-name = "8084_l18"; |
| reg = <0x5100 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5200 { |
| regulator-name = "8084_l19"; |
| reg = <0x5200 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5300 { |
| regulator-name = "8084_l20"; |
| reg = <0x5300 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5400 { |
| regulator-name = "8084_l21"; |
| reg = <0x5400 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5500 { |
| regulator-name = "8084_l22"; |
| reg = <0x5500 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5600 { |
| regulator-name = "8084_l23"; |
| reg = <0x5600 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5700 { |
| regulator-name = "8084_l24"; |
| reg = <0x5700 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5800 { |
| regulator-name = "8084_l25"; |
| reg = <0x5800 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5900 { |
| regulator-name = "8084_l26"; |
| reg = <0x5900 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@5a00 { |
| regulator-name = "8084_l27"; |
| reg = <0x5a00 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@8000 { |
| regulator-name = "8084_lvs1"; |
| reg = <0x8000 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@8100 { |
| regulator-name = "8084_lvs2"; |
| reg = <0x8100 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@8200 { |
| regulator-name = "8084_lvs3"; |
| reg = <0x8200 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@8300 { |
| regulator-name = "8084_lvs4"; |
| reg = <0x8300 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| regulator@8400 { |
| regulator-name = "8084_mvs1"; |
| reg = <0x8400 0x100>; |
| compatible = "qcom,qpnp-regulator"; |
| status = "disabled"; |
| }; |
| |
| krait_regulator_pmic: qcom,krait-regulator-pmic@2900 { |
| spmi-dev-container; |
| compatible = "qcom,krait-regulator-pmic"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "disabled"; |
| |
| qcom,ctl@2900 { |
| reg = <0x2900 0x100>; |
| status = "disabled"; |
| }; |
| |
| qcom,ps@2a00 { |
| reg = <0x2a00 0x100>; |
| status = "disabled"; |
| }; |
| |
| qcom,freq@2b00 { |
| reg = <0x2b00 0x100>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| }; |