Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2967002..385e9c7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -453,4 +453,38 @@
help
Select this option to enable GPIO driver for the TPS65910
chip family.
+
+config MPP_PMIC8901
+ tristate "Qualcomm PMIC8901 MPP"
+ depends on GPIOLIB && PMIC8901
+ default y
+ help
+ Say yes here to support GPIO functionality on Qualcomm's
+ PM8901 chip for MPP(Multi-Purpose Pin) pins. These pins
+ work like GPIO pins when configured as digital input and/or
+ output signals.
+
+config GPIO_PM8XXX
+ tristate "Qualcomm PM8xxx GPIO support"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This option enables support for on-chip GPIO found on Qualcomm PM8xxx
+ PMICs.
+
+config GPIO_PM8XXX_MPP
+ tristate "Support for Qualcomm PM8xxx MPP features"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This is the multi-purpose pin (MPP) driver for Qualcomm PM 8xxx PMIC
+ chips.
+
+config GPIO_PM8XXX_RPC
+ tristate "Qualcomm PM8xxx RPC based GPIO support"
+ depends on MSM_SMD
+ help
+ This option enables support for on-chip GPIO found on Qualcomm PM8xxx
+ PMICs through RPC.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b605f8e..1b2c4b1 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -48,3 +48,7 @@
obj-$(CONFIG_GPIO_ML_IOH) += ml_ioh_gpio.o
obj-$(CONFIG_AB8500_GPIO) += ab8500-gpio.o
obj-$(CONFIG_GPIO_TPS65910) += tps65910-gpio.o
+obj-$(CONFIG_MPP_PMIC8901) += pmic8901-mpp.o
+obj-$(CONFIG_GPIO_PM8XXX) += pm8xxx-gpio.o
+obj-$(CONFIG_GPIO_PM8XXX_MPP) += pm8xxx-mpp.o
+obj-$(CONFIG_GPIO_PM8XXX_RPC) += gpio-pm8xxx-rpc.o
diff --git a/drivers/gpio/gpio-pm8xxx-rpc.c b/drivers/gpio/gpio-pm8xxx-rpc.c
new file mode 100644
index 0000000..1acc741
--- /dev/null
+++ b/drivers/gpio/gpio-pm8xxx-rpc.c
@@ -0,0 +1,241 @@
+/*
+ * Qualcomm PMIC8XXX GPIO driver based on RPC
+ *
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/gpio-pm8xxx-rpc.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <mach/pmic.h>
+
+struct pm8xxx_gpio_rpc_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+};
+
+static LIST_HEAD(pm8xxx_gpio_rpc_chips);
+static DEFINE_MUTEX(pm8xxx_gpio_chips_lock);
+
+static int pm8xxx_gpio_rpc_get(struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip,
+ unsigned gpio)
+{
+ int rc;
+
+ if (gpio >= pm8xxx_gpio_chip->gpio_chip.ngpio
+ || pm8xxx_gpio_chip == NULL)
+ return -EINVAL;
+
+ rc = pmic_gpio_get_value(gpio);
+
+ return rc;
+}
+
+static int pm8xxx_gpio_rpc_set(struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip,
+ unsigned gpio, int value)
+{
+ int rc;
+
+ if (gpio >= pm8xxx_gpio_chip->gpio_chip.ngpio ||
+ pm8xxx_gpio_chip == NULL)
+ return -EINVAL;
+
+ rc = pmic_gpio_set_value(gpio, value);
+
+ return rc;
+}
+
+static int pm8xxx_gpio_rpc_set_direction(struct pm8xxx_gpio_rpc_chip
+ *pm8xxx_gpio_chip, unsigned gpio, int direction)
+{
+ int rc = 0;
+
+ if (!direction || pm8xxx_gpio_chip == NULL)
+ return -EINVAL;
+
+ if (direction == PM_GPIO_DIR_IN)
+ rc = pmic_gpio_direction_input(gpio);
+ else if (direction == PM_GPIO_DIR_OUT)
+ rc = pmic_gpio_direction_output(gpio);
+
+ return rc;
+}
+
+static int pm8xxx_gpio_rpc_read(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip =
+ dev_get_drvdata(gpio_chip->dev);
+
+ return pm8xxx_gpio_rpc_get(pm8xxx_gpio_chip, offset);
+}
+
+static void pm8xxx_gpio_rpc_write(struct gpio_chip *gpio_chip,
+ unsigned offset, int val)
+{
+ struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip =
+ dev_get_drvdata(gpio_chip->dev);
+
+ pm8xxx_gpio_rpc_set(pm8xxx_gpio_chip, offset, !!val);
+}
+
+static int pm8xxx_gpio_rpc_direction_input(struct gpio_chip *gpio_chip,
+ unsigned offset)
+{
+ struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip =
+ dev_get_drvdata(gpio_chip->dev);
+
+ return pm8xxx_gpio_rpc_set_direction(pm8xxx_gpio_chip, offset,
+ PM_GPIO_DIR_IN);
+}
+
+static int pm8xxx_gpio_rpc_direction_output(struct gpio_chip *gpio_chip,
+ unsigned offset, int val)
+{
+ int ret = 0;
+
+ struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip =
+ dev_get_drvdata(gpio_chip->dev);
+
+ ret = pm8xxx_gpio_rpc_set_direction(pm8xxx_gpio_chip, offset,
+ PM_GPIO_DIR_OUT);
+ if (!ret)
+ ret = pm8xxx_gpio_rpc_set(pm8xxx_gpio_chip, offset, !!val);
+
+ return ret;
+}
+
+static void pm8xxx_gpio_rpc_dbg_show(struct seq_file *s, struct gpio_chip
+ *gpio_chip)
+{
+ struct pm8xxx_gpio_rpc_chip *pmxx_gpio_chip =
+ dev_get_drvdata(gpio_chip->dev);
+ u8 state, mode;
+ const char *label;
+ int i;
+
+ for (i = 0; i < gpio_chip->ngpio; i++) {
+ label = gpiochip_is_requested(gpio_chip, i);
+ state = pm8xxx_gpio_rpc_get(pmxx_gpio_chip, i);
+ mode = pmic_gpio_get_direction(i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %s %s",
+ gpio_chip->base + i,
+ label ? label : " ", mode ? "out" : "in",
+ state ? "hi" : "lo");
+ seq_printf(s, "\n");
+ }
+}
+
+static int __devinit pm8xxx_gpio_rpc_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip;
+ const struct pm8xxx_gpio_rpc_platform_data *pdata =
+ pdev->dev.platform_data;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ return -EINVAL;
+ }
+
+ pm8xxx_gpio_chip = kzalloc(sizeof(struct pm8xxx_gpio_rpc_chip),
+ GFP_KERNEL);
+ if (!pm8xxx_gpio_chip) {
+ pr_err("Cannot allocate pm8xxx_gpio_chip\n");
+ return -ENOMEM;
+ }
+
+ pm8xxx_gpio_chip->gpio_chip.label = "pm8xxx-gpio-rpc";
+ pm8xxx_gpio_chip->gpio_chip.direction_input =
+ pm8xxx_gpio_rpc_direction_input;
+ pm8xxx_gpio_chip->gpio_chip.direction_output =
+ pm8xxx_gpio_rpc_direction_output;
+ pm8xxx_gpio_chip->gpio_chip.get = pm8xxx_gpio_rpc_read;
+ pm8xxx_gpio_chip->gpio_chip.set = pm8xxx_gpio_rpc_write;
+ pm8xxx_gpio_chip->gpio_chip.dbg_show = pm8xxx_gpio_rpc_dbg_show;
+ pm8xxx_gpio_chip->gpio_chip.ngpio = pdata->ngpios;
+ pm8xxx_gpio_chip->gpio_chip.can_sleep = 1;
+ pm8xxx_gpio_chip->gpio_chip.dev = &pdev->dev;
+ pm8xxx_gpio_chip->gpio_chip.base = pdata->gpio_base;
+
+ mutex_lock(&pm8xxx_gpio_chips_lock);
+ list_add(&pm8xxx_gpio_chip->link, &pm8xxx_gpio_rpc_chips);
+ mutex_unlock(&pm8xxx_gpio_chips_lock);
+ platform_set_drvdata(pdev, pm8xxx_gpio_chip);
+
+ ret = gpiochip_add(&pm8xxx_gpio_chip->gpio_chip);
+ if (ret) {
+ pr_err("gpiochip_add failed ret = %d\n", ret);
+ goto reset_drvdata;
+ }
+
+ pr_info("OK: base=%d, ngpio=%d\n", pm8xxx_gpio_chip->gpio_chip.base,
+ pm8xxx_gpio_chip->gpio_chip.ngpio);
+
+ return 0;
+
+reset_drvdata:
+ mutex_lock(&pm8xxx_gpio_chips_lock);
+ list_del(&pm8xxx_gpio_chip->link);
+ mutex_unlock(&pm8xxx_gpio_chips_lock);
+ platform_set_drvdata(pdev, NULL);
+ kfree(pm8xxx_gpio_chip);
+ mutex_destroy(&pm8xxx_gpio_chips_lock);
+ return ret;
+}
+
+static int __devexit pm8xxx_gpio_rpc_remove(struct platform_device *pdev)
+{
+ struct pm8xxx_gpio_rpc_chip *pm8xxx_gpio_chip =
+ platform_get_drvdata(pdev);
+
+ mutex_lock(&pm8xxx_gpio_chips_lock);
+ list_del(&pm8xxx_gpio_chip->link);
+ mutex_unlock(&pm8xxx_gpio_chips_lock);
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&pm8xxx_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ kfree(pm8xxx_gpio_chip);
+ mutex_destroy(&pm8xxx_gpio_chips_lock);
+ return 0;
+}
+
+static struct platform_driver pm8xxx_gpio_rpc_driver = {
+ .probe = pm8xxx_gpio_rpc_probe,
+ .remove = __devexit_p(pm8xxx_gpio_rpc_remove),
+ .driver = {
+ .name = PM8XXX_GPIO_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8xxx_gpio_rpc_init(void)
+{
+ return platform_driver_register(&pm8xxx_gpio_rpc_driver);
+}
+postcore_initcall(pm8xxx_gpio_rpc_init);
+
+static void __exit pm8xxx_gpio_rpc_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_gpio_rpc_driver);
+}
+module_exit(pm8xxx_gpio_rpc_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC GPIO driver based on RPC");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_GPIO_DEV_NAME);
diff --git a/drivers/gpio/pm8xxx-gpio.c b/drivers/gpio/pm8xxx-gpio.c
new file mode 100644
index 0000000..026fd05
--- /dev/null
+++ b/drivers/gpio/pm8xxx-gpio.c
@@ -0,0 +1,458 @@
+/*
+ * Qualcomm PMIC8XXX GPIO driver
+ *
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/gpio.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+/* GPIO registers */
+#define SSBI_REG_ADDR_GPIO_BASE 0x150
+#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
+
+/* GPIO */
+#define PM_GPIO_BANK_MASK 0x70
+#define PM_GPIO_BANK_SHIFT 4
+#define PM_GPIO_WRITE 0x80
+
+/* Bank 0 */
+#define PM_GPIO_VIN_MASK 0x0E
+#define PM_GPIO_VIN_SHIFT 1
+#define PM_GPIO_MODE_ENABLE 0x01
+
+/* Bank 1 */
+#define PM_GPIO_MODE_MASK 0x0C
+#define PM_GPIO_MODE_SHIFT 2
+#define PM_GPIO_OUT_BUFFER 0x02
+#define PM_GPIO_OUT_INVERT 0x01
+
+#define PM_GPIO_MODE_OFF 3
+#define PM_GPIO_MODE_OUTPUT 2
+#define PM_GPIO_MODE_INPUT 0
+#define PM_GPIO_MODE_BOTH 1
+
+/* Bank 2 */
+#define PM_GPIO_PULL_MASK 0x0E
+#define PM_GPIO_PULL_SHIFT 1
+
+/* Bank 3 */
+#define PM_GPIO_OUT_STRENGTH_MASK 0x0C
+#define PM_GPIO_OUT_STRENGTH_SHIFT 2
+#define PM_GPIO_PIN_ENABLE 0x00
+#define PM_GPIO_PIN_DISABLE 0x01
+
+/* Bank 4 */
+#define PM_GPIO_FUNC_MASK 0x0E
+#define PM_GPIO_FUNC_SHIFT 1
+
+/* Bank 5 */
+#define PM_GPIO_NON_INT_POL_INV 0x08
+#define PM_GPIO_BANKS 6
+
+struct pm_gpio_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+ spinlock_t pm_lock;
+ u8 *bank1;
+ int irq_base;
+};
+
+static LIST_HEAD(pm_gpio_chips);
+static DEFINE_MUTEX(pm_gpio_chips_lock);
+
+static int pm_gpio_get(struct pm_gpio_chip *pm_gpio_chip, unsigned gpio)
+{
+ int mode;
+
+ if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ /* Get gpio value from config bank 1 if output gpio.
+ Get gpio value from IRQ RT status register for all other gpio modes.
+ */
+ mode = (pm_gpio_chip->bank1[gpio] & PM_GPIO_MODE_MASK) >>
+ PM_GPIO_MODE_SHIFT;
+ if (mode == PM_GPIO_MODE_OUTPUT)
+ return pm_gpio_chip->bank1[gpio] & PM_GPIO_OUT_INVERT;
+ else
+ return pm8xxx_read_irq_stat(pm_gpio_chip->gpio_chip.dev->parent,
+ pm_gpio_chip->irq_base + gpio);
+}
+
+static int pm_gpio_set(struct pm_gpio_chip *pm_gpio_chip,
+ unsigned gpio, int value)
+{
+ int rc;
+ u8 bank1;
+ unsigned long flags;
+
+ if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pm_gpio_chip->pm_lock, flags);
+ bank1 = PM_GPIO_WRITE
+ | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_OUT_INVERT);
+
+ if (value)
+ bank1 |= PM_GPIO_OUT_INVERT;
+
+ pm_gpio_chip->bank1[gpio] = bank1;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(gpio), bank1);
+ spin_unlock_irqrestore(&pm_gpio_chip->pm_lock, flags);
+
+ if (rc)
+ pr_err("FAIL pm8xxx_writeb(): rc=%d. "
+ "(gpio=%d, value=%d)\n",
+ rc, gpio, value);
+
+ return rc;
+}
+
+static int dir_map[] = {
+ PM_GPIO_MODE_OFF,
+ PM_GPIO_MODE_OUTPUT,
+ PM_GPIO_MODE_INPUT,
+ PM_GPIO_MODE_BOTH,
+};
+
+static int pm_gpio_set_direction(struct pm_gpio_chip *pm_gpio_chip,
+ unsigned gpio, int direction)
+{
+ int rc;
+ u8 bank1;
+ unsigned long flags;
+
+ if (!direction || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pm_gpio_chip->pm_lock, flags);
+ bank1 = PM_GPIO_WRITE
+ | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_MODE_MASK);
+
+ bank1 |= ((dir_map[direction] << PM_GPIO_MODE_SHIFT)
+ & PM_GPIO_MODE_MASK);
+
+ pm_gpio_chip->bank1[gpio] = bank1;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(gpio), bank1);
+ spin_unlock_irqrestore(&pm_gpio_chip->pm_lock, flags);
+
+ if (rc)
+ pr_err("Failed on pm8xxx_writeb(): rc=%d (GPIO config)\n",
+ rc);
+
+ return rc;
+}
+
+static int pm_gpio_init_bank1(struct pm_gpio_chip *pm_gpio_chip)
+{
+ int i, rc;
+ u8 bank;
+
+ for (i = 0; i < pm_gpio_chip->gpio_chip.ngpio; i++) {
+ bank = 1 << PM_GPIO_BANK_SHIFT;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ bank);
+ if (rc) {
+ pr_err("error setting bank rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ &pm_gpio_chip->bank1[i]);
+ if (rc) {
+ pr_err("error reading bank 1 rc=%d\n", rc);
+ return rc;
+ }
+ }
+ return 0;
+}
+
+static int pm_gpio_to_irq(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_chip->irq_base + offset;
+}
+
+static int pm_gpio_read(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_get(pm_gpio_chip, offset);
+}
+
+static void pm_gpio_write(struct gpio_chip *gpio_chip,
+ unsigned offset, int val)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ pm_gpio_set(pm_gpio_chip, offset, val);
+}
+
+static int pm_gpio_direction_input(struct gpio_chip *gpio_chip,
+ unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_IN);
+}
+
+static int pm_gpio_direction_output(struct gpio_chip *gpio_chip,
+ unsigned offset,
+ int val)
+{
+ int ret;
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ ret = pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_OUT);
+ if (!ret)
+ ret = pm_gpio_set(pm_gpio_chip, offset, val);
+
+ return ret;
+}
+
+static void pm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gpio_chip)
+{
+ static const char * const cmode[] = { "in", "in/out", "out", "off" };
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+ u8 mode, state, bank;
+ const char *label;
+ int i, j;
+
+ for (i = 0; i < gpio_chip->ngpio; i++) {
+ label = gpiochip_is_requested(gpio_chip, i);
+ mode = (pm_gpio_chip->bank1[i] & PM_GPIO_MODE_MASK) >>
+ PM_GPIO_MODE_SHIFT;
+ state = pm_gpio_get(pm_gpio_chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s",
+ gpio_chip->base + i,
+ label ? label : "--",
+ cmode[mode],
+ state ? "hi" : "lo");
+ for (j = 0; j < PM_GPIO_BANKS; j++) {
+ bank = j << PM_GPIO_BANK_SHIFT;
+ pm8xxx_writeb(gpio_chip->dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ bank);
+ pm8xxx_readb(gpio_chip->dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ &bank);
+ seq_printf(s, " 0x%02x", bank);
+ }
+ seq_printf(s, "\n");
+ }
+}
+
+static int __devinit pm_gpio_probe(struct platform_device *pdev)
+{
+ int ret;
+ const struct pm8xxx_gpio_platform_data *pdata = pdev->dev.platform_data;
+ struct pm_gpio_chip *pm_gpio_chip;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ return -EINVAL;
+ }
+
+ pm_gpio_chip = kzalloc(sizeof(struct pm_gpio_chip), GFP_KERNEL);
+ if (!pm_gpio_chip) {
+ pr_err("Cannot allocate pm_gpio_chip\n");
+ return -ENOMEM;
+ }
+
+ pm_gpio_chip->bank1 = kzalloc(sizeof(u8) * pdata->gpio_cdata.ngpios,
+ GFP_KERNEL);
+ if (!pm_gpio_chip->bank1) {
+ pr_err("Cannot allocate pm_gpio_chip->bank1\n");
+ return -ENOMEM;
+ }
+
+ spin_lock_init(&pm_gpio_chip->pm_lock);
+ pm_gpio_chip->gpio_chip.label = "pm-gpio";
+ pm_gpio_chip->gpio_chip.direction_input = pm_gpio_direction_input;
+ pm_gpio_chip->gpio_chip.direction_output = pm_gpio_direction_output;
+ pm_gpio_chip->gpio_chip.to_irq = pm_gpio_to_irq;
+ pm_gpio_chip->gpio_chip.get = pm_gpio_read;
+ pm_gpio_chip->gpio_chip.set = pm_gpio_write;
+ pm_gpio_chip->gpio_chip.dbg_show = pm_gpio_dbg_show;
+ pm_gpio_chip->gpio_chip.ngpio = pdata->gpio_cdata.ngpios;
+ pm_gpio_chip->gpio_chip.can_sleep = 1;
+ pm_gpio_chip->gpio_chip.dev = &pdev->dev;
+ pm_gpio_chip->gpio_chip.base = pdata->gpio_base;
+ pm_gpio_chip->irq_base = platform_get_irq(pdev, 0);
+ mutex_lock(&pm_gpio_chips_lock);
+ list_add(&pm_gpio_chip->link, &pm_gpio_chips);
+ mutex_unlock(&pm_gpio_chips_lock);
+ platform_set_drvdata(pdev, pm_gpio_chip);
+
+ ret = gpiochip_add(&pm_gpio_chip->gpio_chip);
+ if (ret) {
+ pr_err("gpiochip_add failed ret = %d\n", ret);
+ goto reset_drvdata;
+ }
+
+ ret = pm_gpio_init_bank1(pm_gpio_chip);
+ if (ret) {
+ pr_err("gpio init bank failed ret = %d\n", ret);
+ goto remove_chip;
+ }
+
+ pr_info("OK: base=%d, ngpio=%d\n", pm_gpio_chip->gpio_chip.base,
+ pm_gpio_chip->gpio_chip.ngpio);
+
+ return 0;
+
+remove_chip:
+ if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+reset_drvdata:
+ platform_set_drvdata(pdev, NULL);
+ kfree(pm_gpio_chip);
+ return ret;
+}
+
+static int __devexit pm_gpio_remove(struct platform_device *pdev)
+{
+ struct pm_gpio_chip *pm_gpio_chip
+ = platform_get_drvdata(pdev);
+
+ mutex_lock(&pm_gpio_chips_lock);
+ list_del(&pm_gpio_chip->link);
+ mutex_unlock(&pm_gpio_chips_lock);
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ kfree(pm_gpio_chip->bank1);
+ kfree(pm_gpio_chip);
+ return 0;
+}
+
+int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
+{
+ int rc, pm_gpio = -EINVAL;
+ u8 bank[8];
+ unsigned long flags;
+ struct pm_gpio_chip *pm_gpio_chip;
+ struct gpio_chip *gpio_chip;
+
+ if (param == NULL)
+ return -EINVAL;
+
+ mutex_lock(&pm_gpio_chips_lock);
+ list_for_each_entry(pm_gpio_chip, &pm_gpio_chips, link) {
+ gpio_chip = &pm_gpio_chip->gpio_chip;
+ if (gpio >= gpio_chip->base
+ && gpio < gpio_chip->base + gpio_chip->ngpio) {
+ pm_gpio = gpio - gpio_chip->base;
+ break;
+ }
+ }
+ mutex_unlock(&pm_gpio_chips_lock);
+ if (pm_gpio < 0) {
+ pr_err("called on gpio %d not handled by any pmic\n", gpio);
+ return -EINVAL;
+ }
+
+ /* Select banks and configure the gpio */
+ bank[0] = PM_GPIO_WRITE |
+ ((param->vin_sel << PM_GPIO_VIN_SHIFT) &
+ PM_GPIO_VIN_MASK) |
+ PM_GPIO_MODE_ENABLE;
+ bank[1] = PM_GPIO_WRITE |
+ ((1 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((dir_map[param->direction] <<
+ PM_GPIO_MODE_SHIFT) &
+ PM_GPIO_MODE_MASK) |
+ ((param->direction & PM_GPIO_DIR_OUT) ?
+ ((param->output_buffer & 1) ?
+ PM_GPIO_OUT_BUFFER : 0) : 0) |
+ ((param->direction & PM_GPIO_DIR_OUT) ?
+ param->output_value & 0x01 : 0);
+ bank[2] = PM_GPIO_WRITE |
+ ((2 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->pull << PM_GPIO_PULL_SHIFT) &
+ PM_GPIO_PULL_MASK);
+ bank[3] = PM_GPIO_WRITE |
+ ((3 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->out_strength <<
+ PM_GPIO_OUT_STRENGTH_SHIFT) &
+ PM_GPIO_OUT_STRENGTH_MASK) |
+ (param->disable_pin ?
+ PM_GPIO_PIN_DISABLE : PM_GPIO_PIN_ENABLE);
+ bank[4] = PM_GPIO_WRITE |
+ ((4 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->function << PM_GPIO_FUNC_SHIFT) &
+ PM_GPIO_FUNC_MASK);
+ bank[5] = PM_GPIO_WRITE |
+ ((5 << PM_GPIO_BANK_SHIFT) & PM_GPIO_BANK_MASK) |
+ (param->inv_int_pol ? 0 : PM_GPIO_NON_INT_POL_INV);
+
+ spin_lock_irqsave(&pm_gpio_chip->pm_lock, flags);
+ /* Remember bank1 for later use */
+ pm_gpio_chip->bank1[pm_gpio] = bank[1];
+ rc = pm8xxx_write_buf(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(pm_gpio), bank, 6);
+ spin_unlock_irqrestore(&pm_gpio_chip->pm_lock, flags);
+
+ if (rc)
+ pr_err("Failed on pm8xxx_write_buf() rc=%d (GPIO config)\n",
+ rc);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_gpio_config);
+
+static struct platform_driver pm_gpio_driver = {
+ .probe = pm_gpio_probe,
+ .remove = __devexit_p(pm_gpio_remove),
+ .driver = {
+ .name = PM8XXX_GPIO_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm_gpio_init(void)
+{
+ return platform_driver_register(&pm_gpio_driver);
+}
+postcore_initcall(pm_gpio_init);
+
+static void __exit pm_gpio_exit(void)
+{
+ platform_driver_unregister(&pm_gpio_driver);
+}
+module_exit(pm_gpio_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC GPIO driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_GPIO_DEV_NAME);
diff --git a/drivers/gpio/pm8xxx-mpp.c b/drivers/gpio/pm8xxx-mpp.c
new file mode 100644
index 0000000..82a11a2
--- /dev/null
+++ b/drivers/gpio/pm8xxx-mpp.c
@@ -0,0 +1,334 @@
+/*
+ * Qualcomm PM8XXX Multi-Purpose Pin (MPP) driver
+ *
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+
+/* MPP Type */
+#define PM8XXX_MPP_TYPE_MASK 0xE0
+#define PM8XXX_MPP_TYPE_SHIFT 5
+
+/* MPP Config Level */
+#define PM8XXX_MPP_CONFIG_LVL_MASK 0x1C
+#define PM8XXX_MPP_CONFIG_LVL_SHIFT 2
+
+/* MPP Config Control */
+#define PM8XXX_MPP_CONFIG_CTRL_MASK 0x03
+#define PM8XXX_MPP_CONFIG_CTRL_SHIFT 0
+
+struct pm8xxx_mpp_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+ spinlock_t pm_lock;
+ u8 *ctrl_reg;
+ int mpp_base;
+ int irq_base;
+ int nmpps;
+ u16 base_addr;
+};
+
+static LIST_HEAD(pm8xxx_mpp_chips);
+static DEFINE_MUTEX(pm8xxx_mpp_chips_lock);
+
+static int pm8xxx_mpp_write(struct pm8xxx_mpp_chip *mpp_chip, u16 offset,
+ u8 val, u8 mask)
+{
+ u8 reg;
+ int rc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mpp_chip->pm_lock, flags);
+
+ reg = (mpp_chip->ctrl_reg[offset] & ~mask) | (val & mask);
+ rc = pm8xxx_writeb(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->base_addr + offset, reg);
+ if (!rc)
+ mpp_chip->ctrl_reg[offset] = reg;
+
+ spin_unlock_irqrestore(&mpp_chip->pm_lock, flags);
+
+ return rc;
+}
+
+static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+
+ return mpp_chip->irq_base + offset;
+}
+
+static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc;
+
+ if ((mpp_chip->ctrl_reg[offset] & PM8XXX_MPP_TYPE_MASK) >>
+ PM8XXX_MPP_TYPE_SHIFT == PM8XXX_MPP_TYPE_D_OUTPUT)
+ rc = mpp_chip->ctrl_reg[offset] & PM8XXX_MPP_CONFIG_CTRL_MASK;
+ else
+ rc = pm8xxx_read_irq_stat(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->irq_base + offset);
+
+ return rc;
+}
+
+static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = val ? PM8XXX_MPP_DOUT_CTRL_HIGH : PM8XXX_MPP_DOUT_CTRL_LOW;
+ int rc;
+
+ rc = pm8xxx_mpp_write(mpp_chip, offset, reg,
+ PM8XXX_MPP_CONFIG_CTRL_MASK);
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+}
+
+static int pm8xxx_mpp_dir_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc = pm8xxx_mpp_write(mpp_chip, offset,
+ PM8XXX_MPP_TYPE_D_INPUT << PM8XXX_MPP_TYPE_SHIFT,
+ PM8XXX_MPP_TYPE_MASK);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+ return rc;
+}
+
+static int pm8xxx_mpp_dir_output(struct gpio_chip *chip,
+ unsigned offset, int val)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = (PM8XXX_MPP_TYPE_D_OUTPUT << PM8XXX_MPP_TYPE_SHIFT) |
+ (val & PM8XXX_MPP_CONFIG_CTRL_MASK);
+ u8 mask = PM8XXX_MPP_TYPE_MASK | PM8XXX_MPP_CONFIG_CTRL_MASK;
+ int rc = pm8xxx_mpp_write(mpp_chip, offset, reg, mask);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+ return rc;
+}
+
+static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ static const char * const ctype[] = { "d_in", "d_out", "bi_dir",
+ "a_in", "a_out", "sink",
+ "dtest_sink", "dtest_out"
+ };
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 type, state;
+ const char *label;
+ int i;
+
+ for (i = 0; i < mpp_chip->nmpps; i++) {
+ label = gpiochip_is_requested(chip, i);
+ type = (mpp_chip->ctrl_reg[i] & PM8XXX_MPP_TYPE_MASK) >>
+ PM8XXX_MPP_TYPE_SHIFT;
+ state = pm8xxx_mpp_get(chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s 0x%02x\n",
+ chip->base + i,
+ label ? label : "--",
+ ctype[type],
+ state ? "hi" : "lo",
+ mpp_chip->ctrl_reg[i]);
+ }
+}
+
+int pm8xxx_mpp_config(unsigned mpp, struct pm8xxx_mpp_config_data *config)
+{
+ struct pm8xxx_mpp_chip *mpp_chip;
+ int rc, found = 0;
+ u8 config_reg, mask;
+
+ if (!config) {
+ pr_err("config not specified for MPP %d\n", mpp);
+ return -EINVAL;
+ }
+
+ mutex_lock(&pm8xxx_mpp_chips_lock);
+ list_for_each_entry(mpp_chip, &pm8xxx_mpp_chips, link) {
+ if (mpp >= mpp_chip->mpp_base
+ && mpp < mpp_chip->mpp_base + mpp_chip->nmpps) {
+ found = 1;
+ break;
+ }
+ }
+ mutex_unlock(&pm8xxx_mpp_chips_lock);
+ if (!found) {
+ pr_err("called on mpp %d not handled by any pmic\n", mpp);
+ return -EINVAL;
+ }
+
+ mask = PM8XXX_MPP_TYPE_MASK | PM8XXX_MPP_CONFIG_LVL_MASK |
+ PM8XXX_MPP_CONFIG_CTRL_MASK;
+ config_reg = (config->type << PM8XXX_MPP_TYPE_SHIFT)
+ & PM8XXX_MPP_TYPE_MASK;
+ config_reg |= (config->level << PM8XXX_MPP_CONFIG_LVL_SHIFT)
+ & PM8XXX_MPP_CONFIG_LVL_MASK;
+ config_reg |= config->control & PM8XXX_MPP_CONFIG_CTRL_MASK;
+
+ rc = pm8xxx_mpp_write(mpp_chip, mpp - mpp_chip->mpp_base, config_reg,
+ mask);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_mpp_config);
+
+static int __devinit pm8xxx_mpp_reg_init(struct pm8xxx_mpp_chip *mpp_chip)
+{
+ int rc, i;
+
+ for (i = 0; i < mpp_chip->nmpps; i++) {
+ rc = pm8xxx_readb(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->base_addr + i,
+ &mpp_chip->ctrl_reg[i]);
+ if (rc) {
+ pr_err("failed to read register 0x%x rc=%d\n",
+ mpp_chip->base_addr + i, rc);
+ return rc;
+ }
+ }
+ return 0;
+}
+
+static int __devinit pm8xxx_mpp_probe(struct platform_device *pdev)
+{
+ int rc;
+ const struct pm8xxx_mpp_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8xxx_mpp_chip *mpp_chip;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ return -EINVAL;
+ }
+
+ mpp_chip = kzalloc(sizeof(struct pm8xxx_mpp_chip), GFP_KERNEL);
+ if (!mpp_chip) {
+ pr_err("Cannot allocate %d bytes\n",
+ sizeof(struct pm8xxx_mpp_chip));
+ return -ENOMEM;
+ }
+
+ mpp_chip->ctrl_reg = kzalloc(pdata->core_data.nmpps, GFP_KERNEL);
+ if (!mpp_chip->ctrl_reg) {
+ pr_err("Cannot allocate %d bytes\n", pdata->core_data.nmpps);
+ rc = -ENOMEM;
+ goto free_mpp_chip;
+ }
+
+ spin_lock_init(&mpp_chip->pm_lock);
+
+ mpp_chip->gpio_chip.label = PM8XXX_MPP_DEV_NAME;
+ mpp_chip->gpio_chip.direction_input = pm8xxx_mpp_dir_input;
+ mpp_chip->gpio_chip.direction_output = pm8xxx_mpp_dir_output;
+ mpp_chip->gpio_chip.to_irq = pm8xxx_mpp_to_irq;
+ mpp_chip->gpio_chip.get = pm8xxx_mpp_get;
+ mpp_chip->gpio_chip.set = pm8xxx_mpp_set;
+ mpp_chip->gpio_chip.dbg_show = pm8xxx_mpp_dbg_show;
+ mpp_chip->gpio_chip.ngpio = pdata->core_data.nmpps;
+ mpp_chip->gpio_chip.can_sleep = 1;
+ mpp_chip->gpio_chip.dev = &pdev->dev;
+ mpp_chip->gpio_chip.base = pdata->mpp_base;
+ mpp_chip->irq_base = platform_get_irq(pdev, 0);
+ mpp_chip->mpp_base = pdata->mpp_base;
+ mpp_chip->base_addr = pdata->core_data.base_addr;
+ mpp_chip->nmpps = pdata->core_data.nmpps;
+
+ mutex_lock(&pm8xxx_mpp_chips_lock);
+ list_add(&mpp_chip->link, &pm8xxx_mpp_chips);
+ mutex_unlock(&pm8xxx_mpp_chips_lock);
+
+ platform_set_drvdata(pdev, mpp_chip);
+
+ rc = gpiochip_add(&mpp_chip->gpio_chip);
+ if (rc) {
+ pr_err("gpiochip_add failed, rc=%d\n", rc);
+ goto reset_drvdata;
+ }
+
+ rc = pm8xxx_mpp_reg_init(mpp_chip);
+ if (rc) {
+ pr_err("failed to read MPP ctrl registers, rc=%d\n", rc);
+ goto remove_chip;
+ }
+
+ pr_info("OK: base=%d, ngpio=%d\n", mpp_chip->gpio_chip.base,
+ mpp_chip->gpio_chip.ngpio);
+
+ return 0;
+
+remove_chip:
+ if (gpiochip_remove(&mpp_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+reset_drvdata:
+ platform_set_drvdata(pdev, NULL);
+free_mpp_chip:
+ kfree(mpp_chip);
+ return rc;
+}
+
+static int __devexit pm8xxx_mpp_remove(struct platform_device *pdev)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = platform_get_drvdata(pdev);
+
+ mutex_lock(&pm8xxx_mpp_chips_lock);
+ list_del(&mpp_chip->link);
+ mutex_unlock(&pm8xxx_mpp_chips_lock);
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&mpp_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ kfree(mpp_chip->ctrl_reg);
+ kfree(mpp_chip);
+
+ return 0;
+}
+
+static struct platform_driver pm8xxx_mpp_driver = {
+ .probe = pm8xxx_mpp_probe,
+ .remove = __devexit_p(pm8xxx_mpp_remove),
+ .driver = {
+ .name = PM8XXX_MPP_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8xxx_mpp_init(void)
+{
+ return platform_driver_register(&pm8xxx_mpp_driver);
+}
+postcore_initcall(pm8xxx_mpp_init);
+
+static void __exit pm8xxx_mpp_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_mpp_driver);
+}
+module_exit(pm8xxx_mpp_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PM8XXX MPP driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_MPP_DEV_NAME);
diff --git a/drivers/gpio/pmic8901-mpp.c b/drivers/gpio/pmic8901-mpp.c
new file mode 100644
index 0000000..85e6539
--- /dev/null
+++ b/drivers/gpio/pmic8901-mpp.c
@@ -0,0 +1,231 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+/*
+ * Qualcomm PMIC8901 MPP driver
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/mfd/pmic8901.h>
+#include <mach/mpp.h>
+#include <linux/seq_file.h>
+
+/* MPP Control Registers */
+#define SSBI_MPP_CNTRL_BASE 0x27
+#define SSBI_MPP_CNTRL(n) (SSBI_MPP_CNTRL_BASE + (n))
+
+/* MPP Type */
+#define PM8901_MPP_TYPE_MASK 0xE0
+#define PM8901_MPP_TYPE_SHIFT 5
+
+/* MPP Config Level */
+#define PM8901_MPP_CONFIG_LVL_MASK 0x1C
+#define PM8901_MPP_CONFIG_LVL_SHIFT 2
+
+/* MPP Config Control */
+#define PM8901_MPP_CONFIG_CTL_MASK 0x03
+
+struct pm8901_mpp_chip {
+ struct gpio_chip chip;
+ struct pm8901_chip *pm_chip;
+ u8 ctrl[PM8901_MPPS];
+};
+
+static int pm8901_mpp_write(struct pm8901_chip *chip, u16 addr, u8 val,
+ u8 mask, u8 *bak)
+{
+ u8 reg = (*bak & ~mask) | (val & mask);
+ int rc = pm8901_write(chip, addr, ®, 1);
+ if (!rc)
+ *bak = reg;
+ return rc;
+}
+
+static int pm8901_mpp_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8901_gpio_platform_data *pdata;
+ pdata = chip->dev->platform_data;
+ return pdata->irq_base + offset;
+}
+
+static int pm8901_mpp_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8901_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int ret;
+
+ if ((mpp_chip->ctrl[offset] & PM8901_MPP_TYPE_MASK) >>
+ PM8901_MPP_TYPE_SHIFT == PM_MPP_TYPE_D_OUTPUT)
+ ret = mpp_chip->ctrl[offset] & PM8901_MPP_CONFIG_CTL_MASK;
+ else
+ ret = pm8901_irq_get_rt_status(mpp_chip->pm_chip,
+ pm8901_mpp_to_irq(chip, offset));
+ return ret;
+}
+
+static void pm8901_mpp_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+ struct pm8901_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = val ? PM_MPP_DOUT_CTL_HIGH : PM_MPP_DOUT_CTL_LOW;
+ int rc;
+
+ rc = pm8901_mpp_write(mpp_chip->pm_chip, SSBI_MPP_CNTRL(offset),
+ reg, PM8901_MPP_CONFIG_CTL_MASK,
+ &mpp_chip->ctrl[offset]);
+ if (rc)
+ pr_err("%s: pm8901_mpp_write(): rc=%d\n", __func__, rc);
+}
+
+static int pm8901_mpp_dir_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8901_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc = pm8901_mpp_write(mpp_chip->pm_chip,
+ SSBI_MPP_CNTRL(offset),
+ PM_MPP_TYPE_D_INPUT << PM8901_MPP_TYPE_SHIFT,
+ PM8901_MPP_TYPE_MASK, &mpp_chip->ctrl[offset]);
+ if (rc)
+ pr_err("%s: pm8901_mpp_write(): rc=%d\n", __func__, rc);
+ return rc;
+}
+
+static int pm8901_mpp_dir_output(struct gpio_chip *chip,
+ unsigned offset, int val)
+{
+ struct pm8901_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = (PM_MPP_TYPE_D_OUTPUT << PM8901_MPP_TYPE_SHIFT) |
+ (val & PM8901_MPP_CONFIG_CTL_MASK);
+ u8 mask = PM8901_MPP_TYPE_MASK | PM8901_MPP_CONFIG_CTL_MASK;
+ int rc = pm8901_mpp_write(mpp_chip->pm_chip,
+ SSBI_MPP_CNTRL(offset), reg, mask,
+ &mpp_chip->ctrl[offset]);
+ if (rc)
+ pr_err("%s: pm8901_mpp_write(): rc=%d\n", __func__, rc);
+ return rc;
+}
+
+static void pm8901_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ static const char *ctype[] = { "d_in", "d_out", "bi_dir", "a_in",
+ "a_out", "sink", "dtest_sink", "dtest_out" };
+ struct pm8901_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 type, state;
+ const char *label;
+ int i;
+
+ for (i = 0; i < PM8901_MPPS; i++) {
+ label = gpiochip_is_requested(chip, i);
+ type = (mpp_chip->ctrl[i] & PM8901_MPP_TYPE_MASK) >>
+ PM8901_MPP_TYPE_SHIFT;
+ state = pm8901_mpp_get(chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s 0x%02x\n",
+ chip->base + i,
+ label ? label : "--",
+ ctype[type],
+ state ? "hi" : "lo",
+ mpp_chip->ctrl[i]);
+ }
+}
+
+static struct pm8901_mpp_chip pm8901_mpp_chip = {
+ .chip = {
+ .label = "pm8901-mpp",
+ .to_irq = pm8901_mpp_to_irq,
+ .get = pm8901_mpp_get,
+ .set = pm8901_mpp_set,
+ .direction_input = pm8901_mpp_dir_input,
+ .direction_output = pm8901_mpp_dir_output,
+ .dbg_show = pm8901_mpp_dbg_show,
+ .ngpio = PM8901_MPPS,
+ },
+};
+
+int pm8901_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control)
+{
+ u8 config, mask;
+ int rc;
+
+ if (mpp >= PM8901_MPPS)
+ return -EINVAL;
+
+ mask = PM8901_MPP_TYPE_MASK | PM8901_MPP_CONFIG_LVL_MASK |
+ PM8901_MPP_CONFIG_CTL_MASK;
+ config = (type << PM8901_MPP_TYPE_SHIFT) & PM8901_MPP_TYPE_MASK;
+ config |= (level << PM8901_MPP_CONFIG_LVL_SHIFT) &
+ PM8901_MPP_CONFIG_LVL_MASK;
+ config |= control & PM8901_MPP_CONFIG_CTL_MASK;
+
+ rc = pm8901_mpp_write(pm8901_mpp_chip.pm_chip, SSBI_MPP_CNTRL(mpp),
+ config, mask, &pm8901_mpp_chip.ctrl[mpp]);
+ if (rc)
+ pr_err("%s: pm8901_mpp_write(): rc=%d\n", __func__, rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8901_mpp_config);
+
+static int __devinit pm8901_mpp_probe(struct platform_device *pdev)
+{
+ int ret, i;
+ struct pm8901_gpio_platform_data *pdata = pdev->dev.platform_data;
+
+ pm8901_mpp_chip.pm_chip = dev_get_drvdata(pdev->dev.parent);
+ for (i = 0; i < PM8901_MPPS; i++) {
+ ret = pm8901_read(pm8901_mpp_chip.pm_chip,
+ SSBI_MPP_CNTRL(i), &pm8901_mpp_chip.ctrl[i], 1);
+ if (ret)
+ goto bail;
+
+ }
+ platform_set_drvdata(pdev, &pm8901_mpp_chip);
+ pm8901_mpp_chip.chip.dev = &pdev->dev;
+ pm8901_mpp_chip.chip.base = pdata->gpio_base;
+ ret = gpiochip_add(&pm8901_mpp_chip.chip);
+
+bail:
+ pr_info("%s: gpiochip_add(): rc=%d\n", __func__, ret);
+ return ret;
+}
+
+static int __devexit pm8901_mpp_remove(struct platform_device *pdev)
+{
+ return gpiochip_remove(&pm8901_mpp_chip.chip);
+}
+
+static struct platform_driver pm8901_mpp_driver = {
+ .probe = pm8901_mpp_probe,
+ .remove = __devexit_p(pm8901_mpp_remove),
+ .driver = {
+ .name = "pm8901-mpp",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8901_mpp_init(void)
+{
+ return platform_driver_register(&pm8901_mpp_driver);
+}
+
+static void __exit pm8901_mpp_exit(void)
+{
+ platform_driver_unregister(&pm8901_mpp_driver);
+}
+
+subsys_initcall(pm8901_mpp_init);
+module_exit(pm8901_mpp_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC8901 MPP driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:pm8901-mpp");
diff --git a/drivers/gpio/sx150x.c b/drivers/gpio/sx150x.c
index a4f7353..93b94bd 100644
--- a/drivers/gpio/sx150x.c
+++ b/drivers/gpio/sx150x.c
@@ -8,11 +8,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/i2c.h>
@@ -189,9 +184,9 @@
return err;
}
-static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
+static s32 sx150x_set_oscio(struct sx150x_chip *chip, int val)
{
- sx150x_i2c_write(chip->client,
+ return sx150x_i2c_write(chip->client,
chip->dev_cfg->reg_clock,
(val ? 0x1f : 0x10));
}
@@ -286,11 +281,13 @@
chip = container_of(gc, struct sx150x_chip, gpio_chip);
- if (!offset_is_oscio(chip, offset)) {
- mutex_lock(&chip->lock);
+ mutex_lock(&chip->lock);
+ if (offset_is_oscio(chip, offset))
+ status = sx150x_set_oscio(chip, val);
+ else
status = sx150x_io_output(chip, offset, val);
- mutex_unlock(&chip->lock);
- }
+ mutex_unlock(&chip->lock);
+
return status;
}