Initial Contribution

msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142

Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 01f6362..32d814b 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -18,6 +18,7 @@
 header-y += netfilter_ipv6/
 header-y += usb/
 header-y += wimax/
+header-y += mfd/
 
 objhdr-y += version.h
 
@@ -96,6 +97,7 @@
 header-y += connector.h
 header-y += const.h
 header-y += cramfs_fs.h
+header-y += csdio.h
 header-y += cuda.h
 header-y += cyclades.h
 header-y += cycx_cfm.h
@@ -228,6 +230,7 @@
 header-y += l2tp.h
 header-y += limits.h
 header-y += llc.h
+header-y += l2tp.h
 header-y += loop.h
 header-y += lp.h
 header-y += magic.h
@@ -246,6 +249,7 @@
 header-y += mroute6.h
 header-y += msdos_fs.h
 header-y += msg.h
+header-y += msm_adc.h
 header-y += mtio.h
 header-y += n_r3964.h
 header-y += nbd.h
@@ -399,3 +403,21 @@
 header-y += x25.h
 header-y += xattr.h
 header-y += xfrm.h
+header-y += msm_adsp.h
+header-y += msm_mdp.h
+header-y += msm_kgsl.h
+header-y += msm_q6venc.h
+header-y += msm_q6vdec.h
+header-y += msm_rotator.h
+header-y += msm_vidc_dec.h
+header-y += msm_vidc_enc.h
+header-y += msm_audio.h
+header-y += msm_audio_aac.h
+header-y += msm_audio_acdb.h
+header-y += android_pmem.h
+header-y += msm_audio_wma.h
+header-y += msm_audio_wmapro.h
+header-y += msm_audio_mvs.h
+header-y += msm_ipc.h
+header-y += msm_charm.h
+header-y += tzcom.h
diff --git a/include/linux/adv7520.h b/include/linux/adv7520.h
new file mode 100644
index 0000000..96db7b7
--- /dev/null
+++ b/include/linux/adv7520.h
@@ -0,0 +1,24 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ADV7520_H_
+#define _ADV7520_H_
+#define ADV7520_DRV_NAME 		"adv7520"
+
+/* Configure the 20-bit 'N' used with the CTS to
+regenerate the audio clock in the receiver
+Pixel clock: 74.25 Mhz, Audio sampling: 44.1 Khz -> N
+value = 6272 */
+#define ADV7520_AUDIO_CTS_20BIT_N   6272
+
+#endif
diff --git a/include/linux/android_alarm.h b/include/linux/android_alarm.h
index f8f14e7..cbfeafc 100644
--- a/include/linux/android_alarm.h
+++ b/include/linux/android_alarm.h
@@ -74,6 +74,7 @@
 
 /* set rtc while preserving elapsed realtime */
 int alarm_set_rtc(const struct timespec ts);
+void alarm_update_timedelta(struct timespec tv, struct timespec ts);
 
 #endif
 
diff --git a/include/linux/android_pmem.h b/include/linux/android_pmem.h
index f633621..f42d74b 100644
--- a/include/linux/android_pmem.h
+++ b/include/linux/android_pmem.h
@@ -16,6 +16,20 @@
 #ifndef _ANDROID_PMEM_H_
 #define _ANDROID_PMEM_H_
 
+#include <linux/fs.h>
+
+#define PMEM_KERNEL_TEST_MAGIC 0xc0
+#define PMEM_KERNEL_TEST_NOMINAL_TEST_IOCTL \
+	_IO(PMEM_KERNEL_TEST_MAGIC, 1)
+#define PMEM_KERNEL_TEST_ADVERSARIAL_TEST_IOCTL \
+	_IO(PMEM_KERNEL_TEST_MAGIC, 2)
+#define PMEM_KERNEL_TEST_HUGE_ALLOCATION_TEST_IOCTL \
+	_IO(PMEM_KERNEL_TEST_MAGIC, 3)
+#define PMEM_KERNEL_TEST_FREE_UNALLOCATED_TEST_IOCTL \
+	_IO(PMEM_KERNEL_TEST_MAGIC, 4)
+#define PMEM_KERNEL_TEST_LARGE_REGION_NUMBER_TEST_IOCTL \
+	_IO(PMEM_KERNEL_TEST_MAGIC, 5)
+
 #define PMEM_IOCTL_MAGIC 'p'
 #define PMEM_GET_PHYS		_IOW(PMEM_IOCTL_MAGIC, 1, unsigned int)
 #define PMEM_MAP		_IOW(PMEM_IOCTL_MAGIC, 2, unsigned int)
@@ -33,61 +47,123 @@
  * struct (with offset set to 0). 
  */
 #define PMEM_GET_TOTAL_SIZE	_IOW(PMEM_IOCTL_MAGIC, 7, unsigned int)
-#define PMEM_CACHE_FLUSH	_IOW(PMEM_IOCTL_MAGIC, 8, unsigned int)
+/* Revokes gpu registers and resets the gpu.  Pass a pointer to the
+ * start of the mapped gpu regs (the vaddr returned by mmap) as the argument.
+ */
+#define HW3D_REVOKE_GPU		_IOW(PMEM_IOCTL_MAGIC, 8, unsigned int)
+#define HW3D_GRANT_GPU		_IOW(PMEM_IOCTL_MAGIC, 9, unsigned int)
+#define HW3D_WAIT_FOR_INTERRUPT	_IOW(PMEM_IOCTL_MAGIC, 10, unsigned int)
+
+#define PMEM_CLEAN_INV_CACHES	_IOW(PMEM_IOCTL_MAGIC, 11, unsigned int)
+#define PMEM_CLEAN_CACHES	_IOW(PMEM_IOCTL_MAGIC, 12, unsigned int)
+#define PMEM_INV_CACHES		_IOW(PMEM_IOCTL_MAGIC, 13, unsigned int)
+
+#define PMEM_GET_FREE_SPACE	_IOW(PMEM_IOCTL_MAGIC, 14, unsigned int)
+#define PMEM_ALLOCATE_ALIGNED	_IOW(PMEM_IOCTL_MAGIC, 15, unsigned int)
+struct pmem_region {
+	unsigned long offset;
+	unsigned long len;
+};
+
+struct pmem_addr {
+	unsigned long vaddr;
+	unsigned long offset;
+	unsigned long length;
+};
+
+struct pmem_freespace {
+	unsigned long total;
+	unsigned long largest;
+};
+
+struct pmem_allocation {
+	unsigned long size;
+	unsigned int align;
+};
+
+#ifdef __KERNEL__
+int get_pmem_file(unsigned int fd, unsigned long *start, unsigned long *vstart,
+		  unsigned long *end, struct file **filp);
+int get_pmem_fd(int fd, unsigned long *start, unsigned long *end);
+int get_pmem_user_addr(struct file *file, unsigned long *start,
+		       unsigned long *end);
+void put_pmem_file(struct file* file);
+void put_pmem_fd(int fd);
+void flush_pmem_fd(int fd, unsigned long start, unsigned long len);
+void flush_pmem_file(struct file *file, unsigned long start, unsigned long len);
+int pmem_cache_maint(struct file *file, unsigned int cmd,
+		struct pmem_addr *pmem_addr);
+
+enum pmem_allocator_type {
+	/* Zero is a default in platform PMEM structures in the board files,
+	 * when the "allocator_type" structure element is not explicitly
+	 * defined
+	 */
+	PMEM_ALLOCATORTYPE_BITMAP = 0, /* forced to be zero here */
+	PMEM_ALLOCATORTYPE_SYSTEM,
+
+	PMEM_ALLOCATORTYPE_ALLORNOTHING,
+	PMEM_ALLOCATORTYPE_BUDDYBESTFIT,
+
+	PMEM_ALLOCATORTYPE_MAX,
+};
+
+#define PMEM_MEMTYPE_MASK 0x7
+#define PMEM_INVALID_MEMTYPE 0x0
+#define PMEM_MEMTYPE_EBI1 0x1
+#define PMEM_MEMTYPE_SMI  0x2
+#define PMEM_MEMTYPE_RESERVED_INVALID2 0x3
+#define PMEM_MEMTYPE_RESERVED_INVALID3 0x4
+#define PMEM_MEMTYPE_RESERVED_INVALID4 0x5
+#define PMEM_MEMTYPE_RESERVED_INVALID5 0x6
+#define PMEM_MEMTYPE_RESERVED_INVALID6 0x7
+
+#define PMEM_ALIGNMENT_MASK 0x18
+#define PMEM_ALIGNMENT_RESERVED_INVALID1 0x0
+#define PMEM_ALIGNMENT_4K 0x8 /* the default */
+#define PMEM_ALIGNMENT_1M 0x10
+#define PMEM_ALIGNMENT_RESERVED_INVALID2 0x18
+
+/* flags in the following function defined as above. */
+int32_t pmem_kalloc(const size_t size, const uint32_t flags);
+int32_t pmem_kfree(const int32_t physaddr);
+
+/* kernel api names for board specific data structures */
+#define PMEM_KERNEL_EBI1_DATA_NAME "pmem_kernel_ebi1"
+#define PMEM_KERNEL_SMI_DATA_NAME "pmem_kernel_smi"
 
 struct android_pmem_platform_data
 {
 	const char* name;
-	/* starting physical address of memory region */
-	unsigned long start;
 	/* size of memory region */
 	unsigned long size;
-	/* set to indicate the region should not be managed with an allocator */
-	unsigned no_allocator;
+
+	enum pmem_allocator_type allocator_type;
+	/* treated as a 'hidden' variable in the board files. Can be
+	 * set, but default is the system init value of 0 which becomes a
+	 * quantum of 4K pages.
+	 */
+	unsigned int quantum;
+
 	/* set to indicate maps of this region should be cached, if a mix of
 	 * cached and uncached is desired, set this and open the device with
 	 * O_SYNC to get an uncached region */
 	unsigned cached;
 	/* The MSM7k has bits to enable a write buffer in the bus controller*/
 	unsigned buffered;
+	/* This PMEM is on memory that may be powered off */
+	unsigned unstable;
+	/* which memory type (i.e. SMI, EBI1) this PMEM device is backed by */
+	unsigned memory_type;
 };
 
-struct pmem_region {
-	unsigned long offset;
-	unsigned long len;
-};
-
-#ifdef CONFIG_ANDROID_PMEM
-int is_pmem_file(struct file *file);
-int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart,
-		  unsigned long *end, struct file **filp);
-int get_pmem_user_addr(struct file *file, unsigned long *start,
-		       unsigned long *end);
-void put_pmem_file(struct file* file);
-void flush_pmem_file(struct file *file, unsigned long start, unsigned long len);
 int pmem_setup(struct android_pmem_platform_data *pdata,
 	       long (*ioctl)(struct file *, unsigned int, unsigned long),
 	       int (*release)(struct inode *, struct file *));
+
 int pmem_remap(struct pmem_region *region, struct file *file,
 	       unsigned operation);
-
-#else
-static inline int is_pmem_file(struct file *file) { return 0; }
-static inline int get_pmem_file(int fd, unsigned long *start,
-				unsigned long *vstart, unsigned long *end,
-				struct file **filp) { return -ENOSYS; }
-static inline int get_pmem_user_addr(struct file *file, unsigned long *start,
-				     unsigned long *end) { return -ENOSYS; }
-static inline void put_pmem_file(struct file* file) { return; }
-static inline void flush_pmem_file(struct file *file, unsigned long start,
-				   unsigned long len) { return; }
-static inline int pmem_setup(struct android_pmem_platform_data *pdata,
-	      long (*ioctl)(struct file *, unsigned int, unsigned long),
-	      int (*release)(struct inode *, struct file *)) { return -ENOSYS; }
-
-static inline int pmem_remap(struct pmem_region *region, struct file *file,
-			     unsigned operation) { return -ENOSYS; }
-#endif
+#endif /* __KERNEL__ */
 
 #endif //_ANDROID_PPP_H_
 
diff --git a/include/linux/ashmem.h b/include/linux/ashmem.h
index 1976b10..c05c180 100644
--- a/include/linux/ashmem.h
+++ b/include/linux/ashmem.h
@@ -44,5 +44,10 @@
 #define ASHMEM_UNPIN		_IOW(__ASHMEMIOC, 8, struct ashmem_pin)
 #define ASHMEM_GET_PIN_STATUS	_IO(__ASHMEMIOC, 9)
 #define ASHMEM_PURGE_ALL_CACHES	_IO(__ASHMEMIOC, 10)
+#define ASHMEM_CACHE_FLUSH_RANGE	_IO(__ASHMEMIOC, 11)
+
+int get_ashmem_file(int fd, struct file **filp, struct file **vm_file,
+			unsigned long *len);
+void put_ashmem_file(struct file *file);
 
 #endif	/* _LINUX_ASHMEM_H */
diff --git a/include/linux/atmel_maxtouch.h b/include/linux/atmel_maxtouch.h
new file mode 100644
index 0000000..c582529
--- /dev/null
+++ b/include/linux/atmel_maxtouch.h
@@ -0,0 +1,317 @@
+/*
+ *  Atmel maXTouch header file
+ *  
+ *  Copyright (c) 2010 Atmel Corporation
+ *  Copyright (C) 2010 Ulf Samuelsson (ulf@atmel.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *  See the file "COPYING" in the main directory of this archive
+ *  for more details.
+ *
+ */
+
+#define	MXT224_I2C_ADDR1				0x4A
+#define	MXT224_I2C_ADDR2				0x4B
+#define	MXT1386_I2C_ADDR1				0x4C
+#define	MXT1386_I2C_ADDR2				0x4D
+#define	MXT1386_I2C_ADDR3				0x5A
+#define	MXT1386_I2C_ADDR4				0x5B
+
+/*
+ * Select this address from above depending on what maXTouch
+ * chip you have and how it's address pins are configured;
+ * see datasheet.
+ */
+
+#define MXT_I2C_ADDRESS                                 MXT224_I2C_ADDR2
+
+#define MXT_BL_ADDRESS                                  0x25
+
+#define	MXT224_FAMILYID				        0x80
+#define MXT1386_FAMILYID                                0xA0
+
+#define	MXT224_CAL_VARIANTID				0x01
+#define MXT224_UNCAL_VARIANTID                          0x00
+#define MXT1386_CAL_VARIANTID                           0x00
+
+#define MXT_MAX_REPORTED_WIDTH                          255
+#define MXT_MAX_REPORTED_PRESSURE                       255
+#define MXT_MAX_TOUCH_SIZE                              255
+#define MXT_MAX_NUM_TOUCHES                             10
+
+/* Fixed addresses inside maXTouch device */
+#define	MXT_ADDR_INFO_BLOCK				0
+#define	MXT_ADDR_OBJECT_TABLE				7
+#define MXT_ID_BLOCK_SIZE                               7
+#define	MXT_OBJECT_TABLE_ELEMENT_SIZE			6
+
+/* Object types */
+#define	MXT_DEBUG_DELTAS_T2				2
+#define	MXT_DEBUG_REFERENCES_T3				3
+#define	MXT_GEN_MESSAGEPROCESSOR_T5			5
+#define	MXT_GEN_COMMANDPROCESSOR_T6			6
+#define	MXT_GEN_POWERCONFIG_T7				7
+#define	MXT_GEN_ACQUIRECONFIG_T8			8
+#define	MXT_TOUCH_MULTITOUCHSCREEN_T9			9
+#define MXT_TOUCH_SINGLETOUCHSCREEN_T10                 10
+#define MXT_TOUCH_XSLIDER_T11                           11
+#define MXT_TOUCH_YSLIDER_T12                           12
+#define MXT_TOUCH_XWHEEL_T13                            13
+#define MXT_TOUCH_YWHEEL_T14                            14
+#define	MXT_TOUCH_KEYARRAY_T15				15
+#define	MXT_SPT_GPIOPWM_T19				19
+#define	MXT_PROCI_GRIPFACESUPPRESSION_T20		20
+#define	MXT_PROCG_NOISESUPPRESSION_T22			22
+#define	MXT_TOUCH_PROXIMITY_T23				23
+#define	MXT_PROCI_ONETOUCHGESTUREPROCESSOR_T24		24
+#define	MXT_SPT_SELFTEST_T25				25
+#define MXT_DEBUG_CTERANGE_T26				26
+#define	MXT_PROCI_TWOTOUCHGESTUREPROCESSOR_T27		27
+#define	MXT_SPT_CTECONFIG_T28				28
+#define	MXT_TOUCH_KEYSET_T31				31
+#define	MXT_TOUCH_XSLIDERSET_T32			32
+#define	MXT_DEBUG_DIAGNOSTIC_T37			37
+#define	MXT_USER_INFO_T38				38
+
+
+/*
+ * If a message is read from mXT when there's no new messages available,
+ * the report ID of the message will be 0xFF.
+ */
+#define	MXT_END_OF_MESSAGES				0xFF
+
+
+/* GEN_COMMANDPROCESSOR_T6 Register offsets from T6 base address */
+#define	MXT_ADR_T6_RESET				0x00
+#define	MXT_ADR_T6_BACKUPNV				0x01
+#define	MXT_ADR_T6_CALIBRATE				0x02
+#define	MXT_ADR_T6_REPORTALL				0x03
+#define	MXT_ADR_T6_RESERVED				0x04
+#define	MXT_ADR_T6_DIAGNOSTIC				0x05
+
+/* T6 Debug Diagnostics Commands */
+#define	MXT_CMD_T6_PAGE_UP          0x01
+#define	MXT_CMD_T6_PAGE_DOWN        0x02
+#define	MXT_CMD_T6_DELTAS_MODE      0x10
+#define	MXT_CMD_T6_REFERENCES_MODE  0x11
+#define	MXT_CMD_T6_CTE_MODE         0x31
+
+/* T6 Backup Command */
+#define MXT_CMD_T6_BACKUP           0x55
+
+/* SPT_DEBUG_DIAGNOSTIC_T37 Register offsets from T37 base address */
+#define MXT_ADR_T37_PAGE                                0x01
+#define	MXT_ADR_T37_DATA				0x02
+
+
+
+/************************************************************************
+ * MESSAGE OBJECTS ADDRESS FIELDS
+ *
+ ************************************************************************/
+#define MXT_MSG_REPORTID                                0x00
+
+
+/* MXT_GEN_MESSAGEPROCESSOR_T5 Message address definitions		*/
+#define	MXT_MSG_T5_REPORTID				0x00
+#define	MXT_MSG_T5_MESSAGE				0x01
+#define	MXT_MSG_T5_CHECKSUM				0x08
+
+/* MXT_GEN_COMMANDPROCESSOR_T6 Message address definitions		*/
+#define	MXT_MSG_T6_STATUS				0x01
+#define		MXT_MSGB_T6_COMSERR		0x04
+#define		MXT_MSGB_T6_CFGERR		0x08
+#define		MXT_MSGB_T6_CAL			0x10
+#define		MXT_MSGB_T6_SIGERR		0x20
+#define		MXT_MSGB_T6_OFL			0x40
+#define		MXT_MSGB_T6_RESET		0x80
+/* Three bytes */
+#define	MXT_MSG_T6_CHECKSUM				0x02
+
+/* MXT_GEN_POWERCONFIG_T7 NO Message address definitions		*/
+/* MXT_GEN_ACQUIRECONFIG_T8 Message address definitions			*/
+/* MXT_TOUCH_MULTITOUCHSCREEN_T9 Message address definitions		*/
+
+#define	MXT_MSG_T9_STATUS				0x01
+/* Status bit field */
+#define		MXT_MSGB_T9_SUPPRESS		0x02
+#define		MXT_MSGB_T9_AMP			0x04
+#define		MXT_MSGB_T9_VECTOR		0x08
+#define		MXT_MSGB_T9_MOVE		0x10
+#define		MXT_MSGB_T9_RELEASE		0x20
+#define		MXT_MSGB_T9_PRESS		0x40
+#define		MXT_MSGB_T9_DETECT		0x80
+
+#define	MXT_MSG_T9_XPOSMSB				0x02
+#define	MXT_MSG_T9_YPOSMSB				0x03
+#define	MXT_MSG_T9_XYPOSLSB				0x04
+#define	MXT_MSG_T9_TCHAREA				0x05
+#define	MXT_MSG_T9_TCHAMPLITUDE				0x06
+#define	MXT_MSG_T9_TCHVECTOR				0x07
+
+
+/* MXT_SPT_GPIOPWM_T19 Message address definitions			*/
+#define	MXT_MSG_T19_STATUS				0x01
+
+/* MXT_PROCI_GRIPFACESUPPRESSION_T20 Message address definitions	*/
+#define	MXT_MSG_T20_STATUS				0x01
+#define		MXT_MSGB_T20_FACE_SUPPRESS	0x01
+/* MXT_PROCG_NOISESUPPRESSION_T22 Message address definitions		*/
+#define	MXT_MSG_T22_STATUS				0x01
+#define		MXT_MSGB_T22_FHCHG		0x01
+#define		MXT_MSGB_T22_GCAFERR		0x04
+#define		MXT_MSGB_T22_FHERR		0x08
+#define	MXT_MSG_T22_GCAFDEPTH				0x02
+
+/* MXT_TOUCH_PROXIMITY_T23 Message address definitions			*/
+#define	MXT_MSG_T23_STATUS				0x01
+#define		MXT_MSGB_T23_FALL		0x20
+#define		MXT_MSGB_T23_RISE		0x40
+#define		MXT_MSGB_T23_DETECT		0x80
+/* 16 bit */
+#define	MXT_MSG_T23_PROXDELTA				0x02
+
+/* MXT_PROCI_ONETOUCHGESTUREPROCESSOR_T24 Message address definitions	*/
+#define	MXT_MSG_T24_STATUS				0x01
+#define	MXT_MSG_T24_XPOSMSB				0x02
+#define	MXT_MSG_T24_YPOSMSB				0x03
+#define	MXT_MSG_T24_XYPOSLSB				0x04
+#define	MXT_MSG_T24_DIR					0x05
+/* 16 bit */
+#define	MXT_MSG_T24_DIST				0x06
+
+/* MXT_SPT_SELFTEST_T25 Message address definitions			*/
+#define	MXT_MSG_T25_STATUS				0x01
+/* 5 Bytes */
+#define		MXT_MSGR_T25_OK			0xFE
+#define		MXT_MSGR_T25_INVALID_TEST	0xFD
+#define		MXT_MSGR_T25_PIN_FAULT		0x11
+#define		MXT_MSGR_T25_SIGNAL_LIMIT_FAULT	0x17
+#define		MXT_MSGR_T25_GAIN_ERROR		0x20
+#define	MXT_MSG_T25_INFO				0x02
+
+/* MXT_PROCI_TWOTOUCHGESTUREPROCESSOR_T27 Message address definitions	*/
+#define	MXT_MSG_T27_STATUS			0x01
+#define		MXT_MSGB_T27_ROTATEDIR		0x10
+#define		MXT_MSGB_T27_PINCH		0x20
+#define		MXT_MSGB_T27_ROTATE		0x40
+#define		MXT_MSGB_T27_STRETCH		0x80
+#define	MXT_MSG_T27_XPOSMSB			0x02
+#define	MXT_MSG_T27_YPOSMSB			0x03
+#define	MXT_MSG_T27_XYPOSLSB			0x04
+#define	MXT_MSG_T27_ANGLE			0x05
+
+/* 16 bit */
+#define	MXT_MSG_T27_SEPARATION				0x06
+
+/* MXT_SPT_CTECONFIG_T28 Message address definitions			*/
+#define	MXT_MSG_T28_STATUS				0x01
+#define	MXT_MSGB_T28_CHKERR		0x01
+
+
+/* One Touch Events */
+#define	MXT_GESTURE_RESERVED		0x00
+#define	MXT_GESTURE_PRESS		0x01
+#define	MXT_GESTURE_RELEASE		0x02
+#define	MXT_GESTURE_TAP			0x03
+#define	MXT_GESTURE_DOUBLE_TAP		0x04
+#define	MXT_GESTURE_FLICK		0x05
+#define	MXT_GESTURE_DRAG		0x06
+#define	MXT_GESTURE_SHORT_PRESS		0x07
+#define	MXT_GESTURE_LONG_PRESS		0x08
+#define	MXT_GESTURE_REPEAT_PRESS	0x09
+#define	MXT_GESTURE_TAP_AND_PRESS	0x0a
+#define	MXT_GESTURE_THROW		0x0b
+
+/* Two-touch events */
+#define MXT_GESTURE_STRETCH             (1 << 7)
+#define MXT_GESTURE_ROTATE              (1 << 6)
+#define MXT_GESTURE_PINCH               (1 << 5)
+#define MXT_GESTURE_ROTATEDIR           (1 << 4)
+
+
+
+/* Bootloader states */
+#define WAITING_BOOTLOAD_COMMAND   0xC0
+#define WAITING_FRAME_DATA         0x80
+#define APP_CRC_FAIL               0x40
+#define FRAME_CRC_CHECK            0x02
+#define FRAME_CRC_PASS             0x04
+#define FRAME_CRC_FAIL             0x03
+
+#define MXT_MAX_FRAME_SIZE         276
+
+/* Debug levels */
+#define DEBUG_INFO     1
+#define DEBUG_VERBOSE  2
+#define DEBUG_MESSAGES 5
+#define DEBUG_RAW      8
+#define DEBUG_TRACE   10
+
+/* IOCTL commands */
+/* TODO: get correct numbers! */
+#define MXT_SET_ADDRESS_IOCTL ('x' + 1)  /* Sets the internal address pointer */
+#define MXT_RESET_IOCTL       ('x' + 2)  /* Resets the device */
+#define MXT_CALIBRATE_IOCTL   ('x' + 3)  /* Calibrates the device */
+/* Backups the current state of registers to NVM */
+#define MXT_BACKUP_IOCTL      ('x' + 4) 
+/*
+ * Only non-touch messages can be read from the message buffer 
+ * (/dev/maXTouch_messages)
+ */
+#define MXT_NONTOUCH_MSG_IOCTL ('x' + 5)
+/* All messages can be read from the message buffer */
+#define MXT_ALL_MSG_IOCTL ('x' + 6)  
+
+
+/* Message buffer size. This is a ring buffer, and when full, the oldest entry
+   will be overwritten. */
+#define MXT_MESSAGE_BUFFER_SIZE  128
+
+/* Routines for memory access within a 16 bit address space */
+
+/* TODO: - won't compile if functions aren't defined*/
+/* Bootloader specific function prototypes. */
+
+#if 0
+static int mxt_read_byte_bl(struct i2c_client *client, u8 *value);
+static int mxt_read_block_bl(struct i2c_client *client, u16 length, u8 *value);
+static int mxt_write_byte_bl(struct i2c_client *client, u8 value);
+static int mxt_write_block_bl(struct i2c_client *client, u16 length, u8 *value);
+#endif
+
+/**
+ * struct mxt_platform_data - includes platform specific informatio
+ * related to Atmel maXTouch touchscreen controller.
+ * 
+ * @numtouch:           Number of simultaneous touches supported
+ * @init_platform_hw(): Initialization function, which can for example
+ *                      trigger a hardware reset by toggling a GPIO pin
+ * @exit_platform_hw(): Function to run when the driver is unloaded.
+ * @valid_interrupt():  Function that checks the validity of the interrupt -
+ *                      function that check the validity of a interrupt (by
+ *                      reading the changeline interrupt pin and checking that
+ *                      it really is low for example).
+ * @max_x:              Reported X range
+ * @max_y:              Reported Y range
+ */
+ 
+struct mxt_platform_data {
+	u8    numtouch;	/* Number of touches to report	*/
+	int   (*init_platform_hw)(struct i2c_client *client);
+	int   (*exit_platform_hw)(struct i2c_client *client);
+	int   display_res_x;
+	int   display_res_y;
+	int   min_x;
+	int   min_y;
+	int   max_x;    /* The default reported X range   */  
+	int   max_y;    /* The default reported Y range   */
+	u8    (*valid_interrupt) (void);
+	u8    (*read_chg) (void);
+	bool wakeup;
+	int (*power_on)(bool on);
+};
+
+void	mxt_hw_reset(void);
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index dcafe0b..50e2c16 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -45,6 +45,7 @@
  * bitmap_set(dst, pos, nbits)			Set specified bit area
  * bitmap_clear(dst, pos, nbits)		Clear specified bit area
  * bitmap_find_next_zero_area(buf, len, pos, n, mask)	Find bit free area
+ * bitmap_find_next_zero_area_off(buf, len, pos, n, mask)	as above
  * bitmap_shift_right(dst, src, n, nbits)	*dst = *src >> n
  * bitmap_shift_left(dst, src, n, nbits)	*dst = *src << n
  * bitmap_remap(dst, src, old, new, nbits)	*dst = map(old, new)(src)
@@ -114,11 +115,24 @@
 
 extern void bitmap_set(unsigned long *map, int i, int len);
 extern void bitmap_clear(unsigned long *map, int start, int nr);
-extern unsigned long bitmap_find_next_zero_area(unsigned long *map,
-					 unsigned long size,
-					 unsigned long start,
-					 unsigned int nr,
-					 unsigned long align_mask);
+
+extern unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
+						    unsigned long size,
+						    unsigned long start,
+						    unsigned int nr,
+						    unsigned long align_mask,
+						    unsigned long align_offset);
+
+static inline unsigned long
+bitmap_find_next_zero_area(unsigned long *map,
+			   unsigned long size,
+			   unsigned long start,
+			   unsigned int nr,
+			   unsigned long align_mask)
+{
+	return bitmap_find_next_zero_area_off(map, size, start, nr,
+					      align_mask, 0);
+}
 
 extern int bitmap_scnprintf(char *buf, unsigned int len,
 			const unsigned long *src, int nbits);
diff --git a/include/linux/bma150.h b/include/linux/bma150.h
new file mode 100644
index 0000000..a3d1c4f
--- /dev/null
+++ b/include/linux/bma150.h
@@ -0,0 +1,31 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef LINUX_BMA150_MODULE_H
+#define LINUX_BMA150_MODULE_H
+
+/**
+ * struct bma150_platform_data - data to set up bma150 driver
+ *
+ * @setup: optional callback to activate the driver.
+ * @teardown: optional callback to invalidate the driver.
+ *
+**/
+
+struct bma150_platform_data {
+	int (*setup)(struct device *);
+	void (*teardown)(struct device *);
+	int (*power_on)(void);
+	void (*power_off)(void);
+};
+
+#endif /* LINUX_BMA150_MODULE_H */
diff --git a/include/linux/completion.h b/include/linux/completion.h
index 51494e6..a5b2e1c 100644
--- a/include/linux/completion.h
+++ b/include/linux/completion.h
@@ -77,6 +77,7 @@
 }
 
 extern void wait_for_completion(struct completion *);
+extern void wait_for_completion_io(struct completion *);
 extern int wait_for_completion_interruptible(struct completion *x);
 extern int wait_for_completion_killable(struct completion *x);
 extern unsigned long wait_for_completion_timeout(struct completion *x,
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index ae06dc9..957c5b4 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -199,6 +199,8 @@
 int cpufreq_register_governor(struct cpufreq_governor *governor);
 void cpufreq_unregister_governor(struct cpufreq_governor *governor);
 
+int lock_policy_rwsem_write(int cpu);
+void unlock_policy_rwsem_write(int cpu);
 
 /*********************************************************************
  *                      CPUFREQ DRIVER INTERFACE                     *
diff --git a/include/linux/csdio.h b/include/linux/csdio.h
new file mode 100644
index 0000000..260c49d
--- /dev/null
+++ b/include/linux/csdio.h
@@ -0,0 +1,37 @@
+#ifndef CSDIO_H
+#define CSDIO_H
+
+#include <linux/ioctl.h>
+
+#define CSDIO_IOC_MAGIC  'm'
+
+#define CSDIO_IOC_ENABLE_HIGHSPEED_MODE      _IO(CSDIO_IOC_MAGIC, 0)
+#define CSDIO_IOC_SET_DATA_TRANSFER_CLOCKS   _IO(CSDIO_IOC_MAGIC, 1)
+#define CSDIO_IOC_SET_OP_CODE                _IO(CSDIO_IOC_MAGIC, 2)
+#define CSDIO_IOC_FUNCTION_SET_BLOCK_SIZE    _IO(CSDIO_IOC_MAGIC, 3)
+#define CSDIO_IOC_SET_BLOCK_MODE             _IO(CSDIO_IOC_MAGIC, 4)
+#define CSDIO_IOC_CONNECT_ISR                _IO(CSDIO_IOC_MAGIC, 5)
+#define CSDIO_IOC_DISCONNECT_ISR             _IO(CSDIO_IOC_MAGIC, 6)
+#define CSDIO_IOC_CMD52                      _IO(CSDIO_IOC_MAGIC, 7)
+#define CSDIO_IOC_CMD53                      _IO(CSDIO_IOC_MAGIC, 8)
+#define CSDIO_IOC_ENABLE_ISR                 _IO(CSDIO_IOC_MAGIC, 9)
+#define CSDIO_IOC_DISABLE_ISR                _IO(CSDIO_IOC_MAGIC, 10)
+#define CSDIO_IOC_SET_VDD                    _IO(CSDIO_IOC_MAGIC, 11)
+#define CSDIO_IOC_GET_VDD                    _IO(CSDIO_IOC_MAGIC, 12)
+
+#define CSDIO_IOC_MAXNR   12
+
+struct csdio_cmd53_ctrl_t {
+	uint32_t    m_block_mode;   /* data tran. byte(0)/block(1) mode */
+	uint32_t    m_op_code;      /* address auto increment flag */
+	uint32_t    m_address;
+} __attribute__ ((packed));
+
+struct csdio_cmd52_ctrl_t {
+	uint32_t    m_write;
+	uint32_t    m_address;
+	uint32_t    m_data;
+	uint32_t    m_ret;
+} __attribute__ ((packed));
+
+#endif
diff --git a/include/linux/cyttsp.h b/include/linux/cyttsp.h
new file mode 100644
index 0000000..0644f1a
--- /dev/null
+++ b/include/linux/cyttsp.h
@@ -0,0 +1,679 @@
+/* Header file for:
+ * Cypress TrueTouch(TM) Standard Product touchscreen drivers.
+ * include/linux/cyttsp.h
+ *
+ * Copyright (C) 2009, 2010 Cypress Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, and only version 2, as published by the
+ * Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Cypress reserves the right to make changes without further notice
+ * to the materials described herein. Cypress does not assume any
+ * liability arising out of the application described herein.
+ *
+ * Contact Cypress Semiconductor at www.cypress.com
+ *
+ */
+
+
+#ifndef __CYTTSP_H__
+#define __CYTTSP_H__
+
+#include <linux/input.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+
+#include <asm/mach-types.h>
+
+#define CYPRESS_TTSP_NAME	"cyttsp"
+#define CY_I2C_NAME		"cyttsp-i2c"
+#define CY_SPI_NAME		"cyttsp-spi"
+
+#ifdef CY_DECLARE_GLOBALS
+	uint32_t cyttsp_tsdebug;
+	module_param_named(tsdebug, cyttsp_tsdebug, uint, 0664);
+	uint32_t cyttsp_tsxdebug;
+	module_param_named(tsxdebug, cyttsp_tsxdebug, uint, 0664);
+
+	uint32_t cyttsp_disable_touch;
+	module_param_named(disable_touch, cyttsp_disable_touch, uint, 0664);
+#else
+	extern uint32_t cyttsp_tsdebug;
+	extern uint32_t cyttsp_tsxdebug;
+	extern uint32_t cyttsp_disable_touch;
+#endif
+
+
+
+/******************************************************************************
+ * Global Control, Used to control the behavior of the driver
+ */
+
+/* defines for Gen2 (Txx2xx); Gen3 (Txx3xx)
+ * use these defines to set cyttsp_platform_data.gen in board config file
+ */
+#define CY_GEN2		2
+#define CY_GEN3		3
+
+/* define for using I2C driver
+ */
+#define CY_USE_I2C_DRIVER
+
+/* defines for using SPI driver */
+/*
+#define CY_USE_SPI_DRIVER
+ */
+#define CY_SPI_DFLT_SPEED_HZ		1000000
+#define CY_SPI_MAX_SPEED_HZ		4000000
+#define CY_SPI_SPEED_HZ			CY_SPI_DFLT_SPEED_HZ
+#define CY_SPI_BITS_PER_WORD		8
+#define CY_SPI_DAV			139	/* set correct gpio id */
+#define CY_SPI_BUFSIZE			512
+
+/* Voltage and Current ratings */
+#define CY_TMA300_VTG_MAX_UV		5500000
+#define CY_TMA300_VTG_MIN_UV		1710000
+#define CY_TMA300_CURR_24HZ_UA		17500
+#define CY_I2C_VTG_MAX_UV		1800000
+#define CY_I2C_VTG_MIN_UV		1800000
+#define CY_I2C_CURR_UA			9630
+
+
+/* define for inclusion of TTSP App Update Load File
+ * use this define if update to the TTSP Device is desired
+ */
+/*
+#define CY_INCLUDE_LOAD_FILE
+*/
+
+/* define if force new load file for bootloader load */
+/*
+#define CY_FORCE_FW_UPDATE
+*/
+
+/* undef for production use */
+/*
+#define CY_USE_DEBUG
+*/
+
+/* undef for irq use; use this define in the board configuration file */
+/*
+#define CY_USE_TIMER
+ */
+
+/* undef to allow use of extra debug capability */
+/*
+#define CY_ALLOW_EXTRA_DEBUG
+*/
+
+/* undef to remove additional debug prints */
+/*
+#define CY_USE_EXTRA_DEBUG
+*/
+
+/* undef to remove additional debug prints */
+/*
+#define CY_USE_EXTRA_DEBUG1
+ */
+
+/* undef to use operational touch timer jiffies; else use test jiffies */
+/*
+ */
+#define CY_USE_TIMER_DEBUG
+
+/* define to use canned test data */
+/*
+#define CY_USE_TEST_DATA
+ */
+
+/* define to activate power management */
+/*
+#define CY_USE_LOW_POWER
+ */
+
+/* define if wake on i2c addr is activated */
+/*
+#define CY_USE_DEEP_SLEEP
+ */
+
+/* define if gesture signaling is used
+ * and which gesture groups to use
+ */
+/*
+#define CY_USE_GEST
+#define CY_USE_GEST_GRP1
+#define CY_USE_GEST_GRP2
+#define CY_USE_GEST_GRP3
+#define CY_USE_GEST_GRP4
+ */
+/* Active distance in pixels for a gesture to be reported
+ * if set to 0, then all gesture movements are reported
+ */
+#define CY_ACT_DIST_DFLT	8
+#define CY_ACT_DIST			CY_ACT_DIST_DFLT
+
+/* define if MT signals are desired */
+/*
+*/
+#define CY_USE_MT_SIGNALS
+
+/* define if MT tracking id signals are used */
+/*
+#define CY_USE_MT_TRACK_ID
+ */
+
+/* define if ST signals are required */
+/*
+*/
+#define CY_USE_ST_SIGNALS
+
+/* define to send handshake to device */
+/*
+*/
+#define CY_USE_HNDSHK
+
+/* define if log all raw motion signals to a sysfs file */
+/*
+#define CY_LOG_TO_FILE
+*/
+
+
+/* End of the Global Control section
+ ******************************************************************************
+ */
+#define CY_DIFF(m, n)		((m) != (n))
+
+#ifdef CY_LOG_TO_FILE
+	#define cyttsp_openlog()	/* use sysfs */
+#else
+	#define cyttsp_openlog()
+#endif /* CY_LOG_TO_FILE */
+
+/* see kernel.h for pr_xxx def'ns */
+#define cyttsp_info(f, a...)		pr_info("%s:" f,  __func__ , ## a)
+#define cyttsp_error(f, a...)		pr_err("%s:" f,  __func__ , ## a)
+#define cyttsp_alert(f, a...)		pr_alert("%s:" f,  __func__ , ## a)
+
+#ifdef CY_USE_DEBUG
+	#define cyttsp_debug(f, a...)	pr_alert("%s:" f,  __func__ , ## a)
+#else
+	#define cyttsp_debug(f, a...)	{if (cyttsp_tsdebug) \
+					pr_alert("%s:" f,  __func__ , ## a); }
+#endif /* CY_USE_DEBUG */
+
+#ifdef CY_ALLOW_EXTRA_DEBUG
+#ifdef CY_USE_EXTRA_DEBUG
+	#define cyttsp_xdebug(f, a...)	pr_alert("%s:" f,  __func__ , ## a)
+#else
+	#define cyttsp_xdebug(f, a...)	{if (cyttsp_tsxdebug) \
+					pr_alert("%s:" f,  __func__ , ## a); }
+#endif /* CY_USE_EXTRA_DEBUG */
+
+#ifdef CY_USE_EXTRA_DEBUG1
+	#define cyttsp_xdebug1(f, a...)	pr_alert("%s:" f,  __func__ , ## a)
+#else
+	#define cyttsp_xdebug1(f, a...)
+#endif /* CY_USE_EXTRA_DEBUG1 */
+#else
+	#define cyttsp_xdebug(f, a...)
+	#define cyttsp_xdebug1(f, a...)
+#endif /* CY_ALLOW_EXTRA_DEBUG */
+
+#ifdef CY_USE_TIMER_DEBUG
+	#define	TOUCHSCREEN_TIMEOUT	(msecs_to_jiffies(1000))
+#else
+	#define	TOUCHSCREEN_TIMEOUT	(msecs_to_jiffies(28))
+#endif
+
+/* reduce extra signals in MT only build
+ * be careful not to lose backward compatibility for pre-MT apps
+ */
+#ifdef CY_USE_ST_SIGNALS
+	#define CY_USE_ST	1
+#else
+	#define CY_USE_ST	0
+#endif /* CY_USE_ST_SIGNALS */
+
+/* rely on kernel input.h to define Multi-Touch capability */
+/* if input.h defines the Multi-Touch signals, then use MT */
+#if defined(ABS_MT_TOUCH_MAJOR) && defined(CY_USE_MT_SIGNALS)
+	#define CY_USE_MT	1
+	#define CY_MT_SYNC(input)	input_mt_sync(input)
+#else
+	#define CY_USE_MT	0
+	#define CY_MT_SYNC(input)
+	/* the following includes are provided to ensure a compile;
+	 * the code that compiles with these defines will not be executed if
+	 * the CY_USE_MT is properly used in the platform structure init
+	 */
+	#ifndef ABS_MT_TOUCH_MAJOR
+	#define ABS_MT_TOUCH_MAJOR	0x30	/* touching ellipse */
+	#define ABS_MT_TOUCH_MINOR	0x31	/* (omit if circular) */
+	#define ABS_MT_WIDTH_MAJOR	0x32	/* approaching ellipse */
+	#define ABS_MT_WIDTH_MINOR	0x33	/* (omit if circular) */
+	#define ABS_MT_ORIENTATION	0x34	/* Ellipse orientation */
+	#define ABS_MT_POSITION_X	0x35	/* Center X ellipse position */
+	#define ABS_MT_POSITION_Y	0x36	/* Center Y ellipse position */
+	#define ABS_MT_TOOL_TYPE	0x37	/* Type of touching device */
+	#define ABS_MT_BLOB_ID		0x38	/* Group set of pkts as blob */
+	#endif /* ABS_MT_TOUCH_MAJOR */
+#endif /* ABS_MT_TOUCH_MAJOR and CY_USE_MT_SIGNALS */
+#if defined(ABS_MT_TRACKING_ID)  && defined(CY_USE_MT_TRACK_ID)
+	#define CY_USE_TRACKING_ID	1
+#else
+	#define CY_USE_TRACKING_ID	0
+/* define only if not defined already by system;
+ * value based on linux kernel 2.6.30.10
+ */
+#ifndef ABS_MT_TRACKING_ID
+	#define ABS_MT_TRACKING_ID	(ABS_MT_BLOB_ID+1)
+#endif
+#endif /* ABS_MT_TRACKING_ID */
+
+#ifdef CY_USE_DEEP_SLEEP
+	#define CY_USE_DEEP_SLEEP_SEL	0x80
+#else
+	#define CY_USE_DEEP_SLEEP_SEL	0x00
+#endif
+#ifdef CY_USE_LOW_POWER
+	#define CY_USE_SLEEP	(CY_USE_DEEP_SLEEP_SEL | 0x01)
+#else
+	#define CY_USE_SLEEP	0x00
+#endif /* CY_USE_LOW_POWER */
+
+#ifdef CY_USE_TEST_DATA
+	#define cyttsp_testdat(ray1, ray2, sizeofray) \
+		{ \
+			int i; \
+			u8 *up1 = (u8 *)ray1; \
+			u8 *up2 = (u8 *)ray2; \
+			for (i = 0; i < sizeofray; i++) { \
+				up1[i] = up2[i]; \
+			} \
+		}
+#else
+	#define cyttsp_testdat(xy, test_xy, sizeofray)
+#endif /* CY_USE_TEST_DATA */
+
+/* helper macros */
+#define GET_NUM_TOUCHES(x)		((x) & 0x0F)
+#define GET_TOUCH1_ID(x)		(((x) & 0xF0) >> 4)
+#define GET_TOUCH2_ID(x)		((x) & 0x0F)
+#define GET_TOUCH3_ID(x)		(((x) & 0xF0) >> 4)
+#define GET_TOUCH4_ID(x)		((x) & 0x0F)
+#define IS_LARGE_AREA(x)		(((x) & 0x10) >> 4)
+#define FLIP_DATA_FLAG			0x01
+#define REVERSE_X_FLAG			0x02
+#define REVERSE_Y_FLAG			0x04
+#define FLIP_DATA(flags)		((flags) & FLIP_DATA_FLAG)
+#define REVERSE_X(flags)		((flags) & REVERSE_X_FLAG)
+#define REVERSE_Y(flags)		((flags) & REVERSE_Y_FLAG)
+#define FLIP_XY(x, y)			{ \
+						u16 tmp; \
+						tmp = (x); \
+						(x) = (y); \
+						(y) = tmp; \
+					}
+#define INVERT_X(x, xmax)		((xmax) - (x))
+#define INVERT_Y(y, maxy)		((maxy) - (y))
+#define SET_HSTMODE(reg, mode)		((reg) & (mode))
+#define GET_HSTMODE(reg)		((reg & 0x70) >> 4)
+#define GET_BOOTLOADERMODE(reg)		((reg & 0x10) >> 4)
+
+/* constant definitions */
+/* maximum number of concurrent ST track IDs */
+#define CY_NUM_ST_TCH_ID		2
+
+/* maximum number of concurrent MT track IDs */
+#define CY_NUM_MT_TCH_ID		4
+
+/* maximum number of track IDs */
+#define CY_NUM_TRK_ID			16
+
+#define CY_NTCH				0	/* no touch (lift off) */
+#define CY_TCH				1	/* active touch (touchdown) */
+#define CY_ST_FNGR1_IDX			0
+#define CY_ST_FNGR2_IDX			1
+#define CY_MT_TCH1_IDX			0
+#define CY_MT_TCH2_IDX			1
+#define CY_MT_TCH3_IDX			2
+#define CY_MT_TCH4_IDX			3
+#define CY_XPOS				0
+#define CY_YPOS				1
+#define CY_IGNR_TCH			(-1)
+#define CY_SMALL_TOOL_WIDTH		10
+#define CY_LARGE_TOOL_WIDTH		255
+#define CY_REG_BASE			0x00
+#define CY_REG_GEST_SET			0x1E
+#define CY_REG_ACT_INTRVL		0x1D
+#define CY_REG_TCH_TMOUT		(CY_REG_ACT_INTRVL+1)
+#define CY_REG_LP_INTRVL		(CY_REG_TCH_TMOUT+1)
+#define CY_SOFT_RESET			((1 << 0))
+#define CY_DEEP_SLEEP			((1 << 1))
+#define CY_LOW_POWER			((1 << 2))
+#define CY_MAXZ				255
+#define CY_OK				0
+#define CY_INIT				1
+#define	CY_DLY_DFLT			10	/* ms */
+#define CY_DLY_SYSINFO			20	/* ms */
+#define CY_DLY_BL			300
+#define CY_DLY_DNLOAD			100	/* ms */
+#define CY_NUM_RETRY			4	/* max num touch data read */
+
+/* handshake bit in the hst_mode reg */
+#define CY_HNDSHK_BIT			0x80
+#ifdef CY_USE_HNDSHK
+	#define CY_SEND_HNDSHK		1
+#else
+	#define CY_SEND_HNDSHK		0
+#endif
+
+/* Bootloader File 0 offset */
+#define CY_BL_FILE0			0x00
+
+/* Bootloader command directive */
+#define CY_BL_CMD			0xFF
+
+/* Bootloader Initiate Bootload */
+#define CY_BL_INIT_LOAD			0x38
+
+/* Bootloader Write a Block */
+#define CY_BL_WRITE_BLK			0x39
+
+/* Bootloader Terminate Bootload */
+#define CY_BL_TERMINATE			0x3B
+
+/* Bootloader Exit and Verify Checksum command */
+#define CY_BL_EXIT			0xA5
+
+/* Bootloader default keys */
+#define CY_BL_KEY0			0x00
+#define CY_BL_KEY1			0x01
+#define CY_BL_KEY2			0x02
+#define CY_BL_KEY3			0x03
+#define CY_BL_KEY4			0x04
+#define CY_BL_KEY5			0x05
+#define CY_BL_KEY6			0x06
+#define CY_BL_KEY7			0x07
+
+/* Active Power state scanning/processing refresh interval */
+#define CY_ACT_INTRVL_DFLT		0x00
+
+/* touch timeout for the Active power */
+#define CY_TCH_TMOUT_DFLT		0xFF
+
+/* Low Power state scanning/processing refresh interval */
+#define CY_LP_INTRVL_DFLT		0x0A
+
+#define CY_IDLE_STATE		0
+#define CY_ACTIVE_STATE		1
+#define CY_LOW_PWR_STATE		2
+#define CY_SLEEP_STATE		3
+
+/* device mode bits */
+#define CY_OP_MODE		0x00
+#define CY_SYSINFO_MODE		0x10
+
+/* power mode select bits */
+#define CY_SOFT_RESET_MODE		0x01	/* return to Bootloader mode */
+#define CY_DEEP_SLEEP_MODE		0x02
+#define CY_LOW_PWR_MODE		0x04
+
+#define CY_NUM_KEY			8
+
+#ifdef CY_USE_GEST
+	#define CY_USE_GESTURES	1
+#else
+	#define CY_USE_GESTURES	0
+#endif /* CY_USE_GESTURE_SIGNALS */
+
+#ifdef CY_USE_GEST_GRP1
+	#define CY_GEST_GRP1	0x10
+#else
+	#define CY_GEST_GRP1	0x00
+#endif	/* CY_USE_GEST_GRP1 */
+#ifdef CY_USE_GEST_GRP2
+	#define CY_GEST_GRP2	0x20
+#else
+	#define CY_GEST_GRP2	0x00
+#endif	/* CY_USE_GEST_GRP2 */
+#ifdef CY_USE_GEST_GRP3
+	#define CY_GEST_GRP3	0x40
+#else
+	#define CY_GEST_GRP3	0x00
+#endif	/* CY_USE_GEST_GRP3 */
+#ifdef CY_USE_GEST_GRP4
+	#define CY_GEST_GRP4	0x80
+#else
+	#define CY_GEST_GRP4	0x00
+#endif	/* CY_USE_GEST_GRP4 */
+
+struct cyttsp_regulator {
+	const char *name;
+	u32	min_uV;
+	u32	max_uV;
+	u32	load_uA;
+};
+
+struct cyttsp_platform_data {
+	u32 panel_maxx;
+	u32 panel_maxy;
+	u32 disp_resx;
+	u32 disp_resy;
+	u32 disp_minx;
+	u32 disp_miny;
+	u32 disp_maxx;
+	u32 disp_maxy;
+	u8 correct_fw_ver;
+	u32 flags;
+	u8 gen;
+	u8 use_st;
+	u8 use_mt;
+	u8 use_hndshk;
+	u8 use_trk_id;
+	u8 use_sleep;
+	u8 use_gestures;
+	u8 gest_set;
+	u8 act_intrvl;
+	u8 tch_tmout;
+	u8 lp_intrvl;
+	u8 power_state;
+	bool wakeup;
+	int sleep_gpio;
+	int resout_gpio;
+	int irq_gpio;
+	struct cyttsp_regulator *regulator_info;
+	u8 num_regulators;
+	const char *fw_fname;
+#ifdef CY_USE_I2C_DRIVER
+	s32 (*init)(struct i2c_client *client);
+	s32 (*resume)(struct i2c_client *client);
+#endif
+#ifdef CY_USE_SPI_DRIVER
+	s32 (*init)(struct spi_device *spi);
+	s32 (*resume)(struct spi_device *spi);
+#endif
+};
+
+/* TrueTouch Standard Product Gen3 (Txx3xx) interface definition */
+struct cyttsp_gen3_xydata_t {
+	u8 hst_mode;
+	u8 tt_mode;
+	u8 tt_stat;
+	u16 x1 __attribute__ ((packed));
+	u16 y1 __attribute__ ((packed));
+	u8 z1;
+	u8 touch12_id;
+	u16 x2 __attribute__ ((packed));
+	u16 y2 __attribute__ ((packed));
+	u8 z2;
+	u8 gest_cnt;
+	u8 gest_id;
+	u16 x3 __attribute__ ((packed));
+	u16 y3 __attribute__ ((packed));
+	u8 z3;
+	u8 touch34_id;
+	u16 x4 __attribute__ ((packed));
+	u16 y4 __attribute__ ((packed));
+	u8 z4;
+	u8 tt_undef[3];
+	u8 gest_set;
+	u8 tt_reserved;
+};
+
+/* TrueTouch Standard Product Gen2 (Txx2xx) interface definition */
+#define CY_GEN2_NOTOUCH		0x03	/* Both touches removed */
+#define CY_GEN2_GHOST		0x02	/* ghost */
+#define CY_GEN2_2TOUCH		0x03	/* 2 touch; no ghost */
+#define CY_GEN2_1TOUCH		0x01	/* 1 touch only */
+#define CY_GEN2_TOUCH2		0x01	/* 1st touch removed;
+						 * 2nd touch remains */
+struct cyttsp_gen2_xydata_t {
+	u8 hst_mode;
+	u8 tt_mode;
+	u8 tt_stat;
+	u16 x1 __attribute__ ((packed));
+	u16 y1 __attribute__ ((packed));
+	u8 z1;
+	u8 evnt_idx;
+	u16 x2 __attribute__ ((packed));
+	u16 y2 __attribute__ ((packed));
+	u8 tt_undef1;
+	u8 gest_cnt;
+	u8 gest_id;
+	u8 tt_undef[14];
+	u8 gest_set;
+	u8 tt_reserved;
+};
+
+/* TTSP System Information interface definition */
+struct cyttsp_sysinfo_data_t {
+	u8 hst_mode;
+	u8 mfg_cmd;
+	u8 mfg_stat;
+	u8 cid[3];
+	u8 tt_undef1;
+	u8 uid[8];
+	u8 bl_verh;
+	u8 bl_verl;
+	u8 tts_verh;
+	u8 tts_verl;
+	u8 app_idh;
+	u8 app_idl;
+	u8 app_verh;
+	u8 app_verl;
+	u8 tt_undef[6];
+	u8 act_intrvl;
+	u8 tch_tmout;
+	u8 lp_intrvl;
+};
+
+/* TTSP Bootloader Register Map interface definition */
+#define CY_BL_CHKSUM_OK		0x01
+struct cyttsp_bootloader_data_t {
+	u8 bl_file;
+	u8 bl_status;
+	u8 bl_error;
+	u8 blver_hi;
+	u8 blver_lo;
+	u8 bld_blver_hi;
+	u8 bld_blver_lo;
+	u8 ttspver_hi;
+	u8 ttspver_lo;
+	u8 appid_hi;
+	u8 appid_lo;
+	u8 appver_hi;
+	u8 appver_lo;
+	u8 cid_0;
+	u8 cid_1;
+	u8 cid_2;
+};
+
+#define cyttsp_wake_data_t		cyttsp_gen3_xydata_t
+#ifdef CY_DECLARE_GLOBALS
+	#ifdef CY_INCLUDE_LOAD_FILE
+		/* this file declares:
+		 * firmware download block array (cyttsp_fw[]),
+		 * the number of command block records (cyttsp_fw_records),
+		 * and the version variables
+		 */
+		#include "cyttsp_fw.h"		/* imports cyttsp_fw[] array */
+		#define cyttsp_app_load()	1
+		#ifdef CY_FORCE_FW_UPDATE
+			#define cyttsp_force_fw_load()	1
+		#else
+			#define cyttsp_force_fw_load()	0
+		#endif
+
+	#else
+		/* the following declarations are to allow
+		 * some debugging capability
+		 */
+		unsigned char cyttsp_fw_tts_verh = 0x00;
+		unsigned char cyttsp_fw_tts_verl = 0x01;
+		unsigned char cyttsp_fw_app_idh = 0x02;
+		unsigned char cyttsp_fw_app_idl = 0x03;
+		unsigned char cyttsp_fw_app_verh = 0x04;
+		unsigned char cyttsp_fw_app_verl = 0x05;
+		unsigned char cyttsp_fw_cid_0 = 0x06;
+		unsigned char cyttsp_fw_cid_1 = 0x07;
+		unsigned char cyttsp_fw_cid_2 = 0x08;
+		#define cyttsp_app_load()	0
+		#define cyttsp_force_fw_load()	0
+	#endif
+	#define cyttsp_tts_verh()	cyttsp_fw_tts_verh
+	#define cyttsp_tts_verl()	cyttsp_fw_tts_verl
+	#define cyttsp_app_idh()	cyttsp_fw_app_idh
+	#define cyttsp_app_idl()	cyttsp_fw_app_idl
+	#define cyttsp_app_verh()	cyttsp_fw_app_verh
+	#define cyttsp_app_verl()	cyttsp_fw_app_verl
+	#define cyttsp_cid_0()		cyttsp_fw_cid_0
+	#define cyttsp_cid_1()		cyttsp_fw_cid_1
+	#define cyttsp_cid_2()		cyttsp_fw_cid_2
+	#ifdef CY_USE_TEST_DATA
+		static struct cyttsp_gen2_xydata_t tt_gen2_testray[] = {
+		{0x00}, {0x00}, {0x04},
+		{0x4000}, {0x8000}, {0x80},
+		{0x03},
+		{0x2000}, {0x1000}, {0x00},
+		{0x00},
+		{0x00},
+		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+		{0x00},
+		{0x00}
+		};
+
+		static struct cyttsp_gen3_xydata_t tt_gen3_testray[] = {
+		{0x00}, {0x00}, {0x04},
+		{0x4000}, {0x8000}, {0x80},
+		{0x12},
+		{0x2000}, {0x1000}, {0xA0},
+		{0x00}, {0x00},
+		{0x8000}, {0x4000}, {0xB0},
+		{0x34},
+		{0x4000}, {0x1000}, {0xC0},
+		{0x00, 0x00, 0x00},
+		{0x00},
+		{0x00}
+		};
+	#endif /* CY_USE_TEST_DATA */
+
+#else
+		extern u8 g_appload_ray[];
+#endif
+
+#endif /* __CYTTSP_H__ */
diff --git a/include/linux/debugobjects.h b/include/linux/debugobjects.h
index 65970b8..0e5f578 100644
--- a/include/linux/debugobjects.h
+++ b/include/linux/debugobjects.h
@@ -46,6 +46,8 @@
  *			fails
  * @fixup_free:		fixup function, which is called when the free check
  *			fails
+ * @fixup_assert_init:  fixup function, which is called when the assert_init
+ *			check fails
  */
 struct debug_obj_descr {
 	const char		*name;
@@ -54,6 +56,7 @@
 	int (*fixup_activate)	(void *addr, enum debug_obj_state state);
 	int (*fixup_destroy)	(void *addr, enum debug_obj_state state);
 	int (*fixup_free)	(void *addr, enum debug_obj_state state);
+	int (*fixup_assert_init)(void *addr, enum debug_obj_state state);
 };
 
 #ifdef CONFIG_DEBUG_OBJECTS
@@ -64,6 +67,7 @@
 extern void debug_object_deactivate(void *addr, struct debug_obj_descr *descr);
 extern void debug_object_destroy   (void *addr, struct debug_obj_descr *descr);
 extern void debug_object_free      (void *addr, struct debug_obj_descr *descr);
+extern void debug_object_assert_init(void *addr, struct debug_obj_descr *descr);
 
 /*
  * Active state:
@@ -89,6 +93,8 @@
 debug_object_destroy   (void *addr, struct debug_obj_descr *descr) { }
 static inline void
 debug_object_free      (void *addr, struct debug_obj_descr *descr) { }
+static inline void
+debug_object_assert_init(void *addr, struct debug_obj_descr *descr) { }
 
 static inline void debug_objects_early_init(void) { }
 static inline void debug_objects_mem_init(void) { }
diff --git a/include/linux/delay.h b/include/linux/delay.h
index a6ecb34..0e303d1 100644
--- a/include/linux/delay.h
+++ b/include/linux/delay.h
@@ -47,6 +47,11 @@
 unsigned long msleep_interruptible(unsigned int msecs);
 void usleep_range(unsigned long min, unsigned long max);
 
+static inline void usleep(unsigned long usecs)
+{
+	usleep_range(usecs, usecs);
+}
+
 static inline void ssleep(unsigned int seconds)
 {
 	msleep(seconds * 1000);
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
new file mode 100644
index 0000000..22270de
--- /dev/null
+++ b/include/linux/diagchar.h
@@ -0,0 +1,589 @@
+/* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DIAGCHAR_SHARED
+#define DIAGCHAR_SHARED
+
+#define MSG_MASKS_TYPE			1
+#define LOG_MASKS_TYPE			2
+#define EVENT_MASKS_TYPE		4
+#define PKT_TYPE			8
+#define DEINIT_TYPE			16
+#define MEMORY_DEVICE_LOG_TYPE		32
+#define USB_MODE			1
+#define MEMORY_DEVICE_MODE		2
+#define NO_LOGGING_MODE			3
+
+/* different values that go in for diag_data_type */
+#define DATA_TYPE_EVENT         	0
+#define DATA_TYPE_F3            	1
+#define DATA_TYPE_LOG           	2
+#define DATA_TYPE_RESPONSE      	3
+
+/* Different IOCTL values */
+#define DIAG_IOCTL_COMMAND_REG  	0
+#define DIAG_IOCTL_SWITCH_LOGGING	7
+#define DIAG_IOCTL_GET_DELAYED_RSP_ID 	8
+#define DIAG_IOCTL_LSM_DEINIT		9
+
+/* Machine ID and corresponding PC Tools IDs */
+#define APQ8060_MACHINE_ID	86
+#define AO8960_MACHINE_ID	87
+#define MSM8660_MACHINE_ID	71
+#define APQ8060_TOOLS_ID	4062
+#define AO8960_TOOLS_ID		4064
+
+#define MSG_MASK_0			(0x00000001)
+#define MSG_MASK_1			(0x00000002)
+#define MSG_MASK_2			(0x00000004)
+#define MSG_MASK_3			(0x00000008)
+#define MSG_MASK_4			(0x00000010)
+#define MSG_MASK_5			(0x00000020)
+#define MSG_MASK_6			(0x00000040)
+#define MSG_MASK_7			(0x00000080)
+#define MSG_MASK_8			(0x00000100)
+#define MSG_MASK_9			(0x00000200)
+#define MSG_MASK_10			(0x00000400)
+#define MSG_MASK_11			(0x00000800)
+#define MSG_MASK_12			(0x00001000)
+#define MSG_MASK_13			(0x00002000)
+#define MSG_MASK_14			(0x00004000)
+#define MSG_MASK_15			(0x00008000)
+#define MSG_MASK_16			(0x00010000)
+#define MSG_MASK_17			(0x00020000)
+#define MSG_MASK_18			(0x00040000)
+#define MSG_MASK_19			(0x00080000)
+#define MSG_MASK_20			(0x00100000)
+#define MSG_MASK_21			(0x00200000)
+#define MSG_MASK_22			(0x00400000)
+#define MSG_MASK_23			(0x00800000)
+#define MSG_MASK_24			(0x01000000)
+#define MSG_MASK_25			(0x02000000)
+#define MSG_MASK_26			(0x04000000)
+#define MSG_MASK_27			(0x08000000)
+#define MSG_MASK_28			(0x10000000)
+#define MSG_MASK_29			(0x20000000)
+#define MSG_MASK_30			(0x40000000)
+#define MSG_MASK_31			(0x80000000)
+
+/*  These masks are to be used for support of all legacy messages in the sw.
+The user does not need to remember the names as they will be embedded in
+the appropriate macros. */
+#define MSG_LEGACY_LOW			MSG_MASK_0
+#define MSG_LEGACY_MED			MSG_MASK_1
+#define MSG_LEGACY_HIGH			MSG_MASK_2
+#define MSG_LEGACY_ERROR		MSG_MASK_3
+#define MSG_LEGACY_FATAL		MSG_MASK_4
+
+/* Legacy Message Priorities */
+#define MSG_LVL_FATAL			(MSG_LEGACY_FATAL)
+#define MSG_LVL_ERROR			(MSG_LEGACY_ERROR | MSG_LVL_FATAL)
+#define MSG_LVL_HIGH			(MSG_LEGACY_HIGH | MSG_LVL_ERROR)
+#define MSG_LVL_MED			(MSG_LEGACY_MED | MSG_LVL_HIGH)
+#define MSG_LVL_LOW			(MSG_LEGACY_LOW | MSG_LVL_MED)
+
+#define MSG_LVL_NONE			0
+
+/* This needs to be modified manually now, when we add
+ a new RANGE of SSIDs to the msg_mask_tbl */
+#define MSG_MASK_TBL_CNT		19
+#define EVENT_LAST_ID			0x083F
+
+#define MSG_SSID_0			0
+#define MSG_SSID_0_LAST			68
+#define MSG_SSID_1			500
+#define MSG_SSID_1_LAST			506
+#define MSG_SSID_2			1000
+#define MSG_SSID_2_LAST			1007
+#define MSG_SSID_3			2000
+#define MSG_SSID_3_LAST			2008
+#define MSG_SSID_4			3000
+#define MSG_SSID_4_LAST			3012
+#define MSG_SSID_5			4000
+#define MSG_SSID_5_LAST			4010
+#define MSG_SSID_6			4500
+#define MSG_SSID_6_LAST			4526
+#define MSG_SSID_7			4600
+#define MSG_SSID_7_LAST			4611
+#define MSG_SSID_8			5000
+#define MSG_SSID_8_LAST			5024
+#define MSG_SSID_9			5500
+#define MSG_SSID_9_LAST			5514
+#define MSG_SSID_10			6000
+#define MSG_SSID_10_LAST		6050
+#define MSG_SSID_11			6500
+#define MSG_SSID_11_LAST		6521
+#define MSG_SSID_12			7000
+#define MSG_SSID_12_LAST		7003
+#define MSG_SSID_13			7100
+#define MSG_SSID_13_LAST		7111
+#define MSG_SSID_14			7200
+#define MSG_SSID_14_LAST		7201
+#define MSG_SSID_15			8000
+#define MSG_SSID_15_LAST		8000
+#define MSG_SSID_16			8500
+#define MSG_SSID_16_LAST		8523
+#define MSG_SSID_17			9000
+#define MSG_SSID_17_LAST		9008
+#define MSG_SSID_18			9500
+#define MSG_SSID_18_LAST		9509
+
+struct diagpkt_delay_params {
+	void *rsp_ptr;
+	int size;
+	int *num_bytes_ptr;
+};
+
+static const uint32_t msg_bld_masks_0[] = {
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_ERROR,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_HIGH,
+	MSG_LVL_ERROR,
+	MSG_LVL_LOW,
+	MSG_LVL_ERROR,
+	MSG_LVL_ERROR,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_LOW,
+	MSG_LVL_ERROR,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED|MSG_MASK_7 | \
+		MSG_MASK_8|MSG_MASK_9|MSG_MASK_10|MSG_MASK_11|MSG_MASK_12 | \
+		MSG_MASK_13|MSG_MASK_14|MSG_MASK_15|MSG_MASK_16 | \
+		MSG_MASK_17|MSG_MASK_18|MSG_MASK_19|MSG_MASK_20|MSG_MASK_21,
+	MSG_LVL_MED|MSG_MASK_5 | \
+		MSG_MASK_6|MSG_MASK_7|MSG_MASK_8|MSG_MASK_9|MSG_MASK_10| \
+		MSG_MASK_11|MSG_MASK_12|MSG_MASK_13|MSG_MASK_14| \
+		MSG_MASK_15|MSG_MASK_16|MSG_MASK_17,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED|MSG_MASK_5 | \
+		MSG_MASK_6|MSG_MASK_7|MSG_MASK_8,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_MED,
+	MSG_LVL_MED|MSG_MASK_5 | \
+		MSG_MASK_6|MSG_MASK_7|MSG_MASK_8|MSG_MASK_9|MSG_MASK_10| \
+		MSG_MASK_11|MSG_MASK_12|MSG_MASK_13|MSG_MASK_14|MSG_MASK_15| \
+		MSG_MASK_16|MSG_MASK_17|MSG_MASK_18|MSG_MASK_19|MSG_MASK_20| \
+		MSG_MASK_21|MSG_MASK_22|MSG_MASK_23|MSG_MASK_24|MSG_MASK_25,
+	MSG_LVL_MED|MSG_MASK_5 | \
+		MSG_MASK_6|MSG_MASK_7|MSG_MASK_8|MSG_MASK_9|MSG_MASK_10,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_HIGH,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW | MSG_MASK_5 | \
+		MSG_MASK_6 | MSG_MASK_7 | MSG_MASK_8,
+	MSG_LVL_LOW | MSG_MASK_5 | \
+		MSG_MASK_6,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_MED | MSG_MASK_5 | \
+		MSG_MASK_6|MSG_MASK_7|MSG_MASK_8|MSG_MASK_9|MSG_MASK_10| \
+		MSG_MASK_11|MSG_MASK_12|MSG_MASK_13|MSG_MASK_14|MSG_MASK_15 | \
+		MSG_MASK_16|MSG_MASK_17|MSG_MASK_18|MSG_MASK_19|MSG_MASK_20,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+};
+
+static const uint32_t msg_bld_masks_1[] = {
+	MSG_LVL_MED,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_LOW,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+};
+
+static const uint32_t msg_bld_masks_2[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED,
+	MSG_LVL_MED
+};
+
+static const uint32_t msg_bld_masks_3[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED
+};
+
+static const uint32_t msg_bld_masks_4[] = {
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH,
+	MSG_LVL_HIGH
+};
+
+static const uint32_t msg_bld_masks_5[] = {
+	MSG_LVL_HIGH,
+	MSG_LVL_MED,
+	MSG_LVL_HIGH,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED
+};
+
+static const uint32_t msg_bld_masks_6[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW
+};
+
+static const uint32_t msg_bld_masks_7[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+};
+
+static const uint32_t msg_bld_masks_8[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+};
+
+static const uint32_t msg_bld_masks_9[] = {
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+	MSG_LVL_MED|MSG_MASK_5,
+};
+
+static const uint32_t msg_bld_masks_10[] =  {
+	MSG_LVL_MED,
+	MSG_LVL_ERROR,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW|MSG_MASK_5 | \
+		MSG_MASK_6|MSG_MASK_7|MSG_MASK_8|MSG_MASK_9|MSG_MASK_10| \
+		MSG_MASK_11|MSG_MASK_12|MSG_MASK_13|MSG_MASK_14|MSG_MASK_15| \
+		MSG_MASK_16|MSG_MASK_17|MSG_MASK_18|MSG_MASK_19|MSG_MASK_20| \
+		MSG_MASK_21|MSG_MASK_22,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW,
+	MSG_LVL_MED,
+	MSG_LVL_HIGH,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW|MSG_MASK_5,
+	MSG_LVL_LOW|MSG_MASK_0 | MSG_MASK_1 | MSG_MASK_2 | \
+		MSG_MASK_3 | MSG_MASK_4 | MSG_MASK_5 | MSG_MASK_6,
+	MSG_LVL_HIGH,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+};
+
+static const uint32_t msg_bld_masks_11[] = {
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+};
+
+static const uint32_t msg_bld_masks_12[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+};
+
+static const uint32_t msg_bld_masks_13[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+};
+
+static const uint32_t msg_bld_masks_14[] = {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+};
+
+static const uint32_t msg_bld_masks_15[] = {
+	MSG_LVL_MED
+};
+
+static const uint32_t msg_bld_masks_16[] = {
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+};
+
+static const uint32_t msg_bld_masks_17[] =  {
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+	MSG_LVL_MED | MSG_MASK_6 | \
+		MSG_MASK_7 | MSG_MASK_8 | MSG_MASK_9,
+	MSG_LVL_MED | MSG_MASK_5 | \
+		MSG_MASK_6 | MSG_MASK_7 | MSG_MASK_8 | MSG_MASK_9 | \
+		MSG_MASK_10 | MSG_MASK_11 | MSG_MASK_12 | MSG_MASK_13 | \
+		MSG_MASK_14 | MSG_MASK_15 | MSG_MASK_16 | MSG_MASK_17,
+	MSG_LVL_MED,
+	MSG_LVL_MED | MSG_MASK_5 | \
+		MSG_MASK_6 | MSG_MASK_7 | MSG_MASK_8 | MSG_MASK_9 | \
+		MSG_MASK_10 | MSG_MASK_11 | MSG_MASK_12 | MSG_MASK_13 | \
+		MSG_MASK_14 | MSG_MASK_15 | MSG_MASK_16 | MSG_MASK_17 | \
+		MSG_MASK_18 | MSG_MASK_19 | MSG_MASK_20 | MSG_MASK_21 | \
+		MSG_MASK_22,
+	MSG_LVL_MED,
+	MSG_LVL_MED,
+};
+
+static const uint32_t msg_bld_masks_18[] = {
+	MSG_LVL_LOW,
+	MSG_LVL_LOW | MSG_MASK_8 | MSG_MASK_9 | MSG_MASK_10 | \
+		MSG_MASK_11|MSG_MASK_12|MSG_MASK_13|MSG_MASK_14|MSG_MASK_15 | \
+		MSG_MASK_16|MSG_MASK_17|MSG_MASK_18|MSG_MASK_19|MSG_MASK_20,
+	MSG_LVL_LOW | MSG_MASK_5 | MSG_MASK_6,
+	MSG_LVL_LOW | MSG_MASK_5,
+	MSG_LVL_LOW | MSG_MASK_5 | MSG_MASK_6,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW | MSG_MASK_5 | \
+		MSG_MASK_6 | MSG_MASK_7 | MSG_MASK_8 | MSG_MASK_9,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW,
+	MSG_LVL_LOW
+};
+
+/* LOG CODES */
+
+#define LOG_0	0x0
+#define LOG_1	0x1520
+#define LOG_2	0x0
+#define LOG_3	0x0
+#define LOG_4	0x4910
+#define LOG_5	0x5420
+#define LOG_6	0x0
+#define LOG_7	0x74FF
+#define LOG_8	0x0
+#define LOG_9	0x0
+#define LOG_10	0xA38A
+#define LOG_11	0xB201
+#define LOG_12	0x0
+#define LOG_13	0x0
+#define LOG_14	0x0
+#define LOG_15	0x0
+
+#define LOG_GET_ITEM_NUM(xx_code) (xx_code & 0x0FFF)
+
+#endif
diff --git a/include/linux/fsm_dfe_hh.h b/include/linux/fsm_dfe_hh.h
new file mode 100644
index 0000000..5f09f1e
--- /dev/null
+++ b/include/linux/fsm_dfe_hh.h
@@ -0,0 +1,85 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _FSM_DFE_HH_H_
+#define _FSM_DFE_HH_H_
+
+#include <linux/ioctl.h>
+
+/*
+ * Device interface
+ */
+
+#define DFE_HH_DEVICE_NAME		"dfe_hh"
+
+/*
+ * IOCTL interface
+ */
+
+enum {
+	DFE_IOCTL_COMMAND_CODE_WRITE,
+	DFE_IOCTL_COMMAND_CODE_WRITE_WITH_MASK,
+};
+
+struct dfe_write_register_param {
+	unsigned int offset;
+	unsigned int value;
+};
+
+struct dfe_write_register_mask_param {
+	unsigned int offset;
+	unsigned int value;
+	unsigned int mask;
+};
+
+struct dfe_read_write_array_param {
+	unsigned int offset;
+	unsigned int num; /* number of 16 bit registers */
+	unsigned int *pArray;
+};
+
+struct dfe_command_entry {
+	unsigned int code;
+	unsigned int offset;
+	unsigned int value;
+	unsigned int mask; /* DFE_IOCTL_COMMAND_CODE_WRITE_WITH_MASK only */
+};
+
+struct dfe_command_param {
+	unsigned int num;
+	struct dfe_command_entry *pEntry;
+};
+
+#define DFE_IOCTL_MAGIC				'h'
+#define DFE_IOCTL_IS_UMTS \
+	_IOC(_IOC_READ, DFE_IOCTL_MAGIC, 0x00, \
+		0)
+#define DFE_IOCTL_READ_REGISTER \
+	_IOC(_IOC_READ, DFE_IOCTL_MAGIC, 0x01, \
+		sizeof(unsigned int *))
+#define DFE_IOCTL_WRITE_REGISTER \
+	_IOC(_IOC_WRITE, DFE_IOCTL_MAGIC, 0x02, \
+		sizeof(struct dfe_write_register_param *))
+#define DFE_IOCTL_WRITE_REGISTER_WITH_MASK \
+	_IOC(_IOC_WRITE, DFE_IOCTL_MAGIC, 0x03, \
+		sizeof(struct dfe_write_register_mask_param *))
+#define DFE_IOCTL_READ_REGISTER_ARRAY \
+	_IOC(_IOC_READ, DFE_IOCTL_MAGIC, 0x04, \
+		sizeof(struct dfe_read_write_array_param *))
+#define DFE_IOCTL_WRITE_REGISTER_ARRAY \
+	_IOC(_IOC_WRITE, DFE_IOCTL_MAGIC, 0x05, \
+		sizeof(struct dfe_read_write_array_param *))
+#define DFE_IOCTL_COMMAND \
+	_IOC(_IOC_WRITE, DFE_IOCTL_MAGIC, 0x10, \
+		sizeof(struct dfe_command_param *))
+
+#endif /* _FSM_DFE_HH_H_ */
diff --git a/include/linux/fsm_rfic_ftr.h b/include/linux/fsm_rfic_ftr.h
new file mode 100644
index 0000000..5e8cd89
--- /dev/null
+++ b/include/linux/fsm_rfic_ftr.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _FSM_RFIC_FTR_H_
+#define _FSM_RFIC_FTR_H_
+
+#include <linux/ioctl.h>
+
+/*
+ * Device interface
+ */
+
+#define RFIC_FTR_DEVICE_NAME		"rfic_ftr"
+
+/*
+ * IOCTL interface
+ */
+
+/*
+    Macro to associate the "bus" and "address" pair when accessing the RFIC.
+    Using a 32 bit address, reserve the upper 8 bits for the bus value, and
+    the lower 24 bits for the address.
+ */
+#define RFIC_FTR_ADDR(bus, addr)	(((bus&0x03)<<24)|(addr&0xFFFFFF))
+#define RFIC_FTR_GET_ADDR(busAddr)	(busAddr&0xFFFFFF)
+#define RFIC_FTR_GET_BUS(busAddr)	((busAddr>>24)&0x03)
+
+struct rfic_write_register_param {
+	unsigned int rficAddr;
+	unsigned int value;
+};
+
+struct rfic_write_register_mask_param {
+	unsigned int rficAddr;
+	unsigned int value;
+	unsigned int mask;
+};
+
+struct rfic_grfc_param {
+	unsigned int grfcId;
+	unsigned int maskValue;
+	unsigned int ctrlValue;
+};
+
+#define RFIC_IOCTL_MAGIC				'f'
+#define RFIC_IOCTL_IS_UMTS \
+	_IOC(_IOC_READ, RFIC_IOCTL_MAGIC, 0x00, \
+		0)
+#define RFIC_IOCTL_READ_REGISTER \
+	_IOC(_IOC_READ, RFIC_IOCTL_MAGIC, 0x01, \
+		sizeof(unsigned int *))
+#define RFIC_IOCTL_WRITE_REGISTER \
+	_IOC(_IOC_WRITE, RFIC_IOCTL_MAGIC, 0x02, \
+		sizeof(struct rfic_write_register_param *))
+#define RFIC_IOCTL_WRITE_REGISTER_WITH_MASK \
+	_IOC(_IOC_WRITE, RFIC_IOCTL_MAGIC, 0x03, \
+		sizeof(struct rfic_write_register_mask_param *))
+#define RFIC_IOCTL_GET_GRFC \
+	_IOC(_IOC_WRITE, RFIC_IOCTL_MAGIC, 0x10, \
+		sizeof(struct rfic_grfc_param *))
+#define RFIC_IOCTL_SET_GRFC \
+	_IOC(_IOC_WRITE, RFIC_IOCTL_MAGIC, 0x11, \
+		sizeof(struct rfic_grfc_param *))
+
+#endif /* _FSM_RFIC_FTR_H_ */
diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h
index 5bbebda..3bc7dd7 100644
--- a/include/linux/genalloc.h
+++ b/include/linux/genalloc.h
@@ -8,31 +8,35 @@
  * Version 2.  See the file COPYING for more details.
  */
 
-
 #ifndef __GENALLOC_H__
 #define __GENALLOC_H__
-/*
- *  General purpose special memory pool descriptor.
- */
-struct gen_pool {
-	rwlock_t lock;
-	struct list_head chunks;	/* list of chunks in this pool */
-	int min_alloc_order;		/* minimum allocation order */
-};
 
-/*
- *  General purpose special memory pool chunk descriptor.
- */
-struct gen_pool_chunk {
-	spinlock_t lock;
-	struct list_head next_chunk;	/* next chunk in pool */
-	phys_addr_t phys_addr;		/* physical starting address of memory chunk */
-	unsigned long start_addr;	/* starting address of memory chunk */
-	unsigned long end_addr;		/* ending address of memory chunk */
-	unsigned long bits[0];		/* bitmap for allocating memory chunk */
-};
+struct gen_pool;
 
-extern struct gen_pool *gen_pool_create(int, int);
+struct gen_pool *__must_check gen_pool_create(unsigned order, int nid);
+
+void gen_pool_destroy(struct gen_pool *pool);
+
+unsigned long __must_check
+gen_pool_alloc_aligned(struct gen_pool *pool, size_t size,
+		       unsigned alignment_order);
+
+/**
+ * gen_pool_alloc() - allocate special memory from the pool
+ * @pool:	Pool to allocate from.
+ * @size:	Number of bytes to allocate from the pool.
+ *
+ * Allocate the requested number of bytes from the specified pool.
+ * Uses a first-fit algorithm.
+ */
+static inline unsigned long __must_check
+gen_pool_alloc(struct gen_pool *pool, size_t size)
+{
+	return gen_pool_alloc_aligned(pool, size, 0);
+}
+
+void gen_pool_free(struct gen_pool *pool, unsigned long addr, size_t size);
+
 extern phys_addr_t gen_pool_virt_to_phys(struct gen_pool *pool, unsigned long);
 extern int gen_pool_add_virt(struct gen_pool *, unsigned long, phys_addr_t,
 			     size_t, int);
@@ -48,12 +52,9 @@
  *
  * Returns 0 on success or a -ve errno on failure.
  */
-static inline int gen_pool_add(struct gen_pool *pool, unsigned long addr,
+static inline int __must_check gen_pool_add(struct gen_pool *pool, unsigned long addr,
 			       size_t size, int nid)
 {
 	return gen_pool_add_virt(pool, addr, -1, size, nid);
 }
-extern void gen_pool_destroy(struct gen_pool *);
-extern unsigned long gen_pool_alloc(struct gen_pool *, size_t);
-extern void gen_pool_free(struct gen_pool *, unsigned long, size_t);
 #endif /* __GENALLOC_H__ */
diff --git a/include/linux/gpio-pm8xxx-rpc.h b/include/linux/gpio-pm8xxx-rpc.h
new file mode 100644
index 0000000..5b6f097
--- /dev/null
+++ b/include/linux/gpio-pm8xxx-rpc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC8XXX gpio rpc driver header file
+ *
+ */
+
+#ifndef __GPIO_PM8XXX_RPC_H
+#define __GPIO_PM8XXX_RPC_H
+
+#define PM8XXX_GPIO_DEV_NAME	"pm8xxx-gpio-rpc"
+
+struct pm8xxx_gpio_rpc_platform_data {
+	int	ngpios;
+	int	gpio_base;
+};
+
+/* GPIO parameters */
+/* direction */
+#define	PM_GPIO_DIR_OUT			0x01
+#define	PM_GPIO_DIR_IN			0x02
+#define	PM_GPIO_DIR_BOTH		(PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
+
+#endif
diff --git a/include/linux/gpio_event.h b/include/linux/gpio_event.h
index 360b4dd..8c3f090 100644
--- a/include/linux/gpio_event.h
+++ b/include/linux/gpio_event.h
@@ -83,10 +83,10 @@
 	unsigned int ninputs;
 	unsigned int noutputs;
 	/* time to wait before reading inputs after driving each output */
-	ktime_t settle_time;
+	struct timespec settle_time;
 	/* time to wait before scanning the keypad a second time */
-	ktime_t debounce_delay;
-	ktime_t poll_time;
+	struct timespec debounce_delay;
+	struct timespec poll_time;
 	unsigned flags;
 };
 
diff --git a/include/linux/i2c/bq27520.h b/include/linux/i2c/bq27520.h
new file mode 100644
index 0000000..70c5a4c
--- /dev/null
+++ b/include/linux/i2c/bq27520.h
@@ -0,0 +1,26 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_BQ27520_H
+#define __LINUX_BQ27520_H
+struct bq27520_platform_data {
+	const char *name;
+	unsigned int soc_int;
+	unsigned int bi_tout;
+	unsigned int chip_en; /* CE */
+	const char *vreg_name; /* regulater used by bq27520 */
+	int vreg_value; /* its value */
+	int enable_dlog; /* if enable on-chip coulomb counter data logger */
+};
+
+#endif /* __LINUX_BQ27520_H */
diff --git a/include/linux/i2c/isa1200.h b/include/linux/i2c/isa1200.h
new file mode 100644
index 0000000..7d2e53f
--- /dev/null
+++ b/include/linux/i2c/isa1200.h
@@ -0,0 +1,46 @@
+/*
+ *  isa1200.h - ISA1200 Haptic Motor driver
+ *
+ *  Copyright (C) 2009 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_ISA1200_H
+#define __LINUX_ISA1200_H
+
+enum mode_control {
+	POWER_DOWN_MODE = 0,
+	PWM_INPUT_MODE,
+	PWM_GEN_MODE,
+	WAVE_GEN_MODE
+};
+
+union pwm_div_freq {
+	unsigned int pwm_div; /* PWM gen mode */
+	unsigned int pwm_freq; /* PWM input mode */
+};
+
+struct isa1200_platform_data {
+	const char *name;
+	unsigned int pwm_ch_id; /* pwm channel id */
+	unsigned int max_timeout;
+	unsigned int hap_en_gpio;
+	bool overdrive_high; /* high/low overdrive */
+	bool overdrive_en; /* enable/disable overdrive */
+	enum mode_control mode_ctrl; /* input/generation/wave */
+	union pwm_div_freq pwm_fd;
+	bool smart_en; /* smart mode enable/disable */
+	bool is_erm;
+	bool ext_clk_en;
+	unsigned int chip_en;
+	unsigned int duty;
+	int (*power_on)(int on);
+	int (*dev_setup)(bool on);
+};
+
+#endif /* __LINUX_ISA1200_H */
diff --git a/include/linux/i2c/isl9519.h b/include/linux/i2c/isl9519.h
new file mode 100644
index 0000000..8c98bf7
--- /dev/null
+++ b/include/linux/i2c/isl9519.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ISL9519_H__
+#define __ISL9519_H__
+
+/**
+ * struct isl_platform_data
+ * @chgcurrent:	max current the islchip can draw
+ * @valid_irq:			interrupt for insertion/removal notification
+ * @valid_n_gpio:		gpio to debounce insertion/removal
+ * @valid_config:		machine specific func to configure gpio line
+ * @max_system_voltage:		the max voltage isl should charge battery to
+ * @min_system_voltage:		the min voltage isl should trkl charge the
+ *				battery
+ * @term_current:		the batt current when isl charging should stop
+ * @input_current:		the max current isl should pull from the adapter
+ */
+struct isl_platform_data {
+	int chgcurrent;
+	int valid_n_gpio;
+	int (*chg_detection_config) (void);
+	int max_system_voltage;
+	int min_system_voltage;
+	int term_current;
+	int input_current;
+};
+
+#endif
diff --git a/include/linux/i2c/smb137b.h b/include/linux/i2c/smb137b.h
new file mode 100644
index 0000000..a72b895
--- /dev/null
+++ b/include/linux/i2c/smb137b.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __SMB137B_H__
+#define __SMB137B_H__
+
+/**
+ * struct smb137b_platform_data
+ * structure to pass board specific information to the smb137b charger driver
+ * @chgcurrent:	max current the smb137bchip can draw
+ * @valid_n_gpio:		gpio to debounce insertion/removal
+ * @chg_detection_config:	machine specific func to configure
+ *				insertion/removal gpio line
+ * @batt_mah_rating:		the battery current rating
+ */
+struct smb137b_platform_data {
+	int valid_n_gpio;
+	int (*chg_detection_config) (void);
+	int batt_mah_rating;
+};
+
+void smb137b_otg_power(int on);
+
+#endif
diff --git a/include/linux/i2c/sx150x.h b/include/linux/i2c/sx150x.h
index 52baa79..e73dfd9 100644
--- a/include/linux/i2c/sx150x.h
+++ b/include/linux/i2c/sx150x.h
@@ -11,11 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
  */
 #ifndef __LINUX_I2C_SX150X_H
 #define __LINUX_I2C_SX150X_H
diff --git a/include/linux/i2c/tsc2007.h b/include/linux/i2c/tsc2007.h
index 591427a..195e904 100644
--- a/include/linux/i2c/tsc2007.h
+++ b/include/linux/i2c/tsc2007.h
@@ -13,12 +13,18 @@
 	int	fuzzx; /* fuzz factor for X, Y and pressure axes */
 	int	fuzzy;
 	int	fuzzz;
+	unsigned long irq_flags;
+	bool	invert_x;
+	bool	invert_y;
+	bool	invert_z1;
+	bool	invert_z2;
 
 	int	(*get_pendown_state)(void);
 	void	(*clear_penirq)(void);		/* If needed, clear 2nd level
 						   interrupt source */
 	int	(*init_platform_hw)(void);
 	void	(*exit_platform_hw)(void);
+	int	(*power_shutdown)(bool);
 };
 
 #endif
diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h
index 6d722f4..2cc79ae 100644
--- a/include/linux/if_arp.h
+++ b/include/linux/if_arp.h
@@ -59,6 +59,7 @@
 #define ARPHRD_LAPB	516		/* LAPB				*/
 #define ARPHRD_DDCMP    517		/* Digital's DDCMP protocol     */
 #define ARPHRD_RAWHDLC	518		/* Raw HDLC			*/
+#define ARPHRD_RAWIP	530	        /* Raw IP                       */
 
 #define ARPHRD_TUNNEL	768		/* IPIP tunnel			*/
 #define ARPHRD_TUNNEL6	769		/* IP6IP6 tunnel       		*/
diff --git a/include/linux/input.h b/include/linux/input.h
index 771d6d8..d9133f2 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -658,7 +658,7 @@
 #define KEY_NUMERIC_9		0x209
 #define KEY_NUMERIC_STAR	0x20a
 #define KEY_NUMERIC_POUND	0x20b
-
+#define KEY_CAMERA_SNAPSHOT	0x2fe
 #define KEY_CAMERA_FOCUS	0x210
 #define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
 
diff --git a/include/linux/input/cy8c_ts.h b/include/linux/input/cy8c_ts.h
new file mode 100644
index 0000000..d25f31d
--- /dev/null
+++ b/include/linux/input/cy8c_ts.h
@@ -0,0 +1,65 @@
+/* Header file for:
+ * Cypress CY8CTMA300 Prototype touchscreen driver.
+ *
+ * Copyright (C) 2009, 2010 Cypress Semiconductor, Inc.
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, and only version 2, as published by the
+ * Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Cypress reserves the right to make changes without further notice
+ * to the materials described herein. Cypress does not assume any
+ * liability arising out of the application described herein.
+ *
+ * Contact Cypress Semiconductor at www.cypress.com
+ *
+ * History:
+ *			(C) 2010 Cypress - Update for GPL distribution
+ *			(C) 2009 Cypress - Assume maintenance ownership
+ *			(C) 2009 Enea - Original prototype
+ *
+ */
+#ifndef __CY8C8CTS_H__
+#define __CY8C8CTS_H__
+
+
+/* CY8CTMA300-TMG200 platform data
+ */
+struct cy8c_ts_platform_data {
+	int (*power_on)(int on);
+	int (*dev_setup)(bool on);
+	const char *ts_name;
+	u32 dis_min_x; /* display resoltion */
+	u32 dis_max_x;
+	u32 dis_min_y;
+	u32 dis_max_y;
+	u32 min_touch; /* no.of touches supported */
+	u32 max_touch;
+	u32 min_tid; /* track id */
+	u32 max_tid;
+	u32 min_width;/* size of the finger */
+	u32 max_width;
+	u32 res_x; /* TS resolution */
+	u32 res_y;
+	u32 swap_xy;
+	u32 flags;
+	u16 invert_x;
+	u16 invert_y;
+	u8 nfingers;
+	u32 irq_gpio;
+	int resout_gpio;
+	bool wakeup;
+};
+
+#endif
diff --git a/include/linux/input/kp_flip_switch.h b/include/linux/input/kp_flip_switch.h
new file mode 100644
index 0000000..31c0cc4
--- /dev/null
+++ b/include/linux/input/kp_flip_switch.h
@@ -0,0 +1,25 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __KP_FLIP_SWITCH_H_
+#define __KP_FLIP_SWITCH_H_
+/* flip switch driver platform data */
+struct flip_switch_pdata {
+	int flip_gpio;
+	int left_key;
+	int right_key;
+	int wakeup;
+	int active_low;
+	int (*flip_mpp_config) (void);
+	char name[25];
+};
+#endif
diff --git a/include/linux/input/matrix_keypad.h b/include/linux/input/matrix_keypad.h
index fe7c4b9..d80845e 100644
--- a/include/linux/input/matrix_keypad.h
+++ b/include/linux/input/matrix_keypad.h
@@ -4,12 +4,12 @@
 #include <linux/types.h>
 #include <linux/input.h>
 
-#define MATRIX_MAX_ROWS		32
-#define MATRIX_MAX_COLS		32
+#define MATRIX_MAX_ROWS		18
+#define MATRIX_MAX_COLS		18
 
-#define KEY(row, col, val)	((((row) & (MATRIX_MAX_ROWS - 1)) << 24) |\
-				 (((col) & (MATRIX_MAX_COLS - 1)) << 16) |\
-				 ((val) & 0xffff))
+#define KEY(row, col, val)	((((row) % (MATRIX_MAX_ROWS)) << 24) |\
+				 (((col) % (MATRIX_MAX_COLS)) << 16) |\
+				 (val & 0xffff))
 
 #define KEY_ROW(k)		(((k) >> 24) & 0xff)
 #define KEY_COL(k)		(((k) >> 16) & 0xff)
diff --git a/include/linux/input/msm_ts.h b/include/linux/input/msm_ts.h
new file mode 100644
index 0000000..45df9f7
--- /dev/null
+++ b/include/linux/input/msm_ts.h
@@ -0,0 +1,51 @@
+/*
+ * Internal platform definitions for msm/qsd touchscreen devices
+ *
+ * Copyright (C) 2008 Google Incorporated
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_TS_H
+#define __ASM_ARCH_MSM_TS_H
+
+#include <linux/input.h>
+
+/* The dimensions for the virtual key are for the other axis, i.e. if
+ * virtual keys are in the Y dimension then min/max is the range in the X
+ * dimension where that key would be activated */
+struct ts_virt_key {
+	int key;
+	int min;
+	int max;
+};
+
+struct msm_ts_virtual_keys {
+	struct ts_virt_key	*keys;
+	int			num_keys;
+};
+
+struct msm_ts_platform_data {
+	uint32_t			min_x;
+	uint32_t			max_x;
+	uint32_t			min_y;
+	uint32_t			max_y;
+	uint32_t			min_press;
+	uint32_t			max_press;
+	struct msm_ts_virtual_keys	*vkeys_x;
+	uint32_t			virt_x_start;
+	struct msm_ts_virtual_keys	*vkeys_y;
+	uint32_t			virt_y_start;
+	uint32_t			inv_x;
+	uint32_t			inv_y;
+	bool				can_wakeup;
+};
+
+#endif /* __ASM_ARCH_MSM_TS_H */
diff --git a/include/linux/input/pmic8058-keypad.h b/include/linux/input/pmic8058-keypad.h
new file mode 100644
index 0000000..a2fd6ac
--- /dev/null
+++ b/include/linux/input/pmic8058-keypad.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMIC8058_KEYPAD_H__
+#define __PMIC8058_KEYPAD_H__
+
+#include <linux/input/matrix_keypad.h>
+
+/*
+ * NOTE: Assumption of maximum of five revisions
+ * of PMIC8058 chip.
+ */
+#define MAX_PM8058_REVS		0x5
+
+struct pmic8058_keypad_data {
+	const struct matrix_keymap_data *keymap_data;
+
+	const char *input_name;
+	const char *input_phys_device;
+
+	unsigned int num_cols;
+	unsigned int num_rows;
+
+	unsigned int rows_gpio_start;
+	unsigned int cols_gpio_start;
+
+	unsigned int debounce_ms[MAX_PM8058_REVS];
+	unsigned int scan_delay_ms;
+	unsigned int row_hold_ns;
+
+	int keymap_size;
+	const unsigned int *keymap;
+	
+	unsigned int wakeup;
+	unsigned int rep;
+};
+
+#endif /*__PMIC8058_KEYPAD_H__ */
diff --git a/include/linux/input/qci_kbd.h b/include/linux/input/qci_kbd.h
new file mode 100644
index 0000000..5afda7d
--- /dev/null
+++ b/include/linux/input/qci_kbd.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __QCI_KBD_H__
+#define __QCI_KBD_H__
+
+/**
+ * struct qci_kbd_platform_data - platform data for keyboard
+ * @repeat: enable or disable key repeate feature
+ *
+ * platform data structure for QCI keyboard driver.
+ */
+struct qci_kbd_platform_data {
+	bool repeat;
+	bool standard_scancodes;
+	bool kb_leds;
+};
+
+#endif /*__QCI_KBD_H__*/
diff --git a/include/linux/input/tdisc_shinetsu.h b/include/linux/input/tdisc_shinetsu.h
new file mode 100644
index 0000000..88f84f2
--- /dev/null
+++ b/include/linux/input/tdisc_shinetsu.h
@@ -0,0 +1,42 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _TDISC_SHINETSU_H_
+#define _TDISC_SHINETSU_H_
+
+struct tdisc_abs_values {
+	int	x_max;
+	int	y_max;
+	int	x_min;
+	int	y_min;
+	int	pressure_max;
+	int	pressure_min;
+};
+
+struct tdisc_platform_data {
+	int	(*tdisc_setup) (void);
+	void	(*tdisc_release) (void);
+	int	(*tdisc_enable) (void);
+	int	(*tdisc_disable)(void);
+	int	tdisc_wakeup;
+	int	tdisc_gpio;
+	bool	tdisc_report_keys;
+	bool	tdisc_report_relative;
+	bool	tdisc_report_absolute;
+	bool	tdisc_report_wheel;
+	bool	tdisc_reverse_x;
+	bool	tdisc_reverse_y;
+	struct	tdisc_abs_values *tdisc_abs;
+};
+
+#endif /* _TDISC_SHINETSU_H_ */
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index f6efed0..150107b 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -337,6 +337,7 @@
 
 /* IRQ wakeup (PM) control: */
 extern int irq_set_irq_wake(unsigned int irq, unsigned int on);
+extern int irq_read_line(unsigned int irq);
 
 static inline int enable_irq_wake(unsigned int irq)
 {
@@ -686,5 +687,5 @@
 extern int early_irq_init(void);
 extern int arch_probe_nr_irqs(void);
 extern int arch_early_irq_init(void);
-
+extern void irq_set_pending(unsigned int irq);
 #endif
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 0a2ba40..d56318c 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -19,6 +19,9 @@
 #ifndef __LINUX_IOMMU_H
 #define __LINUX_IOMMU_H
 
+#include <linux/types.h>
+#include <linux/errno.h>
+
 #define IOMMU_READ	(1)
 #define IOMMU_WRITE	(2)
 #define IOMMU_CACHE	(4) /* DMA cache coherency */
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index e9bb22c..07988d03 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -115,6 +115,8 @@
 
 extern struct resource *request_resource_conflict(struct resource *root, struct resource *new);
 extern int request_resource(struct resource *root, struct resource *new);
+extern struct resource *locate_resource(struct resource *root,
+	struct resource *search);
 extern int release_resource(struct resource *new);
 void release_child_resources(struct resource *new);
 extern void reserve_region_with_split(struct resource *root,
diff --git a/include/linux/irq.h b/include/linux/irq.h
index baa397e..243d8e9 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -276,6 +276,7 @@
  * @irq_retrigger:	resend an IRQ to the CPU
  * @irq_set_type:	set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
  * @irq_set_wake:	enable/disable power-management wake-on of an IRQ
+ * @irq_read_line:	return the current value on the irq line
  * @irq_bus_lock:	function to lock access to slow bus (i2c) chips
  * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
  * @irq_cpu_online:	configure an interrupt source for a secondary CPU
@@ -304,6 +305,7 @@
 	int		(*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
 	int		(*irq_retrigger)(struct irq_data *data);
 	int		(*irq_set_type)(struct irq_data *data, unsigned int flow_type);
+	int		(*irq_read_line)(struct irq_data *data);
 	int		(*irq_set_wake)(struct irq_data *data, unsigned int on);
 
 	void		(*irq_bus_lock)(struct irq_data *data);
@@ -397,6 +399,8 @@
 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
 			   irqreturn_t action_ret);
 
+/* Resending of interrupts :*/
+void check_irq_resend(struct irq_desc *desc, unsigned int irq);
 
 /* Enable/disable irq debugging output: */
 extern int noirqdebug_setup(char *str);
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index c2478a3..61d429b 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -116,6 +116,7 @@
 					unsigned long nr_segments,
 					struct kexec_segment __user *segments,
 					unsigned long flags);
+extern void __weak arch_kexec(void);
 extern int kernel_kexec(void);
 #ifdef CONFIG_COMPAT
 extern asmlinkage long compat_sys_kexec_load(unsigned long entry,
diff --git a/include/linux/leds-pm8xxx.h b/include/linux/leds-pm8xxx.h
new file mode 100644
index 0000000..3a03100
--- /dev/null
+++ b/include/linux/leds-pm8xxx.h
@@ -0,0 +1,37 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LEDS_PM8XXX_H__
+#define __LEDS_PM8XXX_H__
+
+
+#define PM8XXX_LEDS_DEV_NAME	"pm8xxx-led"
+
+/**
+ * enum pm8xxx_leds - PMIC8XXX supported led ids
+ * @PM8XXX_ID_LED_KB_LIGHT - keyboard backlight led
+ * @PM8XXX_ID_LED_0 - First low current led
+ * @PM8XXX_ID_LED_1 - Second low current led
+ * @PM8XXX_ID_LED_2 - Third low current led
+ * @PM8XXX_ID_FLASH_LED_0 - First flash led
+ * @PM8XXX_ID_FLASH_LED_0 - Second flash led
+ */
+enum pm8xxx_leds {
+	PM8XXX_ID_LED_KB_LIGHT = 1,
+	PM8XXX_ID_LED_0,
+	PM8XXX_ID_LED_1,
+	PM8XXX_ID_LED_2,
+	PM8XXX_ID_FLASH_LED_0,
+	PM8XXX_ID_FLASH_LED_1,
+};
+
+#endif /* __LEDS_PM8XXX_H__ */
diff --git a/include/linux/leds-pmic8058.h b/include/linux/leds-pmic8058.h
new file mode 100644
index 0000000..cbfde9f
--- /dev/null
+++ b/include/linux/leds-pmic8058.h
@@ -0,0 +1,40 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LEDS_PMIC8058_H__
+#define __LEDS_PMIC8058_H__
+
+enum pmic8058_leds {
+	PMIC8058_ID_LED_KB_LIGHT = 1,
+	PMIC8058_ID_LED_0,
+	PMIC8058_ID_LED_1,
+	PMIC8058_ID_LED_2,
+	PMIC8058_ID_FLASH_LED_0,
+	PMIC8058_ID_FLASH_LED_1,
+};
+
+struct pmic8058_led {
+	const char	*name;
+	const char	*default_trigger;
+	unsigned	max_brightness;
+	int		id;
+};
+
+struct pmic8058_leds_platform_data {
+	int	num_leds;
+	struct pmic8058_led *leds;
+};
+
+int pm8058_set_flash_led_current(enum pmic8058_leds id, unsigned mA);
+int pm8058_set_led_current(enum pmic8058_leds id, unsigned mA);
+
+#endif /* __LEDS_PMIC8058_H__ */
diff --git a/include/linux/libra_sdioif.h b/include/linux/libra_sdioif.h
new file mode 100644
index 0000000..965e2b5
--- /dev/null
+++ b/include/linux/libra_sdioif.h
@@ -0,0 +1,77 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LIBRA_SDIOIF_H__
+#define __LIBRA_SDIOIF_H__
+
+/*
+ * Header for SDIO Card Interface Functions
+ */
+#include <linux/kthread.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+
+/*
+ * Common Defines
+ */
+#define LIBRA_MAN_ID              0x70
+#define LIBRA_REV_1_0_CARD_ID     0x0
+
+#define VOLANS_MAN_ID             0x70
+#define VOLANS_REV_1_0_CARD_ID    0x0
+#define VOLANS_REV_2_0_CARD_ID    0x2881
+
+typedef int (suspend_handler_t)(struct sdio_func *);
+typedef void (resume_handler_t)(struct sdio_func *);
+
+int    libra_sdio_configure(sdio_irq_handler_t libra_sdio_rxhandler,
+		void (*func_drv_fn)(int *status),
+		u32 funcdrv_timeout, u32 blksize);
+void   libra_sdio_deconfigure(struct sdio_func *func);
+struct sdio_func *libra_getsdio_funcdev(void);
+void   libra_sdio_setprivdata(struct sdio_func *sdio_func_dev,
+		void *padapter);
+void   *libra_sdio_getprivdata(struct sdio_func *sdio_func_dev);
+void   libra_claim_host(struct sdio_func *sdio_func_dev,
+		pid_t *curr_claimed, pid_t current_pid,
+		atomic_t *claim_count);
+void   libra_release_host(struct sdio_func *sdio_func_dev,
+		pid_t *curr_claimed, pid_t current_pid,
+		atomic_t *claim_count);
+void   libra_sdiocmd52(struct sdio_func *sdio_func_dev,
+		u32 addr, u8 *b, int write, int *err_ret);
+u8     libra_sdio_readsb(struct sdio_func *func, void *dst,
+		unsigned int addr, int count);
+int    libra_sdio_memcpy_fromio(struct sdio_func *func,
+		void *dst, unsigned int addr, int count);
+int    libra_sdio_writesb(struct sdio_func *func,
+		unsigned int addr, void *src, int count);
+int    libra_sdio_memcpy_toio(struct sdio_func *func,
+		unsigned int addr, void *src, int count);
+int    libra_sdio_enable_polling(void);
+
+int libra_sdio_configure_suspend_resume(
+		suspend_handler_t *libra_sdio_suspend_hdlr,
+		resume_handler_t *libra_sdio_resume_hdlr);
+
+int libra_detect_card_change(void);
+
+void libra_sdio_set_clock(struct sdio_func *func, unsigned int clk_freq);
+void libra_sdio_get_card_id(struct sdio_func *func, unsigned short *card_id);
+void libra_sdio_release_irq(struct sdio_func *func);
+int libra_enable_sdio_irq(struct sdio_func *func, u8 enable);
+void libra_sdio_disable_func(struct sdio_func *func);
+int libra_disable_sdio_irq_capability(struct sdio_func *func, u8 disable);
+
+#endif /* __LIBRA_SDIOIF_H__ */
diff --git a/include/linux/m_adcproc.h b/include/linux/m_adcproc.h
new file mode 100644
index 0000000..e36a90a
--- /dev/null
+++ b/include/linux/m_adcproc.h
@@ -0,0 +1,30 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _M_ADC_PROC_H
+#define _M_ADC_PROC_H
+
+#include <linux/msm_adc.h>
+int32_t tdkntcgtherm(int32_t adc_code, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+int32_t scale_default(int32_t adc_code, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+int32_t scale_msm_therm(int32_t adc_code, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+int32_t scale_batt_therm(int32_t adc_code, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+int32_t scale_pmic_therm(int32_t adc_code, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+int32_t scale_xtern_chgr_cur(int32_t adc_code, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+#endif /* _M_ADC_PROC_H */
diff --git a/include/linux/memory_alloc.h b/include/linux/memory_alloc.h
new file mode 100644
index 0000000..88e64ce
--- /dev/null
+++ b/include/linux/memory_alloc.h
@@ -0,0 +1,53 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_MEMALLOC_H
+#define	_LINUX_MEMALLOC_H
+
+#include <linux/mutex.h>
+#include <linux/genalloc.h>
+#include <linux/rbtree.h>
+
+struct mem_pool {
+	struct mutex pool_mutex;
+	struct gen_pool *gpool;
+	unsigned long paddr;
+	unsigned long size;
+	unsigned long free;
+};
+
+struct alloc {
+	struct rb_node rb_node;
+	void *vaddr;
+	unsigned long paddr;
+	struct mem_pool *mpool;
+	unsigned long len;
+};
+
+struct mem_pool *initialize_memory_pool(unsigned long start,
+	unsigned long size, int mem_type);
+
+void *allocate_contiguous_memory(unsigned long size,
+	int mem_type, unsigned long align, int cached);
+
+unsigned long allocate_contiguous_memory_nomap(unsigned long size,
+	int mem_type, unsigned long align);
+
+void free_contiguous_memory(void *addr);
+void free_contiguous_memory_by_paddr(unsigned long paddr);
+
+unsigned long memory_pool_node_paddr(void *vaddr);
+
+unsigned long memory_pool_node_len(void *vaddr);
+
+int memory_pool_init(void);
+#endif	/* _LINUX_MEMALLOC_H */
diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h
index 8122018d..2d2414b 100644
--- a/include/linux/memory_hotplug.h
+++ b/include/linux/memory_hotplug.h
@@ -10,6 +10,9 @@
 struct pglist_data;
 struct mem_section;
 
+extern unsigned long movable_reserved_start, movable_reserved_size;
+extern unsigned long low_power_memory_start, low_power_memory_size;
+
 #ifdef CONFIG_MEMORY_HOTPLUG
 
 /*
@@ -232,4 +235,14 @@
 extern struct page *sparse_decode_mem_map(unsigned long coded_mem_map,
 					  unsigned long pnum);
 
+extern void reserve_hotplug_pages(unsigned long start_pfn,
+				unsigned long nr_pages);
+extern void unreserve_hotplug_pages(unsigned long start_pfn,
+				unsigned long nr_pages);
 #endif /* __LINUX_MEMORY_HOTPLUG_H */
+extern int physical_remove_memory(u64 start, u64 size);
+extern int arch_physical_remove_memory(u64 start, u64 size);
+extern int physical_low_power_memory(u64 start, u64 size);
+extern int arch_physical_low_power_memory(u64 start, u64 size);
+extern int physical_active_memory(u64 start, u64 size);
+extern int arch_physical_active_memory(u64 start, u64 size);
diff --git a/include/linux/mfd/Kbuild b/include/linux/mfd/Kbuild
new file mode 100644
index 0000000..7f4d8b3
--- /dev/null
+++ b/include/linux/mfd/Kbuild
@@ -0,0 +1,2 @@
+header-y += timpani-audio.h
+header-y += msm-adie-codec.h
diff --git a/include/linux/mfd/marimba-codec.h b/include/linux/mfd/marimba-codec.h
new file mode 100644
index 0000000..bfda146
--- /dev/null
+++ b/include/linux/mfd/marimba-codec.h
@@ -0,0 +1,52 @@
+/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_MFD_MSM_MARIMBA_CODEC_H
+#define __LINUX_MFD_MSM_MARIMBA_CODEC_H
+
+#include <mach/qdsp5v2/adie_marimba.h>
+
+struct adie_codec_register {
+	u8 reg;
+	u8 mask;
+	u8 val;
+};
+
+struct adie_codec_register_image {
+	struct adie_codec_register *regs;
+	u32 img_sz;
+};
+
+struct adie_codec_path {
+	struct adie_codec_dev_profile *profile;
+	struct adie_codec_register_image img;
+	u32 hwsetting_idx;
+	u32 stage_idx;
+	u32 curr_stage;
+};
+
+int adie_codec_open(struct adie_codec_dev_profile *profile,
+	struct adie_codec_path **path_pptr);
+int adie_codec_setpath(struct adie_codec_path *path_ptr,
+	u32 freq_plan, u32 osr);
+int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state);
+int adie_codec_close(struct adie_codec_path *path_ptr);
+u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile,
+							u32 requested_freq);
+int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable);
+
+int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr,
+		u32 num_channels, u32 vol_percentage /* in percentage */);
+
+int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr,
+		u32 num_channels, u32 volume /* in percentage */);
+#endif
diff --git a/include/linux/mfd/marimba-tsadc.h b/include/linux/mfd/marimba-tsadc.h
new file mode 100644
index 0000000..6a05b43
--- /dev/null
+++ b/include/linux/mfd/marimba-tsadc.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MARIMBA_TSADC_H_
+#define _MARIMBA_TSADC_H_
+
+struct marimba_tsadc_client;
+
+#define	TSSC_SUSPEND_LEVEL  1
+#define	TSADC_SUSPEND_LEVEL 2
+
+int marimba_tsadc_start(struct marimba_tsadc_client *client);
+
+struct marimba_tsadc_client *
+marimba_tsadc_register(struct platform_device *pdev, unsigned int is_ts);
+
+void marimba_tsadc_unregister(struct marimba_tsadc_client *client);
+
+#endif /* _MARIMBA_TSADC_H_ */
diff --git a/include/linux/mfd/marimba.h b/include/linux/mfd/marimba.h
new file mode 100644
index 0000000..32fe748
--- /dev/null
+++ b/include/linux/mfd/marimba.h
@@ -0,0 +1,191 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+/*
+ * Qualcomm Marimba Core Driver header file
+ */
+
+#ifndef _MARIMBA_H
+#define _MARIMBA_H_
+
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include <linux/input/msm_ts.h>
+#include <mach/vreg.h>
+
+#define MARIMBA_NUM_CHILD			4
+
+#define MARIMBA_SLAVE_ID_MARIMBA	0x00
+#define MARIMBA_SLAVE_ID_FM			0x01
+#define MARIMBA_SLAVE_ID_CDC		0x02
+#define MARIMBA_SLAVE_ID_QMEMBIST	0x03
+
+#define MARIMBA_ID_TSADC			0x04
+
+#define BAHAMA_SLAVE_ID_FM_ID		0x02
+#define SLAVE_ID_BAHAMA			0x05
+#define SLAVE_ID_BAHAMA_FM		0x07
+#define SLAVE_ID_BAHAMA_QMEMBIST	0x08
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define MARIMBA_SSBI_ADAP		0x7
+#elif defined(CONFIG_ARCH_MSM8X60)
+#define MARIMBA_SSBI_ADAP		0X8
+#endif
+
+enum chip_id {
+	MARIMBA_ID = 0,
+	TIMPANI_ID,
+	BAHAMA_ID,
+	CHIP_ID_MAX
+};
+
+enum bahama_version {
+	BAHAMA_VER_1_0,
+	BAHAMA_VER_2_0,
+	BAHAMA_VER_UNSUPPORTED = 0xFF
+};
+enum {
+	BT_PCM_ON,
+	BT_PCM_OFF,
+	FM_I2S_ON,
+	FM_I2S_OFF,
+};
+struct marimba {
+	struct i2c_client *client;
+
+	struct i2c_msg xfer_msg[2];
+
+	struct mutex xfer_lock;
+
+	int mod_id;
+};
+
+struct marimba_top_level_platform_data {
+	int slave_id;     /* Member added for eg. */
+};
+
+struct marimba_fm_platform_data {
+	int irq;
+	int (*fm_setup)(struct marimba_fm_platform_data *pdata);
+	void (*fm_shutdown)(struct marimba_fm_platform_data *pdata);
+	struct vreg *vreg_s2;
+	struct vreg *vreg_xo_out;
+	/*
+	This is to indicate whether Fm SoC is I2S master/slave
+		false	- FM SoC is I2S slave
+		true	- FM SoC is I2S master
+	*/
+	bool is_fm_soc_i2s_master;
+	int (*config_i2s_gpio)(int mode);
+};
+
+struct marimba_codec_platform_data {
+	int (*marimba_codec_power)(int vreg_on);
+	void (*snddev_profile_init) (void);
+};
+
+struct marimba_tsadc_setup_params {
+	bool pen_irq_en;
+	bool tsadc_en;
+};
+
+enum sample_period {
+	TSADC_CLK_3 = 0,
+	TSADC_CLK_24,
+	TSADC_CLK_36,
+	TSADC_CLK_48,
+	TSADC_CLK_1,
+	TSADC_CLK_2,
+	TSADC_CLK_6,
+	TSADC_CLK_12,
+	TSADC_CLOCK_MAX
+};
+
+struct marimba_tsadc_config_params2 {
+	unsigned long input_clk_khz;
+	enum sample_period sample_prd;
+};
+
+struct marimba_tsadc_config_params3 {
+	unsigned long prechg_time_nsecs;
+	unsigned long stable_time_nsecs;
+	unsigned long tsadc_test_mode;
+};
+
+struct marimba_tsadc_platform_data {
+	int (*marimba_tsadc_power)(int vreg_on);
+	int (*init)(void);
+	int (*exit)(void);
+	int (*level_vote)(int vote_on);
+	bool tsadc_prechg_en;
+	bool can_wakeup;
+	struct marimba_tsadc_setup_params setup;
+	struct marimba_tsadc_config_params2 params2;
+	struct marimba_tsadc_config_params3 params3;
+
+	struct msm_ts_platform_data *tssc_data;
+};
+
+/*
+ * Marimba Platform Data
+ * */
+struct marimba_platform_data {
+	struct marimba_top_level_platform_data	*marimba_tp_level;
+	struct marimba_fm_platform_data		*fm;
+	struct marimba_codec_platform_data	*codec;
+	struct marimba_tsadc_platform_data	*tsadc;
+	u8 slave_id[(MARIMBA_NUM_CHILD + 1) * CHIP_ID_MAX];
+	u32 (*marimba_setup) (void);
+	void (*marimba_shutdown) (void);
+	u32 (*bahama_setup) (void);
+	u32 (*bahama_shutdown) (int);
+	u32 (*marimba_gpio_config) (int);
+	u32 (*bahama_core_config) (int type);
+	u32 tsadc_ssbi_adap;
+};
+
+/*
+ * Read and Write to register
+ * */
+int marimba_read(struct marimba *, u8 reg, u8 *value, unsigned num_bytes);
+int marimba_write(struct marimba *, u8 reg, u8 *value, unsigned num_bytes);
+
+/*
+ * Read and Write single 8 bit register with bit mask
+ * */
+int marimba_read_bit_mask(struct marimba *, u8 reg, u8 *value,
+					unsigned num_bytes, u8 mask);
+int marimba_write_bit_mask(struct marimba *, u8 reg, u8 *value,
+					unsigned num_bytes, u8 mask);
+
+/*
+ * Read and Write to TSADC registers across the SSBI
+ * * */
+int marimba_ssbi_read(struct marimba *, u16 reg, u8 *value, int len);
+int marimba_ssbi_write(struct marimba *, u16 reg , u8 *value, int len);
+
+/* Read and write to Timpani */
+int timpani_read(struct marimba*, u8 reg, u8 *value, unsigned num_bytes);
+int timpani_write(struct marimba*, u8 reg, u8 *value,
+				unsigned num_bytes);
+
+/* Get the detected codec type */
+int adie_get_detected_codec_type(void);
+int adie_get_detected_connectivity_type(void);
+int marimba_gpio_config(int gpio_value);
+bool marimba_get_fm_status(struct marimba *);
+bool marimba_get_bt_status(struct marimba *);
+void marimba_set_fm_status(struct marimba *, bool);
+void marimba_set_bt_status(struct marimba *, bool);
+int marimba_read_bahama_ver(struct marimba *);
+#endif
diff --git a/include/linux/mfd/msm-adie-codec.h b/include/linux/mfd/msm-adie-codec.h
new file mode 100644
index 0000000..651d34a
--- /dev/null
+++ b/include/linux/mfd/msm-adie-codec.h
@@ -0,0 +1,146 @@
+#ifndef __LINUX_MFD_MSM_ADIE_CODEC_H
+#define __LINUX_MFD_MSM_ADIE_CODEC_H
+
+#include <linux/types.h>
+
+/* Value Represents a entry */
+#define ADIE_CODEC_ACTION_ENTRY       0x1
+/* Value representing a delay wait */
+#define ADIE_CODEC_ACTION_DELAY_WAIT      0x2
+/* Value representing a stage reached */
+#define ADIE_CODEC_ACTION_STAGE_REACHED   0x3
+
+/* This value is the state after the client sets the path */
+#define ADIE_CODEC_PATH_OFF                                        0x0050
+
+/* State to which client asks the drv to proceed to where it can
+ * set up the clocks and 0-fill PCM buffers
+ */
+#define ADIE_CODEC_DIGITAL_READY                                   0x0100
+
+/* State to which client asks the drv to proceed to where it can
+ * start sending data after internal steady state delay
+ */
+#define ADIE_CODEC_DIGITAL_ANALOG_READY                            0x1000
+
+
+/*  Client Asks adie to switch off the Analog portion of the
+ *  the internal codec. After the use of this path
+ */
+#define ADIE_CODEC_ANALOG_OFF                                      0x0750
+
+
+/* Client Asks adie to switch off the digital portion of the
+ *  the internal codec. After switching off the analog portion.
+ *
+ *  0-fill PCM may or maynot be sent at this point
+ *
+ */
+#define ADIE_CODEC_DIGITAL_OFF                                     0x0600
+
+/* State to which client asks the drv to write the default values
+ * to the registers */
+#define ADIE_CODEC_FLASH_IMAGE 					   0x0001
+
+/* Path type */
+#define ADIE_CODEC_RX 0
+#define ADIE_CODEC_TX 1
+#define ADIE_CODEC_LB 3
+#define ADIE_CODEC_MAX 4
+
+#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16))
+
+#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
+	do { \
+		((reg) = ((packed >> 16) & (0xff))); \
+		((mask) = ((packed >> 8) & (0xff))); \
+		((val) = ((packed) & (0xff))); \
+	} while (0);
+
+struct adie_codec_action_unit {
+	u32 type;
+	u32 action;
+};
+
+struct adie_codec_hwsetting_entry{
+	struct adie_codec_action_unit *actions;
+	u32 action_sz;
+	u32 freq_plan;
+	u32 osr;
+	/* u32  VolMask;
+	 * u32  SidetoneMask;
+	 */
+};
+
+struct adie_codec_dev_profile {
+	u32 path_type; /* RX or TX */
+	u32 setting_sz;
+	struct adie_codec_hwsetting_entry *settings;
+};
+
+struct adie_codec_register {
+	u8 reg;
+	u8 mask;
+	u8 val;
+};
+
+struct adie_codec_register_image {
+	struct adie_codec_register *regs;
+	u32 img_sz;
+};
+
+struct adie_codec_path;
+
+struct adie_codec_anc_data {
+	u32 size;
+	u32 writes[];
+};
+
+struct adie_codec_operations {
+	int	 codec_id;
+	int (*codec_open) (struct adie_codec_dev_profile *profile,
+				struct adie_codec_path **path_pptr);
+	int (*codec_close) (struct adie_codec_path *path_ptr);
+	int (*codec_setpath) (struct adie_codec_path *path_ptr,
+				u32 freq_plan, u32 osr);
+	int (*codec_proceed_stage) (struct adie_codec_path *path_ptr,
+					u32 state);
+	u32 (*codec_freq_supported) (struct adie_codec_dev_profile *profile,
+					u32 requested_freq);
+	int (*codec_enable_sidetone) (struct adie_codec_path *rx_path_ptr,
+					u32 enable);
+	int (*codec_enable_anc) (struct adie_codec_path *rx_path_ptr,
+		u32 enable, struct adie_codec_anc_data *calibration_writes);
+	int (*codec_set_device_digital_volume) (
+					struct adie_codec_path *path_ptr,
+					u32 num_channels,
+					u32 vol_percentage);
+
+	int (*codec_set_device_analog_volume) (struct adie_codec_path *path_ptr,
+						u32 num_channels,
+						u32 volume);
+	int (*codec_set_master_mode) (struct adie_codec_path *path_ptr,
+					u8 master);
+};
+
+int adie_codec_register_codec_operations(
+				const struct adie_codec_operations *codec_ops);
+int adie_codec_open(struct adie_codec_dev_profile *profile,
+	struct adie_codec_path **path_pptr);
+int adie_codec_setpath(struct adie_codec_path *path_ptr,
+	u32 freq_plan, u32 osr);
+int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state);
+int adie_codec_close(struct adie_codec_path *path_ptr);
+u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile,
+							u32 requested_freq);
+int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable);
+int adie_codec_enable_anc(struct adie_codec_path *rx_path_ptr, u32 enable,
+	struct adie_codec_anc_data *calibration_writes);
+int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr,
+		u32 num_channels, u32 vol_percentage /* in percentage */);
+
+int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr,
+		u32 num_channels, u32 volume /* in percentage */);
+
+int adie_codec_set_master_mode(struct adie_codec_path *path_ptr, u8 master);
+#endif
diff --git a/include/linux/mfd/pm8921-adc.h b/include/linux/mfd/pm8921-adc.h
new file mode 100644
index 0000000..3de621d
--- /dev/null
+++ b/include/linux/mfd/pm8921-adc.h
@@ -0,0 +1,582 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921 ADC driver header file
+ *
+ */
+
+#ifndef __MFD_PM8921_ADC_H
+#define __MFD_PM8921_ADC_H
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+
+/**
+ * enum pm8921_adc_channels - PM8921 AMUX arbiter channels
+ * %CHANNEL_VCOIN: Backup voltage for certain register set
+ * %CHANNEL_VBAT: Battery voltage
+ * %CHANNEL_DCIN: Charger input voltage without internal OVP
+ * %CHANNEL_ICHG: Charge-current monitor
+ * %CHANNEL_VPH_PWR: Main system power
+ * %CHANNEL_IBAT: Battery charge current
+ * %CHANNEL_MPP_1: 16:1 pre-mux unity scale MPP input
+ * %CHANNEL_MPP_2: 16:1 pre-mux 1/3 scale MPP input
+ * %CHANNEL_BATT_THERM: Battery temperature
+ * %CHANNEL_BATT_ID: Battery detection
+ * %CHANNEL_USBIN: Charger input voltage with internal OVP
+ * %CHANNEL_DIE_TEMP: Pmic_die temperature
+ * %CHANNEL_625MV: 625mv reference channel
+ * %CHANNEL_125V: 1.25v reference channel
+ * %CHANNEL_CHG_TEMP: Charger temperature
+ * %CHANNEL_MUXOFF: Channel to reduce input load on the mux
+ * %CHANNEL_NONE: Do not use this channel
+ */
+enum pm8921_adc_channels {
+	CHANNEL_VCOIN = 0,
+	CHANNEL_VBAT,
+	CHANNEL_DCIN,
+	CHANNEL_ICHG,
+	CHANNEL_VPH_PWR,
+	CHANNEL_IBAT,
+	CHANNEL_MPP_1,
+	CHANNEL_MPP_2,
+	CHANNEL_BATT_THERM,
+	CHANNEL_BATT_ID,
+	CHANNEL_USBIN,
+	CHANNEL_DIE_TEMP,
+	CHANNEL_625MV,
+	CHANNEL_125V,
+	CHANNEL_CHG_TEMP,
+	CHANNEL_MUXOFF,
+	CHANNEL_NONE,
+};
+
+/**
+ * enum pm8921_adc_mpp_channels - PM8921 AMUX arbiter MPP channels
+ * Yet to be defined, each of the value is representative
+ * of the device connected to the MPP
+ * %ADC_MPP_AMUX8: Fixed mappaing to PA THERM
+ */
+enum pm8921_adc_mpp_channels {
+	ADC_MPP_ATEST_8 = 0,
+	ADC_MPP_USB_SNS_DIV20,
+	ADC_MPP_DCIN_SNS_DIV20,
+	ADC_MPP_AMUX3,
+	ADC_MPP_AMUX4,
+	ADC_MPP_AMUX5,
+	ADC_MPP_AMUX6,
+	ADC_MPP_AMUX7,
+	ADC_MPP_AMUX8,
+	ADC_MPP_ATEST_1,
+	ADC_MPP_ATEST_2,
+	ADC_MPP_ATEST_3,
+	ADC_MPP_ATEST_4,
+	ADC_MPP_ATEST_5,
+	ADC_MPP_ATEST_6,
+	ADC_MPP_ATEST_7,
+	ADC_MPP_CHANNEL_NONE,
+};
+
+#define PM8921_ADC_PMIC_0	0x0
+
+#define PM8921_CHANNEL_ADC_625_MV	625
+
+#define PM8921_AMUX_MPP_3	0x3
+#define PM8921_AMUX_MPP_4	0x4
+#define PM8921_AMUX_MPP_5	0x5
+#define PM8921_AMUX_MPP_6	0x6
+#define PM8921_AMUX_MPP_8	0x8
+
+#define PM8921_ADC_DEV_NAME	"pm8921-adc"
+
+/**
+ * enum pm8921_adc_decimation_type - Sampling rate supported
+ * %ADC_DECIMATION_TYPE1: 512
+ * %ADC_DECIMATION_TYPE2: 1K
+ * %ADC_DECIMATION_TYPE3: 2K
+ * %ADC_DECIMATION_TYPE4: 4k
+ * %ADC_DECIMATION_NONE: Do not use this Sampling type
+ *
+ * The Sampling rate is specific to each channel of the PM8921 ADC arbiter.
+ */
+enum pm8921_adc_decimation_type {
+	ADC_DECIMATION_TYPE1 = 0,
+	ADC_DECIMATION_TYPE2,
+	ADC_DECIMATION_TYPE3,
+	ADC_DECIMATION_TYPE4,
+	ADC_DECIMATION_NONE,
+};
+
+/**
+ * enum pm8921_adc_calib_type - PM8921 ADC Calibration type
+ * %ADC_CALIB_ABSOLUTE: Use 625mV and 1.25V reference channels
+ * %ADC_CALIB_RATIOMETRIC: Use reference Voltage/GND
+ * %ADC_CALIB_CONFIG_NONE: Do not use this calibration type
+ *
+ * Use the input reference voltage depending on the calibration type
+ * to calcluate the offset and gain parameters. The calibration is
+ * specific to each channel of the PM8921 ADC.
+ */
+enum pm8921_adc_calib_type {
+	ADC_CALIB_ABSOLUTE = 0,
+	ADC_CALIB_RATIOMETRIC,
+	ADC_CALIB_CONFIG_NONE,
+};
+
+/**
+ * enum pm8921_adc_channel_scaling_param - pre-scaling AMUX ratio
+ * %CHAN_PATH_SCALING1: ratio of {1, 1}
+ * %CHAN_PATH_SCALING2: ratio of {1, 3}
+ * %CHAN_PATH_SCALING3: ratio of {1, 4}
+ * %CHAN_PATH_SCALING4: ratio of {1, 6}
+ * %CHAN_PATH_NONE: Do not use this pre-scaling ratio type
+ *
+ * The pre-scaling is applied for signals to be within the voltage range
+ * of the ADC.
+ */
+enum pm8921_adc_channel_scaling_param {
+	CHAN_PATH_SCALING1 = 0,
+	CHAN_PATH_SCALING2,
+	CHAN_PATH_SCALING3,
+	CHAN_PATH_SCALING4,
+	CHAN_PATH_SCALING_NONE,
+};
+
+/**
+ * enum pm8921_adc_amux_input_rsv - HK/XOADC reference voltage
+ * %AMUX_RSV0: XO_IN/XOADC_GND
+ * %AMUX_RSV1: PMIC_IN/XOADC_GND
+ * %AMUX_RSV2: PMIC_IN/BMS_CSP
+ * %AMUX_RSV3: not used
+ * %AMUX_RSV4: XOADC_GND/XOADC_GND
+ * %AMUX_RSV5: XOADC_VREF/XOADC_GND
+ * %AMUX_NONE: Do not use this input reference voltage selection
+ */
+enum pm8921_adc_amux_input_rsv {
+	AMUX_RSV0 = 0,
+	AMUX_RSV1,
+	AMUX_RSV2,
+	AMUX_RSV3,
+	AMUX_RSV4,
+	AMUX_RSV5,
+	AMUX_NONE,
+};
+
+/**
+ * enum pm8921_adc_premux_mpp_scale_type - 16:1 pre-mux scale ratio
+ * %PREMUX_MPP_SCALE_0: No scaling to the input signal
+ * %PREMUX_MPP_SCALE_1: Unity scaling selected by the user for MPP input
+ * %PREMUX_MPP_SCALE_1_DIV3: 1/3 pre-scale to the input MPP signal
+ * %PREMUX_MPP_NONE: Do not use this pre-scale mpp type
+ */
+enum pm8921_adc_premux_mpp_scale_type {
+	PREMUX_MPP_SCALE_0 = 0,
+	PREMUX_MPP_SCALE_1,
+	PREMUX_MPP_SCALE_1_DIV3,
+	PREMUX_MPP_NONE,
+};
+
+/**
+ * enum pm8921_adc_scale_fn_type - Scaling function for pm8921 pre calibrated
+ *				   digital data relative to ADC reference
+ * %ADC_SCALE_DEFAULT: Default scaling to convert raw adc code to voltage
+ * %ADC_SCALE_BATT_THERM: Conversion to temperature based on btm parameters
+ * %ADC_SCALE_PMIC_THERM: Returns result in milli degree's Centigrade
+ * %ADC_SCALE_XTERN_CHGR_CUR: Returns current across 0.1 ohm resistor
+ * %ADC_SCALE_NONE: Do not use this scaling type
+ */
+enum pm8921_adc_scale_fn_type {
+	ADC_SCALE_DEFAULT = 0,
+	ADC_SCALE_BATT_THERM,
+	ADC_SCALE_PMIC_THERM,
+	ADC_SCALE_XTERN_CHGR_CUR,
+	ADC_SCALE_NONE,
+};
+
+/**
+ * struct pm8921_adc_linear_graph - Represent ADC characteristics
+ * @offset: Offset with respect to the actual curve
+ * @dy: Numerator slope to calculate the gain
+ * @dx: Denominator slope to calculate the gain
+ *
+ * Each ADC device has different offset and gain parameters which are computed
+ * to calibrate the device.
+ */
+struct pm8921_adc_linear_graph {
+	int32_t offset;
+	int32_t dy;
+	int32_t dx;
+};
+
+/**
+ * struct pm8921_adc_map_pt - Map the graph representation for ADC channel
+ * @x: Represent the ADC digitized code
+ * @y: Represent the physical data which can be temperature, voltage,
+ *     resistance
+ */
+struct pm8921_adc_map_pt {
+	int32_t x;
+	int32_t y;
+};
+
+/**
+ * struct pm8921_adc_scaling_ratio - Represent scaling ratio for adc input
+ * @num: Numerator scaling parameter
+ * @den: Denominator scaling parameter
+ */
+struct pm8921_adc_scaling_ratio {
+	int32_t num;
+	int32_t den;
+};
+
+/**
+ * struct pm8921_adc_properties - Represent the ADC properties
+ * @adc_reference: Reference voltage for PM8921 ADC
+ * @bitresolution: ADC bit resolution for PM8921 ADC
+ * @biploar: Polarity for PM8921 ADC
+ */
+struct pm8921_adc_properties {
+	uint32_t	adc_vdd_reference;
+	uint32_t	bitresolution;
+	bool		bipolar;
+};
+
+/**
+ * struct pm8921_adc_chan_properties - Represent channel properties of the ADC
+ * @offset_gain_numerator: The inverse numerator of the gain applied to the
+ *			   input channel
+ * @offset_gain_denominator: The inverse denominator of the gain applied to the
+ *			     input channel
+ * @adc_graph: ADC graph for the channel of struct type pm8921_adc_linear_graph
+ */
+struct pm8921_adc_chan_properties {
+	uint32_t			offset_gain_numerator;
+	uint32_t			offset_gain_denominator;
+	struct pm8921_adc_linear_graph	adc_graph[2];
+};
+
+/**
+ * struct pm8921_adc_chan_result - Represent the result of the PM8921 ADC
+ * @chan: The channel number of the requested conversion
+ * @adc_code: The pre-calibrated digital output of a given ADC relative to the
+ *	      the ADC reference
+ * @measurement: In units specific for a given ADC; most ADC uses reference
+ *		 voltage but some ADC uses reference current. This measurement
+ *		 here is a number relative to a reference of a given ADC
+ * @physical: The data meaningful for each individual channel whether it is
+ *	      voltage, current, temperature, etc.
+ */
+struct pm8921_adc_chan_result {
+	uint32_t	chan;
+	int32_t		adc_code;
+	int64_t		measurement;
+	int64_t		physical;
+};
+
+#if defined(CONFIG_MFD_PM8921_ADC) || defined(CONFIG_MFD_PM8921_ADC_MODULE)
+/**
+ * pm8921_adc_scale_default() - Scales the pre-calibrated digital output
+ *		of an ADC to the ADC reference and compensates for the
+ *		gain and offset.
+ * @adc_code:	pre-calibrated digital ouput of the ADC.
+ * @adc_prop:	adc properties of the pm8921 adc such as bit resolution,
+ *		reference voltage.
+ * @chan_prop:	individual channel properties to compensate the i/p scaling,
+ *		slope and offset.
+ * @chan_rslt:	Physical result to be stored.
+ */
+int32_t pm8921_adc_scale_default(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt);
+/**
+ * pm8921_adc_scale_tdkntcg_therm() - Scales the pre-calibrated digital output
+ *		of an ADC to the ADC reference and compensates for the
+ *		gain and offset. Returns the temperature of the xo therm in mili
+		degC.
+ * @adc_code:	pre-calibrated digital ouput of the ADC.
+ * @adc_prop:	adc properties of the pm8921 adc such as bit resolution,
+ *		reference voltage.
+ * @chan_prop:	individual channel properties to compensate the i/p scaling,
+ *		slope and offset.
+ * @chan_rslt:	physical result to be stored.
+ */
+int32_t pm8921_adc_tdkntcg_therm(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt);
+/**
+ * pm8921_adc_scale_batt_therm() - Scales the pre-calibrated digital output
+ *		of an ADC to the ADC reference and compensates for the
+ *		gain and offset. Returns the temperature in degC.
+ * @adc_code:	pre-calibrated digital ouput of the ADC.
+ * @adc_prop:	adc properties of the pm8921 adc such as bit resolution,
+ *		reference voltage.
+ * @chan_prop:	individual channel properties to compensate the i/p scaling,
+ *		slope and offset.
+ * @chan_rslt:	physical result to be stored.
+ */
+int32_t pm8921_adc_scale_batt_therm(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt);
+/**
+ * pm8921_adc_scale_pmic_therm() - Scales the pre-calibrated digital output
+ *		of an ADC to the ADC reference and compensates for the
+ *		gain and offset. Performs the AMUX out as 2mv/K and returns
+ *		the temperature in mili degC.
+ * @adc_code:	pre-calibrated digital ouput of the ADC.
+ * @adc_prop:	adc properties of the pm8921 adc such as bit resolution,
+ *		reference voltage.
+ * @chan_prop:	individual channel properties to compensate the i/p scaling,
+ *		slope and offset.
+ * @chan_rslt:	physical result to be stored.
+ */
+int32_t pm8921_adc_scale_pmic_therm(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt);
+/**
+ * pm8921_adc_scale_xtern_chgr_cur() - Scales the pre-calibrated digital output
+ *		of an ADC to the ADC reference and compensates for the
+ *		gain and offset. Returns the current across the 10m ohm
+ *		resistor.
+ * @adc_code:	pre-calibrated digital ouput of the ADC.
+ * @adc_prop:	adc properties of the pm8921 adc such as bit resolution,
+ *		reference voltage.
+ * @chan_prop:	individual channel properties to compensate the i/p scaling,
+ *		slope and offset.
+ * @chan_rslt:	physical result to be stored.
+ */
+int32_t pm8921_adc_scale_xtern_chgr_cur(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt);
+
+#else
+static inline int32_t pm8921_adc_scale_default(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8921_adc_tdkntcg_therm(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8921_adc_scale_batt_therm(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8921_adc_scale_pmic_therm(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8921_adc_scale_xtern_chgr_cur(int32_t adc_code,
+			const struct pm8921_adc_properties *adc_prop,
+			const struct pm8921_adc_chan_properties *chan_prop,
+			struct pm8921_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+#endif
+
+/**
+ * struct pm8921_adc_scale_fn - Scaling function prototype
+ * @chan: Function pointer to one of the scaling functions
+ *	which takes the adc properties, channel properties,
+ *	and returns the physical result
+ */
+struct pm8921_adc_scale_fn {
+	int32_t (*chan) (int32_t,
+		const struct pm8921_adc_properties *,
+		const struct pm8921_adc_chan_properties *,
+		struct pm8921_adc_chan_result *);
+};
+
+/**
+ * struct pm8921_adc_amux - AMUX properties for individual channel
+ * @name: Channel name
+ * @channel_name: Channel in integer used from pm8921_adc_channels
+ * @chan_path_prescaling: Channel scaling performed on the input signal
+ * @adc_rsv: Input reference Voltage/GND selection to the ADC
+ * @adc_decimation: Sampling rate desired for the channel
+ * adc_scale_fn: Scaling function to convert to the data meaningful for
+ *		 each individual channel whether it is voltage, current,
+ *		 temperature, etc and compensates the channel properties
+ */
+struct pm8921_adc_amux {
+	char					*name;
+	enum pm8921_adc_channels		channel_name;
+	enum pm8921_adc_channel_scaling_param	chan_path_prescaling;
+	enum pm8921_adc_amux_input_rsv		adc_rsv;
+	enum pm8921_adc_decimation_type		adc_decimation;
+	enum pm8921_adc_scale_fn_type		adc_scale_fn;
+};
+
+/**
+ * struct pm8921_adc_arb_btm - PM8921 ADC BTM parameters
+ * @btm_prop: BTM parameters such as input resistance, voltage and Rtherm across
+ * the thermistor
+ * @btm_param: BTM temperature thresholds and interval to program the BTM
+ * @btm_channel_prop: Channel specific properties of the BTM channel
+ */
+struct pm8921_adc_arb_btm {
+	struct pm8921_adc_btm_prop			*btm_prop;
+	struct pm8921_adc_arb_btm_param			*btm_param;
+	struct pm8921_adc_btm_channel_properties	*btm_channel_prop;
+};
+
+/**
+ * struct pm8921_adc_btm_channel_properties - PM8921 ADC BTM channel properties
+ * @btm_channel: Channel name
+ * @decimation: Sampling rate
+ * @btm_rsv: Input selection of Vref/GND
+ * @chan_prop: Channel properties for the BTM channel
+ */
+struct pm8921_adc_btm_channel_properties {
+	enum pm8921_adc_channels		btm_channel;
+	enum pm8921_adc_decimation_type		decimation;
+	enum pm8921_adc_amux_input_rsv		btm_rsv;
+	struct pm8921_adc_chan_properties	*chan_prop;
+};
+
+/**
+ * struct pm8921_adc_btm_prop - BTM specific resistors, voltage reference to
+ *				calcluate the temperature across Rthm
+ * @rs1: Resistor of the Vref_therm
+ * @rs2: Resistor of BTM
+ * @r_thm: Resistance of the thermistor
+ * vref_thm: Voltage of vref_therm
+ */
+struct pm8921_adc_btm_prop {
+	uint32_t rs_1;
+	uint32_t rs_2;
+	uint32_t r_thm;
+	uint32_t vref_thm;
+};
+
+/**
+ * struct pm8921_adc_arb_btm_param - PM8921 ADC BTM parameters to set threshold
+ *				     temperature for client notification
+ * @low_thr_temp: low temperature threshold request for notification
+ * @high_thr_temp: high temperature threshold request for notification
+ * @low_thr_voltage: low temperature converted to voltage by arbiter driver
+ * @high_thr_voltage: high temperature converted to voltage by arbiter driver
+ * @interval: Interval period to check for temperature notification
+ * @btm_warm_fn: Remote function call for warm threshold
+ * @btm_cold_fn: Remote function call for cold threshold
+ *
+ * BTM client passes the parameters to be set for the
+ * temperature threshold notifications. The client is
+ * responsible for setting the new threshold
+ * levels once the thresholds are reached
+ */
+struct pm8921_adc_arb_btm_param {
+	uint32_t	low_thr_temp;
+	uint32_t	high_thr_temp;
+	uint32_t	low_thr_voltage;
+	uint32_t	high_thr_voltage;
+	int32_t		interval;
+	void		(*btm_warm_fn) (void);
+	void		(*btm_cold_fn) (void);
+};
+
+int32_t pm8921_adc_batt_scaler(struct pm8921_adc_arb_btm_param *);
+
+/**
+ * struct pm8921_adc_platform_data - PM8921 ADC platform data
+ * @adc_prop: ADC specific parameters, voltage and channel setup
+ * @adc_channel: Channel properties of the ADC arbiter
+ * @adc_num_channel: Total number of chanels supported
+ */
+struct pm8921_adc_platform_data {
+	struct pm8921_adc_properties	*adc_prop;
+	struct pm8921_adc_amux		*adc_channel;
+	uint32_t			adc_num_channel;
+	u32				adc_wakeup;
+};
+
+/* Public API */
+#if defined(CONFIG_MFD_PM8921_ADC) || defined(CONFIG_MFD_PM8921_ADC_MODULE)
+/**
+ * pm8921_adc_read() - Performs ADC read on the channel.
+ * @channel:	Input channel to perform the ADC read.
+ * @result:	Structure pointer of type adc_chan_result
+ *		in which the ADC read results are stored.
+ */
+uint32_t pm8921_adc_read(enum pm8921_adc_channels channel,
+				struct pm8921_adc_chan_result *result);
+/**
+ * pm8921_mpp_adc_read() - Performs ADC read on the channel.
+ * @channel:	Input channel to perform the ADC read.
+ * @result:	Structure pointer of type adc_chan_result
+ *		in which the ADC read results are stored.
+ * @mpp_scale:	The pre scale value to be performed to the input signal
+ *		passed. Currently the pre-scale support is for 1 and 1/3.
+ */
+uint32_t pm8921_adc_mpp_read(enum pm8921_adc_mpp_channels channel,
+			struct pm8921_adc_chan_result *result,
+			enum pm8921_adc_premux_mpp_scale_type);
+/**
+ * pm8921_adc_btm_start() - Configure the BTM registers and start
+			monitoring the BATT_THERM channel for
+			threshold warm/cold temperature set
+			by the Battery client. The btm_start
+			api is to be used after calling the
+			pm8921_btm_configure() api which sets
+			the temperature thresholds, interval
+			and functions to call when warm/cold
+			events are triggered.
+ * @param:	none.
+ */
+uint32_t pm8921_adc_btm_start(void);
+
+/**
+ * pm8921_adc_btm_end() - Configures the BTM registers to stop
+ *			monitoring the BATT_THERM channel for
+ *			warm/cold events and disables the
+ *			interval timer.
+ * @param:	none.
+ */
+uint32_t pm8921_adc_btm_end(void);
+
+/**
+ * pm8921_adc_btm_configure() - Configures the BATT_THERM channel
+ *			parameters for warm/cold thresholds.
+ *			Sets the interval timer for perfoming
+ *			reading the temperature done by the HW.
+ * @btm_param:		Structure pointer of type adc_arb_btm_param *
+ *			which client provides for threshold warm/cold,
+ *			interval and functions to call when warm/cold
+ *			events are triggered.
+ */
+uint32_t pm8921_adc_btm_configure(struct pm8921_adc_arb_btm_param *);
+#else
+static inline uint32_t pm8921_adc_read(uint32_t channel,
+				struct pm8921_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8921_mpp_adc_read(uint32_t channel,
+		struct pm8921_adc_chan_result *result,
+		enum pm8921_adc_premux_mpp_scale_type scale)
+{ return -ENXIO; }
+static inline uint32_t pm8921_adc_btm_start(void)
+{ return -ENXIO; }
+static inline uint32_t pm8921_adc_btm_end(void)
+{ return -ENXIO; }
+static inline uint32_t pm8921_adc_btm_configure(
+		struct pm8921_adc_arb_btm_param *param)
+{ return -ENXIO; }
+#endif
+
+#endif /* MFD_PM8921_ADC_H */
diff --git a/include/linux/mfd/pm8xxx/batt-alarm.h b/include/linux/mfd/pm8xxx/batt-alarm.h
new file mode 100644
index 0000000..eb874e9
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/batt-alarm.h
@@ -0,0 +1,200 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC PM8xxx Battery Alarm driver
+ *
+ */
+#ifndef __MFD_PM8XXX_BATT_ALARM_H__
+#define __MFD_PM8XXX_BATT_ALARM_H__
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+
+#define PM8XXX_BATT_ALARM_DEV_NAME	"pm8xxx-batt-alarm"
+
+/**
+ * enum pm8xxx_batt_alarm_core_data - PMIC core specific core passed into the
+ *	batter alarm driver as platform data
+ * @irq_name:
+ * @reg_addr_batt_alarm_threshold:	PMIC threshold register address
+ * @reg_addr_batt_alarm_ctrl1:		PMIC control 1 register address
+ * @reg_addr_batt_alarm_ctrl2:		PMIC control 2 register address
+ * @reg_addr_batt_alarm_pwm_ctrl:	PMIC PWM control register address
+ */
+struct pm8xxx_batt_alarm_core_data {
+	char	*irq_name;
+	u16	reg_addr_threshold;
+	u16	reg_addr_ctrl1;
+	u16	reg_addr_ctrl2;
+	u16	reg_addr_pwm_ctrl;
+};
+
+/**
+ * enum pm8xxx_batt_alarm_comparator - battery alarm comparator ID values
+ */
+enum pm8xxx_batt_alarm_comparator {
+	PM8XXX_BATT_ALARM_LOWER_COMPARATOR,
+	PM8XXX_BATT_ALARM_UPPER_COMPARATOR,
+};
+
+/**
+ * enum pm8xxx_batt_alarm_hold_time - hold time required for out of range
+ *	battery voltage needed to trigger a status change.  Enum names denote
+ *	hold time in milliseconds.
+ */
+enum pm8xxx_batt_alarm_hold_time {
+	PM8XXX_BATT_ALARM_HOLD_TIME_0p125_MS = 0,
+	PM8XXX_BATT_ALARM_HOLD_TIME_0p25_MS,
+	PM8XXX_BATT_ALARM_HOLD_TIME_0p5_MS,
+	PM8XXX_BATT_ALARM_HOLD_TIME_1_MS,
+	PM8XXX_BATT_ALARM_HOLD_TIME_2_MS,
+	PM8XXX_BATT_ALARM_HOLD_TIME_4_MS,
+	PM8XXX_BATT_ALARM_HOLD_TIME_8_MS,
+	PM8XXX_BATT_ALARM_HOLD_TIME_16_MS,
+};
+
+/*
+ * Bits that are set in the return value of pm8xxx_batt_alarm_status_read
+ * to indicate crossing of the upper or lower threshold.
+ */
+#define PM8XXX_BATT_ALARM_STATUS_BELOW_LOWER	BIT(0)
+#define PM8XXX_BATT_ALARM_STATUS_ABOVE_UPPER	BIT(1)
+
+#if defined(CONFIG_MFD_PM8XXX_BATT_ALARM) \
+	|| defined(CONFIG_MFD_PM8XXX_BATT_ALARM_MODULE)
+
+/**
+ * pm8xxx_batt_alarm_enable - enable one of the battery voltage threshold
+ *			      comparators
+ * @comparator:	selects which comparator to enable
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_enable(enum pm8xxx_batt_alarm_comparator comparator);
+
+/**
+ * pm8xxx_batt_alarm_disable - disable one of the battery voltage threshold
+ *			       comparators
+ * @comparator:	selects which comparator to disable
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_disable(enum pm8xxx_batt_alarm_comparator comparator);
+
+
+/**
+ * pm8xxx_batt_alarm_threshold_set - set the lower and upper alarm thresholds
+ * @comparator:		selects which comparator to set the threshold of
+ * @threshold_mV:	battery voltage threshold in millivolts
+ *			set points = 2500-5675 mV in 25 mV steps
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_threshold_set(
+	enum pm8xxx_batt_alarm_comparator comparator, int threshold_mV);
+
+/**
+ * pm8xxx_batt_alarm_status_read - get status of both threshold comparators
+ *
+ * RETURNS:	< 0	   = error
+ *		  0	   = battery voltage ok
+ *		BIT(0) set = battery voltage below lower threshold
+ *		BIT(1) set = battery voltage above upper threshold
+ */
+int pm8xxx_batt_alarm_status_read(void);
+
+/**
+ * pm8xxx_batt_alarm_register_notifier - register a notifier to run when a
+ *	battery voltage change interrupt fires
+ * @nb:	notifier block containing callback function to register
+ *
+ * nb->notifier_call must point to a function of this form -
+ * int (*notifier_call)(struct notifier_block *nb, unsigned long status,
+ *			void *unused);
+ * "status" will receive the battery alarm status; "unused" will be NULL.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_register_notifier(struct notifier_block *nb);
+
+/**
+ * pm8xxx_batt_alarm_unregister_notifier - unregister a notifier that is run
+ *	when a battery voltage change interrupt fires
+ * @nb:	notifier block containing callback function to unregister
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * pm8xxx_batt_alarm_hold_time_set - set hold time of interrupt output *
+ * @hold_time:	amount of time that battery voltage must remain outside of the
+ *		threshold range before the battery alarm interrupt triggers
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_hold_time_set(enum pm8xxx_batt_alarm_hold_time hold_time);
+
+/**
+ * pm8xxx_batt_alarm_pwm_rate_set - set battery alarm update rate *
+ * @use_pwm:		1 = use PWM update rate, 0 = comparators always active
+ * @clock_scaler:	PWM clock scaler = 2 to 9
+ * @clock_divider:	PWM clock divider = 2 to 8
+ *
+ * This function sets the rate at which the battery alarm module enables
+ * the threshold comparators.  The rate is determined by the following equation:
+ *
+ * f_update = (1024 Hz) / (clock_divider * (2 ^ clock_scaler))
+ *
+ * Thus, the update rate can range from 0.25 Hz to 128 Hz.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_batt_alarm_pwm_rate_set(int use_pwm, int clock_scaler,
+				   int clock_divider);
+#else
+
+static inline int
+pm8xxx_batt_alarm_enable(enum pm8xxx_batt_alarm_comparator comparator)
+{ return -ENODEV; }
+
+static inline int
+pm8xxx_batt_alarm_disable(enum pm8xxx_batt_alarm_comparator comparator)
+{ return -ENODEV; }
+
+static inline int
+pm8xxx_batt_alarm_threshold_set(enum pm8xxx_batt_alarm_comparator comparator,
+				int threshold_mV)
+{ return -ENODEV; }
+
+static inline int pm8xxx_batt_alarm_status_read(void)
+{ return -ENODEV; }
+
+static inline int pm8xxx_batt_alarm_register_notifier(struct notifier_block *nb)
+{ return -ENODEV; }
+
+static inline int
+pm8xxx_batt_alarm_unregister_notifier(struct notifier_block *nb)
+{ return -ENODEV; }
+
+static inline int
+pm8xxx_batt_alarm_hold_time_set(enum pm8xxx_batt_alarm_hold_time hold_time)
+{ return -ENODEV; }
+
+static inline int
+pm8xxx_batt_alarm_pwm_rate_set(int use_pwm, int clock_scaler, int clock_divider)
+{ return -ENODEV; }
+
+#endif
+
+
+#endif /* __MFD_PM8XXX_BATT_ALARM_H__ */
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
index bd2f4f6..74c35bf 100644
--- a/include/linux/mfd/pm8xxx/core.h
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -20,15 +20,43 @@
 
 #include <linux/mfd/core.h>
 
+enum pm8xxx_version {
+	PM8XXX_VERSION_8058,
+	PM8XXX_VERSION_8901,
+	PM8XXX_VERSION_8921,
+};
+
+/* PMIC version specific silicon revisions */
+#define PM8XXX_REVISION_8058_TEST	0
+#define PM8XXX_REVISION_8058_1p0	1
+#define PM8XXX_REVISION_8058_2p0	2
+#define PM8XXX_REVISION_8058_2p1	3
+
+#define PM8XXX_REVISION_8901_TEST	0
+#define PM8XXX_REVISION_8901_1p0	1
+#define PM8XXX_REVISION_8901_1p1	2
+#define PM8XXX_REVISION_8901_2p0	3
+#define PM8XXX_REVISION_8901_2p1	4
+
+#define PM8XXX_REVISION_8921_TEST	0
+#define PM8XXX_REVISION_8921_1p0	1
+#define PM8XXX_REVISION_8921_1p1	2
+#define PM8XXX_REVISION_8921_2p0	3
+
 struct pm8xxx_drvdata {
-	int	(*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
-	int	(*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
-	int	(*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
-									int n);
-	int	(*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
-									int n);
-	int	(*pmic_read_irq_stat) (const struct device *dev, int irq);
-	void	*pm_chip_data;
+	int			(*pmic_readb) (const struct device *dev,
+						u16 addr, u8 *val);
+	int			(*pmic_writeb) (const struct device *dev,
+						u16 addr, u8 val);
+	int			(*pmic_read_buf) (const struct device *dev,
+						u16 addr, u8 *buf, int n);
+	int			(*pmic_write_buf) (const struct device *dev,
+						u16 addr, u8 *buf, int n);
+	int			(*pmic_read_irq_stat) (const struct device *dev,
+						int irq);
+	enum pm8xxx_version	(*pmic_get_version) (const struct device *dev);
+	int			(*pmic_get_revision) (const struct device *dev);
+	void			*pm_chip_data;
 };
 
 static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
@@ -78,4 +106,22 @@
 	return dd->pmic_read_irq_stat(dev, irq);
 }
 
+static inline enum pm8xxx_version pm8xxx_get_version(const struct device *dev)
+{
+	struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+	if (!dd)
+		return -EINVAL;
+	return dd->pmic_get_version(dev);
+}
+
+static inline int pm8xxx_get_revision(const struct device *dev)
+{
+	struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+	if (!dd)
+		return -EINVAL;
+	return dd->pmic_get_revision(dev);
+}
+
 #endif
diff --git a/include/linux/mfd/pm8xxx/gpio.h b/include/linux/mfd/pm8xxx/gpio.h
new file mode 100644
index 0000000..0a9c95d
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/gpio.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC8XXX gpio driver header file
+ *
+ */
+
+#ifndef __PM8XXX_GPIO_H
+#define __PM8XXX_GPIO_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_GPIO_DEV_NAME	"pm8xxx-gpio"
+
+struct pm8xxx_gpio_core_data {
+	int	ngpios;
+};
+
+struct pm8xxx_gpio_platform_data {
+	struct pm8xxx_gpio_core_data	gpio_cdata;
+	int				gpio_base;
+};
+
+/* GPIO parameters */
+/* direction */
+#define	PM_GPIO_DIR_OUT			0x01
+#define	PM_GPIO_DIR_IN			0x02
+#define	PM_GPIO_DIR_BOTH		(PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
+
+/* output_buffer */
+#define	PM_GPIO_OUT_BUF_OPEN_DRAIN	1
+#define	PM_GPIO_OUT_BUF_CMOS		0
+
+/* pull */
+#define	PM_GPIO_PULL_UP_30		0
+#define	PM_GPIO_PULL_UP_1P5		1
+#define	PM_GPIO_PULL_UP_31P5		2
+#define	PM_GPIO_PULL_UP_1P5_30		3
+#define	PM_GPIO_PULL_DN			4
+#define	PM_GPIO_PULL_NO			5
+
+/* vin_sel: Voltage Input Select */
+#define	PM_GPIO_VIN_VPH			0 /* 3v ~ 4.4v */
+#define	PM_GPIO_VIN_BB			1 /* ~3.3v */
+#define	PM_GPIO_VIN_S4			2 /* 1.8v */
+#define	PM_GPIO_VIN_L15			3
+#define	PM_GPIO_VIN_L4			4
+#define	PM_GPIO_VIN_L3			5
+#define	PM_GPIO_VIN_L17			6
+
+/* out_strength */
+#define	PM_GPIO_STRENGTH_NO		0
+#define	PM_GPIO_STRENGTH_HIGH		1
+#define	PM_GPIO_STRENGTH_MED		2
+#define	PM_GPIO_STRENGTH_LOW		3
+
+/* function */
+#define	PM_GPIO_FUNC_NORMAL		0
+#define	PM_GPIO_FUNC_PAIRED		1
+#define	PM_GPIO_FUNC_1			2
+#define	PM_GPIO_FUNC_2			3
+#define	PM_GPIO_DTEST1			4
+#define	PM_GPIO_DTEST2			5
+#define	PM_GPIO_DTEST3			6
+#define	PM_GPIO_DTEST4			7
+
+/**
+ * struct pm_gpio - structure to specify gpio configurtion values
+ * @direction:		indicates whether the gpio should be input, output, or
+ *			both. Should be of the type PM_GPIO_DIR_*
+ * @output_buffer:	indicates gpio should be configured as CMOS or open
+ *			drain. Should be of the type PM_GPIO_OUT_BUF_*
+ * @output_value:	The gpio output value of the gpio line - 0 or 1
+ * @pull:		Indicates whether a pull up or pull down should be
+ *			applied. If a pullup is required the current strength
+ *			needs to be specified. Current values of 30uA, 1.5uA,
+ *			31.5uA, 1.5uA with 30uA boost are supported. This value
+ *			should be one of the PM_GPIO_PULL_*
+ * @vin_sel:		specifies the voltage level when the output is set to 1.
+ *			For an input gpio specifies the voltage level at which
+ *			the input is interpreted as a logical 1.
+ * @out_strength:	the amount of current supplied for an output gpio,
+ *			should be of the type PM_GPIO_STRENGTH_*
+ * @function:		choose alternate function for the gpio. Certain gpios
+ *			can be paired (shorted) with each other. Some gpio pin
+ *			can act as alternate functions. This parameter should
+ *			be of type PM_GPIO_FUNC_*
+ * @inv_int_pol:	Invert polarity before feeding the line to the interrupt
+ *			module in pmic. This feature will almost be never used
+ *			since the pm8xxx interrupt block can detect both edges
+ *			and both levels.
+ * @disable_pin:	Disable the gpio by configuring it as high impedance.
+ */
+struct pm_gpio {
+	int		direction;
+	int		output_buffer;
+	int		output_value;
+	int		pull;
+	int		vin_sel;
+	int		out_strength;
+	int		function;
+	int		inv_int_pol;
+	int		disable_pin;
+};
+
+#if defined(CONFIG_GPIO_PM8XXX) || defined(CONFIG_GPIO_PM8XXX_MODULE)
+/**
+ * pm8xxx_gpio_config - configure a gpio controlled by a pm8xxx chip
+ * @gpio: gpio number to configure
+ * @param: configuration values
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_gpio_config(int gpio, struct pm_gpio *param);
+#else
+static inline int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
+{
+	return -ENXIO;
+}
+#endif
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/misc.h b/include/linux/mfd/pm8xxx/misc.h
new file mode 100644
index 0000000..17ec31b
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/misc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MFD_PM8XXX_MISC_H__
+#define __MFD_PM8XXX_MISC_H__
+
+#include <linux/err.h>
+
+#define PM8XXX_MISC_DEV_NAME	"pm8xxx-misc"
+
+/**
+ * struct pm8xxx_misc_platform_data - PM8xxx misc driver platform data
+ * @priority:	PMIC prority level in a multi-PMIC system. Lower value means
+ *		greater priority. Actions are performed from highest to lowest
+ *		priority PMIC.
+ */
+struct pm8xxx_misc_platform_data {
+	int	priority;
+};
+
+#if defined(CONFIG_MFD_PM8XXX_MISC) || defined(CONFIG_MFD_PM8XXX_MISC_MODULE)
+
+/**
+ * pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to
+ *			  either reset or shutdown when they are turned off
+ * @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_reset_pwr_off(int reset);
+
+#else
+
+static inline int pm8xxx_reset_pwr_off(int reset)
+{
+	return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/mpp.h b/include/linux/mfd/pm8xxx/mpp.h
new file mode 100644
index 0000000..1bec5a2
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/mpp.h
@@ -0,0 +1,242 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_MPP_H
+#define __PM8XXX_MPP_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_MPP_DEV_NAME	"pm8xxx-mpp"
+
+struct pm8xxx_mpp_core_data {
+	int	base_addr;
+	int	nmpps;
+};
+
+struct pm8xxx_mpp_platform_data {
+	struct pm8xxx_mpp_core_data	core_data;
+	int				mpp_base;
+};
+
+/**
+ * struct pm8xxx_mpp_config_data - structure to specify mpp configuration values
+ * @type:	MPP type which determines the overall MPP function (i.e. digital
+ *		in/out/bi, analog in/out, current sink, or test).  It should be
+ *		set to the value of one of PM8XXX_MPP_TYPE_D_*.
+ * @level:	meaning depends upon MPP type specified
+ * @control:	meaning depends upon MPP type specified
+ *
+ * Usage of level argument:
+ * 1. type = PM8XXX_MPP_TYPE_D_INPUT, PM8XXX_MPP_TYPE_D_OUTPUT,
+ *	     PM8XXX_MPP_TYPE_D_BI_DIR, or PM8XXX_MPP_TYPE_DTEST_OUTPUT -
+ *
+ *	level specifies that digital logic level to use for the MPP.  It should
+ *	be set to the value of one of PM8XXX_MPP_DIG_LEVEL_*.  Actual regulator
+ *	connections for these level choices are PMIC chip specific.
+ *
+ * 2. type = PM8XXX_MPP_TYPE_A_INPUT -
+ *
+ *	level specifies where in the PMIC chip the analog input value should
+ *	be routed to.  It should be set to the value of one of
+ *	PM8XXX_MPP_AIN_AMUX_*.
+ *
+ * 3. type = PM8XXX_MPP_TYPE_A_OUTPUT -
+ *
+ *	level specifies the output analog voltage reference level.  It should
+ *	be set to the value of one of PM8XXX_MPP_AOUT_LVL_*.
+ *
+ * 4. type = PM8XXX_MPP_TYPE_SINK or PM8XXX_MPP_TYPE_DTEST_SINK -
+ *
+ *	level specifies the output current level.  It should be set to the value
+ *	of one of PM8XXX_MPP_CS_OUT_*.
+ *
+ * Usage of control argument:
+ * 1. type = PM8XXX_MPP_TYPE_D_INPUT -
+ *
+ *	control specifies how the digital input should be routed in the chip.
+ *	It should be set to the value of one of PM8XXX_MPP_DIN_TO_*.
+ *
+ * 2. type = PM8XXX_MPP_TYPE_D_OUTPUT -
+ *
+ *	control specifies the digital output value.  It should be set to the
+ *	value of one of PM8XXX_MPP_DOUT_CTRL_*.
+ *
+ * 3. type = PM8XXX_MPP_TYPE_D_BI_DIR -
+ *
+ *	control specifies the pullup resistor value.  It should be set to the
+ *	value of one of PM8XXX_MPP_BI_PULLUP_*.
+ *
+ * 4. type = PM8XXX_MPP_TYPE_A_INPUT -
+ *
+ *	control is unused; a value of 0 is sufficient.
+ *
+ * 5. type = PM8XXX_MPP_TYPE_A_OUTPUT -
+ *
+ *	control specifies if analog output is enabled.  It should be set to the
+ *	value of one of PM8XXX_MPP_AOUT_CTRL_*.
+ *
+ * 6. type = PM8XXX_MPP_TYPE_SINK -
+ *
+ *	control specifies if current sinking is enabled.  It should be set to
+ *	the value of one of PM8XXX_MPP_CS_CTRL_*.
+ *
+ * 7. type = PM8XXX_MPP_TYPE_DTEST_SINK -
+ *
+ *	control specifies if current sinking is enabled.  It should be set to
+ *	the value of one of PM8XXX_MPP_DTEST_CS_CTRL_*.
+ *
+ * 8. type = PM8XXX_MPP_TYPE_DTEST_OUTPUT -
+ *
+ *	control specifies which DTEST bus value to output.  It should be set to
+ *	the value of one of PM8XXX_MPP_DTEST_*.
+ */
+struct pm8xxx_mpp_config_data {
+	unsigned	type;
+	unsigned	level;
+	unsigned	control;
+};
+
+/* API */
+#if defined(CONFIG_GPIO_PM8XXX_MPP) || defined(CONFIG_GPIO_PM8XXX_MPP_MODULE)
+
+/**
+ * pm8xxx_mpp_config() - configure control options of a multi-purpose pin (MPP)
+ * @mpp:	global GPIO number corresponding to the MPP
+ * @config:	configuration to set for this MPP
+ * Context: can sleep
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_mpp_config(unsigned mpp, struct pm8xxx_mpp_config_data *config);
+
+#else
+
+static inline int pm8xxx_mpp_config(unsigned mpp,
+				    struct pm8xxx_mpp_config_data *config)
+{
+	return -ENXIO;
+}
+
+#endif
+
+/* MPP Type: type */
+#define	PM8XXX_MPP_TYPE_D_INPUT		0
+#define	PM8XXX_MPP_TYPE_D_OUTPUT	1
+#define	PM8XXX_MPP_TYPE_D_BI_DIR	2
+#define	PM8XXX_MPP_TYPE_A_INPUT		3
+#define	PM8XXX_MPP_TYPE_A_OUTPUT	4
+#define	PM8XXX_MPP_TYPE_SINK		5
+#define	PM8XXX_MPP_TYPE_DTEST_SINK	6
+#define	PM8XXX_MPP_TYPE_DTEST_OUTPUT	7
+
+/* Digital Input/Output: level */
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_0	0
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_1	1
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_2	2
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_3	3
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_4	4
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_5	5
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_6	6
+#define	PM8XXX_MPP_DIG_LEVEL_VIO_7	7
+
+/* Digital Input/Output: level [PM8058] */
+#define	PM8058_MPP_DIG_LEVEL_VPH	0
+#define	PM8058_MPP_DIG_LEVEL_S3		1
+#define	PM8058_MPP_DIG_LEVEL_L2		2
+#define	PM8058_MPP_DIG_LEVEL_L3		3
+
+/* Digital Input/Output: level [PM8901] */
+#define	PM8901_MPP_DIG_LEVEL_MSMIO	0
+#define	PM8901_MPP_DIG_LEVEL_DIG	1
+#define	PM8901_MPP_DIG_LEVEL_L5		2
+#define	PM8901_MPP_DIG_LEVEL_S4		3
+#define	PM8901_MPP_DIG_LEVEL_VPH	4
+
+/* Digital Input/Output: level [PM8921] */
+#define	PM8921_MPP_DIG_LEVEL_S4		1
+#define	PM8921_MPP_DIG_LEVEL_L15	3
+#define	PM8921_MPP_DIG_LEVEL_L17	4
+#define	PM8921_MPP_DIG_LEVEL_VPH	7
+
+/* Digital Input: control */
+#define	PM8XXX_MPP_DIN_TO_INT		0
+#define	PM8XXX_MPP_DIN_TO_DBUS1		1
+#define	PM8XXX_MPP_DIN_TO_DBUS2		2
+#define	PM8XXX_MPP_DIN_TO_DBUS3		3
+
+/* Digital Output: control */
+#define	PM8XXX_MPP_DOUT_CTRL_LOW	0
+#define	PM8XXX_MPP_DOUT_CTRL_HIGH	1
+#define	PM8XXX_MPP_DOUT_CTRL_MPP	2
+#define	PM8XXX_MPP_DOUT_CTRL_INV_MPP	3
+
+/* Bidirectional: control */
+#define	PM8XXX_MPP_BI_PULLUP_1KOHM	0
+#define	PM8XXX_MPP_BI_PULLUP_OPEN	1
+#define	PM8XXX_MPP_BI_PULLUP_10KOHM	2
+#define	PM8XXX_MPP_BI_PULLUP_30KOHM	3
+
+/* Analog Input: level */
+#define	PM8XXX_MPP_AIN_AMUX_CH5		0
+#define	PM8XXX_MPP_AIN_AMUX_CH6		1
+#define	PM8XXX_MPP_AIN_AMUX_CH7		2
+#define	PM8XXX_MPP_AIN_AMUX_CH8		3
+#define	PM8XXX_MPP_AIN_AMUX_CH9		4
+#define	PM8XXX_MPP_AIN_AMUX_ABUS1	5
+#define	PM8XXX_MPP_AIN_AMUX_ABUS2	6
+#define	PM8XXX_MPP_AIN_AMUX_ABUS3	7
+
+/* Analog Output: level */
+#define	PM8XXX_MPP_AOUT_LVL_1V25	0
+#define	PM8XXX_MPP_AOUT_LVL_1V25_2	1
+#define	PM8XXX_MPP_AOUT_LVL_0V625	2
+#define	PM8XXX_MPP_AOUT_LVL_0V3125	3
+#define	PM8XXX_MPP_AOUT_LVL_MPP		4
+#define	PM8XXX_MPP_AOUT_LVL_ABUS1	5
+#define	PM8XXX_MPP_AOUT_LVL_ABUS2	6
+#define	PM8XXX_MPP_AOUT_LVL_ABUS3	7
+
+/* Analog Output: control */
+#define	PM8XXX_MPP_AOUT_CTRL_DISABLE		0
+#define	PM8XXX_MPP_AOUT_CTRL_ENABLE		1
+#define	PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN	2
+#define	PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN		3
+
+/* Current Sink: level */
+#define	PM8XXX_MPP_CS_OUT_5MA		0
+#define	PM8XXX_MPP_CS_OUT_10MA		1
+#define	PM8XXX_MPP_CS_OUT_15MA		2
+#define	PM8XXX_MPP_CS_OUT_20MA		3
+#define	PM8XXX_MPP_CS_OUT_25MA		4
+#define	PM8XXX_MPP_CS_OUT_30MA		5
+#define	PM8XXX_MPP_CS_OUT_35MA		6
+#define	PM8XXX_MPP_CS_OUT_40MA		7
+
+/* Current Sink: control */
+#define	PM8XXX_MPP_CS_CTRL_DISABLE	0
+#define	PM8XXX_MPP_CS_CTRL_ENABLE	1
+#define	PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN	2
+#define	PM8XXX_MPP_CS_CTRL_MPP_LOW_EN	3
+
+/* DTEST Current Sink: control */
+#define	PM8XXX_MPP_DTEST_CS_CTRL_EN1	0
+#define	PM8XXX_MPP_DTEST_CS_CTRL_EN2	1
+#define	PM8XXX_MPP_DTEST_CS_CTRL_EN3	2
+#define	PM8XXX_MPP_DTEST_CS_CTRL_EN4	3
+
+/* DTEST Digital Output: control */
+#define	PM8XXX_MPP_DTEST_DBUS1		0
+#define	PM8XXX_MPP_DTEST_DBUS2		1
+#define	PM8XXX_MPP_DTEST_DBUS3		2
+#define	PM8XXX_MPP_DTEST_DBUS4		3
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/pm8921-bms.h b/include/linux/mfd/pm8xxx/pm8921-bms.h
new file mode 100644
index 0000000..4b60e78
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8921-bms.h
@@ -0,0 +1,124 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_BMS_H
+#define __PM8XXX_BMS_H
+
+#include <linux/errno.h>
+
+#define PM8921_BMS_DEV_NAME	"pm8921-bms"
+
+#define FCC_CC_COLS		5
+#define FCC_TEMP_COLS		8
+
+#define PC_CC_ROWS		10
+#define PC_CC_COLS		5
+
+#define PC_TEMP_ROWS		29
+#define PC_TEMP_COLS		8
+
+#define MAX_SINGLE_LUT_COLS	20
+
+struct single_row_lut {
+	int x[MAX_SINGLE_LUT_COLS];
+	int y[MAX_SINGLE_LUT_COLS];
+	int cols;
+};
+
+/**
+ * struct pc_sf_lut -
+ * @rows:	number of percent charge entries should be <= PC_CC_ROWS
+ * @cols:	number of charge cycle entries should be <= PC_CC_COLS
+ * @cycles:	the charge cycles at which sf data is available in the table.
+ *		The charge cycles must be in increasing order from 0 to rows.
+ * @percent:	the percent charge at which sf data is available in the table
+ *		The  percentcharge must be in decreasing order from 0 to cols.
+ * @sf:		the scaling factor data
+ */
+struct pc_sf_lut {
+	int rows;
+	int cols;
+	int cycles[PC_CC_COLS];
+	int percent[PC_CC_ROWS];
+	int sf[PC_CC_ROWS][PC_CC_COLS];
+};
+
+/**
+ * struct pc_temp_ocv_lut -
+ * @rows:	number of percent charge entries should be <= PC_TEMP_ROWS
+ * @cols:	number of temperature entries should be <= PC_TEMP_COLS
+ * @temp:	the temperatures at which ocv data is available in the table
+ *		The temperatures must be in increasing order from 0 to rows.
+ * @percent:	the percent charge at which ocv data is available in the table
+ *		The  percentcharge must be in decreasing order from 0 to cols.
+ * @ocv:	the open circuit voltage
+ */
+struct pc_temp_ocv_lut {
+	int rows;
+	int cols;
+	int temp[PC_TEMP_COLS];
+	int percent[PC_TEMP_ROWS];
+	int ocv[PC_TEMP_ROWS][PC_TEMP_COLS];
+};
+
+/**
+ * struct pm8921_bms_battery_data -
+ * @fcc:		full charge capacity (mAmpHour)
+ * @fcc_temp_lut:	table to get fcc at a given temp
+ * @fcc_sf_lut:		table to get fcc scaling factor for given charge cycles
+ * @pc_temp_ocv_lut:	table to get percent charge given batt temp and cycles
+ * @pc_sf_lut:		table to get percent charge scaling factor given cycles
+ *			and percent charge
+ */
+struct pm8921_bms_battery_data {
+	unsigned int			fcc;
+	struct single_row_lut		*fcc_temp_lut;
+	struct single_row_lut		*fcc_sf_lut;
+	struct pc_temp_ocv_lut		*pc_temp_ocv_lut;
+	struct pc_sf_lut		*pc_sf_lut;
+};
+
+/**
+ * struct pm8921_bms_platform_data -
+ * @r_sense:		sense resistor value in (mOhms)
+ * @i_test:		current at which the unusable charger cutoff is to be
+ *			calculated or the peak system current (mA)
+ * @v_failure:		the voltage at which the battery is considered empty(mV)
+ * @calib_delay_ms:	how often should the adc calculate gain and offset
+ * @batt_data:		the battery profile data for the one used in the board
+ */
+struct pm8921_bms_platform_data {
+	unsigned int			r_sense;
+	unsigned int			i_test;
+	unsigned int			v_failure;
+	unsigned int			calib_delay_ms;
+	struct pm8921_bms_battery_data  *batt_data;
+};
+
+#if defined(CONFIG_PM8921_BMS) || defined(CONFIG_PM8921_BMS_MODULE)
+int pm8921_bms_get_percent_charge(void);
+void pm8921_bms_charging_began(void);
+void pm8921_bms_charging_end(void);
+#else
+static inline int pm8921_bms_get_percent_charge(void)
+{
+	return -ENXIO;
+}
+static inline void pm8921_bms_charging_began(void)
+{
+}
+static inline void pm8921_bms_charging_end(void)
+{
+}
+#endif
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
new file mode 100644
index 0000000..a79d753
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -0,0 +1,68 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_CHARGER_H
+#define __PM8XXX_CHARGER_H
+
+#include <linux/errno.h>
+
+#define PM8921_CHARGER_DEV_NAME	"pm8921-charger"
+
+struct pm8xxx_charger_core_data {
+	unsigned int	vbat_channel;
+};
+
+/**
+ * struct pm8921_charger_platform_data -
+ * @safety_time:	max charging time in minutes
+ * @update_time:	how often the userland be updated of the charging
+ * @max_voltage:	the max voltage the battery should be charged up to
+ * @min_voltage:	the voltage where charging method switches from trickle
+ *			to fast. This is also the minimum voltage the system
+ *			operates at
+ * @resume_voltage:	the voltage to wait for before resume charging after the
+ *			battery has been fully charged
+ * @term_current:	the charger current at which EOC happens
+ * @get_batt_capacity_percent:
+ *			a board specific function to return battery
+ *			capacity. If null - a default one will be used
+ *
+ */
+struct pm8921_charger_platform_data {
+	struct pm8xxx_charger_core_data	charger_cdata;
+	unsigned int			safety_time;
+	unsigned int			update_time;
+	unsigned int			max_voltage;
+	unsigned int			min_voltage;
+	unsigned int			resume_voltage;
+	unsigned int			term_current;
+	unsigned int			(*get_batt_capacity_percent) (void);
+};
+
+#if defined(CONFIG_PM8921_CHARGER) || defined(CONFIG_PM8921_CHARGER_MODULE)
+void pm8921_charger_vbus_draw(unsigned int mA);
+int pm8921_charger_register_vbus_sn(void (*callback)(int));
+void pm8921_charger_unregister_vbus_sn(void (*callback)(int));
+#else
+static inline void pm8921_charger_vbus_draw(unsigned int mA)
+{
+}
+static inline int pm8921_charger_register_vbus_sn(void (*callback)(int))
+{
+	return -ENXIO;
+}
+static inline void pm8921_charger_unregister_vbus_sn(void (*callback)(int))
+{
+}
+#endif
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h
index d5517fd..d9ab1a1 100644
--- a/include/linux/mfd/pm8xxx/pm8921.h
+++ b/include/linux/mfd/pm8xxx/pm8921.h
@@ -20,12 +20,111 @@
 
 #include <linux/device.h>
 #include <linux/mfd/pm8xxx/irq.h>
+#include <linux/mfd/pm8xxx/gpio.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+#include <linux/mfd/pm8xxx/rtc.h>
+#include <linux/mfd/pm8xxx/pwm.h>
+#include <linux/mfd/pm8xxx/misc.h>
+#include <linux/mfd/pm8xxx/tm.h>
+#include <linux/mfd/pm8xxx/batt-alarm.h>
+#include <linux/input/pmic8xxx-pwrkey.h>
+#include <linux/input/pmic8xxx-keypad.h>
+#include <linux/regulator/pm8921-regulator.h>
+#include <linux/mfd/pm8xxx/pm8921-charger.h>
+#include <linux/mfd/pm8921-adc.h>
+#include <linux/mfd/pm8xxx/pm8921-bms.h>
+#include <linux/leds.h>
 
 #define PM8921_NR_IRQS		256
 
+#define PM8921_NR_GPIOS		44
+
+#define PM8921_NR_MPPS		12
+
+#define PM8921_GPIO_BLOCK_START	24
+#define PM8921_MPP_BLOCK_START	16
+#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
+
+/* GPIOs and MPPs [1,N] */
+#define PM8921_GPIO_IRQ(base, gpio)	((base) + \
+		PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, (gpio)-1))
+#define PM8921_MPP_IRQ(base, mpp)	((base) + \
+		PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, (mpp)-1))
+
+/* PMIC Interrupts */
+#define PM8921_RTC_ALARM_IRQ		PM8921_IRQ_BLOCK_BIT(4, 7)
+#define PM8921_BATT_ALARM_IRQ		PM8921_IRQ_BLOCK_BIT(5, 6)
+#define PM8921_PWRKEY_REL_IRQ		PM8921_IRQ_BLOCK_BIT(6, 2)
+#define PM8921_PWRKEY_PRESS_IRQ		PM8921_IRQ_BLOCK_BIT(6, 3)
+#define PM8921_KEYPAD_IRQ		PM8921_IRQ_BLOCK_BIT(9, 2)
+#define PM8921_KEYSTUCK_IRQ		PM8921_IRQ_BLOCK_BIT(9, 3)
+#define PM8921_ADC_EOC_USR_IRQ		PM8921_IRQ_BLOCK_BIT(9, 6)
+#define PM8921_ADC_BATT_TEMP_WARM_IRQ	PM8921_IRQ_BLOCK_BIT(9, 1)
+#define PM8921_ADC_BATT_TEMP_COLD_IRQ	PM8921_IRQ_BLOCK_BIT(9, 0)
+#define PM8921_USB_ID_IN_IRQ(base)	(base + PM8921_IRQ_BLOCK_BIT(6, 1))
+
+#define PM8921_USBIN_VALID_IRQ		PM8921_IRQ_BLOCK_BIT(1, 7)
+#define PM8921_USBIN_OV_IRQ		PM8921_IRQ_BLOCK_BIT(1, 6)
+#define PM8921_BATT_INSERTED_IRQ	PM8921_IRQ_BLOCK_BIT(1, 5)
+#define PM8921_VBATDET_LOW_IRQ		PM8921_IRQ_BLOCK_BIT(1, 4)
+#define PM8921_USBIN_UV_IRQ		PM8921_IRQ_BLOCK_BIT(1, 3)
+#define PM8921_VBAT_OV_IRQ		PM8921_IRQ_BLOCK_BIT(1, 2)
+#define PM8921_CHGWDOG_IRQ		PM8921_IRQ_BLOCK_BIT(1, 1)
+#define PM8921_VCP_IRQ			PM8921_IRQ_BLOCK_BIT(1, 0)
+#define PM8921_ATCDONE_IRQ		PM8921_IRQ_BLOCK_BIT(2, 7)
+#define PM8921_ATCFAIL_IRQ		PM8921_IRQ_BLOCK_BIT(2, 6)
+#define PM8921_CHGDONE_IRQ		PM8921_IRQ_BLOCK_BIT(2, 5)
+#define PM8921_CHGFAIL_IRQ		PM8921_IRQ_BLOCK_BIT(2, 4)
+#define PM8921_CHGSTATE_IRQ		PM8921_IRQ_BLOCK_BIT(2, 3)
+#define PM8921_LOOP_CHANGE_IRQ		PM8921_IRQ_BLOCK_BIT(2, 2)
+#define PM8921_FASTCHG_IRQ		PM8921_IRQ_BLOCK_BIT(2, 1)
+#define PM8921_TRKLCHG_IRQ		PM8921_IRQ_BLOCK_BIT(2, 0)
+#define PM8921_BATT_REMOVED_IRQ		PM8921_IRQ_BLOCK_BIT(3, 7)
+#define PM8921_BATTTEMP_HOT_IRQ		PM8921_IRQ_BLOCK_BIT(3, 6)
+#define PM8921_CHGHOT_IRQ		PM8921_IRQ_BLOCK_BIT(3, 5)
+#define PM8921_BATTTEMP_COLD_IRQ	PM8921_IRQ_BLOCK_BIT(3, 4)
+#define PM8921_CHG_GONE_IRQ		PM8921_IRQ_BLOCK_BIT(3, 3)
+#define PM8921_BAT_TEMP_OK_IRQ		PM8921_IRQ_BLOCK_BIT(3, 2)
+#define PM8921_COARSE_DET_LOW_IRQ	PM8921_IRQ_BLOCK_BIT(3, 1)
+#define PM8921_VDD_LOOP_IRQ		PM8921_IRQ_BLOCK_BIT(3, 0)
+#define PM8921_VREG_OV_IRQ		PM8921_IRQ_BLOCK_BIT(5, 7)
+#define PM8921_VBATDET_IRQ		PM8921_IRQ_BLOCK_BIT(5, 5)
+#define PM8921_BATFET_IRQ		PM8921_IRQ_BLOCK_BIT(5, 4)
+#define PM8921_PSI_IRQ			PM8921_IRQ_BLOCK_BIT(5, 3)
+#define PM8921_DCIN_VALID_IRQ		PM8921_IRQ_BLOCK_BIT(5, 2)
+#define PM8921_DCIN_OV_IRQ		PM8921_IRQ_BLOCK_BIT(5, 1)
+#define PM8921_DCIN_UV_IRQ		PM8921_IRQ_BLOCK_BIT(5, 0)
+
+#define PM8921_BMS_SBI_WRITE_OK		PM8921_IRQ_BLOCK_BIT(15, 7)
+#define PM8921_BMS_CC_THR		PM8921_IRQ_BLOCK_BIT(15, 6)
+#define PM8921_BMS_VSENSE_THR		PM8921_IRQ_BLOCK_BIT(15, 5)
+#define PM8921_BMS_VSENSE_FOR_R		PM8921_IRQ_BLOCK_BIT(15, 4)
+#define PM8921_BMS_OCV_FOR_R		PM8921_IRQ_BLOCK_BIT(15, 3)
+#define PM8921_BMS_GOOD_OCV		PM8921_IRQ_BLOCK_BIT(15, 2)
+#define PM8921_BMS_VSENSE_AVG		PM8921_IRQ_BLOCK_BIT(15, 1)
+#define PM8921_BMS_CCADC_EOC		PM8921_IRQ_BLOCK_BIT(15, 0)
+
+#define PM8921_OVERTEMP_IRQ		PM8921_IRQ_BLOCK_BIT(4, 2)
+#define PM8921_TEMPSTAT_IRQ		PM8921_IRQ_BLOCK_BIT(6, 7)
+
+/* PMIC I/O Resources */
+#define PM8921_RTC_BASE 0x11D
+
 struct pm8921_platform_data {
 	int					irq_base;
 	struct pm8xxx_irq_platform_data		*irq_pdata;
+	struct pm8xxx_gpio_platform_data	*gpio_pdata;
+	struct pm8xxx_mpp_platform_data		*mpp_pdata;
+	struct pm8xxx_rtc_platform_data         *rtc_pdata;
+	struct pm8xxx_pwrkey_platform_data	*pwrkey_pdata;
+	struct pm8xxx_keypad_platform_data	*keypad_pdata;
+	struct pm8921_charger_platform_data	*charger_pdata;
+	struct pm8921_bms_platform_data		*bms_pdata;
+	struct pm8xxx_misc_platform_data	*misc_pdata;
+	struct pm8921_regulator_platform_data	*regulator_pdatas;
+	int					num_regulators;
+	struct pm8921_adc_platform_data		*adc_pdata;
+	struct led_platform_data		*leds_pdata;
 };
 
 #endif
diff --git a/include/linux/mfd/pm8xxx/pwm.h b/include/linux/mfd/pm8xxx/pwm.h
new file mode 100644
index 0000000..d85eae0
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pwm.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_PWM_H__
+#define __PM8XXX_PWM_H__
+
+#include <linux/pwm.h>
+
+#define PM8XXX_PWM_DEV_NAME	"pm8xxx-pwm"
+
+#define PM8XXX_PWM_PERIOD_MAX		(327 * USEC_PER_SEC)
+#define PM8XXX_PWM_PERIOD_MIN		7 /* micro seconds */
+
+#define PM_PWM_LUT_SIZE			64
+#define PM_PWM_LUT_DUTY_TIME_MAX	512	/* ms */
+#define PM_PWM_LUT_PAUSE_MAX		(7000 * PM_PWM_LUT_DUTY_TIME_MAX)
+
+/* Flags for Look Up Table */
+#define PM_PWM_LUT_LOOP		0x01
+#define PM_PWM_LUT_RAMP_UP	0x02
+#define PM_PWM_LUT_REVERSE	0x04
+#define PM_PWM_LUT_PAUSE_HI_EN	0x10
+#define PM_PWM_LUT_PAUSE_LO_EN	0x20
+
+#define PM_PWM_LUT_NO_TABLE	0x100
+
+/**
+ * pm8xxx_pwm_lut_config - change a PWM device configuration to use LUT
+ * @pwm: the PWM device
+ * @period_us: period in micro second
+ * @duty_pct: arrary of duty cycles in percent, like 20, 50.
+ * @duty_time_ms: time for each duty cycle in millisecond
+ * @start_idx: start index in lookup table from 0 to MAX-1
+ * @idx_len: number of index
+ * @pause_lo: pause time in millisecond at low index
+ * @pause_hi: pause time in millisecond at high index
+ * @flags: control flags
+ */
+int pm8xxx_pwm_lut_config(struct pwm_device *pwm, int period_us,
+			  int duty_pct[], int duty_time_ms, int start_idx,
+			  int len, int pause_lo, int pause_hi, int flags);
+
+/**
+ * pm8xxx_pwm_lut_enable - control a PWM device to start/stop LUT ramp
+ * @pwm: the PWM device
+ * @start: to start (1), or stop (0)
+ */
+int pm8xxx_pwm_lut_enable(struct pwm_device *pwm, int start);
+
+/* Standard APIs supported */
+/**
+ * pwm_request - request a PWM device
+ * @pwm_id: PWM id or channel
+ * @label: the label to identify the user
+ */
+
+/**
+ * pwm_free - free a PWM device
+ * @pwm: the PWM device
+ */
+
+/**
+ * pwm_config - change a PWM device configuration
+ * @pwm: the PWM device
+ * @period_us: period in microsecond
+ * @duty_us: duty cycle in microsecond
+ */
+
+/**
+ * pwm_enable - start a PWM output toggling
+ * @pwm: the PWM device
+ */
+
+/**
+ * pwm_disable - stop a PWM output toggling
+ * @pwm: the PWM device
+ */
+
+#endif /* __PM8XXX_PWM_H__ */
diff --git a/include/linux/mfd/pm8xxx/rtc.h b/include/linux/mfd/pm8xxx/rtc.h
new file mode 100644
index 0000000..14f1983
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/rtc.h
@@ -0,0 +1,25 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __RTC_PM8XXX_H__
+#define __RTC_PM8XXX_H__
+
+#define PM8XXX_RTC_DEV_NAME     "rtc-pm8xxx"
+/**
+ * struct pm8xxx_rtc_pdata - RTC driver platform data
+ * @rtc_write_enable: variable stating RTC write capability
+ */
+struct pm8xxx_rtc_platform_data {
+	bool rtc_write_enable;
+};
+
+#endif /* __RTC_PM8XXX_H__ */
diff --git a/include/linux/mfd/pm8xxx/tm.h b/include/linux/mfd/pm8xxx/tm.h
new file mode 100644
index 0000000..01edb97
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/tm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC PM8xxx Thermal Manager driver
+ */
+
+#ifndef __PM8XXX_TM_H
+#define __PM8XXX_TM_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_TM_DEV_NAME	"pm8xxx-tm"
+
+enum pm8xxx_tm_adc_type {
+	PM8XXX_TM_ADC_NONE,	/* Estimates temp based on overload level. */
+	PM8XXX_TM_ADC_PM8921_ADC,
+};
+
+struct pm8xxx_tm_core_data {
+	int				adc_channel;
+	unsigned long			default_no_adc_temp;
+	enum pm8xxx_tm_adc_type		adc_type;
+	u16				reg_addr_temp_alarm_ctrl;
+	u16				reg_addr_temp_alarm_pwm;
+	char				*tm_name;
+	char				*irq_name_temp_stat;
+	char				*irq_name_over_temp;
+};
+
+#endif
diff --git a/include/linux/mfd/pmic8058.h b/include/linux/mfd/pmic8058.h
new file mode 100644
index 0000000..4603aed
--- /dev/null
+++ b/include/linux/mfd/pmic8058.h
@@ -0,0 +1,238 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+/*
+ * Qualcomm PMIC8058 driver header file
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/mfd/core.h>
+
+#define PM8058_GPIOS		40
+#define PM8058_MPPS		12
+
+#define PM8058_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
+
+/* MPPs and GPIOs [0,N) */
+#define PM8058_MPP_IRQ(base, mpp)	((base) + \
+					PM8058_IRQ_BLOCK_BIT(16, (mpp)))
+#define PM8058_GPIO_IRQ(base, gpio)	((base) + \
+					PM8058_IRQ_BLOCK_BIT(24, (gpio)))
+
+#define PM8058_KEYPAD_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(9, 2))
+#define PM8058_KEYSTUCK_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(9, 3))
+
+#define PM8058_VCP_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(1, 0))
+#define PM8058_CHGILIM_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(1, 3))
+#define PM8058_VBATDET_LOW_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(1, 4))
+#define PM8058_BATT_REPLACE_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(1, 5))
+#define PM8058_CHGINVAL_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(1, 6))
+#define PM8058_CHGVAL_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(1, 7))
+#define PM8058_CHG_END_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 0))
+#define PM8058_FASTCHG_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 1))
+#define PM8058_CHGSTATE_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 3))
+#define PM8058_AUTO_CHGFAIL_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 4))
+#define PM8058_AUTO_CHGDONE_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 5))
+#define PM8058_ATCFAIL_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 6))
+#define PM8058_ATC_DONE_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(2, 7))
+#define PM8058_OVP_OK_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(3, 0))
+#define PM8058_COARSE_DET_OVP_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(3, 1))
+#define PM8058_VCPMAJOR_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(3, 2))
+#define PM8058_CHG_GONE_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(3, 3))
+#define PM8058_CHGTLIMIT_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(3, 4))
+#define PM8058_CHGHOT_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(3, 5))
+#define PM8058_BATTTEMP_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(3, 6))
+#define PM8058_BATTCONNECT_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(3, 7))
+#define PM8058_BATFET_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(5, 4))
+#define PM8058_VBATDET_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(5, 5))
+#define PM8058_VBAT_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(5, 6))
+
+#define PM8058_CBLPWR_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(4, 3))
+
+#define PM8058_PWRKEY_REL_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(6, 2))
+#define PM8058_PWRKEY_PRESS_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(6, 3))
+#define PM8058_SW_0_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(7, 1))
+#define PM8058_IR_0_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(7, 0))
+#define PM8058_SW_1_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(7, 3))
+#define PM8058_IR_1_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(7, 2))
+#define PM8058_SW_2_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(7, 5))
+#define PM8058_IR_2_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(7, 4))
+#define PM8058_RTC_IRQ(base) 		((base) + PM8058_IRQ_BLOCK_BIT(6, 5))
+#define PM8058_RTC_ALARM_IRQ(base) 	((base) + PM8058_IRQ_BLOCK_BIT(4, 7))
+#define PM8058_ADC_IRQ(base)		((base) + PM8058_IRQ_BLOCK_BIT(9, 4))
+#define PM8058_TEMP_ALARM_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(6, 7))
+#define PM8058_OSCHALT_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(4, 6))
+#define PM8058_BATT_ALARM_IRQ(base)	((base) + PM8058_IRQ_BLOCK_BIT(5, 6))
+
+struct pm8058_chip;
+
+struct pm8058_platform_data {
+	/* This table is only needed for misc interrupts. */
+	int		irq_base;
+	int 		(*init)(struct pm8058_chip *pm_chip);
+
+	int		num_subdevs;
+	struct mfd_cell *sub_devices;
+	int		irq_trigger_flags;
+	struct mfd_cell *charger_sub_device;
+};
+
+struct pm8058_gpio_platform_data {
+	int	gpio_base;
+	int	irq_base;
+	int	(*init)(void);
+};
+
+/* GPIO parameters */
+/* direction */
+#define	PM_GPIO_DIR_OUT			0x01
+#define	PM_GPIO_DIR_IN			0x02
+#define	PM_GPIO_DIR_BOTH		(PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
+
+/* output_buffer */
+#define	PM_GPIO_OUT_BUF_OPEN_DRAIN	1
+#define	PM_GPIO_OUT_BUF_CMOS		0
+
+/* pull */
+#define	PM_GPIO_PULL_UP_30		0
+#define	PM_GPIO_PULL_UP_1P5		1
+#define	PM_GPIO_PULL_UP_31P5		2
+#define	PM_GPIO_PULL_UP_1P5_30		3
+#define	PM_GPIO_PULL_DN			4
+#define	PM_GPIO_PULL_NO			5
+
+/* vin_sel: Voltage Input Select */
+#define	PM_GPIO_VIN_VPH			0
+#define	PM_GPIO_VIN_BB			1
+#define	PM_GPIO_VIN_S3			2
+#define	PM_GPIO_VIN_L3			3
+#define	PM_GPIO_VIN_L7			4
+#define	PM_GPIO_VIN_L6			5
+#define	PM_GPIO_VIN_L5			6
+#define	PM_GPIO_VIN_L2			7
+
+/* out_strength */
+#define	PM_GPIO_STRENGTH_NO		0
+#define	PM_GPIO_STRENGTH_HIGH		1
+#define	PM_GPIO_STRENGTH_MED		2
+#define	PM_GPIO_STRENGTH_LOW		3
+
+/* function */
+#define	PM_GPIO_FUNC_NORMAL		0
+#define	PM_GPIO_FUNC_PAIRED		1
+#define	PM_GPIO_FUNC_1			2
+#define	PM_GPIO_FUNC_2			3
+#define	PM_GPIO_DTEST1			4
+#define	PM_GPIO_DTEST2			5
+#define	PM_GPIO_DTEST3			6
+#define	PM_GPIO_DTEST4			7
+
+struct pm8058_gpio {
+	int		direction;
+	int		output_buffer;
+	int		output_value;
+	int		pull;
+	int		vin_sel;	/* 0..7 */
+	int		out_strength;
+	int		function;
+	int		inv_int_pol;	/* invert interrupt polarity */
+	int		disable_pin;	/* disable pin and tri-state its pad */
+};
+
+/* chip revision */
+#define PM_8058_REV_1p0			0xE1
+#define PM_8058_REV_2p0			0xE2
+#define PM_8058_REV_2p1			0xE3
+
+/* misc: control mask and flag */
+#define	PM8058_UART_MUX_MASK		0x60
+
+#define PM8058_UART_MUX_NO		0x0
+#define PM8058_UART_MUX_1		0x20
+#define PM8058_UART_MUX_2		0x40
+#define PM8058_UART_MUX_3		0x60
+
+enum pon_config{
+	DISABLE_HARD_RESET = 0,
+	SHUTDOWN_ON_HARD_RESET,
+	RESTART_ON_HARD_RESET,
+	MAX_PON_CONFIG,
+};
+
+enum pm8058_smpl_delay {
+	PM8058_SMPL_DELAY_0p5,
+	PM8058_SMPL_DELAY_1p0,
+	PM8058_SMPL_DELAY_1p5,
+	PM8058_SMPL_DELAY_2p0,
+};
+
+/* Note -do not call pm8058_read and pm8058_write in an atomic context */
+int pm8058_read(struct pm8058_chip *pm_chip, u16 addr, u8 *values,
+		unsigned int len);
+int pm8058_write(struct pm8058_chip *pm_chip, u16 addr, u8 *values,
+		 unsigned int len);
+
+int pm8058_gpio_config(int gpio, struct pm8058_gpio *param);
+
+int pm8058_rev(struct pm8058_chip *pm_chip);
+
+int pm8058_irq_get_rt_status(struct pm8058_chip *pm_chip, int irq);
+
+int pm8058_misc_control(struct pm8058_chip *pm_chip, int mask, int flag);
+
+#ifdef CONFIG_PMIC8058
+int pm8058_reset_pwr_off(int reset);
+#else
+static inline int pm8058_reset_pwr_off(int reset) { return 0; }
+#endif
+
+
+int pm8058_hard_reset_config(enum pon_config config);
+
+/**
+ * pm8058_smpl_control - enables/disables SMPL detection
+ * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss
+ *
+ * This function enables or disables the Sudden Momentary Power Loss detection
+ * module.  If SMPL detection is enabled, then when a sufficiently long power
+ * loss event occurs, the PMIC will automatically reset itself.  If SMPL
+ * detection is disabled, then the PMIC will shutdown when power loss occurs.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_smpl_control(int enable);
+
+/**
+ * pm8058_smpl_set_delay - sets the SMPL detection time delay
+ * @delay: enum value corresponding to delay time
+ *
+ * This function sets the time delay of the SMPL detection module.  If power
+ * is reapplied within this interval, then the PMIC reset automatically.  The
+ * SMPL detection module must be enabled for this delay time to take effect.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_smpl_set_delay(enum pm8058_smpl_delay delay);
+
+/**
+ * pm8058_watchdog_reset_control - enables/disables watchdog reset detection
+ * @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low
+ *
+ * This function enables or disables the PMIC watchdog reset detection feature.
+ * If watchdog reset detection is enabled, then the PMIC will reset itself
+ * when PS_HOLD goes low.  If it is not enabled, then the PMIC will shutdown
+ * when PS_HOLD goes low.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_watchdog_reset_control(int enable);
diff --git a/include/linux/mfd/pmic8901.h b/include/linux/mfd/pmic8901.h
new file mode 100644
index 0000000..8b628c5
--- /dev/null
+++ b/include/linux/mfd/pmic8901.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __PMIC8901_H__
+#define __PMIC8901_H__
+/*
+ * Qualcomm PMIC8901 driver header file
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/mfd/core.h>
+
+/* PM8901 interrupt numbers */
+
+#define PM8901_MPPS		4
+
+#define PM8901_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
+
+/* MPPs [0,N) */
+#define PM8901_MPP_IRQ(base, mpp)	((base) + \
+					PM8901_IRQ_BLOCK_BIT(6, (mpp)))
+
+#define PM8901_TEMP_ALARM_IRQ(base)	((base) + PM8901_IRQ_BLOCK_BIT(6, 4))
+#define PM8901_TEMP_HI_ALARM_IRQ(base)	((base) + PM8901_IRQ_BLOCK_BIT(6, 5))
+
+struct pm8901_chip;
+
+struct pm8901_platform_data {
+	/* This table is only needed for misc interrupts. */
+	int		irq_base;
+
+	int		num_subdevs;
+	struct mfd_cell *sub_devices;
+	int		irq_trigger_flags;
+};
+
+struct pm8901_gpio_platform_data {
+	int	gpio_base;
+	int	irq_base;
+};
+
+/* chip revision */
+#define PM_8901_REV_1p0			0xF1
+#define PM_8901_REV_1p1			0xF2
+#define PM_8901_REV_2p0			0xF3
+
+int pm8901_read(struct pm8901_chip *pm_chip, u16 addr, u8 *values,
+		unsigned int len);
+int pm8901_write(struct pm8901_chip *pm_chip, u16 addr, u8 *values,
+		 unsigned int len);
+
+int pm8901_rev(struct pm8901_chip *pm_chip);
+
+int pm8901_irq_get_rt_status(struct pm8901_chip *pm_chip, int irq);
+
+#ifdef CONFIG_PMIC8901
+int pm8901_reset_pwr_off(int reset);
+#else
+static inline int pm8901_reset_pwr_off(int reset) { return 0; }
+#endif
+
+#endif /* __PMIC8901_H__ */
diff --git a/include/linux/mfd/timpani-audio.h b/include/linux/mfd/timpani-audio.h
new file mode 100644
index 0000000..49fd49b
--- /dev/null
+++ b/include/linux/mfd/timpani-audio.h
@@ -0,0 +1,5016 @@
+#ifndef __LINUX_MFD_TIMPANI_AUDIO_H
+#define __LINUX_MFD_TIMPANI_AUDIO_H
+
+/*
+ * MREF
+ */
+#define TIMPANI_A_MREF (0x3)
+#define TIMPANI_MREF_RWC "RW"
+#define TIMPANI_MREF_POR 0xe2
+#define TIMPANI_MREF_S 0
+#define TIMPANI_MREF_M 0xFF
+
+#define TIMPANI_MREF_MREF_BG_EN_S 7
+#define TIMPANI_MREF_MREF_BG_EN_M 0x80
+#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5
+#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20
+#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1
+
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1
+
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1
+
+#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1
+#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2
+#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_RESERVED_S 0
+#define TIMPANI_MREF_RESERVED_M 0x1
+
+
+/* For CDAC_IDAC_REF_CUR */
+#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4)
+#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW"
+#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c
+#define TIMPANI_CDAC_IDAC_REF_CUR_S 0
+#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF
+
+
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7
+
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7
+
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3
+
+
+/* -- For TXADC12_REF_CURR */
+#define TIMPANI_A_TXADC12_REF_CURR (0x5)
+#define TIMPANI_TXADC12_REF_CURR_RWC "RW"
+#define TIMPANI_TXADC12_REF_CURR_POR 0xa0
+#define TIMPANI_TXADC12_REF_CURR_S 0
+#define TIMPANI_TXADC12_REF_CURR_M 0xFF
+
+
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3
+
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3
+
+#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0
+#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF
+
+
+/* -- For TXADC3_EN */
+#define TIMPANI_A_TXADC3_EN (0x9)
+#define TIMPANI_TXADC3_EN_RWC "RW"
+#define TIMPANI_TXADC3_EN_POR 0
+#define TIMPANI_TXADC3_EN_S 0
+#define TIMPANI_TXADC3_EN_M 0xFF
+
+
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_RESERVED_S 0
+#define TIMPANI_TXADC3_EN_RESERVED_M 0x1
+
+
+/* -- For TXADC4_EN */
+#define TIMPANI_A_TXADC4_EN (0xA)
+#define TIMPANI_TXADC4_EN_RWC "RW"
+#define TIMPANI_TXADC4_EN_POR 0
+#define TIMPANI_TXADC4_EN_S 0
+#define TIMPANI_TXADC4_EN_M 0xFF
+
+
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_RESERVED_S 0
+#define TIMPANI_TXADC4_EN_RESERVED_M 0x1
+
+
+/* -- For CODEC_TXADC_STATUS_REGISTER_1 */
+#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB)
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R"
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF
+
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF
+
+
+/* -- For TXFE1 */
+#define TIMPANI_A_TXFE1 (0xD)
+#define TIMPANI_TXFE1_RWC "RW"
+#define TIMPANI_TXFE1_POR 0
+#define TIMPANI_TXFE1_S 0
+#define TIMPANI_TXFE1_M 0xFF
+
+
+#define TIMPANI_TXFE1_TXFE1_EN_S 7
+#define TIMPANI_TXFE1_TXFE1_EN_M 0x80
+#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0
+#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE1_TXFE1_GAIN_S 5
+#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1
+
+
+/* -- For TXFE2 */
+#define TIMPANI_A_TXFE2 (0xE)
+#define TIMPANI_TXFE2_RWC "RW"
+#define TIMPANI_TXFE2_POR 0
+#define TIMPANI_TXFE2_S 0
+#define TIMPANI_TXFE2_M 0xFF
+
+
+#define TIMPANI_TXFE2_TXFE2_EN_S 7
+#define TIMPANI_TXFE2_TXFE2_EN_M 0x80
+#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0
+#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE2_TXFE2_GAIN_S 5
+#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1
+
+
+/* -- For TXFE12_ATEST */
+#define TIMPANI_A_TXFE12_ATEST (0xF)
+#define TIMPANI_TXFE12_ATEST_RWC "RW"
+#define TIMPANI_TXFE12_ATEST_POR 0
+#define TIMPANI_TXFE12_ATEST_S 0
+#define TIMPANI_TXFE12_ATEST_M 0xFF
+
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1
+
+
+/*  -- For TXFE_CLT */
+#define TIMPANI_A_TXFE_CLT (0x10)
+#define TIMPANI_TXFE_CLT_RWC "RW"
+#define TIMPANI_TXFE_CLT_POR 0x68
+#define TIMPANI_TXFE_CLT_S 0
+#define TIMPANI_TXFE_CLT_M 0xFF
+
+
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7
+
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3
+
+#define TIMPANI_TXFE_CLT_RESERVED_S 0
+#define TIMPANI_TXFE_CLT_RESERVED_M 0x7
+
+
+/* -- For TXADC1_EN */
+#define TIMPANI_A_TXADC1_EN (0x11)
+#define TIMPANI_TXADC1_EN_RWC "RW"
+#define TIMPANI_TXADC1_EN_POR 0
+#define TIMPANI_TXADC1_EN_S 0
+#define TIMPANI_TXADC1_EN_M 0xFF
+
+
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_RESERVED_S 0
+#define TIMPANI_TXADC1_EN_RESERVED_M 0x1
+
+
+/* -- For TXADC2_EN */
+#define TIMPANI_A_TXADC2_EN (0x12)
+#define TIMPANI_TXADC2_EN_RWC "RW"
+#define TIMPANI_TXADC2_EN_POR 0
+#define TIMPANI_TXADC2_EN_S 0
+#define TIMPANI_TXADC2_EN_M 0xFF
+
+
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_RESERVED_S 0
+#define TIMPANI_TXADC2_EN_RESERVED_M 0x1
+
+
+/* -- For TXADC_CTL */
+#define TIMPANI_A_TXADC_CTL (0x13)
+#define TIMPANI_TXADC_CTL_RWC "RW"
+#define TIMPANI_TXADC_CTL_POR 0x58
+#define TIMPANI_TXADC_CTL_S 0
+#define TIMPANI_TXADC_CTL_M 0xFF
+
+
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3
+
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3
+
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3
+
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3
+
+
+/* -- For TXADC_CTL2 */
+#define TIMPANI_A_TXADC_CTL2 (0x14)
+#define TIMPANI_TXADC_CTL2_RWC "RW"
+#define TIMPANI_TXADC_CTL2_POR 0x64
+#define TIMPANI_TXADC_CTL2_S 0
+#define TIMPANI_TXADC_CTL2_M 0xFF
+
+
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3
+
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3
+
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3
+
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1
+
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1
+
+
+/* -- For TXADC_CTL3 */
+#define TIMPANI_A_TXADC_CTL3 (0x15)
+#define TIMPANI_TXADC_CTL3_RWC "RW"
+#define TIMPANI_TXADC_CTL3_POR 0x64
+#define TIMPANI_TXADC_CTL3_S 0
+#define TIMPANI_TXADC_CTL3_M 0xFF
+
+
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3
+
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3
+
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3
+
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1
+
+#define TIMPANI_TXADC_CTL3_RESERVED_S 0
+#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1
+
+
+/* -- For TXADC_CHOP_CTL */
+#define TIMPANI_A_TXADC_CHOP_CTL (0x16)
+#define TIMPANI_TXADC_CHOP_CTL_RWC "RW"
+#define TIMPANI_TXADC_CHOP_CTL_POR 0
+#define TIMPANI_TXADC_CHOP_CTL_S 0
+#define TIMPANI_TXADC_CHOP_CTL_M 0xFF
+
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1
+
+#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0
+#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3
+
+
+/* -- For TXFE3 */
+#define TIMPANI_A_TXFE3 (0x18)
+#define TIMPANI_TXFE3_RWC "RW"
+#define TIMPANI_TXFE3_POR 0
+#define TIMPANI_TXFE3_S 0
+#define TIMPANI_TXFE3_M 0xFF
+
+
+#define TIMPANI_TXFE3_TXFE3_EN_S 7
+#define TIMPANI_TXFE3_TXFE3_EN_M 0x80
+#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_TXFE3_GAIN_S 5
+#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE3_RESERVED_1_S 2
+#define TIMPANI_TXFE3_RESERVED_1_M 0x1C
+
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1
+
+#define TIMPANI_TXFE3_RESERVED_2_S 0
+#define TIMPANI_TXFE3_RESERVED_2_M 0x1
+
+
+/*  -- For TXFE4 */
+#define TIMPANI_A_TXFE4 (0x19)
+#define TIMPANI_TXFE4_RWC "RW"
+#define TIMPANI_TXFE4_POR 0
+#define TIMPANI_TXFE4_S 0
+#define TIMPANI_TXFE4_M 0xFF
+
+
+#define TIMPANI_TXFE4_TXFE4_EN_S 7
+#define TIMPANI_TXFE4_TXFE4_EN_M 0x80
+#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0
+#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE4_TXFE4_GAIN_S 5
+#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE4_RESERVED_1_S 2
+#define TIMPANI_TXFE4_RESERVED_1_M 0x1C
+
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1
+
+#define TIMPANI_TXFE4_RESERVED_2_S 0
+#define TIMPANI_TXFE4_RESERVED_2_M 0x1
+
+
+/* -- For TXFE3_ATEST */
+#define TIMPANI_A_TXFE3_ATEST (0x1A)
+#define TIMPANI_TXFE3_ATEST_RWC "RW"
+#define TIMPANI_TXFE3_ATEST_POR 0
+#define TIMPANI_TXFE3_ATEST_S 0
+#define TIMPANI_TXFE3_ATEST_M 0xFF
+
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1
+
+
+/* -- For TXFE_DIFF_SE */
+#define TIMPANI_A_TXFE_DIFF_SE (0x1B)
+#define TIMPANI_TXFE_DIFF_SE_RWC "RW"
+#define TIMPANI_TXFE_DIFF_SE_POR 0
+#define TIMPANI_TXFE_DIFF_SE_S 0
+#define TIMPANI_TXFE_DIFF_SE_M 0xFF
+
+
+#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4
+#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1
+
+
+/* -- For CDAC_RX_CLK_CTL */
+#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20)
+#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW"
+#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98
+#define TIMPANI_CDAC_RX_CLK_CTL_S 0
+#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1
+
+
+/* -- For CDAC_BUFF_CTL */
+#define TIMPANI_A_CDAC_BUFF_CTL (0x21)
+#define TIMPANI_CDAC_BUFF_CTL_RWC "RW"
+#define TIMPANI_CDAC_BUFF_CTL_POR 0x60
+#define TIMPANI_CDAC_BUFF_CTL_S 0
+#define TIMPANI_CDAC_BUFF_CTL_M 0xFF
+
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1
+
+
+/* -- For CDAC_REF_CTL1 */
+#define TIMPANI_A_CDAC_REF_CTL1 (0x22)
+#define TIMPANI_CDAC_REF_CTL1_RWC "RW"
+#define TIMPANI_CDAC_REF_CTL1_POR 0xe1
+#define TIMPANI_CDAC_REF_CTL1_S 0
+#define TIMPANI_CDAC_REF_CTL1_M 0xFF
+
+
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7
+
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7
+
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3
+
+
+/* -- For IDAC_DWA_FIR_CTL */
+#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23)
+#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW"
+#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28
+#define TIMPANI_IDAC_DWA_FIR_CTL_S 0
+#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF
+
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0
+#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7
+
+
+/* -- For CDAC_REF_CTL2 */
+#define TIMPANI_A_CDAC_REF_CTL2 (0x24)
+#define TIMPANI_CDAC_REF_CTL2_RWC "RW"
+#define TIMPANI_CDAC_REF_CTL2_POR 0xc
+#define TIMPANI_CDAC_REF_CTL2_S 0
+#define TIMPANI_CDAC_REF_CTL2_M 0xFF
+
+
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3
+
+
+/* -- For CDAC_CTL1 */
+#define TIMPANI_A_CDAC_CTL1 (0x25)
+#define TIMPANI_CDAC_CTL1_RWC "RW"
+#define TIMPANI_CDAC_CTL1_POR 0xb
+#define TIMPANI_CDAC_CTL1_S 0
+#define TIMPANI_CDAC_CTL1_M 0xFF
+
+
+#define TIMPANI_CDAC_CTL1_RESERVED_S 6
+#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0
+
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3
+
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0
+
+
+/* -- For CDAC_CTL2 */
+#define TIMPANI_A_CDAC_CTL2 (0x26)
+#define TIMPANI_CDAC_CTL2_RWC "RW"
+#define TIMPANI_CDAC_CTL2_POR 0xd0
+#define TIMPANI_CDAC_CTL2_S 0
+#define TIMPANI_CDAC_CTL2_M 0xFF
+
+
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7
+
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7
+
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2
+
+
+/* -- For IDAC_L_CTL */
+#define TIMPANI_A_IDAC_L_CTL (0x28)
+#define TIMPANI_IDAC_L_CTL_RWC "RW"
+#define TIMPANI_IDAC_L_CTL_POR 0xe
+#define TIMPANI_IDAC_L_CTL_S 0
+#define TIMPANI_IDAC_L_CTL_M 0xFF
+
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
+
+
+/* -- For IDAC_R_CTL */
+#define TIMPANI_A_IDAC_R_CTL (0x29)
+#define TIMPANI_IDAC_R_CTL_RWC "RW"
+#define TIMPANI_IDAC_R_CTL_POR 0xe
+#define TIMPANI_IDAC_R_CTL_S 0
+#define TIMPANI_IDAC_R_CTL_M 0xFF
+
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
+
+
+/* -- For PA_MASTER_BIAS */
+#define TIMPANI_A_PA_MASTER_BIAS (0x2D)
+#define TIMPANI_PA_MASTER_BIAS_RWC "RW"
+#define TIMPANI_PA_MASTER_BIAS_POR 0x6f
+#define TIMPANI_PA_MASTER_BIAS_S 0
+#define TIMPANI_PA_MASTER_BIAS_M 0xFF
+
+
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7
+
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7
+
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3
+
+
+/* -- For PA_CLASSD_BIAS */
+#define TIMPANI_A_PA_CLASSD_BIAS (0x2E)
+#define TIMPANI_PA_CLASSD_BIAS_RWC "RW"
+#define TIMPANI_PA_CLASSD_BIAS_POR 0x55
+#define TIMPANI_PA_CLASSD_BIAS_S 0
+#define TIMPANI_PA_CLASSD_BIAS_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3
+
+
+/* -- For AUXPGA_CUR */
+#define TIMPANI_A_AUXPGA_CUR (0x2F)
+#define TIMPANI_AUXPGA_CUR_RWC "RW"
+#define TIMPANI_AUXPGA_CUR_POR 0x44
+#define TIMPANI_AUXPGA_CUR_S 0
+#define TIMPANI_AUXPGA_CUR_M 0xFF
+
+
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF
+
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF
+
+
+/* -- For AUXPGA_CM */
+#define TIMPANI_A_AUXPGA_CM (0x30)
+#define TIMPANI_AUXPGA_CM_RWC "RW"
+#define TIMPANI_AUXPGA_CM_POR 0x92
+#define TIMPANI_AUXPGA_CM_S 0
+#define TIMPANI_AUXPGA_CM_M 0xFF
+
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0
+
+
+/* -- For PA_HPH_EARPA_MSTB_EN */
+#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31)
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW"
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0
+
+
+/* -- For PA_LINE_AUXO_EN */
+#define TIMPANI_A_PA_LINE_AUXO_EN (0x32)
+#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW"
+#define TIMPANI_PA_LINE_AUXO_EN_POR 0
+#define TIMPANI_PA_LINE_AUXO_EN_S 0
+#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0
+
+
+/* -- For PA_CLASSD_AUXPGA_EN */
+#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33)
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW"
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1
+
+
+/* -- For PA_LINE_L_GAIN */
+#define TIMPANI_A_PA_LINE_L_GAIN (0x34)
+#define TIMPANI_PA_LINE_L_GAIN_RWC "RW"
+#define TIMPANI_PA_LINE_L_GAIN_POR 0xac
+#define TIMPANI_PA_LINE_L_GAIN_S 0
+#define TIMPANI_PA_LINE_L_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0
+#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3
+
+
+/* -- For PA_LINE_R_GAIN */
+#define TIMPANI_A_PA_LINE_R_GAIN (0x35)
+#define TIMPANI_PA_LINE_R_GAIN_RWC "RW"
+#define TIMPANI_PA_LINE_R_GAIN_POR 0xac
+#define TIMPANI_PA_LINE_R_GAIN_S 0
+#define TIMPANI_PA_LINE_R_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0
+#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3
+
+
+/* -- For PA_HPH_L_GAIN */
+#define TIMPANI_A_PA_HPH_L_GAIN (0x36)
+#define TIMPANI_PA_HPH_L_GAIN_RWC "RW"
+#define TIMPANI_PA_HPH_L_GAIN_POR 0xae
+#define TIMPANI_PA_HPH_L_GAIN_S 0
+#define TIMPANI_PA_HPH_L_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0
+#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1
+
+
+/* -- For PA_HPH_R_GAIN */
+#define TIMPANI_A_PA_HPH_R_GAIN (0x37)
+#define TIMPANI_PA_HPH_R_GAIN_RWC "RW"
+#define TIMPANI_PA_HPH_R_GAIN_POR 0xae
+#define TIMPANI_PA_HPH_R_GAIN_S 0
+#define TIMPANI_PA_HPH_R_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0
+#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1
+
+
+/* -- For AUXPGA_LR_GAIN */
+#define TIMPANI_A_AUXPGA_LR_GAIN (0x38)
+#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW"
+#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa
+#define TIMPANI_AUXPGA_LR_GAIN_S 0
+#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF
+
+
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF
+
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF
+
+
+/* -- For PA_AUXO_EARPA_CONN */
+#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39)
+#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW"
+#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_S 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF
+
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4
+#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1
+
+
+/* -- For PA_LINE_ST_CONN */
+#define TIMPANI_A_PA_LINE_ST_CONN (0x3A)
+#define TIMPANI_PA_LINE_ST_CONN_RWC "RW"
+#define TIMPANI_PA_LINE_ST_CONN_POR 0
+#define TIMPANI_PA_LINE_ST_CONN_S 0
+#define TIMPANI_PA_LINE_ST_CONN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3
+
+
+/* -- For PA_LINE_MONO_CONN */
+#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B)
+#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW"
+#define TIMPANI_PA_LINE_MONO_CONN_POR 0
+#define TIMPANI_PA_LINE_MONO_CONN_S 0
+#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3
+
+
+/* -- For PA_HPH_ST_CONN */
+#define TIMPANI_A_PA_HPH_ST_CONN (0x3C)
+#define TIMPANI_PA_HPH_ST_CONN_RWC "RW"
+#define TIMPANI_PA_HPH_ST_CONN_POR 0
+#define TIMPANI_PA_HPH_ST_CONN_S 0
+#define TIMPANI_PA_HPH_ST_CONN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0
+
+
+/* -- For PA_HPH_MONO_CONN */
+#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D)
+#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW"
+#define TIMPANI_PA_HPH_MONO_CONN_POR 0
+#define TIMPANI_PA_HPH_MONO_CONN_S 0
+#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0
+#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3
+
+
+/* -- For PA_CLASSD_CONN */
+#define TIMPANI_A_PA_CLASSD_CONN (0x3E)
+#define TIMPANI_PA_CLASSD_CONN_RWC "RW"
+#define TIMPANI_PA_CLASSD_CONN_POR 0
+#define TIMPANI_PA_CLASSD_CONN_S 0
+#define TIMPANI_PA_CLASSD_CONN_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0
+
+#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0
+#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF
+
+
+/* -- For PA_CNP_CTL */
+#define TIMPANI_A_PA_CNP_CTL (0x3F)
+#define TIMPANI_PA_CNP_CTL_RWC "RW"
+#define TIMPANI_PA_CNP_CTL_POR 0x07
+#define TIMPANI_PA_CNP_CTL_S 0
+#define TIMPANI_PA_CNP_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3
+
+#define TIMPANI_PA_CNP_CTL_RESERVED_S 4
+#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30
+
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7
+
+
+/* -- For PA_CLASSD_L_CTL */
+#define TIMPANI_A_PA_CLASSD_L_CTL (0x40)
+#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08
+#define TIMPANI_PA_CLASSD_L_CTL_S 0
+#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6
+#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1
+
+
+/* -- For PA_CLASSD_R_CTL */
+#define TIMPANI_A_PA_CLASSD_R_CTL (0x41)
+#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08
+#define TIMPANI_PA_CLASSD_R_CTL_S 0
+#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6
+#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1
+
+
+/* -- For PA_CLASSD_INT2_CTL */
+#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42)
+#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0
+#define TIMPANI_PA_CLASSD_INT2_CTL_S 0
+#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3
+
+
+/* -- For PA_HPH_L_OCP_CLK_CTL */
+#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43)
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW"
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3
+
+
+/* -- For PA_CLASSD_L_SW_CTL */
+#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44)
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37
+#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
+
+/* -- For PA_CLASSD_L_OCP1 */
+#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45)
+#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff
+#define TIMPANI_PA_CLASSD_L_OCP1_S 0
+#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1
+
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3
+
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF
+
+/* -- For PA_CLASSD_L_OCP2 */
+#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46)
+#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77
+#define TIMPANI_PA_CLASSD_L_OCP2_S 0
+#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF
+
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF
+
+
+/* -- For PA_HPH_R_OCP_CLK_CTL */
+#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47)
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW"
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3
+
+
+/* -- For PA_CLASSD_R_SW_CTL */
+#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48)
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37
+#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
+
+
+/* -- For PA_CLASSD_R_OCP1 */
+#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49)
+#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff
+#define TIMPANI_PA_CLASSD_R_OCP1_S 0
+#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1
+
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3
+
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF
+
+
+/* -- For PA_CLASSD_R_OCP2 */
+#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A)
+#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77
+#define TIMPANI_PA_CLASSD_R_OCP2_S 0
+#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF
+
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF
+
+
+/* -- For PA_HPH_CTL1 */
+#define TIMPANI_A_PA_HPH_CTL1 (0x4B)
+#define TIMPANI_PA_HPH_CTL1_RWC "RW"
+#define TIMPANI_PA_HPH_CTL1_POR 0x44
+#define TIMPANI_PA_HPH_CTL1_S 0
+#define TIMPANI_PA_HPH_CTL1_M 0xFF
+
+
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC
+
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1
+
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7
+
+
+/* -- For PA_HPH_CTL2 */
+#define TIMPANI_A_PA_HPH_CTL2 (0x4C)
+#define TIMPANI_PA_HPH_CTL2_RWC "RW"
+#define TIMPANI_PA_HPH_CTL2_POR 0xC8
+#define TIMPANI_PA_HPH_CTL2_S 0
+#define TIMPANI_PA_HPH_CTL2_M 0xFF
+
+
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3
+
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1
+
+#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0
+#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1
+
+
+/* -- For PA_LINE_AUXO_CTL */
+#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D)
+#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW"
+#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_S 0
+#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF
+
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3
+
+
+/* -- For PA_AUXO_EARPA_CTL */
+#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E)
+#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW"
+#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe
+#define TIMPANI_PA_AUXO_EARPA_CTL_S 0
+#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF
+
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6
+#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0
+
+
+/* -- For PA_EARO_CTL */
+#define TIMPANI_A_PA_EARO_CTL (0x4F)
+#define TIMPANI_PA_EARO_CTL_RWC "RW"
+#define TIMPANI_PA_EARO_CTL_POR 0x0
+#define TIMPANI_PA_EARO_CTL_S 0
+#define TIMPANI_PA_EARO_CTL_M 0xFF
+
+
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1
+
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1
+
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7
+
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7
+
+
+/* -- For PA_MASTER_BIAS_CUR */
+#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50)
+#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW"
+#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea
+#define TIMPANI_PA_MASTER_BIAS_CUR_S 0
+#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF
+
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0
+#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1
+
+
+/* -- For PA_CLASSD_SC_STATUS */
+#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51)
+#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R"
+#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_S 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1
+
+
+/* -- For PA_HPH_SC_STATUS */
+#define TIMPANI_A_PA_HPH_SC_STATUS (0x52)
+#define TIMPANI_PA_HPH_SC_STATUS_RWC "R"
+#define TIMPANI_PA_HPH_SC_STATUS_POR 0
+#define TIMPANI_PA_HPH_SC_STATUS_S 0
+#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF
+
+
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70
+
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4
+
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3
+
+
+/* -- For ATEST_EN */
+#define TIMPANI_A_ATEST_EN (0x53)
+#define TIMPANI_ATEST_EN_RWC "RW"
+#define TIMPANI_ATEST_EN_POR 0
+#define TIMPANI_ATEST_EN_S 0
+#define TIMPANI_ATEST_EN_M 0xFF
+
+
+#define TIMPANI_ATEST_EN_ATEST_EN_S 7
+#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80
+#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0
+#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1
+
+#define TIMPANI_ATEST_EN_RESERVED_S 0
+#define TIMPANI_ATEST_EN_RESERVED_M 0x7F
+
+
+/* -- For ATEST_TSHKADC */
+#define TIMPANI_A_ATEST_TSHKADC (0x54)
+#define TIMPANI_ATEST_TSHKADC_RWC "RW"
+#define TIMPANI_ATEST_TSHKADC_POR 0
+#define TIMPANI_ATEST_TSHKADC_S 0
+#define TIMPANI_ATEST_TSHKADC_M 0xFF
+
+
+#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4
+#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0
+
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3
+
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3
+
+
+/* -- For ATEST_TXADC13 */
+#define TIMPANI_A_ATEST_TXADC13 (0x55)
+#define TIMPANI_ATEST_TXADC13_RWC "RW"
+#define TIMPANI_ATEST_TXADC13_POR 0
+#define TIMPANI_ATEST_TXADC13_S 0
+#define TIMPANI_ATEST_TXADC13_M 0xFF
+
+
+#define TIMPANI_ATEST_TXADC13_RESERVED_S 7
+#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80
+
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1
+
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6
+
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6
+
+
+/* -- For ATEST_TXADC24 */
+#define TIMPANI_A_ATEST_TXADC24 (0x56)
+#define TIMPANI_ATEST_TXADC24_RWC "RW"
+#define TIMPANI_ATEST_TXADC24_POR 0
+#define TIMPANI_ATEST_TXADC24_S 0
+#define TIMPANI_ATEST_TXADC24_M 0xFF
+
+
+#define TIMPANI_ATEST_TXADC24_RESERVED_S 7
+#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80
+
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1
+
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6
+
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6
+
+
+/* -- For ATEST_AUXPGA */
+#define TIMPANI_A_ATEST_AUXPGA (0x57)
+#define TIMPANI_ATEST_AUXPGA_RWC "RW"
+#define TIMPANI_ATEST_AUXPGA_POR 0
+#define TIMPANI_ATEST_AUXPGA_S 0
+#define TIMPANI_ATEST_AUXPGA_M 0xFF
+
+
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0
+#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7
+
+
+/* -- For ATEST_CDAC */
+#define TIMPANI_A_ATEST_CDAC (0x58)
+#define TIMPANI_ATEST_CDAC_RWC "RW"
+#define TIMPANI_ATEST_CDAC_POR 0
+#define TIMPANI_ATEST_CDAC_S 0
+#define TIMPANI_ATEST_CDAC_M 0xFF
+
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3
+
+
+/* -- For ATEST_IDAC */
+#define TIMPANI_A_ATEST_IDAC (0x59)
+#define TIMPANI_ATEST_IDAC_RWC "RW"
+#define TIMPANI_ATEST_IDAC_POR 0
+#define TIMPANI_ATEST_IDAC_S 0
+#define TIMPANI_ATEST_IDAC_M 0xFF
+
+
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0
+
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0
+
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0
+
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0
+
+
+/* -- For ATEST_PA1 */
+#define TIMPANI_A_ATEST_PA1 (0x5A)
+#define TIMPANI_ATEST_PA1_RWC "RW"
+#define TIMPANI_ATEST_PA1_POR 0
+#define TIMPANI_ATEST_PA1_S 0
+#define TIMPANI_ATEST_PA1_M 0xFF
+
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1
+
+
+/* -- For ATEST_CLASSD */
+#define TIMPANI_A_ATEST_CLASSD (0x5B)
+#define TIMPANI_ATEST_CLASSD_RWC "RW"
+#define TIMPANI_ATEST_CLASSD_POR 0
+#define TIMPANI_ATEST_CLASSD_S 0
+#define TIMPANI_ATEST_CLASSD_M 0xFF
+
+
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF
+
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF
+
+
+/* -- For ATEST_LINEO_AUXO */
+#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C)
+#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW"
+#define TIMPANI_ATEST_LINEO_AUXO_POR 0
+#define TIMPANI_ATEST_LINEO_AUXO_S 0
+#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF
+
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1
+
+
+/* -- For CDC_RESET_CTL */
+#define TIMPANI_A_CDC_RESET_CTL (0x80)
+#define TIMPANI_CDC_RESET_CTL_RWC "RW"
+#define TIMPANI_CDC_RESET_CTL_POR 0
+#define TIMPANI_CDC_RESET_CTL_S 0
+#define TIMPANI_CDC_RESET_CTL_M 0x7F
+
+
+#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6
+#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40
+
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20
+
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10
+
+#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3
+#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8
+
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4
+
+#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1
+#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2
+
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1
+
+
+/* -- For CDC_RX1_CTL */
+#define TIMPANI_A_CDC_RX1_CTL (0x81)
+#define TIMPANI_CDC_RX1_CTL_RWC "RW"
+#define TIMPANI_CDC_RX1_CTL_POR 0xc
+#define TIMPANI_CDC_RX1_CTL_S 0
+#define TIMPANI_CDC_RX1_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20
+
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10
+
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0
+
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0
+
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0
+
+
+/* -- For CDC_TX_I2S_CTL */
+#define TIMPANI_A_CDC_TX_I2S_CTL (0x82)
+#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW"
+#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc
+#define TIMPANI_CDC_TX_I2S_CTL_S 0
+#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5
+#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4
+#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0
+
+
+/* -- For CDC_CH_CTL */
+#define TIMPANI_A_CDC_CH_CTL (0x83)
+#define TIMPANI_CDC_CH_CTL_RWC "RW"
+#define TIMPANI_CDC_CH_CTL_POR 0
+#define TIMPANI_CDC_CH_CTL_S 0
+#define TIMPANI_CDC_CH_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7
+#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80
+
+#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6
+#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40
+
+#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5
+#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20
+
+#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4
+#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10
+
+#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3
+#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8
+
+#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2
+#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4
+
+#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1
+#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2
+
+#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0
+#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1
+
+
+/* -- For CDC_RX1LG */
+#define TIMPANI_A_CDC_RX1LG (0x84)
+#define TIMPANI_CDC_RX1LG_RWC "RW"
+#define TIMPANI_CDC_RX1LG_POR 0xac
+#define TIMPANI_CDC_RX1LG_S 0
+#define TIMPANI_CDC_RX1LG_M 0xFF
+
+
+#define TIMPANI_CDC_RX1LG_GAIN_S 0
+#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF
+
+
+/* -- For CDC_RX1RG */
+#define TIMPANI_A_CDC_RX1RG (0x85)
+#define TIMPANI_CDC_RX1RG_RWC "RW"
+#define TIMPANI_CDC_RX1RG_POR 0xac
+#define TIMPANI_CDC_RX1RG_S 0
+#define TIMPANI_CDC_RX1RG_M 0xFF
+
+
+#define TIMPANI_CDC_RX1RG_GAIN_S 0
+#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX1LG */
+#define TIMPANI_A_CDC_TX1LG (0x86)
+#define TIMPANI_CDC_TX1LG_RWC "RW"
+#define TIMPANI_CDC_TX1LG_POR 0xac
+#define TIMPANI_CDC_TX1LG_S 0
+#define TIMPANI_CDC_TX1LG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1LG_GAIN_S 0
+#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX1RG */
+#define TIMPANI_A_CDC_TX1RG (0x87)
+#define TIMPANI_CDC_TX1RG_RWC "RW"
+#define TIMPANI_CDC_TX1RG_POR 0xac
+#define TIMPANI_CDC_TX1RG_S 0
+#define TIMPANI_CDC_TX1RG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1RG_GAIN_S 0
+#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF
+
+
+/* -- For CDC_RX_PGA_TIMER */
+#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88)
+#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW"
+#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff
+#define TIMPANI_CDC_RX_PGA_TIMER_S 0
+#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF
+
+
+#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0
+#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF
+
+
+/* -- For CDC_TX_PGA_TIMER */
+#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89)
+#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW"
+#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff
+#define TIMPANI_CDC_TX_PGA_TIMER_S 0
+#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF
+
+
+#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0
+#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF
+
+
+/* -- For CDC_GCTL1 */
+#define TIMPANI_A_CDC_GCTL1 (0x8A)
+#define TIMPANI_CDC_GCTL1_RWC "RW"
+#define TIMPANI_CDC_GCTL1_POR 0x33
+#define TIMPANI_CDC_GCTL1_S 0
+#define TIMPANI_CDC_GCTL1_M 0xFF
+
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1
+
+
+/* -- For CDC_TX1L_STG */
+#define TIMPANI_A_CDC_TX1L_STG (0x8B)
+#define TIMPANI_CDC_TX1L_STG_RWC "RW"
+#define TIMPANI_CDC_TX1L_STG_POR 0xac
+#define TIMPANI_CDC_TX1L_STG_S 0
+#define TIMPANI_CDC_TX1L_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1L_STG_GAIN_S 0
+#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_ST_CTL */
+#define TIMPANI_A_CDC_ST_CTL (0x8C)
+#define TIMPANI_CDC_ST_CTL_RWC "RW"
+#define TIMPANI_CDC_ST_CTL_POR 0x55
+#define TIMPANI_CDC_ST_CTL_S 0
+#define TIMPANI_CDC_ST_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80
+
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40
+
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20
+
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10
+
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8
+
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4
+
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2
+
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1
+
+
+/* -- For CDC_RX1L_DCOFFSET */
+#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D)
+#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_S 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_RX1R_DCOFFSET */
+#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E)
+#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_S 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_BYPASS_CTL1 */
+#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F)
+#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2
+#define TIMPANI_CDC_BYPASS_CTL1_S 0
+#define TIMPANI_CDC_BYPASS_CTL1_M 0xF
+
+
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0
+#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1
+
+
+/* -- For CDC_PDM_CONFIG */
+#define TIMPANI_A_CDC_PDM_CONFIG (0x90)
+#define TIMPANI_CDC_PDM_CONFIG_RWC "RW"
+#define TIMPANI_CDC_PDM_CONFIG_POR 0
+#define TIMPANI_CDC_PDM_CONFIG_S 0
+#define TIMPANI_CDC_PDM_CONFIG_M 0xF
+
+
+#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0
+#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF
+
+
+/* -- For CDC_TESTMODE1 */
+#define TIMPANI_A_CDC_TESTMODE1 (0x91)
+#define TIMPANI_CDC_TESTMODE1_RWC "RW"
+#define TIMPANI_CDC_TESTMODE1_POR 0
+#define TIMPANI_CDC_TESTMODE1_S 0
+#define TIMPANI_CDC_TESTMODE1_M 0x3F
+
+
+#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5
+#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20
+
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10
+
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8
+
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4
+
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2
+
+#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0
+#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1
+
+
+/* -- For CDC_DMIC_CLK_CTL */
+#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92)
+#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_S 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0
+
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0
+
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1
+
+
+/* -- For CDC_ADC12_CLK_CTL */
+#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93)
+#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_S 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0
+
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0
+
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0
+
+
+/* -- For CDC_TX1_CTL */
+#define TIMPANI_A_CDC_TX1_CTL (0x94)
+#define TIMPANI_CDC_TX1_CTL_RWC "RW"
+#define TIMPANI_CDC_TX1_CTL_POR 0x1b
+#define TIMPANI_CDC_TX1_CTL_S 0
+#define TIMPANI_CDC_TX1_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20
+
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0
+
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4
+
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0
+
+
+/* -- For CDC_ADC34_CLK_CTL */
+#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95)
+#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_S 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0
+
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0
+
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0
+
+
+/* -- For CDC_TX2_CTL */
+#define TIMPANI_A_CDC_TX2_CTL (0x96)
+#define TIMPANI_CDC_TX2_CTL_RWC "RW"
+#define TIMPANI_CDC_TX2_CTL_POR 0x1b
+#define TIMPANI_CDC_TX2_CTL_S 0
+#define TIMPANI_CDC_TX2_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20
+
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0
+
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4
+
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0
+
+
+/* -- For CDC_RX1_CLK_CTL */
+#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97)
+#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_S 0
+#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F
+
+
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0
+
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0
+
+
+/* -- For CDC_RX2_CLK_CTL */
+#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98)
+#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_S 0
+#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F
+
+
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0
+
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0
+
+
+/* -- For CDC_DEC_ADC_SEL */
+#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99)
+#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW"
+#define TIMPANI_CDC_DEC_ADC_SEL_POR 0
+#define TIMPANI_CDC_DEC_ADC_SEL_S 0
+#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF
+
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0
+
+
+/* -- For CDC_ANC_INPUT_MUX */
+#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A)
+#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW"
+#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_S 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF
+
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0
+
+
+/* -- For CDC_ANC_RX_CLK_NS_SEL */
+#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B)
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW"
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1
+
+
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1
+
+
+/* -- For CDC_ANC_FB_TUNE_SEL */
+#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C)
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW"
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3
+
+
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0
+
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0
+
+
+/* -- For CLK_DIV_SYNC_CTL */
+#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E)
+#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW"
+#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_S 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3
+
+
+#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1
+#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2
+
+#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1
+
+
+/* -- For CDC_ADC_CLK_EN */
+#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F)
+#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW"
+#define TIMPANI_CDC_ADC_CLK_EN_POR 0
+#define TIMPANI_CDC_ADC_CLK_EN_S 0
+#define TIMPANI_CDC_ADC_CLK_EN_M 0xF
+
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1
+
+
+/* -- For CDC_ST_MIXING */
+#define TIMPANI_A_CDC_ST_MIXING (0xA0)
+#define TIMPANI_CDC_ST_MIXING_RWC "RW"
+#define TIMPANI_CDC_ST_MIXING_POR 0
+#define TIMPANI_CDC_ST_MIXING_S 0
+#define TIMPANI_CDC_ST_MIXING_M 0xF
+
+
+#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3
+#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8
+
+#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2
+#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4
+
+#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1
+#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2
+
+#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0
+#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1
+
+
+/* -- For CDC_RX2_CTL */
+#define TIMPANI_A_CDC_RX2_CTL (0xA1)
+#define TIMPANI_CDC_RX2_CTL_RWC "RW"
+#define TIMPANI_CDC_RX2_CTL_POR 0xc
+#define TIMPANI_CDC_RX2_CTL_S 0
+#define TIMPANI_CDC_RX2_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20
+
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10
+
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0
+
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0
+
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0
+
+
+/* -- For CDC_ARB_CLK_EN */
+#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2)
+#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW"
+#define TIMPANI_CDC_ARB_CLK_EN_POR 0
+#define TIMPANI_CDC_ARB_CLK_EN_S 0
+#define TIMPANI_CDC_ARB_CLK_EN_M 0x1
+
+
+#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0
+#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1
+
+
+/* -- For CDC_I2S_CTL2 */
+#define TIMPANI_A_CDC_I2S_CTL2 (0xA3)
+#define TIMPANI_CDC_I2S_CTL2_RWC "RW"
+#define TIMPANI_CDC_I2S_CTL2_POR 0
+#define TIMPANI_CDC_I2S_CTL2_S 0
+#define TIMPANI_CDC_I2S_CTL2_M 0x3F
+
+
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0
+
+#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2
+#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4
+
+#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1
+#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2
+
+#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0
+#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1
+
+
+/* -- For CDC_RX2LG */
+#define TIMPANI_A_CDC_RX2LG (0xA4)
+#define TIMPANI_CDC_RX2LG_RWC "RW"
+#define TIMPANI_CDC_RX2LG_POR 0xac
+#define TIMPANI_CDC_RX2LG_S 0
+#define TIMPANI_CDC_RX2LG_M 0xFF
+
+
+#define TIMPANI_CDC_RX2LG_GAIN_S 0
+#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF
+
+
+/* -- For CDC_RX2RG */
+#define TIMPANI_A_CDC_RX2RG (0xA5)
+#define TIMPANI_CDC_RX2RG_RWC "RW"
+#define TIMPANI_CDC_RX2RG_POR 0xac
+#define TIMPANI_CDC_RX2RG_S 0
+#define TIMPANI_CDC_RX2RG_M 0xFF
+
+
+#define TIMPANI_CDC_RX2RG_GAIN_S 0
+#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2LG */
+#define TIMPANI_A_CDC_TX2LG (0xA6)
+#define TIMPANI_CDC_TX2LG_RWC "RW"
+#define TIMPANI_CDC_TX2LG_POR 0xac
+#define TIMPANI_CDC_TX2LG_S 0
+#define TIMPANI_CDC_TX2LG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2LG_GAIN_S 0
+#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2RG */
+#define TIMPANI_A_CDC_TX2RG (0xA7)
+#define TIMPANI_CDC_TX2RG_RWC "RW"
+#define TIMPANI_CDC_TX2RG_POR 0xac
+#define TIMPANI_CDC_TX2RG_S 0
+#define TIMPANI_CDC_TX2RG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2RG_GAIN_S 0
+#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF
+
+
+/* -- For CDC_DMIC_MUX */
+#define TIMPANI_A_CDC_DMIC_MUX (0xA8)
+#define TIMPANI_CDC_DMIC_MUX_RWC "RW"
+#define TIMPANI_CDC_DMIC_MUX_POR 0
+#define TIMPANI_CDC_DMIC_MUX_S 0
+#define TIMPANI_CDC_DMIC_MUX_M 0xFF
+
+
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0
+
+
+/* -- For CDC_ARB_CLK_CTL */
+#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9)
+#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ARB_CLK_CTL_POR 0
+#define TIMPANI_CDC_ARB_CLK_CTL_S 0
+#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3
+
+
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3
+
+
+/*  -- For CDC_GCTL2 */
+#define TIMPANI_A_CDC_GCTL2 (0xAA)
+#define TIMPANI_CDC_GCTL2_RWC "RW"
+#define TIMPANI_CDC_GCTL2_POR 0x33
+#define TIMPANI_CDC_GCTL2_S 0
+#define TIMPANI_CDC_GCTL2_M 0xFF
+
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1
+
+
+/* -- For CDC_BYPASS_CTL2 */
+#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB)
+#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D
+#define TIMPANI_CDC_BYPASS_CTL2_S 0
+#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F
+
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1
+
+
+/* -- For CDC_BYPASS_CTL3 */
+#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC)
+#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D
+#define TIMPANI_CDC_BYPASS_CTL3_S 0
+#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F
+
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1
+
+
+/* -- For CDC_BYPASS_CTL4 */
+#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD)
+#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2
+#define TIMPANI_CDC_BYPASS_CTL4_S 0
+#define TIMPANI_CDC_BYPASS_CTL4_M 0xF
+
+
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0
+#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1
+
+
+/* -- For CDC_RX2L_DCOFFSET */
+#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE)
+#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_S 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_RX2R_DCOFFSET */
+#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF)
+#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_S 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_RX_MIX_CTL */
+#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0)
+#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW"
+#define TIMPANI_CDC_RX_MIX_CTL_POR 0
+#define TIMPANI_CDC_RX_MIX_CTL_S 0
+#define TIMPANI_CDC_RX_MIX_CTL_M 0x3
+
+
+#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1
+#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2
+
+#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0
+#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1
+
+
+/* -- For CDC_SPARE_CTL */
+#define TIMPANI_A_CDC_SPARE_CTL (0xB1)
+#define TIMPANI_CDC_SPARE_CTL_RWC "RW"
+#define TIMPANI_CDC_SPARE_CTL_POR 0
+#define TIMPANI_CDC_SPARE_CTL_S 0
+#define TIMPANI_CDC_SPARE_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0
+#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF
+
+
+/* -- For CDC_TESTMODE2 */
+#define TIMPANI_A_CDC_TESTMODE2 (0xB2)
+#define TIMPANI_CDC_TESTMODE2_RWC "RW"
+#define TIMPANI_CDC_TESTMODE2_POR 0
+#define TIMPANI_CDC_TESTMODE2_S 0
+#define TIMPANI_CDC_TESTMODE2_M 0x1F
+
+
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10
+
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8
+
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4
+
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2
+
+#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0
+#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1
+
+
+/* -- For CDC_PDM_OE */
+#define TIMPANI_A_CDC_PDM_OE (0xB3)
+#define TIMPANI_CDC_PDM_OE_RWC "RW"
+#define TIMPANI_CDC_PDM_OE_POR 0
+#define TIMPANI_CDC_PDM_OE_S 0
+#define TIMPANI_CDC_PDM_OE_M 0x3F
+
+
+#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5
+#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20
+
+#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4
+#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10
+
+#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3
+#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8
+
+#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2
+#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4
+
+#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1
+#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2
+
+#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0
+#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1
+
+
+/* -- For CDC_TX1R_STG */
+#define TIMPANI_A_CDC_TX1R_STG (0xB4)
+#define TIMPANI_CDC_TX1R_STG_RWC "RW"
+#define TIMPANI_CDC_TX1R_STG_POR 0xac
+#define TIMPANI_CDC_TX1R_STG_S 0
+#define TIMPANI_CDC_TX1R_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1R_STG_GAIN_S 0
+#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2L_STG */
+#define TIMPANI_A_CDC_TX2L_STG (0xB5)
+#define TIMPANI_CDC_TX2L_STG_RWC "RW"
+#define TIMPANI_CDC_TX2L_STG_POR 0xac
+#define TIMPANI_CDC_TX2L_STG_S 0
+#define TIMPANI_CDC_TX2L_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2L_STG_GAIN_S 0
+#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2R_STG */
+#define TIMPANI_A_CDC_TX2R_STG (0xB6)
+#define TIMPANI_CDC_TX2R_STG_RWC "RW"
+#define TIMPANI_CDC_TX2R_STG_POR 0xac
+#define TIMPANI_CDC_TX2R_STG_S 0
+#define TIMPANI_CDC_TX2R_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2R_STG_GAIN_S 0
+#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_ARB_BYPASS_CTL */
+#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7)
+#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW"
+#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1
+
+
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0
+
+
+/* -- For CDC_ANC1_CTL1 */
+#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0)
+#define TIMPANI_CDC_ANC1_CTL1_RWC "RW"
+#define TIMPANI_CDC_ANC1_CTL1_POR 0
+#define TIMPANI_CDC_ANC1_CTL1_S 0
+#define TIMPANI_CDC_ANC1_CTL1_M 0x3F
+
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0
+
+
+/* -- For CDC_ANC1_CTL2 */
+#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1)
+#define TIMPANI_CDC_ANC1_CTL2_RWC "RW"
+#define TIMPANI_CDC_ANC1_CTL2_POR 0
+#define TIMPANI_CDC_ANC1_CTL2_S 0
+#define TIMPANI_CDC_ANC1_CTL2_M 0x1F
+
+
+#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0
+#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F
+
+
+/* -- For CDC_ANC1_FF_FB_SHIFT */
+#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2)
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW"
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0
+
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF
+
+
+/* -- For CDC_ANC1_RX_NS */
+#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3)
+#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW"
+#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1
+#define TIMPANI_CDC_ANC1_RX_NS_S 0
+#define TIMPANI_CDC_ANC1_RX_NS_M 0x7
+
+
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4
+
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2
+
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1
+
+
+/* -- For CDC_ANC1_SPARE */
+#define TIMPANI_A_CDC_ANC1_SPARE (0xC4)
+#define TIMPANI_CDC_ANC1_SPARE_RWC "RW"
+#define TIMPANI_CDC_ANC1_SPARE_POR 0
+#define TIMPANI_CDC_ANC1_SPARE_S 0
+#define TIMPANI_CDC_ANC1_SPARE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0
+#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF
+
+
+/*  -- For CDC_ANC1_IIR_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F
+
+
+/* -- For CDC_ANC1_IIR_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1
+
+
+/* -- For CDC_ANC1_IIR_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC1_IIR_COEFF_CTL */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0
+
+
+/* -- For CDC_ANC1_LPF_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF
+
+
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF
+
+
+/* -- For CDC_ANC1_LPF_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF
+
+
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF
+
+
+/* -- For CDC_ANC1_LPF_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC1_SCALE_PTR */
+#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC)
+#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7
+
+
+#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7
+
+
+/* -- For CDC_ANC1_SCALE */
+#define TIMPANI_A_CDC_ANC1_SCALE (0xCD)
+#define TIMPANI_CDC_ANC1_SCALE_RWC "RW"
+#define TIMPANI_CDC_ANC1_SCALE_POR 0
+#define TIMPANI_CDC_ANC1_SCALE_S 0
+#define TIMPANI_CDC_ANC1_SCALE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0
+#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF
+
+
+/* -- For CDC_ANC1_DEBUG */
+#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE)
+#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW"
+#define TIMPANI_CDC_ANC1_DEBUG_POR 0
+#define TIMPANI_CDC_ANC1_DEBUG_S 0
+#define TIMPANI_CDC_ANC1_DEBUG_M 0xF
+
+
+#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0
+#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF
+
+
+/* -- For CDC_ANC2_CTL1 */
+#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0)
+#define TIMPANI_CDC_ANC2_CTL1_RWC "RW"
+#define TIMPANI_CDC_ANC2_CTL1_POR 0
+#define TIMPANI_CDC_ANC2_CTL1_S 0
+#define TIMPANI_CDC_ANC2_CTL1_M 0x3F
+
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0
+
+
+/* -- For CDC_ANC2_CTL2 */
+#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1)
+#define TIMPANI_CDC_ANC2_CTL2_RWC "RW"
+#define TIMPANI_CDC_ANC2_CTL2_POR 0
+#define TIMPANI_CDC_ANC2_CTL2_S 0
+#define TIMPANI_CDC_ANC2_CTL2_M 0x1F
+
+
+#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0
+#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F
+
+
+/* -- For CDC_ANC2_FF_FB_SHIFT */
+#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2)
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW"
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0
+
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF
+
+
+/* -- For CDC_ANC2_RX_NS */
+#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3)
+#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW"
+#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1
+#define TIMPANI_CDC_ANC2_RX_NS_S 0
+#define TIMPANI_CDC_ANC2_RX_NS_M 0x7
+
+
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4
+
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2
+
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1
+
+
+/* -- For CDC_ANC2_SPARE */
+#define TIMPANI_A_CDC_ANC2_SPARE (0xD4)
+#define TIMPANI_CDC_ANC2_SPARE_RWC "RW"
+#define TIMPANI_CDC_ANC2_SPARE_POR 0
+#define TIMPANI_CDC_ANC2_SPARE_S 0
+#define TIMPANI_CDC_ANC2_SPARE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0
+#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF
+
+
+/* -- For CDC_ANC2_IIR_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F
+
+
+/* -- For CDC_ANC2_IIR_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1
+
+
+/* -- For CDC_ANC2_IIR_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC2_IIR_COEFF_CTL */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0
+
+
+/* -- For CDC_ANC2_LPF_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF
+
+
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF
+
+
+/* -- For CDC_ANC2_LPF_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF
+
+
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF
+
+
+/* -- For CDC_ANC2_LPF_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC2_SCALE_PTR */
+#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC)
+#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7
+
+
+#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7
+
+
+/* -- For CDC_ANC2_SCALE */
+#define TIMPANI_A_CDC_ANC2_SCALE (0xDD)
+#define TIMPANI_CDC_ANC2_SCALE_RWC "RW"
+#define TIMPANI_CDC_ANC2_SCALE_POR 0
+#define TIMPANI_CDC_ANC2_SCALE_S 0
+#define TIMPANI_CDC_ANC2_SCALE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0
+#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF
+
+
+/* -- For CDC_ANC2_DEBUG */
+#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE)
+#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW"
+#define TIMPANI_CDC_ANC2_DEBUG_POR 0
+#define TIMPANI_CDC_ANC2_DEBUG_S 0
+#define TIMPANI_CDC_ANC2_DEBUG_M 0xF
+
+
+#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0
+#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF
+
+
+/* -- For CDC_LINE_L_AVOL */
+#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0)
+#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW"
+#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac
+#define TIMPANI_CDC_LINE_L_AVOL_S 0
+#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3
+
+
+/* -- For CDC_LINE_R_AVOL */
+#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1)
+#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW"
+#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac
+#define TIMPANI_CDC_LINE_R_AVOL_S 0
+#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3
+
+
+/* -- For CDC_HPH_L_AVOL */
+#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2)
+#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW"
+#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae
+#define TIMPANI_CDC_HPH_L_AVOL_S 0
+#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0
+
+#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1
+
+
+/* -- For CDC_HPH_R_AVOL */
+#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3)
+#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW"
+#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae
+#define TIMPANI_CDC_HPH_R_AVOL_S 0
+#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0
+
+#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1
+
+
+/* -- For CDC_COMP_CTL1 */
+#define TIMPANI_A_CDC_COMP_CTL1 (0xE4)
+#define TIMPANI_CDC_COMP_CTL1_RWC "RW"
+#define TIMPANI_CDC_COMP_CTL1_POR 0
+#define TIMPANI_CDC_COMP_CTL1_S 0
+#define TIMPANI_CDC_COMP_CTL1_M 0xFF
+
+
+#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7
+#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6
+#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40
+
+#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5
+#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4
+#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10
+
+#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3
+#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8
+
+#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2
+#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1
+#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0
+#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1
+
+
+/* -- For CDC_COMP_CTL2 */
+#define TIMPANI_A_CDC_COMP_CTL2 (0xE5)
+#define TIMPANI_CDC_COMP_CTL2_RWC "RW"
+#define TIMPANI_CDC_COMP_CTL2_POR 0xe
+#define TIMPANI_CDC_COMP_CTL2_S 0
+#define TIMPANI_CDC_COMP_CTL2_M 0xF
+
+
+#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2
+#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC
+
+#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0
+#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3
+
+
+/* -- For CDC_COMP_PEAK_METER */
+#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6)
+#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW"
+#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9
+#define TIMPANI_CDC_COMP_PEAK_METER_S 0
+#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF
+
+
+#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0
+#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF
+
+
+/* -- For CDC_COMP_LEVEL_METER_CTL1 */
+#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7)
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW"
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF
+
+
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF
+
+
+/* -- For CDC_COMP_LEVEL_METER_CTL2 */
+#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8)
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW"
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF
+
+
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF
+
+
+/* -- For CDC_COMP_ZONE_SELECT */
+#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9)
+#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW"
+#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b
+#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0
+#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F
+
+
+#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3
+#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78
+
+#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0
+#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7
+
+
+/* -- For CDC_COMP_ZC_MSB */
+#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA)
+#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW"
+#define TIMPANI_CDC_COMP_ZC_MSB_POR 0
+#define TIMPANI_CDC_COMP_ZC_MSB_S 0
+#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7
+
+
+#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0
+#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7
+
+
+/* -- For CDC_COMP_ZC_LSB */
+#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB)
+#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW"
+#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f
+#define TIMPANI_CDC_COMP_ZC_LSB_S 0
+#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0
+#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF
+
+
+/* -- For CDC_COMP_SHUT_DOWN */
+#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC)
+#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW"
+#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b
+#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F
+
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3
+#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7
+
+
+/* -- For CDC_COMP_SHUT_DOWN_STATUS */
+#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED)
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW"
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF
+
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1
+
+
+/* -- For CDC_COMP_HALT */
+#define TIMPANI_A_CDC_COMP_HALT (0xEE)
+#define TIMPANI_CDC_COMP_HALT_RWC "RW"
+#define TIMPANI_CDC_COMP_HALT_POR 0
+#define TIMPANI_CDC_COMP_HALT_S 0
+#define TIMPANI_CDC_COMP_HALT_M 0x1
+
+
+#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0
+#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1
+
+
+#endif
diff --git a/include/linux/mfd/tps65023.h b/include/linux/mfd/tps65023.h
new file mode 100644
index 0000000..4cce091
--- /dev/null
+++ b/include/linux/mfd/tps65023.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_I2C_TPS65023_H
+#define __LINUX_I2C_TPS65023_H
+
+#ifndef CONFIG_TPS65023
+/* Set the output voltage for the DCDC1 convertor */
+#define tps65023_set_dcdc1_level(mvolts)  (-ENODEV)
+
+/* Read the output voltage from the DCDC1 convertor */
+#define tps65023_get_dcdc1_level(mvolts)  (-ENODEV)
+
+#else
+/* Set the output voltage for the DCDC1 convertor */
+extern int tps65023_set_dcdc1_level(int mvolts);
+
+/* Read the output voltage from the DCDC1 convertor */
+extern int tps65023_get_dcdc1_level(int *mvolts);
+#endif
+
+#endif
diff --git a/include/linux/mfd/wcd9310/core.h b/include/linux/mfd/wcd9310/core.h
new file mode 100644
index 0000000..2d03c95
--- /dev/null
+++ b/include/linux/mfd/wcd9310/core.h
@@ -0,0 +1,115 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MFD_TABLA_CORE_H__
+#define __MFD_TABLA_CORE_H__
+
+#include <linux/interrupt.h>
+
+#define TABLA_NUM_IRQ_REGS 3
+
+#define TABLA_SLIM_NUM_PORT_REG 3
+
+enum {
+	TABLA_IRQ_SLIMBUS = 0,
+	TABLA_IRQ_MBHC_REMOVAL,
+	TABLA_IRQ_MBHC_SHORT_TERM,
+	TABLA_IRQ_MBHC_PRESS,
+	TABLA_IRQ_MBHC_RELEASE,
+	TABLA_IRQ_MBHC_POTENTIAL,
+	TABLA_IRQ_MBHC_INSERTION,
+	TABLA_IRQ_BG_PRECHARGE,
+	TABLA_IRQ_PA1_STARTUP,
+	TABLA_IRQ_PA2_STARTUP,
+	TABLA_IRQ_PA3_STARTUP,
+	TABLA_IRQ_PA4_STARTUP,
+	TABLA_IRQ_PA5_STARTUP,
+	TABLA_IRQ_MICBIAS1_PRECHARGE,
+	TABLA_IRQ_MICBIAS2_PRECHARGE,
+	TABLA_IRQ_MICBIAS3_PRECHARGE,
+	TABLA_IRQ_HPH_PA_OCPL_FAULT,
+	TABLA_IRQ_HPH_PA_OCPR_FAULT,
+	TABLA_IRQ_EAR_PA_OCPL_FAULT,
+	TABLA_IRQ_HPH_L_PA_STARTUP,
+	TABLA_IRQ_HPH_R_PA_STARTUP,
+	TABLA_IRQ_EAR_PA_STARTUP,
+	TABLA_NUM_IRQS,
+};
+
+struct tabla {
+	struct device *dev;
+	struct slim_device *slim;
+	struct slim_device *slim_slave;
+	struct mutex io_lock;
+	struct mutex xfer_lock;
+	struct mutex irq_lock;
+
+	unsigned int irq_base;
+	unsigned int irq;
+	u8 irq_masks_cur[TABLA_NUM_IRQ_REGS];
+	u8 irq_masks_cache[TABLA_NUM_IRQ_REGS];
+	u8 irq_level[TABLA_NUM_IRQ_REGS];
+
+	int reset_gpio;
+
+	int (*read_dev)(struct tabla *tabla, unsigned short reg,
+			int bytes, void *dest, bool interface_reg);
+	int (*write_dev)(struct tabla *tabla, unsigned short reg,
+			 int bytes, void *src, bool interface_reg);
+
+	struct regulator_bulk_data *supplies;
+};
+
+int tabla_reg_read(struct tabla *tabla, unsigned short reg);
+int tabla_reg_write(struct tabla *tabla, unsigned short reg,
+		u8 val);
+int tabla_interface_reg_read(struct tabla *tabla, unsigned short reg);
+int tabla_interface_reg_write(struct tabla *tabla, unsigned short reg,
+		u8 val);
+int tabla_bulk_read(struct tabla *tabla, unsigned short reg,
+			int count, u8 *buf);
+int tabla_bulk_write(struct tabla *tabla, unsigned short reg,
+			int count, u8 *buf);
+int tabla_irq_init(struct tabla *tabla);
+void tabla_irq_exit(struct tabla *tabla);
+int tabla_get_logical_addresses(u8 *pgd_la, u8 *inf_la);
+
+static inline int tabla_request_irq(struct tabla *tabla, int irq,
+				     irq_handler_t handler, const char *name,
+				     void *data)
+{
+	if (!tabla->irq_base)
+		return -EINVAL;
+	return request_threaded_irq(tabla->irq_base + irq, NULL, handler,
+				    IRQF_TRIGGER_RISING, name,
+				    data);
+}
+static inline void tabla_free_irq(struct tabla *tabla, int irq, void *data)
+{
+	if (!tabla->irq_base)
+		return;
+	free_irq(tabla->irq_base + irq, data);
+}
+static inline void tabla_enable_irq(struct tabla *tabla, int irq)
+{
+	if (!tabla->irq_base)
+		return;
+	enable_irq(tabla->irq_base + irq);
+}
+static inline void tabla_disable_irq(struct tabla *tabla, int irq)
+{
+	if (!tabla->irq_base)
+		return;
+	disable_irq_nosync(tabla->irq_base + irq);
+}
+
+#endif
diff --git a/include/linux/mfd/wcd9310/pdata.h b/include/linux/mfd/wcd9310/pdata.h
new file mode 100644
index 0000000..f8f7912
--- /dev/null
+++ b/include/linux/mfd/wcd9310/pdata.h
@@ -0,0 +1,27 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MFD_TABLA_PDATA_H__
+
+#define __MFD_TABLA_PDATA_H__
+
+#include <linux/slimbus/slimbus.h>
+
+struct tabla_pdata {
+	int irq;
+	int irq_base;
+	int num_irqs;
+	int reset_gpio;
+	struct slim_device slimbus_slave_device;
+};
+
+#endif
diff --git a/include/linux/mfd/wcd9310/registers.h b/include/linux/mfd/wcd9310/registers.h
new file mode 100644
index 0000000..364f0a7
--- /dev/null
+++ b/include/linux/mfd/wcd9310/registers.h
@@ -0,0 +1,1013 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef TABLA_CODEC_DIGITAL_H
+
+#define TABLA_CODEC_DIGITAL_H
+
+#define TABLA_A_CHIP_CTL			(0x00)
+#define TABLA_A_CHIP_CTL__POR			(0x00000000)
+#define TABLA_A_CHIP_STATUS			(0x01)
+#define TABLA_A_CHIP_STATUS__POR			(0x00000000)
+#define TABLA_A_CHIP_ID_BYTE_0			(0x04)
+#define TABLA_A_CHIP_ID_BYTE_0__POR			(0x00000000)
+#define TABLA_A_CHIP_ID_BYTE_1			(0x05)
+#define TABLA_A_CHIP_ID_BYTE_1__POR			(0x00000000)
+#define TABLA_A_CHIP_ID_BYTE_2			(0x06)
+#define TABLA_A_CHIP_ID_BYTE_2__POR			(0x00000000)
+#define TABLA_A_CHIP_ID_BYTE_3			(0x07)
+#define TABLA_A_CHIP_ID_BYTE_3__POR			(0x00000001)
+#define TABLA_A_CHIP_VERSION			(0x08)
+#define TABLA_A_CHIP_VERSION__POR			(0x00000020)
+#define TABLA_A_SB_VERSION			(0x09)
+#define TABLA_A_SB_VERSION__POR			(0x00000010)
+#define TABLA_A_SLAVE_ID_1			(0x0C)
+#define TABLA_A_SLAVE_ID_1__POR			(0x00000077)
+#define TABLA_A_SLAVE_ID_2			(0x0D)
+#define TABLA_A_SLAVE_ID_2__POR			(0x00000066)
+#define TABLA_A_SLAVE_ID_3			(0x0E)
+#define TABLA_A_SLAVE_ID_3__POR			(0x00000055)
+#define TABLA_A_PIN_CTL_OE0			(0x10)
+#define TABLA_A_PIN_CTL_OE0__POR			(0x00000000)
+#define TABLA_A_PIN_CTL_OE1			(0x11)
+#define TABLA_A_PIN_CTL_OE1__POR			(0x00000000)
+#define TABLA_A_PIN_CTL_DATA0			(0x12)
+#define TABLA_A_PIN_CTL_DATA0__POR			(0x00000000)
+#define TABLA_A_PIN_CTL_DATA1			(0x13)
+#define TABLA_A_PIN_CTL_DATA1__POR			(0x00000000)
+#define TABLA_A_HDRIVE_GENERIC			(0x18)
+#define TABLA_A_HDRIVE_GENERIC__POR			(0x00000000)
+#define TABLA_A_HDRIVE_OVERRIDE			(0x19)
+#define TABLA_A_HDRIVE_OVERRIDE__POR			(0x00000008)
+#define TABLA_A_ANA_CSR_WAIT_STATE			(0x20)
+#define TABLA_A_ANA_CSR_WAIT_STATE__POR			(0x00000044)
+#define TABLA_A_PROCESS_MONITOR_CTL0			(0x40)
+#define TABLA_A_PROCESS_MONITOR_CTL0__POR			(0x00000080)
+#define TABLA_A_PROCESS_MONITOR_CTL1			(0x41)
+#define TABLA_A_PROCESS_MONITOR_CTL1__POR			(0x00000000)
+#define TABLA_A_PROCESS_MONITOR_CTL2			(0x42)
+#define TABLA_A_PROCESS_MONITOR_CTL2__POR			(0x00000000)
+#define TABLA_A_PROCESS_MONITOR_CTL3			(0x43)
+#define TABLA_A_PROCESS_MONITOR_CTL3__POR			(0x00000001)
+#define TABLA_A_QFUSE_CTL			(0x48)
+#define TABLA_A_QFUSE_CTL__POR			(0x00000000)
+#define TABLA_A_QFUSE_STATUS			(0x49)
+#define TABLA_A_QFUSE_STATUS__POR			(0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT0			(0x4A)
+#define TABLA_A_QFUSE_DATA_OUT0__POR			(0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT1			(0x4B)
+#define TABLA_A_QFUSE_DATA_OUT1__POR			(0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT2			(0x4C)
+#define TABLA_A_QFUSE_DATA_OUT2__POR			(0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT3			(0x4D)
+#define TABLA_A_QFUSE_DATA_OUT3__POR			(0x00000000)
+#define TABLA_A_CDC_CTL			(0x80)
+#define TABLA_A_CDC_CTL__POR			(0x00000000)
+#define TABLA_A_LEAKAGE_CTL			(0x88)
+#define TABLA_A_LEAKAGE_CTL__POR			(0x00000004)
+#define TABLA_A_INTR_MODE			(0x90)
+#define TABLA_A_INTR_MODE__POR			(0x00000000)
+#define TABLA_A_INTR_MASK0			(0x94)
+#define TABLA_A_INTR_MASK0__POR			(0x000000ff)
+#define TABLA_A_INTR_MASK1			(0x95)
+#define TABLA_A_INTR_MASK1__POR			(0x000000ff)
+#define TABLA_A_INTR_MASK2			(0x96)
+#define TABLA_A_INTR_MASK2__POR			(0x000000ff)
+#define TABLA_A_INTR_STATUS0			(0x98)
+#define TABLA_A_INTR_STATUS0__POR			(0x00000000)
+#define TABLA_A_INTR_STATUS1			(0x99)
+#define TABLA_A_INTR_STATUS1__POR			(0x00000000)
+#define TABLA_A_INTR_STATUS2			(0x9A)
+#define TABLA_A_INTR_STATUS2__POR			(0x00000000)
+#define TABLA_A_INTR_CLEAR0			(0x9C)
+#define TABLA_A_INTR_CLEAR0__POR			(0x00000000)
+#define TABLA_A_INTR_CLEAR1			(0x9D)
+#define TABLA_A_INTR_CLEAR1__POR			(0x00000000)
+#define TABLA_A_INTR_CLEAR2			(0x9E)
+#define TABLA_A_INTR_CLEAR2__POR			(0x00000000)
+#define TABLA_A_INTR_LEVEL0			(0xA0)
+#define TABLA_A_INTR_LEVEL0__POR			(0x00000001)
+#define TABLA_A_INTR_LEVEL1			(0xA1)
+#define TABLA_A_INTR_LEVEL1__POR			(0x00000000)
+#define TABLA_A_INTR_LEVEL2			(0xA2)
+#define TABLA_A_INTR_LEVEL2__POR			(0x00000000)
+#define TABLA_A_INTR_TEST0			(0xA4)
+#define TABLA_A_INTR_TEST0__POR			(0x00000000)
+#define TABLA_A_INTR_TEST1			(0xA5)
+#define TABLA_A_INTR_TEST1__POR			(0x00000000)
+#define TABLA_A_INTR_TEST2			(0xA6)
+#define TABLA_A_INTR_TEST2__POR			(0x00000000)
+#define TABLA_A_INTR_SET0			(0xA8)
+#define TABLA_A_INTR_SET0__POR			(0x00000000)
+#define TABLA_A_INTR_SET1			(0xA9)
+#define TABLA_A_INTR_SET1__POR			(0x00000000)
+#define TABLA_A_INTR_SET2			(0xAA)
+#define TABLA_A_INTR_SET2__POR			(0x00000000)
+#define TABLA_A_CDC_TX_I2S_SCK_MODE			(0xC0)
+#define TABLA_A_CDC_TX_I2S_SCK_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_TX_I2S_WS_MODE			(0xC1)
+#define TABLA_A_CDC_TX_I2S_WS_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_DMIC_DATA0_MODE			(0xC4)
+#define TABLA_A_CDC_DMIC_DATA0_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_DMIC_CLK0_MODE			(0xC5)
+#define TABLA_A_CDC_DMIC_CLK0_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_DMIC_DATA1_MODE			(0xC6)
+#define TABLA_A_CDC_DMIC_DATA1_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_DMIC_CLK1_MODE			(0xC7)
+#define TABLA_A_CDC_DMIC_CLK1_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_RX_I2S_SCK_MODE			(0xC8)
+#define TABLA_A_CDC_RX_I2S_SCK_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_RX_I2S_WS_MODE			(0xC9)
+#define TABLA_A_CDC_RX_I2S_WS_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_DMIC_DATA2_MODE			(0xCA)
+#define TABLA_A_CDC_DMIC_DATA2_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_DMIC_CLK2_MODE			(0xCB)
+#define TABLA_A_CDC_DMIC_CLK2_MODE__POR			(0x00000000)
+#define TABLA_A_CDC_INTR_MODE			(0xCC)
+#define TABLA_A_CDC_INTR_MODE__POR			(0x00000000)
+#define TABLA_A_BIAS_REF_CTL			(0x0100)
+#define TABLA_A_BIAS_REF_CTL__POR			(0x0000001C)
+#define TABLA_A_BIAS_CENTRAL_BG_CTL			(0x0101)
+#define TABLA_A_BIAS_CENTRAL_BG_CTL__POR			(0x00000050)
+#define TABLA_A_BIAS_PRECHRG_CTL			(0x0102)
+#define TABLA_A_BIAS_PRECHRG_CTL__POR			(0x00000007)
+#define TABLA_A_BIAS_CURR_CTL_1			(0x0103)
+#define TABLA_A_BIAS_CURR_CTL_1__POR			(0x00000052)
+#define TABLA_A_BIAS_CURR_CTL_2			(0x0104)
+#define TABLA_A_BIAS_CURR_CTL_2__POR			(0x00000000)
+#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL			(0x0105)
+#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL__POR			(0x00000016)
+#define TABLA_A_BIAS_BG_STATUS			(0x0106)
+#define TABLA_A_BIAS_BG_STATUS__POR			(0x00000000)
+#define TABLA_A_CLK_BUFF_EN1			(0x0108)
+#define TABLA_A_CLK_BUFF_EN1__POR			(0x00000004)
+#define TABLA_A_CLK_BUFF_EN2			(0x0109)
+#define TABLA_A_CLK_BUFF_EN2__POR			(0x00000002)
+#define TABLA_A_LDO_H_MODE_1			(0x0110)
+#define TABLA_A_LDO_H_MODE_1__POR			(0x00000065)
+#define TABLA_A_LDO_H_MODE_2			(0x0111)
+#define TABLA_A_LDO_H_MODE_2__POR			(0x000000A8)
+#define TABLA_A_LDO_H_LOOP_CTL			(0x0112)
+#define TABLA_A_LDO_H_LOOP_CTL__POR			(0x0000006B)
+#define TABLA_A_LDO_H_COMP_1			(0x0113)
+#define TABLA_A_LDO_H_COMP_1__POR			(0x00000084)
+#define TABLA_A_LDO_H_COMP_2			(0x0114)
+#define TABLA_A_LDO_H_COMP_2__POR			(0x000000E0)
+#define TABLA_A_LDO_H_BIAS_1			(0x0115)
+#define TABLA_A_LDO_H_BIAS_1__POR			(0x0000006D)
+#define TABLA_A_LDO_H_BIAS_2			(0x0116)
+#define TABLA_A_LDO_H_BIAS_2__POR			(0x000000A5)
+#define TABLA_A_LDO_H_BIAS_3			(0x0117)
+#define TABLA_A_LDO_H_BIAS_3__POR			(0x00000060)
+#define TABLA_A_LDO_L_MODE_1			(0x0118)
+#define TABLA_A_LDO_L_MODE_1__POR			(0x00000028)
+#define TABLA_A_LDO_L_MODE_2			(0x0119)
+#define TABLA_A_LDO_L_MODE_2__POR			(0x000000A8)
+#define TABLA_A_LDO_L_LOOP_CTL			(0x011A)
+#define TABLA_A_LDO_L_LOOP_CTL__POR			(0x0000006D)
+#define TABLA_A_LDO_L_COMP_1			(0x011B)
+#define TABLA_A_LDO_L_COMP_1__POR			(0x00000031)
+#define TABLA_A_LDO_L_COMP_2			(0x011C)
+#define TABLA_A_LDO_L_COMP_2__POR			(0x000000A0)
+#define TABLA_A_LDO_L_BIAS_1			(0x011D)
+#define TABLA_A_LDO_L_BIAS_1__POR			(0x0000006D)
+#define TABLA_A_LDO_L_BIAS_2			(0x011E)
+#define TABLA_A_LDO_L_BIAS_2__POR			(0x00000065)
+#define TABLA_A_LDO_L_BIAS_3			(0x011F)
+#define TABLA_A_LDO_L_BIAS_3__POR			(0x00000050)
+#define TABLA_A_MICB_CFILT_1_CTL			(0x0128)
+#define TABLA_A_MICB_CFILT_1_CTL__POR			(0x00000040)
+#define TABLA_A_MICB_CFILT_1_VAL			(0x0129)
+#define TABLA_A_MICB_CFILT_1_VAL__POR			(0x00000080)
+#define TABLA_A_MICB_CFILT_1_PRECHRG			(0x012A)
+#define TABLA_A_MICB_CFILT_1_PRECHRG__POR			(0x00000038)
+#define TABLA_A_MICB_1_CTL			(0x012B)
+#define TABLA_A_MICB_1_CTL__POR			(0x00000016)
+#define TABLA_A_MICB_1_INT_RBIAS			(0x012C)
+#define TABLA_A_MICB_1_INT_RBIAS__POR			(0x00000000)
+#define TABLA_A_MICB_1_MBHC			(0x012D)
+#define TABLA_A_MICB_1_MBHC__POR			(0x00000001)
+#define TABLA_A_MICB_CFILT_2_CTL			(0x012E)
+#define TABLA_A_MICB_CFILT_2_CTL__POR			(0x00000040)
+#define TABLA_A_MICB_CFILT_2_VAL			(0x012F)
+#define TABLA_A_MICB_CFILT_2_VAL__POR			(0x00000080)
+#define TABLA_A_MICB_CFILT_2_PRECHRG			(0x0130)
+#define TABLA_A_MICB_CFILT_2_PRECHRG__POR			(0x00000038)
+#define TABLA_A_MICB_2_CTL			(0x0131)
+#define TABLA_A_MICB_2_CTL__POR			(0x00000016)
+#define TABLA_A_MICB_2_INT_RBIAS			(0x0132)
+#define TABLA_A_MICB_2_INT_RBIAS__POR			(0x00000000)
+#define TABLA_A_MICB_2_MBHC			(0x0133)
+#define TABLA_A_MICB_2_MBHC__POR			(0x00000000)
+#define TABLA_A_MICB_CFILT_3_CTL			(0x0134)
+#define TABLA_A_MICB_CFILT_3_CTL__POR			(0x00000040)
+#define TABLA_A_MICB_CFILT_3_VAL			(0x0135)
+#define TABLA_A_MICB_CFILT_3_VAL__POR			(0x00000080)
+#define TABLA_A_MICB_CFILT_3_PRECHRG			(0x0136)
+#define TABLA_A_MICB_CFILT_3_PRECHRG__POR			(0x00000038)
+#define TABLA_A_MICB_3_CTL			(0x0137)
+#define TABLA_A_MICB_3_CTL__POR			(0x00000016)
+#define TABLA_A_MICB_3_INT_RBIAS			(0x0138)
+#define TABLA_A_MICB_3_INT_RBIAS__POR			(0x00000000)
+#define TABLA_A_MICB_3_MBHC			(0x0139)
+#define TABLA_A_MICB_3_MBHC__POR			(0x00000000)
+#define TABLA_A_MICB_4_CTL			(0x013A)
+#define TABLA_A_MICB_4_CTL__POR			(0x00000016)
+#define TABLA_A_MICB_4_INT_RBIAS			(0x013B)
+#define TABLA_A_MICB_4_INT_RBIAS__POR			(0x00000000)
+#define TABLA_A_MICB_4_MBHC			(0x013C)
+#define TABLA_A_MICB_4_MBHC__POR			(0x00000001)
+#define TABLA_A_TX_COM_BIAS			(0x014C)
+#define TABLA_A_TX_COM_BIAS__POR			(0x000000E0)
+#define TABLA_A_MBHC_SCALING_MUX_1			(0x014E)
+#define TABLA_A_MBHC_SCALING_MUX_1__POR			(0x00000000)
+#define TABLA_A_MBHC_SCALING_MUX_2			(0x014F)
+#define TABLA_A_MBHC_SCALING_MUX_2__POR			(0x00000080)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_1			(0x0151)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_1__POR			(0x00000000)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_2			(0x0152)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_2__POR			(0x00000080)
+#define TABLA_A_TX_1_2_EN			(0x0153)
+#define TABLA_A_TX_1_2_EN__POR			(0x00000000)
+#define TABLA_A_TX_1_2_TEST_EN			(0x0154)
+#define TABLA_A_TX_1_2_TEST_EN__POR			(0x000000CC)
+#define TABLA_A_TX_1_2_ADC_CH1			(0x0155)
+#define TABLA_A_TX_1_2_ADC_CH1__POR			(0x00000044)
+#define TABLA_A_TX_1_2_ADC_CH2			(0x0156)
+#define TABLA_A_TX_1_2_ADC_CH2__POR			(0x00000044)
+#define TABLA_A_TX_1_2_ATEST_REFCTRL			(0x0157)
+#define TABLA_A_TX_1_2_ATEST_REFCTRL__POR			(0x00000000)
+#define TABLA_A_TX_1_2_TEST_CTL			(0x0158)
+#define TABLA_A_TX_1_2_TEST_CTL__POR			(0x00000038)
+#define TABLA_A_TX_1_2_TEST_BLOCK_EN			(0x0159)
+#define TABLA_A_TX_1_2_TEST_BLOCK_EN__POR			(0x000000FF)
+#define TABLA_A_TX_1_2_TXFE_CLKDIV			(0x015A)
+#define TABLA_A_TX_1_2_TXFE_CLKDIV__POR			(0x000000EE)
+#define TABLA_A_TX_1_2_SAR_ERR_CH1			(0x015B)
+#define TABLA_A_TX_1_2_SAR_ERR_CH1__POR			(0x00000000)
+#define TABLA_A_TX_1_2_SAR_ERR_CH2			(0x015C)
+#define TABLA_A_TX_1_2_SAR_ERR_CH2__POR			(0x00000000)
+#define TABLA_A_TX_3_4_EN			(0x015D)
+#define TABLA_A_TX_3_4_EN__POR			(0x00000000)
+#define TABLA_A_TX_3_4_TEST_EN			(0x015E)
+#define TABLA_A_TX_3_4_TEST_EN__POR			(0x000000CC)
+#define TABLA_A_TX_3_4_ADC_CH3			(0x015F)
+#define TABLA_A_TX_3_4_ADC_CH3__POR			(0x00000044)
+#define TABLA_A_TX_3_4_ADC_CH4			(0x0160)
+#define TABLA_A_TX_3_4_ADC_CH4__POR			(0x00000044)
+#define TABLA_A_TX_3_4_ATEST_REFCTRL			(0x0161)
+#define TABLA_A_TX_3_4_ATEST_REFCTRL__POR			(0x00000000)
+#define TABLA_A_TX_3_4_TEST_CTL			(0x0162)
+#define TABLA_A_TX_3_4_TEST_CTL__POR			(0x00000038)
+#define TABLA_A_TX_3_4_TEST_BLOCK_EN			(0x0163)
+#define TABLA_A_TX_3_4_TEST_BLOCK_EN__POR			(0x000000FF)
+#define TABLA_A_TX_3_4_TXFE_CKDIV			(0x0164)
+#define TABLA_A_TX_3_4_TXFE_CKDIV__POR			(0x000000EE)
+#define TABLA_A_TX_3_4_SAR_ERR_CH3			(0x0165)
+#define TABLA_A_TX_3_4_SAR_ERR_CH3__POR			(0x00000000)
+#define TABLA_A_TX_3_4_SAR_ERR_CH4			(0x0166)
+#define TABLA_A_TX_3_4_SAR_ERR_CH4__POR			(0x00000000)
+#define TABLA_A_TX_5_6_EN			(0x0167)
+#define TABLA_A_TX_5_6_EN__POR			(0x00000011)
+#define TABLA_A_TX_5_6_TEST_EN			(0x0168)
+#define TABLA_A_TX_5_6_TEST_EN__POR			(0x000000CC)
+#define TABLA_A_TX_5_6_ADC_CH5			(0x0169)
+#define TABLA_A_TX_5_6_ADC_CH5__POR			(0x00000044)
+#define TABLA_A_TX_5_6_ADC_CH6			(0x016A)
+#define TABLA_A_TX_5_6_ADC_CH6__POR			(0x00000044)
+#define TABLA_A_TX_5_6_ATEST_REFCTRL			(0x016B)
+#define TABLA_A_TX_5_6_ATEST_REFCTRL__POR			(0x00000000)
+#define TABLA_A_TX_5_6_TEST_CTL			(0x016C)
+#define TABLA_A_TX_5_6_TEST_CTL__POR			(0x00000038)
+#define TABLA_A_TX_5_6_TEST_BLOCK_EN			(0x016D)
+#define TABLA_A_TX_5_6_TEST_BLOCK_EN__POR			(0x000000FF)
+#define TABLA_A_TX_5_6_TXFE_CKDIV			(0x016E)
+#define TABLA_A_TX_5_6_TXFE_CKDIV__POR			(0x000000EE)
+#define TABLA_A_TX_5_6_SAR_ERR_CH5			(0x016F)
+#define TABLA_A_TX_5_6_SAR_ERR_CH5__POR			(0x00000000)
+#define TABLA_A_TX_5_6_SAR_ERR_CH6			(0x0170)
+#define TABLA_A_TX_5_6_SAR_ERR_CH6__POR			(0x00000000)
+#define TABLA_A_TX_7_MBHC_EN			(0x0171)
+#define TABLA_A_TX_7_MBHC_EN__POR			(0x0000000C)
+#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL			(0x0172)
+#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL__POR			(0x00000000)
+#define TABLA_A_TX_7_MBHC_ADC			(0x0173)
+#define TABLA_A_TX_7_MBHC_ADC__POR			(0x00000044)
+#define TABLA_A_TX_7_MBHC_TEST_CTL			(0x0174)
+#define TABLA_A_TX_7_MBHC_TEST_CTL__POR			(0x00000038)
+#define TABLA_A_TX_7_MBHC_SAR_ERR			(0x0175)
+#define TABLA_A_TX_7_MBHC_SAR_ERR__POR			(0x00000000)
+#define TABLA_A_TX_7_TXFE_CLKDIV			(0x0176)
+#define TABLA_A_TX_7_TXFE_CLKDIV__POR			(0x0000001C)
+#define TABLA_A_AUX_COM_CTL			(0x0180)
+#define TABLA_A_AUX_COM_CTL__POR			(0x00000034)
+#define TABLA_A_AUX_COM_ATEST			(0x0181)
+#define TABLA_A_AUX_COM_ATEST__POR			(0x00000000)
+#define TABLA_A_AUX_L_EN			(0x0182)
+#define TABLA_A_AUX_L_EN__POR			(0x00000000)
+#define TABLA_A_AUX_L_GAIN			(0x0183)
+#define TABLA_A_AUX_L_GAIN__POR			(0x0000001F)
+#define TABLA_A_AUX_L_PA_CONN			(0x0184)
+#define TABLA_A_AUX_L_PA_CONN__POR			(0x00000000)
+#define TABLA_A_AUX_L_PA_CONN_INV			(0x0185)
+#define TABLA_A_AUX_L_PA_CONN_INV__POR			(0x00000000)
+#define TABLA_A_AUX_R_EN			(0x0186)
+#define TABLA_A_AUX_R_EN__POR			(0x00000000)
+#define TABLA_A_AUX_R_GAIN			(0x0187)
+#define TABLA_A_AUX_R_GAIN__POR			(0x0000001F)
+#define TABLA_A_AUX_R_PA_CONN			(0x0188)
+#define TABLA_A_AUX_R_PA_CONN__POR			(0x00000000)
+#define TABLA_A_AUX_R_PA_CONN_INV			(0x0189)
+#define TABLA_A_AUX_R_PA_CONN_INV__POR			(0x00000000)
+#define TABLA_A_CP_EN			(0x0192)
+#define TABLA_A_CP_EN__POR			(0x000000E6)
+#define TABLA_A_CP_CLK			(0x0193)
+#define TABLA_A_CP_CLK__POR			(0x00000029)
+#define TABLA_A_CP_STATIC			(0x0194)
+#define TABLA_A_CP_STATIC__POR			(0x00000010)
+#define TABLA_A_CP_DCC1			(0x0195)
+#define TABLA_A_CP_DCC1__POR			(0x00000052)
+#define TABLA_A_CP_DCC3			(0x0196)
+#define TABLA_A_CP_DCC3__POR			(0x00000001)
+#define TABLA_A_CP_ATEST			(0x0197)
+#define TABLA_A_CP_ATEST__POR			(0x00000000)
+#define TABLA_A_CP_DTEST			(0x0198)
+#define TABLA_A_CP_DTEST__POR			(0x00000000)
+#define TABLA_A_RX_COM_TIMER_DIV			(0x019E)
+#define TABLA_A_RX_COM_TIMER_DIV__POR			(0x000000E8)
+#define TABLA_A_RX_COM_OCP_CTL			(0x019F)
+#define TABLA_A_RX_COM_OCP_CTL__POR			(0x0000001F)
+#define TABLA_A_RX_COM_OCP_COUNT			(0x01A0)
+#define TABLA_A_RX_COM_OCP_COUNT__POR			(0x00000077)
+#define TABLA_A_RX_COM_DAC_CTL			(0x01A1)
+#define TABLA_A_RX_COM_DAC_CTL__POR			(0x00000000)
+#define TABLA_A_RX_COM_BIAS			(0x01A2)
+#define TABLA_A_RX_COM_BIAS__POR			(0x00000000)
+#define TABLA_A_RX_HPH_BIAS_PA			(0x01A6)
+#define TABLA_A_RX_HPH_BIAS_PA__POR			(0x000000AA)
+#define TABLA_A_RX_HPH_BIAS_LDO			(0x01A7)
+#define TABLA_A_RX_HPH_BIAS_LDO__POR			(0x00000086)
+#define TABLA_A_RX_HPH_BIAS_CNP			(0x01A8)
+#define TABLA_A_RX_HPH_BIAS_CNP__POR			(0x0000008A)
+#define TABLA_A_RX_HPH_BIAS_WG			(0x01A9)
+#define TABLA_A_RX_HPH_BIAS_WG__POR			(0x00000060)
+#define TABLA_A_RX_HPH_OCP_CTL			(0x01AA)
+#define TABLA_A_RX_HPH_OCP_CTL__POR			(0x000000E8)
+#define TABLA_A_RX_HPH_CNP_EN			(0x01AB)
+#define TABLA_A_RX_HPH_CNP_EN__POR			(0x00000080)
+#define TABLA_A_RX_HPH_CNP_WG_CTL			(0x01AC)
+#define TABLA_A_RX_HPH_CNP_WG_CTL__POR			(0x000000DC)
+#define TABLA_A_RX_HPH_CNP_WG_TIME			(0x01AD)
+#define TABLA_A_RX_HPH_CNP_WG_TIME__POR			(0x00000028)
+#define TABLA_A_RX_HPH_L_GAIN			(0x01AE)
+#define TABLA_A_RX_HPH_L_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_HPH_L_TEST			(0x01AF)
+#define TABLA_A_RX_HPH_L_TEST__POR			(0x00000001)
+#define TABLA_A_RX_HPH_L_PA_CTL			(0x01B0)
+#define TABLA_A_RX_HPH_L_PA_CTL__POR			(0x00000040)
+#define TABLA_A_RX_HPH_L_DAC_CTL			(0x01B1)
+#define TABLA_A_RX_HPH_L_DAC_CTL__POR			(0x00000000)
+#define TABLA_A_RX_HPH_L_ATEST			(0x01B2)
+#define TABLA_A_RX_HPH_L_ATEST__POR			(0x00000000)
+#define TABLA_A_RX_HPH_L_STATUS			(0x01B3)
+#define TABLA_A_RX_HPH_L_STATUS__POR			(0x00000004)
+#define TABLA_A_RX_HPH_R_GAIN			(0x01B4)
+#define TABLA_A_RX_HPH_R_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_HPH_R_TEST			(0x01B5)
+#define TABLA_A_RX_HPH_R_TEST__POR			(0x00000001)
+#define TABLA_A_RX_HPH_R_PA_CTL			(0x01B6)
+#define TABLA_A_RX_HPH_R_PA_CTL__POR			(0x00000040)
+#define TABLA_A_RX_HPH_R_DAC_CTL			(0x01B7)
+#define TABLA_A_RX_HPH_R_DAC_CTL__POR			(0x00000000)
+#define TABLA_A_RX_HPH_R_ATEST			(0x01B8)
+#define TABLA_A_RX_HPH_R_ATEST__POR			(0x00000000)
+#define TABLA_A_RX_HPH_R_STATUS			(0x01B9)
+#define TABLA_A_RX_HPH_R_STATUS__POR			(0x00000004)
+#define TABLA_A_RX_EAR_BIAS_PA			(0x01BA)
+#define TABLA_A_RX_EAR_BIAS_PA__POR			(0x000000AA)
+#define TABLA_A_RX_EAR_BIAS_CMBUFF			(0x01BB)
+#define TABLA_A_RX_EAR_BIAS_CMBUFF__POR			(0x000000A0)
+#define TABLA_A_RX_EAR_EN			(0x01BC)
+#define TABLA_A_RX_EAR_EN__POR			(0x00000000)
+#define TABLA_A_RX_EAR_GAIN			(0x01BD)
+#define TABLA_A_RX_EAR_GAIN__POR			(0x00000008)
+#define TABLA_A_RX_EAR_CMBUFF			(0x01BE)
+#define TABLA_A_RX_EAR_CMBUFF__POR			(0x00000000)
+#define TABLA_A_RX_EAR_ICTL			(0x01BF)
+#define TABLA_A_RX_EAR_ICTL__POR			(0x00000040)
+#define TABLA_A_RX_EAR_CCOMP			(0x01C0)
+#define TABLA_A_RX_EAR_CCOMP__POR			(0x00000008)
+#define TABLA_A_RX_EAR_VCM			(0x01C1)
+#define TABLA_A_RX_EAR_VCM__POR			(0x00000000)
+#define TABLA_A_RX_EAR_CNP			(0x01C2)
+#define TABLA_A_RX_EAR_CNP__POR			(0x00000080)
+#define TABLA_A_RX_EAR_ATEST			(0x01C3)
+#define TABLA_A_RX_EAR_ATEST__POR			(0x00000000)
+#define TABLA_A_RX_EAR_STATUS			(0x01C5)
+#define TABLA_A_RX_EAR_STATUS__POR			(0x00000004)
+#define TABLA_A_RX_LINE_BIAS_PA			(0x01C6)
+#define TABLA_A_RX_LINE_BIAS_PA__POR			(0x000000AA)
+#define TABLA_A_RX_LINE_BIAS_DAC			(0x01C7)
+#define TABLA_A_RX_LINE_BIAS_DAC__POR			(0x000000A0)
+#define TABLA_A_RX_LINE_BIAS_CNP			(0x01C8)
+#define TABLA_A_RX_LINE_BIAS_CNP__POR			(0x0000003A)
+#define TABLA_A_RX_LINE_COM			(0x01C9)
+#define TABLA_A_RX_LINE_COM__POR			(0x00000000)
+#define TABLA_A_RX_LINE_CNP_EN			(0x01CA)
+#define TABLA_A_RX_LINE_CNP_EN__POR			(0x00000080)
+#define TABLA_A_RX_LINE_CNP_WG_CTL			(0x01CB)
+#define TABLA_A_RX_LINE_CNP_WG_CTL__POR			(0x0000001C)
+#define TABLA_A_RX_LINE_CNP_WG_TIME			(0x01CC)
+#define TABLA_A_RX_LINE_CNP_WG_TIME__POR			(0x00000064)
+#define TABLA_A_RX_LINE_1_GAIN			(0x01CD)
+#define TABLA_A_RX_LINE_1_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_LINE_1_TEST			(0x01CE)
+#define TABLA_A_RX_LINE_1_TEST__POR			(0x00000000)
+#define TABLA_A_RX_LINE_1_DAC_CTL			(0x01CF)
+#define TABLA_A_RX_LINE_1_DAC_CTL__POR			(0x0000000C)
+#define TABLA_A_RX_LINE_1_STATUS			(0x01D0)
+#define TABLA_A_RX_LINE_1_STATUS__POR			(0x00000000)
+#define TABLA_A_RX_LINE_2_GAIN			(0x01D1)
+#define TABLA_A_RX_LINE_2_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_LINE_2_TEST			(0x01D2)
+#define TABLA_A_RX_LINE_2_TEST__POR			(0x00000000)
+#define TABLA_A_RX_LINE_2_DAC_CTL			(0x01D3)
+#define TABLA_A_RX_LINE_2_DAC_CTL__POR			(0x0000000C)
+#define TABLA_A_RX_LINE_2_STATUS			(0x01D4)
+#define TABLA_A_RX_LINE_2_STATUS__POR			(0x00000000)
+#define TABLA_A_RX_LINE_3_GAIN			(0x01D5)
+#define TABLA_A_RX_LINE_3_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_LINE_3_TEST			(0x01D6)
+#define TABLA_A_RX_LINE_3_TEST__POR			(0x00000000)
+#define TABLA_A_RX_LINE_3_DAC_CTL			(0x01D7)
+#define TABLA_A_RX_LINE_3_DAC_CTL__POR			(0x0000000C)
+#define TABLA_A_RX_LINE_3_STATUS			(0x01D8)
+#define TABLA_A_RX_LINE_3_STATUS__POR			(0x00000000)
+#define TABLA_A_RX_LINE_4_GAIN			(0x01D9)
+#define TABLA_A_RX_LINE_4_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_LINE_4_TEST			(0x01DA)
+#define TABLA_A_RX_LINE_4_TEST__POR			(0x00000000)
+#define TABLA_A_RX_LINE_4_DAC_CTL			(0x01DB)
+#define TABLA_A_RX_LINE_4_DAC_CTL__POR			(0x0000000C)
+#define TABLA_A_RX_LINE_4_STATUS			(0x01DC)
+#define TABLA_A_RX_LINE_4_STATUS__POR			(0x00000000)
+#define TABLA_A_RX_LINE_5_GAIN			(0x01DD)
+#define TABLA_A_RX_LINE_5_GAIN__POR			(0x00000000)
+#define TABLA_A_RX_LINE_5_TEST			(0x01DE)
+#define TABLA_A_RX_LINE_5_TEST__POR			(0x00000000)
+#define TABLA_A_RX_LINE_5_DAC_CTL			(0x01DF)
+#define TABLA_A_RX_LINE_5_DAC_CTL__POR			(0x0000000C)
+#define TABLA_A_RX_LINE_5_STATUS			(0x01E0)
+#define TABLA_A_RX_LINE_5_STATUS__POR			(0x00000000)
+#define TABLA_A_RX_LINE_CNP_DBG			(0x01EC)
+#define TABLA_A_RX_LINE_CNP_DBG__POR			(0x00000000)
+#define TABLA_A_MBHC_HPH			(0x01ED)
+#define TABLA_A_MBHC_HPH__POR			(0x00000048)
+#define TABLA_A_CONFIG_MODE_FREQ			(0x01F7)
+#define TABLA_A_CONFIG_MODE_FREQ__POR			(0x00000047)
+#define TABLA_A_CONFIG_MODE_TEST			(0x01F8)
+#define TABLA_A_CONFIG_MODE_TEST__POR			(0x0000000A)
+#define TABLA_A_CONFIG_MODE_STATUS			(0x01F9)
+#define TABLA_A_CONFIG_MODE_STATUS__POR			(0x0000001C)
+#define TABLA_A_CONFIG_MODE_TUNER			(0x01FA)
+#define TABLA_A_CONFIG_MODE_TUNER__POR			(0x00000000)
+#define TABLA_A_CDC_TX1_VOL_CTL_TIMER			(0x00000220)
+#define TABLA_A_CDC_TX1_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_TIMER			(0x00000228)
+#define TABLA_A_CDC_TX2_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX3_VOL_CTL_TIMER			(0x00000230)
+#define TABLA_A_CDC_TX3_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_TIMER			(0x00000238)
+#define TABLA_A_CDC_TX4_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX5_VOL_CTL_TIMER			(0x00000240)
+#define TABLA_A_CDC_TX5_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_TIMER			(0x00000248)
+#define TABLA_A_CDC_TX6_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX7_VOL_CTL_TIMER			(0x00000250)
+#define TABLA_A_CDC_TX7_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_TIMER			(0x00000258)
+#define TABLA_A_CDC_TX8_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX9_VOL_CTL_TIMER			(0x00000260)
+#define TABLA_A_CDC_TX9_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_TIMER			(0x00000268)
+#define TABLA_A_CDC_TX10_VOL_CTL_TIMER__POR			(0x00000000)
+#define TABLA_A_CDC_TX1_VOL_CTL_GAIN			(0x00000221)
+#define TABLA_A_CDC_TX1_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_GAIN			(0x00000229)
+#define TABLA_A_CDC_TX2_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX3_VOL_CTL_GAIN			(0x00000231)
+#define TABLA_A_CDC_TX3_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_GAIN			(0x00000239)
+#define TABLA_A_CDC_TX4_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX5_VOL_CTL_GAIN			(0x00000241)
+#define TABLA_A_CDC_TX5_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_GAIN			(0x00000249)
+#define TABLA_A_CDC_TX6_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX7_VOL_CTL_GAIN			(0x00000251)
+#define TABLA_A_CDC_TX7_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_GAIN			(0x00000259)
+#define TABLA_A_CDC_TX8_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX9_VOL_CTL_GAIN			(0x00000261)
+#define TABLA_A_CDC_TX9_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_GAIN			(0x00000269)
+#define TABLA_A_CDC_TX10_VOL_CTL_GAIN__POR			(0x00000000)
+#define TABLA_A_CDC_TX1_VOL_CTL_CFG			(0x00000222)
+#define TABLA_A_CDC_TX1_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_CFG			(0x0000022A)
+#define TABLA_A_CDC_TX2_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX3_VOL_CTL_CFG			(0x00000232)
+#define TABLA_A_CDC_TX3_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_CFG			(0x0000023A)
+#define TABLA_A_CDC_TX4_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX5_VOL_CTL_CFG			(0x00000242)
+#define TABLA_A_CDC_TX5_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_CFG			(0x0000024A)
+#define TABLA_A_CDC_TX6_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX7_VOL_CTL_CFG			(0x00000252)
+#define TABLA_A_CDC_TX7_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_CFG			(0x0000025A)
+#define TABLA_A_CDC_TX8_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX9_VOL_CTL_CFG			(0x00000262)
+#define TABLA_A_CDC_TX9_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_CFG			(0x0000026A)
+#define TABLA_A_CDC_TX10_VOL_CTL_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_TX1_MUX_CTL			(0x00000223)
+#define TABLA_A_CDC_TX1_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX2_MUX_CTL			(0x0000022B)
+#define TABLA_A_CDC_TX2_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX3_MUX_CTL			(0x00000233)
+#define TABLA_A_CDC_TX3_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX4_MUX_CTL			(0x0000023B)
+#define TABLA_A_CDC_TX4_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX5_MUX_CTL			(0x00000243)
+#define TABLA_A_CDC_TX5_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX6_MUX_CTL			(0x0000024B)
+#define TABLA_A_CDC_TX6_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX7_MUX_CTL			(0x00000253)
+#define TABLA_A_CDC_TX7_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX8_MUX_CTL			(0x0000025B)
+#define TABLA_A_CDC_TX8_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX9_MUX_CTL			(0x00000263)
+#define TABLA_A_CDC_TX9_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX10_MUX_CTL			(0x0000026B)
+#define TABLA_A_CDC_TX10_MUX_CTL__POR			(0x00000008)
+#define TABLA_A_CDC_TX1_CLK_FS_CTL			(0x00000224)
+#define TABLA_A_CDC_TX1_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX2_CLK_FS_CTL			(0x0000022C)
+#define TABLA_A_CDC_TX2_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX3_CLK_FS_CTL			(0x00000234)
+#define TABLA_A_CDC_TX3_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX4_CLK_FS_CTL			(0x0000023C)
+#define TABLA_A_CDC_TX4_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX5_CLK_FS_CTL			(0x00000244)
+#define TABLA_A_CDC_TX5_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX6_CLK_FS_CTL			(0x0000024C)
+#define TABLA_A_CDC_TX6_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX7_CLK_FS_CTL			(0x00000254)
+#define TABLA_A_CDC_TX7_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX8_CLK_FS_CTL			(0x0000025C)
+#define TABLA_A_CDC_TX8_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX9_CLK_FS_CTL			(0x00000264)
+#define TABLA_A_CDC_TX9_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX10_CLK_FS_CTL			(0x0000026C)
+#define TABLA_A_CDC_TX10_CLK_FS_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_TX1_DMIC_CTL			(0x00000225)
+#define TABLA_A_CDC_TX1_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX2_DMIC_CTL			(0x0000022D)
+#define TABLA_A_CDC_TX2_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX3_DMIC_CTL			(0x00000235)
+#define TABLA_A_CDC_TX3_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX4_DMIC_CTL			(0x0000023D)
+#define TABLA_A_CDC_TX4_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX5_DMIC_CTL			(0x00000245)
+#define TABLA_A_CDC_TX5_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX6_DMIC_CTL			(0x0000024D)
+#define TABLA_A_CDC_TX6_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX7_DMIC_CTL			(0x00000255)
+#define TABLA_A_CDC_TX7_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX8_DMIC_CTL			(0x0000025D)
+#define TABLA_A_CDC_TX8_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX9_DMIC_CTL			(0x00000265)
+#define TABLA_A_CDC_TX9_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TX10_DMIC_CTL			(0x0000026D)
+#define TABLA_A_CDC_TX10_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_SRC1_PDA_CFG			(0x000002A0)
+#define TABLA_A_CDC_SRC1_PDA_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_SRC2_PDA_CFG			(0x000002A8)
+#define TABLA_A_CDC_SRC2_PDA_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_SRC1_FS_CTL			(0x000002A1)
+#define TABLA_A_CDC_SRC1_FS_CTL__POR			(0x0000001b)
+#define TABLA_A_CDC_SRC2_FS_CTL			(0x000002A9)
+#define TABLA_A_CDC_SRC2_FS_CTL__POR			(0x0000001b)
+#define TABLA_A_CDC_RX1_B1_CTL			(0x000002B0)
+#define TABLA_A_CDC_RX1_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_B1_CTL			(0x000002B8)
+#define TABLA_A_CDC_RX2_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_B1_CTL			(0x000002C0)
+#define TABLA_A_CDC_RX3_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_B1_CTL			(0x000002C8)
+#define TABLA_A_CDC_RX4_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_B1_CTL			(0x000002D0)
+#define TABLA_A_CDC_RX5_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_B1_CTL			(0x000002D8)
+#define TABLA_A_CDC_RX6_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_B1_CTL			(0x000002E0)
+#define TABLA_A_CDC_RX7_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX1_B2_CTL			(0x000002B1)
+#define TABLA_A_CDC_RX1_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_B2_CTL			(0x000002B9)
+#define TABLA_A_CDC_RX2_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_B2_CTL			(0x000002C1)
+#define TABLA_A_CDC_RX3_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_B2_CTL			(0x000002C9)
+#define TABLA_A_CDC_RX4_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_B2_CTL			(0x000002D1)
+#define TABLA_A_CDC_RX5_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_B2_CTL			(0x000002D9)
+#define TABLA_A_CDC_RX6_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_B2_CTL			(0x000002E1)
+#define TABLA_A_CDC_RX7_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX1_B3_CTL			(0x000002B2)
+#define TABLA_A_CDC_RX1_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_B3_CTL			(0x000002BA)
+#define TABLA_A_CDC_RX2_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_B3_CTL			(0x000002C2)
+#define TABLA_A_CDC_RX3_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_B3_CTL			(0x000002CA)
+#define TABLA_A_CDC_RX4_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_B3_CTL			(0x000002D2)
+#define TABLA_A_CDC_RX5_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_B3_CTL			(0x000002DA)
+#define TABLA_A_CDC_RX6_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_B3_CTL			(0x000002E2)
+#define TABLA_A_CDC_RX7_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX1_B4_CTL			(0x000002B3)
+#define TABLA_A_CDC_RX1_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_B4_CTL			(0x000002BB)
+#define TABLA_A_CDC_RX2_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_B4_CTL			(0x000002C3)
+#define TABLA_A_CDC_RX3_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_B4_CTL			(0x000002CB)
+#define TABLA_A_CDC_RX4_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_B4_CTL			(0x000002D3)
+#define TABLA_A_CDC_RX5_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_B4_CTL			(0x000002DB)
+#define TABLA_A_CDC_RX6_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_B4_CTL			(0x000002E3)
+#define TABLA_A_CDC_RX7_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX1_B5_CTL			(0x000002B4)
+#define TABLA_A_CDC_RX1_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX2_B5_CTL			(0x000002BC)
+#define TABLA_A_CDC_RX2_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX3_B5_CTL			(0x000002C4)
+#define TABLA_A_CDC_RX3_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX4_B5_CTL			(0x000002CC)
+#define TABLA_A_CDC_RX4_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX5_B5_CTL			(0x000002D4)
+#define TABLA_A_CDC_RX5_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX6_B5_CTL			(0x000002DC)
+#define TABLA_A_CDC_RX6_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX7_B5_CTL			(0x000002E4)
+#define TABLA_A_CDC_RX7_B5_CTL__POR			(0x00000060)
+#define TABLA_A_CDC_RX1_B6_CTL			(0x000002B5)
+#define TABLA_A_CDC_RX1_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_B6_CTL			(0x000002BD)
+#define TABLA_A_CDC_RX2_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_B6_CTL			(0x000002C5)
+#define TABLA_A_CDC_RX3_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_B6_CTL			(0x000002CD)
+#define TABLA_A_CDC_RX4_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_B6_CTL			(0x000002D5)
+#define TABLA_A_CDC_RX5_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_B6_CTL			(0x000002DD)
+#define TABLA_A_CDC_RX6_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_B6_CTL			(0x000002E5)
+#define TABLA_A_CDC_RX7_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL			(0x000002B6)
+#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL			(0x000002BE)
+#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL			(0x000002C6)
+#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL			(0x000002CE)
+#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL			(0x000002D6)
+#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL			(0x000002DE)
+#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL			(0x000002E6)
+#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL			(0x000002B7)
+#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL			(0x000002BF)
+#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL			(0x000002C7)
+#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL			(0x000002CF)
+#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL			(0x000002D7)
+#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL			(0x000002DF)
+#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL			(0x000002E7)
+#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_RX_RESET_CTL			(0x00000301)
+#define TABLA_A_CDC_CLK_RX_RESET_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL			(0x00000302)
+#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL			(0x00000303)
+#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_DMIC_CTL			(0x00000304)
+#define TABLA_A_CDC_CLK_DMIC_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_RX_I2S_CTL			(0x00000305)
+#define TABLA_A_CDC_CLK_RX_I2S_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_CLK_TX_I2S_CTL			(0x00000306)
+#define TABLA_A_CDC_CLK_TX_I2S_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_CLK_OTHR_RESET_CTL			(0x00000307)
+#define TABLA_A_CDC_CLK_OTHR_RESET_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL			(0x00000308)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL			(0x00000309)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_OTHR_CTL			(0x0000030A)
+#define TABLA_A_CDC_CLK_OTHR_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL			(0x0000030B)
+#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_RX_B1_CTL			(0x0000030D)
+#define TABLA_A_CDC_CLK_RX_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_RX_B2_CTL			(0x0000030E)
+#define TABLA_A_CDC_CLK_RX_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_MCLK_CTL			(0x0000030F)
+#define TABLA_A_CDC_CLK_MCLK_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_PDM_CTL			(0x00000310)
+#define TABLA_A_CDC_CLK_PDM_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLK_SD_CTL			(0x00000311)
+#define TABLA_A_CDC_CLK_SD_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL			(0x00000320)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR		(0x00000007)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL			(0x00000321)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR		(0x00000013)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL			(0x00000322)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR		(0x00000053)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL			(0x00000323)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR		(0x0000007f)
+#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL			(0x00000324)
+#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL__POR			(0x00000026)
+#define TABLA_A_CDC_CLSG_TIMER_B1_CFG			(0x00000325)
+#define TABLA_A_CDC_CLSG_TIMER_B1_CFG__POR			(0x0000000a)
+#define TABLA_A_CDC_CLSG_TIMER_B2_CFG			(0x00000326)
+#define TABLA_A_CDC_CLSG_TIMER_B2_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_CLSG_CTL			(0x00000327)
+#define TABLA_A_CDC_CLSG_CTL__POR			(0x00000013)
+#define TABLA_A_CDC_IIR1_GAIN_B1_CTL			(0x00000340)
+#define TABLA_A_CDC_IIR1_GAIN_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B1_CTL			(0x00000350)
+#define TABLA_A_CDC_IIR2_GAIN_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B2_CTL			(0x00000341)
+#define TABLA_A_CDC_IIR1_GAIN_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B2_CTL			(0x00000351)
+#define TABLA_A_CDC_IIR2_GAIN_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B3_CTL			(0x00000342)
+#define TABLA_A_CDC_IIR1_GAIN_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B3_CTL			(0x00000352)
+#define TABLA_A_CDC_IIR2_GAIN_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B4_CTL			(0x00000343)
+#define TABLA_A_CDC_IIR1_GAIN_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B4_CTL			(0x00000353)
+#define TABLA_A_CDC_IIR2_GAIN_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B5_CTL			(0x00000344)
+#define TABLA_A_CDC_IIR1_GAIN_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B5_CTL			(0x00000354)
+#define TABLA_A_CDC_IIR2_GAIN_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B6_CTL			(0x00000345)
+#define TABLA_A_CDC_IIR1_GAIN_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B6_CTL			(0x00000355)
+#define TABLA_A_CDC_IIR2_GAIN_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B7_CTL			(0x00000346)
+#define TABLA_A_CDC_IIR1_GAIN_B7_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B7_CTL			(0x00000356)
+#define TABLA_A_CDC_IIR2_GAIN_B7_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B8_CTL			(0x00000347)
+#define TABLA_A_CDC_IIR1_GAIN_B8_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B8_CTL			(0x00000357)
+#define TABLA_A_CDC_IIR2_GAIN_B8_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_CTL			(0x00000348)
+#define TABLA_A_CDC_IIR1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_CTL			(0x00000358)
+#define TABLA_A_CDC_IIR2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL			(0x00000349)
+#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL			(0x00000359)
+#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B1_CTL			(0x0000034A)
+#define TABLA_A_CDC_IIR1_COEF_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B1_CTL			(0x0000035A)
+#define TABLA_A_CDC_IIR2_COEF_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B2_CTL			(0x0000034B)
+#define TABLA_A_CDC_IIR1_COEF_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B2_CTL			(0x0000035B)
+#define TABLA_A_CDC_IIR2_COEF_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B3_CTL			(0x0000034C)
+#define TABLA_A_CDC_IIR1_COEF_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B3_CTL			(0x0000035C)
+#define TABLA_A_CDC_IIR2_COEF_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B4_CTL			(0x0000034D)
+#define TABLA_A_CDC_IIR1_COEF_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B4_CTL			(0x0000035D)
+#define TABLA_A_CDC_IIR2_COEF_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B5_CTL			(0x0000034E)
+#define TABLA_A_CDC_IIR1_COEF_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B5_CTL			(0x0000035E)
+#define TABLA_A_CDC_IIR2_COEF_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_TOP_GAIN_UPDATE			(0x00000360)
+#define TABLA_A_CDC_TOP_GAIN_UPDATE__POR			(0x00000000)
+#define TABLA_A_CDC_DEBUG_B1_CTL			(0x00000368)
+#define TABLA_A_CDC_DEBUG_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_DEBUG_B2_CTL			(0x00000369)
+#define TABLA_A_CDC_DEBUG_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_DEBUG_B3_CTL			(0x0000036A)
+#define TABLA_A_CDC_DEBUG_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_DEBUG_B4_CTL			(0x0000036B)
+#define TABLA_A_CDC_DEBUG_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_DEBUG_B5_CTL			(0x0000036C)
+#define TABLA_A_CDC_DEBUG_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_DEBUG_B6_CTL			(0x0000036D)
+#define TABLA_A_CDC_DEBUG_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B1_CTL			(0x00000380)
+#define TABLA_A_CDC_CONN_RX1_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B2_CTL			(0x00000381)
+#define TABLA_A_CDC_CONN_RX1_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B3_CTL			(0x00000382)
+#define TABLA_A_CDC_CONN_RX1_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B1_CTL			(0x00000383)
+#define TABLA_A_CDC_CONN_RX2_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B2_CTL			(0x00000384)
+#define TABLA_A_CDC_CONN_RX2_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B3_CTL			(0x00000385)
+#define TABLA_A_CDC_CONN_RX2_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B1_CTL			(0x00000386)
+#define TABLA_A_CDC_CONN_RX3_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B2_CTL			(0x00000387)
+#define TABLA_A_CDC_CONN_RX3_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B3_CTL			(0x00000388)
+#define TABLA_A_CDC_CONN_RX3_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX4_B1_CTL			(0x00000389)
+#define TABLA_A_CDC_CONN_RX4_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX4_B2_CTL			(0x0000038A)
+#define TABLA_A_CDC_CONN_RX4_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX5_B1_CTL			(0x0000038B)
+#define TABLA_A_CDC_CONN_RX5_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX5_B2_CTL			(0x0000038C)
+#define TABLA_A_CDC_CONN_RX5_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX6_B1_CTL			(0x0000038D)
+#define TABLA_A_CDC_CONN_RX6_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX6_B2_CTL			(0x0000038E)
+#define TABLA_A_CDC_CONN_RX6_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX7_B1_CTL			(0x0000038F)
+#define TABLA_A_CDC_CONN_RX7_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX7_B2_CTL			(0x00000390)
+#define TABLA_A_CDC_CONN_RX7_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_B1_CTL			(0x00000393)
+#define TABLA_A_CDC_CONN_TX_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_B2_CTL			(0x00000394)
+#define TABLA_A_CDC_CONN_TX_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_B3_CTL			(0x00000395)
+#define TABLA_A_CDC_CONN_TX_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_B4_CTL			(0x00000396)
+#define TABLA_A_CDC_CONN_TX_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B1_CTL			(0x00000397)
+#define TABLA_A_CDC_CONN_EQ1_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B2_CTL			(0x00000398)
+#define TABLA_A_CDC_CONN_EQ1_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B3_CTL			(0x00000399)
+#define TABLA_A_CDC_CONN_EQ1_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B4_CTL			(0x0000039A)
+#define TABLA_A_CDC_CONN_EQ1_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B1_CTL			(0x0000039B)
+#define TABLA_A_CDC_CONN_EQ2_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B2_CTL			(0x0000039C)
+#define TABLA_A_CDC_CONN_EQ2_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B3_CTL			(0x0000039D)
+#define TABLA_A_CDC_CONN_EQ2_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B4_CTL			(0x0000039E)
+#define TABLA_A_CDC_CONN_EQ2_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_SRC1_B1_CTL			(0x0000039F)
+#define TABLA_A_CDC_CONN_SRC1_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_SRC1_B2_CTL			(0x000003A0)
+#define TABLA_A_CDC_CONN_SRC1_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_SRC2_B1_CTL			(0x000003A1)
+#define TABLA_A_CDC_CONN_SRC2_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_SRC2_B2_CTL			(0x000003A2)
+#define TABLA_A_CDC_CONN_SRC2_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B1_CTL			(0x000003A3)
+#define TABLA_A_CDC_CONN_TX_SB_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B2_CTL			(0x000003A4)
+#define TABLA_A_CDC_CONN_TX_SB_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B3_CTL			(0x000003A5)
+#define TABLA_A_CDC_CONN_TX_SB_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B4_CTL			(0x000003A6)
+#define TABLA_A_CDC_CONN_TX_SB_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B5_CTL			(0x000003A7)
+#define TABLA_A_CDC_CONN_TX_SB_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B6_CTL			(0x000003A8)
+#define TABLA_A_CDC_CONN_TX_SB_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B7_CTL			(0x000003A9)
+#define TABLA_A_CDC_CONN_TX_SB_B7_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B8_CTL			(0x000003AA)
+#define TABLA_A_CDC_CONN_TX_SB_B8_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B9_CTL			(0x000003AB)
+#define TABLA_A_CDC_CONN_TX_SB_B9_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B10_CTL			(0x000003AC)
+#define TABLA_A_CDC_CONN_TX_SB_B10_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B11_CTL			(0x000003AD)
+#define TABLA_A_CDC_CONN_TX_SB_B11_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX_SB_B1_CTL			(0x000003AE)
+#define TABLA_A_CDC_CONN_RX_SB_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_RX_SB_B2_CTL			(0x000003AF)
+#define TABLA_A_CDC_CONN_RX_SB_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_CLSG_CTL			(0x000003B0)
+#define TABLA_A_CDC_CONN_CLSG_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_CONN_SPARE			(0x000003B1)
+#define TABLA_A_CDC_CONN_SPARE__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_EN_CTL			(0x000003C0)
+#define TABLA_A_CDC_MBHC_EN_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG			(0x000003C1)
+#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG			(0x000003C2)
+#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG__POR			(0x00000006)
+#define TABLA_A_CDC_MBHC_TIMER_B1_CTL			(0x000003C3)
+#define TABLA_A_CDC_MBHC_TIMER_B1_CTL__POR			(0x00000003)
+#define TABLA_A_CDC_MBHC_TIMER_B2_CTL			(0x000003C4)
+#define TABLA_A_CDC_MBHC_TIMER_B2_CTL__POR			(0x00000009)
+#define TABLA_A_CDC_MBHC_TIMER_B3_CTL			(0x000003C5)
+#define TABLA_A_CDC_MBHC_TIMER_B3_CTL__POR			(0x0000001e)
+#define TABLA_A_CDC_MBHC_TIMER_B4_CTL			(0x000003C6)
+#define TABLA_A_CDC_MBHC_TIMER_B4_CTL__POR			(0x00000045)
+#define TABLA_A_CDC_MBHC_TIMER_B5_CTL			(0x000003C7)
+#define TABLA_A_CDC_MBHC_TIMER_B5_CTL__POR			(0x00000004)
+#define TABLA_A_CDC_MBHC_TIMER_B6_CTL			(0x000003C8)
+#define TABLA_A_CDC_MBHC_TIMER_B6_CTL__POR			(0x00000078)
+#define TABLA_A_CDC_MBHC_B1_STATUS			(0x000003C9)
+#define TABLA_A_CDC_MBHC_B1_STATUS__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_B2_STATUS			(0x000003CA)
+#define TABLA_A_CDC_MBHC_B2_STATUS__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_B3_STATUS			(0x000003CB)
+#define TABLA_A_CDC_MBHC_B3_STATUS__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_B4_STATUS			(0x000003CC)
+#define TABLA_A_CDC_MBHC_B4_STATUS__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_B5_STATUS			(0x000003CD)
+#define TABLA_A_CDC_MBHC_B5_STATUS__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_B1_CTL			(0x000003CE)
+#define TABLA_A_CDC_MBHC_B1_CTL__POR			(0x000000c0)
+#define TABLA_A_CDC_MBHC_B2_CTL			(0x000003CF)
+#define TABLA_A_CDC_MBHC_B2_CTL__POR			(0x0000005d)
+#define TABLA_A_CDC_MBHC_VOLT_B1_CTL			(0x000003D0)
+#define TABLA_A_CDC_MBHC_VOLT_B1_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B2_CTL			(0x000003D1)
+#define TABLA_A_CDC_MBHC_VOLT_B2_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B3_CTL			(0x000003D2)
+#define TABLA_A_CDC_MBHC_VOLT_B3_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B4_CTL			(0x000003D3)
+#define TABLA_A_CDC_MBHC_VOLT_B4_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B5_CTL			(0x000003D4)
+#define TABLA_A_CDC_MBHC_VOLT_B5_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B6_CTL			(0x000003D5)
+#define TABLA_A_CDC_MBHC_VOLT_B6_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B7_CTL			(0x000003D6)
+#define TABLA_A_CDC_MBHC_VOLT_B7_CTL__POR			(0x000000ff)
+#define TABLA_A_CDC_MBHC_VOLT_B8_CTL			(0x000003D7)
+#define TABLA_A_CDC_MBHC_VOLT_B8_CTL__POR			(0x00000007)
+#define TABLA_A_CDC_MBHC_VOLT_B9_CTL			(0x000003D8)
+#define TABLA_A_CDC_MBHC_VOLT_B9_CTL__POR			(0x000000ff)
+#define TABLA_A_CDC_MBHC_VOLT_B10_CTL			(0x000003D9)
+#define TABLA_A_CDC_MBHC_VOLT_B10_CTL__POR			(0x0000007f)
+#define TABLA_A_CDC_MBHC_VOLT_B11_CTL			(0x000003DA)
+#define TABLA_A_CDC_MBHC_VOLT_B11_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B12_CTL			(0x000003DB)
+#define TABLA_A_CDC_MBHC_VOLT_B12_CTL__POR			(0x00000080)
+#define TABLA_A_CDC_MBHC_CLK_CTL			(0x000003DC)
+#define TABLA_A_CDC_MBHC_CLK_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_INT_CTL			(0x000003DD)
+#define TABLA_A_CDC_MBHC_INT_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_DEBUG_CTL			(0x000003DE)
+#define TABLA_A_CDC_MBHC_DEBUG_CTL__POR			(0x00000000)
+#define TABLA_A_CDC_MBHC_SPARE			(0x000003DF)
+#define TABLA_A_CDC_MBHC_SPARE__POR			(0x00000000)
+
+
+/* SLIMBUS Slave Registers */
+#define TABLA_SLIM_PGD_PORT_INT_EN0                     (0x30)
+#define TABLA_SLIM_PGD_PORT_INT_STATUS0                 (0x34)
+#define TABLA_SLIM_PGD_PORT_INT_CLR0                    (0x38)
+#define TABLA_SLIM_PGD_PORT_INT_SOURCE0			(0x60)
+
+#endif
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 1584b52..fd62a22 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -221,7 +221,6 @@
 	struct work_struct	clk_gate_work; /* delayed clock gate */
 	unsigned int		clk_old;	/* old clock value cache */
 	spinlock_t		clk_lock;	/* lock for clk fields */
-	struct mutex		clk_gate_mutex;	/* mutex for clock gating */
 #endif
 
 	/* host specific block data */
@@ -258,6 +257,7 @@
 
 	wait_queue_head_t	wq;
 	struct task_struct	*claimer;	/* task that has host claimed */
+	struct task_struct	*suspend_task;
 	int			claim_cnt;	/* "claim" nesting count */
 
 	struct delayed_work	detect;
@@ -294,6 +294,20 @@
 	} embedded_sdio_data;
 #endif
 
+#ifdef CONFIG_MMC_PERF_PROFILING
+	struct {
+
+		unsigned long rbytes_mmcq; /* Rd bytes MMC queue */
+		unsigned long wbytes_mmcq; /* Wr bytes MMC queue */
+		unsigned long rbytes_drv;  /* Rd bytes MMC Host  */
+		unsigned long wbytes_drv;  /* Wr bytes MMC Host  */
+		ktime_t rtime_mmcq;	   /* Rd time  MMC queue */
+		ktime_t wtime_mmcq;	   /* Wr time  MMC queue */
+		ktime_t rtime_drv;	   /* Rd time  MMC Host  */
+		ktime_t wtime_drv;	   /* Wr time  MMC Host  */
+		ktime_t start;
+	} perf;
+#endif
 	unsigned long		private[0] ____cacheline_aligned;
 };
 
@@ -376,7 +390,12 @@
 int mmc_host_enable(struct mmc_host *host);
 int mmc_host_disable(struct mmc_host *host);
 int mmc_host_lazy_disable(struct mmc_host *host);
-int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
+#ifdef CONFIG_PM
+int mmc_pm_notify(struct notifier_block *notify_block, unsigned long mode,
+		  void *unused);
+#else
+#define mmc_pm_notify NULL
+#endif
 
 static inline void mmc_set_disable_delay(struct mmc_host *host,
 					 unsigned int disable_delay)
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index ac26a68..e10b278 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -211,6 +211,7 @@
  * OCR bits are mostly in host.h
  */
 #define MMC_CARD_BUSY	0x80000000	/* Card Power up status bit */
+#define MMC_CARD_SECTOR_ADDR 0x40000000 /* Card supports sectors */
 
 /*
  * Card Command Classes (CCC)
diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h
index 245cdac..e376b37 100644
--- a/include/linux/mmc/sdio.h
+++ b/include/linux/mmc/sdio.h
@@ -96,6 +96,7 @@
 
 #define  SDIO_BUS_WIDTH_1BIT	0x00
 #define  SDIO_BUS_WIDTH_4BIT	0x02
+#define  SDIO_BUS_WIDTH_8BIT  	0x03
 #define  SDIO_BUS_ECSI		0x20	/* Enable continuous SPI interrupt */
 #define  SDIO_BUS_SCSI		0x40	/* Support continuous SPI interrupt */
 
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 9f7c3eb..26360cc 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -454,6 +454,12 @@
 	return test_bit(ZONE_OOM_LOCKED, &zone->flags);
 }
 
+#ifdef CONFIG_SMP
+unsigned long zone_nr_free_pages(struct zone *zone);
+#else
+#define zone_nr_free_pages(zone) zone_page_state(zone, NR_FREE_PAGES)
+#endif /* CONFIG_SMP */
+
 /*
  * The "priority" of VM scanning is how much of the queues we will scan in one
  * go. A value of 12 for DEF_PRIORITY implies that we will scan 1/4096th of the
@@ -1089,7 +1095,10 @@
 #define pfn_to_nid(pfn)		(0)
 #endif
 
+#ifndef early_pfn_valid
 #define early_pfn_valid(pfn)	pfn_valid(pfn)
+#endif
+
 void sparse_init(void);
 #else
 #define sparse_init()	do {} while (0)
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index ae28e93..18997d7 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -427,6 +427,15 @@
 			__attribute__((aligned(sizeof(kernel_ulong_t))));
 };
 
+#define SLIMBUS_NAME_SIZE	32
+#define SLIMBUS_MODULE_PREFIX "slim:"
+
+struct slim_device_id {
+	char name[SLIMBUS_NAME_SIZE];
+	kernel_ulong_t driver_data	/* Data private to the driver */
+			__attribute__((aligned(sizeof(kernel_ulong_t))));
+};
+
 /* dmi */
 enum dmi_field {
 	DMI_NONE,
diff --git a/include/linux/msm-charger.h b/include/linux/msm-charger.h
new file mode 100644
index 0000000..1e4d479
--- /dev/null
+++ b/include/linux/msm-charger.h
@@ -0,0 +1,136 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MSM_CHARGER_H__
+#define __MSM_CHARGER_H__
+
+#include <linux/power_supply.h>
+
+enum {
+	CHG_TYPE_USB,
+	CHG_TYPE_AC
+};
+
+enum msm_hardware_charger_event {
+	CHG_INSERTED_EVENT,
+	CHG_ENUMERATED_EVENT,
+	CHG_REMOVED_EVENT,
+	CHG_DONE_EVENT,
+	CHG_BATT_BEGIN_FAST_CHARGING,
+	CHG_BATT_CHG_RESUME,
+	CHG_BATT_TEMP_OUTOFRANGE,
+	CHG_BATT_TEMP_INRANGE,
+	CHG_BATT_INSERTED,
+	CHG_BATT_REMOVED,
+	CHG_BATT_STATUS_CHANGE,
+	CHG_BATT_NEEDS_RECHARGING,
+};
+
+/**
+ * enum hardware_charger_state
+ * @CHG_ABSENT_STATE: charger cable is unplugged
+ * @CHG_PRESENT_STATE: charger cable is plugged but charge current isnt drawn
+ * @CHG_READY_STATE: charger cable is plugged and kernel knows how much current
+ *			it can draw
+ * @CHG_CHARGING_STATE: charger cable is plugged and current is drawn for
+ *			charging
+ */
+enum msm_hardware_charger_state {
+	CHG_ABSENT_STATE,
+	CHG_PRESENT_STATE,
+	CHG_READY_STATE,
+	CHG_CHARGING_STATE,
+};
+
+struct msm_hardware_charger {
+	int type;
+	int rating;
+	const char *name;
+	int (*start_charging) (struct msm_hardware_charger *hw_chg,
+			       int chg_voltage, int chg_current);
+	int (*stop_charging) (struct msm_hardware_charger *hw_chg);
+	int (*charging_switched) (struct msm_hardware_charger *hw_chg);
+
+	void *charger_private;	/* used by the msm_charger.c */
+};
+
+struct msm_battery_gauge {
+	int (*get_battery_mvolts) (void);
+	int (*get_battery_temperature) (void);
+	int (*is_battery_present) (void);
+	int (*is_battery_temp_within_range) (void);
+	int (*is_battery_id_valid) (void);
+	int (*get_battery_status)(void);
+	int (*get_batt_remaining_capacity) (void);
+	int (*monitor_for_recharging) (void);
+};
+/**
+ * struct msm_charger_platform_data
+ * @safety_time: max charging time in minutes
+ * @update_time: how often the userland be updated of the charging progress
+ * @max_voltage: the max voltage the battery should be charged upto
+ * @min_voltage: the voltage where charging method switches from trickle to fast
+ * @get_batt_capacity_percent: a board specific function to return battery
+ *			capacity. Can be null - a default one will be used
+ */
+struct msm_charger_platform_data {
+	unsigned int safety_time;
+	unsigned int update_time;
+	unsigned int max_voltage;
+	unsigned int min_voltage;
+	unsigned int (*get_batt_capacity_percent) (void);
+};
+
+typedef void (*notify_vbus_state) (int);
+#if defined(CONFIG_BATTERY_MSM8X60) || defined(CONFIG_BATTERY_MSM8X60_MODULE)
+void msm_battery_gauge_register(struct msm_battery_gauge *batt_gauge);
+void msm_battery_gauge_unregister(struct msm_battery_gauge *batt_gauge);
+int msm_charger_register(struct msm_hardware_charger *hw_chg);
+int msm_charger_unregister(struct msm_hardware_charger *hw_chg);
+int msm_charger_notify_event(struct msm_hardware_charger *hw_chg,
+			     enum msm_hardware_charger_event event);
+void msm_charger_vbus_draw(unsigned int mA);
+
+int msm_charger_register_vbus_sn(void (*callback)(int));
+void msm_charger_unregister_vbus_sn(void (*callback)(int));
+#else
+static inline void msm_battery_gauge_register(struct msm_battery_gauge *gauge)
+{
+}
+static inline void msm_battery_gauge_unregister(struct msm_battery_gauge *gauge)
+{
+}
+static inline int msm_charger_register(struct msm_hardware_charger *hw_chg)
+{
+	return -ENXIO;
+}
+static inline int msm_charger_unregister(struct msm_hardware_charger *hw_chg)
+{
+	return -ENXIO;
+}
+static inline int msm_charger_notify_event(struct msm_hardware_charger *hw_chg,
+			     enum msm_hardware_charger_event event)
+{
+	return -ENXIO;
+}
+static inline void msm_charger_vbus_draw(unsigned int mA)
+{
+}
+static inline int msm_charger_register_vbus_sn(void (*callback)(int))
+{
+	return -ENXIO;
+}
+static inline void msm_charger_unregister_vbus_sn(void (*callback)(int))
+{
+}
+#endif
+#endif /* __MSM_CHARGER_H__ */
diff --git a/include/linux/msm_adc.h b/include/linux/msm_adc.h
new file mode 100644
index 0000000..b8ab599
--- /dev/null
+++ b/include/linux/msm_adc.h
@@ -0,0 +1,347 @@
+#ifndef __MSM_ADC_H
+#define __MSM_ADC_H
+
+#include <linux/sched.h>
+
+#define MSM_ADC_MAX_CHAN_STR 64
+
+/* must be <= to the max buffer size in the modem implementation */
+#define MSM_ADC_DEV_MAX_INFLIGHT 9
+
+#define MSM_ADC_IOCTL_CODE		0x90
+
+struct msm_adc_conversion {
+	/* hwmon channel number - this is not equivalent to the DAL chan */
+	uint32_t chan;
+	/* returned result in ms */
+	int result;
+};
+
+struct adc_chan_result {
+	/* The channel number of the requesting/requested conversion */
+	uint32_t chan;
+	/* The pre-calibrated digital output of a given ADC relative to the
+	ADC reference */
+	int32_t adc_code;
+	/* in units specific for a given ADC; most ADC uses reference voltage
+	 *  but some ADC uses reference current.  This measurement here is
+	 *  a number relative to a reference of a given ADC */
+	int64_t measurement;
+	/* The data meaningful for each individual channel whether it is
+	 * voltage, current, temperature, etc. */
+	int64_t physical;
+};
+
+/*
+ * Issue a blocking adc conversion request. Once the call returns, the data
+ * can be found in the 'physical' field of adc_chan_result. This call will
+ * return ENODATA if there is an invalid result returned by the modem driver.
+ */
+#define MSM_ADC_REQUEST			_IOWR(MSM_ADC_IOCTL_CODE, 1,	\
+					     struct adc_chan_result)
+
+/*
+ * Issue a non-blocking adc conversion request. The results from this
+ * request can be obtained by calling AIO_READ once the transfer is
+ * completed. To verify completion, the blocking call AIO_POLL can be used.
+ * If there are no slot resources, this call will return an error with errno
+ * set to EWOULDBLOCK.
+ */
+#define MSM_ADC_AIO_REQUEST		_IOWR(MSM_ADC_IOCTL_CODE, 2,	\
+					     struct adc_chan_result)
+
+/*
+ * Same non-blocking semantics as AIO_REQUEST, except this call will block
+ * if there are no available slot resources. This call can fail with errno
+ * set to EDEADLK if there are no resources and the file descriptor in question
+ * has outstanding conversion requests already. This is done so the client
+ * does not block on resources that can only be freed by reading the results --
+ * effectively deadlocking the system. In this case, the client must read
+ * pending results before proceeding to free up resources.
+ */
+#define MSM_ADC_AIO_REQUEST_BLOCK_RES	_IOWR(MSM_ADC_IOCTL_CODE, 3,	\
+					     struct adc_chan_result)
+
+/*
+ * Returns the number of pending results that are associated with a particular
+ * file descriptor. If there are no pending results, this call will block until
+ * there is at least one. If there are no requests queued at all on this file
+ * descriptor, this call will fail with EDEADLK. This is to prevent deadlock in
+ * a single-threaded scenario where POLL would never return.
+ */
+#define MSM_ADC_AIO_POLL		_IOR(MSM_ADC_IOCTL_CODE, 4,	\
+					     uint32_t)
+
+#define MSM_ADC_FLUID_INIT	_IOR(MSM_ADC_IOCTL_CODE, 5,	\
+					     uint32_t)
+
+#define MSM_ADC_FLUID_DEINIT	_IOR(MSM_ADC_IOCTL_CODE, 6,	\
+					     uint32_t)
+
+struct msm_adc_aio_result {
+	uint32_t chan;
+	int result;
+};
+
+/*
+ * Read the results from an AIO / non-blocking conversion request. AIO_POLL
+ * should be used before using this command to verify how many pending requests
+ * are available for the file descriptor. This call will fail with errno set to
+ * ENOMSG if there are no pending messages to be read at the time of the call.
+ * The call will return ENODATA if there is an invalid result returned by the
+ * modem driver.
+ */
+#define MSM_ADC_AIO_READ		_IOR(MSM_ADC_IOCTL_CODE, 5,	\
+					     struct adc_chan_result)
+
+struct msm_adc_lookup {
+	/* channel name (input) */
+	char name[MSM_ADC_MAX_CHAN_STR];
+	/* local channel index (output) */
+	uint32_t chan_idx;
+};
+
+/*
+ * Look up a channel name and get back an index that can be used
+ * as a parameter to the conversion request commands.
+ */
+#define MSM_ADC_LOOKUP			_IOWR(MSM_ADC_IOCTL_CODE, 6,	\
+					     struct msm_adc_lookup)
+
+
+#ifdef __KERNEL__
+#define MSM_ADC_MAX_NUM_DEVS		3
+
+enum {
+	ADC_CONFIG_TYPE1,
+	ADC_CONFIG_TYPE2,
+	ADC_CONFIG_NONE = 0xffffffff
+};
+
+enum {
+	ADC_CALIB_CONFIG_TYPE1,
+	ADC_CALIB_CONFIG_TYPE2,
+	ADC_CALIB_CONFIG_TYPE3,
+	ADC_CALIB_CONFIG_TYPE4,
+	ADC_CALIB_CONFIG_TYPE5,
+	ADC_CALIB_CONFIG_TYPE6,
+	ADC_CALIB_CONFIG_TYPE7,
+	ADC_CALIB_CONFIG_NONE = 0xffffffff
+};
+
+enum {
+	/* CHAN_PATH_TYPEn is specific for each ADC driver
+	and can be used however way it wants*/
+	CHAN_PATH_TYPE1,
+	CHAN_PATH_TYPE2,
+	CHAN_PATH_TYPE3,
+	CHAN_PATH_TYPE4,
+	CHAN_PATH_TYPE5,
+	CHAN_PATH_TYPE6,
+	CHAN_PATH_TYPE7,
+	CHAN_PATH_TYPE8,
+	CHAN_PATH_TYPE9,
+	CHAN_PATH_TYPE10,
+	CHAN_PATH_TYPE11,
+	CHAN_PATH_TYPE12,
+	CHAN_PATH_TYPE13,
+	CHAN_PATH_TYPE14,
+	CHAN_PATH_TYPE15,
+	CHAN_PATH_TYPE16,
+	/* A given channel connects directly to the ADC */
+	CHAN_PATH_TYPE_NONE = 0xffffffff
+};
+
+#define CHANNEL_ADC_BATT_ID     0
+#define CHANNEL_ADC_BATT_THERM  1
+#define CHANNEL_ADC_BATT_AMON   2
+#define CHANNEL_ADC_VBATT       3
+#define CHANNEL_ADC_VCOIN       4
+#define CHANNEL_ADC_VCHG        5
+#define CHANNEL_ADC_CHG_MONITOR 6
+#define CHANNEL_ADC_VPH_PWR     7
+#define CHANNEL_ADC_USB_VBUS    8
+#define CHANNEL_ADC_DIE_TEMP    9
+#define CHANNEL_ADC_DIE_TEMP_4K 0xa
+#define CHANNEL_ADC_XOTHERM     0xb
+#define CHANNEL_ADC_XOTHERM_4K  0xc
+#define CHANNEL_ADC_HDSET       0xd
+#define CHANNEL_ADC_MSM_THERM	0xe
+#define CHANNEL_ADC_625_REF	0xf
+#define CHANNEL_ADC_1250_REF	0x10
+#define CHANNEL_ADC_325_REF	0x11
+#define CHANNEL_ADC_FSM_THERM	0x12
+#define CHANNEL_ADC_PA_THERM	0x13
+
+enum {
+	CALIB_STARTED,
+	CALIB_NOT_REQUIRED = 0xffffffff,
+};
+
+struct linear_graph {
+	int32_t offset;
+	int32_t dy; /* Slope numerator */
+	int32_t dx; /* Slope denominator */
+};
+
+struct adc_map_pt {
+	int32_t x;
+	int32_t y;
+};
+
+struct adc_properties {
+	uint32_t adc_reference; /* milli-voltage for this adc */
+	uint32_t bitresolution;
+	bool bipolar;
+	uint32_t conversiontime;
+};
+
+struct chan_properties {
+	uint32_t gain_numerator;
+	uint32_t gain_denominator;
+	struct linear_graph *adc_graph;
+/* this maybe the same as adc_properties.ConversionTime
+   if channel does not change the adc properties */
+	uint32_t chan_conv_time;
+};
+
+struct msm_adc_channels {
+	char *name;
+	uint32_t channel_name;
+	uint32_t adc_dev_instance;
+	struct adc_access_fn *adc_access_fn;
+	uint32_t chan_path_type;
+	uint32_t adc_config_type;
+	uint32_t adc_calib_type;
+	int32_t (*chan_processor)(int32_t, const struct adc_properties *,
+		const struct chan_properties *, struct adc_chan_result *);
+
+};
+
+struct msm_adc_platform_data {
+	struct msm_adc_channels *channel;
+	uint32_t num_chan_supported;
+	uint32_t num_adc;
+	uint32_t chan_per_adc;
+	char **dev_names;
+	uint32_t target_hw;
+	uint32_t gpio_config;
+	u32 (*adc_gpio_enable) (int);
+	u32 (*adc_gpio_disable) (int);
+	u32 (*adc_fluid_enable) (void);
+	u32 (*adc_fluid_disable) (void);
+};
+
+enum hw_type {
+	MSM_7x30,
+	MSM_8x60,
+	FSM_9xxx,
+};
+
+enum epm_gpio_config {
+	MPROC_CONFIG,
+	APROC_CONFIG
+};
+
+enum adc_request {
+	START_OF_CONV,
+	END_OF_CONV,
+	START_OF_CALIBRATION,
+	END_OF_CALIBRATION,
+};
+
+struct adc_dev_spec {
+	uint32_t			hwmon_dev_idx;
+	struct dal_dev_spec {
+		uint32_t		dev_idx;
+		uint32_t		chan_idx;
+	} dal;
+};
+
+struct dal_conv_request {
+	struct dal_dev_spec		target;
+	void				*cb_h;
+};
+
+struct dal_adc_result {
+	uint32_t			status;
+	uint32_t			token;
+	uint32_t			dev_idx;
+	uint32_t			chan_idx;
+	int				physical;
+	uint32_t			percent;
+	uint32_t			microvolts;
+	uint32_t			reserved;
+};
+
+struct dal_conv_slot {
+	void				*cb_h;
+	struct dal_adc_result		result;
+	struct completion		comp;
+	struct list_head		list;
+	uint32_t			idx;
+	uint32_t			chan_idx;
+	bool				blocking;
+	struct msm_client_data		*client;
+};
+
+struct dal_translation {
+	uint32_t			dal_dev_idx;
+	uint32_t			hwmon_dev_idx;
+	uint32_t			hwmon_start;
+	uint32_t			hwmon_end;
+};
+
+struct msm_client_data {
+	struct list_head		complete_list;
+	bool				online;
+	int32_t				adc_chan;
+	uint32_t			num_complete;
+	uint32_t			num_outstanding;
+	wait_queue_head_t		data_wait;
+	wait_queue_head_t		outst_wait;
+	struct mutex lock;
+};
+
+struct adc_conv_slot {
+	void				*cb_h;
+	union {
+		struct adc_chan_result		result;
+		struct dal_adc_result		dal_result;
+	} conv;
+	struct completion		comp;
+	struct completion		*compk;
+	struct list_head		list;
+	uint32_t			idx;
+	enum adc_request		adc_request;
+	bool				blocking;
+	struct msm_client_data		*client;
+	struct work_struct		work;
+	struct chan_properties		chan_properties;
+	uint32_t			chan_path;
+	uint32_t			chan_adc_config;
+	uint32_t			chan_adc_calib;
+};
+
+struct adc_access_fn {
+	int32_t (*adc_select_chan_and_start_conv)(uint32_t,
+				struct adc_conv_slot*);
+	int32_t (*adc_read_adc_code)(uint32_t dev_instance, int32_t *data);
+	struct adc_properties *(*adc_get_properties)(uint32_t dev_instance);
+	void (*adc_slot_request)(uint32_t dev_instance,
+				struct adc_conv_slot **);
+	void (*adc_restore_slot)(uint32_t dev_instance,
+				struct adc_conv_slot *slot);
+	int32_t (*adc_calibrate)(uint32_t dev_instance, struct adc_conv_slot*,
+		int *);
+};
+
+void msm_adc_wq_work(struct work_struct *work);
+void msm_adc_conv_cb(void *context, u32 param, void *evt_buf, u32 len);
+int32_t adc_channel_open(uint32_t channel, void **h);
+int32_t adc_channel_close(void *h);
+int32_t adc_channel_request_conv(void *h, struct completion *conv_complete_evt);
+int32_t adc_channel_read_result(void *h, struct adc_chan_result *chan_result);
+int32_t adc_calib_request(void *h, struct completion *calib_complete_evt);
+#endif
+#endif /* __MSM_ADC_H */
diff --git a/include/linux/msm_adsp.h b/include/linux/msm_adsp.h
new file mode 100644
index 0000000..ca23ad8
--- /dev/null
+++ b/include/linux/msm_adsp.h
@@ -0,0 +1,78 @@
+/* include/linux/msm_adsp.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Iliyan Malchev <ibm@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_MSM_ADSP_H
+#define __LINUX_MSM_ADSP_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define ADSP_IOCTL_MAGIC 'q'
+
+/* ADSP_IOCTL_WRITE_COMMAND */
+struct adsp_command_t {
+	uint16_t queue;
+	uint32_t len;		/* bytes */
+	uint8_t *data;
+};
+
+/* ADSP_IOCTL_GET_EVENT */
+struct adsp_event_t {
+	uint16_t type;		/* 1 == event (RPC), 0 == message (adsp) */
+	uint32_t timeout_ms;	/* -1 for infinite, 0 for immediate return */
+	uint16_t msg_id;
+	uint16_t flags;		/* 1 == 16--bit event, 0 == 32-bit event */
+	uint32_t len;		/* size in, number of bytes out */
+	uint8_t *data;
+};
+
+#define ADSP_IOCTL_ENABLE \
+	_IOR(ADSP_IOCTL_MAGIC, 1, unsigned)
+
+#define ADSP_IOCTL_DISABLE \
+	_IOR(ADSP_IOCTL_MAGIC, 2, unsigned)
+
+#define ADSP_IOCTL_DISABLE_ACK \
+	_IOR(ADSP_IOCTL_MAGIC, 3, unsigned)
+
+#define ADSP_IOCTL_WRITE_COMMAND \
+	_IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *)
+
+#define ADSP_IOCTL_GET_EVENT \
+	_IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *)
+
+#define ADSP_IOCTL_SET_CLKRATE \
+	_IOR(ADSP_IOCTL_MAGIC, 6, unsigned)
+
+#define ADSP_IOCTL_DISABLE_EVENT_RSP \
+	_IOR(ADSP_IOCTL_MAGIC, 10, unsigned)
+
+#define ADSP_IOCTL_REGISTER_PMEM \
+	_IOW(ADSP_IOCTL_MAGIC, 13, unsigned)
+
+#define ADSP_IOCTL_UNREGISTER_PMEM \
+	_IOW(ADSP_IOCTL_MAGIC, 14, unsigned)
+
+/* Cause any further GET_EVENT ioctls to fail (-ENODEV)
+ * until the device is closed and reopened.  Useful for
+ * terminating event dispatch threads
+ */
+#define ADSP_IOCTL_ABORT_EVENT_READ \
+	_IOW(ADSP_IOCTL_MAGIC, 15, unsigned)
+
+#define ADSP_IOCTL_LINK_TASK \
+	_IOW(ADSP_IOCTL_MAGIC, 16, unsigned)
+
+#endif
diff --git a/include/linux/msm_audio.h b/include/linux/msm_audio.h
new file mode 100644
index 0000000..30d74ce
--- /dev/null
+++ b/include/linux/msm_audio.h
@@ -0,0 +1,353 @@
+/* include/linux/msm_audio.h
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_MSM_AUDIO_H
+#define __LINUX_MSM_AUDIO_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/* PCM Audio */
+
+#define AUDIO_IOCTL_MAGIC 'a'
+
+#define AUDIO_START        _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned)
+#define AUDIO_STOP         _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned)
+#define AUDIO_FLUSH        _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned)
+#define AUDIO_GET_CONFIG   _IOR(AUDIO_IOCTL_MAGIC, 3, unsigned)
+#define AUDIO_SET_CONFIG   _IOW(AUDIO_IOCTL_MAGIC, 4, unsigned)
+#define AUDIO_GET_STATS    _IOR(AUDIO_IOCTL_MAGIC, 5, unsigned)
+#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned)
+#define AUDIO_SET_ADRC     _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned)
+#define AUDIO_SET_EQ       _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned)
+#define AUDIO_SET_RX_IIR   _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned)
+#define AUDIO_SET_VOLUME   _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned)
+#define AUDIO_PAUSE        _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned)
+#define AUDIO_PLAY_DTMF    _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned)
+#define AUDIO_GET_EVENT    _IOR(AUDIO_IOCTL_MAGIC, 13, unsigned)
+#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned)
+#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned)
+#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned)
+#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, unsigned)
+#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, unsigned)
+#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode)
+#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned)
+#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, \
+				struct msm_snd_device_list)
+#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned)
+#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned)
+#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, \
+				struct msm_audio_route_config)
+#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned)
+#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned)
+#define AUDIO_SWITCH_DEVICE  _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned)
+#define AUDIO_SET_MUTE       _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned)
+#define AUDIO_UPDATE_ACDB    _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned)
+#define AUDIO_START_VOICE    _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned)
+#define AUDIO_STOP_VOICE     _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned)
+#define AUDIO_REINIT_ACDB    _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned)
+#define AUDIO_OUTPORT_FLUSH  _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short)
+#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, \
+					unsigned short)
+#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, \
+			       struct msm_audio_bitstream_error_info)
+/* Qualcomm extensions */
+#define AUDIO_SET_STREAM_CONFIG   _IOW(AUDIO_IOCTL_MAGIC, 80, \
+				struct msm_audio_stream_config)
+#define AUDIO_GET_STREAM_CONFIG   _IOR(AUDIO_IOCTL_MAGIC, 81, \
+				struct msm_audio_stream_config)
+#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short)
+#define AUDIO_GET_STREAM_INFO   _IOR(AUDIO_IOCTL_MAGIC, 83, \
+			       struct msm_audio_bitstream_info)
+#define AUDIO_SET_PAN       _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned)
+#define AUDIO_SET_QCONCERT_PLUS       _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned)
+#define AUDIO_SET_MBADRC       _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned)
+#define AUDIO_SET_VOLUME_PATH   _IOW(AUDIO_IOCTL_MAGIC, 87, \
+				     struct msm_vol_info)
+#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned)
+#define AUDIO_ENABLE_AUDPRE  _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned)
+#define AUDIO_SET_AGC        _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned)
+#define AUDIO_SET_NS         _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned)
+#define AUDIO_SET_TX_IIR     _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned)
+#define AUDIO_GET_BUF_CFG    _IOW(AUDIO_IOCTL_MAGIC, 93, \
+					struct msm_audio_buf_cfg)
+#define AUDIO_SET_BUF_CFG    _IOW(AUDIO_IOCTL_MAGIC, 94, \
+					struct msm_audio_buf_cfg)
+#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95,  \
+					struct msm_acdb_cmd_device)
+#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96,  \
+					struct msm_acdb_cmd_device)
+
+#define	AUDIO_MAX_COMMON_IOCTL_NUM	100
+
+
+#define HANDSET_MIC			0x01
+#define HANDSET_SPKR			0x02
+#define HEADSET_MIC			0x03
+#define HEADSET_SPKR_MONO		0x04
+#define HEADSET_SPKR_STEREO		0x05
+#define SPKR_PHONE_MIC			0x06
+#define SPKR_PHONE_MONO			0x07
+#define SPKR_PHONE_STEREO		0x08
+#define BT_SCO_MIC			0x09
+#define BT_SCO_SPKR			0x0A
+#define BT_A2DP_SPKR			0x0B
+#define TTY_HEADSET_MIC			0x0C
+#define TTY_HEADSET_SPKR		0x0D
+
+/* Default devices are not supported in a */
+/* device switching context. Only supported */
+/* for stream devices. */
+/* DO NOT USE */
+#define DEFAULT_TX			0x0E
+#define DEFAULT_RX			0x0F
+
+#define BT_A2DP_TX			0x10
+
+#define HEADSET_MONO_PLUS_SPKR_MONO_RX         0x11
+#define HEADSET_MONO_PLUS_SPKR_STEREO_RX       0x12
+#define HEADSET_STEREO_PLUS_SPKR_MONO_RX       0x13
+#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX     0x14
+
+#define I2S_RX				0x20
+#define I2S_TX				0x21
+
+#define ADRC_ENABLE		0x0001
+#define EQ_ENABLE		0x0002
+#define IIR_ENABLE		0x0004
+#define QCONCERT_PLUS_ENABLE	0x0008
+#define MBADRC_ENABLE		0x0010
+
+#define AGC_ENABLE		0x0001
+#define NS_ENABLE		0x0002
+#define TX_IIR_ENABLE		0x0004
+#define FLUENCE_ENABLE		0x0008
+
+#define VOC_REC_UPLINK		0x00
+#define VOC_REC_DOWNLINK	0x01
+#define VOC_REC_BOTH		0x02
+
+struct msm_audio_config {
+	uint32_t buffer_size;
+	uint32_t buffer_count;
+	uint32_t channel_count;
+	uint32_t sample_rate;
+	uint32_t type;
+	uint32_t meta_field;
+	uint32_t bits;
+	uint32_t unused[3];
+};
+
+struct msm_audio_stream_config {
+	uint32_t buffer_size;
+	uint32_t buffer_count;
+};
+
+struct msm_audio_buf_cfg{
+	uint32_t meta_info_enable;
+	uint32_t frames_per_buf;
+};
+
+struct msm_audio_stats {
+	uint32_t byte_count;
+	uint32_t sample_count;
+	uint32_t unused[2];
+};
+
+struct msm_audio_pmem_info {
+	int fd;
+	void *vaddr;
+};
+
+struct msm_audio_aio_buf {
+	void *buf_addr;
+	uint32_t buf_len;
+	uint32_t data_len;
+	void *private_data;
+	unsigned short mfield_sz; /*only useful for data has meta field */
+};
+
+/* Audio routing */
+
+#define SND_IOCTL_MAGIC 's'
+
+#define SND_MUTE_UNMUTED 0
+#define SND_MUTE_MUTED   1
+
+struct msm_mute_info {
+	uint32_t mute;
+	uint32_t path;
+};
+
+struct msm_vol_info {
+	uint32_t vol;
+	uint32_t path;
+};
+
+struct msm_voicerec_mode {
+	uint32_t rec_mode;
+};
+
+struct msm_snd_device_config {
+	uint32_t device;
+	uint32_t ear_mute;
+	uint32_t mic_mute;
+};
+
+#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *)
+
+#define SND_METHOD_VOICE 0
+
+struct msm_snd_volume_config {
+	uint32_t device;
+	uint32_t method;
+	uint32_t volume;
+};
+
+#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *)
+
+/* Returns the number of SND endpoints supported. */
+
+#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *)
+
+struct msm_snd_endpoint {
+	int id; /* input and output */
+	char name[64]; /* output only */
+};
+
+/* Takes an index between 0 and one less than the number returned by
+ * SND_GET_NUM_ENDPOINTS, and returns the SND index and name of a
+ * SND endpoint.  On input, the .id field contains the number of the
+ * endpoint, and on exit it contains the SND index, while .name contains
+ * the description of the endpoint.
+ */
+
+#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *)
+
+
+#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned *)
+#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned *)
+
+struct msm_audio_pcm_config {
+	uint32_t pcm_feedback;	/* 0 - disable > 0 - enable */
+	uint32_t buffer_count;	/* Number of buffers to allocate */
+	uint32_t buffer_size;	/* Size of buffer for capturing of
+				   PCM samples */
+};
+
+#define AUDIO_EVENT_SUSPEND 0
+#define AUDIO_EVENT_RESUME 1
+#define AUDIO_EVENT_WRITE_DONE 2
+#define AUDIO_EVENT_READ_DONE   3
+#define AUDIO_EVENT_STREAM_INFO 4
+#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5
+
+#define AUDIO_CODEC_TYPE_MP3 0
+#define AUDIO_CODEC_TYPE_AAC 1
+
+struct msm_audio_bitstream_info {
+	uint32_t codec_type;
+	uint32_t chan_info;
+	uint32_t sample_rate;
+	uint32_t bit_stream_info;
+	uint32_t bit_rate;
+	uint32_t unused[3];
+};
+
+struct msm_audio_bitstream_error_info {
+	uint32_t dec_id;
+	uint32_t err_msg_indicator;
+	uint32_t err_type;
+};
+
+union msm_audio_event_payload {
+	struct msm_audio_aio_buf aio_buf;
+	struct msm_audio_bitstream_info stream_info;
+	struct msm_audio_bitstream_error_info error_info;
+	int reserved;
+};
+
+struct msm_audio_event {
+	int event_type;
+	int timeout_ms;
+	union msm_audio_event_payload event_payload;
+};
+
+#define MSM_SNDDEV_CAP_RX 0x1
+#define MSM_SNDDEV_CAP_TX 0x2
+#define MSM_SNDDEV_CAP_VOICE 0x4
+
+struct msm_snd_device_info {
+	uint32_t dev_id;
+	uint32_t dev_cap; /* bitmask describe capability of device */
+	char dev_name[64];
+};
+
+struct msm_snd_device_list {
+	uint32_t  num_dev; /* Indicate number of device info to be retrieved */
+	struct msm_snd_device_info *list;
+};
+
+struct msm_dtmf_config {
+	uint16_t path;
+	uint16_t dtmf_hi;
+	uint16_t dtmf_low;
+	uint16_t duration;
+	uint16_t tx_gain;
+	uint16_t rx_gain;
+	uint16_t mixing;
+};
+
+#define AUDIO_ROUTE_STREAM_VOICE_RX 0
+#define AUDIO_ROUTE_STREAM_VOICE_TX 1
+#define AUDIO_ROUTE_STREAM_PLAYBACK 2
+#define AUDIO_ROUTE_STREAM_REC      3
+
+struct msm_audio_route_config {
+	uint32_t stream_type;
+	uint32_t stream_id;
+	uint32_t dev_id;
+};
+
+#define AUDIO_MAX_EQ_BANDS 12
+
+struct msm_audio_eq_band {
+	uint16_t     band_idx; /* The band index, 0 .. 11 */
+	uint32_t     filter_type; /* Filter band type */
+	uint32_t     center_freq_hz; /* Filter band center frequency */
+	uint32_t     filter_gain; /* Filter band initial gain (dB) */
+			/* Range is +12 dB to -12 dB with 1dB increments. */
+	uint32_t     q_factor;
+} __attribute__ ((packed));
+
+struct msm_audio_eq_stream_config {
+	uint32_t	enable; /* Number of consequtive bands specified */
+	uint32_t	num_bands;
+	struct msm_audio_eq_band	eq_bands[AUDIO_MAX_EQ_BANDS];
+} __attribute__ ((packed));
+
+struct msm_acdb_cmd_device {
+	uint32_t     command_id;
+	uint32_t     device_id;
+	uint32_t     network_id;
+	uint32_t     sample_rate_id;      /* Actual sample rate value */
+	uint32_t     interface_id;        /* See interface id's above */
+	uint32_t     algorithm_block_id;  /* See enumerations above */
+	uint32_t     total_bytes;         /* Length in bytes used by buffer */
+	uint32_t     *phys_buf;           /* Physical Address of data */
+};
+
+
+#endif
diff --git a/include/linux/msm_audio_aac.h b/include/linux/msm_audio_aac.h
new file mode 100644
index 0000000..6e6acff
--- /dev/null
+++ b/include/linux/msm_audio_aac.h
@@ -0,0 +1,71 @@
+#ifndef __MSM_AUDIO_AAC_H
+#define __MSM_AUDIO_AAC_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_SET_AAC_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+  (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_GET_AAC_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+  (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+#define AUDIO_SET_AAC_ENC_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+  (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config)
+
+#define AUDIO_GET_AAC_ENC_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+  (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config)
+
+#define AUDIO_AAC_FORMAT_ADTS		-1
+#define	AUDIO_AAC_FORMAT_RAW		0x0000
+#define	AUDIO_AAC_FORMAT_PSUEDO_RAW	0x0001
+#define AUDIO_AAC_FORMAT_LOAS		0x0002
+
+#define AUDIO_AAC_OBJECT_LC            	0x0002
+#define AUDIO_AAC_OBJECT_LTP		0x0004
+#define AUDIO_AAC_OBJECT_ERLC  		0x0011
+#define AUDIO_AAC_OBJECT_BSAC  		0x0016
+
+#define AUDIO_AAC_SEC_DATA_RES_ON       0x0001
+#define AUDIO_AAC_SEC_DATA_RES_OFF      0x0000
+
+#define AUDIO_AAC_SCA_DATA_RES_ON       0x0001
+#define AUDIO_AAC_SCA_DATA_RES_OFF      0x0000
+
+#define AUDIO_AAC_SPEC_DATA_RES_ON      0x0001
+#define AUDIO_AAC_SPEC_DATA_RES_OFF     0x0000
+
+#define AUDIO_AAC_SBR_ON_FLAG_ON	0x0001
+#define AUDIO_AAC_SBR_ON_FLAG_OFF	0x0000
+
+#define AUDIO_AAC_SBR_PS_ON_FLAG_ON	0x0001
+#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF	0x0000
+
+/* Primary channel on both left and right channels */
+#define AUDIO_AAC_DUAL_MONO_PL_PR  0
+/* Secondary channel on both left and right channels */
+#define AUDIO_AAC_DUAL_MONO_SL_SR  1
+/* Primary channel on right channel and 2nd on left channel */
+#define AUDIO_AAC_DUAL_MONO_SL_PR  2
+/* 2nd channel on right channel and primary on left channel */
+#define AUDIO_AAC_DUAL_MONO_PL_SR  3
+
+struct msm_audio_aac_config {
+	signed short format;
+	unsigned short audio_object;
+	unsigned short ep_config;	/* 0 ~ 3 useful only obj = ERLC */
+	unsigned short aac_section_data_resilience_flag;
+	unsigned short aac_scalefactor_data_resilience_flag;
+	unsigned short aac_spectral_data_resilience_flag;
+	unsigned short sbr_on_flag;
+	unsigned short sbr_ps_on_flag;
+	unsigned short dual_mono_mode;
+	unsigned short channel_configuration;
+};
+
+struct msm_audio_aac_enc_config {
+	uint32_t channels;
+	uint32_t sample_rate;
+	uint32_t bit_rate;
+	uint32_t stream_format;
+};
+
+#endif /* __MSM_AUDIO_AAC_H */
diff --git a/include/linux/msm_audio_acdb.h b/include/linux/msm_audio_acdb.h
new file mode 100644
index 0000000..04cb67f
--- /dev/null
+++ b/include/linux/msm_audio_acdb.h
@@ -0,0 +1,73 @@
+#ifndef __MSM_AUDIO_ACDB_H
+#define __MSM_AUDIO_ACDB_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_SET_VOCPROC_CAL		_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_VOCPROC_STREAM_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+#define AUDIO_SET_VOCPROC_VOL_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+2), unsigned)
+#define AUDIO_SET_AUDPROC_RX_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+3), unsigned)
+#define AUDIO_SET_AUDPROC_RX_STREAM_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+4), unsigned)
+#define AUDIO_SET_AUDPROC_RX_VOL_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+5), unsigned)
+#define AUDIO_SET_AUDPROC_TX_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+6), unsigned)
+#define AUDIO_SET_AUDPROC_TX_STREAM_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+7), unsigned)
+#define AUDIO_SET_AUDPROC_TX_VOL_CAL	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+8), unsigned)
+#define AUDIO_SET_SIDETONE_CAL		_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+9), unsigned)
+#define AUDIO_SET_ANC_CAL		_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+10), unsigned)
+#define AUDIO_SET_VOICE_RX_TOPOLOGY	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+11), unsigned)
+#define AUDIO_SET_VOICE_TX_TOPOLOGY	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+12), unsigned)
+#define AUDIO_SET_ADM_TOPOLOGY	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+13), unsigned)
+#define AUDIO_SET_ASM_TOPOLOGY	_IOW(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+14), unsigned)
+
+/* ACDB structures */
+struct cal_block {
+	uint32_t	cal_size;	/* Size of Cal Data */
+	uint32_t	cal_offset;	/* offset pointer to Cal Data */
+};
+
+struct sidetone_cal {
+	uint16_t	enable;
+	uint16_t	gain;
+};
+
+/* For Real-Time Audio Calibration */
+#define AUDIO_GET_RTAC_DEV_CTRL_INFO	_IOR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+15), unsigned)
+#define AUDIO_GET_RTAC_ADM_INFO		_IOR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+16), unsigned)
+#define AUDIO_GET_RTAC_VOICE_INFO	_IOR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+17), unsigned)
+#define AUDIO_GET_RTAC_ADM_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+18), unsigned)
+#define AUDIO_SET_RTAC_ADM_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+19), unsigned)
+#define AUDIO_GET_RTAC_ASM_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+20), unsigned)
+#define AUDIO_SET_RTAC_ASM_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+21), unsigned)
+#define AUDIO_GET_RTAC_CVS_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+22), unsigned)
+#define AUDIO_SET_RTAC_CVS_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+23), unsigned)
+#define AUDIO_GET_RTAC_CVP_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+24), unsigned)
+#define AUDIO_SET_RTAC_CVP_CAL	_IOWR(AUDIO_IOCTL_MAGIC, \
+			(AUDIO_MAX_COMMON_IOCTL_NUM+25), unsigned)
+
+
+#endif /* __MSM_AUDIO_ACDB_H */
diff --git a/include/linux/msm_audio_amrnb.h b/include/linux/msm_audio_amrnb.h
new file mode 100644
index 0000000..977335e
--- /dev/null
+++ b/include/linux/msm_audio_amrnb.h
@@ -0,0 +1,51 @@
+/* arch/arm/mach-msm/include/mach/msm_audio_amrnb.h
+ *
+ * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can find it at http://www.fsf.org.
+ *
+ */
+
+#ifndef __MSM_AUDIO_AMRNB_H
+#define __MSM_AUDIO_AMRNB_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_GET_AMRNB_ENC_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_AMRNB_ENC_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+#define AUDIO_GET_AMRNB_ENC_CONFIG_V2  _IOW(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM+2), \
+	struct msm_audio_amrnb_enc_config_v2)
+#define AUDIO_SET_AMRNB_ENC_CONFIG_V2  _IOR(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM+3), \
+	struct msm_audio_amrnb_enc_config_v2)
+
+struct msm_audio_amrnb_enc_config {
+	unsigned short voicememoencweight1;
+	unsigned short voicememoencweight2;
+	unsigned short voicememoencweight3;
+	unsigned short voicememoencweight4;
+	unsigned short dtx_mode_enable; /* 0xFFFF - enable, 0- disable */
+	unsigned short test_mode_enable; /* 0xFFFF - enable, 0- disable */
+	unsigned short enc_mode; /* 0-MR475,1-MR515,2-MR59,3-MR67,4-MR74
+				5-MR795, 6- MR102, 7- MR122(default) */
+};
+
+struct msm_audio_amrnb_enc_config_v2 {
+	uint32_t band_mode;
+	uint32_t dtx_enable;
+	uint32_t frame_format;
+};
+#endif /* __MSM_AUDIO_AMRNB_H */
diff --git a/include/linux/msm_audio_mvs.h b/include/linux/msm_audio_mvs.h
new file mode 100644
index 0000000..f401c1f
--- /dev/null
+++ b/include/linux/msm_audio_mvs.h
@@ -0,0 +1,111 @@
+#ifndef __MSM_AUDIO_MVS_H
+#define __MSM_AUDIO_MVS_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_GET_MVS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM + 0), unsigned)
+#define AUDIO_SET_MVS_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM + 1), unsigned)
+
+/* MVS modes */
+#define MVS_MODE_IS733 1
+#define MVS_MODE_IS127 2
+#define MVS_MODE_4GV_NB 3
+#define MVS_MODE_4GV_WB 4
+#define MVS_MODE_AMR 5
+#define MVS_MODE_EFR 6
+#define MVS_MODE_FR 7
+#define MVS_MODE_HR 8
+#define MVS_MODE_LINEAR_PCM 9
+#define MVS_MODE_G711 10
+#define MVS_MODE_PCM 12
+#define MVS_MODE_AMR_WB 13
+#define MVS_MODE_G729A 14
+#define MVS_MODE_G711A 15
+#define MVS_MODE_G722 16
+
+enum msm_audio_amr_mode {
+	MVS_AMR_MODE_0475, /* AMR 4.75 kbps */
+	MVS_AMR_MODE_0515, /* AMR 5.15 kbps */
+	MVS_AMR_MODE_0590, /* AMR 5.90 kbps */
+	MVS_AMR_MODE_0670, /* AMR 6.70 kbps */
+	MVS_AMR_MODE_0740, /* AMR 7.40 kbps */
+	MVS_AMR_MODE_0795, /* AMR 7.95 kbps */
+	MVS_AMR_MODE_1020, /* AMR 10.20 kbps */
+	MVS_AMR_MODE_1220, /* AMR 12.20 kbps */
+	MVS_AMR_MODE_0660, /* AMR-WB 6.60 kbps */
+	MVS_AMR_MODE_0885, /* AMR-WB 8.85 kbps */
+	MVS_AMR_MODE_1265, /* AMR-WB 12.65 kbps */
+	MVS_AMR_MODE_1425, /* AMR-WB 14.25 kbps */
+	MVS_AMR_MODE_1585, /* AMR-WB 15.85 kbps */
+	MVS_AMR_MODE_1825, /* AMR-WB 18.25 kbps */
+	MVS_AMR_MODE_1985, /* AMR-WB 19.85 kbps */
+	MVS_AMR_MODE_2305, /* AMR-WB 23.05 kbps */
+	MVS_AMR_MODE_2385, /* AMR-WB 23.85 kbps */
+	MVS_AMR_MODE_UNDEF
+};
+
+enum msm_audio_voc_rate {
+		MVS_VOC_0_RATE, /* Blank frame */
+		MVS_VOC_8_RATE, /* 1/8 rate    */
+		MVS_VOC_4_RATE, /* 1/4 rate    */
+		MVS_VOC_2_RATE, /* 1/2 rate    */
+		MVS_VOC_1_RATE	/* Full rate   */
+};
+
+enum msm_audio_amr_frame_type {
+	MVS_AMR_SPEECH_GOOD,	      /* Good speech frame              */
+	MVS_AMR_SPEECH_DEGRADED,      /* Speech degraded                */
+	MVS_AMR_ONSET,		      /* Onset                          */
+	MVS_AMR_SPEECH_BAD,	      /* Corrupt speech frame (bad CRC) */
+	MVS_AMR_SID_FIRST,	      /* First silence descriptor       */
+	MVS_AMR_SID_UPDATE,	      /* Comfort noise frame            */
+	MVS_AMR_SID_BAD,	      /* Corrupt SID frame (bad CRC)    */
+	MVS_AMR_NO_DATA,	      /* Nothing to transmit            */
+	MVS_AMR_SPEECH_LOST	      /* Downlink speech lost           */
+};
+
+enum msm_audio_g711a_mode {
+	MVS_G711A_MODE_MULAW,
+	MVS_G711A_MODE_ALAW
+};
+
+enum mvs_g722_mode_type {
+	MVS_G722_MODE_01,
+	MVS_G722_MODE_02,
+	MVS_G722_MODE_03,
+	MVS_G722_MODE_MAX,
+	MVS_G722_MODE_UNDEF
+};
+
+enum msm_audio_g711a_frame_type {
+	MVS_G711A_SPEECH_GOOD,
+	MVS_G711A_SID,
+	MVS_G711A_NO_DATA,
+	MVS_G711A_ERASURE
+};
+
+enum msm_audio_g729a_frame_type {
+	MVS_G729A_NO_DATA,
+	MVS_G729A_SPEECH_GOOD,
+	MVS_G729A_SID,
+	MVS_G729A_ERASURE
+};
+
+struct msm_audio_mvs_config {
+	uint32_t mvs_mode;
+	uint32_t rate_type;
+	uint32_t dtx_mode;
+};
+
+#define MVS_MAX_VOC_PKT_SIZE 320
+
+struct msm_audio_mvs_frame {
+	uint32_t frame_type;
+	uint32_t len;
+	uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE];
+
+};
+
+#endif /* __MSM_AUDIO_MVS_H */
diff --git a/include/linux/msm_audio_qcp.h b/include/linux/msm_audio_qcp.h
new file mode 100644
index 0000000..c5e42cf
--- /dev/null
+++ b/include/linux/msm_audio_qcp.h
@@ -0,0 +1,50 @@
+/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MSM_AUDIO_QCP_H
+#define __MSM_AUDIO_QCP_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_SET_QCELP_ENC_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+	0, struct msm_audio_qcelp_enc_config)
+
+#define AUDIO_GET_QCELP_ENC_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+	1, struct msm_audio_qcelp_enc_config)
+
+#define AUDIO_SET_EVRC_ENC_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+	2, struct msm_audio_evrc_enc_config)
+
+#define AUDIO_GET_EVRC_ENC_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+	3, struct msm_audio_evrc_enc_config)
+
+#define CDMA_RATE_BLANK		0x00
+#define CDMA_RATE_EIGHTH	0x01
+#define CDMA_RATE_QUARTER	0x02
+#define CDMA_RATE_HALF		0x03
+#define CDMA_RATE_FULL		0x04
+#define CDMA_RATE_ERASURE	0x05
+
+struct msm_audio_qcelp_enc_config {
+	uint32_t cdma_rate;
+	uint32_t min_bit_rate;
+	uint32_t max_bit_rate;
+};
+
+struct msm_audio_evrc_enc_config {
+	uint32_t cdma_rate;
+	uint32_t min_bit_rate;
+	uint32_t max_bit_rate;
+};
+
+#endif /* __MSM_AUDIO_QCP_H */
diff --git a/include/linux/msm_audio_sbc.h b/include/linux/msm_audio_sbc.h
new file mode 100644
index 0000000..0a7602a
--- /dev/null
+++ b/include/linux/msm_audio_sbc.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MSM_AUDIO_SBC_H
+#define __MSM_AUDIO_SBC_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_SET_SBC_ENC_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+  (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_sbc_enc_config)
+
+#define AUDIO_GET_SBC_ENC_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+  (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_sbc_enc_config)
+
+#define AUDIO_SBC_BA_LOUDNESS		0x0
+#define AUDIO_SBC_BA_SNR		0x1
+
+#define AUDIO_SBC_MODE_MONO		0x0
+#define AUDIO_SBC_MODE_DUAL		0x1
+#define AUDIO_SBC_MODE_STEREO		0x2
+#define AUDIO_SBC_MODE_JSTEREO		0x3
+
+#define AUDIO_SBC_BANDS_8		0x1
+
+#define AUDIO_SBC_BLOCKS_4		0x0
+#define AUDIO_SBC_BLOCKS_8		0x1
+#define AUDIO_SBC_BLOCKS_12		0x2
+#define AUDIO_SBC_BLOCKS_16		0x3
+
+struct msm_audio_sbc_enc_config {
+	uint32_t channels;
+	uint32_t sample_rate;
+	uint32_t bit_allocation;
+	uint32_t number_of_subbands;
+	uint32_t number_of_blocks;
+	uint32_t bit_rate;
+	uint32_t mode;
+};
+#endif /* __MSM_AUDIO_SBC_H */
diff --git a/include/linux/msm_audio_voicememo.h b/include/linux/msm_audio_voicememo.h
new file mode 100644
index 0000000..5cb1d65
--- /dev/null
+++ b/include/linux/msm_audio_voicememo.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MSM_AUDIO_VOICEMEMO_H
+#define __MSM_AUDIO_VOICEMEMO_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_GET_VOICEMEMO_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_VOICEMEMO_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+	(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+/* rec_type */
+enum rpc_voc_rec_dir_type {
+	RPC_VOC_REC_NONE,
+	RPC_VOC_REC_FORWARD,
+	RPC_VOC_REC_REVERSE,
+	RPC_VOC_REC_BOTH,
+	RPC_VOC_MAX_REC_TYPE
+};
+
+/* capability */
+enum rpc_voc_capability_type {
+	RPC_VOC_CAP_IS733 = 4,
+	RPC_VOC_CAP_IS127 = 8,
+	RPC_VOC_CAP_AMR = 64,
+	RPC_VOC_CAP_32BIT_DUMMY = 2147483647
+};
+
+/* Rate */
+enum rpc_voc_rate_type {
+	RPC_VOC_0_RATE = 0,
+	RPC_VOC_8_RATE,
+	RPC_VOC_4_RATE,
+	RPC_VOC_2_RATE,
+	RPC_VOC_1_RATE,
+	RPC_VOC_ERASURE,
+	RPC_VOC_ERR_RATE,
+	RPC_VOC_AMR_RATE_475 = 0,
+	RPC_VOC_AMR_RATE_515 = 1,
+	RPC_VOC_AMR_RATE_590 = 2,
+	RPC_VOC_AMR_RATE_670 = 3,
+	RPC_VOC_AMR_RATE_740 = 4,
+	RPC_VOC_AMR_RATE_795 = 5,
+	RPC_VOC_AMR_RATE_1020 = 6,
+	RPC_VOC_AMR_RATE_1220 = 7,
+};
+
+/* frame_format */
+enum rpc_voc_pb_len_rate_var_type {
+	RPC_VOC_PB_NATIVE_QCP = 3,
+	RPC_VOC_PB_AMR,
+	RPC_VOC_PB_EVB
+};
+
+struct msm_audio_voicememo_config {
+	uint32_t rec_type;
+	uint32_t rec_interval_ms;
+	uint32_t auto_stop_ms;
+	uint32_t capability;
+	uint32_t max_rate;
+	uint32_t min_rate;
+	uint32_t frame_format;
+	uint32_t dtx_enable;
+	uint32_t data_req_ms;
+};
+
+#endif /* __MSM_AUDIO_VOICEMEMO_H */
diff --git a/include/linux/msm_audio_wma.h b/include/linux/msm_audio_wma.h
new file mode 100644
index 0000000..24ff264
--- /dev/null
+++ b/include/linux/msm_audio_wma.h
@@ -0,0 +1,33 @@
+#ifndef __MSM_AUDIO_WMA_H
+#define __MSM_AUDIO_WMA_H
+
+#define AUDIO_GET_WMA_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+	  (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_WMA_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+	  (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+#define AUDIO_GET_WMA_CONFIG_V2  _IOR(AUDIO_IOCTL_MAGIC, \
+	  (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2)
+#define AUDIO_SET_WMA_CONFIG_V2  _IOW(AUDIO_IOCTL_MAGIC, \
+	  (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2)
+
+struct msm_audio_wma_config {
+	unsigned short 	armdatareqthr;
+	unsigned short 	channelsdecoded;
+	unsigned short 	wmabytespersec;
+	unsigned short	wmasamplingfreq;
+	unsigned short	wmaencoderopts;
+};
+
+struct msm_audio_wma_config_v2 {
+	unsigned short	format_tag;
+	unsigned short	numchannels;
+	uint32_t	samplingrate;
+	uint32_t	avgbytespersecond;
+	unsigned short	block_align;
+	unsigned short  validbitspersample;
+	uint32_t	channelmask;
+	unsigned short	encodeopt;
+};
+
+#endif /* __MSM_AUDIO_WMA_H */
diff --git a/include/linux/msm_audio_wmapro.h b/include/linux/msm_audio_wmapro.h
new file mode 100644
index 0000000..b680f41
--- /dev/null
+++ b/include/linux/msm_audio_wmapro.h
@@ -0,0 +1,22 @@
+#ifndef __MSM_AUDIO_WMAPRO_H
+#define __MSM_AUDIO_WMAPRO_H
+
+#define AUDIO_GET_WMAPRO_CONFIG  _IOR(AUDIO_IOCTL_MAGIC, \
+	  (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_WMAPRO_CONFIG  _IOW(AUDIO_IOCTL_MAGIC, \
+	  (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+struct msm_audio_wmapro_config {
+	unsigned short 	armdatareqthr;
+	uint8_t         validbitspersample;
+	uint8_t         numchannels;
+	unsigned short  formattag;
+	unsigned short  samplingrate;
+	unsigned short  avgbytespersecond;
+	unsigned short  asfpacketlength;
+	unsigned short 	channelmask;
+	unsigned short 	encodeopt;
+	unsigned short	advancedencodeopt;
+	uint32_t	advancedencodeopt2;
+};
+#endif /* __MSM_AUDIO_WMAPRO_H */
diff --git a/include/linux/msm_charm.h b/include/linux/msm_charm.h
new file mode 100644
index 0000000..779fd38
--- /dev/null
+++ b/include/linux/msm_charm.h
@@ -0,0 +1,19 @@
+#ifndef _ARCH_ARM_MACH_MSM_MDM_IOCTLS_H
+#define _ARXH_ARM_MACH_MSM_MDM_IOCTLS_H
+
+
+#define CHARM_CODE		0xCC
+#define WAKE_CHARM		_IO(CHARM_CODE, 1)
+#define RESET_CHARM		_IO(CHARM_CODE, 2)
+#define CHECK_FOR_BOOT		_IOR(CHARM_CODE, 3, int)
+#define WAIT_FOR_BOOT		_IO(CHARM_CODE, 4)
+#define NORMAL_BOOT_DONE	_IOW(CHARM_CODE, 5, int)
+#define RAM_DUMP_DONE		_IOW(CHARM_CODE, 6, int)
+#define WAIT_FOR_RESTART	_IOR(CHARM_CODE, 7, int)
+
+enum charm_boot_type {
+	CHARM_NORMAL_BOOT = 0,
+	CHARM_RAM_DUMPS,
+};
+
+#endif
diff --git a/include/linux/msm_dsps.h b/include/linux/msm_dsps.h
new file mode 100644
index 0000000..7f4d2dd
--- /dev/null
+++ b/include/linux/msm_dsps.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSPS_H_
+#define _DSPS_H_
+
+#include <linux/ioctl.h>
+
+#define DSPS_IOCTL_MAGIC 'd'
+
+#define DSPS_IOCTL_ON	_IO(DSPS_IOCTL_MAGIC, 1)
+#define DSPS_IOCTL_OFF	_IO(DSPS_IOCTL_MAGIC, 2)
+
+#define DSPS_IOCTL_READ_SLOW_TIMER _IOR(DSPS_IOCTL_MAGIC, 3, unsigned int*)
+#define DSPS_IOCTL_READ_FAST_TIMER _IOR(DSPS_IOCTL_MAGIC, 4, unsigned int*)
+
+#endif	/* _DSPS_H_ */
diff --git a/include/linux/msm_ipc.h b/include/linux/msm_ipc.h
new file mode 100644
index 0000000..19cb82e
--- /dev/null
+++ b/include/linux/msm_ipc.h
@@ -0,0 +1,72 @@
+#ifndef _LINUX_MSM_IPC_H_
+#define _LINUX_MSM_IPC_H_
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+struct msm_ipc_port_addr {
+	uint32_t node_id;
+	uint32_t port_id;
+};
+
+struct msm_ipc_port_name {
+	uint32_t service;
+	uint32_t instance;
+};
+
+struct msm_ipc_addr {
+	unsigned char  addrtype;
+	union {
+		struct msm_ipc_port_addr port_addr;
+		struct msm_ipc_port_name port_name;
+	} addr;
+};
+
+#define MSM_IPC_WAIT_FOREVER	(~0)  /* timeout for permanent subscription */
+
+/*
+ * Socket API
+ */
+
+#ifndef AF_MSM_IPC
+#define AF_MSM_IPC		27
+#endif
+
+#ifndef PF_MSM_IPC
+#define PF_MSM_IPC		AF_MSM_IPC
+#endif
+
+#define MSM_IPC_ADDR_NAME		1
+#define MSM_IPC_ADDR_ID			2
+
+struct sockaddr_msm_ipc {
+	unsigned short family;
+	struct msm_ipc_addr address;
+	unsigned char reserved;
+};
+
+#define IPC_ROUTER_IOCTL_MAGIC (0xC3)
+
+#define IPC_ROUTER_IOCTL_GET_VERSION \
+	_IOR(IPC_ROUTER_IOCTL_MAGIC, 0, unsigned int)
+
+#define IPC_ROUTER_IOCTL_GET_MTU \
+	_IOR(IPC_ROUTER_IOCTL_MAGIC, 1, unsigned int)
+
+#define IPC_ROUTER_IOCTL_LOOKUP_SERVER \
+	_IOWR(IPC_ROUTER_IOCTL_MAGIC, 2, struct sockaddr_msm_ipc)
+
+#define IPC_ROUTER_IOCTL_GET_CURR_PKT_SIZE \
+	_IOR(IPC_ROUTER_IOCTL_MAGIC, 3, unsigned int)
+
+#define IPC_ROUTER_IOCTL_BIND_CONTROL_PORT \
+	_IOR(IPC_ROUTER_IOCTL_MAGIC, 4, unsigned int)
+
+struct server_lookup_args {
+	struct msm_ipc_port_name port_name;
+	int num_entries_in_array;
+	int num_entries_found;
+	struct msm_ipc_port_addr port_addr[0];
+};
+
+#endif
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
new file mode 100644
index 0000000..2a38d52
--- /dev/null
+++ b/include/linux/msm_kgsl.h
@@ -0,0 +1,408 @@
+#ifndef _MSM_KGSL_H
+#define _MSM_KGSL_H
+
+#define KGSL_VERSION_MAJOR        3
+#define KGSL_VERSION_MINOR        4
+
+/*context flags */
+#define KGSL_CONTEXT_SAVE_GMEM	1
+#define KGSL_CONTEXT_NO_GMEM_ALLOC	2
+#define KGSL_CONTEXT_SUBMIT_IB_LIST	4
+#define KGSL_CONTEXT_CTX_SWITCH	8
+
+/* Memory allocayion flags */
+#define KGSL_MEMFLAGS_GPUREADONLY	0x01000000
+
+/* generic flag values */
+#define KGSL_FLAGS_NORMALMODE  0x00000000
+#define KGSL_FLAGS_SAFEMODE    0x00000001
+#define KGSL_FLAGS_INITIALIZED0 0x00000002
+#define KGSL_FLAGS_INITIALIZED 0x00000004
+#define KGSL_FLAGS_STARTED     0x00000008
+#define KGSL_FLAGS_ACTIVE      0x00000010
+#define KGSL_FLAGS_RESERVED0   0x00000020
+#define KGSL_FLAGS_RESERVED1   0x00000040
+#define KGSL_FLAGS_RESERVED2   0x00000080
+#define KGSL_FLAGS_SOFT_RESET  0x00000100
+
+#define KGSL_MAX_PWRLEVELS 5
+
+/* device id */
+enum kgsl_deviceid {
+	KGSL_DEVICE_3D0		= 0x00000000,
+	KGSL_DEVICE_2D0		= 0x00000001,
+	KGSL_DEVICE_2D1		= 0x00000002,
+	KGSL_DEVICE_MAX		= 0x00000003
+};
+
+enum kgsl_user_mem_type {
+	KGSL_USER_MEM_TYPE_PMEM		= 0x00000000,
+	KGSL_USER_MEM_TYPE_ASHMEM	= 0x00000001,
+	KGSL_USER_MEM_TYPE_ADDR		= 0x00000002
+};
+
+struct kgsl_devinfo {
+
+	unsigned int device_id;
+	/* chip revision id
+	* coreid:8 majorrev:8 minorrev:8 patch:8
+	*/
+	unsigned int chip_id;
+	unsigned int mmu_enabled;
+	unsigned int gmem_gpubaseaddr;
+	/*
+	* This field contains the adreno revision
+	* number 200, 205, 220, etc...
+	*/
+	unsigned int gpu_id;
+	unsigned int gmem_sizebytes;
+};
+
+/* this structure defines the region of memory that can be mmap()ed from this
+   driver. The timestamp fields are volatile because they are written by the
+   GPU
+*/
+struct kgsl_devmemstore {
+	volatile unsigned int soptimestamp;
+	unsigned int sbz;
+	volatile unsigned int eoptimestamp;
+	unsigned int sbz2;
+	volatile unsigned int ts_cmp_enable;
+	unsigned int sbz3;
+	volatile unsigned int ref_wait_ts;
+	unsigned int sbz4;
+	unsigned int current_context;
+	unsigned int sbz5;
+};
+
+#define KGSL_DEVICE_MEMSTORE_OFFSET(field) \
+	offsetof(struct kgsl_devmemstore, field)
+
+
+/* timestamp id*/
+enum kgsl_timestamp_type {
+	KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */
+	KGSL_TIMESTAMP_RETIRED  = 0x00000002, /* end-of-pipeline timestamp*/
+	KGSL_TIMESTAMP_MAX      = 0x00000002,
+};
+
+/* property types - used with kgsl_device_getproperty */
+enum kgsl_property_type {
+	KGSL_PROP_DEVICE_INFO     = 0x00000001,
+	KGSL_PROP_DEVICE_SHADOW   = 0x00000002,
+	KGSL_PROP_DEVICE_POWER    = 0x00000003,
+	KGSL_PROP_SHMEM           = 0x00000004,
+	KGSL_PROP_SHMEM_APERTURES = 0x00000005,
+	KGSL_PROP_MMU_ENABLE 	  = 0x00000006,
+	KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
+	KGSL_PROP_VERSION         = 0x00000008,
+};
+
+struct kgsl_shadowprop {
+	unsigned int gpuaddr;
+	unsigned int size;
+	unsigned int flags; /* contains KGSL_FLAGS_ values */
+};
+
+struct kgsl_pwrlevel {
+	unsigned int gpu_freq;
+	unsigned int bus_freq;
+};
+
+struct kgsl_version {
+	unsigned int drv_major;
+	unsigned int drv_minor;
+	unsigned int dev_major;
+	unsigned int dev_minor;
+};
+
+#ifdef __KERNEL__
+
+#define KGSL_3D0_REG_MEMORY	"kgsl_3d0_reg_memory"
+#define KGSL_3D0_IRQ		"kgsl_3d0_irq"
+#define KGSL_2D0_REG_MEMORY	"kgsl_2d0_reg_memory"
+#define KGSL_2D0_IRQ		"kgsl_2d0_irq"
+#define KGSL_2D1_REG_MEMORY	"kgsl_2d1_reg_memory"
+#define KGSL_2D1_IRQ		"kgsl_2d1_irq"
+
+struct kgsl_grp_clk_name {
+	const char *clk;
+	const char *pclk;
+};
+
+struct kgsl_device_pwr_data {
+	struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
+	int init_level;
+	int num_levels;
+	int (*set_grp_async)(void);
+	unsigned int idle_timeout;
+	unsigned int nap_allowed;
+	unsigned int idle_pass;
+};
+
+struct kgsl_clk_data {
+	struct kgsl_grp_clk_name name;
+	struct msm_bus_scale_pdata *bus_scale_table;
+};
+
+struct kgsl_device_platform_data {
+	struct kgsl_device_pwr_data pwr_data;
+	struct kgsl_clk_data clk;
+	/* imem_clk_name is for 3d only, not used in 2d devices */
+	struct kgsl_grp_clk_name imem_clk_name;
+};
+
+#endif
+
+/* structure holds list of ibs */
+struct kgsl_ibdesc {
+	unsigned int gpuaddr;
+	void *hostptr;
+	unsigned int sizedwords;
+	unsigned int ctrl;
+};
+
+/* ioctls */
+#define KGSL_IOC_TYPE 0x09
+
+/* get misc info about the GPU
+   type should be a value from enum kgsl_property_type
+   value points to a structure that varies based on type
+   sizebytes is sizeof() that structure
+   for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo
+   this structure contaings hardware versioning info.
+   for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop
+   this is used to find mmap() offset and sizes for mapping
+   struct kgsl_memstore into userspace.
+*/
+struct kgsl_device_getproperty {
+	unsigned int type;
+	void  *value;
+	unsigned int sizebytes;
+};
+
+#define IOCTL_KGSL_DEVICE_GETPROPERTY \
+	_IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
+
+
+/* read a GPU register.
+   offsetwords it the 32 bit word offset from the beginning of the
+   GPU register space.
+ */
+struct kgsl_device_regread {
+	unsigned int offsetwords;
+	unsigned int value; /* output param */
+};
+
+#define IOCTL_KGSL_DEVICE_REGREAD \
+	_IOWR(KGSL_IOC_TYPE, 0x3, struct kgsl_device_regread)
+
+
+/* block until the GPU has executed past a given timestamp
+ * timeout is in milliseconds.
+ */
+struct kgsl_device_waittimestamp {
+	unsigned int timestamp;
+	unsigned int timeout;
+};
+
+#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \
+	_IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
+
+
+/* issue indirect commands to the GPU.
+ * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE
+ * ibaddr and sizedwords must specify a subset of a buffer created
+ * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM
+ * flags may be a mask of KGSL_CONTEXT_ values
+ * timestamp is a returned counter value which can be passed to
+ * other ioctls to determine when the commands have been executed by
+ * the GPU.
+ */
+struct kgsl_ringbuffer_issueibcmds {
+	unsigned int drawctxt_id;
+	unsigned int ibdesc_addr;
+	unsigned int numibs;
+	unsigned int timestamp; /*output param */
+	unsigned int flags;
+};
+
+#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \
+	_IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)
+
+/* read the most recently executed timestamp value
+ * type should be a value from enum kgsl_timestamp_type
+ */
+struct kgsl_cmdstream_readtimestamp {
+	unsigned int type;
+	unsigned int timestamp; /*output param */
+};
+
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \
+	_IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
+
+/* free memory when the GPU reaches a given timestamp.
+ * gpuaddr specify a memory region created by a
+ * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call
+ * type should be a value from enum kgsl_timestamp_type
+ */
+struct kgsl_cmdstream_freememontimestamp {
+	unsigned int gpuaddr;
+	unsigned int type;
+	unsigned int timestamp;
+};
+
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \
+	_IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
+
+/* Previous versions of this header had incorrectly defined
+   IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead
+   of a write only ioctl.  To ensure binary compatability, the following
+   #define will be used to intercept the incorrect ioctl
+*/
+
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \
+	_IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
+
+/* create a draw context, which is used to preserve GPU state.
+ * The flags field may contain a mask KGSL_CONTEXT_*  values
+ */
+struct kgsl_drawctxt_create {
+	unsigned int flags;
+	unsigned int drawctxt_id; /*output param */
+};
+
+#define IOCTL_KGSL_DRAWCTXT_CREATE \
+	_IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)
+
+/* destroy a draw context */
+struct kgsl_drawctxt_destroy {
+	unsigned int drawctxt_id;
+};
+
+#define IOCTL_KGSL_DRAWCTXT_DESTROY \
+	_IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
+
+/* add a block of pmem, fb, ashmem or user allocated address
+ * into the GPU address space */
+struct kgsl_map_user_mem {
+	int fd;
+	unsigned int gpuaddr;   /*output param */
+	unsigned int len;
+	unsigned int offset;
+	unsigned int hostptr;   /*input param */
+	enum kgsl_user_mem_type memtype;
+	unsigned int reserved;	/* May be required to add
+				params for another mem type */
+};
+
+#define IOCTL_KGSL_MAP_USER_MEM \
+	_IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem)
+
+/* add a block of pmem or fb into the GPU address space */
+struct kgsl_sharedmem_from_pmem {
+	int pmem_fd;
+	unsigned int gpuaddr;	/*output param */
+	unsigned int len;
+	unsigned int offset;
+};
+
+#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \
+	_IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem)
+
+/* remove memory from the GPU's address space */
+struct kgsl_sharedmem_free {
+	unsigned int gpuaddr;
+};
+
+#define IOCTL_KGSL_SHAREDMEM_FREE \
+	_IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
+
+
+struct kgsl_gmem_desc {
+	unsigned int x;
+	unsigned int y;
+	unsigned int width;
+	unsigned int height;
+	unsigned int pitch;
+};
+
+struct kgsl_buffer_desc {
+	void 			*hostptr;
+	unsigned int	gpuaddr;
+	int				size;
+	unsigned int	format;
+	unsigned int  	pitch;
+	unsigned int  	enabled;
+};
+
+struct kgsl_bind_gmem_shadow {
+	unsigned int drawctxt_id;
+	struct kgsl_gmem_desc gmem_desc;
+	unsigned int shadow_x;
+	unsigned int shadow_y;
+	struct kgsl_buffer_desc shadow_buffer;
+	unsigned int buffer_id;
+};
+
+#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \
+    _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)
+
+/* add a block of memory into the GPU address space */
+struct kgsl_sharedmem_from_vmalloc {
+	unsigned int gpuaddr;	/*output param */
+	unsigned int hostptr;
+	unsigned int flags;
+};
+
+#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \
+	_IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)
+
+#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \
+	_IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)
+
+struct kgsl_drawctxt_set_bin_base_offset {
+	unsigned int drawctxt_id;
+	unsigned int offset;
+};
+
+#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \
+	_IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
+
+enum kgsl_cmdwindow_type {
+	KGSL_CMDWINDOW_MIN     = 0x00000000,
+	KGSL_CMDWINDOW_2D      = 0x00000000,
+	KGSL_CMDWINDOW_3D      = 0x00000001, /* legacy */
+	KGSL_CMDWINDOW_MMU     = 0x00000002,
+	KGSL_CMDWINDOW_ARBITER = 0x000000FF,
+	KGSL_CMDWINDOW_MAX     = 0x000000FF,
+};
+
+/* write to the command window */
+struct kgsl_cmdwindow_write {
+	enum kgsl_cmdwindow_type target;
+	unsigned int addr;
+	unsigned int data;
+};
+
+#define IOCTL_KGSL_CMDWINDOW_WRITE \
+	_IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
+
+struct kgsl_gpumem_alloc {
+	unsigned long gpuaddr;
+	size_t size;
+	unsigned int flags;
+};
+
+#define IOCTL_KGSL_GPUMEM_ALLOC \
+	_IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc)
+
+#ifdef __KERNEL__
+#ifdef CONFIG_MSM_KGSL_DRM
+int kgsl_gem_obj_addr(int drm_fd, int handle, unsigned long *start,
+			unsigned long *len);
+#else
+#define kgsl_gem_obj_addr(...) 0
+#endif
+#endif
+#endif /* _MSM_KGSL_H */
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index fe722c1..9dced1a 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -15,25 +15,73 @@
 #define _MSM_MDP_H_
 
 #include <linux/types.h>
+#include <linux/fb.h>
 
 #define MSMFB_IOCTL_MAGIC 'm'
 #define MSMFB_GRP_DISP          _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
 #define MSMFB_BLIT              _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
+#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
+#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
+#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
+#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
+#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram)
+/* new ioctls's for set/get ccs matrix */
+#define MSMFB_GET_CCS_MATRIX  _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
+#define MSMFB_SET_CCS_MATRIX  _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
+#define MSMFB_OVERLAY_SET       _IOWR(MSMFB_IOCTL_MAGIC, 135, \
+						struct mdp_overlay)
+#define MSMFB_OVERLAY_UNSET     _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
+#define MSMFB_OVERLAY_PLAY      _IOW(MSMFB_IOCTL_MAGIC, 137, \
+						struct msmfb_overlay_data)
+#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
+					struct mdp_page_protection)
+#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
+					struct mdp_page_protection)
+#define MSMFB_OVERLAY_GET      _IOR(MSMFB_IOCTL_MAGIC, 140, \
+						struct mdp_overlay)
+#define MSMFB_OVERLAY_PLAY_ENABLE     _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
+#define MSMFB_OVERLAY_BLT       _IOWR(MSMFB_IOCTL_MAGIC, 142, \
+						struct msmfb_overlay_blt)
+#define MSMFB_OVERLAY_BLT_OFFSET     _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
+#define MSMFB_HISTOGRAM_START	_IO(MSMFB_IOCTL_MAGIC, 144)
+#define MSMFB_HISTOGRAM_STOP	_IO(MSMFB_IOCTL_MAGIC, 145)
+#define MSMFB_NOTIFY_UPDATE	_IOW(MSMFB_IOCTL_MAGIC, 146, unsigned int)
+
+#define MSMFB_OVERLAY_3D       _IOWR(MSMFB_IOCTL_MAGIC, 147, \
+						struct msmfb_overlay_3d)
+
+#define FB_TYPE_3D_PANEL 0x10101010
+#define MDP_IMGTYPE2_START 0x10000
+#define MSMFB_DRIVER_VERSION	0xF9E8D701
 
 enum {
-	MDP_RGB_565,		/* RGB 565 planar */
-	MDP_XRGB_8888,		/* RGB 888 padded */
-	MDP_Y_CBCR_H2V2,	/* Y and CbCr, pseudo planar w/ Cb is in MSB */
-	MDP_ARGB_8888,		/* ARGB 888 */
-	MDP_RGB_888,		/* RGB 888 planar */
-	MDP_Y_CRCB_H2V2,	/* Y and CrCb, pseudo planar w/ Cr is in MSB */
-	MDP_YCRYCB_H2V1,	/* YCrYCb interleave */
-	MDP_Y_CRCB_H2V1,	/* Y and CrCb, pseduo planar w/ Cr is in MSB */
-	MDP_Y_CBCR_H2V1,	/* Y and CrCb, pseduo planar w/ Cr is in MSB */
-	MDP_RGBA_8888,		/* ARGB 888 */
-	MDP_BGRA_8888,		/* ABGR 888 */
-	MDP_RGBX_8888,		/* RGBX 888 */
-	MDP_IMGTYPE_LIMIT	/* Non valid image type after this enum */
+	NOTIFY_UPDATE_START,
+	NOTIFY_UPDATE_STOP,
+};
+
+enum {
+	MDP_RGB_565,      /* RGB 565 planer */
+	MDP_XRGB_8888,    /* RGB 888 padded */
+	MDP_Y_CBCR_H2V2,  /* Y and CbCr, pseudo planer w/ Cb is in MSB */
+	MDP_ARGB_8888,    /* ARGB 888 */
+	MDP_RGB_888,      /* RGB 888 planer */
+	MDP_Y_CRCB_H2V2,  /* Y and CrCb, pseudo planer w/ Cr is in MSB */
+	MDP_YCRYCB_H2V1,  /* YCrYCb interleave */
+	MDP_Y_CRCB_H2V1,  /* Y and CrCb, pseduo planer w/ Cr is in MSB */
+	MDP_Y_CBCR_H2V1,   /* Y and CrCb, pseduo planer w/ Cr is in MSB */
+	MDP_RGBA_8888,    /* ARGB 888 */
+	MDP_BGRA_8888,	  /* ABGR 888 */
+	MDP_RGBX_8888,	  /* RGBX 888 */
+	MDP_Y_CRCB_H2V2_TILE,  /* Y and CrCb, pseudo planer tile */
+	MDP_Y_CBCR_H2V2_TILE,  /* Y and CbCr, pseudo planer tile */
+	MDP_Y_CR_CB_H2V2,  /* Y, Cr and Cb, planar */
+	MDP_Y_CB_CR_H2V2,  /* Y, Cb and Cr, planar */
+	MDP_Y_CRCB_H1V1,  /* Y and CrCb, pseduo planer w/ Cr is in MSB */
+	MDP_Y_CBCR_H1V1,  /* Y and CbCr, pseduo planer w/ Cb is in MSB */
+	MDP_IMGTYPE_LIMIT,
+	MDP_BGR_565 = MDP_IMGTYPE2_START,      /* BGR 565 planer */
+	MDP_FB_FORMAT,    /* framebuffer format */
+	MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
 };
 
 enum {
@@ -41,39 +89,182 @@
 	FB_IMG,
 };
 
-/* flag values */
-#define MDP_ROT_NOP	0
-#define MDP_FLIP_LR	0x1
-#define MDP_FLIP_UD	0x2
-#define MDP_ROT_90	0x4
-#define MDP_ROT_180	(MDP_FLIP_UD|MDP_FLIP_LR)
-#define MDP_ROT_270	(MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
-#define MDP_DITHER	0x8
-#define MDP_BLUR	0x10
+/* mdp_blit_req flag values */
+#define MDP_ROT_NOP 0
+#define MDP_FLIP_LR 0x1
+#define MDP_FLIP_UD 0x2
+#define MDP_ROT_90 0x4
+#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
+#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
+#define MDP_DITHER 0x8
+#define MDP_BLUR 0x10
+#define MDP_BLEND_FG_PREMULT 0x20000
+#define MDP_DEINTERLACE 0x80000000
+#define MDP_SHARPENING  0x40000000
+#define MDP_NO_DMA_BARRIER_START	0x20000000
+#define MDP_NO_DMA_BARRIER_END		0x10000000
+#define MDP_NO_BLIT			0x08000000
+#define MDP_BLIT_WITH_DMA_BARRIERS	0x000
+#define MDP_BLIT_WITH_NO_DMA_BARRIERS    \
+	(MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
+#define MDP_BLIT_SRC_GEM                0x04000000
+#define MDP_BLIT_DST_GEM                0x02000000
+#define MDP_BLIT_NON_CACHED		0x01000000
+#define MDP_OV_PIPE_SHARE		0x00800000
+#define MDP_DEINTERLACE_ODD		0x00400000
+#define MDP_OV_PLAY_NOWAIT		0x00200000
+#define MDP_SOURCE_ROTATED_90		0x00100000
 
-#define MDP_TRANSP_NOP	0xffffffff
-#define MDP_ALPHA_NOP	0xff
+#define MDP_TRANSP_NOP 0xffffffff
+#define MDP_ALPHA_NOP 0xff
+
+#define MDP_FB_PAGE_PROTECTION_NONCACHED         (0)
+#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE      (1)
+#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
+#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE    (3)
+#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE  (4)
+/* Sentinel: Don't use! */
+#define MDP_FB_PAGE_PROTECTION_INVALID           (5)
+/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
+#define MDP_NUM_FB_PAGE_PROTECTION_VALUES        (5)
 
 struct mdp_rect {
-	u32 x, y, w, h;
+	uint32_t x;
+	uint32_t y;
+	uint32_t w;
+	uint32_t h;
 };
 
 struct mdp_img {
-	u32 width, height, format, offset;
+	uint32_t width;
+	uint32_t height;
+	uint32_t format;
+	uint32_t offset;
 	int memory_id;		/* the file descriptor */
+	uint32_t priv;
 };
 
+/*
+ * {3x3} + {3} ccs matrix
+ */
+
+#define MDP_CCS_RGB2YUV 	0
+#define MDP_CCS_YUV2RGB 	1
+
+#define MDP_CCS_SIZE	9
+#define MDP_BV_SIZE	3
+
+struct mdp_ccs {
+	int direction;			/* MDP_CCS_RGB2YUV or YUV2RGB */
+	uint16_t ccs[MDP_CCS_SIZE];	/* 3x3 color coefficients */
+	uint16_t bv[MDP_BV_SIZE];	/* 1x3 bias vector */
+};
+
+/* The version of the mdp_blit_req structure so that
+ * user applications can selectively decide which functionality
+ * to include
+ */
+
+#define MDP_BLIT_REQ_VERSION 2
+
 struct mdp_blit_req {
 	struct mdp_img src;
 	struct mdp_img dst;
 	struct mdp_rect src_rect;
 	struct mdp_rect dst_rect;
-	u32 alpha, transp_mask, flags;
+	uint32_t alpha;
+	uint32_t transp_mask;
+	uint32_t flags;
+	int sharpening_strength;  /* -127 <--> 127, default 64 */
 };
 
 struct mdp_blit_req_list {
-	u32 count;
+	uint32_t count;
 	struct mdp_blit_req req[];
 };
 
-#endif /* _MSM_MDP_H_ */
+#define MSMFB_DATA_VERSION 2
+
+struct msmfb_data {
+	uint32_t offset;
+	int memory_id;
+	int id;
+	uint32_t flags;
+	uint32_t priv;
+};
+
+#define MSMFB_NEW_REQUEST -1
+
+struct msmfb_overlay_data {
+	uint32_t id;
+	struct msmfb_data data;
+	uint32_t version_key;
+	struct msmfb_data plane1_data;
+	struct msmfb_data plane2_data;
+};
+
+struct msmfb_img {
+	uint32_t width;
+	uint32_t height;
+	uint32_t format;
+};
+
+struct dpp_ctrl {
+	/*
+	 *'sharp_strength' has inputs = -128 <-> 127
+	 *  Increasingly positive values correlate with increasingly sharper
+	 *  picture. Increasingly negative values correlate with increasingly
+	 *  smoothed picture.
+	 */
+	int8_t sharp_strength;
+};
+
+struct mdp_overlay {
+	struct msmfb_img src;
+	struct mdp_rect src_rect;
+	struct mdp_rect dst_rect;
+	uint32_t z_order;	/* stage number */
+	uint32_t is_fg;		/* control alpha & transp */
+	uint32_t alpha;
+	uint32_t transp_mask;
+	uint32_t flags;
+	uint32_t id;
+	uint32_t user_data[8];
+	struct dpp_ctrl dpp;
+};
+
+struct msmfb_overlay_3d {
+	uint32_t is_3d;
+	uint32_t width;
+	uint32_t height;
+};
+
+
+struct msmfb_overlay_blt {
+	uint32_t enable;
+	uint32_t offset;
+	uint32_t width;
+	uint32_t height;
+	uint32_t bpp;
+};
+
+struct mdp_histogram {
+	uint32_t frame_cnt;
+	uint32_t bin_cnt;
+	uint32_t *r;
+	uint32_t *g;
+	uint32_t *b;
+};
+
+struct mdp_page_protection {
+	uint32_t page_protection;
+};
+
+#ifdef __KERNEL__
+
+/* get the framebuffer physical address information */
+int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num);
+
+#endif
+
+#endif /*_MSM_MDP_H_*/
diff --git a/include/linux/msm_q6vdec.h b/include/linux/msm_q6vdec.h
new file mode 100644
index 0000000..47b8163
--- /dev/null
+++ b/include/linux/msm_q6vdec.h
@@ -0,0 +1,277 @@
+#ifndef _MSM_VDEC_H_
+#define _MSM_VDEC_H_
+
+#include <linux/types.h>
+
+#define VDEC_IOCTL_MAGIC 'v'
+
+#define VDEC_IOCTL_INITIALIZE   _IOWR(VDEC_IOCTL_MAGIC, 1, struct vdec_init)
+#define VDEC_IOCTL_SETBUFFERS   _IOW(VDEC_IOCTL_MAGIC, 2, struct vdec_buffer)
+#define VDEC_IOCTL_QUEUE        _IOWR(VDEC_IOCTL_MAGIC, 3, \
+					struct vdec_input_buf)
+#define VDEC_IOCTL_REUSEFRAMEBUFFER  _IOW(VDEC_IOCTL_MAGIC, 4, unsigned int)
+#define VDEC_IOCTL_FLUSH        _IOW(VDEC_IOCTL_MAGIC, 5, unsigned int)
+#define VDEC_IOCTL_EOS          _IO(VDEC_IOCTL_MAGIC, 6)
+#define VDEC_IOCTL_GETMSG       _IOR(VDEC_IOCTL_MAGIC, 7, struct vdec_msg)
+#define VDEC_IOCTL_CLOSE        _IO(VDEC_IOCTL_MAGIC, 8)
+#define VDEC_IOCTL_FREEBUFFERS  _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_buf_info)
+#define VDEC_IOCTL_GETDECATTRIBUTES   _IOR(VDEC_IOCTL_MAGIC, 10, \
+						struct vdec_dec_attributes)
+#define VDEC_IOCTL_GETVERSION   _IOR(VDEC_IOCTL_MAGIC, 11, struct vdec_version)
+#define VDEC_IOCTL_SETPROPERTY _IOW \
+   (VDEC_IOCTL_MAGIC, 12, struct vdec_property_info)
+#define VDEC_IOCTL_GETPROPERTY _IOR  \
+   (VDEC_IOCTL_MAGIC, 13, struct vdec_property_info)
+#define VDEC_IOCTL_PERFORMANCE_CHANGE_REQ  _IOW(VDEC_IOCTL_MAGIC, 14, \
+						unsigned int)
+
+enum {
+	VDEC_FRAME_DECODE_OK,
+	VDEC_FRAME_DECODE_ERR,
+	VDEC_FATAL_ERR,
+	VDEC_FLUSH_FINISH,
+	VDEC_EOS,
+	VDEC_FRAME_FLUSH,
+	VDEC_STREAM_SWITCH,
+	VDEC_SUSPEND_FINISH,
+	VDEC_BUFFER_CONSUMED
+};
+
+enum {
+	VDEC_FLUSH_INPUT,
+	VDEC_FLUSH_OUTPUT,
+	VDEC_FLUSH_ALL
+};
+
+enum {
+	VDEC_BUFFER_TYPE_INPUT,
+	VDEC_BUFFER_TYPE_OUTPUT,
+	VDEC_BUFFER_TYPE_INTERNAL1,
+	VDEC_BUFFER_TYPE_INTERNAL2,
+};
+
+enum {
+	VDEC_QUEUE_SUCCESS,
+	VDEC_QUEUE_FAILED,
+	VDEC_QUEUE_BADSTATE,
+};
+
+enum {
+	VDEC_COLOR_FORMAT_NV21 = 0x01,
+	VDEC_COLOR_FORMAT_NV21_YAMOTO = 0x02
+   };
+
+enum vdec_property_id {
+	VDEC_FOURCC,
+	VDEC_PROFILE,
+	VDEC_LEVEL,
+	VDEC_DIMENSIONS,
+	VDEC_CWIN,
+	VDEC_INPUT_BUF_REQ,
+	VDEC_OUTPUT_BUF_REQ,
+	VDEC_LUMA_CHROMA_STRIDE,
+	VDEC_NUM_DAL_PORTS,
+	VDEC_PRIORITY,
+	VDEC_FRAME_ALIGNMENT
+};
+
+enum {
+	PERF_REQUEST_SET_MIN = 0,
+	PERF_REQUEST_LOWER,
+	PERF_REQUEST_RAISE,
+	PERF_REQUEST_SET_MAX
+};
+
+struct vdec_input_buf_info {
+	u32 offset;
+	u32 data;
+	u32 size;
+	int timestamp_lo;
+	int timestamp_hi;
+	int avsync_state;
+	u32 flags;
+};
+
+struct vdec_buf_desc {
+	u32 bufsize;
+	u32 num_min_buffers;
+	u32 num_max_buffers;
+};
+
+struct vdec_buf_req {
+	u32 max_input_queue_size;
+	struct vdec_buf_desc input;
+	struct vdec_buf_desc output;
+	struct vdec_buf_desc dec_req1;
+	struct vdec_buf_desc dec_req2;
+};
+
+struct vdec_region_info {
+	u32 src_id;
+	u32 offset;
+	u32 size;
+};
+
+struct vdec_config {
+	u32 fourcc;		/* video format */
+	u32 width;		/* source width */
+	u32 height;		/* source height */
+	u32 order;		/* render decoder order */
+	u32 notify_enable;	/* enable notify input buffer done event */
+	u32 vc1_rowbase;
+	u32 h264_startcode_detect;
+	u32 h264_nal_len_size;
+	u32 postproc_flag;
+	u32 fruc_enable;
+	u32 color_format;           /* used to set YUV color format */
+};
+
+struct vdec_vc1_panscan_regions {
+	int num;
+	int width[4];
+	int height[4];
+	int xoffset[4];
+	int yoffset[4];
+};
+
+struct vdec_cropping_window {
+	u32 x1;
+	u32 y1;
+	u32 x2;
+	u32 y2;
+};
+
+struct vdec_frame_info {
+	u32 status;		/* video decode status */
+	u32 offset;		/* buffer offset */
+	u32 data1;		/* user data field 1 */
+	u32 data2;		/* user data field 2 */
+	int timestamp_lo;	/* lower 32 bits timestamp, in msec */
+	int timestamp_hi;	/* higher 32 bits timestamp, in msec */
+	int cal_timestamp_lo;	/* lower 32 bits cal timestamp, in msec */
+	int cal_timestamp_hi;	/* higher  32 bits cal timestamp, in msec */
+	u32 dec_width;		/* frame roi width */
+	u32 dec_height;		/* frame roi height */
+	struct vdec_cropping_window cwin;	/* The frame cropping window */
+	u32 picture_type[2];	/* picture coding type */
+	u32 picture_format;	/* picture coding format */
+	u32 vc1_rangeY;		/* luma range mapping */
+	u32 vc1_rangeUV;	/* chroma range mapping */
+	u32 picture_resolution;	/* scaling factor */
+	u32 frame_disp_repeat;	/* how often repeated by disp */
+	u32 repeat_first_field;	/* repeat 1st field after 2nd */
+	u32 top_field_first;	/* top field displayed first */
+	u32 interframe_interp;	/* not for inter-frame interp */
+	struct vdec_vc1_panscan_regions panscan;	/* pan region */
+	u32 concealed_macblk_num;	/* number of concealed macro blk */
+	u32 flags;		/* input flags */
+	u32 performance_stats;	/* performance statistics returned by decoder */
+	u32 data3;              /* user data field 3 */
+};
+
+struct vdec_buf_info {
+	u32 buf_type;
+	struct vdec_region_info region;
+	u32 num_buf;
+	u32 islast;
+};
+
+struct vdec_buffer {
+	u32 pmem_id;
+	struct vdec_buf_info buf;
+};
+
+struct vdec_sequence {
+	u8 *header;
+	u32 len;
+};
+
+struct vdec_config_sps {
+	struct vdec_config cfg;
+	struct vdec_sequence seq;
+};
+
+#define VDEC_MSG_REUSEINPUTBUFFER 	1
+#define VDEC_MSG_FRAMEDONE 		2
+
+struct vdec_msg {
+	u32 id;
+
+	union {
+		/* id = VDEC_MSG_REUSEINPUTBUFFER */
+		u32 buf_id;
+		/* id = VDEC_MSG_FRAMEDONE */
+		struct vdec_frame_info vfr_info;
+	};
+};
+
+struct vdec_init {
+	struct vdec_config_sps sps_cfg;
+	struct vdec_buf_req *buf_req;
+};
+
+struct vdec_input_buf {
+	u32 pmem_id;
+	struct vdec_input_buf_info buffer;
+	struct vdec_queue_status *queue_status;
+};
+
+struct vdec_queue_status {
+	u32 status;
+};
+
+struct vdec_dec_attributes {
+	u32 fourcc;
+	u32 profile;
+	u32 level;
+	u32 dec_pic_width;
+	u32 dec_pic_height;
+	struct vdec_buf_desc input;
+	struct vdec_buf_desc output;
+	struct vdec_buf_desc dec_req1;
+	struct vdec_buf_desc dec_req2;
+};
+
+struct vdec_version {
+	u32 major;
+	u32 minor;
+};
+
+struct dal_vdec_rectangle {
+	u32 width;
+	u32 height;
+};
+
+struct stride_type {
+	u32 luma;
+	u32 chroma;
+};
+
+struct frame_alignment_type {
+	u32 luma_width;
+	u32 luma_height;
+	u32 chroma_width;
+	u32 chroma_height;
+	u32 chroma_offset;
+};
+
+union vdec_property {
+	u32 fourcc;
+	u32 profile;
+	u32 level;
+	struct dal_vdec_rectangle dim;
+	struct vdec_cropping_window cw;
+	struct vdec_buf_desc input_req;
+	struct vdec_buf_desc output_req;
+	struct stride_type stride;
+	u32 num_dal_ports;
+	u32 priority;
+	struct frame_alignment_type frame_alignment;
+	u32 def_type;
+};
+
+struct vdec_property_info {
+	enum vdec_property_id id;
+	union vdec_property property;
+};
+#endif /* _MSM_VDEC_H_ */
diff --git a/include/linux/msm_q6venc.h b/include/linux/msm_q6venc.h
new file mode 100644
index 0000000..c6bf20c
--- /dev/null
+++ b/include/linux/msm_q6venc.h
@@ -0,0 +1,303 @@
+#ifndef _MSM_VENC_H_
+#define _MSM_VENC_H_
+
+#include <linux/types.h>
+
+#define VENC_MAX_RECON_BUFFERS 2
+
+#define VENC_FLAG_EOS                   0x00000001
+#define VENC_FLAG_END_OF_FRAME          0x00000010
+#define VENC_FLAG_SYNC_FRAME            0x00000020
+#define VENC_FLAG_EXTRA_DATA            0x00000040
+#define VENC_FLAG_CODEC_CONFIG          0x00000080
+
+enum venc_flush_type {
+	VENC_FLUSH_INPUT,
+	VENC_FLUSH_OUTPUT,
+	VENC_FLUSH_ALL
+};
+
+enum venc_state_type {
+	VENC_STATE_PAUSE = 0x1,
+	VENC_STATE_START = 0x2,
+	VENC_STATE_STOP = 0x4
+};
+
+enum venc_event_type_enum {
+	VENC_EVENT_START_STATUS,
+	VENC_EVENT_STOP_STATUS,
+	VENC_EVENT_SUSPEND_STATUS,
+	VENC_EVENT_RESUME_STATUS,
+	VENC_EVENT_FLUSH_STATUS,
+	VENC_EVENT_RELEASE_INPUT,
+	VENC_EVENT_DELIVER_OUTPUT,
+	VENC_EVENT_UNKNOWN_STATUS
+};
+
+enum venc_status_code {
+	VENC_STATUS_SUCCESS,
+	VENC_STATUS_ERROR,
+	VENC_STATUS_INVALID_STATE,
+	VENC_STATUS_FLUSHING,
+	VENC_STATUS_INVALID_PARAM,
+	VENC_STATUS_CMD_QUEUE_FULL,
+	VENC_STATUS_CRITICAL,
+	VENC_STATUS_INSUFFICIENT_RESOURCES,
+	VENC_STATUS_TIMEOUT
+};
+
+enum venc_msg_code {
+	VENC_MSG_INDICATION,
+	VENC_MSG_INPUT_BUFFER_DONE,
+	VENC_MSG_OUTPUT_BUFFER_DONE,
+	VENC_MSG_NEED_OUTPUT_BUFFER,
+	VENC_MSG_FLUSH,
+	VENC_MSG_START,
+	VENC_MSG_STOP,
+	VENC_MSG_PAUSE,
+	VENC_MSG_RESUME,
+	VENC_MSG_STOP_READING_MSG
+};
+
+enum venc_error_code {
+	VENC_S_SUCCESS,
+	VENC_S_EFAIL,
+	VENC_S_EFATAL,
+	VENC_S_EBADPARAM,
+	VENC_S_EINVALSTATE,
+	VENC_S_ENOSWRES,
+	VENC_S_ENOHWRES,
+	VENC_S_EBUFFREQ,
+	VENC_S_EINVALCMD,
+	VENC_S_ETIMEOUT,
+	VENC_S_ENOREATMPT,
+	VENC_S_ENOPREREQ,
+	VENC_S_ECMDQFULL,
+	VENC_S_ENOTSUPP,
+	VENC_S_ENOTIMPL,
+	VENC_S_ENOTPMEM,
+	VENC_S_EFLUSHED,
+	VENC_S_EINSUFBUF,
+	VENC_S_ESAMESTATE,
+	VENC_S_EINVALTRANS
+};
+
+enum venc_mem_region_enum {
+	VENC_PMEM_EBI1,
+	VENC_PMEM_SMI
+};
+
+struct venc_buf_type {
+	u32 region;
+	u32 phys;
+	u32 size;
+	int offset;
+};
+
+struct venc_qp_range {
+	u32 min_qp;
+	u32 max_qp;
+};
+
+struct venc_frame_rate {
+	u32 frame_rate_num;
+	u32 frame_rate_den;
+};
+
+struct venc_slice_info {
+	u32 slice_mode;
+	u32 units_per_slice;
+};
+
+struct venc_extra_data {
+	u32 slice_extra_data_flag;
+	u32 slice_client_data1;
+	u32 slice_client_data2;
+	u32 slice_client_data3;
+	u32 none_extra_data_flag;
+	u32 none_client_data1;
+	u32 none_client_data2;
+	u32 none_client_data3;
+};
+
+struct venc_common_config {
+	u32 standard;
+	u32 input_frame_height;
+	u32 input_frame_width;
+	u32 output_frame_height;
+	u32 output_frame_width;
+	u32 rotation_angle;
+	u32 intra_period;
+	u32 rate_control;
+	struct venc_frame_rate frame_rate;
+	u32 bitrate;
+	struct venc_qp_range qp_range;
+	u32 iframe_qp;
+	u32 pframe_qp;
+	struct venc_slice_info slice_config;
+	struct venc_extra_data extra_data;
+};
+
+struct venc_nonio_buf_config {
+	struct venc_buf_type recon_buf1;
+	struct venc_buf_type recon_buf2;
+	struct venc_buf_type wb_buf;
+	struct venc_buf_type cmd_buf;
+	struct venc_buf_type vlc_buf;
+};
+
+struct venc_mpeg4_config {
+	u32 profile;
+	u32 level;
+	u32 time_resolution;
+	u32 ac_prediction;
+	u32 hec_interval;
+	u32 data_partition;
+	u32 short_header;
+	u32 rvlc_enable;
+};
+
+struct venc_h263_config {
+	u32 profile;
+	u32 level;
+};
+
+struct venc_h264_config {
+	u32 profile;
+	u32 level;
+	u32 max_nal;
+	u32 idr_period;
+};
+
+struct venc_pmem {
+	int src;
+	int fd;
+	u32 offset;
+	void *virt;
+	void *phys;
+	u32 size;
+};
+
+struct venc_buffer {
+	unsigned char *ptr_buffer;
+	u32 size;
+	u32 len;
+	u32 offset;
+	long long time_stamp;
+	u32 flags;
+	u32 client_data;
+
+};
+
+struct venc_buffers {
+	struct venc_pmem recon_buf[VENC_MAX_RECON_BUFFERS];
+	struct venc_pmem wb_buf;
+	struct venc_pmem cmd_buf;
+	struct venc_pmem vlc_buf;
+};
+
+struct venc_buffer_flush {
+	u32 flush_mode;
+};
+
+union venc_msg_data {
+	struct venc_buffer buf;
+	struct venc_buffer_flush flush_ret;
+
+};
+
+struct venc_msg {
+	u32 status_code;
+	u32 msg_code;
+	u32 msg_data_size;
+	union venc_msg_data msg_data;
+};
+
+union venc_codec_config {
+	struct venc_mpeg4_config mpeg4_params;
+	struct venc_h263_config h263_params;
+	struct venc_h264_config h264_params;
+};
+
+struct venc_q6_config {
+	struct venc_common_config config_params;
+	union venc_codec_config codec_params;
+	struct venc_nonio_buf_config buf_params;
+	void *callback_event;
+};
+
+struct venc_hdr_config {
+	struct venc_common_config config_params;
+	union venc_codec_config codec_params;
+};
+
+struct venc_init_config {
+	struct venc_q6_config q6_config;
+	struct venc_buffers q6_bufs;
+};
+
+struct venc_seq_config {
+	int size;
+	struct venc_pmem buf;
+	struct venc_q6_config q6_config;
+};
+
+struct venc_version {
+	u32 major;
+	u32 minor;
+};
+
+#define VENC_IOCTL_MAGIC 'V'
+
+#define VENC_IOCTL_CMD_READ_NEXT_MSG \
+	_IOWR(VENC_IOCTL_MAGIC, 1, struct venc_msg)
+
+#define VENC_IOCTL_CMD_STOP_READ_MSG  _IO(VENC_IOCTL_MAGIC, 2)
+
+#define VENC_IOCTL_SET_INPUT_BUFFER \
+	_IOW(VENC_IOCTL_MAGIC, 3, struct venc_pmem)
+
+#define VENC_IOCTL_SET_OUTPUT_BUFFER \
+	_IOW(VENC_IOCTL_MAGIC, 4, struct venc_pmem)
+
+#define VENC_IOCTL_CMD_START _IOW(VENC_IOCTL_MAGIC, 5, struct venc_init_config)
+
+#define VENC_IOCTL_CMD_ENCODE_FRAME \
+	_IOW(VENC_IOCTL_MAGIC, 6, struct venc_buffer)
+
+#define VENC_IOCTL_CMD_FILL_OUTPUT_BUFFER \
+	_IOW(VENC_IOCTL_MAGIC, 7, struct venc_buffer)
+
+#define VENC_IOCTL_CMD_FLUSH \
+	_IOW(VENC_IOCTL_MAGIC, 8, struct venc_buffer_flush)
+
+#define VENC_IOCTL_CMD_PAUSE _IO(VENC_IOCTL_MAGIC, 9)
+
+#define VENC_IOCTL_CMD_RESUME _IO(VENC_IOCTL_MAGIC, 10)
+
+#define VENC_IOCTL_CMD_STOP _IO(VENC_IOCTL_MAGIC, 11)
+
+#define VENC_IOCTL_SET_INTRA_PERIOD \
+	_IOW(VENC_IOCTL_MAGIC, 12, int)
+
+#define VENC_IOCTL_CMD_REQUEST_IFRAME _IO(VENC_IOCTL_MAGIC, 13)
+
+#define VENC_IOCTL_GET_SEQUENCE_HDR \
+	_IOWR(VENC_IOCTL_MAGIC, 14, struct venc_seq_config)
+
+#define VENC_IOCTL_SET_INTRA_REFRESH \
+	_IOW(VENC_IOCTL_MAGIC, 15, int)
+
+#define VENC_IOCTL_SET_FRAME_RATE \
+	_IOW(VENC_IOCTL_MAGIC, 16, struct venc_frame_rate)
+
+#define VENC_IOCTL_SET_TARGET_BITRATE \
+	_IOW(VENC_IOCTL_MAGIC, 17, int)
+
+#define VENC_IOCTL_SET_QP_RANGE \
+	_IOW(VENC_IOCTL_MAGIC, 18, struct venc_qp_range)
+
+#define VENC_IOCTL_GET_VERSION \
+	 _IOR(VENC_IOCTL_MAGIC, 19, struct venc_version)
+
+#endif
diff --git a/include/linux/msm_rmnet.h b/include/linux/msm_rmnet.h
new file mode 100644
index 0000000..9f52464
--- /dev/null
+++ b/include/linux/msm_rmnet.h
@@ -0,0 +1,54 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MSM_RMNET_H_
+#define _MSM_RMNET_H_
+
+/* Bitmap macros for RmNET driver operation mode. */
+#define RMNET_MODE_NONE     (0x00)
+#define RMNET_MODE_LLP_ETH  (0x01)
+#define RMNET_MODE_LLP_IP   (0x02)
+#define RMNET_MODE_QOS      (0x04)
+#define RMNET_MODE_MASK     (RMNET_MODE_LLP_ETH | \
+			     RMNET_MODE_LLP_IP  | \
+			     RMNET_MODE_QOS)
+
+#define RMNET_IS_MODE_QOS(mode)  \
+	((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS)
+#define RMNET_IS_MODE_IP(mode)   \
+	((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP)
+
+/* IOCTL command enum
+ * Values chosen to not conflict with other drivers in the ecosystem */
+enum rmnet_ioctl_cmds_e {
+	RMNET_IOCTL_SET_LLP_ETHERNET = 0x000089F1, /* Set Ethernet protocol  */
+	RMNET_IOCTL_SET_LLP_IP       = 0x000089F2, /* Set RAWIP protocol     */
+	RMNET_IOCTL_GET_LLP          = 0x000089F3, /* Get link protocol      */
+	RMNET_IOCTL_SET_QOS_ENABLE   = 0x000089F4, /* Set QoS header enabled */
+	RMNET_IOCTL_SET_QOS_DISABLE  = 0x000089F5, /* Set QoS header disabled*/
+	RMNET_IOCTL_GET_QOS          = 0x000089F6, /* Get QoS header state   */
+	RMNET_IOCTL_GET_OPMODE       = 0x000089F7, /* Get operation mode     */
+	RMNET_IOCTL_OPEN             = 0x000089F8, /* Open transport port    */
+	RMNET_IOCTL_CLOSE            = 0x000089F9, /* Close transport port   */
+	RMNET_IOCTL_MAX
+};
+
+/* QMI QoS header definition */
+#define QMI_QOS_HDR_S  __attribute((__packed__)) qmi_qos_hdr_s
+struct QMI_QOS_HDR_S {
+	unsigned char    version;
+	unsigned char    flags;
+	unsigned long    flow_id;
+};
+
+#endif /* _MSM_RMNET_H_ */
diff --git a/include/linux/msm_rotator.h b/include/linux/msm_rotator.h
new file mode 100644
index 0000000..98352b7
--- /dev/null
+++ b/include/linux/msm_rotator.h
@@ -0,0 +1,57 @@
+#ifndef __MSM_ROTATOR_H__
+
+#include <linux/types.h>
+#include <linux/msm_mdp.h>
+
+#define MSM_ROTATOR_IOCTL_MAGIC 'R'
+
+#define MSM_ROTATOR_IOCTL_START   \
+		_IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info)
+#define MSM_ROTATOR_IOCTL_ROTATE   \
+		_IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info)
+#define MSM_ROTATOR_IOCTL_FINISH   \
+		_IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int)
+
+#define ROTATOR_VERSION_01	0xA5B4C301
+
+enum rotator_clk_type {
+	ROTATOR_CORE_CLK,
+	ROTATOR_AXI_CLK,
+	ROTATOR_PCLK,
+	ROTATOR_IMEM_CLK
+};
+
+struct msm_rotator_img_info {
+	unsigned int session_id;
+	struct msmfb_img  src;
+	struct msmfb_img  dst;
+	struct mdp_rect src_rect;
+	unsigned int    dst_x;
+	unsigned int    dst_y;
+	unsigned char   rotations;
+	int enable;
+};
+
+struct msm_rotator_data_info {
+	int session_id;
+	struct msmfb_data src;
+	struct msmfb_data dst;
+	unsigned int version_key;
+	struct msmfb_data src_chroma;
+	struct msmfb_data dst_chroma;
+};
+
+struct msm_rot_clocks {
+	const char *clk_name;
+	enum rotator_clk_type clk_type;
+	unsigned int clk_rate;
+};
+
+struct msm_rotator_platform_data {
+	unsigned int number_of_clocks;
+	unsigned int hardware_version_number;
+	struct msm_rot_clocks *rotator_clks;
+	const char *regulator_name;
+};
+#endif
+
diff --git a/include/linux/msm_rpcrouter.h b/include/linux/msm_rpcrouter.h
new file mode 100644
index 0000000..01d3809
--- /dev/null
+++ b/include/linux/msm_rpcrouter.h
@@ -0,0 +1,50 @@
+/* include/linux/msm_rpcrouter.h
+ *
+ * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ * Copyright (C) 2007 Google, Inc.
+ * Author: San Mehat <san@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_MSM_RPCROUTER_H
+#define __LINUX_MSM_RPCROUTER_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define RPC_ROUTER_VERSION_V1 0x00010000
+
+struct rpcrouter_ioctl_server_args {
+	uint32_t prog;
+	uint32_t vers;
+};
+
+#define RPC_ROUTER_IOCTL_MAGIC (0xC1)
+
+#define RPC_ROUTER_IOCTL_GET_VERSION \
+	_IOR(RPC_ROUTER_IOCTL_MAGIC, 0, unsigned int)
+
+#define RPC_ROUTER_IOCTL_GET_MTU \
+	_IOR(RPC_ROUTER_IOCTL_MAGIC, 1, unsigned int)
+
+#define RPC_ROUTER_IOCTL_REGISTER_SERVER \
+	_IOWR(RPC_ROUTER_IOCTL_MAGIC, 2, unsigned int)
+
+#define RPC_ROUTER_IOCTL_UNREGISTER_SERVER \
+	_IOWR(RPC_ROUTER_IOCTL_MAGIC, 3, unsigned int)
+
+#define RPC_ROUTER_IOCTL_CLEAR_NETRESET \
+	_IOWR(RPC_ROUTER_IOCTL_MAGIC, 4, unsigned int)
+
+#define RPC_ROUTER_IOCTL_GET_CURR_PKT_SIZE \
+	_IOR(RPC_ROUTER_IOCTL_MAGIC, 5, unsigned int)
+
+#endif
diff --git a/include/linux/msm_smd_pkt.h b/include/linux/msm_smd_pkt.h
new file mode 100644
index 0000000..dc7328f
--- /dev/null
+++ b/include/linux/msm_smd_pkt.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_MSM_SMD_PKT_H
+#define __LINUX_MSM_SMD_PKT_H
+
+#include <linux/ioctl.h>
+
+#define SMD_PKT_IOCTL_MAGIC (0xC2)
+
+#define SMD_PKT_IOCTL_BLOCKING_WRITE \
+	_IOR(SMD_PKT_IOCTL_MAGIC, 0, unsigned int)
+
+#endif /* __LINUX_MSM_SMD_PKT_H */
diff --git a/include/linux/msm_ssbi.h b/include/linux/msm_ssbi.h
new file mode 100644
index 0000000..e90398a
--- /dev/null
+++ b/include/linux/msm_ssbi.h
@@ -0,0 +1,50 @@
+/* Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Author: Dima Zavin <dima@android.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_MSM_SSBI_H
+#define _LINUX_MSM_SSBI_H
+
+#include <linux/types.h>
+
+struct msm_ssbi_slave_info {
+	const char	*name;
+	void		*platform_data;
+};
+
+enum msm_ssbi_controller_type {
+	MSM_SBI_CTRL_SSBI = 0,
+	MSM_SBI_CTRL_SSBI2,
+	MSM_SBI_CTRL_PMIC_ARBITER,
+	FSM_SBI_CTRL_SSBI,
+};
+
+struct msm_ssbi_platform_data {
+	struct msm_ssbi_slave_info	slave;
+	enum msm_ssbi_controller_type controller_type;
+};
+
+#ifdef CONFIG_MSM_SSBI
+int msm_ssbi_write(struct device *dev, u16 addr, u8 *buf, int len);
+int msm_ssbi_read(struct device *dev, u16 addr, u8 *buf, int len);
+#else
+static inline int msm_ssbi_write(struct device *dev, u16 addr, u8 *buf, int len)
+{
+	return -ENXIO;
+}
+static inline int msm_ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
+{
+	return -ENXIO;
+}
+#endif
+#endif
diff --git a/include/linux/msm_vidc_dec.h b/include/linux/msm_vidc_dec.h
new file mode 100644
index 0000000..fb781f4
--- /dev/null
+++ b/include/linux/msm_vidc_dec.h
@@ -0,0 +1,547 @@
+#ifndef _MSM_VIDC_DEC_H_
+#define _MSM_VIDC_DEC_H_
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/* STATUS CODES */
+/* Base value for status codes */
+#define VDEC_S_BASE	0x40000000
+/* Success */
+#define VDEC_S_SUCCESS	(VDEC_S_BASE)
+/* General failure */
+#define VDEC_S_EFAIL	(VDEC_S_BASE + 1)
+/* Fatal irrecoverable  failure. Need to  tear down session. */
+#define VDEC_S_EFATAL   (VDEC_S_BASE + 2)
+/* Error detected in the passed  parameters */
+#define VDEC_S_EBADPARAM	(VDEC_S_BASE + 3)
+/* Command called in invalid  state. */
+#define VDEC_S_EINVALSTATE	(VDEC_S_BASE + 4)
+ /* Insufficient OS  resources - thread, memory etc. */
+#define VDEC_S_ENOSWRES	(VDEC_S_BASE + 5)
+ /* Insufficient HW resources -  core capacity  maxed  out. */
+#define VDEC_S_ENOHWRES	(VDEC_S_BASE + 6)
+/* Invalid command  called */
+#define VDEC_S_EINVALCMD	(VDEC_S_BASE + 7)
+/* Command timeout. */
+#define VDEC_S_ETIMEOUT	(VDEC_S_BASE + 8)
+/* Pre-requirement is  not met for API. */
+#define VDEC_S_ENOPREREQ	(VDEC_S_BASE + 9)
+/* Command queue is full. */
+#define VDEC_S_ECMDQFULL	(VDEC_S_BASE + 10)
+/* Command is not supported  by this driver */
+#define VDEC_S_ENOTSUPP	(VDEC_S_BASE + 11)
+/* Command is not implemented by thedriver. */
+#define VDEC_S_ENOTIMPL	(VDEC_S_BASE + 12)
+/* Command is not implemented by the driver.  */
+#define VDEC_S_BUSY	(VDEC_S_BASE + 13)
+
+#define VDEC_INTF_VER	1
+#define VDEC_MSG_BASE	0x0000000
+/* Codes to identify asynchronous message responses and events that driver
+  wants to communicate to the app.*/
+#define VDEC_MSG_INVALID	(VDEC_MSG_BASE + 0)
+#define VDEC_MSG_RESP_INPUT_BUFFER_DONE	(VDEC_MSG_BASE + 1)
+#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE	(VDEC_MSG_BASE + 2)
+#define VDEC_MSG_RESP_INPUT_FLUSHED	(VDEC_MSG_BASE + 3)
+#define VDEC_MSG_RESP_OUTPUT_FLUSHED	(VDEC_MSG_BASE + 4)
+#define VDEC_MSG_RESP_FLUSH_INPUT_DONE	(VDEC_MSG_BASE + 5)
+#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE	(VDEC_MSG_BASE + 6)
+#define VDEC_MSG_RESP_START_DONE	(VDEC_MSG_BASE + 7)
+#define VDEC_MSG_RESP_STOP_DONE	(VDEC_MSG_BASE + 8)
+#define VDEC_MSG_RESP_PAUSE_DONE	(VDEC_MSG_BASE + 9)
+#define VDEC_MSG_RESP_RESUME_DONE	(VDEC_MSG_BASE + 10)
+#define VDEC_MSG_RESP_RESOURCE_LOADED	(VDEC_MSG_BASE + 11)
+#define VDEC_EVT_RESOURCES_LOST	(VDEC_MSG_BASE + 12)
+#define VDEC_MSG_EVT_CONFIG_CHANGED	(VDEC_MSG_BASE + 13)
+#define VDEC_MSG_EVT_HW_ERROR	(VDEC_MSG_BASE + 14)
+#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED	(VDEC_MSG_BASE + 15)
+
+/*Buffer flags bits masks.*/
+#define VDEC_BUFFERFLAG_EOS	0x00000001
+#define VDEC_BUFFERFLAG_DECODEONLY	0x00000004
+#define VDEC_BUFFERFLAG_DATACORRUPT	0x00000008
+#define VDEC_BUFFERFLAG_ENDOFFRAME	0x00000010
+#define VDEC_BUFFERFLAG_SYNCFRAME	0x00000020
+#define VDEC_BUFFERFLAG_EXTRADATA	0x00000040
+#define VDEC_BUFFERFLAG_CODECCONFIG	0x00000080
+
+/*Post processing flags bit masks*/
+#define VDEC_EXTRADATA_NONE 0x001
+#define VDEC_EXTRADATA_QP 0x004
+#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008
+#define VDEC_EXTRADATA_SEI 0x010
+#define VDEC_EXTRADATA_VUI 0x020
+#define VDEC_EXTRADATA_VC1 0x040
+
+#define VDEC_CMDBASE	0x800
+#define VDEC_CMD_SET_INTF_VERSION	(VDEC_CMDBASE)
+
+#define VDEC_IOCTL_MAGIC 'v'
+
+struct vdec_ioctl_msg {
+	void __user *in;
+	void __user *out;
+};
+
+/* CMD params: InputParam:enum vdec_codec
+   OutputParam: struct vdec_profile_level*/
+#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \
+	_IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg)
+
+/*CMD params:InputParam: NULL
+  OutputParam: uint32_t(bitmask)*/
+#define VDEC_IOCTL_GET_INTERLACE_FORMAT \
+	_IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg)
+
+/* CMD params: InputParam:  enum vdec_codec
+   OutputParam: struct vdec_profile_level*/
+#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \
+	_IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg)
+
+/*CMD params: SET: InputParam: enum vdec_output_fromat  OutputParam: NULL
+  GET:  InputParam: NULL OutputParam: enum vdec_output_fromat*/
+#define VDEC_IOCTL_SET_OUTPUT_FORMAT \
+	_IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_OUTPUT_FORMAT \
+	_IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg)
+
+/*CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL
+  GET: InputParam: NULL OutputParam: enum vdec_codec*/
+#define VDEC_IOCTL_SET_CODEC \
+	_IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_CODEC \
+	_IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg)
+
+/*CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL
+ GET: InputParam: NULL outputparam: struct vdec_picsize*/
+#define VDEC_IOCTL_SET_PICRES \
+	_IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_PICRES \
+	_IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_EXTRADATA \
+	_IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_EXTRADATA \
+	_IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_SEQUENCE_HEADER \
+	_IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg)
+
+/* CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL
+   GET: InputParam - NULL, OutputParam - vdec_allocatorproperty*/
+#define VDEC_IOCTL_SET_BUFFER_REQ \
+	_IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_BUFFER_REQ \
+	_IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg)
+/* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */
+#define VDEC_IOCTL_ALLOCATE_BUFFER \
+	_IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg)
+/* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/
+#define VDEC_IOCTL_FREE_BUFFER \
+	_IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg)
+
+/*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/
+#define VDEC_IOCTL_SET_BUFFER \
+	_IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg)
+
+/* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/
+#define VDEC_IOCTL_FILL_OUTPUT_BUFFER \
+	_IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg)
+
+/*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/
+#define VDEC_IOCTL_DECODE_FRAME \
+	_IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19)
+#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20)
+#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21)
+#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22)
+#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23)
+
+/*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */
+#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg)
+
+/* ========================================================
+ * IOCTL for getting asynchronous notification from driver
+ * ========================================================*/
+
+/*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/
+#define VDEC_IOCTL_GET_NEXT_MSG \
+	_IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26)
+
+#define VDEC_IOCTL_GET_NUMBER_INSTANCES \
+	_IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_PICTURE_ORDER \
+	_IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_FRAME_RATE \
+	_IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_H264_MV_BUFFER \
+	_IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_FREE_H264_MV_BUFFER \
+	_IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_GET_MV_BUFFER_SIZE  \
+	_IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_IDR_ONLY_DECODING \
+	_IO(VDEC_IOCTL_MAGIC, 33)
+
+#define VDEC_IOCTL_SET_CONT_ON_RECONFIG  \
+	_IO(VDEC_IOCTL_MAGIC, 34)
+
+enum vdec_picture {
+	PICTURE_TYPE_I,
+	PICTURE_TYPE_P,
+	PICTURE_TYPE_B,
+	PICTURE_TYPE_BI,
+	PICTURE_TYPE_SKIP,
+	PICTURE_TYPE_UNKNOWN
+};
+
+enum vdec_buffer {
+	VDEC_BUFFER_TYPE_INPUT,
+	VDEC_BUFFER_TYPE_OUTPUT
+};
+
+struct vdec_allocatorproperty {
+	enum vdec_buffer buffer_type;
+	uint32_t mincount;
+	uint32_t maxcount;
+	uint32_t actualcount;
+	size_t buffer_size;
+	uint32_t alignment;
+	uint32_t buf_poolid;
+};
+
+struct vdec_bufferpayload {
+	void __user *bufferaddr;
+	size_t buffer_len;
+	int pmem_fd;
+	size_t offset;
+	size_t mmaped_size;
+};
+
+struct vdec_setbuffer_cmd {
+	enum vdec_buffer buffer_type;
+	struct vdec_bufferpayload buffer;
+};
+
+struct vdec_fillbuffer_cmd {
+	struct vdec_bufferpayload buffer;
+	void *client_data;
+};
+
+enum vdec_bufferflush {
+	VDEC_FLUSH_TYPE_INPUT,
+	VDEC_FLUSH_TYPE_OUTPUT,
+	VDEC_FLUSH_TYPE_ALL
+};
+
+enum vdec_codec {
+	VDEC_CODECTYPE_H264 = 0x1,
+	VDEC_CODECTYPE_H263 = 0x2,
+	VDEC_CODECTYPE_MPEG4 = 0x3,
+	VDEC_CODECTYPE_DIVX_3 = 0x4,
+	VDEC_CODECTYPE_DIVX_4 = 0x5,
+	VDEC_CODECTYPE_DIVX_5 = 0x6,
+	VDEC_CODECTYPE_DIVX_6 = 0x7,
+	VDEC_CODECTYPE_XVID = 0x8,
+	VDEC_CODECTYPE_MPEG1 = 0x9,
+	VDEC_CODECTYPE_MPEG2 = 0xa,
+	VDEC_CODECTYPE_VC1 = 0xb,
+	VDEC_CODECTYPE_VC1_RCV = 0xc
+};
+
+enum vdec_mpeg2_profile {
+	VDEC_MPEG2ProfileSimple = 0x1,
+	VDEC_MPEG2ProfileMain = 0x2,
+	VDEC_MPEG2Profile422 = 0x4,
+	VDEC_MPEG2ProfileSNR = 0x8,
+	VDEC_MPEG2ProfileSpatial = 0x10,
+	VDEC_MPEG2ProfileHigh = 0x20,
+	VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000,
+	VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000,
+	VDEC_MPEG2ProfileMax = 0x7FFFFFFF
+};
+
+enum vdec_mpeg2_level {
+
+	VDEC_MPEG2LevelLL = 0x1,
+	VDEC_MPEG2LevelML = 0x2,
+	VDEC_MPEG2LevelH14 = 0x4,
+	VDEC_MPEG2LevelHL = 0x8,
+	VDEC_MPEG2LevelKhronosExtensions = 0x6F000000,
+	VDEC_MPEG2LevelVendorStartUnused = 0x7F000000,
+	VDEC_MPEG2LevelMax = 0x7FFFFFFF
+};
+
+enum vdec_mpeg4_profile {
+	VDEC_MPEG4ProfileSimple = 0x01,
+	VDEC_MPEG4ProfileSimpleScalable = 0x02,
+	VDEC_MPEG4ProfileCore = 0x04,
+	VDEC_MPEG4ProfileMain = 0x08,
+	VDEC_MPEG4ProfileNbit = 0x10,
+	VDEC_MPEG4ProfileScalableTexture = 0x20,
+	VDEC_MPEG4ProfileSimpleFace = 0x40,
+	VDEC_MPEG4ProfileSimpleFBA = 0x80,
+	VDEC_MPEG4ProfileBasicAnimated = 0x100,
+	VDEC_MPEG4ProfileHybrid = 0x200,
+	VDEC_MPEG4ProfileAdvancedRealTime = 0x400,
+	VDEC_MPEG4ProfileCoreScalable = 0x800,
+	VDEC_MPEG4ProfileAdvancedCoding = 0x1000,
+	VDEC_MPEG4ProfileAdvancedCore = 0x2000,
+	VDEC_MPEG4ProfileAdvancedScalable = 0x4000,
+	VDEC_MPEG4ProfileAdvancedSimple = 0x8000,
+	VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000,
+	VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000,
+	VDEC_MPEG4ProfileMax = 0x7FFFFFFF
+};
+
+enum vdec_mpeg4_level {
+	VDEC_MPEG4Level0 = 0x01,
+	VDEC_MPEG4Level0b = 0x02,
+	VDEC_MPEG4Level1 = 0x04,
+	VDEC_MPEG4Level2 = 0x08,
+	VDEC_MPEG4Level3 = 0x10,
+	VDEC_MPEG4Level4 = 0x20,
+	VDEC_MPEG4Level4a = 0x40,
+	VDEC_MPEG4Level5 = 0x80,
+	VDEC_MPEG4LevelKhronosExtensions = 0x6F000000,
+	VDEC_MPEG4LevelVendorStartUnused = 0x7F000000,
+	VDEC_MPEG4LevelMax = 0x7FFFFFFF
+};
+
+enum vdec_avc_profile {
+	VDEC_AVCProfileBaseline = 0x01,
+	VDEC_AVCProfileMain = 0x02,
+	VDEC_AVCProfileExtended = 0x04,
+	VDEC_AVCProfileHigh = 0x08,
+	VDEC_AVCProfileHigh10 = 0x10,
+	VDEC_AVCProfileHigh422 = 0x20,
+	VDEC_AVCProfileHigh444 = 0x40,
+	VDEC_AVCProfileKhronosExtensions = 0x6F000000,
+	VDEC_AVCProfileVendorStartUnused = 0x7F000000,
+	VDEC_AVCProfileMax = 0x7FFFFFFF
+};
+
+enum vdec_avc_level {
+	VDEC_AVCLevel1 = 0x01,
+	VDEC_AVCLevel1b = 0x02,
+	VDEC_AVCLevel11 = 0x04,
+	VDEC_AVCLevel12 = 0x08,
+	VDEC_AVCLevel13 = 0x10,
+	VDEC_AVCLevel2 = 0x20,
+	VDEC_AVCLevel21 = 0x40,
+	VDEC_AVCLevel22 = 0x80,
+	VDEC_AVCLevel3 = 0x100,
+	VDEC_AVCLevel31 = 0x200,
+	VDEC_AVCLevel32 = 0x400,
+	VDEC_AVCLevel4 = 0x800,
+	VDEC_AVCLevel41 = 0x1000,
+	VDEC_AVCLevel42 = 0x2000,
+	VDEC_AVCLevel5 = 0x4000,
+	VDEC_AVCLevel51 = 0x8000,
+	VDEC_AVCLevelKhronosExtensions = 0x6F000000,
+	VDEC_AVCLevelVendorStartUnused = 0x7F000000,
+	VDEC_AVCLevelMax = 0x7FFFFFFF
+};
+
+enum vdec_divx_profile {
+	VDEC_DIVXProfile_qMobile = 0x01,
+	VDEC_DIVXProfile_Mobile = 0x02,
+	VDEC_DIVXProfile_HD = 0x04,
+	VDEC_DIVXProfile_Handheld = 0x08,
+	VDEC_DIVXProfile_Portable = 0x10,
+	VDEC_DIVXProfile_HomeTheater = 0x20
+};
+
+enum vdec_xvid_profile {
+	VDEC_XVIDProfile_Simple = 0x1,
+	VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2,
+	VDEC_XVIDProfile_Advanced_Simple = 0x4
+};
+
+enum vdec_xvid_level {
+	VDEC_XVID_LEVEL_S_L0 = 0x1,
+	VDEC_XVID_LEVEL_S_L1 = 0x2,
+	VDEC_XVID_LEVEL_S_L2 = 0x4,
+	VDEC_XVID_LEVEL_S_L3 = 0x8,
+	VDEC_XVID_LEVEL_ARTS_L1 = 0x10,
+	VDEC_XVID_LEVEL_ARTS_L2 = 0x20,
+	VDEC_XVID_LEVEL_ARTS_L3 = 0x40,
+	VDEC_XVID_LEVEL_ARTS_L4 = 0x80,
+	VDEC_XVID_LEVEL_AS_L0 = 0x100,
+	VDEC_XVID_LEVEL_AS_L1 = 0x200,
+	VDEC_XVID_LEVEL_AS_L2 = 0x400,
+	VDEC_XVID_LEVEL_AS_L3 = 0x800,
+	VDEC_XVID_LEVEL_AS_L4 = 0x1000
+};
+
+enum vdec_h263profile {
+	VDEC_H263ProfileBaseline = 0x01,
+	VDEC_H263ProfileH320Coding = 0x02,
+	VDEC_H263ProfileBackwardCompatible = 0x04,
+	VDEC_H263ProfileISWV2 = 0x08,
+	VDEC_H263ProfileISWV3 = 0x10,
+	VDEC_H263ProfileHighCompression = 0x20,
+	VDEC_H263ProfileInternet = 0x40,
+	VDEC_H263ProfileInterlace = 0x80,
+	VDEC_H263ProfileHighLatency = 0x100,
+	VDEC_H263ProfileKhronosExtensions = 0x6F000000,
+	VDEC_H263ProfileVendorStartUnused = 0x7F000000,
+	VDEC_H263ProfileMax = 0x7FFFFFFF
+};
+
+enum vdec_h263level {
+	VDEC_H263Level10 = 0x01,
+	VDEC_H263Level20 = 0x02,
+	VDEC_H263Level30 = 0x04,
+	VDEC_H263Level40 = 0x08,
+	VDEC_H263Level45 = 0x10,
+	VDEC_H263Level50 = 0x20,
+	VDEC_H263Level60 = 0x40,
+	VDEC_H263Level70 = 0x80,
+	VDEC_H263LevelKhronosExtensions = 0x6F000000,
+	VDEC_H263LevelVendorStartUnused = 0x7F000000,
+	VDEC_H263LevelMax = 0x7FFFFFFF
+};
+
+enum vdec_wmv_format {
+	VDEC_WMVFormatUnused = 0x01,
+	VDEC_WMVFormat7 = 0x02,
+	VDEC_WMVFormat8 = 0x04,
+	VDEC_WMVFormat9 = 0x08,
+	VDEC_WMFFormatKhronosExtensions = 0x6F000000,
+	VDEC_WMFFormatVendorStartUnused = 0x7F000000,
+	VDEC_WMVFormatMax = 0x7FFFFFFF
+};
+
+enum vdec_vc1_profile {
+	VDEC_VC1ProfileSimple = 0x1,
+	VDEC_VC1ProfileMain = 0x2,
+	VDEC_VC1ProfileAdvanced = 0x4
+};
+
+enum vdec_vc1_level {
+	VDEC_VC1_LEVEL_S_Low = 0x1,
+	VDEC_VC1_LEVEL_S_Medium = 0x2,
+	VDEC_VC1_LEVEL_M_Low = 0x4,
+	VDEC_VC1_LEVEL_M_Medium = 0x8,
+	VDEC_VC1_LEVEL_M_High = 0x10,
+	VDEC_VC1_LEVEL_A_L0 = 0x20,
+	VDEC_VC1_LEVEL_A_L1 = 0x40,
+	VDEC_VC1_LEVEL_A_L2 = 0x80,
+	VDEC_VC1_LEVEL_A_L3 = 0x100,
+	VDEC_VC1_LEVEL_A_L4 = 0x200
+};
+
+struct vdec_profile_level {
+	uint32_t profiles;
+	uint32_t levels;
+};
+
+enum vdec_interlaced_format {
+	VDEC_InterlaceFrameProgressive = 0x1,
+	VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2,
+	VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4
+};
+
+enum vdec_output_fromat {
+	VDEC_YUV_FORMAT_NV12 = 0x1,
+	VDEC_YUV_FORMAT_TILE_4x2 = 0x2
+};
+
+enum vdec_output_order {
+	VDEC_ORDER_DISPLAY = 0x1,
+	VDEC_ORDER_DECODE = 0x2
+};
+
+struct vdec_picsize {
+	uint32_t frame_width;
+	uint32_t frame_height;
+	uint32_t stride;
+	uint32_t scan_lines;
+};
+
+struct vdec_seqheader {
+	void __user *ptr_seqheader;
+	size_t seq_header_len;
+	int pmem_fd;
+	size_t pmem_offset;
+};
+
+struct vdec_mberror {
+	void __user *ptr_errormap;
+	size_t err_mapsize;
+};
+
+struct vdec_input_frameinfo {
+	void __user *bufferaddr;
+	size_t offset;
+	size_t datalen;
+	uint32_t flags;
+	int64_t timestamp;
+	void *client_data;
+	int pmem_fd;
+	size_t pmem_offset;
+};
+
+struct vdec_framesize {
+	uint32_t   left;
+	uint32_t   top;
+	uint32_t   right;
+	uint32_t   bottom;
+};
+
+struct vdec_output_frameinfo {
+	void __user *bufferaddr;
+	size_t offset;
+	size_t len;
+	uint32_t flags;
+	int64_t time_stamp;
+	enum vdec_picture pic_type;
+	void *client_data;
+	void *input_frame_clientdata;
+	struct vdec_framesize framesize;
+	enum vdec_interlaced_format interlaced_format;
+};
+
+union vdec_msgdata {
+	struct vdec_output_frameinfo output_frame;
+	void *input_frame_clientdata;
+};
+
+struct vdec_msginfo {
+	uint32_t status_code;
+	uint32_t msgcode;
+	union vdec_msgdata msgdata;
+	size_t msgdatasize;
+};
+
+struct vdec_framerate {
+	unsigned long fps_denominator;
+	unsigned long fps_numerator;
+};
+
+struct vdec_h264_mv{
+	size_t size;
+	int count;
+	int pmem_fd;
+	int offset;
+};
+
+struct vdec_mv_buff_size{
+	int width;
+	int height;
+	int size;
+	int alignment;
+};
+
+#endif /* end of macro _VDECDECODER_H_ */
diff --git a/include/linux/msm_vidc_enc.h b/include/linux/msm_vidc_enc.h
new file mode 100644
index 0000000..12c7afd
--- /dev/null
+++ b/include/linux/msm_vidc_enc.h
@@ -0,0 +1,594 @@
+#ifndef _MSM_VIDC_ENC_H_
+#define _MSM_VIDC_ENC_H_
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/** STATUS CODES*/
+/* Base value for status codes */
+#define VEN_S_BASE	0x00000000
+#define VEN_S_SUCCESS	(VEN_S_BASE)/* Success */
+#define VEN_S_EFAIL	(VEN_S_BASE+1)/* General failure */
+#define VEN_S_EFATAL	(VEN_S_BASE+2)/* Fatal irrecoverable failure*/
+#define VEN_S_EBADPARAM	(VEN_S_BASE+3)/* Error passed parameters*/
+/*Command called in invalid state*/
+#define VEN_S_EINVALSTATE	(VEN_S_BASE+4)
+#define VEN_S_ENOSWRES	(VEN_S_BASE+5)/* Insufficient OS resources*/
+#define VEN_S_ENOHWRES	(VEN_S_BASE+6)/*Insufficient HW resources */
+#define VEN_S_EBUFFREQ	(VEN_S_BASE+7)/* Buffer requirements were not met*/
+#define VEN_S_EINVALCMD	(VEN_S_BASE+8)/* Invalid command called */
+#define VEN_S_ETIMEOUT	(VEN_S_BASE+9)/* Command timeout. */
+/*Re-attempt was made when multiple invocation not supported for API.*/
+#define VEN_S_ENOREATMPT	(VEN_S_BASE+10)
+#define VEN_S_ENOPREREQ	(VEN_S_BASE+11)/*Pre-requirement is not met for API*/
+#define VEN_S_ECMDQFULL	(VEN_S_BASE+12)/*Command queue is full*/
+#define VEN_S_ENOTSUPP	(VEN_S_BASE+13)/*Command not supported*/
+#define VEN_S_ENOTIMPL	(VEN_S_BASE+14)/*Command not implemented.*/
+#define VEN_S_ENOTPMEM	(VEN_S_BASE+15)/*Buffer is not from PMEM*/
+#define VEN_S_EFLUSHED	(VEN_S_BASE+16)/*returned buffer was flushed*/
+#define VEN_S_EINSUFBUF	(VEN_S_BASE+17)/*provided buffer size insufficient*/
+#define VEN_S_ESAMESTATE	(VEN_S_BASE+18)
+#define VEN_S_EINVALTRANS	(VEN_S_BASE+19)
+
+#define VEN_INTF_VER			 1
+
+/*Asynchronous messages from driver*/
+#define VEN_MSG_INDICATION	0
+#define VEN_MSG_INPUT_BUFFER_DONE	1
+#define VEN_MSG_OUTPUT_BUFFER_DONE	2
+#define VEN_MSG_NEED_OUTPUT_BUFFER	3
+#define VEN_MSG_FLUSH_INPUT_DONE	4
+#define VEN_MSG_FLUSH_OUPUT_DONE	5
+#define VEN_MSG_START	6
+#define VEN_MSG_STOP	7
+#define VEN_MSG_PAUSE	8
+#define VEN_MSG_RESUME	9
+#define VEN_MSG_STOP_READING_MSG	10
+
+/*Buffer flags bits masks*/
+#define VEN_BUFFLAG_EOS	0x00000001
+#define VEN_BUFFLAG_ENDOFFRAME	0x00000010
+#define VEN_BUFFLAG_SYNCFRAME	0x00000020
+#define VEN_BUFFLAG_EXTRADATA	0x00000040
+#define VEN_BUFFLAG_CODECCONFIG	0x00000080
+
+/*ENCODER CONFIGURATION CONSTANTS*/
+
+/*Encoded video frame types*/
+#define VEN_FRAME_TYPE_I	1/* I frame type */
+#define VEN_FRAME_TYPE_P	2/* P frame type */
+#define VEN_FRAME_TYPE_B	3/* B frame type */
+
+/*Video codec types*/
+#define VEN_CODEC_MPEG4	1/* MPEG4 Codec */
+#define VEN_CODEC_H264	2/* H.264 Codec */
+#define VEN_CODEC_H263	3/* H.263 Codec */
+
+/*Video codec profile types.*/
+#define VEN_PROFILE_MPEG4_SP      1/* 1 - MPEG4 SP profile      */
+#define VEN_PROFILE_MPEG4_ASP     2/* 2 - MPEG4 ASP profile     */
+#define VEN_PROFILE_H264_BASELINE 3/* 3 - H264 Baseline profile	*/
+#define VEN_PROFILE_H264_MAIN     4/* 4 - H264 Main profile     */
+#define VEN_PROFILE_H264_HIGH     5/* 5 - H264 High profile     */
+#define VEN_PROFILE_H263_BASELINE 6/* 6 - H263 Baseline profile */
+
+/*Video codec profile level types.*/
+#define VEN_LEVEL_MPEG4_0	 0x1/* MPEG4 Level 0  */
+#define VEN_LEVEL_MPEG4_1	 0x2/* MPEG4 Level 1  */
+#define VEN_LEVEL_MPEG4_2	 0x3/* MPEG4 Level 2  */
+#define VEN_LEVEL_MPEG4_3	 0x4/* MPEG4 Level 3  */
+#define VEN_LEVEL_MPEG4_4	 0x5/* MPEG4 Level 4  */
+#define VEN_LEVEL_MPEG4_5	 0x6/* MPEG4 Level 5  */
+#define VEN_LEVEL_MPEG4_3b	 0x7/* MPEG4 Level 3b */
+#define VEN_LEVEL_MPEG4_6	 0x8/* MPEG4 Level 6  */
+
+#define VEN_LEVEL_H264_1	 0x9/* H.264 Level 1   */
+#define VEN_LEVEL_H264_1b        0xA/* H.264 Level 1b  */
+#define VEN_LEVEL_H264_1p1	 0xB/* H.264 Level 1.1 */
+#define VEN_LEVEL_H264_1p2	 0xC/* H.264 Level 1.2 */
+#define VEN_LEVEL_H264_1p3	 0xD/* H.264 Level 1.3 */
+#define VEN_LEVEL_H264_2	 0xE/* H.264 Level 2   */
+#define VEN_LEVEL_H264_2p1	 0xF/* H.264 Level 2.1 */
+#define VEN_LEVEL_H264_2p2	0x10/* H.264 Level 2.2 */
+#define VEN_LEVEL_H264_3	0x11/* H.264 Level 3   */
+#define VEN_LEVEL_H264_3p1	0x12/* H.264 Level 3.1 */
+#define VEN_LEVEL_H264_4	0x13/* H.264 Level 4   */
+
+#define VEN_LEVEL_H263_10	0x14/* H.263 Level 10  */
+#define VEN_LEVEL_H263_20	0x15/* H.263 Level 20  */
+#define VEN_LEVEL_H263_30	0x16/* H.263 Level 30  */
+#define VEN_LEVEL_H263_40	0x17/* H.263 Level 40  */
+#define VEN_LEVEL_H263_45	0x18/* H.263 Level 45  */
+#define VEN_LEVEL_H263_50	0x19/* H.263 Level 50  */
+#define VEN_LEVEL_H263_60	0x1A/* H.263 Level 60  */
+#define VEN_LEVEL_H263_70	0x1B/* H.263 Level 70  */
+
+/*Entropy coding model selection for H.264 encoder.*/
+#define VEN_ENTROPY_MODEL_CAVLC	1
+#define VEN_ENTROPY_MODEL_CABAC	2
+/*Cabac model number (0,1,2) for encoder.*/
+#define VEN_CABAC_MODEL_0	1/* CABAC Model 0. */
+#define VEN_CABAC_MODEL_1	2/* CABAC Model 1. */
+#define VEN_CABAC_MODEL_2	3/* CABAC Model 2. */
+
+/*Deblocking filter control type for encoder.*/
+#define VEN_DB_DISABLE	1/* 1 - Disable deblocking filter*/
+#define VEN_DB_ALL_BLKG_BNDRY	2/* 2 - All blocking boundary filtering*/
+#define VEN_DB_SKIP_SLICE_BNDRY	3/* 3 - Filtering except sliceboundary*/
+
+/*Different methods of Multi slice selection.*/
+#define VEN_MSLICE_OFF	1
+#define VEN_MSLICE_CNT_MB	2 /*number of MBscount per slice*/
+#define VEN_MSLICE_CNT_BYTE	3 /*number of bytes count per slice.*/
+#define VEN_MSLICE_GOB	4 /*Multi slice by GOB for H.263 only.*/
+
+/*Different modes for Rate Control.*/
+#define VEN_RC_OFF	1
+#define VEN_RC_VBR_VFR	2
+#define VEN_RC_VBR_CFR	3
+#define VEN_RC_CBR_VFR	4
+#define VEN_RC_CBR_CFR	5
+
+/*Different modes for flushing buffers*/
+#define VEN_FLUSH_INPUT	1
+#define VEN_FLUSH_OUTPUT	2
+#define VEN_FLUSH_ALL	3
+
+/*Different input formats for YUV data.*/
+#define VEN_INPUTFMT_NV12	1/* NV12 Linear */
+#define VEN_INPUTFMT_NV21	2/* NV21 Linear */
+#define VEN_INPUTFMT_NV12_16M2KA	3/* NV12 Linear */
+
+/*Different allowed rotation modes.*/
+#define VEN_ROTATION_0	1/* 0 degrees */
+#define VEN_ROTATION_90	2/* 90 degrees */
+#define VEN_ROTATION_180	3/* 180 degrees */
+#define VEN_ROTATION_270	4/* 270 degrees */
+
+/*IOCTL timeout values*/
+#define VEN_TIMEOUT_INFINITE	0xffffffff
+
+/*Different allowed intra refresh modes.*/
+#define VEN_IR_OFF	1
+#define VEN_IR_CYCLIC	2
+#define VEN_IR_RANDOM	3
+
+/*IOCTL BASE CODES Not to be used directly by the client.*/
+/* Base value for ioctls that are not related to encoder configuration.*/
+#define VEN_IOCTLBASE_NENC	0x800
+/* Base value for encoder configuration ioctls*/
+#define VEN_IOCTLBASE_ENC	0x850
+
+struct venc_ioctl_msg{
+	void __user *in;
+	void __user *out;
+};
+
+/*NON ENCODER CONFIGURATION IOCTLs*/
+
+/*IOCTL params:SET: InputData - unsigned long, OutputData - NULL*/
+#define VEN_IOCTL_SET_INTF_VERSION \
+	_IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - venc_timeout, OutputData - venc_msg*/
+#define VEN_IOCTL_CMD_READ_NEXT_MSG \
+	_IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - NULL, OutputData - NULL*/
+#define VEN_IOCTL_CMD_STOP_READ_MSG	_IO(VEN_IOCTLBASE_NENC, 2)
+
+/*IOCTL params:SET: InputData - venc_allocatorproperty, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_allocatorproperty*/
+#define VEN_IOCTL_SET_INPUT_BUFFER_REQ \
+	_IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_INPUT_BUFFER_REQ \
+	_IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/
+#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/
+#define VEN_IOCTL_SET_INPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg)
+
+/*IOCTL params: CMD: InputData - venc_bufferpayload, OutputData - NULL*/
+#define VEN_IOCTL_CMD_FREE_INPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_allocatorproperty, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_allocatorproperty*/
+#define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ \
+	_IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ \
+	_IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/
+#define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg)
+
+
+/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/
+#define VEN_IOCTL_SET_OUTPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL.*/
+#define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg)
+
+
+/* Asynchronous respone message code:* VEN_MSG_START*/
+#define VEN_IOCTL_CMD_START	_IO(VEN_IOCTLBASE_NENC, 13)
+
+
+/*IOCTL params:CMD: InputData - venc_buffer, OutputData - NULL
+ Asynchronous respone message code:VEN_MSG_INPUT_BUFFER_DONE*/
+#define VEN_IOCTL_CMD_ENCODE_FRAME \
+	_IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg)
+
+
+/*IOCTL params:CMD: InputData - venc_buffer, OutputData - NULL
+ Asynchronous response message code:VEN_MSG_OUTPUT_BUFFER_DONE*/
+#define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg)
+
+/*IOCTL params:CMD: InputData - venc_bufferflush, OutputData - NULL
+ * Asynchronous response message code:VEN_MSG_INPUT_BUFFER_DONE*/
+#define VEN_IOCTL_CMD_FLUSH \
+	_IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg)
+
+
+/*Asynchronous respone message code:VEN_MSG_PAUSE*/
+#define VEN_IOCTL_CMD_PAUSE	_IO(VEN_IOCTLBASE_NENC, 17)
+
+/*Asynchronous respone message code:VEN_MSG_RESUME*/
+#define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18)
+
+/* Asynchronous respone message code:VEN_MSG_STOP*/
+#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19)
+
+#define VEN_IOCTL_SET_RECON_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_FREE_RECON_BUFFER \
+	_IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_GET_RECON_BUFFER_SIZE \
+	_IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg)
+
+/*ENCODER PROPERTY CONFIGURATION & CAPABILITY IOCTLs*/
+
+/*IOCTL params:SET: InputData - venc_basecfg, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_basecfg*/
+#define VEN_IOCTL_SET_BASE_CFG \
+	_IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_BASE_CFG \
+	_IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_switch*/
+#define VEN_IOCTL_SET_LIVE_MODE \
+	_IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_LIVE_MODE \
+	_IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_profile, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_profile*/
+#define VEN_IOCTL_SET_CODEC_PROFILE \
+	_IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_CODEC_PROFILE \
+	_IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - ven_profilelevel, OutputData - NULL
+  GET: InputData - NULL, OutputData - ven_profilelevel*/
+#define VEN_IOCTL_SET_PROFILE_LEVEL \
+	_IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_GET_PROFILE_LEVEL \
+	_IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_switch*/
+#define VEN_IOCTL_SET_SHORT_HDR \
+	_IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_SHORT_HDR \
+	_IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg)
+
+
+/*IOCTL params: SET: InputData - venc_sessionqp, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_sessionqp*/
+#define VEN_IOCTL_SET_SESSION_QP \
+	_IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_SESSION_QP \
+	_IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_intraperiod, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_intraperiod*/
+#define VEN_IOCTL_SET_INTRA_PERIOD \
+	_IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_INTRA_PERIOD \
+	_IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg)
+
+
+/* Request an Iframe*/
+#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15)
+
+/*IOCTL params:GET: InputData - NULL, OutputData - venc_capability*/
+#define VEN_IOCTL_GET_CAPABILITY \
+	_IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg)
+
+
+/*IOCTL params:GET: InputData - NULL, OutputData - venc_seqheader*/
+#define VEN_IOCTL_GET_SEQUENCE_HDR \
+	_IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_entropycfg, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_entropycfg*/
+#define VEN_IOCTL_SET_ENTROPY_CFG \
+	_IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_ENTROPY_CFG \
+	_IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_dbcfg, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_dbcfg*/
+#define VEN_IOCTL_SET_DEBLOCKING_CFG \
+	_IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_DEBLOCKING_CFG \
+	_IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_intrarefresh, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_intrarefresh*/
+#define VEN_IOCTL_SET_INTRA_REFRESH \
+	_IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_INTRA_REFRESH \
+	_IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_multiclicecfg, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_multiclicecfg*/
+#define VEN_IOCTL_SET_MULTI_SLICE_CFG \
+	_IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_MULTI_SLICE_CFG \
+	_IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_ratectrlcfg, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_ratectrlcfg*/
+#define VEN_IOCTL_SET_RATE_CTRL_CFG \
+	_IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_RATE_CTRL_CFG \
+	_IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_voptimingcfg, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_voptimingcfg*/
+#define VEN_IOCTL_SET_VOP_TIMING_CFG \
+	_IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_VOP_TIMING_CFG \
+	_IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_framerate, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_framerate*/
+#define VEN_IOCTL_SET_FRAME_RATE \
+	_IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_FRAME_RATE \
+	_IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_targetbitrate, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_targetbitrate*/
+#define VEN_IOCTL_SET_TARGET_BITRATE \
+	_IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_TARGET_BITRATE \
+	_IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_rotation, OutputData - NULL
+  GET: InputData - NULL, OutputData - venc_rotation*/
+#define VEN_IOCTL_SET_ROTATION \
+	_IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_ROTATION \
+	_IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_headerextension, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_headerextension*/
+#define VEN_IOCTL_SET_HEC \
+	_IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_HEC \
+	_IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_switch*/
+#define VEN_IOCTL_SET_DATA_PARTITION \
+	_IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_DATA_PARTITION \
+	_IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_switch*/
+#define VEN_IOCTL_SET_RVLC \
+	_IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_RVLC \
+	_IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_switch*/
+#define VEN_IOCTL_SET_AC_PREDICTION \
+	_IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_AC_PREDICTION \
+	_IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - venc_qprange, OutputData - NULL
+ GET: InputData - NULL, OutputData - venc_qprange*/
+#define VEN_IOCTL_SET_QP_RANGE \
+	_IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_QP_RANGE \
+	_IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_GET_NUMBER_INSTANCES \
+	_IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg)
+
+struct venc_switch{
+	unsigned char	status;
+};
+
+struct venc_allocatorproperty{
+	unsigned long	 mincount;
+	unsigned long	 maxcount;
+	unsigned long	 actualcount;
+	unsigned long	 datasize;
+	unsigned long	 suffixsize;
+	unsigned long	 alignment;
+	unsigned long	 bufpoolid;
+};
+
+struct venc_bufferpayload{
+	unsigned char *pbuffer;
+	size_t	sz;
+	int	fd;
+	unsigned int	offset;
+	unsigned int	maped_size;
+	unsigned long	filled_len;
+};
+
+struct venc_buffer{
+ unsigned char *ptrbuffer;
+ unsigned long	sz;
+ unsigned long	len;
+ unsigned long	offset;
+ long long	timestamp;
+ unsigned long	flags;
+ void	*clientdata;
+};
+
+struct venc_basecfg{
+	unsigned long	input_width;
+	unsigned long	input_height;
+	unsigned long	dvs_width;
+	unsigned long	dvs_height;
+	unsigned long	codectype;
+	unsigned long	fps_num;
+	unsigned long	fps_den;
+	unsigned long	targetbitrate;
+	unsigned long	inputformat;
+};
+
+struct venc_profile{
+	unsigned long	profile;
+};
+struct ven_profilelevel{
+	unsigned long	level;
+};
+
+struct venc_sessionqp{
+	unsigned long	iframeqp;
+	unsigned long	pframqp;
+};
+
+struct venc_qprange{
+	unsigned long	maxqp;
+	unsigned long	minqp;
+};
+struct venc_intraperiod{
+	unsigned long	num_pframes;
+	unsigned long	num_bframes;
+};
+struct venc_seqheader{
+	unsigned char *hdrbufptr;
+	unsigned long	bufsize;
+	unsigned long	hdrlen;
+};
+
+struct venc_capability{
+	unsigned long	codec_types;
+	unsigned long	maxframe_width;
+	unsigned long	maxframe_height;
+	unsigned long	maxtarget_bitrate;
+	unsigned long	maxframe_rate;
+	unsigned long	input_formats;
+	unsigned char	dvs;
+};
+
+struct venc_entropycfg{
+	unsigned longentropysel;
+	unsigned long	cabacmodel;
+};
+
+struct venc_dbcfg{
+	unsigned long	db_mode;
+	unsigned long	slicealpha_offset;
+	unsigned long	slicebeta_offset;
+};
+
+struct venc_intrarefresh{
+	unsigned long	irmode;
+	unsigned long	mbcount;
+};
+
+struct venc_multiclicecfg{
+	unsigned long	mslice_mode;
+	unsigned long	mslice_size;
+};
+
+struct venc_bufferflush{
+	unsigned long	flush_mode;
+};
+
+struct venc_ratectrlcfg{
+	unsigned long	rcmode;
+};
+
+struct	venc_voptimingcfg{
+	unsigned long	voptime_resolution;
+};
+struct venc_framerate{
+	unsigned long	fps_denominator;
+	unsigned long	fps_numerator;
+};
+
+struct venc_targetbitrate{
+	unsigned long	target_bitrate;
+};
+
+
+struct venc_rotation{
+	unsigned long	rotation;
+};
+
+struct venc_timeout{
+	 unsigned long	millisec;
+};
+
+struct venc_headerextension{
+	 unsigned long	header_extension;
+};
+
+struct venc_msg{
+	unsigned long	statuscode;
+	unsigned long	msgcode;
+	struct venc_buffer	buf;
+	unsigned long	msgdata_size;
+};
+
+struct venc_recon_addr{
+	unsigned char *pbuffer;
+	unsigned long buffer_size;
+	unsigned long pmem_fd;
+	unsigned long offset;
+};
+
+struct venc_recon_buff_size{
+	int width;
+	int height;
+	int size;
+	int alignment;
+};
+
+#endif /* _MSM_VIDC_ENC_H_ */
diff --git a/include/linux/ofn_atlab.h b/include/linux/ofn_atlab.h
new file mode 100644
index 0000000..16c34d7
--- /dev/null
+++ b/include/linux/ofn_atlab.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+/*
+ * Atlab optical Finger Navigation driver
+ *
+ */
+
+struct ofn_function1 {
+	bool no_motion1_en;
+	bool touch_sensor_en;
+	bool ofn_en;
+	u16 clock_select_khz;
+	u32 cpi_selection;
+};
+
+struct ofn_function2 {
+	bool invert_y;
+	bool invert_x;
+	bool swap_x_y;
+	bool hold_a_b_en;
+	bool motion_filter_en;
+};
+
+struct ofn_atlab_platform_data {
+	int irq_button_l;
+	int irq_button_r;
+	int gpio_button_l;
+	int gpio_button_r;
+	int rotate_xy;
+	int (*gpio_setup)(void);
+	void (*gpio_release)(void);
+	int (*optnav_on)(void);
+	void (*optnav_off)(void);
+	struct ofn_function1 function1;
+	struct ofn_function2 function2;
+};
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index e0786e3..fc94089 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -32,6 +32,7 @@
 	PERF_TYPE_HW_CACHE			= 3,
 	PERF_TYPE_RAW				= 4,
 	PERF_TYPE_BREAKPOINT			= 5,
+	PERF_TYPE_SHARED			= 6,
 
 	PERF_TYPE_MAX,				/* non-ABI */
 };
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index c533670..addaebb 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -118,6 +118,7 @@
 struct tc_prio_qopt {
 	int	bands;			/* Number of bands */
 	__u8	priomap[TC_PRIO_MAX+1];	/* Map: logical priority -> PRIO band */
+	__u8	enable_flow;		/* Enable dequeue */
 };
 
 /* MULTIQ section */
diff --git a/include/linux/platform_data/qcom_crypto_device.h b/include/linux/platform_data/qcom_crypto_device.h
new file mode 100644
index 0000000..c6ef40a
--- /dev/null
+++ b/include/linux/platform_data/qcom_crypto_device.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_CRYPTO_DEVICE__H
+#define __QCOM_CRYPTO_DEVICE__H
+
+struct msm_ce_hw_support {
+	uint32_t ce_shared;
+	uint32_t shared_ce_resource;
+	uint32_t hw_key_support;
+	uint32_t sha_hmac;
+};
+
+#endif /* __QCOM_CRYPTO_DEVICE__H */
diff --git a/include/linux/platform_data/usb_rmnet.h b/include/linux/platform_data/usb_rmnet.h
new file mode 100644
index 0000000..68c0db7
--- /dev/null
+++ b/include/linux/platform_data/usb_rmnet.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __LINUX_USB_GADGET_RMNET_H__
+#define __LINUX_USB_GADGET_RMNET_H__
+
+#include <linux/platform_device.h>
+
+struct usb_rmnet_pdata {
+	unsigned	num_instances;
+};
+
+#endif
diff --git a/include/linux/pmic8058-batt-alarm.h b/include/linux/pmic8058-batt-alarm.h
new file mode 100644
index 0000000..0a0ac78
--- /dev/null
+++ b/include/linux/pmic8058-batt-alarm.h
@@ -0,0 +1,124 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8058 Battery Alarm Device driver
+ *
+ */
+#ifndef __PMIC8058_BATT_ALARM_H__
+#define __PMIC8058_BATT_ALARM_H__
+
+#include <linux/bitops.h>
+
+/**
+ * enum pm8058_batt_alarm_hold_time - hold time required for out of range
+ *	battery voltage needed to trigger a status change.  Enum names denote
+ *	hold time in milliseconds.
+ */
+enum pm8058_batt_alarm_hold_time {
+	PM8058_BATT_ALARM_HOLD_TIME_0p125_MS = 0,
+	PM8058_BATT_ALARM_HOLD_TIME_0p25_MS,
+	PM8058_BATT_ALARM_HOLD_TIME_0p5_MS,
+	PM8058_BATT_ALARM_HOLD_TIME_1_MS,
+	PM8058_BATT_ALARM_HOLD_TIME_2_MS,
+	PM8058_BATT_ALARM_HOLD_TIME_4_MS,
+	PM8058_BATT_ALARM_HOLD_TIME_8_MS,
+	PM8058_BATT_ALARM_HOLD_TIME_16_MS,
+};
+
+/*
+ * Bits that are set in the return value of pm8058_batt_alarm_status_read
+ * to indicate crossing of the upper or lower threshold.
+ */
+#define PM8058_BATT_ALARM_STATUS_BELOW_LOWER	BIT(0)
+#define PM8058_BATT_ALARM_STATUS_ABOVE_UPPER	BIT(1)
+
+/**
+ * pm8058_batt_alarm_state_set - enable or disable the threshold comparators
+ * @enable_lower_comparator: 1 = enable comparator, 0 = disable comparator
+ * @enable_upper_comparator: 1 = enable comparator, 0 = disable comparator
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_batt_alarm_state_set(int enable_lower_comparator,
+				int enable_upper_comparator);
+
+/**
+ * pm8058_batt_alarm_threshold_set - set the lower and upper alarm thresholds
+ * @lower_threshold_mV: battery undervoltage threshold in millivolts
+ * @upper_threshold_mV: battery overvoltage threshold in millivolts
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_batt_alarm_threshold_set(int lower_threshold_mV,
+				    int upper_threshold_mV);
+
+/**
+ * pm8058_batt_alarm_status_read - get status of both threshold comparators
+ *
+ * RETURNS:	< 0	   = error
+ *		  0	   = battery voltage ok
+ *		BIT(0) set = battery voltage below lower threshold
+ *		BIT(1) set = battery voltage above upper threshold
+ */
+int pm8058_batt_alarm_status_read(void);
+
+/**
+ * pm8058_batt_alarm_register_notifier - register a notifier to run when a
+ *	battery voltage change interrupt fires
+ * @nb:	notifier block containing callback function to register
+ *
+ * nb->notifier_call must point to a function of this form -
+ * int (*notifier_call)(struct notifier_block *nb, unsigned long status,
+ *			void *unused);
+ * "status" will receive the battery alarm status; "unused" will be NULL.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_batt_alarm_register_notifier(struct notifier_block *nb);
+
+/**
+ * pm8058_batt_alarm_unregister_notifier - unregister a notifier that is run
+ *	when a battery voltage change interrupt fires
+ * @nb:	notifier block containing callback function to unregister
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_batt_alarm_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * pm8058_batt_alarm_hold_time_set - set hold time of interrupt output *
+ * @hold_time:	amount of time that battery voltage must remain outside of the
+ *		threshold range before the battery alarm interrupt triggers
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_batt_alarm_hold_time_set(enum pm8058_batt_alarm_hold_time hold_time);
+
+/**
+ * pm8058_batt_alarm_pwm_rate_set - set battery alarm update rate *
+ * @use_pwm:		1 = use PWM update rate, 0 = comparators always active
+ * @clock_scaler:	PWM clock scaler = 2 to 9
+ * @clock_divider:	PWM clock divider = 2 to 8
+ *
+ * This function sets the rate at which the battery alarm module enables
+ * the threshold comparators.  The rate is determined by the following equation:
+ *
+ * f_update = (1024 Hz) / (clock_divider * (2 ^ clock_scaler))
+ *
+ * Thus, the update rate can range from 0.25 Hz to 128 Hz.
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8058_batt_alarm_pwm_rate_set(int use_pwm, int clock_scaler,
+				   int clock_divider);
+
+#endif /* __PMIC8058_BATT_ALARM_H__ */
diff --git a/include/linux/pmic8058-charger.h b/include/linux/pmic8058-charger.h
new file mode 100644
index 0000000..f1fd25c
--- /dev/null
+++ b/include/linux/pmic8058-charger.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PMIC8058_CHARGER_H__
+#define __PMIC8058_CHARGER_H__
+
+#if defined(CONFIG_BATTERY_MSM8X60) || defined(CONFIG_BATTERY_MSM8X60_MODULE)
+int pmic8058_get_charge_batt(void);
+int pmic8058_set_charge_batt(int);
+#else
+int pmic8058_get_charge_batt(void)
+{
+	return -ENXIO;
+}
+int pmic8058_set_charge_batt(int)
+{
+	return -ENXIO;
+}
+#endif
+#endif /* __PMIC8058_CHARGER_H__ */
diff --git a/include/linux/pmic8058-misc.h b/include/linux/pmic8058-misc.h
new file mode 100644
index 0000000..5675a93
--- /dev/null
+++ b/include/linux/pmic8058-misc.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __PMIC8058_MISC_H__
+#define __PMIC8058_MISC_H__
+
+enum pm8058_vib_en_mode {
+	PM8058_VIB_MANUAL,
+	PM8058_VIB_DTEST1,
+	PM8058_VIB_DTEST2,
+	PM8058_VIB_DTEST3
+};
+
+enum pm8058_coincell_chg_voltage {
+	PM8058_COINCELL_VOLTAGE_3p2V = 1,
+	PM8058_COINCELL_VOLTAGE_3p1V,
+	PM8058_COINCELL_VOLTAGE_3p0V,
+	PM8058_COINCELL_VOLTAGE_2p5V = 16
+};
+
+enum pm8058_coincell_chg_resistor {
+	PM8058_COINCELL_RESISTOR_2100_OHMS,
+	PM8058_COINCELL_RESISTOR_1700_OHMS,
+	PM8058_COINCELL_RESISTOR_1200_OHMS,
+	PM8058_COINCELL_RESISTOR_800_OHMS
+};
+
+enum pm8058_coincell_chg_state {
+	PM8058_COINCELL_CHG_DISABLE,
+	PM8058_COINCELL_CHG_ENABLE
+};
+
+struct pm8058_vib_config {
+	u16			drive_mV;
+	u8			active_low;
+	enum pm8058_vib_en_mode	enable_mode;
+};
+
+struct pm8058_coincell_chg_config {
+	enum pm8058_coincell_chg_state		state;
+	enum pm8058_coincell_chg_voltage	voltage;
+	enum pm8058_coincell_chg_resistor	resistor;
+};
+
+int pm8058_vibrator_config(struct pm8058_vib_config *vib_config);
+int pm8058_coincell_chg_config(struct pm8058_coincell_chg_config *chg_config);
+
+#endif /* __PMIC8058_MISC_H__ */
diff --git a/include/linux/pmic8058-nfc.h b/include/linux/pmic8058-nfc.h
new file mode 100644
index 0000000..5b2d6cf
--- /dev/null
+++ b/include/linux/pmic8058-nfc.h
@@ -0,0 +1,77 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __PMIC8058_NFC_H__
+#define __PMIC8058_NFC_H__
+
+struct pm8058_nfc_device;
+
+/* masks, flags and status */
+#define	PM_NFC_VDDLDO_MON_LEVEL		0x0003
+#define	PM_NFC_VPH_PWR_EN		0x0008
+#define	PM_NFC_EXT_VDDLDO_EN		0x0010
+#define	PM_NFC_EN			0x0020
+#define	PM_NFC_LDO_EN			0x0040
+#define	PM_NFC_SUPPORT_EN		0x0080
+
+#define	PM_NFC_EXT_EN_HIGH		0x0100
+#define	PM_NFC_MBG_EN_HIGH		0x0200
+#define	PM_NFC_VDDLDO_OK_HIGH		0x0400
+#define	PM_NFC_DTEST1_MODE		0x2000
+#define	PM_NFC_ATEST_EN			0x4000
+#define	PM_NFC_VDDLDO_MON_EN		0x8000
+
+#define	PM_NFC_CTRL_REQ			(PM_NFC_SUPPORT_EN |\
+					PM_NFC_LDO_EN |\
+					PM_NFC_EN |\
+					PM_NFC_EXT_VDDLDO_EN |\
+					PM_NFC_VPH_PWR_EN |\
+					PM_NFC_VDDLDO_MON_LEVEL)
+
+#define	PM_NFC_TEST_REQ			(PM_NFC_VDDLDO_MON_EN |\
+					PM_NFC_DTEST1_MODE |\
+					PM_NFC_ATEST_EN)
+
+#define	PM_NFC_TEST_STATUS		(PM_NFC_EXT_EN_HIGH |\
+					PM_NFC_MBG_EN_HIGH |\
+					PM_NFC_VDDLDO_OK_HIGH)
+
+/*
+ * pm8058_nfc_request - request a handle to access NFC device
+ */
+struct pm8058_nfc_device *pm8058_nfc_request(void);
+
+/*
+ * pm8058_nfc_config - configure NFC signals
+ *
+ * @nfcdev: the NFC device
+ * @mask: signal mask to configure
+ * @flags: control flags
+ */
+int pm8058_nfc_config(struct pm8058_nfc_device *nfcdev, u32 mask, u32 flags);
+
+/*
+ * pm8058_nfc_get_status - get NFC status
+ *
+ * @nfcdev: the NFC device
+ * @mask: of status mask to read
+ * @status: pointer to the status variable
+ */
+int pm8058_nfc_get_status(struct pm8058_nfc_device *nfcdev,
+			  u32 mask, u32 *status);
+
+/*
+ * pm8058_nfc_free - free the NFC device
+ */
+void pm8058_nfc_free(struct pm8058_nfc_device *nfcdev);
+
+#endif /* __PMIC8058_NFC_H__ */
diff --git a/include/linux/pmic8058-othc.h b/include/linux/pmic8058-othc.h
new file mode 100644
index 0000000..4c59845
--- /dev/null
+++ b/include/linux/pmic8058-othc.h
@@ -0,0 +1,146 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMIC8058_OTHC_H__
+#define __PMIC8058_OTHC_H__
+
+/* Accessory detecion flags */
+#define OTHC_MICBIAS_DETECT	BIT(0)
+#define OTHC_GPIO_DETECT	BIT(1)
+#define OTHC_SWITCH_DETECT	BIT(2)
+#define OTHC_ADC_DETECT		BIT(3)
+
+enum othc_accessory_type {
+	OTHC_NO_DEVICE = 0,
+	OTHC_HEADSET = 1 << 0,
+	OTHC_HEADPHONE = 1 << 1,
+	OTHC_MICROPHONE = 1 << 2,
+	OTHC_ANC_HEADSET = 1 << 3,
+	OTHC_ANC_HEADPHONE = 1 << 4,
+	OTHC_ANC_MICROPHONE = 1 << 5,
+	OTHC_SVIDEO_OUT = 1 << 6,
+};
+
+struct accessory_adc_thres {
+	int min_threshold;
+	int max_threshold;
+};
+
+struct othc_accessory_info {
+	unsigned int accessory;
+	unsigned int detect_flags;
+	unsigned int gpio;
+	unsigned int active_low;
+	unsigned int key_code;
+	bool enabled;
+	struct accessory_adc_thres adc_thres;
+};
+
+enum othc_headset_type {
+	OTHC_HEADSET_NO,
+	OTHC_HEADSET_NC,
+};
+
+struct othc_regulator_config {
+	const char *regulator;
+	unsigned int max_uV;
+	unsigned int min_uV;
+};
+
+/* Signal control for OTHC module */
+enum othc_micbias_enable {
+	/* Turn off MICBIAS signal */
+	OTHC_SIGNAL_OFF,
+	/* Turn on MICBIAS signal when TCXO is enabled */
+	OTHC_SIGNAL_TCXO,
+	/* Turn on MICBIAS signal when PWM is high or TCXO is enabled */
+	OTHC_SIGNAL_PWM_TCXO,
+	/* MICBIAS always enabled */
+	OTHC_SIGNAL_ALWAYS_ON,
+};
+
+/* Number of MICBIAS lines supported by PMIC8058 */
+enum othc_micbias {
+	OTHC_MICBIAS_0,
+	OTHC_MICBIAS_1,
+	OTHC_MICBIAS_2,
+	OTHC_MICBIAS_MAX,
+};
+
+enum othc_micbias_capability {
+	/* MICBIAS used only for BIAS with on/off capability */
+	OTHC_MICBIAS,
+	/* MICBIAS used to support HSED functionality */
+	OTHC_MICBIAS_HSED,
+};
+
+struct othc_switch_info {
+	u32 min_adc_threshold;
+	u32 max_adc_threshold;
+	u32 key_code;
+};
+
+struct othc_n_switch_config {
+	u32 voltage_settling_time_ms;
+	u8 num_adc_samples;
+	uint32_t adc_channel;
+	struct othc_switch_info *switch_info;
+	u8 num_keys;
+	bool default_sw_en;
+	u8 default_sw_idx;
+};
+
+struct hsed_bias_config {
+	enum othc_headset_type othc_headset;
+	u16 othc_lowcurr_thresh_uA;
+	u16 othc_highcurr_thresh_uA;
+	u32 othc_hyst_prediv_us;
+	u32 othc_period_clkdiv_us;
+	u32 othc_hyst_clk_us;
+	u32 othc_period_clk_us;
+	int othc_wakeup;
+};
+
+/* Configuration data for HSED */
+struct othc_hsed_config {
+	struct hsed_bias_config *hsed_bias_config;
+	unsigned long detection_delay_ms;
+	/* Switch configuration */
+	unsigned long switch_debounce_ms;
+	bool othc_support_n_switch; /* Set if supporting > 1 switch */
+	struct othc_n_switch_config *switch_config;
+	/* Accessory configuration */
+	bool accessories_support;
+	bool accessories_adc_support;
+	uint32_t accessories_adc_channel;
+	struct othc_accessory_info *accessories;
+	int othc_num_accessories;
+	int video_out_gpio;
+	int ir_gpio;
+};
+
+struct pmic8058_othc_config_pdata {
+	enum othc_micbias micbias_select;
+	enum othc_micbias_enable micbias_enable;
+	enum othc_micbias_capability micbias_capability;
+	struct othc_hsed_config *hsed_config;
+	const char *hsed_name;
+	struct othc_regulator_config *micbias_regulator;
+};
+
+int pm8058_micbias_enable(enum othc_micbias micbias,
+			enum othc_micbias_enable enable);
+int pm8058_othc_svideo_enable(enum othc_micbias micbias,
+			bool enable);
+
+#endif /* __PMIC8058_OTHC_H__ */
diff --git a/include/linux/pmic8058-pwm.h b/include/linux/pmic8058-pwm.h
new file mode 100644
index 0000000..2523f99
--- /dev/null
+++ b/include/linux/pmic8058-pwm.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __PMIC8058_PWM_H__
+#define __PMIC8058_PWM_H__
+
+/* The MAX value is computation limit. Hardware limit is 393 seconds. */
+#define	PM_PWM_PERIOD_MAX		(274 * USEC_PER_SEC)
+/* The MIN value is hardware limit. */
+#define	PM_PWM_PERIOD_MIN		7 /* micro seconds */
+
+struct pm8058_pwm_pdata {
+	int 	(*config)(struct pwm_device *pwm, int ch, int on);
+	int 	(*enable)(struct pwm_device *pwm, int ch, int on);
+};
+
+#define	PM_PWM_LUT_SIZE			64
+#define	PM_PWM_LUT_DUTY_TIME_MAX	512	/* ms */
+#define	PM_PWM_LUT_PAUSE_MAX		(7000 * PM_PWM_LUT_DUTY_TIME_MAX)
+
+/* Flags for Look Up Table */
+#define	PM_PWM_LUT_LOOP		0x01
+#define	PM_PWM_LUT_RAMP_UP	0x02
+#define	PM_PWM_LUT_REVERSE	0x04
+#define	PM_PWM_LUT_PAUSE_HI_EN	0x10
+#define	PM_PWM_LUT_PAUSE_LO_EN	0x20
+
+#define	PM_PWM_LUT_NO_TABLE	0x100
+
+/* PWM LED ID */
+#define	PM_PWM_LED_0		0
+#define	PM_PWM_LED_1		1
+#define	PM_PWM_LED_2		2
+#define	PM_PWM_LED_KPD		3
+#define	PM_PWM_LED_FLASH	4
+#define	PM_PWM_LED_FLASH1	5
+
+/* PWM LED configuration mode */
+#define	PM_PWM_CONF_NONE	0x0
+#define	PM_PWM_CONF_PWM1	0x1
+#define	PM_PWM_CONF_PWM2	0x2
+#define	PM_PWM_CONF_PWM3	0x3
+#define	PM_PWM_CONF_DTEST1	0x4
+#define	PM_PWM_CONF_DTEST2	0x5
+#define	PM_PWM_CONF_DTEST3	0x6
+#define	PM_PWM_CONF_DTEST4	0x7
+
+/*
+ * pm8058_pwm_lut_config - change a PWM device configuration to use LUT
+ *
+ * @pwm: the PWM device
+ * @period_us: period in micro second
+ * @duty_pct: arrary of duty cycles in percent, like 20, 50.
+ * @duty_time_ms: time for each duty cycle in millisecond
+ * @start_idx: start index in lookup table from 0 to MAX-1
+ * @idx_len: number of index
+ * @pause_lo: pause time in millisecond at low index
+ * @pause_hi: pause time in millisecond at high index
+ * @flags: control flags
+ *
+ */
+int pm8058_pwm_lut_config(struct pwm_device *pwm, int period_us,
+			  int duty_pct[], int duty_time_ms, int start_idx,
+			  int len, int pause_lo, int pause_hi, int flags);
+
+/*
+ * pm8058_pwm_lut_enable - control a PWM device to start/stop LUT ramp
+ *
+ * @pwm: the PWM device
+ * @start: to start (1), or stop (0)
+ */
+int pm8058_pwm_lut_enable(struct pwm_device *pwm, int start);
+
+int pm8058_pwm_set_dtest(struct pwm_device *pwm, int enable);
+
+int pm8058_pwm_config_led(struct pwm_device *pwm, int id,
+			  int mode, int max_current);
+
+#endif /* __PMIC8058_PWM_H__ */
diff --git a/include/linux/pmic8058-pwrkey.h b/include/linux/pmic8058-pwrkey.h
new file mode 100644
index 0000000..6953872
--- /dev/null
+++ b/include/linux/pmic8058-pwrkey.h
@@ -0,0 +1,30 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMIC8058_PWRKEY_H__
+#define __PMIC8058_PWRKEY_H__
+
+struct pmic8058_pwrkey_pdata {
+	bool pull_up;
+	/* time after which pwr key event should be generated, if key is
+	 * released before that then end key event is reported
+	 */
+	u16  pwrkey_time_ms;
+	/* time delay for pwr-key state change
+	 * interrupt triggering.
+	 */
+	u32  kpd_trigger_delay_us;
+	u32  wakeup;
+};
+
+#endif /* __PMIC8058_PWRKEY_H__ */
diff --git a/include/linux/pmic8058-upl.h b/include/linux/pmic8058-upl.h
new file mode 100644
index 0000000..a8979f4
--- /dev/null
+++ b/include/linux/pmic8058-upl.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __PMIC8058_UPL_H__
+#define __PMIC8058_UPL_H__
+
+struct pm8058_upl_device;
+
+/* control masks and flags */
+#define PM8058_UPL_MOD_ENABLE_MASK	(0x10)
+#define PM8058_UPL_MOD_ENABLE		(0x10)
+#define PM8058_UPL_MOD_DISABLE		(0x00)
+
+#define PM8058_UPL_OUT_DTEST_MASK	(0xE0)
+#define PM8058_UPL_OUT_GPIO_ONLY	(0x00)
+#define PM8058_UPL_OUT_DTEST_1		(0x80)
+#define PM8058_UPL_OUT_DTEST_2		(0xA0)
+#define PM8058_UPL_OUT_DTEST_3		(0xC0)
+#define PM8058_UPL_OUT_DTEST_4		(0xE0)
+
+#define PM8058_UPL_IN_A_MASK		(0x01)
+#define PM8058_UPL_IN_A_GPIO		(0x00)
+#define PM8058_UPL_IN_A_DTEST		(0x01)
+#define PM8058_UPL_IN_B_MASK		(0x02)
+#define PM8058_UPL_IN_B_GPIO		(0x00)
+#define PM8058_UPL_IN_B_DTEST		(0x02)
+#define PM8058_UPL_IN_C_MASK		(0x04)
+#define PM8058_UPL_IN_C_GPIO		(0x00)
+#define PM8058_UPL_IN_C_DTEST		(0x04)
+#define PM8058_UPL_IN_D_MASK		(0x08)
+#define PM8058_UPL_IN_D_GPIO		(0x00)
+#define PM8058_UPL_IN_D_DTEST		(0x08)
+
+/*
+ * pm8058_upl_request - request a handle to access UPL device
+ */
+struct pm8058_upl_device *pm8058_upl_request(void);
+
+int pm8058_upl_read_truthtable(struct pm8058_upl_device *upldev,
+				u16 *truthtable);
+
+int pm8058_upl_write_truthtable(struct pm8058_upl_device *upldev,
+				u16 truthtable);
+
+/*
+ * pm8058_upl_config - configure UPL I/O settings and UPL enable/disable
+ *
+ * @upldev: the UPL device
+ * @mask: setting mask to configure
+ * @flags: setting flags
+ */
+int pm8058_upl_config(struct pm8058_upl_device *upldev, u32 mask, u32 flags);
+
+#endif /* __PMIC8058_UPL_H__ */
diff --git a/include/linux/pmic8058-vibrator.h b/include/linux/pmic8058-vibrator.h
new file mode 100644
index 0000000..e539058
--- /dev/null
+++ b/include/linux/pmic8058-vibrator.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __PMIC8058_VIBRATOR_H__
+#define __PMIC8058_VIBRATOR_H__
+
+struct pmic8058_vibrator_pdata {
+	int initial_vibrate_ms;
+	int max_timeout_ms;
+
+	int level_mV;
+};
+
+#endif /* __PMIC8058_VIBRATOR_H__ */
diff --git a/include/linux/pmic8058-xoadc.h b/include/linux/pmic8058-xoadc.h
new file mode 100644
index 0000000..8a5820f
--- /dev/null
+++ b/include/linux/pmic8058-xoadc.h
@@ -0,0 +1,84 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Qualcomm XOADC Driver header file
+ */
+
+#ifndef _XOADC_H
+#define _XOADC_H_
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/workqueue.h>
+
+struct xoadc_conv_state {
+	struct adc_conv_slot	*context;
+	struct list_head	slots;
+	struct mutex		list_lock;
+};
+
+#define CHANNEL_VCOIN		0
+#define CHANNEL_VBAT		1
+#define CHANNEL_VCHG		2
+#define CHANNEL_CHG_MONITOR	3
+#define CHANNEL_VPH_PWR		4
+#define CHANNEL_MPP5		5
+#define CHANNEL_MPP6		6
+#define CHANNEL_MPP7		7
+#define CHANNEL_MPP8		8
+#define CHANNEL_MPP9		9
+#define CHANNEL_USB_VBUS	0Xa
+#define CHANNEL_DIE_TEMP	0Xb
+#define CHANNEL_INTERNAL	0xc
+#define CHANNEL_125V		0xd
+#define CHANNEL_INTERNAL_2	0Xe
+#define CHANNEL_MUXOFF		0xf
+
+#define XOADC_MPP_3		0x2
+#define XOADC_MPP_4             0X3
+#define XOADC_MPP_5             0x4
+#define XOADC_MPP_7             0x6
+#define XOADC_MPP_8             0x7
+#define XOADC_MPP_10		0X9
+
+#define XOADC_PMIC_0		0x0
+
+#define CHANNEL_ADC_625_MV      625
+
+struct xoadc_platform_data {
+	struct adc_properties *xoadc_prop;
+	u32 (*xoadc_setup) (void);
+	void (*xoadc_shutdown) (void);
+	void (*xoadc_mpp_config) (void);
+	int (*xoadc_vreg_set) (int);
+	int (*xoadc_vreg_setup) (void);
+	void (*xoadc_vreg_shutdown) (void);
+	u32 xoadc_num;
+	u32 xoadc_wakeup;
+};
+
+int32_t pm8058_xoadc_read_adc_code(uint32_t , int32_t *data);
+
+int32_t pm8058_xoadc_select_chan_and_start_conv(uint32_t,
+						struct adc_conv_slot *);
+
+void pm8058_xoadc_slot_request(uint32_t, struct adc_conv_slot **slot);
+
+void pm8058_xoadc_restore_slot(uint32_t, struct adc_conv_slot *slot);
+
+struct adc_properties *pm8058_xoadc_get_properties(uint32_t);
+
+int32_t pm8058_xoadc_calibrate(uint32_t, struct adc_conv_slot *, int *);
+
+int32_t pm8058_xoadc_registered(void);
+
+int32_t pm8058_xoadc_calib_device(uint32_t adc_instance);
+#endif
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 7c77575..e0c8c3f 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -3,29 +3,31 @@
 
 struct pwm_device;
 
+/* Add __weak functions to support PWM */
+
 /*
  * pwm_request - request a PWM device
  */
-struct pwm_device *pwm_request(int pwm_id, const char *label);
+struct pwm_device __weak *pwm_request(int pwm_id, const char *label);
 
 /*
  * pwm_free - free a PWM device
  */
-void pwm_free(struct pwm_device *pwm);
+void __weak pwm_free(struct pwm_device *pwm);
 
 /*
  * pwm_config - change a PWM device configuration
  */
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
+int __weak pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
 
 /*
  * pwm_enable - start a PWM output toggling
  */
-int pwm_enable(struct pwm_device *pwm);
+int __weak pwm_enable(struct pwm_device *pwm);
 
 /*
  * pwm_disable - stop a PWM output toggling
  */
-void pwm_disable(struct pwm_device *pwm);
+void __weak pwm_disable(struct pwm_device *pwm);
 
 #endif /* __LINUX_PWM_H */
diff --git a/include/linux/qcomwlan7x27a_pwrif.h b/include/linux/qcomwlan7x27a_pwrif.h
new file mode 100644
index 0000000..16e1783
--- /dev/null
+++ b/include/linux/qcomwlan7x27a_pwrif.h
@@ -0,0 +1,20 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_WLAN_PWRIF_H__
+#define __QCOM_WLAN_PWRIF_H__
+
+#include <linux/types.h>
+
+int chip_power_qrf6285(bool on);
+
+#endif /* __QCOM_WLAN_PWRIF_H__ */
diff --git a/include/linux/qcomwlan_pwrif.h b/include/linux/qcomwlan_pwrif.h
new file mode 100644
index 0000000..74d2a80
--- /dev/null
+++ b/include/linux/qcomwlan_pwrif.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __QCOM_WLAN_PWRIF_H__
+#define __QCOM_WLAN_PWRIF_H__
+
+/*
+ * Headers for WLAN Power Interface Functions
+ */
+#include <linux/err.h>
+#include <mach/mpp.h>
+#include <linux/device.h>
+#include <mach/vreg.h>
+#include <linux/delay.h>
+#include <linux/mfd/pmic8058.h>
+#include <linux/regulator/consumer.h>
+#include <linux/gpio.h>
+#include <mach/msm_xo.h>
+#include <asm/mach-types.h>
+#include <mach/rpm-regulator.h>
+
+#define CHIP_POWER_ON         1
+#define CHIP_POWER_OFF        0
+
+int vos_chip_power_qrf8615(int on);
+int qcomwlan_pmic_xo_core_force_enable(int on);
+int qcomwlan_freq_change_1p3v_supply(enum rpm_vreg_freq freq);
+
+#endif /* __QCOM_WLAN_PWRIF_H__ */
diff --git a/include/linux/qcomwlan_secif.h b/include/linux/qcomwlan_secif.h
new file mode 100644
index 0000000..8c6e425
--- /dev/null
+++ b/include/linux/qcomwlan_secif.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_WLAN_SECIF_H__
+#define __QCOM_WLAN_SECIF_H__
+
+#include <crypto/hash.h>
+
+/*
+ * Prototypes for WLAN Security Interface Functions
+ */
+
+extern struct crypto_ahash *
+wcnss_wlan_crypto_alloc_ahash(const char *alg_name, u32 type, u32 mask);
+
+extern int wcnss_wlan_crypto_ahash_digest(struct ahash_request *req);
+extern void wcnss_wlan_crypto_free_ahash(struct crypto_ahash *tfm);
+extern int wcnss_wlan_crypto_ahash_setkey(struct crypto_ahash *tfm,
+					const u8 *key, unsigned int keylen);
+extern struct crypto_ablkcipher *
+wcnss_wlan_crypto_alloc_ablkcipher(const char *alg_name, u32 type, u32 mask);
+extern void wcnss_wlan_ablkcipher_request_free(struct ablkcipher_request *req);
+
+#endif /* __QCOM_WLAN_SECIF_H__ */
diff --git a/include/linux/qcota.h b/include/linux/qcota.h
new file mode 100644
index 0000000..afc6b7f
--- /dev/null
+++ b/include/linux/qcota.h
@@ -0,0 +1,165 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __QCOTA__H
+#define __QCOTA__H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define QCE_OTA_MAX_BEARER   31
+#define OTA_KEY_SIZE 16   /* 128 bits of keys. */
+
+enum qce_ota_dir_enum {
+	QCE_OTA_DIR_UPLINK   = 0,
+	QCE_OTA_DIR_DOWNLINK = 1,
+	QCE_OTA_DIR_LAST
+};
+
+enum qce_ota_algo_enum {
+	QCE_OTA_ALGO_KASUMI = 0,
+	QCE_OTA_ALGO_SNOW3G = 1,
+	QCE_OTA_ALGO_LAST
+};
+
+/**
+ * struct qce_f8_req - qce f8 request
+ * @data_in:	packets input data stream to be ciphered.
+ *		If NULL, streaming mode operation.
+ * @data_out:	ciphered packets output data.
+ * @data_len:	length of data_in and data_out in bytes.
+ * @count_c:	count-C, ciphering sequence number, 32 bit
+ * @bearer:	5 bit of radio bearer identifier.
+ * @ckey:	128 bits of confidentiality key,
+ *		ckey[0] bit 127-120, ckey[1] bit 119-112,.., ckey[15] bit 7-0.
+ * @direction:	uplink or donwlink.
+ * @algorithm:	Kasumi, or Snow3G.
+ *
+ * If data_in is NULL, the engine will run in a special mode called
+ * key stream mode. In this special mode, the engine will generate
+ * key stream output for the number of bytes specified in the
+ * data_len, based on the input parameters of direction, algorithm,
+ * ckey, bearer, and count_c. The data_len is restricted to
+ * the length of multiple of 16 bytes.  Application can then take the
+ * output stream, do a exclusive or to the input data stream, and
+ * generate the final cipher data stream.
+ */
+struct qce_f8_req {
+	uint8_t  *data_in;
+	uint8_t  *data_out;
+	uint16_t  data_len;
+	uint32_t  count_c;
+	uint8_t   bearer;
+	uint8_t   ckey[OTA_KEY_SIZE];
+	enum qce_ota_dir_enum  direction;
+	enum qce_ota_algo_enum algorithm;
+};
+
+/**
+ * struct qce_f8_multi_pkt_req - qce f8 multiple packet request
+ *			Muliptle packets with uniform size, and
+ *			F8 ciphering parameters can be ciphered in a
+ *			single request.
+ *
+ * @num_pkt:		number of packets.
+ *
+ * @cipher_start:	ciphering starts offset within a packet.
+ *
+ * @cipher_size:	number of bytes to be ciphered within a packet.
+ *
+ * @qce_f8_req:		description of the packet and F8 parameters.
+ *			The following fields have special meaning for
+ *			multiple packet operation,
+ *
+ *	@data_len:	data_len indicates the length of a packet.
+ *
+ *	@data_in:	packets are concatenated together in a byte
+ *			stream started at data_in.
+ *
+ *	@data_out:	The returned ciphered output for multiple
+ *			packets.
+ *			Each packet ciphered output are concatenated
+ *			together into a byte stream started at data_out.
+ *			Note, each ciphered packet output area from
+ *			offset 0 to cipher_start-1, and from offset
+ *			cipher_size to data_len -1 are remained
+ *			unaltered from packet input area.
+ *	@count_c:	count-C of the first packet, 32 bit.
+ *
+ *
+ *   In one request, multiple packets can be ciphered, and output to the
+ *   data_out stream.
+ *
+ *   Packet data are layed out contiguously in sequence in data_in,
+ *   and data_out area. Every packet is identical size.
+ *   If the PDU is not byte aligned, set the data_len value of
+ *   to the rounded up value of the packet size. Eg, PDU size of
+ *   253 bits, set the packet size to 32 bytes. Next packet starts on
+ *   the next byte boundary.
+ *
+ *   For each packet, data from offset 0 to cipher_start
+ *   will be left unchanged and output to the data_out area.
+ *   This area of the packet can be for the RLC header, which is not
+ *   to be ciphered.
+ *
+ *   The ciphering of a packet starts from offset cipher_start, for
+ *   cipher_size bytes of data. Data starting from
+ *   offset cipher_start + cipher_size to the end of packet will be left
+ *   unchanged and output to the dataOut area.
+ *
+ *   For each packet the input arguments of bearer, direction,
+ *   ckey, algoritm have to be the same. count_c is the ciphering sequence
+ *   number of the first packet. The 2nd packet's ciphering sequence
+ *   number is assumed to be count_c + 1. The 3rd packet's ciphering sequence
+ *   number is count_c + 2.....
+ *
+ */
+struct qce_f8_multi_pkt_req {
+	uint16_t    num_pkt;
+	uint16_t    cipher_start;
+	uint16_t    cipher_size;
+	struct qce_f8_req qce_f8_req;
+};
+
+/**
+ * struct qce_f9_req - qce f9 request
+ * @message:	message
+ * @msize:	message size in bytes (include the last partial byte).
+ * @last_bits:	valid bits in the last byte of message.
+ * @mac_i:	32 bit message authentication code, to be returned.
+ * @fresh:	random 32 bit number, one per user.
+ * @count_i:	32 bit count-I integrity sequence number.
+ * @direction:	uplink or donwlink.
+ * @ikey:	128 bits of integrity key,
+ *		ikey[0] bit 127-120, ikey[1] bit 119-112,.., ikey[15] bit 7-0.
+ * @algorithm:  Kasumi, or Snow3G.
+ */
+struct qce_f9_req {
+	uint8_t   *message;
+	uint16_t   msize;
+	uint8_t    last_bits;
+	uint32_t   mac_i;
+	uint32_t   fresh;
+	uint32_t   count_i;
+	enum qce_ota_dir_enum direction;
+	uint8_t    ikey[OTA_KEY_SIZE];
+	enum qce_ota_algo_enum algorithm;
+};
+
+#define QCOTA_IOC_MAGIC     0x85
+
+#define QCOTA_F8_REQ _IOWR(QCOTA_IOC_MAGIC, 1, struct qce_f8_req)
+#define QCOTA_F8_MPKT_REQ _IOWR(QCOTA_IOC_MAGIC, 2, struct qce_f8_multi_pkt_req)
+#define QCOTA_F9_REQ _IOWR(QCOTA_IOC_MAGIC, 3, struct qce_f9_req)
+
+#endif /* __QCOTA__H */
diff --git a/include/linux/qfp_fuse.h b/include/linux/qfp_fuse.h
new file mode 100644
index 0000000..8e3fd5e
--- /dev/null
+++ b/include/linux/qfp_fuse.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _QFP_FUSE_H_
+#define _QFP_FUSE_H_
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define QFP_FUSE_IOC_MAGIC          0x92
+
+#define QFP_FUSE_IOC_WRITE          _IO(QFP_FUSE_IOC_MAGIC, 1)
+#define QFP_FUSE_IOC_READ           _IO(QFP_FUSE_IOC_MAGIC, 2)
+
+
+/*
+ * This structure is used to exchange the fuse parameters with the user
+ * space application. The pointer to this structure is passed to the ioctl
+ * function.
+ * offset   = offset from the QFPROM base for the data to be read/written.
+ * size     = number of 32-bit words to be read/written.
+ * data     = pointer to the 32 bit word denoting userspace data.
+ */
+struct qfp_fuse_req {
+	u32 offset;
+	u32 size;
+	u32 *data;
+};
+
+#endif
diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h
index 9e87c1c..d210407 100644
--- a/include/linux/regulator/consumer.h
+++ b/include/linux/regulator/consumer.h
@@ -237,6 +237,11 @@
 {
 }
 
+static inline int regulator_count_voltages(struct regulator *regulator)
+{
+	return 0;
+}
+
 static inline int regulator_set_voltage(struct regulator *regulator,
 					int min_uV, int max_uV)
 {
diff --git a/include/linux/regulator/gpio-regulator.h b/include/linux/regulator/gpio-regulator.h
new file mode 100644
index 0000000..68abf45
--- /dev/null
+++ b/include/linux/regulator/gpio-regulator.h
@@ -0,0 +1,37 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __GPIO_REGULATOR_H__
+#define __GPIO_REGULATOR_H__
+
+#include <linux/regulator/machine.h>
+
+#define GPIO_REGULATOR_DEV_NAME "gpio-regulator"
+
+/**
+ * struct gpio_regulator_platform_data - GPIO regulator platform data
+ * @init_data:		regulator constraints
+ * @gpio_label:		label to use when requesting the GPIO
+ * @regulator_name:	name for regulator used during registration
+ * @gpio:		gpio number
+ * @active_low:		0 = regulator is enabled when GPIO outputs high
+ *			1 = regulator is enabled when GPIO outputs low
+ */
+struct gpio_regulator_platform_data {
+	struct regulator_init_data	init_data;
+	char				*gpio_label;
+	char				*regulator_name;
+	unsigned			gpio;
+	int				active_low;
+};
+
+#endif
diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h
index ce3127a..6804ef3 100644
--- a/include/linux/regulator/machine.h
+++ b/include/linux/regulator/machine.h
@@ -192,6 +192,7 @@
 #ifdef CONFIG_REGULATOR
 void regulator_has_full_constraints(void);
 void regulator_use_dummy_regulator(void);
+void regulator_suppress_info_printing(void);
 #else
 static inline void regulator_has_full_constraints(void)
 {
@@ -200,6 +201,10 @@
 static inline void regulator_use_dummy_regulator(void)
 {
 }
+
+static inline void regulator_suppress_info_printing(void)
+{
+}
 #endif
 
 #endif
diff --git a/include/linux/regulator/pm8058-xo.h b/include/linux/regulator/pm8058-xo.h
new file mode 100644
index 0000000..9b363c4
--- /dev/null
+++ b/include/linux/regulator/pm8058-xo.h
@@ -0,0 +1,30 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8058_XO_H__
+#define __PM8058_XO_H__
+
+#include <linux/regulator/machine.h>
+
+#define PM8058_XO_BUFFER_DEV_NAME	"pm8058-xo-buffer"
+
+/* XO buffer control ids */
+#define PM8058_XO_ID_A0		0
+#define PM8058_XO_ID_A1		1
+
+#define PM8058_XO_ID_MAX	(PM8058_XO_ID_A1 + 1)
+
+struct pm8058_xo_pdata {
+	struct regulator_init_data	init_data;
+};
+
+#endif
diff --git a/include/linux/regulator/pm8921-regulator.h b/include/linux/regulator/pm8921-regulator.h
new file mode 100644
index 0000000..5ed5b0d
--- /dev/null
+++ b/include/linux/regulator/pm8921-regulator.h
@@ -0,0 +1,155 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8921_REGULATOR_H__
+#define __PM8921_REGULATOR_H__
+
+#include <linux/regulator/machine.h>
+
+#define PM8921_REGULATOR_DEV_NAME	"pm8921-regulator"
+
+/**
+ * enum pm8921_vreg_id - PMIC 8921 regulator ID numbers
+ */
+enum pm8921_vreg_id {
+	PM8921_VREG_ID_L1 = 0,
+	PM8921_VREG_ID_L2,
+	PM8921_VREG_ID_L3,
+	PM8921_VREG_ID_L4,
+	PM8921_VREG_ID_L5,
+	PM8921_VREG_ID_L6,
+	PM8921_VREG_ID_L7,
+	PM8921_VREG_ID_L8,
+	PM8921_VREG_ID_L9,
+	PM8921_VREG_ID_L10,
+	PM8921_VREG_ID_L11,
+	PM8921_VREG_ID_L12,
+	PM8921_VREG_ID_L14,
+	PM8921_VREG_ID_L15,
+	PM8921_VREG_ID_L16,
+	PM8921_VREG_ID_L17,
+	PM8921_VREG_ID_L18,
+	PM8921_VREG_ID_L21,
+	PM8921_VREG_ID_L22,
+	PM8921_VREG_ID_L23,
+	PM8921_VREG_ID_L24,
+	PM8921_VREG_ID_L25,
+	PM8921_VREG_ID_L26,
+	PM8921_VREG_ID_L27,
+	PM8921_VREG_ID_L28,
+	PM8921_VREG_ID_L29,
+	PM8921_VREG_ID_S1,
+	PM8921_VREG_ID_S2,
+	PM8921_VREG_ID_S3,
+	PM8921_VREG_ID_S4,
+	PM8921_VREG_ID_S5,
+	PM8921_VREG_ID_S6,
+	PM8921_VREG_ID_S7,
+	PM8921_VREG_ID_S8,
+	PM8921_VREG_ID_LVS1,
+	PM8921_VREG_ID_LVS2,
+	PM8921_VREG_ID_LVS3,
+	PM8921_VREG_ID_LVS4,
+	PM8921_VREG_ID_LVS5,
+	PM8921_VREG_ID_LVS6,
+	PM8921_VREG_ID_LVS7,
+	PM8921_VREG_ID_USB_OTG,
+	PM8921_VREG_ID_HDMI_MVS,
+	PM8921_VREG_ID_NCP,
+	/* The following are IDs for regulator devices to enable pin control. */
+	PM8921_VREG_ID_L1_PC,
+	PM8921_VREG_ID_L2_PC,
+	PM8921_VREG_ID_L3_PC,
+	PM8921_VREG_ID_L4_PC,
+	PM8921_VREG_ID_L5_PC,
+	PM8921_VREG_ID_L6_PC,
+	PM8921_VREG_ID_L7_PC,
+	PM8921_VREG_ID_L8_PC,
+	PM8921_VREG_ID_L9_PC,
+	PM8921_VREG_ID_L10_PC,
+	PM8921_VREG_ID_L11_PC,
+	PM8921_VREG_ID_L12_PC,
+	PM8921_VREG_ID_L14_PC,
+	PM8921_VREG_ID_L15_PC,
+	PM8921_VREG_ID_L16_PC,
+	PM8921_VREG_ID_L17_PC,
+	PM8921_VREG_ID_L18_PC,
+	PM8921_VREG_ID_L21_PC,
+	PM8921_VREG_ID_L22_PC,
+	PM8921_VREG_ID_L23_PC,
+
+	PM8921_VREG_ID_L29_PC,
+	PM8921_VREG_ID_S1_PC,
+	PM8921_VREG_ID_S2_PC,
+	PM8921_VREG_ID_S3_PC,
+	PM8921_VREG_ID_S4_PC,
+
+	PM8921_VREG_ID_S7_PC,
+	PM8921_VREG_ID_S8_PC,
+	PM8921_VREG_ID_LVS1_PC,
+
+	PM8921_VREG_ID_LVS3_PC,
+	PM8921_VREG_ID_LVS4_PC,
+	PM8921_VREG_ID_LVS5_PC,
+	PM8921_VREG_ID_LVS6_PC,
+	PM8921_VREG_ID_LVS7_PC,
+
+	PM8921_VREG_ID_MAX,
+};
+
+/* Pin control input pins. */
+#define PM8921_VREG_PIN_CTRL_NONE	0x00
+#define PM8921_VREG_PIN_CTRL_D1		0x01
+#define PM8921_VREG_PIN_CTRL_A0		0x02
+#define PM8921_VREG_PIN_CTRL_A1		0x04
+#define PM8921_VREG_PIN_CTRL_A2		0x08
+
+/* Minimum high power mode loads in uA. */
+#define PM8921_VREG_LDO_50_HPM_MIN_LOAD		5000
+#define PM8921_VREG_LDO_150_HPM_MIN_LOAD	10000
+#define PM8921_VREG_LDO_300_HPM_MIN_LOAD	10000
+#define PM8921_VREG_LDO_600_HPM_MIN_LOAD	10000
+#define PM8921_VREG_LDO_1200_HPM_MIN_LOAD	10000
+#define PM8921_VREG_SMPS_1500_HPM_MIN_LOAD	100000
+#define PM8921_VREG_SMPS_2000_HPM_MIN_LOAD	100000
+
+/**
+ * enum pm8921_vreg_pin_function - action to perform when pin control is active
+ * %PM8921_VREG_PIN_FN_ENABLE:	pin control enables the regulator
+ * %PM8921_VREG_PIN_FN_MODE:	pin control changes mode from LPM to HPM
+ */
+enum pm8921_vreg_pin_function {
+	PM8921_VREG_PIN_FN_ENABLE = 0,
+	PM8921_VREG_PIN_FN_MODE,
+};
+
+/**
+ * struct pm8921_regulator_platform_data - PMIC 8921 regulator platform data
+ * @init_data:		regulator constraints
+ * @id:			regulator id; from enum pm8921_vreg_id
+ * @pull_down_enable:	0 = no pulldown, 1 = pulldown when regulator disabled
+ * @pin_ctrl:		pin control inputs to use for the regulator; should be
+ *			a combination of PM8921_VREG_PIN_CTRL_* values
+ * @pin_fn:		action to perform when pin control pin is active
+ * @system_uA:		current drawn from regulator not accounted for by any
+ *			regulator framework consumer
+ */
+struct pm8921_regulator_platform_data {
+	struct regulator_init_data	init_data;
+	enum pm8921_vreg_id		id;
+	unsigned			pull_down_enable;
+	unsigned			pin_ctrl;
+	enum pm8921_vreg_pin_function	pin_fn;
+	int				system_uA;
+};
+
+#endif
diff --git a/include/linux/regulator/pmic8058-regulator.h b/include/linux/regulator/pmic8058-regulator.h
new file mode 100644
index 0000000..83d4412
--- /dev/null
+++ b/include/linux/regulator/pmic8058-regulator.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMIC8058_REGULATOR_H__
+#define __PMIC8058_REGULATOR_H__
+
+#include <linux/regulator/machine.h>
+
+/* Low dropout regulator ids */
+#define PM8058_VREG_ID_L0	0
+#define PM8058_VREG_ID_L1	1
+#define PM8058_VREG_ID_L2	2
+#define PM8058_VREG_ID_L3	3
+#define PM8058_VREG_ID_L4	4
+#define PM8058_VREG_ID_L5	5
+#define PM8058_VREG_ID_L6	6
+#define PM8058_VREG_ID_L7	7
+#define PM8058_VREG_ID_L8	8
+#define PM8058_VREG_ID_L9	9
+#define PM8058_VREG_ID_L10	10
+#define PM8058_VREG_ID_L11	11
+#define PM8058_VREG_ID_L12	12
+#define PM8058_VREG_ID_L13	13
+#define PM8058_VREG_ID_L14	14
+#define PM8058_VREG_ID_L15	15
+#define PM8058_VREG_ID_L16	16
+#define PM8058_VREG_ID_L17	17
+#define PM8058_VREG_ID_L18	18
+#define PM8058_VREG_ID_L19	19
+#define PM8058_VREG_ID_L20	20
+#define PM8058_VREG_ID_L21	21
+#define PM8058_VREG_ID_L22	22
+#define PM8058_VREG_ID_L23	23
+#define PM8058_VREG_ID_L24	24
+#define PM8058_VREG_ID_L25	25
+
+/* Switched-mode power supply regulator ids */
+#define PM8058_VREG_ID_S0	26
+#define PM8058_VREG_ID_S1	27
+#define PM8058_VREG_ID_S2	28
+#define PM8058_VREG_ID_S3	29
+#define PM8058_VREG_ID_S4	30
+
+/* Low voltage switch regulator ids */
+#define PM8058_VREG_ID_LVS0	31
+#define PM8058_VREG_ID_LVS1	32
+
+/* Negative charge pump regulator id */
+#define PM8058_VREG_ID_NCP	33
+
+#define PM8058_VREG_MAX		(PM8058_VREG_ID_NCP + 1)
+
+#define PM8058_VREG_PIN_CTRL_NONE	0x00
+#define PM8058_VREG_PIN_CTRL_A0		0x01
+#define PM8058_VREG_PIN_CTRL_A1		0x02
+#define PM8058_VREG_PIN_CTRL_D0		0x04
+#define PM8058_VREG_PIN_CTRL_D1		0x08
+
+/* Minimum high power mode loads in uA. */
+#define PM8058_VREG_LDO_50_HPM_MIN_LOAD		5000
+#define PM8058_VREG_LDO_150_HPM_MIN_LOAD	10000
+#define PM8058_VREG_LDO_300_HPM_MIN_LOAD	10000
+#define PM8058_VREG_SMPS_HPM_MIN_LOAD		50000
+
+/* Pin ctrl enables/disables or toggles high/low power modes */
+enum pm8058_vreg_pin_fn {
+	PM8058_VREG_PIN_FN_ENABLE = 0,
+	PM8058_VREG_PIN_FN_MODE,
+};
+
+struct pm8058_vreg_pdata {
+	struct regulator_init_data	init_data;
+	unsigned			pull_down_enable;
+	unsigned			pin_ctrl;
+	enum pm8058_vreg_pin_fn		pin_fn;
+};
+
+#endif
diff --git a/include/linux/regulator/pmic8901-regulator.h b/include/linux/regulator/pmic8901-regulator.h
new file mode 100644
index 0000000..953c4ad
--- /dev/null
+++ b/include/linux/regulator/pmic8901-regulator.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMIC8901_REGULATOR_H__
+#define __PMIC8901_REGULATOR_H__
+
+#include <linux/regulator/machine.h>
+
+/* Low dropout regulator ids */
+#define PM8901_VREG_ID_L0	0
+#define PM8901_VREG_ID_L1	1
+#define PM8901_VREG_ID_L2	2
+#define PM8901_VREG_ID_L3	3
+#define PM8901_VREG_ID_L4	4
+#define PM8901_VREG_ID_L5	5
+#define PM8901_VREG_ID_L6	6
+
+/* Switched-mode power supply regulator ids */
+#define PM8901_VREG_ID_S0	7
+#define PM8901_VREG_ID_S1	8
+#define PM8901_VREG_ID_S2	9
+#define PM8901_VREG_ID_S3	10
+#define PM8901_VREG_ID_S4	11
+
+/* External regulator controlled by MPP pin ids */
+#define PM8901_VREG_ID_MPP0	12
+
+/* Low voltage switch regulator ids */
+#define PM8901_VREG_ID_LVS0	13
+#define PM8901_VREG_ID_LVS1	14
+#define PM8901_VREG_ID_LVS2	15
+#define PM8901_VREG_ID_LVS3	16
+
+/* Medium voltage switch regulator ids */
+#define PM8901_VREG_ID_MVS0	17
+
+/* USB OTG voltage switch regulator ids */
+#define PM8901_VREG_ID_USB_OTG	18
+
+/* HDMI medium voltage switch regulator ids */
+#define PM8901_VREG_ID_HDMI_MVS	19
+
+#define PM8901_VREG_MAX		(PM8901_VREG_ID_HDMI_MVS + 1)
+
+#define PM8901_VREG_PIN_CTRL_NONE	0x00
+#define PM8901_VREG_PIN_CTRL_A0		0x01
+#define PM8901_VREG_PIN_CTRL_A1		0x02
+#define PM8901_VREG_PIN_CTRL_D0		0x04
+#define PM8901_VREG_PIN_CTRL_D1		0x08
+
+/* Minimum high power mode loads in uA. */
+#define PM8901_VREG_LDO_300_HPM_MIN_LOAD	10000
+#define PM8901_VREG_FTSMPS_HPM_MIN_LOAD		100000
+
+/* Pin ctrl enables/disables or toggles high/low power modes */
+enum pm8901_vreg_pin_fn {
+	PM8901_VREG_PIN_FN_ENABLE = 0,
+	PM8901_VREG_PIN_FN_MODE,
+};
+
+struct pm8901_vreg_pdata {
+	struct regulator_init_data	init_data;
+	unsigned			pull_down_enable;
+	unsigned			pin_ctrl;
+	enum pm8901_vreg_pin_fn		pin_fn;
+	unsigned			active_high; /* For use with MPP. */
+};
+
+#endif
diff --git a/include/linux/remote_spinlock.h b/include/linux/remote_spinlock.h
new file mode 100644
index 0000000..535592e
--- /dev/null
+++ b/include/linux/remote_spinlock.h
@@ -0,0 +1,116 @@
+/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_REMOTE_SPINLOCK_H
+#define __LINUX_REMOTE_SPINLOCK_H
+
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+
+#include <asm/remote_spinlock.h>
+
+/* Grabbing a local spin lock before going for a remote lock has several
+ * advantages:
+ * 1. Get calls to preempt enable/disable and IRQ save/restore for free.
+ * 2. For UP kernel, there is no overhead.
+ * 3. Reduces the possibility of executing the remote spin lock code. This is
+ *    especially useful when the remote CPUs' mutual exclusion instructions
+ *    don't work with the local CPUs' instructions. In such cases, one has to
+ *    use software based mutex algorithms (e.g. Lamport's bakery algorithm)
+ *    which could get expensive when the no. of contending CPUs is high.
+ * 4. In the case of software based mutex algorithm the exection time will be
+ *    smaller since the no. of contending CPUs is reduced by having just one
+ *    contender for all the local CPUs.
+ * 5. Get most of the spin lock debug features for free.
+ * 6. The code will continue to work "gracefully" even when the remote spin
+ *    lock code is stubbed out for debug purposes or when there is no remote
+ *    CPU in some board/machine types.
+ */
+typedef struct {
+	spinlock_t local;
+	_remote_spinlock_t remote;
+} remote_spinlock_t;
+
+#define remote_spin_lock_init(lock, id) \
+	({ \
+		spin_lock_init(&((lock)->local)); \
+		_remote_spin_lock_init(id, &((lock)->remote)); \
+	})
+#define remote_spin_lock(lock) \
+	do { \
+		spin_lock(&((lock)->local)); \
+		_remote_spin_lock(&((lock)->remote)); \
+	} while (0)
+#define remote_spin_unlock(lock) \
+	do { \
+		_remote_spin_unlock(&((lock)->remote)); \
+		spin_unlock(&((lock)->local)); \
+	} while (0)
+#define remote_spin_lock_irqsave(lock, flags) \
+	do { \
+		spin_lock_irqsave(&((lock)->local), flags); \
+		_remote_spin_lock(&((lock)->remote)); \
+	} while (0)
+#define remote_spin_unlock_irqrestore(lock, flags) \
+	do { \
+		_remote_spin_unlock(&((lock)->remote)); \
+		spin_unlock_irqrestore(&((lock)->local), flags); \
+	} while (0)
+#define remote_spin_trylock(lock) \
+	({ \
+		spin_trylock(&((lock)->local)) \
+		? _remote_spin_trylock(&((lock)->remote)) \
+			? 1 \
+			: ({ spin_unlock(&((lock)->local)); 0; }) \
+		: 0; \
+	})
+#define remote_spin_trylock_irqsave(lock, flags) \
+	({ \
+		spin_trylock_irqsave(&((lock)->local), flags) \
+		? _remote_spin_trylock(&((lock)->remote)) \
+			? 1 \
+			: ({ spin_unlock_irqrestore(&((lock)->local), flags); \
+				0; }) \
+		: 0; \
+	})
+
+
+typedef struct {
+	struct mutex local;
+	_remote_mutex_t remote;
+} remote_mutex_t;
+
+#define remote_mutex_init(lock, id) \
+	({ \
+		mutex_init(&((lock)->local)); \
+		_remote_mutex_init(id, &((lock)->remote)); \
+	})
+#define remote_mutex_lock(lock) \
+	do { \
+		mutex_lock(&((lock)->local)); \
+		_remote_mutex_lock(&((lock)->remote)); \
+	} while (0)
+#define remote_mutex_trylock(lock) \
+	({ \
+		mutex_trylock(&((lock)->local)) \
+		? _remote_mutex_trylock(&((lock)->remote)) \
+			? 1 \
+			: ({mutex_unlock(&((lock)->local)); 0; }) \
+		: 0; \
+	})
+#define remote_mutex_unlock(lock) \
+	do { \
+		_remote_mutex_unlock(&((lock)->remote)); \
+		mutex_unlock(&((lock)->local)); \
+	} while (0)
+
+#endif
diff --git a/include/linux/rmt_storage_client.h b/include/linux/rmt_storage_client.h
new file mode 100644
index 0000000..f56819a
--- /dev/null
+++ b/include/linux/rmt_storage_client.h
@@ -0,0 +1,83 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __RMT_STORAGE_SERVER_H
+#define __RMT_STORAGE_SERVER_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define RMT_STORAGE_OPEN              0
+#define RMT_STORAGE_WRITE             1
+#define RMT_STORAGE_CLOSE             2
+#define RMT_STORAGE_SEND_USER_DATA    3
+#define RMT_STORAGE_READ              4
+#define RMT_STORAGE_NOOP              255
+
+#define RMT_STORAGE_MAX_IOVEC_XFR_CNT 5
+#define MAX_NUM_CLIENTS 10
+#define MAX_RAMFS_TBL_ENTRIES 3
+#define RAMFS_BLOCK_SIZE		512
+
+
+enum {
+	RMT_STORAGE_NO_ERROR = 0,	/* Success */
+	RMT_STORAGE_ERROR_PARAM,	/* Invalid parameters */
+	RMT_STORAGE_ERROR_PIPE,		/* RPC pipe failure */
+	RMT_STORAGE_ERROR_UNINIT,	/* Server is not initalized */
+	RMT_STORAGE_ERROR_BUSY,		/* Device busy */
+	RMT_STORAGE_ERROR_DEVICE	/* Remote storage device */
+} rmt_storage_status;
+
+struct rmt_storage_iovec_desc {
+	uint32_t sector_addr;
+	uint32_t data_phy_addr;
+	uint32_t num_sector;
+};
+
+#define MAX_PATH_NAME 32
+struct rmt_storage_event {
+	uint32_t id;		/* Event ID */
+	uint32_t sid;		/* Storage ID */
+	uint32_t handle;	/* Client handle */
+	char path[MAX_PATH_NAME];
+	struct rmt_storage_iovec_desc xfer_desc[RMT_STORAGE_MAX_IOVEC_XFR_CNT];
+	uint32_t xfer_cnt;
+	uint32_t usr_data;
+};
+
+struct rmt_storage_send_sts {
+	uint32_t err_code;
+	uint32_t data;
+	uint32_t handle;
+	uint32_t xfer_dir;
+};
+
+struct rmt_shrd_mem_param {
+	uint32_t sid;		/* Storage ID */
+	uint32_t start;		/* Physical memory address */
+	uint32_t size;		/* Physical memory size */
+	void *base;		/* Virtual user-space memory address */
+};
+
+#define RMT_STORAGE_IOCTL_MAGIC (0xC2)
+
+#define RMT_STORAGE_SHRD_MEM_PARAM \
+	_IOWR(RMT_STORAGE_IOCTL_MAGIC, 0, struct rmt_shrd_mem_param)
+
+#define RMT_STORAGE_WAIT_FOR_REQ \
+	_IOR(RMT_STORAGE_IOCTL_MAGIC, 1, struct rmt_storage_event)
+
+#define RMT_STORAGE_SEND_STATUS \
+	_IOW(RMT_STORAGE_IOCTL_MAGIC, 2, struct rmt_storage_send_sts)
+#endif
diff --git a/include/linux/rtc-msm.h b/include/linux/rtc-msm.h
new file mode 100644
index 0000000..f8f6a16
--- /dev/null
+++ b/include/linux/rtc-msm.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __RTC_MSM_H__
+#define __RTC_MSM_H__
+
+/*
+ * This is the only function which updates the xtime structure. This
+ * function is supposed to be called only once during kernel initialization.
+ * But we need to call this function whenever we receive an RTC update
+ * from MODEM.
+ */
+int rtc_hctosys(void);
+
+extern void msm_pm_set_max_sleep_time(int64_t sleep_time_ns);
+void msmrtc_updateatsuspend(struct timespec *ts);
+
+#ifdef CONFIG_PM
+int64_t msm_timer_get_sclk_time(int64_t *period);
+#endif /* CONFIG_PM */
+
+#endif  /* __RTC_MSM_H__ */
diff --git a/include/linux/rtc/rtc-pm8058.h b/include/linux/rtc/rtc-pm8058.h
new file mode 100644
index 0000000..0690e1a
--- /dev/null
+++ b/include/linux/rtc/rtc-pm8058.h
@@ -0,0 +1,21 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __RTC_PM8058_H__
+#define __RTC_PM8058_H__
+
+struct pm8058_rtc_pdata {
+	bool rtc_write_enable;
+};
+
+#endif /* __RTC_PM8058_H__ */
diff --git a/include/linux/slimbus/slimbus.h b/include/linux/slimbus/slimbus.h
new file mode 100644
index 0000000..fc76b77
--- /dev/null
+++ b/include/linux/slimbus/slimbus.h
@@ -0,0 +1,934 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_SLIMBUS_H
+#define _LINUX_SLIMBUS_H
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/mod_devicetable.h>
+
+/* Interfaces between SLIMbus manager drivers and SLIMbus infrastructure. */
+
+extern struct bus_type slimbus_type;
+
+/* Standard values per SLIMbus spec needed by controllers and devices */
+#define SLIM_CL_PER_SUPERFRAME		6144
+#define SLIM_CL_PER_SUPERFRAME_DIV8	(SLIM_CL_PER_SUPERFRAME >> 3)
+#define SLIM_MAX_CLK_GEAR		10
+#define SLIM_CL_PER_SL			4
+#define SLIM_SL_PER_SUPERFRAME		(SLIM_CL_PER_SUPERFRAME >> 2)
+#define SLIM_FRM_SLOTS_PER_SUPERFRAME	16
+#define SLIM_GDE_SLOTS_PER_SUPERFRAME	2
+
+/*
+ * SLIMbus message types. Related to interpretation of message code.
+ * Values are defined in Table 32 (slimbus spec 1.01.01)
+ */
+#define SLIM_MSG_MT_CORE			0x0
+#define SLIM_MSG_MT_DEST_REFERRED_CLASS		0x1
+#define SLIM_MSG_MT_DEST_REFERRED_USER		0x2
+#define SLIM_MSG_MT_SRC_REFERRED_CLASS		0x5
+#define SLIM_MSG_MT_SRC_REFERRED_USER		0x6
+
+/*
+ * SLIMbus core type Message Codes.
+ * Values are defined in Table 65 (slimbus spec 1.01.01)
+ */
+/* Device management messages */
+#define SLIM_MSG_MC_REPORT_PRESENT               0x1
+#define SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS       0x2
+#define SLIM_MSG_MC_RESET_DEVICE                 0x4
+#define SLIM_MSG_MC_CHANGE_LOGICAL_ADDRESS       0x8
+#define SLIM_MSG_MC_CHANGE_ARBITRATION_PRIORITY  0x9
+#define SLIM_MSG_MC_REQUEST_SELF_ANNOUNCEMENT    0xC
+#define SLIM_MSG_MC_REPORT_ABSENT                0xF
+
+/* Data channel management messages */
+#define SLIM_MSG_MC_CONNECT_SOURCE               0x10
+#define SLIM_MSG_MC_CONNECT_SINK                 0x11
+#define SLIM_MSG_MC_DISCONNECT_PORT              0x14
+#define SLIM_MSG_MC_CHANGE_CONTENT               0x18
+
+/* Information management messages */
+#define SLIM_MSG_MC_REQUEST_INFORMATION          0x20
+#define SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION    0x21
+#define SLIM_MSG_MC_REPLY_INFORMATION            0x24
+#define SLIM_MSG_MC_CLEAR_INFORMATION            0x28
+#define SLIM_MSG_MC_REPORT_INFORMATION           0x29
+
+/* Reconfiguration messages */
+#define SLIM_MSG_MC_BEGIN_RECONFIGURATION        0x40
+#define SLIM_MSG_MC_NEXT_ACTIVE_FRAMER           0x44
+#define SLIM_MSG_MC_NEXT_SUBFRAME_MODE           0x45
+#define SLIM_MSG_MC_NEXT_CLOCK_GEAR              0x46
+#define SLIM_MSG_MC_NEXT_ROOT_FREQUENCY          0x47
+#define SLIM_MSG_MC_NEXT_PAUSE_CLOCK             0x4A
+#define SLIM_MSG_MC_NEXT_RESET_BUS               0x4B
+#define SLIM_MSG_MC_NEXT_SHUTDOWN_BUS            0x4C
+#define SLIM_MSG_MC_NEXT_DEFINE_CHANNEL          0x50
+#define SLIM_MSG_MC_NEXT_DEFINE_CONTENT          0x51
+#define SLIM_MSG_MC_NEXT_ACTIVATE_CHANNEL        0x54
+#define SLIM_MSG_MC_NEXT_DEACTIVATE_CHANNEL      0x55
+#define SLIM_MSG_MC_NEXT_REMOVE_CHANNEL          0x58
+#define SLIM_MSG_MC_RECONFIGURE_NOW              0x5F
+
+/* Value management messages */
+#define SLIM_MSG_MC_REQUEST_VALUE                0x60
+#define SLIM_MSG_MC_REQUEST_CHANGE_VALUE         0x61
+#define SLIM_MSG_MC_REPLY_VALUE                  0x64
+#define SLIM_MSG_MC_CHANGE_VALUE                 0x68
+
+struct slim_controller;
+struct slim_device;
+
+/* Destination type Values defined in Table 33 (slimbus spec 1.01.01) */
+#define SLIM_MSG_DEST_LOGICALADDR	0
+#define SLIM_MSG_DEST_ENUMADDR		1
+#define	SLIM_MSG_DEST_BROADCAST		3
+
+/*
+ * @start_offset: Specifies starting offset in information/value element map
+ * @num_bytes: Can be 1, 2, 3, 4, 6, 8, 12, 16 per spec. This ensures that the
+ *	message will fit in the 40-byte message limit and the slicesize can be
+ *	compatible with values in table 21 (slimbus spec 1.01.01)
+ * @comp: Completion to indicate end of message-transfer. Used if client wishes
+ *	to use the API asynchronously.
+ */
+struct slim_ele_access {
+	u16			start_offset;
+	u8			num_bytes;
+	struct completion	*comp;
+};
+
+/*
+ * struct slim_framer - Represents Slimbus framer.
+ * Every controller may have multiple framers.
+ * Manager is responsible for framer hand-over.
+ * @e_addr: 6 byte Elemental address of the framer.
+ * @rootfreq: Root Frequency at which the framer can run. This is maximum
+ *	frequency (clock gear 10 per slimbus spec) at which the bus can operate.
+ * @superfreq: Superframes per root frequency. Every frame is 6144 cells (bits)
+ *	per slimbus specification.
+ */
+struct slim_framer {
+	u8	e_addr[6];
+	int	rootfreq;
+	int	superfreq;
+};
+#define to_slim_framer(d) container_of(d, struct slim_framer, dev);
+
+/*
+ * struct slim_addrt: slimbus address used internally by the slimbus framework.
+ * @valid: If the device is still there or if the address can be reused.
+ * @eaddr: 6-bytes-long elemental address
+ */
+struct slim_addrt {
+	bool	valid;
+	u8	eaddr[6];
+};
+
+/*
+ * struct slim_msg_txn: Message to be sent by the controller.
+ * Linux framework uses this structure with drivers implementing controller.
+ * This structure has packet header, payload and buffer to be filled (if any)
+ * For the header information, refer to Table 34-36.
+ * @rl: Header field. remaining length.
+ * @mt: Header field. Message type.
+ * @mc: Header field. Message code for type mt.
+ * @dt: Header field. Destination type.
+ * @ec: Element size. Used for elemental access APIs.
+ * @len: Length of payload. (excludes ec)
+ * @tid: Transaction ID. Used for messages expecting response.
+ *	(e.g. relevant for mc = SLIM_MSG_MC_REQUEST_INFORMATION)
+ * @la: Logical address of the device this message is going to.
+ *	(Not used when destination type is broadcast.)
+ * @rbuf: Buffer to be populated by controller when response is received.
+ * @wbuf: Payload of the message. (e.g. channel number for DATA channel APIs)
+ * @comp: Completion structure. Used by controller to notify response.
+ *	(Field is relevant when tid is used)
+ */
+struct slim_msg_txn {
+	u8			rl;
+	u8			mt;
+	u8			mc;
+	u8			dt;
+	u16			ec;
+	u8			len;
+	u8			tid;
+	u8			la;
+	u8			*rbuf;
+	const u8		*wbuf;
+	struct completion	*comp;
+};
+
+/* Internal port state used by slimbus framework to manage data-ports */
+enum slim_port_state {
+	SLIM_P_FREE,
+	SLIM_P_UNCFG,
+	SLIM_P_CFG,
+};
+
+/*
+ * enum slim_port_req: Request port type by user through APIs to manage ports
+ * User can request default, half-duplex or port to be used in multi-channel
+ * configuration. Default indicates a simplex port.
+ */
+enum slim_port_req {
+	SLIM_REQ_DEFAULT,
+	SLIM_REQ_HALF_DUP,
+	SLIM_REQ_MULTI_CH,
+};
+
+/*
+ * enum slim_port_cfg: Port configuration parameters requested.
+ * User can request no configuration, packed data, or MSB aligned data port
+ */
+enum slim_port_cfg {
+	SLIM_CFG_NONE,
+	SLIM_CFG_PACKED,
+	SLIM_CFG_ALIGN_MSB,
+};
+
+/* enum slim_port_flow: Port flow type (inbound/outbound). */
+enum slim_port_flow {
+	SLIM_SRC,
+	SLIM_SINK,
+};
+
+/* enum slim_port_err: Port errors */
+enum slim_port_err {
+	SLIM_P_INPROGRESS,
+	SLIM_P_OVERFLOW,
+	SLIM_P_UNDERFLOW,
+	SLIM_P_DISCONNECT,
+	SLIM_P_NOT_OWNED,
+};
+
+/*
+ * struct slim_port: Internal structure used by framework to manage ports
+ * @err: Port error if any for this port. Refer to enum above.
+ * @state: Port state. Refer to enum above.
+ * @req: Port request for this port.
+ * @cfg: Port configuration for this port.
+ * @flow: Flow type of this port.
+ * @ch: Channel association of this port.
+ * @xcomp: Completion to indicate error, data transfer done event.
+ * @ctrl: Controller to which this port belongs to. This is useful to associate
+ *	port with the SW since port hardware interrupts may only contain port
+ *	information.
+ */
+struct slim_port {
+	enum slim_port_err	err;
+	enum slim_port_state	state;
+	enum slim_port_req	req;
+	enum slim_port_cfg	cfg;
+	enum slim_port_flow	flow;
+	struct slim_ch		*ch;
+	struct completion	*xcomp;
+	struct slim_controller	*ctrl;
+};
+
+/*
+ * enum slim_ch_state: Channel state of a channel.
+ * Channel transition happens from free-to-allocated-to-defined-to-pending-
+ * active-to-active.
+ * Once active, channel can be removed or suspended. Suspended channels are
+ * still scheduled, but data transfer doesn't happen.
+ * Removed channels are not deallocated until dealloc_ch API is used.
+ * Deallocation reset channel state back to free.
+ * Removed channels can be defined with different parameters.
+ */
+enum slim_ch_state {
+	SLIM_CH_FREE,
+	SLIM_CH_ALLOCATED,
+	SLIM_CH_DEFINED,
+	SLIM_CH_PENDING_ACTIVE,
+	SLIM_CH_ACTIVE,
+	SLIM_CH_SUSPENDED,
+	SLIM_CH_PENDING_REMOVAL,
+};
+
+/*
+ * enum slim_ch_proto: Channel protocol used by the channel.
+ * Hard Isochronous channel is not scheduled if current frequency doesn't allow
+ * the channel to be run without flow-control.
+ * Auto isochronous channel will be scheduled as hard-isochronous or push-pull
+ * depending on current bus frequency.
+ * Currently, Push-pull or async or extended channels are not supported.
+ * For more details, refer to slimbus spec
+ */
+enum slim_ch_proto {
+	SLIM_HARD_ISO,
+	SLIM_AUTO_ISO,
+	SLIM_PUSH,
+	SLIM_PULL,
+	SLIM_ASYNC_SMPLX,
+	SLIM_ASYNC_HALF_DUP,
+	SLIM_EXT_SMPLX,
+	SLIM_EXT_HALF_DUP,
+};
+
+/*
+ * enum slim_ch_rate: Most commonly used frequency rate families.
+ * Use 1HZ for push-pull transport.
+ * 4KHz and 11.025KHz are most commonly used in audio applications.
+ * Typically, slimbus runs at frequencies to support channels running at 4KHz
+ * and/or 11.025KHz isochronously.
+ */
+enum slim_ch_rate {
+	SLIM_RATE_1HZ,
+	SLIM_RATE_4000HZ,
+	SLIM_RATE_11025HZ,
+};
+
+/*
+ * enum slim_ch_coeff: Coefficient of a channel used internally by framework.
+ * Coefficient is applicable to channels running isochronously.
+ * Coefficient is calculated based on channel rate multiplier.
+ * (If rate multiplier is power of 2, it's coeff.1 channel. Otherwise it's
+ * coeff.3 channel.
+ */
+enum slim_ch_coeff {
+	SLIM_COEFF_1,
+	SLIM_COEFF_3,
+};
+
+/*
+ * enum slim_ch_control: Channel control.
+ * Activate will schedule channel and/or group of channels in the TDM frame.
+ * Suspend will keep the schedule but data-transfer won't happen.
+ * Remove will remove the channel/group from the TDM frame.
+ */
+enum slim_ch_control {
+	SLIM_CH_ACTIVATE,
+	SLIM_CH_SUSPEND,
+	SLIM_CH_REMOVE,
+};
+
+/* enum slim_ch_dataf: Data format per table 60 from slimbus spec 1.01.01 */
+enum slim_ch_dataf {
+	SLIM_CH_DATAF_NOT_DEFINED = 0,
+	SLIM_CH_DATAF_LPCM_AUDIO = 1,
+	SLIM_CH_DATAF_IEC61937_COMP_AUDIO = 2,
+	SLIM_CH_DATAF_PACKED_PDM_AUDIO = 3,
+};
+
+/* enum slim_ch_auxf: Auxiliary field format per table 59 from slimbus spec */
+enum slim_ch_auxf {
+	SLIM_CH_AUXF_NOT_APPLICABLE = 0,
+	SLIM_CH_AUXF_ZCUV_TUNNEL_IEC60958 = 1,
+	SLIM_CH_USER_DEFINED = 0xF,
+};
+
+/*
+ * struct slim_ch: Channel structure used externally by users of channel APIs.
+ * @prot: Desired slimbus protocol.
+ * @baser: Desired base rate. (Typical isochronous rates are: 4KHz, or 11.025KHz
+ * @dataf: Data format.
+ * @auxf: Auxiliary format.
+ * @ratem: Channel rate multiplier. (e.g. 48KHz channel will have 4KHz base rate
+ *	and 12 as rate multiplier.
+ * @sampleszbits: Sample size in bits.
+ */
+struct slim_ch {
+	enum slim_ch_proto	prot;
+	enum slim_ch_rate	baser;
+	enum slim_ch_dataf	dataf;
+	enum slim_ch_auxf	auxf;
+	u32			ratem;
+	u32			sampleszbits;
+};
+
+/*
+ * struct slim_ich: Internal channel structure used by slimbus framework.
+ * @prop: structure passed by the client.
+ * @coeff: Coefficient of this channel.
+ * @state: Current state of the channel.
+ * @nextgrp: If this channel is part of group, next channel in this group.
+ * @prrate: Presence rate of this channel (per table 62 of the spec)
+ * @offset: Offset of this channel in the superframe.
+ * @newoff: Used during scheduling to hold temporary new offset until the offset
+ *	is accepted/rejected by slimbus reconfiguration.
+ * @interval: Interval of this channel per superframe.
+ * @newintr: Used during scheduling to new interval temporarily.
+ * @seglen: Segment length of this channel.
+ * @rootexp: root exponent of this channel. Rate can be found using rootexp and
+ *	coefficient. Used during scheduling.
+ * @srch: Source ports used by this channel.
+ * @nsrc: number of source ports used by this channel.
+ * @sinkh: Sink port used by this channel.
+ */
+struct slim_ich {
+	struct slim_ch		prop;
+	enum slim_ch_coeff	coeff;
+	enum slim_ch_state	state;
+	u16			nextgrp;
+	u32			prrate;
+	u32			offset;
+	u32			newoff;
+	u32			interval;
+	u32			newintr;
+	u32			seglen;
+	u8			rootexp;
+	u32			*srch;
+	int			nsrc;
+	u32			sinkh;
+};
+
+/*
+ * struct slim_sched: Framework uses this structure internally for scheduling.
+ * @chc3: Array of all active coeffient 3 channels.
+ * @num_cc3: Number of active coeffient 3 channels.
+ * @chc1: Array of all active coeffient 1 channels.
+ * @num_cc1: Number of active coeffient 1 channels.
+ * @subfrmcode: Current subframe-code used by TDM. This is decided based on
+ *	requested message bandwidth and current channels scheduled.
+ * @usedslots: Slots used by all active channels.
+ * @msgsl: Slots used by message-bandwidth.
+ * @pending_msgsl: Used to store pending request of message bandwidth (in slots)
+ *	until the scheduling is accepted by reconfiguration.
+ * @m_reconf: This mutex is held until current reconfiguration (data channel
+ *	scheduling, message bandwidth reservation) is done. Message APIs can
+ *	use the bus concurrently when this mutex is held since elemental access
+ *	messages can be sent on the bus when reconfiguration is in progress.
+ * @slots: Used for debugging purposes to debug/verify current schedule in TDM.
+ */
+struct slim_sched {
+	struct slim_ich	**chc3;
+	int		num_cc3;
+	struct slim_ich	**chc1;
+	int		num_cc1;
+	u32		subfrmcode;
+	u32		usedslots;
+	u32		msgsl;
+	u32		pending_msgsl;
+	struct mutex	m_reconf;
+	u8		*slots;
+};
+
+/*
+ * struct slim_controller: Represents manager for a SlimBUS
+ *				(similar to 'master' on I2C)
+ * @dev: Device interface to this driver
+ * @nr: Board-specific number identifier for this controller/bus
+ * @list: Link with other slimbus controllers
+ * @name: Name for this controller
+ * @clkgear: Current clock gear in which this bus is running
+ * @a_framer: Active framer which is clocking the bus managed by this controller
+ * @m_ctrl: Mutex protecting controller data structures (ports, channels etc)
+ * @addrt: Logical address table
+ * @num_dev: Number of active slimbus slaves on this bus
+ * @txnt: Table of transactions having transaction ID
+ * @last_tid: size of the table txnt (can't grow beyond 256 since TID is 8-bits)
+ * @ports: Ports associated with this controller
+ * @nports: Number of ports supported by the controller
+ * @chans: Channels associated with this controller
+ * @nchans: Number of channels supported
+ * @sched: scheduler structure used by the controller
+ * @dev_released: completion used to signal when sysfs has released this
+ *	controller so that it can be deleted during shutdown
+ * @xfer_msg: Transfer a message on this controller (this can be a broadcast
+ *	control/status message like data channel setup, or a unicast message
+ *	like value element read/write.
+ * @set_laddr: Setup logical address at laddr for the slave with elemental
+ *	address e_addr. Drivers implementing controller will be expected to
+ *	send unicast message to this device with its logical address.
+ * @config_port: Configure a port and make it ready for data transfer. This is
+ *	called by framework after connect_port message is sent successfully.
+ * @framer_handover: If this controller has multiple framers, this API will
+ *	be called to switch between framers if controller desires to change
+ *	the active framer.
+ * @port_xfer: Called to schedule a transfer on port pn. iobuf is physical
+ *	address and the buffer may have to be DMA friendly since data channels
+ *	will be using data from this buffers without SW intervention.
+ * @port_xfer_status: Called by framework when client calls get_xfer_status
+ *	API. Returns how much buffer is actually processed and the port
+ *	errors (e.g. overflow/underflow) if any.
+ */
+struct slim_controller {
+	struct device		dev;
+	unsigned int		nr;
+	struct list_head	list;
+	char			name[SLIMBUS_NAME_SIZE];
+	int			clkgear;
+	struct slim_framer	*a_framer;
+	struct mutex		m_ctrl;
+	struct slim_addrt	*addrt;
+	u8			num_dev;
+	struct slim_msg_txn	**txnt;
+	u8			last_tid;
+	struct slim_port	*ports;
+	int			nports;
+	struct slim_ich		*chans;
+	int			nchans;
+	struct slim_sched	sched;
+	struct completion	dev_released;
+	int			(*xfer_msg)(struct slim_controller *ctrl,
+				struct slim_msg_txn *txn);
+	int			(*set_laddr)(struct slim_controller *ctrl,
+				const u8 *ea, u8 elen, u8 laddr);
+	int			(*config_port)(struct slim_controller *ctrl,
+				u8 port);
+	int			(*framer_handover)(struct slim_controller *ctrl,
+				struct slim_framer *new_framer);
+	int			(*port_xfer)(struct slim_controller *ctrl,
+				u8 pn, u8 *iobuf, u32 len,
+				struct completion *comp);
+	enum slim_port_err	(*port_xfer_status)(struct slim_controller *ctr,
+				u8 pn, u8 **done_buf, u32 *done_len);
+};
+#define to_slim_controller(d) container_of(d, struct slim_controller, dev)
+
+/*
+ * struct slim_driver: Manage Slimbus generic/slave device driver
+ * @probe: Binds this driver to a slimbus device.
+ * @remove: Unbinds this driver from the slimbus device.
+ * @shutdown: Standard shutdown callback used during powerdown/halt.
+ * @suspend: Standard suspend callback used during system suspend
+ * @resume: Standard resume callback used during system resume
+ * @driver: Slimbus device drivers should initialize name and owner field of
+ *	this structure
+ * @id_table: List of slimbus devices supported by this driver
+ */
+struct slim_driver {
+	int				(*probe)(struct slim_device *sldev);
+	int				(*remove)(struct slim_device *sldev);
+	void				(*shutdown)(struct slim_device *sldev);
+	int				(*suspend)(struct slim_device *sldev,
+					pm_message_t pmesg);
+	int				(*resume)(struct slim_device *sldev);
+
+	struct device_driver		driver;
+	const struct slim_device_id	*id_table;
+};
+#define to_slim_driver(d) container_of(d, struct slim_driver, driver)
+
+/*
+ * struct slim_pending_ch: List of pending channels used by framework.
+ * @chan: Channel number
+ * @pending: list of channels
+ */
+struct slim_pending_ch {
+	u8	chan;
+	struct	list_head pending;
+};
+
+/*
+ * Client/device handle (struct slim_device):
+ * ------------------------------------------
+ *  This is the client/device handle returned when a slimbus
+ *  device is registered with a controller. This structure can be provided
+ *  during register_board_info, or can be allocated using slim_add_device API.
+ *  Pointer to this structure is used by client-driver as a handle.
+ *  @dev: Driver model representation of the device.
+ *  @name: Name of driver to use with this device.
+ *  @e_addr: 6-byte elemental address of this device.
+ *  @driver: Device's driver. Pointer to access routines.
+ *  @ctrl: Slimbus controller managing the bus hosting this device.
+ *  @laddr: 1-byte Logical address of this device.
+ *  @mark_define: List of channels pending definition/activation.
+ *  @mark_suspend: List of channels pending suspend.
+ *  @mark_removal: List of channels pending removal.
+ *  @sldev_reconf: Mutex to protect the pending data-channel lists.
+ *  @pending_msgsl: Message bandwidth reservation request by this client in
+ *	slots that's pending reconfiguration.
+ *  @cur_msgsl: Message bandwidth reserved by this client in slots.
+ *  These 3 lists are managed by framework. Lists are populated when client
+ *  calls channel control API without reconfig-flag set and the lists are
+ *  emptied when the reconfiguration is done by this client.
+ */
+struct slim_device {
+	struct device		dev;
+	const char		*name;
+	u8			e_addr[6];
+	struct slim_driver	*driver;
+	struct slim_controller	*ctrl;
+	u8			laddr;
+	struct list_head	mark_define;
+	struct list_head	mark_suspend;
+	struct list_head	mark_removal;
+	struct mutex		sldev_reconf;
+	u32			pending_msgsl;
+	u32			cur_msgsl;
+};
+#define to_slim_device(d) container_of(d, struct slim_device, dev)
+
+/*
+ * struct slim_boardinfo: Declare board info for Slimbus device bringup.
+ * @bus_num: Controller number (bus) on which this device will sit.
+ * @slim_slave: Device to be registered with slimbus.
+ */
+struct slim_boardinfo {
+	int			bus_num;
+	struct slim_device	*slim_slave;
+};
+
+/*
+ * slim_get_logical_addr: Return the logical address of a slimbus device.
+ * @sb: client handle requesting the adddress.
+ * @e_addr: Elemental address of the device.
+ * @e_len: Length of e_addr
+ * @laddr: output buffer to store the address
+ * context: can sleep
+ * -EINVAL is returned in case of invalid parameters, and -ENXIO is returned if
+ *  the device with this elemental address is not found.
+ */
+
+extern int slim_get_logical_addr(struct slim_device *sb, const u8 *e_addr,
+					u8 e_len, u8 *laddr);
+
+
+/* Message APIs Unicast message APIs used by slimbus slave drivers */
+
+/*
+ * Message API access routines.
+ * @sb: client handle requesting elemental message reads, writes.
+ * @msg: Input structure for start-offset, number of bytes to read.
+ * @rbuf: data buffer to be filled with values read.
+ * @len: data buffer size
+ * @wbuf: data buffer containing value/information to be written
+ * context: can sleep
+ * Returns:
+ * -EINVAL: Invalid parameters
+ * -ETIMEDOUT: If controller could not complete the request. This may happen if
+ *  the bus lines are not clocked, controller is not powered-on, slave with
+ *  given address is not enumerated/responding.
+ */
+extern int slim_request_val_element(struct slim_device *sb,
+					struct slim_ele_access *msg, u8 *buf,
+					u8 len);
+extern int slim_request_inf_element(struct slim_device *sb,
+					struct slim_ele_access *msg, u8 *buf,
+					u8 len);
+extern int slim_change_val_element(struct slim_device *sb,
+					struct slim_ele_access *msg,
+					const u8 *buf, u8 len);
+extern int slim_clear_inf_element(struct slim_device *sb,
+					struct slim_ele_access *msg, u8 *buf,
+					u8 len);
+extern int slim_request_change_val_element(struct slim_device *sb,
+					struct slim_ele_access *msg, u8 *rbuf,
+					const u8 *wbuf, u8 len);
+extern int slim_request_clear_inf_element(struct slim_device *sb,
+					struct slim_ele_access *msg, u8 *rbuf,
+					const u8 *wbuf, u8 len);
+
+/*
+ * Broadcast message API:
+ * call this API directly with sbdev = NULL.
+ * For broadcast reads, make sure that buffers are big-enough to incorporate
+ * replies from all logical addresses.
+ * All controllers may not support broadcast
+ */
+extern int slim_xfer_msg(struct slim_controller *ctrl,
+			struct slim_device *sbdev, struct slim_ele_access *msg,
+			u8 mc, u8 *rbuf, const u8 *wbuf, u8 len);
+/* end of message apis */
+
+/* Port management for manager device APIs */
+
+/*
+ * slim_alloc_mgrports: Allocate port on manager side.
+ * @sb: device/client handle.
+ * @req: Port request type.
+ * @nports: Number of ports requested
+ * @rh: output buffer to store the port handles
+ * @hsz: size of buffer storing handles
+ * context: can sleep
+ * This port will be typically used by SW. e.g. client driver wants to receive
+ * some data from audio codec HW using a data channel.
+ * Port allocated using this API will be used to receive the data.
+ * If half-duplex ports are requested, two adjacent ports are allocated for
+ * 1 half-duplex port. So the handle-buffer size should be twice the number
+ * of half-duplex ports to be allocated.
+ * -EDQUOT is returned if all ports are in use.
+ */
+extern int slim_alloc_mgrports(struct slim_device *sb, enum slim_port_req req,
+				int nports, u32 *rh, int hsz);
+
+/* Deallocate the port(s) allocated using the API above */
+extern int slim_dealloc_mgrports(struct slim_device *sb, u32 *hdl, int hsz);
+
+/*
+ * slim_port_xfer: Schedule buffer to be transferred/received using port-handle.
+ * @sb: client handle
+ * @ph: port-handle
+ * @iobuf: buffer to be transferred or populated
+ * @len: buffer size.
+ * @comp: completion signal to indicate transfer done or error.
+ * context: can sleep
+ * Returns number of bytes transferred/received if used synchronously.
+ * Will return 0 if used asynchronously.
+ * Client will call slim_port_get_xfer_status to get error and/or number of
+ * bytes transferred if used asynchronously.
+ */
+extern int slim_port_xfer(struct slim_device *sb, u32 ph, u8 *iobuf, u32 len,
+				struct completion *comp);
+
+/*
+ * slim_port_get_xfer_status: Poll for port transfers, or get transfer status
+ *	after completion is done.
+ * @sb: client handle
+ * @ph: port-handle
+ * @done_buf: return pointer (iobuf from slim_port_xfer) which is processed.
+ * @done_len: Number of bytes transferred.
+ * This can be called when port_xfer complition is signalled.
+ * The API will return port transfer error (underflow/overflow/disconnect)
+ * and/or done_len will reflect number of bytes transferred. Note that
+ * done_len may be valid even if port error (overflow/underflow) has happened.
+ * e.g. If the transfer was scheduled with a few bytes to be transferred and
+ * client has not supplied more data to be transferred, done_len will indicate
+ * number of bytes transferred with underflow error. To avoid frequent underflow
+ * errors, multiple transfers can be queued (e.g. ping-pong buffers) so that
+ * channel has data to be transferred even if client is not ready to transfer
+ * data all the time. done_buf will indicate address of the last buffer
+ * processed from the multiple transfers.
+ */
+extern enum slim_port_err slim_port_get_xfer_status(struct slim_device *sb,
+			u32 ph, u8 **done_buf, u32 *done_len);
+
+/*
+ * slim_connect_ports: Connect port(s) to channel.
+ * @sb: client handle
+ * @srch: source handles to be connected to this channel
+ * @nrsc: number of source ports
+ * @sinkh: sink handle to be connected to this channel
+ * @chanh: Channel with which the ports need to be associated with.
+ * Per slimbus specification, a channel may have multiple source-ports and 1
+ * sink port.Channel specified in chanh needs to be allocated first.
+ */
+extern int slim_connect_ports(struct slim_device *sb, u32 *srch, int nsrc,
+				u32 sinkh, u16 chanh);
+
+/*
+ * slim_disconnect_ports: Disconnect port(s) from channel
+ * @sb: client handle
+ * @ph: ports to be disconnected
+ * @nph: number of ports.
+ * Disconnects ports from a channel.
+ */
+extern int slim_disconnect_ports(struct slim_device *sb, u32 *ph, int nph);
+
+/*
+ * slim_get_slaveport: Get slave port handle
+ * @la: slave device logical address.
+ * @idx: port index at slave
+ * @rh: return handle
+ * @flw: Flow type (source or destination)
+ * This API only returns a slave port's representation as expected by slimbus
+ * driver. This port is not managed by the slimbus driver. Caller is expected
+ * to have visibility of this port since it's a device-port.
+ */
+extern int slim_get_slaveport(u8 la, int idx, u32 *rh, enum slim_port_flow flw);
+
+
+/* Channel functions. */
+
+/*
+ * slim_alloc_ch: Allocate a slimbus channel and return its handle.
+ * @sb: client handle.
+ * @chanh: return channel handle
+ * Slimbus channels are limited to 256 per specification. LSB of the handle
+ * indicates channel number and MSB of the handle is used by the slimbus
+ * framework. -EXFULL is returned if all channels are in use.
+ * Although slimbus specification supports 256 channels, a controller may not
+ * support that many channels.
+ */
+extern int slim_alloc_ch(struct slim_device *sb, u16 *chanh);
+
+/*
+ * slim_dealloc_ch: Deallocate channel allocated using the API above
+ * -EISCONN is returned if the channel is tried to be deallocated without
+ *  being removed first.
+ */
+extern int slim_dealloc_ch(struct slim_device *sb, u16 chanh);
+
+
+/*
+ * slim_define_ch: Define a channel.This API defines channel parameters for a
+ *	given channel.
+ * @sb: client handle.
+ * @prop: slim_ch structure with channel parameters desired to be used.
+ * @chanh: list of channels to be defined.
+ * @nchan: number of channels in a group (1 if grp is false)
+ * @grp: Are the channels grouped
+ * @grph: return group handle if grouping of channels is desired.
+ *	Channels can be grouped if multiple channels use same parameters
+ *	(e.g. 5.1 audio has 6 channels with same parameters. They will all be
+ *	grouped and given 1 handle for simplicity and avoid repeatedly calling
+ *	the API)
+ * -EISCONN is returned if the channel is already connected. -EBUSY is
+ * returned if the channel is already allocated to some other client.
+ */
+extern int slim_define_ch(struct slim_device *sb, struct slim_ch *prop,
+				u16 *chanh, u8 nchan, bool grp, u16 *grph);
+
+/*
+ * slim_control_ch: Channel control API.
+ * @sb: client handle
+ * @grpchanh: group or channel handle to be controlled
+ * @chctrl: Control command (activate/suspend/remove)
+ * @commit: flag to indicate whether the control should take effect right-away.
+ * This API activates, removes or suspends a channel (or group of channels)
+ * grpchanh indicates the channel or group handle (returned by the define_ch
+ * API). Reconfiguration may be time-consuming since it can change all other
+ * active channel allocations on the bus, change in clock gear used by the
+ * slimbus, and change in the control space width used for messaging.
+ * commit makes sure that multiple channels can be activated/deactivated before
+ * reconfiguration is started.
+ * -EXFULL is returned if there is no space in TDM to reserve the bandwidth.
+ * -EISCONN/-ENOTCONN is returned if the channel is already connected or not
+ * yet defined.
+ */
+extern int slim_control_ch(struct slim_device *sb, u16 grpchanh,
+				enum slim_ch_control chctrl, bool commit);
+
+/*
+ * slim_get_ch_state: Channel state.
+ * This API returns the channel's state (active, suspended, inactive etc)
+ */
+extern enum slim_ch_state slim_get_ch_state(struct slim_device *sb,
+						u16 chanh);
+
+/*
+ * slim_reservemsg_bw: Request to reserve bandwidth for messages.
+ * @sb: client handle
+ * @bw_bps: message bandwidth in bits per second to be requested
+ * @commit: indicates whether the reconfiguration needs to be acted upon.
+ * This API call can be grouped with slim_control_ch API call with only one of
+ * the APIs specifying the commit flag to avoid reconfiguration being called too
+ * frequently. -EXFULL is returned if there is no space in TDM to reserve the
+ * bandwidth. -EBUSY is returned if reconfiguration is requested, but a request
+ * is already in progress.
+ */
+extern int slim_reservemsg_bw(struct slim_device *sb, u32 bw_bps, bool commit);
+
+/*
+ * slim_reconfigure_now: Request reconfiguration now.
+ * @sb: client handle
+ * This API does what commit flag in other scheduling APIs do.
+ * -EXFULL is returned if there is no space in TDM to reserve the
+ * bandwidth. -EBUSY is returned if reconfiguration request is already in
+ * progress.
+ */
+extern int slim_reconfigure_now(struct slim_device *sb);
+
+/*
+ * slim_driver_register: Client driver registration with slimbus
+ * @drv:Client driver to be associated with client-device.
+ * This API will register the client driver with the slimbus
+ * It is called from the driver's module-init function.
+ */
+extern int slim_driver_register(struct slim_driver *drv);
+
+/*
+ * slim_add_numbered_controller: Controller bring-up.
+ * @ctrl: Controller to be registered.
+ * A controller is registered with the framework using this API. ctrl->nr is the
+ * desired number with which slimbus framework registers the controller.
+ * Function will return -EBUSY if the number is in use.
+ */
+extern int slim_add_numbered_controller(struct slim_controller *ctrl);
+
+/*
+ * slim_del_controller: Controller tear-down.
+ * Controller added with the above API is teared down using this API.
+ */
+extern int slim_del_controller(struct slim_controller *ctrl);
+
+/*
+ * slim_add_device: Add a new device without register board info.
+ * @ctrl: Controller to which this device is to be added to.
+ * Called when device doesn't have an explicit client-driver to be probed, or
+ * the client-driver is a module installed dynamically.
+ */
+extern int slim_add_device(struct slim_controller *ctrl,
+			struct slim_device *sbdev);
+
+/* slim_remove_device: Remove the effect of slim_add_device() */
+extern void slim_remove_device(struct slim_device *sbdev);
+
+/*
+ * slim_assign_laddr: Assign logical address to a device enumerated.
+ * @ctrl: Controller with which device is enumerated.
+ * @e_addr: 6-byte elemental address of the device.
+ * @e_len: buffer length for e_addr
+ * @laddr: Return logical address.
+ * Called by controller in response to REPORT_PRESENT. Framework will assign
+ * a logical address to this enumeration address.
+ * Function returns -EXFULL to indicate that all logical addresses are already
+ * taken.
+ */
+extern int slim_assign_laddr(struct slim_controller *ctrl, const u8 *e_addr,
+				u8 e_len, u8 *laddr);
+
+/*
+ * slim_msg_response: Deliver Message response received from a device to the
+ *	framework.
+ * @ctrl: Controller handle
+ * @reply: Reply received from the device
+ * @len: Length of the reply
+ * @tid: Transaction ID received with which framework can associate reply.
+ * Called by controller to inform framework about the response received.
+ * This helps in making the API asynchronous, and controller-driver doesn't need
+ * to manage 1 more table other than the one managed by framework mapping TID
+ * with buffers
+ */
+extern void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid,
+				u8 len);
+
+/*
+ * slim_busnum_to_ctrl: Map bus number to controller
+ * @busnum: Bus number
+ * Returns controller representing this bus number
+ */
+extern struct slim_controller *slim_busnum_to_ctrl(u32 busnum);
+
+/*
+ * slim_register_board_info: Board-initialization routine.
+ * @info: List of all devices on all controllers present on the board.
+ * @n: number of entries.
+ * API enumerates respective devices on corresponding controller.
+ * Called from board-init function.
+ */
+#ifdef CONFIG_SLIMBUS
+extern int slim_register_board_info(struct slim_boardinfo const *info,
+					unsigned n);
+#else
+int slim_register_board_info(struct slim_boardinfo const *info,
+					unsigned n)
+{
+	return 0;
+}
+#endif
+
+static inline void *slim_get_ctrldata(const struct slim_controller *dev)
+{
+	return dev_get_drvdata(&dev->dev);
+}
+
+static inline void slim_set_ctrldata(struct slim_controller *dev, void *data)
+{
+	dev_set_drvdata(&dev->dev, data);
+}
+
+static inline void *slim_get_devicedata(const struct slim_device *dev)
+{
+	return dev_get_drvdata(&dev->dev);
+}
+
+static inline void slim_set_clientdata(struct slim_device *dev, void *data)
+{
+	dev_set_drvdata(&dev->dev, data);
+}
+#endif /* _LINUX_SLIMBUS_H */
diff --git a/include/linux/smsc911x.h b/include/linux/smsc911x.h
index 4dde70e..0493fbd 100644
--- a/include/linux/smsc911x.h
+++ b/include/linux/smsc911x.h
@@ -24,7 +24,14 @@
 #include <linux/phy.h>
 
 /* platform_device configuration data, should be assigned to
- * the platform_device's dev.platform_data */
+ * the platform_device's dev.platform_data
+ * Provides 2 GPIO-related fields
+ * reset_gpio to map the ETHERNET_RESET GPIO pin
+ * has_reset_gpio - to indicate if the GPIO is being set(1) or not(0)
+ * and remain compatible with architectures not using GPIOs
+ * Default would be zero if its not being assigned any value.
+ * Both values would need to set in the appropriate board file
+ */
 struct smsc911x_platform_config {
 	unsigned int irq_polarity;
 	unsigned int irq_type;
@@ -32,6 +39,8 @@
 	unsigned int shift;
 	phy_interface_t phy_interface;
 	unsigned char mac[6];
+	unsigned char has_reset_gpio;
+	unsigned int reset_gpio;
 };
 
 /* Constants for platform_device irq polarity configuration */
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 11684d9..dc29f94 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -153,6 +153,7 @@
 	KERN_MAX_LOCK_DEPTH=74, /* int: rtmutex's maximum lock depth */
 	KERN_NMI_WATCHDOG=75, /* int: enable/disable nmi watchdog */
 	KERN_PANIC_ON_NMI=76, /* int: whether we will panic on an unrecovered */
+	KERN_BOOT_REASON = 77, /* int: identify reason system was booted */
 };
 
 
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index d3ec89f..11b410c 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -37,11 +37,19 @@
 	THERMAL_DEVICE_ENABLED,
 };
 
+enum thermal_trip_activation_mode {
+	THERMAL_TRIP_ACTIVATION_DISABLED = 0,
+	THERMAL_TRIP_ACTIVATION_ENABLED,
+};
+
 enum thermal_trip_type {
 	THERMAL_TRIP_ACTIVE = 0,
 	THERMAL_TRIP_PASSIVE,
 	THERMAL_TRIP_HOT,
 	THERMAL_TRIP_CRITICAL,
+	THERMAL_TRIP_CONFIGURABLE_HI,
+	THERMAL_TRIP_CONFIGURABLE_LOW,
+	THERMAL_TRIP_CRITICAL_LOW,
 };
 
 struct thermal_zone_device_ops {
@@ -56,8 +64,12 @@
 		enum thermal_device_mode);
 	int (*get_trip_type) (struct thermal_zone_device *, int,
 		enum thermal_trip_type *);
+	int (*activate_trip_type) (struct thermal_zone_device *, int,
+		enum thermal_trip_activation_mode);
 	int (*get_trip_temp) (struct thermal_zone_device *, int,
 			      unsigned long *);
+	int (*set_trip_temp) (struct thermal_zone_device *, int,
+			      long);
 	int (*get_crit_temp) (struct thermal_zone_device *, unsigned long *);
 	int (*notify) (struct thermal_zone_device *, int,
 		       enum thermal_trip_type);
diff --git a/include/linux/tsif_api.h b/include/linux/tsif_api.h
new file mode 100644
index 0000000..3142b7b
--- /dev/null
+++ b/include/linux/tsif_api.h
@@ -0,0 +1,207 @@
+/**
+ * TSIF driver
+ *
+ * Kernel API
+ *
+ * Copyright (c) 2009-2010, Code Aurora Forum. All rights
+ * reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _TSIF_API_H_
+#define _TSIF_API_H_
+/**
+ * Theory of operation
+ *
+ * TSIF driver maintains internal cyclic data buffer where
+ * received TSIF packets are stored. Size of buffer, in packets,
+ * and its address, may be obtained by tsif_get_info().
+ *
+ * TSIF stream delivered to the client that should register with
+ * TSIF driver using tsif_attach()
+ *
+ * Producer-consumer pattern used. TSIF driver act as producer,
+ * writing data to the buffer; clientis consumer.
+ * 2 indexes maintained by the TSIF driver:
+ * - wi (write index) points to the next item to be written by
+ *   TSIF
+ * - ri (read index) points to the next item available for read
+ *   by the client.
+ * Write index advanced by the TSIF driver when new data
+ * received;
+ * Read index advanced only when client tell so to the TSIF
+ * driver by tsif_reclaim_packets()
+ *
+ * Consumer may directly access data TSIF buffer between ri and
+ * wi. When ri==wi, buffer is empty.
+ *
+ * TSIF driver notifies client about any change by calling
+ * notify function. Client should use tsif_get_state() to query
+ * new state.
+ */
+
+/* bytes in TSIF packet. not customizable */
+#define TSIF_PKT_SIZE             (192)
+
+/**
+ * tsif_pkt_status - get TSIF packet status
+ *
+ * @pkt: TSIF packet location
+ *
+ * Return last DWORD of packet, containing status.
+ * Status dword consists of:
+ * - 3 low bytes TTS
+ * - 1 byte (last byte of packet) with status bits
+ */
+static inline u32 tsif_pkt_status(void *pkt)
+{
+	u32 *x = pkt;
+	return x[TSIF_PKT_SIZE / sizeof(u32) - 1];
+}
+
+/**
+ * Status dword parts for status returned by @tsif_pkt_status
+ */
+#define TSIF_STATUS_TTS(x)   ((x) & 0xffffff)
+#define TSIF_STATUS_VALID(x) ((x) & (1<<24))
+#define TSIF_STATUS_FIRST(x) ((x) & (1<<25))
+#define TSIF_STATUS_OVFLW(x) ((x) & (1<<26))
+#define TSIF_STATUS_ERROR(x) ((x) & (1<<27))
+#define TSIF_STATUS_NULL(x)  ((x) & (1<<28))
+#define TSIF_STATUS_TIMEO(x) ((x) & (1<<30))
+
+/**
+ * enum tsif_state - TSIF device state
+ * @tsif_state_stopped:     Idle state, data acquisition not running
+ * @tsif_state_running:     Data acquisition in progress
+ * @tsif_state_flushing:    Device is flushing
+ *
+ * State transition diagram:
+ *
+ * init -> tsif_state_stopped
+ *
+ * tsif_state_stopped:
+ *   - open -> tsif_state_running
+ *
+ * tsif_state_running:
+ *   - close -> tsif_state_flushing
+ *
+ * tsif_state_flushing:
+ *   - flushed -> tsif_state_stopped
+ */
+enum tsif_state {
+	tsif_state_stopped  = 0,
+	tsif_state_running  = 1,
+	tsif_state_flushing = 2,
+	tsif_state_error    = 3,
+};
+
+/**
+ * tsif_attach - Attach to the device.
+ * @id:       TSIF device ID, used to identify TSIF instance.
+ * @notify:   client callback, called when
+ *            any client visible TSIF state changed.
+ *            This includes new data available and device state change
+ * @data:     client data, will be passed to @notify
+ *
+ * Return     TSIF cookie or error code
+ *
+ * Should be called prior to any other tsif_XXX function.
+ */
+void *tsif_attach(int id, void (*notify)(void *client_data), void *client_data);
+/**
+ * tsif_detach - detach from device
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ */
+void tsif_detach(void *cookie);
+/**
+ * tsif_get_info - get data buffer info
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ * @pdata:     if not NULL, TSIF data buffer will be stored there
+ * @psize:     if not NULL, TSIF data buffer size, in packets,
+ *             will be stored there
+ *
+ * Data buffer information should be queried after each tsif_start() before
+ * using data; since data buffer will be re-allocated on tsif_start()
+ */
+void tsif_get_info(void *cookie, void **pdata, int *psize);
+/**
+ * tsif_set_mode - set TSIF mode
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ * @mode:      desired mode of operation
+ *
+ * Return      error code
+ *
+ * Mode may be changed only when TSIF device is stopped.
+ */
+int tsif_set_mode(void *cookie, int mode);
+/**
+ * tsif_set_time_limit - set TSIF time limit
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ * @value:     desired time limit, 0 to disable
+ *
+ * Return      error code
+ *
+ * Time limit may be changed only when TSIF device is stopped.
+ */
+int tsif_set_time_limit(void *cookie, u32 value);
+/**
+ * tsif_set_buf_config - configure data buffer
+ *
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ * @pkts_in_chunk: requested number of packets per chunk
+ * @chunks_in_buf: requested number of chunks in buffer
+ *
+ * Return      error code
+ *
+ * Parameter selection criteria:
+ *
+ * - @pkts_in_chunk defines size of DMA transfer and, in turn, time between
+ *   consecutive DMA transfers. Increase @pkts_in_chunk reduces chance for
+ *   hardware overflow. If TSIF stats reports overflows, increase it.
+ *
+ * - @chunks_in_buf * @pkts_in_chunk defines total buffer size. Increase this
+ *   parameter if client latency is large and TSIF reports "soft drop" in its
+ *   stats
+ */
+int tsif_set_buf_config(void *cookie, u32 pkts_in_chunk, u32 chunks_in_buf);
+/**
+ * tsif_get_state - query current data buffer information
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ * @ri:        if not NULL, read index will be stored here
+ * @wi:        if not NULL, write index will be stored here
+ * @state:     if not NULL, state will be stored here
+ */
+void tsif_get_state(void *cookie, int *ri, int *wi, enum tsif_state *state);
+/**
+ * tsif_start - start data acquisition
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ *
+ * Return      error code
+ */
+int tsif_start(void *cookie);
+/**
+ * tsif_stop - stop data acquisition
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ *
+ * Data buffer allocated during this function call; thus client should
+ * query data buffer info using tsif_get_info() and reset its data pointers.
+ */
+void tsif_stop(void *cookie);
+/**
+ * tsif_reclaim_packets - inform that buffer space may be reclaimed
+ * @cookie:    TSIF cookie previously obtained with tsif_attach()
+ * @ri:        new value for read index
+ */
+void tsif_reclaim_packets(void *cookie, int ri);
+
+#endif /* _TSIF_API_H_ */
+
diff --git a/include/linux/tzcom.h b/include/linux/tzcom.h
new file mode 100644
index 0000000..1a3c774
--- /dev/null
+++ b/include/linux/tzcom.h
@@ -0,0 +1,101 @@
+/* Qualcomm TrustZone communicator API */
+
+#ifndef __TZCOM_H_
+#define __TZCOM_H_
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/**
+ * struct tzcom_register_svc_op_req - for register service ioctl request
+ * @svc_id - service id (shared between userspace and TZ)
+ * @cmd_id_low - low number in cmd_id range (shared between userspace and TZ)
+ * @cmd_id_high - high number in cmd_id range (shared between userspace and TZ)
+ * @instance_id - unique id for the given service generated by tzcom driver
+ */
+struct tzcom_register_svc_op_req {
+	uint32_t svc_id; /* in */
+	uint32_t cmd_id_low; /* in */
+	uint32_t cmd_id_high; /* in */
+	uint32_t instance_id; /* out */
+};
+
+/**
+ * struct tzcom_unregister_svc_op_req - for unregister service ioctl request
+ * @svc_id - service id to unregister (provided in register_service request)
+ * @instance_id - instance id generated in register service request
+ */
+struct tzcom_unregister_svc_op_req {
+	uint32_t svc_id; /* in */
+	uint32_t instance_id; /* in */
+};
+
+/**
+ * struct tzcom_next_cmd_op_req - for read next command ioctl request
+ * @svc_id - has to be a registered svc_id (see @tzcom_register_svc_op_req)
+ * @instance_id - unique id for the given service (see @tzcom_register_svc_op_req)
+ * @cmd_id - command to execute on the given service, received from TZ
+ * @req_len - request buffer length, received from TZ
+ * @req - request buffer, received from TZ
+ */
+struct tzcom_next_cmd_op_req {
+	uint32_t svc_id; /* in */
+	uint32_t instance_id; /* in */
+	uint32_t cmd_id; /* out */
+	unsigned int req_len; /* in/out */
+	void *req_buf; /* in/out */
+};
+
+/**
+ * struct tzcom_send_cmd_op_req - for send command ioctl request
+ * @cmd_id - command to execute on TZBSP side
+ * @cmd_len - command buffer length
+ * @cmd_buf - command buffer
+ * @resp_len - response buffer length
+ * @resp_buf - response buffer
+ */
+struct tzcom_send_cmd_op_req {
+	uint32_t cmd_id; /* in */
+	unsigned int cmd_len; /* in */
+	void *cmd_buf; /* in */
+	unsigned int resp_len; /* in/out */
+	void *resp_buf; /* in/out */
+};
+
+/**
+ * struct tzcom_cont_cmd_op_req - for continue command ioctl request. used
+ * as a trigger from HLOS service to notify TZCOM that it's done with its
+ * operation and provide the response for TZCOM can continue the incomplete
+ * command execution
+ * @cmd_id - Command to continue filled in by tzcom as tzcom knows about the
+ *           last incomplete command.
+ * @instance_id - Instance id of the svc
+ * @resp_len - Length of the response
+ * @resp_buf - Response buffer where the response of the cmd should go.
+ */
+struct tzcom_cont_cmd_op_req {
+	uint32_t cmd_id; /* out */
+	uint32_t instance_id; /* in */
+	unsigned int resp_len; /* in */
+	void *resp_buf; /* in */
+};
+
+#define TZCOM_IOC_MAGIC    0x97
+
+/* For HLOS service */
+#define TZCOM_IOCTL_REGISTER_SERVICE_REQ \
+	_IOWR(TZCOM_IOC_MAGIC, 1, struct tzcom_register_svc_op_req)
+/* For HLOS service */
+#define TZCOM_IOCTL_UNREGISTER_SERVICE_REQ \
+	_IOWR(TZCOM_IOC_MAGIC, 2, struct tzcom_unregister_svc_op_req)
+/* For TZ service */
+#define TZCOM_IOCTL_SEND_CMD_REQ \
+	_IOWR(TZCOM_IOC_MAGIC, 3, struct tzcom_send_cmd_op_req)
+/* For HLOS service */
+#define TZCOM_IOCTL_READ_NEXT_CMD_REQ \
+	_IOWR(TZCOM_IOC_MAGIC, 4, struct tzcom_next_cmd_op_req)
+/* For TZ service */
+#define TZCOM_IOCTL_CONTINUE_CMD_REQ \
+	_IOWR(TZCOM_IOC_MAGIC, 5, struct tzcom_cont_cmd_op_req)
+
+#endif /* __TZCOM_H_ */
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 73c7df4..583ceb8 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -321,6 +321,8 @@
 	u8 otg_port;			/* 0, or number of OTG/HNP port */
 	unsigned is_b_host:1;		/* true during some HNP roleswitches */
 	unsigned b_hnp_enable:1;	/* OTG: did A-Host enable HNP? */
+	unsigned hnp_support:1;		/* OTG: HNP is supported on OTG port */
+	struct delayed_work hnp_polling;/* OTG: HNP polling work */
 	unsigned sg_tablesize;		/* 0 or largest number of sg list entries */
 
 	int devnum_next;		/* Next open device number in
@@ -362,6 +364,16 @@
  * limit. Because the arrays need to add a bit for hub status data, we
  * do 31, so plus one evens out to four bytes.
  */
+
+#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
+#define USB_OTG_SUSPEND		0x1
+#define USB_OTG_ENUMERATE	0x2
+#define USB_OTG_DISCONNECT	0x4
+#define USB_OTG_RESUME		0x8
+#define USB_OTG_REMOTEWAKEUP	0x10
+#define USB_OTG_WAKEUP_ALL	0x20
+#endif
+
 #define USB_MAXCHILDREN		(31)
 
 struct usb_tt;
@@ -475,6 +487,18 @@
 	struct dentry *usbfs_dentry;
 #endif
 
+#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
+	/*otg add ons */
+	u8 otgdevice;				/*device is otg type */
+
+	/*otg states from otg driver, suspend, enumerate, disconnect */
+	u8 otgstate;
+	void *otgpriv;
+	void (*otg_notif) (void *otg_priv,
+				unsigned long notif, unsigned long data);
+	void *hcd_priv;
+	void (*hcd_suspend) (void *hcd_priv);
+#endif
 	int maxchild;
 	struct usb_device *children[USB_MAXCHILDREN];
 
@@ -1584,8 +1608,15 @@
 #define USB_DEVICE_REMOVE	0x0002
 #define USB_BUS_ADD		0x0003
 #define USB_BUS_REMOVE		0x0004
+#define USB_DEVICE_CONFIG	0x0005
+
+#ifdef CONFIG_USB
 extern void usb_register_notify(struct notifier_block *nb);
 extern void usb_unregister_notify(struct notifier_block *nb);
+#else
+static inline void usb_register_notify(struct notifier_block *nb) {}
+static inline void usb_unregister_notify(struct notifier_block *nb) {}
+#endif
 
 #ifdef DEBUG
 #define dbg(format, arg...)						\
diff --git a/include/linux/usb/android.h b/include/linux/usb/android.h
new file mode 100644
index 0000000..9d7e4a8
--- /dev/null
+++ b/include/linux/usb/android.h
@@ -0,0 +1,24 @@
+/*
+ * Platform data for Android USB
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef	__LINUX_USB_ANDROID_H
+#define	__LINUX_USB_ANDROID_H
+
+struct android_usb_platform_data {
+	int (*update_pid_and_serial_num)(uint32_t, const char *);
+};
+
+#endif	/* __LINUX_USB_ANDROID_H */
diff --git a/include/linux/usb/android_composite.h b/include/linux/usb/android_composite.h
new file mode 100644
index 0000000..438dfa4
--- /dev/null
+++ b/include/linux/usb/android_composite.h
@@ -0,0 +1,97 @@
+/*
+ * Platform data for Android USB
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef	__LINUX_USB_ANDROID_H
+#define	__LINUX_USB_ANDROID_H
+
+#include <linux/usb/composite.h>
+#include <linux/if_ether.h>
+
+struct android_usb_function {
+	struct list_head	list;
+	char			*name;
+	int 			(*bind_config)(struct usb_configuration *c);
+};
+
+struct android_usb_product {
+	/* Default product ID. */
+	__u16 product_id;
+
+	/* List of function names associated with this product.
+	 * This is used to compute the USB product ID dynamically
+	 * based on which functions are enabled.
+	 */
+	int num_functions;
+	char **functions;
+};
+
+struct android_usb_platform_data {
+	/* USB device descriptor fields */
+	__u16 vendor_id;
+
+	/* Default product ID. */
+	__u16 product_id;
+
+	__u16 version;
+
+	char *product_name;
+	char *manufacturer_name;
+	char *serial_number;
+
+	/* List of available USB products.
+	 * This is used to compute the USB product ID dynamically
+	 * based on which functions are enabled.
+	 * if num_products is zero or no match can be found,
+	 * we use the default product ID
+	 */
+	int num_products;
+	struct android_usb_product *products;
+
+	/* List of all supported USB functions.
+	 * This list is used to define the order in which
+	 * the functions appear in the configuration's list of USB interfaces.
+	 * This is necessary to avoid depending upon the order in which
+	 * the individual function drivers are initialized.
+	 */
+	int num_functions;
+	char **functions;
+};
+
+/* Platform data for "usb_mass_storage" driver. */
+struct usb_mass_storage_platform_data {
+	/* Contains values for the SC_INQUIRY SCSI command. */
+	char *vendor;
+	char *product;
+	int release;
+
+	char can_stall;
+	/* number of LUNS */
+	int nluns;
+};
+
+/* Platform data for USB ethernet driver. */
+struct usb_ether_platform_data {
+	u8	ethaddr[ETH_ALEN];
+	u32	vendorID;
+	const char *vendorDescr;
+};
+
+extern void android_register_function(struct android_usb_function *f);
+
+extern int android_enable_function(struct usb_function *f, int enable);
+
+
+#endif	/* __LINUX_USB_ANDROID_H */
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index 0fd3fbd..736203b 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -146,6 +146,10 @@
 
 #define USB_ENDPOINT_HALT		0	/* IN/OUT will STALL */
 
+#define OTG_STATUS_SELECTOR	0xF000
+#define THOST_REQ_POLL		2000    /* msec */
+#define HOST_REQUEST_FLAG	0
+
 /* Bit array elements as returned by the USB_REQ_GET_STATUS request. */
 #define USB_DEV_STAT_U1_ENABLED		2	/* transition into U1 state */
 #define USB_DEV_STAT_U2_ENABLED		3	/* transition into U2 state */
diff --git a/include/linux/usb/f_mtp.h b/include/linux/usb/f_mtp.h
index 7422b17..9f21846 100644
--- a/include/linux/usb/f_mtp.h
+++ b/include/linux/usb/f_mtp.h
@@ -35,6 +35,11 @@
 
 #endif /* __KERNEL__ */
 
+/* Constants for MTP_SET_INTERFACE_MODE */
+#define MTP_INTERFACE_MODE_MTP  0
+#define MTP_INTERFACE_MODE_PTP  1
+
+
 struct mtp_file_range {
 	/* file descriptor for file to transfer */
 	int			fd;
@@ -65,6 +70,8 @@
  * The file is created if it does not exist.
  */
 #define MTP_RECEIVE_FILE           _IOW('M', 1, struct mtp_file_range)
+/* Sets the driver mode to either MTP or PTP */
+#define MTP_SET_INTERFACE_MODE     _IOW('M', 2, int)
 /* Sends an event to the host via the interrupt endpoint */
 #define MTP_SEND_EVENT             _IOW('M', 3, struct mtp_event)
 /* Sends the specified file range to the host,
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index dd1571d..c83035d 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -486,6 +486,7 @@
 	unsigned			b_hnp_enable:1;
 	unsigned			a_hnp_support:1;
 	unsigned			a_alt_hnp_support:1;
+	unsigned			host_request:1;
 	const char			*name;
 	struct device			dev;
 };
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 00311fe..8942eea 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -20,6 +20,7 @@
 
 #include <linux/types.h>
 #include <linux/usb/otg.h>
+#include <linux/wakelock.h>
 
 /**
  * Supported USB modes
@@ -68,6 +69,7 @@
 };
 
 #define IDEV_CHG_MAX	1500
+#define IDEV_CHG_MIN	500
 #define IUNIT		100
 
 /**
@@ -102,13 +104,27 @@
  * USB_DCP_CHARGER	Dedicated charger port (AC charger/ Wall charger).
  * USB_CDP_CHARGER	Charging downstream port. Enumeration can happen and
  *                      IDEV_CHG_MAX can be drawn irrespective of USB state.
- *
+ * USB_ACA_A_CHARGER	B-device is connected on accessory port with charger
+ *                      connected on charging port. This configuration allows
+ *                      charging in host mode.
+ * USB_ACA_B_CHARGER	No device (or A-device without VBUS) is connected on
+ *                      accessory port with charger connected on charging port.
+ * USB_ACA_C_CHARGER	A-device (with VBUS) is connected on
+ *                      accessory port with charger connected on charging port.
+ * USB_ACA_DOCK_CHARGER	A docking station that has one upstream port and one
+ *			or more downstream ports. Capable of supplying
+ *			IDEV_CHG_MAX irrespective of devices connected on
+ *			accessory ports.
  */
 enum usb_chg_type {
 	USB_INVALID_CHARGER = 0,
 	USB_SDP_CHARGER,
 	USB_DCP_CHARGER,
 	USB_CDP_CHARGER,
+	USB_ACA_A_CHARGER,
+	USB_ACA_B_CHARGER,
+	USB_ACA_C_CHARGER,
+	USB_ACA_DOCK_CHARGER,
 };
 
 /**
@@ -124,6 +140,7 @@
  *              OTG switch is controller by user.
  * @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
  *              dfab_usb_hs_clk in case of 8660 and 8960.
+ * @pmic_id_irq: IRQ number assigned for PMIC USB ID line.
  */
 struct msm_otg_platform_data {
 	int *phy_init_seq;
@@ -135,6 +152,7 @@
 	enum msm_usb_phy_type phy_type;
 	void (*setup_gpio)(enum usb_otg_state state);
 	char *pclk_src_name;
+	int pmic_id_irq;
 };
 
 /**
@@ -158,6 +176,12 @@
  * @chg_type: The type of charger attached.
  * @dcd_retires: The retry count used to track Data contact
  *               detection process.
+ * @wlock: Wake lock struct to prevent system suspend when
+ *               USB is active.
+ * @usbdev_nb: The notifier block used to know about the B-device
+ *             connected. Useful only when ACA_A charger is
+ *             connected.
+ * @mA_port: The amount of current drawn by the attached B-device.
  */
 struct msm_otg {
 	struct otg_transceiver otg;
@@ -171,6 +195,9 @@
 	void __iomem *regs;
 #define ID		0
 #define B_SESS_VLD	1
+#define ID_A		2
+#define ID_B		3
+#define ID_C		4
 	unsigned long inputs;
 	struct work_struct sm_work;
 	atomic_t in_lpm;
@@ -180,6 +207,32 @@
 	enum usb_chg_state chg_state;
 	enum usb_chg_type chg_type;
 	u8 dcd_retries;
+	struct wake_lock wlock;
+	struct notifier_block usbdev_nb;
+	unsigned mA_port;
+	unsigned long caps;
+	/*
+	 * Allowing PHY power collpase turns off the HSUSB 3.3v and 1.8v
+	 * analog regulators while going to low power mode.
+	 * Currently only 8960(28nm PHY) has the support to allowing PHY
+	 * power collapse since it doesn't have leakage currents while
+	 * turning off the power rails.
+	 */
+#define ALLOW_PHY_POWER_COLLAPSE	BIT(0)
+	/*
+	 * Allow PHY RETENTION mode before turning off the digital
+	 * voltage regulator(VDDCX).
+	 */
+#define ALLOW_PHY_RETENTION		BIT(1)
+	  /*
+	   * Disable the OTG comparators to save more power
+	   * if depends on PMIC for VBUS and ID interrupts.
+	   */
+#define ALLOW_PHY_COMP_DISABLE		BIT(2)
+	unsigned long lpm_flags;
+#define PHY_PWR_COLLAPSED		BIT(0)
+#define PHY_RETENTIONED			BIT(1)
+#define PHY_OTG_COMP_DISABLED		BIT(2)
 };
 
 #endif
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index 6e97a2d..55dc134 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -21,6 +21,7 @@
 #define USB_CAPLENGTH        (MSM_USB_BASE + 0x0100) /* 8 bit */
 
 #define USB_USBCMD           (MSM_USB_BASE + 0x0140)
+#define USB_USBSTS           (MSM_USB_BASE + 0x0144)
 #define USB_PORTSC           (MSM_USB_BASE + 0x0184)
 #define USB_OTGSC            (MSM_USB_BASE + 0x01A4)
 #define USB_USBMODE          (MSM_USB_BASE + 0x01A8)
@@ -41,6 +42,11 @@
 #define ULPI_DATA(n)          ((n) & 255)
 #define ULPI_DATA_READ(n)     (((n) >> 8) & 255)
 
+/* synopsys 28nm phy registers */
+#define ULPI_PWR_CLK_MNG_REG	0x88
+#define OTG_COMP_DISABLE	BIT(0)
+
+#define PHY_ALT_INT		(1 << 28) /* PHY alternate interrupt */
 #define ASYNC_INTR_CTRL         (1 << 29) /* Enable async interrupt */
 #define ULPI_STP_CTRL           (1 << 30) /* Block communication with PHY */
 #define PHY_RETEN               (1 << 1) /* PHY retention enable/disable */
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index d87f44f..61814a7 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -35,6 +35,34 @@
 	OTG_STATE_A_VBUS_ERR,
 };
 
+enum usb_otg_event {
+	/* Device is not connected within
+	 * TA_WAIT_BCON or not responding.
+	 */
+	OTG_EVENT_DEV_CONN_TMOUT,
+	/* B-device returned STALL for
+	 * B_HNP_ENABLE feature request.
+	 */
+	OTG_EVENT_NO_RESP_FOR_HNP_ENABLE,
+	/* HUB class devices are not
+	 * supported.
+	 */
+	OTG_EVENT_HUB_NOT_SUPPORTED,
+	/* Device is not supported i.e
+	 * not listed in TPL.
+	 */
+	OTG_EVENT_DEV_NOT_SUPPORTED,
+	/* HNP failed due to
+	 * TA_AIDL_BDIS timeout or
+	 * TB_ASE0_BRST timeout
+	 */
+	OTG_EVENT_HNP_FAILED,
+	/* B-device did not detect VBUS
+	 * within TB_SRP_FAIL time.
+	 */
+	OTG_EVENT_NO_RESP_FOR_SRP,
+};
+
 enum usb_xceiv_events {
 	USB_EVENT_NONE,         /* no events or cable disconnected */
 	USB_EVENT_VBUS,         /* vbus valid event */
@@ -111,6 +139,10 @@
 	/* start or continue HNP role switch */
 	int	(*start_hnp)(struct otg_transceiver *otg);
 
+	/* send events to user space */
+	int	(*send_event)(struct otg_transceiver *otg,
+			enum usb_otg_event event);
+
 };
 
 
@@ -164,6 +196,10 @@
 		otg->shutdown(otg);
 }
 
+/* for USB core, host and peripheral controller drivers */
+/* Context: can sleep */
+extern int otg_send_event(enum usb_otg_event event);
+
 /* for usb host and peripheral controller drivers */
 #ifdef CONFIG_USB_OTG_UTILS
 extern struct otg_transceiver *otg_get_transceiver(void);
diff --git a/include/linux/vcm.h b/include/linux/vcm.h
new file mode 100644
index 0000000..776b8b2
--- /dev/null
+++ b/include/linux/vcm.h
@@ -0,0 +1,652 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _VCM_H_
+#define _VCM_H_
+
+/* All undefined types must be defined using platform specific headers */
+
+#include <linux/vcm_types.h>
+
+/*
+ * Virtual contiguous memory (VCM) region primitives.
+ *
+ * Current memory mapping software uses a CPU centric management
+ * model. This makes sense in general, average hardware only contains an
+ * CPU MMU and possibly a graphics MMU. If every device in the system
+ * has one or more MMUs a CPU centric MM programming model breaks down.
+ *
+ * Looking at mapping from a system-wide perspective reveals a general
+ * graph problem. Each node that talks to memory, either through an MMU
+ * or directly (via physical memory) can be thought of as the device end
+ * of a mapping edge. The other edge is the physical memory that is
+ * mapped.
+ *
+ * In the direct mapped case, it is useful to give the device an
+ * MMU. This one-to-one MMU allows direct mapped devices to
+ * participate in graph management, they simply see memory through a
+ * one-to-one mapping.
+ *
+ * The CPU nodes can also be brought under the same mapping
+ * abstraction with the use of a light overlay on the existing
+ * VMM. This light overlay brings the VMM's page table abstraction for
+ * each process and the kernel into the graph management API.
+ *
+ * Taken together this system wide approach provides a capability that
+ * is greater than the sum of its parts by allowing users to reason
+ * about system wide mapping issues without getting bogged down in CPU
+ * centric device page table management issues.
+ */
+
+
+/*
+ * Creating, freeing and managing VCMs.
+ *
+ * A VCM region is a virtual space that can be reserved from and
+ * associated with one or more devices. At creation the user can
+ * specify an offset to start addresses and a length of the entire VCM
+ * region. Reservations out of a VCM region are always contiguous.
+ */
+
+/**
+ * vcm_create() - Create a VCM region
+ * @start_addr:		The starting address of the VCM region.
+ * @len:		The len of the VCM region. This must be at least
+ *			vcm_get_min_page_size() bytes.
+ *
+ * A VCM typically abstracts a page table.
+ *
+ * All functions in this API are passed and return opaque things
+ * because the underlying implementations will vary. The goal
+ * is really graph management. vcm_create() creates the "device end"
+ * of an edge in the mapping graph.
+ *
+ * The return value is non-zero if a VCM has successfully been
+ * created. It will return zero if a VCM region cannot be created or
+ * len is invalid.
+ */
+struct vcm *vcm_create(unsigned long start_addr, size_t len);
+
+
+/**
+ * vcm_create_from_prebuilt() - Create a VCM region from an existing region
+ * @ext_vcm_id:		An external opaque value that allows the
+ *			implementation to reference an already built table.
+ *
+ * The ext_vcm_id will probably reference a page table that's been built
+ * by the VM.
+ *
+ * The platform specific implementation will provide this.
+ *
+ * The return value is non-zero if a VCM has successfully been created.
+ */
+struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id);
+
+
+/**
+ * vcm_clone() - Clone a VCM
+ * @vcm:		A VCM to clone from.
+ *
+ * Perform a VCM "deep copy." The resulting VCM will match the original at
+ * the point of cloning. Subsequent updates to either VCM will only be
+ * seen by that VCM.
+ *
+ * The return value is non-zero if a VCM has been successfully cloned.
+ */
+struct vcm *vcm_clone(struct vcm *vcm);
+
+
+/**
+ * vcm_get_start_addr() - Get the starting address of the VCM region.
+ * @vcm:		The VCM we're interested in getting the starting
+ *			address of.
+ *
+ * The return value will be 1 if an error has occurred.
+ */
+size_t vcm_get_start_addr(struct vcm *vcm);
+
+
+/**
+ * vcm_get_len() - Get the length of the VCM region.
+ * @vcm:		The VCM we're interested in reading the length from.
+ *
+ * The return value will be non-zero for a valid VCM. VCM regions
+ * cannot have 0 len.
+ */
+size_t vcm_get_len(struct vcm *vcm);
+
+
+/**
+ * vcm_free() - Free a VCM.
+ * @vcm:		The VCM we're interested in freeing.
+ *
+ * The return value is 0 if the VCM has been freed or:
+ * -EBUSY		The VCM region contains reservations or has been
+ *			associated (active or not) and cannot be freed.
+ * -EINVAL		The vcm argument is invalid.
+ */
+int vcm_free(struct vcm *vcm);
+
+
+/*
+ * Creating, freeing and managing reservations out of a VCM.
+ *
+ */
+
+/**
+ * vcm_reserve() - Create a reservation from a VCM region.
+ * @vcm:		The VCM region to reserve from.
+ * @len:		The length of the reservation. Must be at least
+ *			vcm_get_min_page_size() bytes.
+ * @attr:		See 'Reservation Attributes'.
+ *
+ * A reservation, res_t, is a contiguous range from a VCM region.
+ *
+ * The return value is non-zero if a reservation has been successfully
+ * created. It is 0 if any of the parameters are invalid.
+ */
+struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr);
+
+
+/**
+ * vcm_reserve_at() - Make a reservation at a given logical location.
+ * @memtarget:		A logical location to start the reservation from.
+ * @vcm:		The VCM region to start the reservation from.
+ * @len:		The length of the reservation.
+ * @attr:		See 'Reservation Attributes'.
+ *
+ * The return value is non-zero if a reservation has been successfully
+ * created.
+ */
+struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm *vcm,
+			   size_t len, u32 attr);
+
+
+/**
+ * vcm_get_vcm_from_res() - Return the VCM region of a reservation.
+ * @res:		The reservation to return the VCM region of.
+ *
+ * Te return value will be non-zero if the reservation is valid. A valid
+ * reservation is always associated with a VCM region; there is no such
+ * thing as an orphan reservation.
+ */
+struct vcm *vcm_get_vcm_from_res(struct res *res);
+
+
+/**
+ * vcm_unreserve() - Unreserve the reservation.
+ * @res:		The reservation to unreserve.
+ *
+ * The return value will be 0 if the reservation was successfully
+ * unreserved and:
+ * -EBUSY		The reservation is still backed,
+ * -EINVAL		The vcm argument is invalid.
+ */
+int vcm_unreserve(struct res *res);
+
+
+/**
+ * vcm_set_res_attr() - Set attributes of an existing reservation.
+ * @res:		An existing reservation of interest.
+ * @attr:		See 'Reservation Attributes'.
+ *
+ * This function can only be used on an existing reservation; there
+ * are no orphan reservations. All attributes can be set on a existing
+ * reservation.
+ *
+ * The return value will be 0 for a success, otherwise it will be:
+ * -EINVAL		res or attr are invalid.
+ */
+int vcm_set_res_attr(struct res *res, u32 attr);
+
+
+/**
+ * vcm_get_num_res() - Return the number of reservations in a VCM region.
+ * @vcm:		The VCM region of interest.
+ */
+size_t vcm_get_num_res(struct vcm *vcm);
+
+
+/**
+ * vcm_get_next_res() - Read each reservation one at a time.
+ * @vcm:		The VCM region of interest.
+ * @res:		Contains the last reservation. Pass NULL on the
+ *			first call.
+ *
+ * This function works like a foreach reservation in a VCM region.
+ *
+ * The return value will be non-zero for each reservation in a VCM. A
+ * zero indicates no further reservations.
+ */
+struct res *vcm_get_next_res(struct vcm *vcm, struct res *res);
+
+
+/**
+ * vcm_res_copy() - Copy len bytes from one reservation to another.
+ * @to:			The reservation to copy to.
+ * @from:		The reservation to copy from.
+ * @len:		The length of bytes to copy.
+ *
+ * The return value is the number of bytes copied.
+ */
+size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, size_t
+		    from_off, size_t len);
+
+
+/**
+ * vcm_get_min_page_size() - Return the minimum page size supported by
+ *			     the architecture.
+ */
+size_t vcm_get_min_page_size(void);
+
+
+/**
+ * vcm_back() - Physically back a reservation.
+ * @res:		The reservation containing the virtual contiguous
+ *			region to back.
+ * @physmem:		The physical memory that will back the virtual
+ *			contiguous memory region.
+ *
+ * One VCM can be associated with multiple devices. When you vcm_back()
+ * each association must be active. This is not strictly necessary. It may
+ * be changed in the future.
+ *
+ * This function returns 0 on a successful physical backing. Otherwise
+ * it returns:
+ * -EINVAL		res or physmem is invalid or res's len
+ *			is different from physmem's len.
+ * -EAGAIN		Try again, one of the devices hasn't been activated.
+ */
+int vcm_back(struct res *res, struct physmem *physmem);
+
+
+/**
+ * vcm_unback() - Unback a reservation.
+ * @res:		The reservation to unback.
+ *
+ * One VCM can be associated with multiple devices. When you vcm_unback()
+ * each association must be active.
+ *
+ * This function returns 0 on a successful unbacking. Otherwise
+ * it returns:
+ * -EINVAL		res is invalid.
+ * -EAGAIN		Try again, one of the devices hasn't been activated.
+ */
+int vcm_unback(struct res *res);
+
+
+/**
+ * vcm_phys_alloc() - Allocate physical memory for the VCM region.
+ * @memtype:		The memory type to allocate.
+ * @len:		The length of the allocation.
+ * @attr:		See 'Physical Allocation Attributes'.
+ *
+ * This function will allocate chunks of memory according to the attr
+ * it is passed.
+ *
+ * The return value is non-zero if physical memory has been
+ * successfully allocated.
+ */
+struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, u32 attr);
+
+
+/**
+ * vcm_phys_free() - Free a physical allocation.
+ * @physmem:		The physical allocation to free.
+ *
+ * The return value is 0 if the physical allocation has been freed or:
+ * -EBUSY		Their are reservation mapping the physical memory.
+ * -EINVAL		The physmem argument is invalid.
+ */
+int vcm_phys_free(struct physmem *physmem);
+
+
+/**
+ * vcm_get_physmem_from_res() - Return a reservation's physmem
+ * @res:		An existing reservation of interest.
+ *
+ * The return value will be non-zero on success, otherwise it will be:
+ * -EINVAL		res is invalid
+ * -ENOMEM		res is unbacked
+ */
+struct physmem *vcm_get_physmem_from_res(struct res *res);
+
+
+/**
+ * vcm_get_memtype_of_physalloc() - Return the memtype of a reservation.
+ * @physmem:		The physical allocation of interest.
+ *
+ * This function returns the memtype of a reservation or VCM_INVALID
+ * if res is invalid.
+ */
+enum memtype_t vcm_get_memtype_of_physalloc(struct physmem *physmem);
+
+
+/*
+ * Associate a VCM with a device, activate that association and remove it.
+ *
+ */
+
+/**
+ * vcm_assoc() - Associate a VCM with a device.
+ * @vcm:		The VCM region of interest.
+ * @dev:		The device to associate the VCM with.
+ * @attr:		See 'Association Attributes'.
+ *
+ * This function returns non-zero if a association is made. It returns 0
+ * if any of its parameters are invalid or VCM_ATTR_VALID is not present.
+ */
+struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr);
+
+
+/**
+ * vcm_deassoc() - Deassociate a VCM from a device.
+ * @avcm:		The association we want to break.
+ *
+ * The function returns 0 on success or:
+ * -EBUSY		The association is currently activated.
+ * -EINVAL		The avcm parameter is invalid.
+ */
+int vcm_deassoc(struct avcm *avcm);
+
+
+/**
+ * vcm_set_assoc_attr() - Set an AVCM's attributes.
+ * @avcm:		The AVCM of interest.
+ * @attr:		The new attr. See 'Association Attributes'.
+ *
+ * Every attribute can be set at runtime if an association isn't activated.
+ *
+ * This function returns 0 on success or:
+ * -EBUSY		The association is currently activated.
+ * -EINVAL		The avcm parameter is invalid.
+ */
+int vcm_set_assoc_attr(struct avcm *avcm, u32 attr);
+
+
+/**
+ * vcm_get_assoc_attr() - Return an AVCM's attributes.
+ * @avcm:		The AVCM of interest.
+ *
+ * This function returns 0 on error.
+ */
+u32 vcm_get_assoc_attr(struct avcm *avcm);
+
+
+/**
+ * vcm_activate() - Activate an AVCM.
+ * @avcm:		The AVCM to activate.
+ *
+ * You have to deactivate, before you activate.
+ *
+ * This function returns 0 on success or:
+ * -EINVAL		avcm is invalid
+ * -ENODEV		no device
+ * -EBUSY		device is already active
+ * -1			hardware failure
+ */
+int vcm_activate(struct avcm *avcm);
+
+
+/**
+ * vcm_deactivate() - Deactivate an association.
+ * @avcm:		The AVCM to deactivate.
+ *
+ * This function returns 0 on success or:
+ * -ENOENT		avcm is not activate
+ * -EINVAL		avcm is invalid
+ * -1			hardware failure
+ */
+int vcm_deactivate(struct avcm *avcm);
+
+
+/**
+ * vcm_is_active() - Query if an AVCM is active.
+ * @avcm:		The AVCM of interest.
+ *
+ * returns 0 for not active, 1 for active or -EINVAL for error.
+ *
+ */
+int vcm_is_active(struct avcm *avcm);
+
+
+/*
+ * Create, manage and remove a boundary in a VCM.
+ */
+
+/**
+ * vcm_create_bound() - Create a bound in a VCM.
+ * @vcm:		The VCM that needs a bound.
+ * @len:		The len of the bound.
+ *
+ * The allocator picks the virtual addresses of the bound.
+ *
+ * This function returns non-zero if a bound was created.
+ */
+struct bound *vcm_create_bound(struct vcm *vcm, size_t len);
+
+
+/**
+ * vcm_free_bound() - Free a bound.
+ * @bound:		The bound to remove.
+ *
+ * This function returns 0 if bound has been removed or:
+ * -EBUSY		The bound contains reservations and cannot be removed.
+ * -EINVAL		The bound is invalid.
+ */
+int vcm_free_bound(struct bound *bound);
+
+
+/**
+ * vcm_reserve_from_bound() - Make a reservation from a bounded area.
+ * @bound:		The bound to reserve from.
+ * @len:		The len of the reservation.
+ * @attr:		See 'Reservation Attributes'.
+ *
+ * The return value is non-zero on success. It is 0 if any parameter
+ * is invalid.
+ */
+struct res *vcm_reserve_from_bound(struct bound *bound, size_t len,
+				   u32 attr);
+
+
+/**
+ * vcm_get_bound_start_addr() - Return the starting device address of the bound
+ * @bound:		The bound of interest.
+ *
+ * On success this function returns the starting addres of the bound. On error
+ * it returns:
+ * 1			bound_id is invalid.
+ */
+size_t vcm_get_bound_start_addr(struct bound *bound);
+
+
+
+/*
+ * Perform low-level control over VCM regions and reservations.
+ */
+
+/**
+ * vcm_map_phys_addr() - Produce a physmem from a contiguous
+ *                       physical address
+ *
+ * @phys:		The physical address of the contiguous range.
+ * @len:		The len of the contiguous address range.
+ *
+ * Returns non-zero on success, 0 on failure.
+ */
+struct physmem *vcm_map_phys_addr(phys_addr_t phys, size_t len);
+
+
+/**
+ * vcm_get_next_phys_addr() - Get the next physical addr and len of a physmem.
+ * @physmem:		The physmem of interest.
+ * @phys:		The current physical address. Set this to NULL to
+ *			start the iteration.
+ * @len			An output: the len of the next physical segment.
+ *
+ * physmems may contain physically discontiguous sections. This
+ * function returns the next physical address and len. Pass NULL to
+ * phys to get the first physical address. The len of the physical
+ * segment is returned in *len.
+ *
+ * Returns 0 if there is no next physical address.
+ */
+size_t vcm_get_next_phys_addr(struct physmem *physmem, phys_addr_t phys,
+			      size_t *len);
+
+
+/**
+ * vcm_get_dev_addr() - Return the device address of a reservation.
+ * @res:		The reservation of interest.
+ *
+ *
+ * On success this function returns the device address of a reservation. On
+ * error it returns:
+ * 1			res is invalid.
+ *
+ * Note: This may return a kernel address if the reservation was
+ * created from vcm_create_from_prebuilt() and the prebuilt ext_vcm_id
+ * references a VM page table.
+ */
+phys_addr_t vcm_get_dev_addr(struct res *res);
+
+
+/**
+ * vcm_get_res() - Return the reservation from a device address and a VCM
+ * @dev_addr:		The device address of interest.
+ * @vcm:		The VCM that contains the reservation
+ *
+ * This function returns 0 if there is no reservation whose device
+ * address is dev_addr.
+ */
+struct res *vcm_get_res(unsigned long dev_addr, struct vcm *vcm);
+
+
+/**
+ * vcm_translate() - Translate from one device address to another.
+ * @src_dev:		The source device address.
+ * @src_vcm:		The source VCM region.
+ * @dst_vcm:		The destination VCM region.
+ *
+ * Derive the device address from a VCM region that maps the same physical
+ * memory as a device address from another VCM region.
+ *
+ * On success this function returns the device address of a translation. On
+ * error it returns:
+ * 1			res_id is invalid.
+ */
+size_t vcm_translate(struct device *src_dev, struct vcm *src_vcm,
+		     struct vcm *dst_vcm);
+
+
+/**
+ * vcm_get_phys_num_res() - Return the number of reservations mapping a
+ *			    physical address.
+ * @phys:		The physical address to read.
+ */
+size_t vcm_get_phys_num_res(phys_addr_t phys);
+
+
+/**
+ * vcm_get_next_phys_res() - Return the next reservation mapped to a physical
+ *			     address.
+ * @phys:		The physical address to map.
+ * @res:		The starting reservation. Set this to NULL for the first
+ *			reservation.
+ * @len:		The virtual length of the reservation
+ *
+ * This function returns 0 for the last reservation or no reservation.
+ */
+struct res *vcm_get_next_phys_res(phys_addr_t phys, struct res *res,
+				  size_t *len);
+
+
+/**
+ * vcm_get_pgtbl_pa() - Return the physcial address of a VCM's page table.
+ * @vcm:	The VCM region of interest.
+ *
+ * This function returns non-zero on success.
+ */
+phys_addr_t vcm_get_pgtbl_pa(struct vcm *vcm);
+
+
+/**
+ * vcm_get_cont_memtype_pa() - Return the phys base addr of a memtype's
+ *			       first contiguous region.
+ * @memtype:		The memtype of interest.
+ *
+ * This function returns non-zero on success. A zero return indicates that
+ * the given memtype does not have a contiguous region or that the memtype
+ * is invalid.
+ */
+phys_addr_t vcm_get_cont_memtype_pa(enum memtype_t memtype);
+
+
+/**
+ * vcm_get_cont_memtype_len() - Return the len of a memtype's
+ *				first contiguous region.
+ * @memtype:		The memtype of interest.
+ *
+ * This function returns non-zero on success. A zero return indicates that
+ * the given memtype does not have a contiguous region or that the memtype
+ * is invalid.
+ */
+size_t vcm_get_cont_memtype_len(enum memtype_t memtype);
+
+
+/**
+ * vcm_dev_addr_to_phys_addr() - Perform a device address page-table lookup.
+ * @vcm:		VCM to use for translation.
+ * @dev_addr:		The device address to map.
+ *
+ * This function returns the pa of a va from a device's page-table. It will
+ * fault if the dev_addr is not mapped.
+ */
+phys_addr_t vcm_dev_addr_to_phys_addr(struct vcm *vcm, unsigned long dev_addr);
+
+
+/*
+ * Fault Hooks
+ *
+ * vcm_hook()
+ */
+
+/**
+ * vcm_hook() - Add a fault handler.
+ * @dev:		The device.
+ * @handler:		The handler.
+ * @data:		A private piece of data that will get passed to the
+ *			handler.
+ *
+ * This function returns 0 for a successful registration or:
+ * -EINVAL		The arguments are invalid.
+ */
+int vcm_hook(struct device *dev, vcm_handler handler, void *data);
+
+
+
+/*
+ * Low level, platform agnostic, HW control.
+ *
+ * vcm_hw_ver()
+ */
+
+/**
+ * vcm_hw_ver() - Return the hardware version of a device, if it has one.
+ * @dev		The device.
+ */
+size_t vcm_hw_ver(size_t dev);
+
+#endif /* _VCM_H_ */
+
diff --git a/include/linux/vcm_alloc.h b/include/linux/vcm_alloc.h
new file mode 100644
index 0000000..f0e4ea4
--- /dev/null
+++ b/include/linux/vcm_alloc.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef VCM_ALLOC_H
+#define VCM_ALLOC_H
+
+#include <linux/list.h>
+#include <linux/vcm.h>
+#include <linux/vcm_types.h>
+
+#define MAX_NUM_PRIO_POOLS 8
+
+/* Data structure to inform VCM about the memory it manages */
+struct physmem_region {
+	size_t addr;
+	size_t size;
+	int chunk_size;
+};
+
+/* Mapping between memtypes and physmem_regions based on chunk size */
+struct vcm_memtype_map {
+	int pool_id[MAX_NUM_PRIO_POOLS];
+	int num_pools;
+};
+
+int vcm_alloc_pool_idx_to_size(int pool_idx);
+int vcm_alloc_idx_to_size(int idx);
+int vcm_alloc_get_mem_size(void);
+int vcm_alloc_blocks_avail(enum memtype_t memtype, int idx);
+int vcm_alloc_get_num_chunks(enum memtype_t memtype);
+int vcm_alloc_all_blocks_avail(enum memtarget_t memtype);
+int vcm_alloc_count_allocated(enum memtype_t memtype);
+void vcm_alloc_print_list(enum memtype_t memtype, int just_allocated);
+int vcm_alloc_idx_to_size(int idx);
+int vcm_alloc_destroy(void);
+int vcm_alloc_init(struct physmem_region *mem, int n_regions,
+		   struct vcm_memtype_map *mt_map, int n_mt);
+int vcm_alloc_free_blocks(enum memtype_t memtype,
+			  struct phys_chunk *alloc_head);
+int vcm_alloc_num_blocks(int num, enum memtype_t memtype,
+			 int idx, /* chunk size */
+			 struct phys_chunk *alloc_head);
+int vcm_alloc_max_munch(int len, enum memtype_t memtype,
+			struct phys_chunk *alloc_head);
+
+/* bring-up init, destroy */
+int vcm_sys_init(struct physmem_region *mem, int n_regions,
+		 struct vcm_memtype_map *mt_map, int n_mt,
+		 void *cont_pa, unsigned int cont_sz);
+
+int vcm_sys_destroy(void);
+
+#endif /* VCM_ALLOC_H */
diff --git a/include/linux/vcm_mm.h b/include/linux/vcm_mm.h
new file mode 100644
index 0000000..4cc5358
--- /dev/null
+++ b/include/linux/vcm_mm.h
@@ -0,0 +1,105 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* Architecture-specific VCM functions */
+
+/* Device attributes */
+
+/*
+ * Sharing attributes. Pick only one.
+ */
+#define VCM_DEV_ATTR_NON_SH 	(0x00)
+#define VCM_DEV_ATTR_SH		(0x04)
+
+/*
+ * Caching attributes. Pick only one.
+ */
+#define VCM_DEV_ATTR_NONCACHED		(0x00)
+#define VCM_DEV_ATTR_CACHED_WB_WA	(0x01)
+#define VCM_DEV_ATTR_CACHED_WB_NWA	(0x02)
+#define VCM_DEV_ATTR_CACHED_WT		(0x03)
+
+/*
+ * A "good" default set of attributes: shareable and non-cacheable.
+ */
+#define VCM_DEV_DEFAULT_ATTR	(VCM_DEV_ATTR_SH | VCM_DEV_ATTR_NONCACHED)
+
+/**
+ * set_arm7_pte_attr() - Set ARMv7 page table attributes
+ * pt_base	Virtual address of the first-level page table
+ * @va		Virtual address whose attributes are to be set
+ * @len		Page size used to map the given virtual address
+ * @attr	Attributes to set for this mapping.
+ *
+ * Modify a mapping attribute. The base address of the page table must
+ * be a virtual address containing a valid ARMv7 page table.  The
+ * virtual address must refer to an existing mapping and must be
+ * aligned to the length with which it was mapped. The mapping length
+ * must similarly be the same as was specified when the mapping was
+ * made (one of 4KB, 64KB, 1MB, or 16MB). The attribute must be one of
+ * the shareability attributes above ORed with one of the cacheability
+ * attributes. Any previous attributes are completely replaced by the
+ * most recent call to this function. This function only sets the
+ * cacheability and shareability attributes. This is accomplished by
+ * modifying the TEX class and the S bit in the PTE. It is an error to
+ * call this function without having called vcm_setup_tex_classes at
+ * least once.
+ *
+ * The return value is zero on success and non-zero on failure.
+ */
+int set_arm7_pte_attr(unsigned long pt_base, unsigned long va,
+		     unsigned long len,	unsigned int attr);
+
+
+/**
+ * cpu_set_attr() - Set page table attributes on the CPU's page tables
+ * @va		Virtual address whose attributes are to be set
+ * @len		Page size used to map the given virtual address
+ * @attr	Attributes to set for this mapping.
+ *
+ * Modify a mapping attribute within the ARM page tables. The va must
+ * refer to an existing mapping and must be aligned to the length with
+ * which it was mapped. The mapping length must similarly be the same
+ * as was specified when the mapping was made (one of 4KB, 64KB, 1MB,
+ * or 16MB). The attribute must be one of the shareability attributes
+ * above ORed with one of the cacheability attributes. Any previous
+ * attributes are completely replaced by the most recent call to this
+ * function. This function only sets the cacheability and shareability
+ * attributes. This is accomplished by modifying the TEX class and the
+ * S bit in the PTE. It is an error to call this function without
+ * having called vcm_setup_tex_classes at least once. It is an error
+ * to call this function on any system using a memory configuration
+ * that is anything OTHER than ARMv7 with TEX remap enabled. Only the
+ * HW page tables are modified; the Linux page tables are left
+ * untouched.
+ *
+ * The return value is zero on success and non-zero on failure.
+ */
+int cpu_set_attr(unsigned long va, unsigned long len, unsigned int attr);
+
+
+/**
+ * vcm_setup_tex_classes() - Prepare TEX class table for use
+ *
+ * Initialize the attribute mapping table by examining the TEX classes
+ * used by the CPU and finding the classes that match the device
+ * attributes (VCM_DEV_xx) defined above. This function is only
+ * relevant if TEX remap is enabled. The results will be unpredictable
+ * and irrelevant if TEX remap is not in use. It is an error to call
+ * this function in any system using a memory configuration of
+ * anything OTHER than ARMv7 with TEX remap enabled.
+ *
+ * The return value is zero on success or non-zero on failure. In the
+ * present version, a failure will result in a panic.
+ */
+int vcm_setup_tex_classes(void);
diff --git a/include/linux/vcm_types.h b/include/linux/vcm_types.h
new file mode 100644
index 0000000..7ec20a6
--- /dev/null
+++ b/include/linux/vcm_types.h
@@ -0,0 +1,355 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef VCM_TYPES_H
+#define VCM_TYPES_H
+
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/genalloc.h>
+#include <linux/list.h>
+
+/*
+ * Reservation Attributes
+ *
+ * Used in vcm_reserve(), vcm_reserve_at(), vcm_set_res_attr() and
+ * vcm_reserve_bound().
+ *
+ *	VCM_READ	Specifies that the reservation can be read.
+ *	VCM_WRITE	Specifies that the reservation can be written.
+ *	VCM_EXECUTE	Specifies that the reservation can be executed.
+ *	VCM_USER	Specifies that this reservation is used for
+ *			userspace access.
+ *	VCM_SUPERVISOR	Specifies that this reservation is used for
+ *				supervisor access.
+ *	VCM_SECURE	Specifies that the target of the reservation is
+ *			secure. The usage of this setting is TBD.
+ *
+ *	Caching behavior as a 4 bit field:
+ *		VCM_NOTCACHED		The VCM region is not cached.
+ *		VCM_INNER_WB_WA		The VCM region is inner cached
+ *					and is write-back and write-allocate.
+ *		VCM_INNER_WT_NWA	The VCM region is inner cached and is
+ *					write-through and no-write-allocate.
+ *		VCM_INNER_WB_NWA	The VCM region is inner cached and is
+ *					write-back and no-write-allocate.
+ *		VCM_OUTER_WB_WA		The VCM region is outer cached and is
+ *					write-back and write-allocate.
+ *		VCM_OUTER_WT_NWA	The VCM region is outer cached and is
+ *					write-through and no-write-allocate.
+ *		VCM_OUTER_WB_NWA	The VCM region is outer cached and is
+ *					write-back and no-write-allocate.
+ *		VCM_WB_WA		The VCM region is cached and is write
+ *					-back and write-allocate.
+ *		VCM_WT_NWA		The VCM region is cached and is write
+ *					-through and no-write-allocate.
+ *		VCM_WB_NWA		The VCM region is cached and is write
+ *					-back and no-write-allocate.
+ */
+
+/* Order of alignment (power of 2). Ie, 12 = 4k, 13 = 8k, 14 = 16k
+ * Alignments of less than 1MB on buffers of size 1MB or greater should be
+ * avoided. Alignments of less than 64KB on buffers of size 64KB or greater
+ * should be avoided. Strictly speaking, it will work, but will result in
+ * suboptimal performance, and a warning will be printed to that effect if
+ * VCM_PERF_WARN is enabled.
+ */
+#define VCM_ALIGN_SHIFT		10
+#define VCM_ALIGN_MASK		0x1F
+#define VCM_ALIGN_ATTR(order)	(((order) & VCM_ALIGN_MASK) << VCM_ALIGN_SHIFT)
+
+#define VCM_ALIGN_DEFAULT	0
+#define VCM_ALIGN_4K		(VCM_ALIGN_ATTR(12))
+#define VCM_ALIGN_8K		(VCM_ALIGN_ATTR(13))
+#define VCM_ALIGN_16K		(VCM_ALIGN_ATTR(14))
+#define VCM_ALIGN_32K		(VCM_ALIGN_ATTR(15))
+#define VCM_ALIGN_64K		(VCM_ALIGN_ATTR(16))
+#define VCM_ALIGN_128K		(VCM_ALIGN_ATTR(17))
+#define VCM_ALIGN_256K		(VCM_ALIGN_ATTR(18))
+#define VCM_ALIGN_512K		(VCM_ALIGN_ATTR(19))
+#define VCM_ALIGN_1M		(VCM_ALIGN_ATTR(20))
+#define VCM_ALIGN_2M		(VCM_ALIGN_ATTR(21))
+#define VCM_ALIGN_4M		(VCM_ALIGN_ATTR(22))
+#define VCM_ALIGN_8M		(VCM_ALIGN_ATTR(23))
+#define VCM_ALIGN_16M		(VCM_ALIGN_ATTR(24))
+#define VCM_ALIGN_32M		(VCM_ALIGN_ATTR(25))
+#define VCM_ALIGN_64M		(VCM_ALIGN_ATTR(26))
+#define VCM_ALIGN_128M		(VCM_ALIGN_ATTR(27))
+#define VCM_ALIGN_256M		(VCM_ALIGN_ATTR(28))
+#define VCM_ALIGN_512M		(VCM_ALIGN_ATTR(29))
+#define VCM_ALIGN_1GB		(VCM_ALIGN_ATTR(30))
+
+
+#define VCM_CACHE_POLICY	(0xF << 0)
+#define VCM_READ		(1UL << 9)
+#define VCM_WRITE		(1UL << 8)
+#define VCM_EXECUTE		(1UL << 7)
+#define VCM_USER		(1UL << 6)
+#define VCM_SUPERVISOR		(1UL << 5)
+#define VCM_SECURE		(1UL << 4)
+#define VCM_NOTCACHED		(0UL << 0)
+#define VCM_WB_WA		(1UL << 0)
+#define VCM_WB_NWA		(2UL << 0)
+#define VCM_WT			(3UL << 0)
+
+
+/*
+ * Physical Allocation Attributes
+ *
+ * Used in vcm_phys_alloc().
+ *
+ *	Alignment as a power of 2 starting at 4 KB. 5 bit field.
+ *	1 = 4KB, 2 = 8KB, etc.
+ *
+ *			Specifies that the reservation should have the
+ *			alignment specified.
+ *
+ *	VCM_4KB		Specifies that the reservation should use 4KB pages.
+ *	VCM_64KB	Specifies that the reservation should use 64KB pages.
+ *	VCM_1MB		specifies that the reservation should use 1MB pages.
+ *	VCM_ALL		Specifies that the reservation should use all
+ *			available page sizes.
+ *	VCM_PHYS_CONT	Specifies that a reservation should be backed with
+ *			physically contiguous memory.
+ *	VCM_COHERENT	Specifies that the reservation must be kept coherent
+ *			because it's shared.
+ */
+
+#define VCM_4KB			(1UL << 5)
+#define VCM_64KB		(1UL << 4)
+#define VCM_1MB			(1UL << 3)
+#define VCM_ALL			(1UL << 2)
+#define VCM_PAGE_SEL_MASK       (0xFUL << 2)
+#define VCM_PHYS_CONT		(1UL << 1)
+#define VCM_COHERENT		(1UL << 0)
+
+
+#define SHIFT_4KB               (12)
+
+#define ALIGN_REQ_BYTES(attr) (1UL << (((attr & VCM_ALIGNMENT_MASK) >> 6) + 12))
+/* set the alignment in pow 2, 0 = 4KB */
+#define SET_ALIGN_REQ_BYTES(attr, align) \
+	((attr & ~VCM_ALIGNMENT_MASK) | ((align << 6) & VCM_ALIGNMENT_MASK))
+
+/*
+ * Association Attributes
+ *
+ * Used in vcm_assoc(), vcm_set_assoc_attr().
+ *
+ *	VCM_USE_LOW_BASE	Use the low base register.
+ *	VCM_USE_HIGH_BASE	Use the high base register.
+ *
+ *	VCM_SPLIT		A 5 bit field that defines the
+ *				high/low split.  This value defines
+ *				the number of 0's left-filled into the
+ *				split register. Addresses that match
+ *				this will use VCM_USE_LOW_BASE
+ *				otherwise they'll use
+ *				VCM_USE_HIGH_BASE. An all 0's value
+ *				directs all translations to
+ *				VCM_USE_LOW_BASE.
+ */
+
+#define VCM_SPLIT		(1UL << 3)
+#define VCM_USE_LOW_BASE	(1UL << 2)
+#define VCM_USE_HIGH_BASE	(1UL << 1)
+
+
+/*
+ * External VCMs
+ *
+ * Used in vcm_create_from_prebuilt()
+ *
+ * Externally created VCM IDs for creating kernel and user space
+ * mappings to VCMs and kernel and user space buffers out of
+ * VCM_MEMTYPE_0,1,2, etc.
+ *
+ */
+#define VCM_PREBUILT_KERNEL		1
+#define VCM_PREBUILT_USER		2
+
+/**
+ * enum memtarget_t - A logical location in a VCM.
+ * @VCM_START:			Indicates the start of a VCM_REGION.
+ */
+enum memtarget_t {
+	VCM_START
+};
+
+
+/**
+ * enum memtype_t - A logical location in a VCM.
+ * @VCM_MEMTYPE_0:		Generic memory type 0
+ * @VCM_MEMTYPE_1:		Generic memory type 1
+ * @VCM_MEMTYPE_2:		Generic memory type 2
+ *
+ * A memtype encapsulates a platform specific memory arrangement. The
+ * memtype needn't refer to a single type of memory, it can refer to a
+ * set of memories that can back a reservation.
+ *
+ */
+enum memtype_t {
+	VCM_MEMTYPE_0 = 0,
+	VCM_MEMTYPE_1 = 1,
+	VCM_MEMTYPE_2 = 2,
+	VCM_MEMTYPE_3 = 3,
+	VCM_INVALID = 4,
+};
+
+/**
+ * vcm_handler - The signature of the fault hook.
+ * @dev:			The device id of the faulting device.
+ * @data:			The generic data pointer.
+ * @fault_data:			System specific common fault data.
+ *
+ * The handler should return 0 for success. This indicates that the
+ * fault was handled. A non-zero return value is an error and will be
+ * propagated up the stack.
+ */
+typedef int (*vcm_handler)(struct device *dev, void *data, void *fault_data);
+
+
+/**
+ * enum vcm_type - The type of VCM.
+ * @VCM_DEVICE:			VCM used for device mappings
+ * @VCM_EXT_KERNEL:		VCM used for kernel-side mappings
+ * @VCM_EXT_USER:		VCM used for userspace mappings
+ * @VCM_ONE_TO_ONE:		VCM used for devices without SMMUs
+ *
+ */
+enum vcm_type {
+	VCM_DEVICE,
+	VCM_EXT_KERNEL,
+	VCM_EXT_USER,
+	VCM_ONE_TO_ONE,
+};
+
+
+/**
+ * struct vcm - A Virtually Contiguous Memory region.
+ * @start_addr:		The starting address of the VCM region.
+ * @len:		The len of the VCM region. This must be at least
+ *			vcm_min() bytes.
+ */
+struct vcm {
+	/* public */
+	unsigned long start_addr;
+	size_t len;
+
+	/* private */
+	enum vcm_type type;
+
+	struct device *dev; /* opaque device control */
+
+	struct iommu_domain *domain;
+
+	/* allocator dependent */
+	struct gen_pool *pool;
+
+	struct list_head res_head;
+
+	/* this will be a very short list */
+	struct list_head assoc_head;
+};
+
+/**
+ * struct avcm - A VCM to device association
+ * @vcm:		The VCM region of interest.
+ * @dev:		The device to associate the VCM with.
+ * @attr:		See 'Association Attributes'.
+ */
+struct avcm {
+	/* public */
+	struct vcm *vcm;
+	struct device *dev;
+	u32 attr;
+
+	/* private */
+	struct list_head assoc_elm;
+
+	int is_active; /* is this particular association active */
+};
+
+/**
+ * struct bound - A boundary to reserve from in a VCM region.
+ * @vcm:		The VCM that needs a bound.
+ * @len:		The len of the bound.
+ */
+struct bound {
+	struct vcm *vcm;
+	size_t len;
+};
+
+struct phys_chunk {
+	struct list_head list;
+	struct list_head allocated; /* used to record is allocated */
+
+	struct list_head refers_to;
+	phys_addr_t pa;
+	int pool_idx;
+	int size;
+};
+
+/**
+ * struct physmem - A physical memory allocation.
+ * @memtype:		The memory type of the VCM region.
+ * @len:		The len of the physical memory allocation.
+ * @attr:		See 'Physical Allocation Attributes'.
+ */
+struct physmem {
+	/* public */
+	enum memtype_t memtype;
+	size_t len;
+	u32 attr;
+
+	/* private */
+	struct phys_chunk alloc_head;
+
+	/* if the physmem is cont then use the built in VCM */
+	int is_cont;
+	struct res *res;
+};
+
+
+/**
+ * struct res - A reservation in a VCM region.
+ * @vcm:		The VCM region to reserve from.
+ * @len:		The length of the reservation. Must be at least
+ *			vcm_min() bytes.
+ * @attr:		See 'Reservation Attributes'.
+ * @dev_addr:		The device-side address.
+ */
+struct res {
+	/* public */
+	struct vcm *vcm;
+	size_t len;
+	u32 attr;
+	unsigned long dev_addr;
+
+	/* private */
+	struct physmem *physmem;
+	/* allocator dependent */
+	size_t alignment_req;
+	size_t aligned_len;
+	unsigned long ptr;
+
+	struct list_head res_elm;
+
+	/* type VCM_EXT_KERNEL */
+	struct vm_struct *vm_area;
+	int mapped;
+};
+
+#endif /* VCM_TYPES_H */
diff --git a/include/linux/wait.h b/include/linux/wait.h
index 3efc9f3..42d9e34 100644
--- a/include/linux/wait.h
+++ b/include/linux/wait.h
@@ -346,6 +346,93 @@
 	__ret;								\
 })
 
+#define __wait_io_event_interruptible(wq, condition, ret)		\
+do {									\
+	DEFINE_WAIT(__wait);						\
+									\
+	for (;;) {							\
+		prepare_to_wait(&wq, &__wait, TASK_INTERRUPTIBLE);	\
+		if (condition)						\
+			break;						\
+		if (!signal_pending(current)) {				\
+			io_schedule();					\
+			continue;					\
+		}							\
+		ret = -ERESTARTSYS;					\
+		break;							\
+	}								\
+	finish_wait(&wq, &__wait);					\
+} while (0)
+
+/**
+ * wait_io_event_interruptible - sleep until an io condition gets true
+ * @wq: the waitqueue to wait on
+ * @condition: a C expression for the event to wait for
+ *
+ * The process is put to sleep (TASK_INTERRUPTIBLE) until the
+ * @condition evaluates to true or a signal is received.
+ * The @condition is checked each time the waitqueue @wq is woken up.
+ *
+ * wake_up() has to be called after changing any variable that could
+ * change the result of the wait condition.
+ *
+ * The function will return -ERESTARTSYS if it was interrupted by a
+ * signal and 0 if @condition evaluated to true.
+ */
+#define wait_io_event_interruptible(wq, condition)			\
+({									\
+	int __ret = 0;							\
+	if (!(condition))						\
+		__wait_io_event_interruptible(wq, condition, __ret);	\
+	__ret;								\
+})
+
+#define __wait_io_event_interruptible_timeout(wq, condition, ret)	\
+do {									\
+	DEFINE_WAIT(__wait);						\
+									\
+	for (;;) {							\
+		prepare_to_wait(&wq, &__wait, TASK_INTERRUPTIBLE);	\
+		if (condition)						\
+			break;						\
+		if (!signal_pending(current)) {				\
+			ret = io_schedule_timeout(ret);			\
+			if (!ret)					\
+				break;					\
+			continue;					\
+		}							\
+		ret = -ERESTARTSYS;					\
+		break;							\
+	}								\
+	finish_wait(&wq, &__wait);					\
+} while (0)
+
+/**
+ * wait_io_event_interruptible_timeout - sleep until an io condition gets true or a timeout elapses
+ * @wq: the waitqueue to wait on
+ * @condition: a C expression for the event to wait for
+ * @timeout: timeout, in jiffies
+ *
+ * The process is put to sleep (TASK_INTERRUPTIBLE) until the
+ * @condition evaluates to true or a signal is received.
+ * The @condition is checked each time the waitqueue @wq is woken up.
+ *
+ * wake_up() has to be called after changing any variable that could
+ * change the result of the wait condition.
+ *
+ * The function returns 0 if the @timeout elapsed, -ERESTARTSYS if it
+ * was interrupted by a signal, and the remaining jiffies otherwise
+ * if the condition evaluated to true before the timeout elapsed.
+ */
+
+#define wait_io_event_interruptible_timeout(wq, condition, timeout)	\
+({									\
+	long __ret = timeout;						\
+	if (!(condition))						\
+		__wait_io_event_interruptible_timeout(wq, condition, __ret); \
+	__ret;								\
+})
+
 #define __wait_event_interruptible_exclusive(wq, condition, ret)	\
 do {									\
 	DEFINE_WAIT(__wait);						\
diff --git a/include/linux/wcnss_wlan.h b/include/linux/wcnss_wlan.h
new file mode 100644
index 0000000..d1c2134
--- /dev/null
+++ b/include/linux/wcnss_wlan.h
@@ -0,0 +1,31 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _WCNSS_WLAN_H_
+#define _WCNSS_WLAN_H_
+
+#include <linux/device.h>
+
+#define WCNSS_WLAN_IRQ_INVALID -1
+
+struct device *wcnss_wlan_get_device(void);
+struct resource *wcnss_wlan_get_memory_map(struct device *dev);
+int wcnss_wlan_get_dxe_tx_irq(struct device *dev);
+int wcnss_wlan_get_dxe_rx_irq(struct device *dev);
+void wcnss_wlan_register_pm_ops(struct device *dev,
+				const struct dev_pm_ops *pm_ops);
+
+#define wcnss_wlan_get_drvdata(dev) dev_get_drvdata(dev)
+#define wcnss_wlan_set_drvdata(dev, data) dev_set_drvdata((dev), (data))
+
+#endif /* _WCNSS_WLAN_H_ */
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index f584aba..647d6b0 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -346,6 +346,8 @@
 
 extern void destroy_workqueue(struct workqueue_struct *wq);
 
+extern bool workqueue_empty(struct workqueue_struct *wq);
+
 extern int queue_work(struct workqueue_struct *wq, struct work_struct *work);
 extern int queue_work_on(int cpu, struct workqueue_struct *wq,
 			struct work_struct *work);
diff --git a/include/linux/wpce775x.h b/include/linux/wpce775x.h
new file mode 100644
index 0000000..1803122
--- /dev/null
+++ b/include/linux/wpce775x.h
@@ -0,0 +1,30 @@
+/* Quanta EC driver for the Winbond Embedded Controller
+ *
+ * Copyright (C) 2009 Quanta Computer Inc.
+ * 
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef WPCE775X_DRV_H
+#define WPCE775X_DRV_H
+
+#include <linux/i2c.h>
+
+struct i2c_client *wpce_get_i2c_client(void);
+int wpce_smbus_write_word_data(u8 command, u16 value);
+struct i2c_client *wpce_get_i2c_client(void);
+void wpce_poweroff(void);
+void wpce_restart(void);
+int wpce_i2c_transfer(struct i2c_msg *msg);
+int wpce_smbus_write_word_data(u8 command, u16 value);
+int wpce_smbus_write_byte_data(u8 command, u8 value);
+
+#endif