| commit | 4512a44b8966e316a6496e6df85a0c2e4ba2b9b2 | [log] [tgz] |
|---|---|---|
| author | Carl Vanderlip <carlv@codeaurora.org> | Wed Mar 20 17:02:23 2013 -0700 |
| committer | Carl Vanderlip <carlv@codeaurora.org> | Tue Apr 02 09:40:08 2013 -0700 |
| tree | d96999c1e78b542038c8c789fab1528da0747716 | |
| parent | 1753cdb91382b3cd149c1e1b595ab5c5f9d19e98 [diff] |
arm/dt: msm8974: Increase MDSS clock hysteresis cycles Increase the number of cycles the various MDSS clocks (VIG, RGB, DMA, ROT, DSPP, et al.) stay active for from 4 to 32 cycles. Change-Id: I291d2c60a01a2e0a5b8e5a5fb640fddc1ab141de Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>