msm: 9625: Add support for the external L2 controller
The 9625 chipset has an external L2 cache controller; add support for it
to the device tree and board config.
Change-Id: I900aa28ded4dc6968c5305f9b5a31aa44d2f9774
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
diff --git a/arch/arm/boot/dts/msm9625.dts b/arch/arm/boot/dts/msm9625.dts
index 6b44be9..deddc5f 100644
--- a/arch/arm/boot/dts/msm9625.dts
+++ b/arch/arm/boot/dts/msm9625.dts
@@ -26,6 +26,15 @@
<0xF9002000 0x1000>;
};
+ l2: cache-controller@f9040000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xf9040000 0x1000>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
msmgpio: gpio@fd510000 {
compatible = "qcom,msm-gpio";
interrupt-controller;
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a5d851e..2cf05d8 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -310,6 +310,7 @@
bool "MSM9625"
select ARM_GIC
select GIC_SECURE
+ select MIGHT_HAVE_CACHE_L2X0
select ARCH_MSM_CORTEX_A5
select SMP
select MSM_SMP
diff --git a/arch/arm/mach-msm/board-9625.c b/arch/arm/mach-msm/board-9625.c
index 60dfe3c..4a9bbcd 100644
--- a/arch/arm/mach-msm/board-9625.c
+++ b/arch/arm/mach-msm/board-9625.c
@@ -21,6 +21,7 @@
#include <linux/of_irq.h>
#include <linux/memory.h>
#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/arch_timer.h>
#include <asm/mach/arch.h>
@@ -30,6 +31,10 @@
#include <mach/gpio.h>
#include "clock.h"
+#define L2CC_AUX_CTRL ((0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \
+ (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
+ (0x1 << L2X0_AUX_CTRL_EVNT_MON_BUS_EN_SHIFT))
+
static struct clk_lookup msm_clocks_dummy[] = {
CLK_DUMMY("core_clk", BLSP1_UART_CLK, "msm_serial_hsl.0", OFF),
CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "msm_serial_hsl.0", OFF),
@@ -72,6 +77,7 @@
void __init msm9625_init_irq(void)
{
+ l2x0_of_init(L2CC_AUX_CTRL, L2X0_AUX_CTRL_MASK);
of_irq_init(irq_match);
}