[ARM] Add old Feroceon support to compressed/head.S
This patch supports the cache handling for some old Feroceon cores for
which the CPU ID is like 0x41159260. This is a complement to
commit ab6d15d50637fc25ee941710b23fed09ceb28db3.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 01d49be..4515728 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -674,6 +674,15 @@
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
+#ifdef CONFIG_CPU_FEROCEON_OLD_ID
+ /* this conflicts with the standard ARMv5TE entry */
+ .long 0x41009260 @ Old Feroceon
+ .long 0xff00fff0
+ b __armv4_mmu_cache_on
+ b __armv4_mmu_cache_off
+ b __armv5tej_mmu_cache_flush
+#endif
+
.word 0x66015261 @ FA526
.word 0xff01fff1
b __fa526_cache_on