arch/arm/boot/dts/msm8226-v2.dtsi

/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/*
 * As a general rule, only version-specific property overrides should be placed
 * inside this file. However, device definitions should be placed inside the
 * msm8226.dtsi file.
 */

/include/ "msm8226.dtsi"
/include/ "msm8226-v2-pm.dtsi"

/ {
	qcom,msm-id = <145 0x20000>,
		      <158 0x20000>,
		      <159 0x20000>,
		      <198 0x20000>,
		      <205 0x20000>,
		      <220 0x20000>,
		      <221 0x20000>,
		      <222 0x20000>,
		      <223 0x20000>;
};

&pm8226_l3 {
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1337500>;
};

&pm8226_l3_ao {
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1337500>;
};

&pm8226_l3_so {
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1337500>;
};

&pm8226_s2 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1330000>;
};

&apc_vreg_corner {
	qcom,pvs-init-voltage = <1330000 1330000 1330000 1320000 1310000
					1300000 1290000 1280000 1270000 1260000
					1250000 1240000 1230000 1220000 1210000
					1200000 1190000 1180000 1170000 1160000
					1150000 1140000 1140000 1140000 1140000
					1140000 1140000 1140000 1140000 1140000
					1140000 1140000>;
	qcom,pvs-corner-ceiling-slow = <1050000 1150000 1280000>;
	qcom,pvs-corner-ceiling-nom  = <1050000 1080000 1200000>;
	qcom,pvs-corner-ceiling-fast = <1050000 1050000 1100000>;
	qcom,cpr-step-quotient = <30>;
	qcom,cpr-up-threshold = <0>;
	qcom,cpr-down-threshold = <5>;
	qcom,cpr-apc-volt-step = <10000>;
};

&msm_gpu {
	/* Updated chip ID */
	qcom,chipid = <0x03000512>;
};

&soc {
	qcom,clock-a7@f9011050 {
		reg =	<0xf9011050 0x8>,
			<0xfc4b80b0 0x8>;
		reg-names = "rcg-base", "efuse";
		qcom,speed0-bin-v2 =
			<         0 0>,
			< 384000000 2>,
			< 787200000 4>,
			<1190400000 7>;
		qcom,speed2-bin-v2 =
			<         0 0>,
			< 384000000 2>,
			< 787200000 4>,
			<1401600000 10>;
		qcom,speed1-bin-v2 =
			<         0 0>,
			< 384000000 2>,
			< 787200000 4>,
			< 998400000 5>,
			<1094400000 6>,
			<1190400000 7>,
			<1305600000 8>,
			<1344000000 9>,
			<1401600000 10>,
			<1497600000 11>,
			<1593600000 12>;
		qcom,speed5-bin-v2 =
			<         0 0>,
			< 384000000 2>,
			< 787200000 4>,
			< 998400000 5>,
			<1094400000 6>,
			<1190400000 7>,
			<1305600000 8>,
			<1344000000 9>,
			<1401600000 10>,
			<1497600000 11>,
			<1593600000 12>,
			<1689600000 13>,
			<1785600000 14>;
	};
};

&tsens {
	qcom,sensors = <6>;
	qcom,slope = <2901 2846 3038 2955 2901 2846>;
};