msm: pil: Align max address calculation to 4K
Both iommus and XPUs require that the region mapped or protected
be 4K aligned. Not all images have memory sizes aligned to 4K so
fix the alignment for those images by rounding up the max address
to the next 4K boundary. This should force the region the image
resides in to be 4K aligned.
Change-Id: Ib6d089c8d8b0fb50a9e76d0d6a7b7eacc6765962
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/arch/arm/mach-msm/peripheral-loader.c b/arch/arm/mach-msm/peripheral-loader.c
index 88aae81..c903b72 100644
--- a/arch/arm/mach-msm/peripheral-loader.c
+++ b/arch/arm/mach-msm/peripheral-loader.c
@@ -313,7 +313,7 @@
struct ion_handle *region;
int ret;
unsigned int mask;
- size_t size = round_up(max_addr - min_addr, align);
+ size_t size = max_addr - min_addr;
if (!ion) {
WARN_ON_ONCE("No ION client, can't support relocation\n");
@@ -386,6 +386,13 @@
}
+ /*
+ * Align the max address to the next 4K boundary to satisfy iommus and
+ * XPUs that operate on 4K chunks.
+ */
+ max_addr_n = ALIGN(max_addr_n, SZ_4K);
+ max_addr_r = ALIGN(max_addr_r, SZ_4K);
+
if (relocatable) {
ret = pil_alloc_region(priv, min_addr_r, max_addr_r, align);
} else {