msm: acpuclock-krait: Support scaling CPU current requests
The current acpuclock-krait driver asserts a constant regulator
current request when a CPU is initialized or inserted, and
removes it when a CPU is hotplug-removed.
Improve on this by allowing the current requests to scale based
on the speed of the CPUs. This allows acpuclock drivers to
factor dynamic power into its current requests, which will
change based on the frequency.
Only msm8974 regulators support current requests, so the cur_ua
column is omitted from the other frequency tables. The 8974
table is populated with pessimistic placeholder currents for now,
until characterization data is available.
Change-Id: I1ef89406a0de0038d32039c361b755a5eedba847
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index d46d268..f9bdc14 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -43,7 +43,7 @@
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -53,7 +53,7 @@
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -63,7 +63,7 @@
.aux_clk_sel_phys = 0x020A8014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x6501,
- .vreg[VREG_CORE] = { "krait2", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait2", 1300000 },
.vreg[VREG_MEM] = { "krait2_mem", 1150000 },
.vreg[VREG_DIG] = { "krait2_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
@@ -73,7 +73,7 @@
.aux_clk_sel_phys = 0x020B8014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x7501,
- .vreg[VREG_CORE] = { "krait3", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait3", 1300000 },
.vreg[VREG_MEM] = { "krait3_mem", 1150000 },
.vreg[VREG_DIG] = { "krait3_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
diff --git a/arch/arm/mach-msm/acpuclock-8627.c b/arch/arm/mach-msm/acpuclock-8627.c
index 8060803..b10359d 100644
--- a/arch/arm/mach-msm/acpuclock-8627.c
+++ b/arch/arm/mach-msm/acpuclock-8627.c
@@ -49,7 +49,7 @@
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -59,7 +59,7 @@
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
index d04ce03..c5d8145 100644
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ b/arch/arm/mach-msm/acpuclock-8930.c
@@ -49,7 +49,7 @@
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -59,7 +59,7 @@
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
diff --git a/arch/arm/mach-msm/acpuclock-8930aa.c b/arch/arm/mach-msm/acpuclock-8930aa.c
index 0a37c29..157a08a 100644
--- a/arch/arm/mach-msm/acpuclock-8930aa.c
+++ b/arch/arm/mach-msm/acpuclock-8930aa.c
@@ -49,7 +49,7 @@
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -59,7 +59,7 @@
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000, 1740000 },
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index 8623c2b..9c2e169 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -43,7 +43,7 @@
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000, 3200000 },
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
@@ -54,7 +54,7 @@
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000, 3200000 },
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 9ed038b..53c4b08 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -46,7 +46,7 @@
[CPU0] = {
.hfpll_phys_base = 0xF908A000,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1050000, 3200000 },
+ .vreg[VREG_CORE] = { "krait0", 1050000 },
.vreg[VREG_MEM] = { "krait0_mem", 1050000 },
.vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll_a", 2150000 },
@@ -55,7 +55,7 @@
[CPU1] = {
.hfpll_phys_base = 0xF909A000,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1050000, 3200000 },
+ .vreg[VREG_CORE] = { "krait1", 1050000 },
.vreg[VREG_MEM] = { "krait1_mem", 1050000 },
.vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll_a", 2150000 },
@@ -64,7 +64,7 @@
[CPU2] = {
.hfpll_phys_base = 0xF90AA000,
.l2cpmr_iaddr = 0x6501,
- .vreg[VREG_CORE] = { "krait2", 1050000, 3200000 },
+ .vreg[VREG_CORE] = { "krait2", 1050000 },
.vreg[VREG_MEM] = { "krait2_mem", 1050000 },
.vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll_a", 2150000 },
@@ -73,7 +73,7 @@
[CPU3] = {
.hfpll_phys_base = 0xF90BA000,
.l2cpmr_iaddr = 0x7501,
- .vreg[VREG_CORE] = { "krait3", 1050000, 3200000 },
+ .vreg[VREG_CORE] = { "krait3", 1050000 },
.vreg[VREG_MEM] = { "krait3_mem", 1050000 },
.vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll_a", 2150000 },
@@ -118,18 +118,18 @@
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 0, {STBY_KHZ, QSB, 0, 0, 0 }, L2(0), 1050000 },
- { 1, { 300000, PLL_0, 0, 2, 0 }, L2(1), 1050000 },
- { 1, { 384000, HFPLL, 2, 0, 40 }, L2(2), 1050000 },
- { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 1050000 },
- { 1, { 537600, HFPLL, 1, 0, 28 }, L2(4), 1050000 },
- { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 1050000 },
- { 1, { 652800, HFPLL, 1, 0, 34 }, L2(6), 1050000 },
- { 1, { 729600, HFPLL, 1, 0, 38 }, L2(7), 1050000 },
- { 1, { 806400, HFPLL, 1, 0, 42 }, L2(8), 1050000 },
- { 1, { 883200, HFPLL, 1, 0, 46 }, L2(9), 1050000 },
- { 1, { 960000, HFPLL, 1, 0, 50 }, L2(10), 1050000 },
- { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(11), 1050000 },
+ { 0, {STBY_KHZ, QSB, 0, 0, 0 }, L2(0), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 2, 0 }, L2(1), 1050000, 3200000 },
+ { 1, { 384000, HFPLL, 2, 0, 40 }, L2(2), 1050000, 3200000 },
+ { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 1050000, 3200000 },
+ { 1, { 537600, HFPLL, 1, 0, 28 }, L2(4), 1050000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 1050000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 0, 34 }, L2(6), 1050000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 0, 38 }, L2(7), 1050000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 0, 42 }, L2(8), 1050000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 0, 46 }, L2(9), 1050000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 0, 50 }, L2(10), 1050000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(11), 1050000, 3200000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 01f6c33..d6f98b0 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -234,40 +234,59 @@
sc->cur_speed = tgt_s;
}
+struct vdd_data {
+ int vdd_mem;
+ int vdd_dig;
+ int vdd_core;
+ int ua_core;
+};
+
/* Apply any per-cpu voltage increases. */
-static int increase_vdd(int cpu, int vdd_core, int vdd_mem, int vdd_dig,
+static int increase_vdd(int cpu, struct vdd_data *data,
enum setrate_reason reason)
{
struct scalable *sc = &drv.scalable[cpu];
- int rc = 0;
+ int rc;
/*
* Increase vdd_mem active-set before vdd_dig.
* vdd_mem should be >= vdd_dig.
*/
- if (vdd_mem > sc->vreg[VREG_MEM].cur_vdd) {
+ if (data->vdd_mem > sc->vreg[VREG_MEM].cur_vdd) {
rc = rpm_regulator_set_voltage(sc->vreg[VREG_MEM].rpm_reg,
- vdd_mem, sc->vreg[VREG_MEM].max_vdd);
+ data->vdd_mem, sc->vreg[VREG_MEM].max_vdd);
if (rc) {
dev_err(drv.dev,
"vdd_mem (cpu%d) increase failed (%d)\n",
cpu, rc);
return rc;
}
- sc->vreg[VREG_MEM].cur_vdd = vdd_mem;
+ sc->vreg[VREG_MEM].cur_vdd = data->vdd_mem;
}
/* Increase vdd_dig active-set vote. */
- if (vdd_dig > sc->vreg[VREG_DIG].cur_vdd) {
+ if (data->vdd_dig > sc->vreg[VREG_DIG].cur_vdd) {
rc = rpm_regulator_set_voltage(sc->vreg[VREG_DIG].rpm_reg,
- vdd_dig, sc->vreg[VREG_DIG].max_vdd);
+ data->vdd_dig, sc->vreg[VREG_DIG].max_vdd);
if (rc) {
dev_err(drv.dev,
"vdd_dig (cpu%d) increase failed (%d)\n",
cpu, rc);
return rc;
}
- sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
+ sc->vreg[VREG_DIG].cur_vdd = data->vdd_dig;
+ }
+
+ /* Increase current request. */
+ if (data->ua_core > sc->vreg[VREG_CORE].cur_ua) {
+ rc = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
+ data->ua_core);
+ if (rc < 0) {
+ dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
+ sc->vreg[VREG_CORE].name, rc);
+ return rc;
+ }
+ sc->vreg[VREG_CORE].cur_ua = data->ua_core;
}
/*
@@ -276,25 +295,25 @@
* because we don't know what CPU we are running on at this point, but
* the CPU regulator API requires we call it from the affected CPU.
*/
- if (vdd_core > sc->vreg[VREG_CORE].cur_vdd
+ if (data->vdd_core > sc->vreg[VREG_CORE].cur_vdd
&& reason != SETRATE_HOTPLUG) {
- rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
- sc->vreg[VREG_CORE].max_vdd);
+ rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg,
+ data->vdd_core, sc->vreg[VREG_CORE].max_vdd);
if (rc) {
dev_err(drv.dev,
"vdd_core (cpu%d) increase failed (%d)\n",
cpu, rc);
return rc;
}
- sc->vreg[VREG_CORE].cur_vdd = vdd_core;
+ sc->vreg[VREG_CORE].cur_vdd = data->vdd_core;
}
- return rc;
+ return 0;
}
/* Apply any per-cpu voltage decreases. */
-static void decrease_vdd(int cpu, int vdd_core, int vdd_mem, int vdd_dig,
- enum setrate_reason reason)
+static void decrease_vdd(int cpu, struct vdd_data *data,
+ enum setrate_reason reason)
{
struct scalable *sc = &drv.scalable[cpu];
int ret;
@@ -304,46 +323,58 @@
* that's being affected. Don't do this in the hotplug remove path,
* where the rail is off and we're executing on the other CPU.
*/
- if (vdd_core < sc->vreg[VREG_CORE].cur_vdd
+ if (data->vdd_core < sc->vreg[VREG_CORE].cur_vdd
&& reason != SETRATE_HOTPLUG) {
- ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
- sc->vreg[VREG_CORE].max_vdd);
+ ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg,
+ data->vdd_core, sc->vreg[VREG_CORE].max_vdd);
if (ret) {
dev_err(drv.dev,
"vdd_core (cpu%d) decrease failed (%d)\n",
cpu, ret);
return;
}
- sc->vreg[VREG_CORE].cur_vdd = vdd_core;
+ sc->vreg[VREG_CORE].cur_vdd = data->vdd_core;
+ }
+
+ /* Decrease current request. */
+ if (data->ua_core < sc->vreg[VREG_CORE].cur_ua) {
+ ret = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
+ data->ua_core);
+ if (ret < 0) {
+ dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
+ sc->vreg[VREG_CORE].name, ret);
+ return;
+ }
+ sc->vreg[VREG_CORE].cur_ua = data->ua_core;
}
/* Decrease vdd_dig active-set vote. */
- if (vdd_dig < sc->vreg[VREG_DIG].cur_vdd) {
+ if (data->vdd_dig < sc->vreg[VREG_DIG].cur_vdd) {
ret = rpm_regulator_set_voltage(sc->vreg[VREG_DIG].rpm_reg,
- vdd_dig, sc->vreg[VREG_DIG].max_vdd);
+ data->vdd_dig, sc->vreg[VREG_DIG].max_vdd);
if (ret) {
dev_err(drv.dev,
"vdd_dig (cpu%d) decrease failed (%d)\n",
cpu, ret);
return;
}
- sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
+ sc->vreg[VREG_DIG].cur_vdd = data->vdd_dig;
}
/*
* Decrease vdd_mem active-set after vdd_dig.
* vdd_mem should be >= vdd_dig.
*/
- if (vdd_mem < sc->vreg[VREG_MEM].cur_vdd) {
+ if (data->vdd_mem < sc->vreg[VREG_MEM].cur_vdd) {
ret = rpm_regulator_set_voltage(sc->vreg[VREG_MEM].rpm_reg,
- vdd_mem, sc->vreg[VREG_MEM].max_vdd);
+ data->vdd_mem, sc->vreg[VREG_MEM].max_vdd);
if (ret) {
dev_err(drv.dev,
"vdd_mem (cpu%d) decrease failed (%d)\n",
cpu, ret);
return;
}
- sc->vreg[VREG_MEM].cur_vdd = vdd_mem;
+ sc->vreg[VREG_MEM].cur_vdd = data->vdd_mem;
}
}
@@ -380,7 +411,7 @@
const struct core_speed *strt_acpu_s, *tgt_acpu_s;
const struct acpu_level *tgt;
int tgt_l2_l;
- int vdd_mem, vdd_dig, vdd_core;
+ struct vdd_data vdd_data;
unsigned long flags;
int rc = 0;
@@ -409,13 +440,14 @@
}
/* Calculate voltage requirements for the current CPU. */
- vdd_mem = calculate_vdd_mem(tgt);
- vdd_dig = calculate_vdd_dig(tgt);
- vdd_core = calculate_vdd_core(tgt);
+ vdd_data.vdd_mem = calculate_vdd_mem(tgt);
+ vdd_data.vdd_dig = calculate_vdd_dig(tgt);
+ vdd_data.vdd_core = calculate_vdd_core(tgt);
+ vdd_data.ua_core = tgt->ua_core;
/* Increase VDD levels if needed. */
if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG) {
- rc = increase_vdd(cpu, vdd_core, vdd_mem, vdd_dig, reason);
+ rc = increase_vdd(cpu, &vdd_data, reason);
if (rc)
goto out;
}
@@ -446,7 +478,7 @@
set_bus_bw(drv.l2_freq_tbl[tgt_l2_l].bw_level);
/* Drop VDD levels if we can. */
- decrease_vdd(cpu, vdd_core, vdd_mem, vdd_dig, reason);
+ decrease_vdd(cpu, &vdd_data, reason);
pr_debug("ACPU%d speed change complete\n", cpu);
@@ -565,6 +597,14 @@
sc->vreg[VREG_CORE].name, ret);
goto err_core_get;
}
+ ret = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
+ acpu_level->ua_core);
+ if (ret < 0) {
+ dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
+ sc->vreg[VREG_CORE].name, ret);
+ goto err_core_conf;
+ }
+ sc->vreg[VREG_CORE].cur_ua = acpu_level->ua_core;
vdd_core = calculate_vdd_core(acpu_level);
ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
sc->vreg[VREG_CORE].max_vdd);
@@ -574,13 +614,6 @@
goto err_core_conf;
}
sc->vreg[VREG_CORE].cur_vdd = vdd_core;
- ret = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
- sc->vreg[VREG_CORE].peak_ua);
- if (ret < 0) {
- dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
- sc->vreg[VREG_CORE].name, ret);
- goto err_core_conf;
- }
ret = regulator_enable(sc->vreg[VREG_CORE].reg);
if (ret) {
dev_err(drv.dev, "regulator_enable(%s) failed (%d)\n",
@@ -828,7 +861,7 @@
if (WARN_ON(!prev_khz[cpu]))
return NOTIFY_BAD;
rc = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
- sc->vreg[VREG_CORE].peak_ua);
+ sc->vreg[VREG_CORE].cur_ua);
if (rc < 0)
return NOTIFY_BAD;
acpuclk_krait_set_rate(cpu, prev_khz[cpu], SETRATE_HOTPLUG);
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
index 830a0f6..d4c3aa5 100644
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ b/arch/arm/mach-msm/acpuclock-krait.h
@@ -96,15 +96,15 @@
* @reg: Regulator handle.
* @rpm_reg: RPM Regulator handle.
* @cur_vdd: Last-set voltage in uV.
- * @peak_ua: Maximum current draw expected in uA.
+ * @cur_ua: Last-set current in uA.
*/
struct vreg {
const char *name;
const int max_vdd;
- const int peak_ua;
struct regulator *reg;
struct rpm_regulator *rpm_reg;
int cur_vdd;
+ int cur_ua;
};
/**
@@ -143,12 +143,14 @@
* @speed: CPU clock configuration.
* @l2_level: L2 configuration to use.
* @vdd_core: CPU core voltage in uV.
+ * @ua_core: CPU core current consumption in uA.
*/
struct acpu_level {
const int use_for_scaling;
const struct core_speed speed;
const unsigned int l2_level;
int vdd_core;
+ int ua_core;
};
/**