Merge "msm_fb: display: Correct LVDS bitmap setting" into msm-3.4
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 21b6c0a..df5f748 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -3527,6 +3527,12 @@
static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = {
[VDD_DIG_LOW] = 192000000,
[VDD_DIG_NOMINAL] = 320000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
+static unsigned long fmax_gfx3d_8930aa[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 192000000,
+ [VDD_DIG_NOMINAL] = 320000000,
[VDD_DIG_HIGH] = 450000000
};
@@ -6481,12 +6487,15 @@
* Change the freq tables and voltage requirements for
* clocks which differ between 8960 and 8930.
*/
- if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
- gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
-
+ if (cpu_is_msm8930() || cpu_is_msm8627()) {
memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930,
sizeof(gfx3d_clk.c.fmax));
-
+ } else if (cpu_is_msm8930aa()) {
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930aa,
+ sizeof(gfx3d_clk.c.fmax));
+ }
+ if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
+ gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
pll15_clk.c.rate = 900000000;
gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
}
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index e203667..d73764f 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -819,7 +819,7 @@
msm_pm_power_collapse_standalone(false);
else if (allow[MSM_PM_SLEEP_MODE_RETENTION])
msm_pm_retention();
- else if (allow[MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT])
+ else
msm_pm_swfi();
}
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index 340faa2..851a9ad 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -329,6 +329,27 @@
wait_for_completion(&vctrl->dmap_comp);
}
+
+static void mdp4_dsi_video_wait4dmap_done(int cndx)
+{
+ unsigned long flags;
+ struct vsycn_ctrl *vctrl;
+
+ if (cndx >= MAX_CONTROLLER) {
+ pr_err("%s: out or range: cndx=%d\n", __func__, cndx);
+ return;
+ }
+ vctrl = &vsync_ctrl_db[cndx];
+
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ INIT_COMPLETION(vctrl->dmap_comp);
+ vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+ mdp4_dsi_video_wait4dmap(cndx);
+ vsync_irq_disable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
+}
+
+
static void mdp4_dsi_video_wait4ov(int cndx)
{
struct vsycn_ctrl *vctrl;
@@ -492,20 +513,13 @@
pipe = vctrl->base_pipe;
}
-#ifdef CONTINUOUS_SPLASH
- /* MDP cmd block enable */
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-
if (!(mfd->cont_splash_done)) {
mfd->cont_splash_done = 1;
- mdp_pipe_ctrl(MDP_CMD_BLOCK,
- MDP_BLOCK_POWER_OFF, FALSE);
- mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
- /* disable timing generator */
+ mdp4_dsi_video_wait4dmap_done(0);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mipi_dsi_controller_cfg(0);
}
-#endif
+
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;