Merge "net: usb: Add debug support to the driver" into msm-3.0
diff --git a/arch/arm/boot/dts/msmcopper.dtsi b/arch/arm/boot/dts/msmcopper.dtsi
index ca67181..284426a 100644
--- a/arch/arm/boot/dts/msmcopper.dtsi
+++ b/arch/arm/boot/dts/msmcopper.dtsi
@@ -72,7 +72,7 @@
reg = <0xf980b000 0x1000>;
interrupts = <0 123 0>;
- qcom,sdcc-clk-rates = <400000 24000000 48000000 96000000 192000000>;
+ qcom,sdcc-clk-rates = <400000 25000000 50000000 96000000 192000000>;
qcom,sdcc-sup-voltages = <3300 3300>;
qcom,sdcc-bus-width = <8>;
qcom,sdcc-hs200;
@@ -86,7 +86,7 @@
reg = <0xf984b000 0x1000>;
interrupts = <0 127 0>;
- qcom,sdcc-clk-rates = <400000 24000000 48000000>;
+ qcom,sdcc-clk-rates = <400000 25000000 50000000>;
qcom,sdcc-sup-voltages = <3300 3300>;
qcom,sdcc-bus-width = <4>;
qcom,sdcc-disable_cmd23;
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 1cf5df3..5b77374 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -229,7 +229,8 @@
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_MSM=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+CONFIG_SENSORS_MSM_ADC=y
CONFIG_MARIMBA_CORE=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index 8d31ee6..287e7fb 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -230,7 +230,8 @@
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_MSM=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+CONFIG_SENSORS_MSM_ADC=y
CONFIG_MARIMBA_CORE=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 9c6ebdf..a6bbaf4 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -319,12 +319,18 @@
CONFIG_MFD_PM8XXX_BATT_ALARM=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_USB_VIDEO_CLASS=y
-CONFIG_IMX074=y
+CONFIG_MSM_CAMERA_V4L2=y
CONFIG_WEBCAM_OV9726=y
CONFIG_MT9E013=y
+CONFIG_IMX074=y
+CONFIG_IMX074_ACT=y
+CONFIG_OV7692=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_ACTUATOR=y
CONFIG_MSM_GEMINI=y
CONFIG_RADIO_TAVARUA=y
CONFIG_ION=y
@@ -340,8 +346,10 @@
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_OVERLAY=y
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
+CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
+CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index aae900a..df49bdc 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -320,12 +320,18 @@
CONFIG_MFD_PM8XXX_BATT_ALARM=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_USB_VIDEO_CLASS=y
-CONFIG_IMX074=y
+CONFIG_MSM_CAMERA_V4L2=y
CONFIG_WEBCAM_OV9726=y
CONFIG_MT9E013=y
+CONFIG_IMX074=y
+CONFIG_IMX074_ACT=y
+CONFIG_OV7692=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_ACTUATOR=y
CONFIG_MSM_GEMINI=y
CONFIG_RADIO_TAVARUA=y
CONFIG_ION=y
@@ -341,8 +347,10 @@
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_OVERLAY=y
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
+CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
+CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm8960-perf_defconfig b/arch/arm/configs/msm8960-perf_defconfig
index dc2db27..b5a17cd 100644
--- a/arch/arm/configs/msm8960-perf_defconfig
+++ b/arch/arm/configs/msm8960-perf_defconfig
@@ -90,6 +90,7 @@
CONFIG_MSM_CACHE_ERP=y
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
CONFIG_MSM_DCVS=y
+CONFIG_MSM_HSIC_SYSMON=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index ba616b0..e18f0ea 100644
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -97,6 +97,7 @@
CONFIG_MSM_DCVS=y
CONFIG_MSM_CACHE_DUMP=y
CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
+CONFIG_MSM_HSIC_SYSMON=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index 3dfb62f..7a5b21a 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -141,7 +141,7 @@
unsigned int msmsdcc_fmax;
bool nonremovable;
bool pclk_src_dfab;
- int (*cfg_mpm_sdiowakeup)(struct device *, unsigned);
+ unsigned int mpm_sdiowakeup_int;
unsigned int wpswitch_gpio;
unsigned char wpswitch_polarity;
struct msm_mmc_slot_reg_data *vreg_data;
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 33c84a6..4ea24a4 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -2275,4 +2275,21 @@
want to dump the L1 and L2 caches on panic before any flush occurs.
If unsure, say N
+config MSM_HSIC_SYSMON
+ tristate "MSM HSIC system monitor driver"
+ depends on USB
+ help
+ Add support for bridging with the system monitor interface of MDM
+ over HSIC. This driver allows the local system monitor to
+ communicate with the remote system monitor interface.
+
+config MSM_HSIC_SYSMON_TEST
+ tristate "MSM HSIC system monitor bridge test"
+ depends on USB && MSM_HSIC_SYSMON && DEBUG_FS
+ help
+ Enable the test hook for the Qualcomm system monitor HSIC driver.
+ This will create a debugfs file entry named "hsic_sysmon_test" which
+ can be read and written to send character data to the sysmon port of
+ the modem over USB.
+
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index fec1b4f..f14f1ea 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -87,7 +87,7 @@
ifdef CONFIG_DEBUG_FS
obj-$(CONFIG_MSM_IPC_LOGGING) += ipc_logging_debug.o
endif
-obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o remote_spinlock.o
+obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o remote_spinlock.o smd_private.o
obj-y += socinfo.o
ifndef CONFIG_ARCH_MSM9615
ifndef CONFIG_ARCH_APQ8064
@@ -168,7 +168,7 @@
obj-$(CONFIG_ARCH_QSD8X50) += devices-qsd8x50.o clock-pcom-lookup.o
obj-$(CONFIG_MACH_QSD8X50_SURF) += board-qsd8x50.o
obj-$(CONFIG_MACH_QSD8X50_FFA) += board-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o
+obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o clock-pll.o
obj-$(CONFIG_ARCH_MSM8X60) += clock-rpm.o
obj-$(CONFIG_ARCH_MSM8X60) += saw-regulator.o
obj-$(CONFIG_ARCH_MSM8X60) += footswitch-8x60.o
@@ -240,10 +240,10 @@
obj-$(CONFIG_MACH_MSM8625_EVB) += board-qrd7627a.o board-7627a-all.o
obj-$(CONFIG_MACH_MSM8625_QRD7) += board-qrd7627a.o board-7627a-all.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
-obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
+obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o clock-pll.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
obj-$(CONFIG_MACH_MSM7X25_FFA) += board-msm7x27.o devices-msm7x25.o
-obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o
+obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o clock-pll.o
obj-$(CONFIG_ARCH_MSM8960) += footswitch-8x60.o
obj-$(CONFIG_ARCH_MSM8960) += acpuclock-8960.o
obj-$(CONFIG_ARCH_MSM8960) += memory_topology.o
@@ -270,8 +270,8 @@
obj-$(CONFIG_MACH_MPQ8064_HRD) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_MPQ8064_DTV) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o board-9615-gpiomux.o board-9615-storage.o board-9615-display.o
-obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o
-obj-$(CONFIG_ARCH_MSMCOPPER) += board-copper.o board-dt.o board-copper-regulator.o
+obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o clock-pll.o
+obj-$(CONFIG_ARCH_MSMCOPPER) += board-copper.o board-dt.o board-copper-regulator.o board-copper-gpiomux.o
obj-$(CONFIG_ARCH_MSMCOPPER) += acpuclock-krait.o acpuclock-copper.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
@@ -345,3 +345,6 @@
obj-$(CONFIG_MSM_RTB) += msm_rtb.o
obj-$(CONFIG_MSM_CACHE_ERP) += cache_erp.o
obj-$(CONFIG_MSM_CACHE_DUMP) += msm_cache_dump.o
+
+obj-$(CONFIG_MSM_HSIC_SYSMON) += hsic_sysmon.o
+obj-$(CONFIG_MSM_HSIC_SYSMON_TEST) += hsic_sysmon_test.o
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 66d2a57..eba5637 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -240,6 +240,7 @@
static int a2_pc_disabled_wakelock_skipped;
static int disconnect_ack;
static LIST_HEAD(bam_other_notify_funcs);
+static DEFINE_MUTEX(smsm_cb_lock);
struct outside_notify_func {
void (*notify)(void *, int, unsigned long);
@@ -1074,7 +1075,7 @@
fail:
pr_err("%s: reverting to polling\n", __func__);
- queue_work(bam_mux_rx_workqueue, &rx_timer_work);
+ queue_work_on(0, bam_mux_rx_workqueue, &rx_timer_work);
}
static void rx_timer_work_func(struct work_struct *work)
@@ -1179,7 +1180,11 @@
}
grab_wakelock();
polling_mode = 1;
- queue_work(bam_mux_rx_workqueue, &rx_timer_work);
+ /*
+ * run on core 0 so that netif_rx() in rmnet uses only
+ * one queue
+ */
+ queue_work_on(0, bam_mux_rx_workqueue, &rx_timer_work);
}
break;
default:
@@ -2112,10 +2117,20 @@
static void bam_dmux_smsm_cb(void *priv, uint32_t old_state, uint32_t new_state)
{
+ static int last_processed_state;
+
+ mutex_lock(&smsm_cb_lock);
bam_dmux_power_state = new_state & SMSM_A2_POWER_CONTROL ? 1 : 0;
DBG_INC_A2_POWER_CONTROL_IN_CNT();
bam_dmux_log("%s: 0x%08x -> 0x%08x\n", __func__, old_state,
new_state);
+ if (last_processed_state == (new_state & SMSM_A2_POWER_CONTROL)) {
+ bam_dmux_log("%s: already processed this state\n", __func__);
+ mutex_unlock(&smsm_cb_lock);
+ return;
+ }
+
+ last_processed_state = new_state & SMSM_A2_POWER_CONTROL;
if (bam_mux_initialized && new_state & SMSM_A2_POWER_CONTROL) {
bam_dmux_log("%s: reconnect\n", __func__);
@@ -2137,6 +2152,7 @@
bam_dmux_log("%s: bad state change\n", __func__);
pr_err("%s: unsupported state change\n", __func__);
}
+ mutex_unlock(&smsm_cb_lock);
}
@@ -2172,7 +2188,13 @@
if (rc)
pr_err("%s: unable to set dfab clock rate\n", __func__);
- bam_mux_rx_workqueue = create_singlethread_workqueue("bam_dmux_rx");
+ /*
+ * setup the workqueue so that it can be pinned to core 0 and not
+ * block the watchdog pet function, so that netif_rx() in rmnet
+ * only uses one queue.
+ */
+ bam_mux_rx_workqueue = alloc_workqueue("bam_dmux_rx",
+ WQ_MEM_RECLAIM | WQ_CPU_INTENSIVE, 1);
if (!bam_mux_rx_workqueue)
return -ENOMEM;
diff --git a/arch/arm/mach-msm/board-8064-gpiomux.c b/arch/arm/mach-msm/board-8064-gpiomux.c
index 8464752..de6e0d2 100644
--- a/arch/arm/mach-msm/board-8064-gpiomux.c
+++ b/arch/arm/mach-msm/board-8064-gpiomux.c
@@ -71,6 +71,265 @@
};
#endif
+#ifdef CONFIG_MSM_VCAP
+static struct gpiomux_setting gpio_vcap_config[] = {
+ {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_3,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_4,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_5,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_6,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_7,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_8,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_9,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+ {
+ .func = GPIOMUX_FUNC_A,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ },
+};
+
+struct msm_gpiomux_config vcap_configs[] = {
+ {
+ .gpio = 20,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[7],
+ }
+ },
+ {
+ .gpio = 25,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 24,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[1],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[1],
+ }
+ },
+ {
+ .gpio = 23,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 19,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[8],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[8],
+ }
+ },
+ {
+ .gpio = 22,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 21,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[7],
+ }
+ },
+ {
+ .gpio = 12,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[6],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[6],
+ }
+ },
+ {
+ .gpio = 18,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[9],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[9],
+ }
+ },
+ {
+ .gpio = 11,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[10],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[10],
+ }
+ },
+ {
+ .gpio = 10,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[9],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[9],
+ }
+ },
+ {
+ .gpio = 9,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 26,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[1],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[1],
+ }
+ },
+ {
+ .gpio = 8,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[3],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[3],
+ }
+ },
+ {
+ .gpio = 7,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[7],
+ }
+ },
+ {
+ .gpio = 6,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[7],
+ }
+ },
+ {
+ .gpio = 80,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 86,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[1],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[1],
+ }
+ },
+ {
+ .gpio = 85,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[4],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[4],
+ }
+ },
+ {
+ .gpio = 84,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[3],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[3],
+ }
+ },
+ {
+ .gpio = 5,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 4,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[3],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[3],
+ }
+ },
+ {
+ .gpio = 3,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[6],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[6],
+ }
+ },
+ {
+ .gpio = 2,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[5],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[5],
+ }
+ },
+ {
+ .gpio = 82,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[4],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[4],
+ }
+ },
+ {
+ .gpio = 83,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[4],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[4],
+ }
+ },
+ {
+ .gpio = 87,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[2],
+ }
+ },
+ {
+ .gpio = 13,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_vcap_config[6],
+ [GPIOMUX_ACTIVE] = &gpio_vcap_config[6],
+ }
+ },
+};
+#endif
+
static struct gpiomux_setting gpio_i2c_config = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
@@ -658,6 +917,10 @@
machine_is_mpq8064_dtv()) {
msm_gpiomux_install(mpq8064_gsbi5_i2c_configs,
ARRAY_SIZE(mpq8064_gsbi5_i2c_configs));
+#ifdef CONFIG_MSM_VCAP
+ msm_gpiomux_install(vcap_configs,
+ ARRAY_SIZE(vcap_configs));
+#endif
} else {
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
msm_gpiomux_install(apq8064_ethernet_configs,
diff --git a/arch/arm/mach-msm/board-8064-storage.c b/arch/arm/mach-msm/board-8064-storage.c
index cd8fba5..275c893 100644
--- a/arch/arm/mach-msm/board-8064-storage.c
+++ b/arch/arm/mach-msm/board-8064-storage.c
@@ -196,6 +196,9 @@
},
};
+#define MSM_MPM_PIN_SDC1_DAT1 17
+#define MSM_MPM_PIN_SDC3_DAT1 21
+
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
static unsigned int sdc1_sup_clk_rates[] = {
400000, 24000000, 48000000, 96000000
@@ -215,6 +218,7 @@
.pin_data = &mmc_slot_pin_data[SDCC1],
.vreg_data = &mmc_slot_vreg_data[SDCC1],
.uhs_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
};
static struct mmc_platform_data *apq8064_sdc1_pdata = &sdc1_data;
#else
@@ -244,6 +248,7 @@
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800),
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
};
static struct mmc_platform_data *apq8064_sdc3_pdata = &sdc3_data;
#else
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index fe85d81..59f42e5 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -933,22 +933,27 @@
static int isa1200_power(int on)
{
+ int rc = 0;
+
gpio_set_value_cansleep(ISA1200_HAP_CLK, !!on);
- return 0;
+ if (on)
+ rc = pm8xxx_aux_clk_control(CLK_MP3_2, XO_DIV_1, true);
+ else
+ rc = pm8xxx_aux_clk_control(CLK_MP3_2, XO_DIV_NONE, true);
+
+ if (rc) {
+ pr_err("%s: unable to write aux clock register(%d)\n",
+ __func__, rc);
+ }
+
+ return rc;
}
static int isa1200_dev_setup(bool enable)
{
int rc = 0;
- rc = pm8xxx_aux_clk_control(CLK_MP3_2, XO_DIV_1, enable);
- if (rc) {
- pr_err("%s: unable to write aux clock register(%d)\n",
- __func__, rc);
- return rc;
- }
-
if (!enable)
goto free_gpio;
@@ -1063,6 +1068,7 @@
0,
};
+#ifndef CONFIG_MSM_VCAP
#define MXT_TS_GPIO_IRQ 6
#define MXT_TS_PWR_EN_GPIO PM8921_GPIO_PM_TO_SYS(23)
#define MXT_TS_RESET_GPIO 33
@@ -1114,6 +1120,7 @@
.irq = MSM_GPIO_TO_INT(MXT_TS_GPIO_IRQ),
},
};
+#endif
#define CYTTSP_TS_GPIO_IRQ 6
#define CYTTSP_TS_GPIO_RESOUT 7
#define CYTTSP_TS_GPIO_SLEEP 33
@@ -1272,6 +1279,83 @@
.id = -1,
};
+#ifdef CONFIG_QSEECOM
+/* qseecom bus scaling */
+static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = 0,
+ .ab = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = 0,
+ .ab = 0,
+ },
+};
+
+static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = (492 * 8) * 1000000UL,
+ .ab = (492 * 8) * 100000UL,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = 0,
+ .ab = 0,
+ },
+};
+
+static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = 0,
+ .ab = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = (64 * 8) * 1000000UL,
+ .ab = (64 * 8) * 100000UL,
+ },
+};
+
+static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
+ {
+ ARRAY_SIZE(qseecom_clks_init_vectors),
+ qseecom_clks_init_vectors,
+ },
+ {
+ ARRAY_SIZE(qseecom_enable_dfab_vectors),
+ qseecom_enable_sfpb_vectors,
+ },
+ {
+ ARRAY_SIZE(qseecom_enable_sfpb_vectors),
+ qseecom_enable_sfpb_vectors,
+ },
+};
+
+static struct msm_bus_scale_pdata qseecom_bus_pdata = {
+ qseecom_hw_bus_scale_usecases,
+ ARRAY_SIZE(qseecom_hw_bus_scale_usecases),
+ .name = "qsee",
+};
+
+static struct platform_device qseecom_device = {
+ .name = "qseecom",
+ .id = 0,
+ .dev = {
+ .platform_data = &qseecom_bus_pdata,
+ },
+};
+#endif
+
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
@@ -1772,9 +1856,11 @@
static struct platform_device *common_devices[] __initdata = {
&apq8064_device_dmov,
+#ifndef CONFIG_MSM_VCAP
&apq8064_device_qup_i2c_gsbi1,
&apq8064_device_qup_i2c_gsbi3,
&apq8064_device_qup_i2c_gsbi4,
+#endif
&apq8064_device_qup_spi_gsbi5,
&apq8064_device_ext_5v_vreg,
&apq8064_device_ext_mpp8_vreg,
@@ -1804,6 +1890,10 @@
&msm8064_device_saw_regulator_core1,
&msm8064_device_saw_regulator_core2,
&msm8064_device_saw_regulator_core3,
+#if defined(CONFIG_QSEECOM)
+ &qseecom_device,
+#endif
+
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
&qcrypto_device,
@@ -1845,6 +1935,7 @@
&apq_cpudai_stub,
&apq_cpudai_slimbus_1_rx,
&apq_cpudai_slimbus_1_tx,
+ &apq_cpudai_slimbus_2_tx,
&apq8064_rpm_device,
&apq8064_rpm_log_device,
&apq8064_rpm_stat_device,
@@ -1871,6 +1962,8 @@
&msm_tpiu_device,
&msm_funnel_device,
&apq8064_etm_device,
+ &apq_cpudai_slim_4_rx,
+ &apq_cpudai_slim_4_tx,
};
static struct platform_device *sim_devices[] __initdata = {
@@ -1967,6 +2060,9 @@
&mpq8064_device_ext_2p2_buck_vreg,
&mpq8064_device_ext_5v_buck_vreg,
&mpq8064_device_ext_3p3v_ldo_vreg,
+#ifdef CONFIG_MSM_VCAP
+ &msm8064_device_vcap,
+#endif
};
static struct msm_spi_platform_data apq8064_qup_spi_gsbi5_pdata = {
@@ -2192,14 +2288,6 @@
platform_device_register(&msm_dsps_device_8064);
}
-static void __init apq8064_clock_init(void)
-{
- if (machine_is_apq8064_rumi3())
- msm_clock_init(&apq8064_dummy_clock_init_data);
- else
- msm_clock_init(&apq8064_clock_init_data);
-}
-
#define I2C_SURF 1
#define I2C_FFA (1 << 1)
#define I2C_RUMI (1 << 2)
@@ -2223,12 +2311,14 @@
smb349_charger_i2c_info,
ARRAY_SIZE(smb349_charger_i2c_info)
},
+#ifndef CONFIG_MSM_VCAP
{
I2C_SURF | I2C_LIQUID,
APQ_8064_GSBI3_QUP_I2C_BUS_ID,
mxt_device_info,
ARRAY_SIZE(mxt_device_info),
},
+#endif
{
I2C_FFA,
APQ_8064_GSBI3_QUP_I2C_BUS_ID,
@@ -2408,7 +2498,7 @@
platform_device_register(&apq8064_device_rpm_regulator);
if (msm_xo_init())
pr_err("Failed to initialize XO votes\n");
- apq8064_clock_init();
+ msm_clock_init(&apq8064_clock_init_data);
apq8064_init_gpiomux();
apq8064_i2c_init();
register_i2c_devices();
diff --git a/arch/arm/mach-msm/board-8930-camera.c b/arch/arm/mach-msm/board-8930-camera.c
index 12312ee..1a7e2e1 100644
--- a/arch/arm/mach-msm/board-8930-camera.c
+++ b/arch/arm/mach-msm/board-8930-camera.c
@@ -138,6 +138,13 @@
[GPIOMUX_SUSPENDED] = &cam_settings[0],
},
},
+ {
+ .gpio = 54,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &cam_settings[2],
+ [GPIOMUX_SUSPENDED] = &cam_settings[0],
+ },
+ },
};
static struct msm_gpiomux_config msm8930_cam_2d_configs[] = {
@@ -373,6 +380,7 @@
static struct gpio msm8930_back_cam_gpio[] = {
{107, GPIOF_DIR_OUT, "CAM_RESET"},
+ {54, GPIOF_DIR_OUT, "CAM_STBY_N"},
};
static struct msm_gpio_set_tbl msm8930_front_cam_gpio_set_tbl[] = {
@@ -381,6 +389,8 @@
};
static struct msm_gpio_set_tbl msm8930_back_cam_gpio_set_tbl[] = {
+ {54, GPIOF_OUT_INIT_LOW, 1000},
+ {54, GPIOF_OUT_INIT_HIGH, 4000},
{107, GPIOF_OUT_INIT_LOW, 1000},
{107, GPIOF_OUT_INIT_HIGH, 4000},
};
diff --git a/arch/arm/mach-msm/board-8930-regulator.c b/arch/arm/mach-msm/board-8930-regulator.c
index f760e7b..fc89a11 100644
--- a/arch/arm/mach-msm/board-8930-regulator.c
+++ b/arch/arm/mach-msm/board-8930-regulator.c
@@ -148,7 +148,6 @@
};
VREG_CONSUMERS(S1) = {
REGULATOR_SUPPLY("8038_s1", NULL),
- REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_otg"),
REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"),
};
VREG_CONSUMERS(S2) = {
@@ -192,6 +191,7 @@
};
VREG_CONSUMERS(VDD_DIG_CORNER) = {
REGULATOR_SUPPLY("vdd_dig_corner", NULL),
+ REGULATOR_SUPPLY("hsusb_vdd_dig", "msm_otg"),
};
#define PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, _modes, _ops, \
diff --git a/arch/arm/mach-msm/board-8930-storage.c b/arch/arm/mach-msm/board-8930-storage.c
index 83fb5fd..ecebfa9 100644
--- a/arch/arm/mach-msm/board-8930-storage.c
+++ b/arch/arm/mach-msm/board-8930-storage.c
@@ -207,13 +207,18 @@
},
};
+#define MSM_MPM_PIN_SDC1_DAT1 17
+#define MSM_MPM_PIN_SDC3_DAT1 21
+
static unsigned int sdc1_sup_clk_rates[] = {
400000, 24000000, 48000000,
};
+#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
static unsigned int sdc3_sup_clk_rates[] = {
400000, 24000000, 48000000, 96000000, 192000000,
};
+#endif
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
static struct mmc_platform_data msm8960_sdc1_data = {
@@ -228,7 +233,8 @@
.pclk_src_dfab = 1,
.nonremovable = 1,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
- .pin_data = &mmc_slot_pin_data[SDCC1]
+ .pin_data = &mmc_slot_pin_data[SDCC1],
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
};
#endif
@@ -266,6 +272,7 @@
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800),
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
};
#endif
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 173ec95..8bbb596 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -654,6 +654,83 @@
.dev = {.platform_data = &qcom_wcnss_pdata},
};
+#ifdef CONFIG_QSEECOM
+/* qseecom bus scaling */
+static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = 0,
+ .ab = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = 0,
+ .ab = 0,
+ },
+};
+
+static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = (492 * 8) * 1000000UL,
+ .ab = (492 * 8) * 100000UL,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = 0,
+ .ab = 0,
+ },
+};
+
+static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = 0,
+ .ab = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = (64 * 8) * 1000000UL,
+ .ab = (64 * 8) * 100000UL,
+ },
+};
+
+static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
+ {
+ ARRAY_SIZE(qseecom_clks_init_vectors),
+ qseecom_clks_init_vectors,
+ },
+ {
+ ARRAY_SIZE(qseecom_enable_dfab_vectors),
+ qseecom_enable_sfpb_vectors,
+ },
+ {
+ ARRAY_SIZE(qseecom_enable_sfpb_vectors),
+ qseecom_enable_sfpb_vectors,
+ },
+};
+
+static struct msm_bus_scale_pdata qseecom_bus_pdata = {
+ qseecom_hw_bus_scale_usecases,
+ ARRAY_SIZE(qseecom_hw_bus_scale_usecases),
+ .name = "qsee",
+};
+
+static struct platform_device qseecom_device = {
+ .name = "qseecom",
+ .id = 0,
+ .dev = {
+ .platform_data = &qseecom_bus_pdata,
+ },
+};
+#endif
+
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
@@ -1301,7 +1378,7 @@
/* T6 Object */
0, 0, 0, 0, 0, 0,
/* T38 Object */
- 15, 1, 0, 15, 12, 11, 0, 0,
+ 15, 2, 0, 15, 12, 11, 0, 0,
/* T7 Object */
48, 255, 25,
/* T8 Object */
@@ -1646,6 +1723,10 @@
&msm8960_device_qup_i2c_gsbi12,
&msm_slim_ctrl,
&msm_device_wcnss_wlan,
+#if defined(CONFIG_QSEECOM)
+ &qseecom_device,
+#endif
+
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
&qcrypto_device,
diff --git a/arch/arm/mach-msm/board-8960-camera.c b/arch/arm/mach-msm/board-8960-camera.c
index a3d9cba..0d1c72d 100644
--- a/arch/arm/mach-msm/board-8960-camera.c
+++ b/arch/arm/mach-msm/board-8960-camera.c
@@ -412,9 +412,11 @@
.cam_bus_scale_table = &cam_bus_client_pdata,
},
{
- .ioclk.mclk_clk_rate = 24000000,
- .ioclk.vfe_clk_rate = 228570000,
.csid_core = 2,
+ .is_csiphy = 1,
+ .is_csid = 1,
+ .is_ispif = 1,
+ .is_vpe = 1,
.cam_bus_scale_table = &cam_bus_client_pdata,
},
};
@@ -630,7 +632,10 @@
};
static struct msm_camera_sensor_flash_data flash_imx091 = {
- .flash_type = MSM_CAMERA_FLASH_NONE,
+ .flash_type = MSM_CAMERA_FLASH_LED,
+#ifdef CONFIG_MSM_CAMERA_FLASH
+ .flash_src = &msm_flash_src
+#endif
};
static struct msm_camera_sensor_platform_info sensor_board_info_imx091 = {
diff --git a/arch/arm/mach-msm/board-8960-display.c b/arch/arm/mach-msm/board-8960-display.c
index 4b887e8..8c41e8c 100644
--- a/arch/arm/mach-msm/board-8960-display.c
+++ b/arch/arm/mach-msm/board-8960-display.c
@@ -480,6 +480,7 @@
return 0;
}
+static char mipi_dsi_splash_is_enabled(void);
static int mipi_dsi_panel_power(int on)
{
int ret;
@@ -497,6 +498,7 @@
static struct mipi_dsi_platform_data mipi_dsi_pdata = {
.vsync_gpio = MDP_VSYNC_GPIO,
.dsi_power_save = mipi_dsi_panel_power,
+ .splash_is_enabled = mipi_dsi_splash_is_enabled,
};
#ifdef CONFIG_MSM_BUS_SCALING
@@ -619,6 +621,11 @@
#endif
}
+static char mipi_dsi_splash_is_enabled(void)
+{
+ return mdp_pdata.cont_splash_enabled;
+}
+
static struct platform_device mipi_dsi_renesas_panel_device = {
.name = "mipi_renesas",
.id = 0,
@@ -1058,12 +1065,21 @@
void __init msm8960_set_display_params(char *prim_panel, char *ext_panel)
{
+ int disable_splash = 0;
if (strnlen(prim_panel, PANEL_NAME_MAX_LEN)) {
strlcpy(msm_fb_pdata.prim_panel_name, prim_panel,
PANEL_NAME_MAX_LEN);
pr_debug("msm_fb_pdata.prim_panel_name %s\n",
msm_fb_pdata.prim_panel_name);
+ if (strncmp((char *)msm_fb_pdata.prim_panel_name,
+ MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
+ strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
+ PANEL_NAME_MAX_LEN))) {
+ /* Disable splash for panels other than Toshiba WSVGA */
+ disable_splash = 1;
+ }
+
if (!strncmp((char *)msm_fb_pdata.prim_panel_name,
HDMI_PANEL_NAME, strnlen(HDMI_PANEL_NAME,
PANEL_NAME_MAX_LEN))) {
@@ -1086,6 +1102,6 @@
msm_fb_pdata.ext_panel_name);
}
- if (hdmi_is_primary)
+ if (disable_splash)
mdp_pdata.cont_splash_enabled = 0;
}
diff --git a/arch/arm/mach-msm/board-8960-gpiomux.c b/arch/arm/mach-msm/board-8960-gpiomux.c
index 2cb923c..9bf80ed 100644
--- a/arch/arm/mach-msm/board-8960-gpiomux.c
+++ b/arch/arm/mach-msm/board-8960-gpiomux.c
@@ -61,6 +61,18 @@
.pull = GPIOMUX_PULL_NONE,
};
+static struct gpiomux_setting gsbi9_active_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting gsbi9_suspended_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
static struct gpiomux_setting gsbi10 = {
.func = GPIOMUX_FUNC_2,
.drv = GPIOMUX_DRV_8MA,
@@ -276,6 +288,37 @@
};
#endif
+static struct msm_gpiomux_config msm8960_fusion_gsbi_configs[] = {
+ {
+ .gpio = 93,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+ {
+ .gpio = 94,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+ {
+ .gpio = 95,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+ {
+ .gpio = 96,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+};
+
static struct msm_gpiomux_config msm8960_gsbi_configs[] __initdata = {
{
.gpio = 6, /* GSBI1 QUP SPI_DATA_MOSI */
@@ -730,6 +773,10 @@
else
msm_gpiomux_install(msm8960_gsbi5_uart_configs,
ARRAY_SIZE(msm8960_gsbi5_uart_configs));
+ /* For 8960 Fusion 2.2 Primary IPC */
+ if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE)
+ msm_gpiomux_install(msm8960_fusion_gsbi_configs,
+ ARRAY_SIZE(msm8960_fusion_gsbi_configs));
return 0;
}
diff --git a/arch/arm/mach-msm/board-8960-storage.c b/arch/arm/mach-msm/board-8960-storage.c
index b03da38..cd53f83 100644
--- a/arch/arm/mach-msm/board-8960-storage.c
+++ b/arch/arm/mach-msm/board-8960-storage.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -206,13 +206,18 @@
},
};
+#define MSM_MPM_PIN_SDC1_DAT1 17
+#define MSM_MPM_PIN_SDC3_DAT1 21
+
static unsigned int sdc1_sup_clk_rates[] = {
400000, 24000000, 48000000
};
+#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
static unsigned int sdc3_sup_clk_rates[] = {
400000, 24000000, 48000000, 96000000, 192000000
};
+#endif
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
static struct mmc_platform_data msm8960_sdc1_data = {
@@ -228,6 +233,7 @@
.nonremovable = 1,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
.pin_data = &mmc_slot_pin_data[SDCC1],
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
};
#endif
@@ -253,6 +259,7 @@
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_600),
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
};
#endif
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index c677d97..6ed174c 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -41,6 +41,7 @@
#include <linux/ks8851.h>
#include <linux/i2c/isa1200.h>
#include <linux/memory.h>
+#include <linux/memblock.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -51,6 +52,7 @@
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/msm_spi.h>
+#include <mach/msm_serial_hs.h>
#ifdef CONFIG_USB_MSM_OTG_72K
#include <mach/msm_hsusb.h>
#else
@@ -158,6 +160,12 @@
#define MSM_LIQUID_ION_MM_SIZE (MSM_ION_MM_SIZE + 0x600000)
#define MSM_LIQUID_ION_SF_SIZE MSM_LIQUID_PMEM_SIZE
#define MSM_HDMI_PRIM_ION_SF_SIZE MSM_HDMI_PRIM_PMEM_SIZE
+
+#define MSM8960_FIXED_AREA_START 0xa0000000
+#define MAX_FIXED_AREA_SIZE 0x10000000
+#define MSM_MM_FW_SIZE 0x200000
+#define MSM8960_FW_START (MSM8960_FIXED_AREA_START - MSM_MM_FW_SIZE)
+
static unsigned msm_ion_sf_size = MSM_ION_SF_SIZE;
#else
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x110C000
@@ -366,6 +374,7 @@
.align = PAGE_SIZE,
.reusable = FMEM_ENABLED,
.mem_is_fmem = FMEM_ENABLED,
+ .fixed_position = FIXED_MIDDLE,
};
static struct ion_cp_heap_pdata cp_mfc_ion_pdata = {
@@ -373,6 +382,7 @@
.align = PAGE_SIZE,
.reusable = 0,
.mem_is_fmem = FMEM_ENABLED,
+ .fixed_position = FIXED_HIGH,
};
static struct ion_co_heap_pdata co_ion_pdata = {
@@ -385,6 +395,7 @@
.adjacent_mem_id = ION_CP_MM_HEAP_ID,
.align = SZ_128K,
.mem_is_fmem = FMEM_ENABLED,
+ .fixed_position = FIXED_LOW,
};
#endif
@@ -512,6 +523,24 @@
msm8960_reserve_table[mem_type].size += size;
}
+static void __init msm8960_reserve_fixed_area(unsigned long fixed_area_size)
+{
+#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
+ int ret;
+
+ if (fixed_area_size > MAX_FIXED_AREA_SIZE)
+ panic("fixed area size is larger than %dM\n",
+ MAX_FIXED_AREA_SIZE >> 20);
+
+ reserve_info->fixed_area_size = fixed_area_size;
+ reserve_info->fixed_area_start = MSM8960_FW_START;
+
+ ret = memblock_remove(reserve_info->fixed_area_start,
+ reserve_info->fixed_area_size);
+ BUG_ON(ret);
+#endif
+}
+
/**
* Reserve memory for ION and calculate amount of reusable memory for fmem.
* We only reserve memory for heaps that are not reusable. However, we only
@@ -529,11 +558,17 @@
#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
unsigned int i;
unsigned int reusable_count = 0;
+ unsigned int fixed_size = 0;
+ unsigned int fixed_low_size, fixed_middle_size, fixed_high_size;
+ unsigned long fixed_low_start, fixed_middle_start, fixed_high_start;
adjust_mem_for_liquid();
fmem_pdata.size = 0;
fmem_pdata.reserved_size_low = 0;
fmem_pdata.reserved_size_high = 0;
+ fixed_low_size = 0;
+ fixed_middle_size = 0;
+ fixed_high_size = 0;
/* We only support 1 reusable heap. Check if more than one heap
* is specified as reusable and set as non-reusable if found.
@@ -556,40 +591,98 @@
}
for (i = 0; i < ion_pdata.nr; ++i) {
- int reusable = 0;
- int adjacent_heap_id = INVALID_HEAP_ID;
- int mem_is_fmem = 0;
const struct ion_platform_heap *heap = &(ion_pdata.heaps[i]);
if (heap->extra_data) {
+ int fixed_position = NOT_FIXED;
+ int mem_is_fmem = 0;
+
switch (heap->type) {
case ION_HEAP_TYPE_CP:
- reusable = ((struct ion_cp_heap_pdata *)
- heap->extra_data)->reusable;
mem_is_fmem = ((struct ion_cp_heap_pdata *)
- heap->extra_data)->mem_is_fmem;
+ heap->extra_data)->mem_is_fmem;
+ fixed_position = ((struct ion_cp_heap_pdata *)
+ heap->extra_data)->fixed_position;
break;
case ION_HEAP_TYPE_CARVEOUT:
- adjacent_heap_id = ((struct ion_co_heap_pdata *)
- heap->extra_data)->adjacent_mem_id;
mem_is_fmem = ((struct ion_co_heap_pdata *)
- heap->extra_data)->mem_is_fmem;
+ heap->extra_data)->mem_is_fmem;
+ fixed_position = ((struct ion_co_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ default:
+ break;
+ }
+
+ if (fixed_position != NOT_FIXED)
+ fixed_size += heap->size;
+ else
+ reserve_mem_for_ion(MEMTYPE_EBI1, heap->size);
+
+ if (fixed_position == FIXED_LOW)
+ fixed_low_size += heap->size;
+ else if (fixed_position == FIXED_MIDDLE)
+ fixed_middle_size += heap->size;
+ else if (fixed_position == FIXED_HIGH)
+ fixed_high_size += heap->size;
+
+ if (mem_is_fmem)
+ fmem_pdata.size += heap->size;
+ }
+ }
+
+ if (!fixed_size)
+ return;
+
+ if (fmem_pdata.size) {
+ fmem_pdata.reserved_size_low = fixed_low_size;
+ fmem_pdata.reserved_size_high = fixed_high_size;
+ }
+
+ /* Since the fixed area may be carved out of lowmem,
+ * make sure the length is a multiple of 1M.
+ */
+ fixed_size = (fixed_size + MSM_MM_FW_SIZE + SECTION_SIZE - 1)
+ & SECTION_MASK;
+ msm8960_reserve_fixed_area(fixed_size);
+
+ fixed_low_start = MSM8960_FIXED_AREA_START;
+ fixed_middle_start = fixed_low_start + fixed_low_size;
+ fixed_high_start = fixed_middle_start + fixed_middle_size;
+
+ for (i = 0; i < ion_pdata.nr; ++i) {
+ struct ion_platform_heap *heap = &(ion_pdata.heaps[i]);
+
+ if (heap->extra_data) {
+ int fixed_position = NOT_FIXED;
+
+ switch (heap->type) {
+ case ION_HEAP_TYPE_CP:
+ fixed_position = ((struct ion_cp_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ case ION_HEAP_TYPE_CARVEOUT:
+ fixed_position = ((struct ion_co_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ default:
+ break;
+ }
+
+ switch (fixed_position) {
+ case FIXED_LOW:
+ heap->base = fixed_low_start;
+ break;
+ case FIXED_MIDDLE:
+ heap->base = fixed_middle_start;
+ break;
+ case FIXED_HIGH:
+ heap->base = fixed_high_start;
break;
default:
break;
}
}
-
- if (mem_is_fmem && !reusable) {
- if (adjacent_heap_id != INVALID_HEAP_ID)
- fmem_pdata.reserved_size_low += heap->size;
- else
- fmem_pdata.reserved_size_high += heap->size;
- }
- if (mem_is_fmem)
- fmem_pdata.size += heap->size;
- else
- reserve_mem_for_ion(MEMTYPE_EBI1, heap->size);
}
#endif
}
@@ -658,6 +751,7 @@
static struct reserve_info msm8960_reserve_info __initdata = {
.memtype_reserve_table = msm8960_reserve_table,
.calculate_reserve_sizes = msm8960_calculate_reserve_sizes,
+ .reserve_fixed_area = msm8960_reserve_fixed_area,
.paddr_to_memtype = msm8960_paddr_to_memtype,
};
@@ -673,6 +767,8 @@
unsigned long low, high;
bank_size = msm8960_memory_bank_size();
+ msm8960_reserve_info.bank_size = bank_size;
+
low = meminfo.bank[0].start;
high = mb->start + mb->size;
@@ -680,12 +776,14 @@
if (high < mb->start)
high = ~0UL;
+ if (high < MAX_FIXED_AREA_SIZE + MSM8960_FIXED_AREA_START)
+ panic("fixed area extends beyond end of memory\n");
+
low &= ~(bank_size - 1);
if (high - low <= bank_size)
- return;
+ goto no_dmm;
- msm8960_reserve_info.bank_size = bank_size;
#ifdef CONFIG_ENABLE_DMM
msm8960_reserve_info.low_unstable_address = mb->start -
MIN_MEMORY_BLOCK_SIZE + mb->size;
@@ -694,10 +792,11 @@
msm8960_reserve_info.low_unstable_address,
msm8960_reserve_info.max_unstable_size,
msm8960_reserve_info.bank_size);
-#else
- msm8960_reserve_info.low_unstable_address = 0;
- msm8960_reserve_info.max_unstable_size = 0;
+ return;
#endif
+no_dmm:
+ msm8960_reserve_info.low_unstable_address = high;
+ msm8960_reserve_info.max_unstable_size = 0;
}
static void __init place_movable_zone(void)
@@ -739,7 +838,18 @@
{
msm8960_set_display_params(prim_panel_name, ext_panel_name);
msm_reserve();
- fmem_pdata.phys = reserve_memory_for_fmem(fmem_pdata.size);
+ if (fmem_pdata.size) {
+#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
+ fmem_pdata.phys = reserve_info->fixed_area_start +
+ MSM_MM_FW_SIZE;
+ pr_info("mm fw at %lx (fixed) size %x\n",
+ reserve_info->fixed_area_start, MSM_MM_FW_SIZE);
+ pr_info("fmem start %lx (fixed) size %lx\n",
+ fmem_pdata.phys, fmem_pdata.size);
+#else
+ fmem_pdata.phys = reserve_memory_for_fmem(fmem_pdata.size);
+#endif
+ }
}
static int msm8960_change_memory_power(u64 start, u64 size,
@@ -957,6 +1067,83 @@
.dev = {.platform_data = &qcom_wcnss_pdata},
};
+#ifdef CONFIG_QSEECOM
+/* qseecom bus scaling */
+static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = 0,
+ .ab = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = 0,
+ .ab = 0,
+ },
+};
+
+static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = (492 * 8) * 1000000UL,
+ .ab = (492 * 8) * 100000UL,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = 0,
+ .ab = 0,
+ },
+};
+
+static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_SPS,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ib = 0,
+ .ab = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_SPDM,
+ .dst = MSM_BUS_SLAVE_SPDM,
+ .ib = (64 * 8) * 1000000UL,
+ .ab = (64 * 8) * 100000UL,
+ },
+};
+
+static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
+ {
+ ARRAY_SIZE(qseecom_clks_init_vectors),
+ qseecom_clks_init_vectors,
+ },
+ {
+ ARRAY_SIZE(qseecom_enable_dfab_vectors),
+ qseecom_enable_sfpb_vectors,
+ },
+ {
+ ARRAY_SIZE(qseecom_enable_sfpb_vectors),
+ qseecom_enable_sfpb_vectors,
+ },
+};
+
+static struct msm_bus_scale_pdata qseecom_bus_pdata = {
+ qseecom_hw_bus_scale_usecases,
+ ARRAY_SIZE(qseecom_hw_bus_scale_usecases),
+ .name = "qsee",
+};
+
+static struct platform_device qseecom_device = {
+ .name = "qseecom",
+ .id = 0,
+ .dev = {
+ .platform_data = &qseecom_bus_pdata,
+ },
+};
+#endif
+
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
@@ -2214,11 +2401,45 @@
.platform_data = &msm_rpm_regulator_pdata,
},
};
+#ifdef CONFIG_SERIAL_MSM_HS
+static int configure_uart_gpios(int on)
+{
+ int ret = 0, i;
+ int uart_gpios[] = {93, 94, 95, 96};
+
+ for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
+ if (on) {
+ ret = gpio_request(uart_gpios[i], NULL);
+ if (ret) {
+ pr_err("%s: unable to request uart gpio[%d]\n",
+ __func__, uart_gpios[i]);
+ break;
+ }
+ } else {
+ gpio_free(uart_gpios[i]);
+ }
+ }
+
+ if (ret && on && i)
+ for (; i >= 0; i--)
+ gpio_free(uart_gpios[i]);
+ return ret;
+}
+
+static struct msm_serial_hs_platform_data msm_uart_dm9_pdata = {
+ .inject_rx_on_wakeup = 1,
+ .rx_to_inject = 0xFD,
+ .gpio_config = configure_uart_gpios,
+};
+#else
+static struct msm_serial_hs_platform_data msm_uart_dm9_pdata;
+#endif
static struct platform_device *common_devices[] __initdata = {
&msm8960_device_dmov,
&msm_device_smd,
&msm_device_uart_dm6,
+ &msm_device_uart_dm9,
&msm_device_saw_core0,
&msm_device_saw_core1,
&msm8960_device_ext_5v_vreg,
@@ -2233,6 +2454,9 @@
#endif
&msm_slim_ctrl,
&msm_device_wcnss_wlan,
+#if defined(CONFIG_QSEECOM)
+ &qseecom_device,
+#endif
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
&qcrypto_device,
@@ -2317,6 +2541,7 @@
&msm_pcm_routing,
&msm_cpudai0,
&msm_cpudai1,
+ &msm8960_cpudai_slimbus_2_tx,
&msm_cpudai_hdmi_rx,
&msm_cpudai_bt_rx,
&msm_cpudai_bt_tx,
@@ -2372,6 +2597,7 @@
&msm_pcm_routing,
&msm_cpudai0,
&msm_cpudai1,
+ &msm8960_cpudai_slimbus_2_tx,
&msm_cpudai_hdmi_rx,
&msm_cpudai_bt_rx,
&msm_cpudai_bt_tx,
@@ -2795,7 +3021,6 @@
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
platform_device_register(&msm8960_device_rpm_regulator);
- msm_clock_init(&msm8960_dummy_clock_init_data);
msm8960_init_gpiomux();
msm8960_init_pmic();
msm8960_device_qup_spi_gsbi1.dev.platform_data =
@@ -2809,6 +3034,8 @@
platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
msm8960_init_mmc();
register_i2c_devices();
+
+
msm8960_init_fb();
slim_register_board_info(msm_slim_devices,
ARRAY_SIZE(msm_slim_devices));
@@ -2872,6 +3099,10 @@
else
platform_device_register(&msm8960_device_uart_gsbi5);
+ /* For 8960 Fusion 2.2 Primary IPC */
+ if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE)
+ msm_device_uart_dm9.dev.platform_data = &msm_uart_dm9_pdata;
+
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
msm8960_pm8921_gpio_mpp_init();
platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
diff --git a/arch/arm/mach-msm/board-9615-storage.c b/arch/arm/mach-msm/board-9615-storage.c
index c73e5a9..6bf7c69 100644
--- a/arch/arm/mach-msm/board-9615-storage.c
+++ b/arch/arm/mach-msm/board-9615-storage.c
@@ -163,6 +163,8 @@
#endif
};
+#define MSM_MPM_PIN_SDC1_DAT1 17
+
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
static unsigned int sdc1_sup_clk_rates[] = {
400000, 24000000, 48000000
@@ -183,7 +185,8 @@
#endif
.xpc_cap = 1,
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
- MMC_CAP_MAX_CURRENT_400)
+ MMC_CAP_MAX_CURRENT_400),
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
};
static struct mmc_platform_data *msm9615_sdc1_pdata = &sdc1_data;
#else
diff --git a/arch/arm/mach-msm/board-copper-gpiomux.c b/arch/arm/mach-msm/board-copper-gpiomux.c
new file mode 100644
index 0000000..50b03fc
--- /dev/null
+++ b/arch/arm/mach-msm/board-copper-gpiomux.c
@@ -0,0 +1,53 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/gpiomux.h>
+
+static struct gpiomux_setting gpio_uart_config = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_16MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_OUT_HIGH,
+};
+
+static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
+ {
+ .gpio = 45, /* BLSP8 UART TX */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_uart_config,
+ },
+ },
+ {
+ .gpio = 46, /* BLSP8 UART RX */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_uart_config,
+ },
+ },
+};
+
+void __init msm_copper_init_gpiomux(void)
+{
+ int rc;
+
+ rc = msm_gpiomux_init(NR_GPIO_IRQS);
+ if (rc) {
+ pr_err(KERN_ERR "msmcopper_init_gpiomux failed %d\n", rc);
+ return;
+ }
+
+ msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs));
+}
diff --git a/arch/arm/mach-msm/board-copper.c b/arch/arm/mach-msm/board-copper.c
index b074809..28f5e7f 100644
--- a/arch/arm/mach-msm/board-copper.c
+++ b/arch/arm/mach-msm/board-copper.c
@@ -340,19 +340,6 @@
msm_reserve();
}
-static int __init gpiomux_init(void)
-{
- int rc;
-
- rc = msm_gpiomux_init(NR_GPIO_IRQS);
- if (rc) {
- pr_err("%s: msm_gpiomux_init failed %d\n", __func__, rc);
- return rc;
- }
-
- return 0;
-}
-
static struct platform_device android_usb_device = {
.name = "android_usb",
.id = -1,
@@ -401,7 +388,6 @@
CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF),
CLK_DUMMY("phy_clk", NULL, "msm_otg", OFF),
CLK_DUMMY("core_clk", NULL, "msm_otg", OFF),
- CLK_DUMMY("alt_core_clk", NULL, "msm_otg", OFF),
CLK_DUMMY("iface_clk", NULL, "msm_otg", OFF),
CLK_DUMMY("xo", NULL, "msm_otg", OFF),
CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
@@ -428,13 +414,16 @@
"spi_qsd.1", NULL),
OF_DEV_AUXDATA("qcom,spmi-pmic-arb", 0xFC4C0000, \
"spmi-pmic-arb.0", NULL),
+ OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF980B000, \
+ "msm_sdcc.1", NULL),
+ OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF984B000, \
+ "msm_sdcc.3", NULL),
{}
};
void __init msm_copper_init(struct of_dev_auxdata **adata)
{
- if (gpiomux_init())
- pr_err("%s: gpiomux_init() failed\n", __func__);
+ msm_copper_init_gpiomux();
msm_clock_init(&msm_dummy_clock_init_data);
*adata = msm_copper_auxdata_lookup;
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 5b60af0..c3650fa 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -49,6 +49,7 @@
#include <linux/smsc911x.h>
#include <linux/atmel_maxtouch.h>
#include <linux/fmem.h>
+#include <linux/msm_adc.h>
#include "devices.h"
#include "timer.h"
#include "board-msm7x27a-regulator.h"
@@ -712,6 +713,24 @@
"eth_fifo_sel" },
};
+static char *msm_adc_surf_device_names[] = {
+ "XO_ADC",
+};
+
+static struct msm_adc_platform_data msm_adc_pdata = {
+ .dev_names = msm_adc_surf_device_names,
+ .num_adc = ARRAY_SIZE(msm_adc_surf_device_names),
+ .target_hw = MSM_8x25,
+};
+
+static struct platform_device msm_adc_device = {
+ .name = "msm_adc",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_adc_pdata,
+ },
+};
+
#define ETH_FIFO_SEL_GPIO 49
static void msm7x27a_cfg_smsc911x(void)
{
@@ -814,6 +833,7 @@
&asoc_msm_dai0,
&asoc_msm_dai1,
&msm_batt_device,
+ &msm_adc_device,
};
static struct platform_device *msm8625_surf_devices[] __initdata = {
diff --git a/arch/arm/mach-msm/board-msm8x60-camera.c b/arch/arm/mach-msm/board-msm8x60-camera.c
index 95561e4..c12dce6 100644
--- a/arch/arm/mach-msm/board-msm8x60-camera.c
+++ b/arch/arm/mach-msm/board-msm8x60-camera.c
@@ -12,7 +12,6 @@
*/
#include <asm/mach-types.h>
-#include <devices-msm8x60.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/mfd/pmic8901.h>
@@ -20,6 +19,7 @@
#include <mach/board-msm8660.h>
#include <mach/gpiomux.h>
#include <mach/msm_bus_board.h>
+#include "devices-msm8x60.h"
#include "devices.h"
#define GPIO_EXT_CAMIF_PWR_EN1 (PM8901_MPP_BASE + PM8901_MPPS + 13)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 8e02093..da362a0 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -2630,7 +2630,7 @@
#endif /* CONFIG_FB_MSM_OVERLAY1_WRITEBACK */
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x3BC000
-#define MSM_PMEM_ADSP_SIZE 0x2000000
+#define MSM_PMEM_ADSP_SIZE 0x4200000
#define MSM_PMEM_AUDIO_SIZE 0x4CF000
#define MSM_SMI_BASE 0x38000000
@@ -8311,44 +8311,10 @@
}
#endif
#endif
-
-#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
-static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
-{
- struct platform_device *pdev;
- enum msm_mpm_pin pin;
- int ret = 0;
-
- pdev = container_of(dev, struct platform_device, dev);
-
- /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
- if (pdev->id == 4)
- pin = MSM_MPM_PIN_SDC4_DAT1;
- else
- return -EINVAL;
-
- switch (mode) {
- case SDC_DAT1_DISABLE:
- ret = msm_mpm_enable_pin(pin, 0);
- break;
- case SDC_DAT1_ENABLE:
- ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
- ret = msm_mpm_enable_pin(pin, 1);
- break;
- case SDC_DAT1_ENWAKE:
- ret = msm_mpm_set_pin_wake(pin, 1);
- break;
- case SDC_DAT1_DISWAKE:
- ret = msm_mpm_set_pin_wake(pin, 0);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
#endif
-#endif
+
+#define MSM_MPM_PIN_SDC3_DAT1 21
+#define MSM_MPM_PIN_SDC4_DAT1 23
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
static struct mmc_platform_data msm8x60_sdc1_data = {
@@ -8402,6 +8368,7 @@
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
.pclk_src_dfab = 1,
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
};
#endif
@@ -8415,7 +8382,7 @@
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
.pclk_src_dfab = 1,
- .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC4_DAT1,
};
#endif
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 4a6b150..3e8dd8f 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -30,6 +30,7 @@
#include <linux/regulator/consumer.h>
#include <linux/memblock.h>
#include <linux/input/ft5x06_ts.h>
+#include <linux/msm_adc.h>
#include <asm/mach/mmc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -599,6 +600,24 @@
.dev.platform_data = &msm_psy_batt_data,
};
+static char *msm_adc_surf_device_names[] = {
+ "XO_ADC",
+};
+
+static struct msm_adc_platform_data msm_adc_pdata = {
+ .dev_names = msm_adc_surf_device_names,
+ .num_adc = ARRAY_SIZE(msm_adc_surf_device_names),
+ .target_hw = MSM_8x25,
+};
+
+static struct platform_device msm_adc_device = {
+ .name = "msm_adc",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_adc_pdata,
+ },
+};
+
static struct platform_device *common_devices[] __initdata = {
&android_usb_device,
&android_pmem_device,
@@ -610,6 +629,7 @@
&asoc_msm_pcm,
&asoc_msm_dai0,
&asoc_msm_dai1,
+ &msm_adc_device,
};
static struct platform_device *qrd7627a_devices[] __initdata = {
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index f9d8dbe..5951734 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -31,6 +31,7 @@
#include "clock-pcom.h"
#include "clock-voter.h"
#include "proc_comm.h"
+#include "clock-pll.h"
#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
#define REG(off) (MSM_CLK_CTL_SH2_BASE + (off))
@@ -268,6 +269,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(1),
.status_reg = PLL1_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &tcxo_clk.c,
.c = {
.dbg_name = "pll1_clk",
@@ -282,6 +284,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(2),
.status_reg = PLL2_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &tcxo_clk.c,
.c = {
.dbg_name = "pll2_clk",
@@ -296,6 +299,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(3),
.status_reg = PLL3_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &lpxo_clk.c,
.c = {
.dbg_name = "pll3_clk",
@@ -309,6 +313,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(4),
.status_reg = PLL4_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &lpxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index bbe7bae..873db2d 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -33,6 +33,7 @@
#include "clock-voter.h"
#include "clock-dss-8960.h"
#include "devices.h"
+#include "clock-pll.h"
#define REG(off) (MSM_CLK_CTL_BASE + (off))
#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
@@ -478,7 +479,7 @@
.c = {
.dbg_name = "pll2_clk",
.rate = 800000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
.warned = true,
},
@@ -490,7 +491,7 @@
.c = {
.dbg_name = "pll3_clk",
.rate = 1200000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
.vdd_class = &vdd_sr2_pll,
.fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
CLK_INIT(pll3_clk.c),
@@ -502,6 +503,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
@@ -516,6 +518,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
@@ -530,6 +533,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(14),
.status_reg = BB_PLL14_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
@@ -546,7 +550,7 @@
.c = {
.dbg_name = "pll15_clk",
.rate = 975000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll15_clk.c),
.warned = true,
},
@@ -4357,7 +4361,7 @@
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0),
+ { .ns_val = BIT(10) /* external input */ },
F_PCM( 512000, pll4, 4, 1, 192),
F_PCM( 768000, pll4, 4, 1, 128),
F_PCM( 1024000, pll4, 4, 1, 96),
@@ -4385,7 +4389,7 @@
.ns_reg = LCC_PCM_NS_REG,
.md_reg = LCC_PCM_MD_REG,
.root_en_mask = BIT(9),
- .ns_mask = (BM(31, 16) | BM(6, 0)),
+ .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0),
.mnd_en_mask = BIT(8),
.set_rate = set_rate_mnd,
.freq_tbl = clk_tbl_pcm,
@@ -5034,11 +5038,14 @@
CLK_LOOKUP("bus_clk",
gfx3d_axi_clk_8064.c, "footswitch-8x60.2"),
CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", vcap_p_clk.c, "msm_vcap.0"),
CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
CLK_LOOKUP("core_clk", vcap_clk.c, ""),
+ CLK_LOOKUP("core_clk", vcap_clk.c, "msm_vcap.0"),
CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
+ CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, "msm_vcap.0"),
CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
CLK_LOOKUP("mem_clk", imem_axi_clk.c, ""),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, ""),
@@ -5226,7 +5233,7 @@
CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"),
- CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"),
CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
@@ -5279,7 +5286,7 @@
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"),
- CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"),
CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
@@ -6032,7 +6039,7 @@
vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
- clk_ops_pll.enable = sr_pll_clk_enable;
+ clk_ops_local_pll.enable = sr_pll_clk_enable;
/* Initialize clock registers. */
reg_init();
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 6c85450..a1bbf53 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -31,6 +31,7 @@
#include "clock-local.h"
#include "clock-rpm.h"
#include "clock-voter.h"
+#include "clock-pll.h"
#ifdef CONFIG_MSM_SECURE_IO
#undef readl_relaxed
@@ -304,6 +305,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
@@ -320,7 +322,7 @@
.c = {
.dbg_name = "pll2_clk",
.rate = 800000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
.warned = true,
},
@@ -332,7 +334,7 @@
.c = {
.dbg_name = "pll3_clk",
.rate = 0, /* TODO: Detect rate dynamically */
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll3_clk.c),
.warned = true,
},
@@ -3062,7 +3064,7 @@
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0),
+ { .ns_val = BIT(10) /* external input */ },
F_PCM( 512000, pll4, 4, 1, 264),
F_PCM( 768000, pll4, 4, 1, 176),
F_PCM( 1024000, pll4, 4, 1, 132),
@@ -3090,7 +3092,7 @@
.ns_reg = LCC_PCM_NS_REG,
.md_reg = LCC_PCM_MD_REG,
.root_en_mask = BIT(9),
- .ns_mask = (BM(31, 16) | BM(6, 0)),
+ .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0),
.mnd_en_mask = BIT(8),
.set_rate = set_rate_mnd,
.freq_tbl = clk_tbl_pcm,
@@ -3574,7 +3576,7 @@
CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "msm_serial_hsl.0"),
CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.5"),
- CLK_LOOKUP("ppss_pclk", ppss_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", ppss_p_clk.c, "msm_dsps"),
CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.0"),
CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.1"),
CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
@@ -3692,8 +3694,10 @@
CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
+ CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
+ CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "msm_iommu.7"),
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 411e615..3f25556 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -32,6 +32,7 @@
#include "clock-voter.h"
#include "clock-rpm.h"
#include "devices.h"
+#include "clock-pll.h"
#define REG(off) (MSM_CLK_CTL_BASE + (off))
#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
@@ -259,6 +260,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll0,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
@@ -275,6 +277,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.soft_vote = &soft_vote_pll0,
.soft_vote_mask = PLL_SOFT_VOTE_ACPU,
.c = {
@@ -290,6 +293,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
@@ -306,6 +310,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll8,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
@@ -322,6 +327,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.soft_vote = &soft_vote_pll8,
.soft_vote_mask = PLL_SOFT_VOTE_ACPU,
.c = {
@@ -338,7 +344,7 @@
.c = {
.dbg_name = "pll9_acpu_clk",
.rate = 440000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll9_acpu_clk.c),
.warned = true,
},
@@ -348,6 +354,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(11),
.status_reg = BB_PLL14_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
@@ -1247,7 +1254,7 @@
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0),
+ { .ns_val = BIT(10) /* external input */ },
F_PCM( 512000, pll4, 4, 1, 192),
F_PCM( 768000, pll4, 4, 1, 128),
F_PCM( 1024000, pll4, 4, 1, 96),
@@ -1275,7 +1282,7 @@
.ns_reg = LCC_PCM_NS_REG,
.md_reg = LCC_PCM_MD_REG,
.root_en_mask = BIT(9),
- .ns_mask = (BM(31, 16) | BM(6, 0)),
+ .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0),
.mnd_en_mask = BIT(8),
.set_rate = set_rate_mnd,
.freq_tbl = clk_tbl_pcm,
@@ -1742,7 +1749,7 @@
vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
- clk_ops_pll.enable = sr_pll_clk_enable;
+ clk_ops_local_pll.enable = sr_pll_clk_enable;
/* Enable PDM CXO source. */
regval = readl_relaxed(PDM_CLK_NS_REG);
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index 84aa086..d414e44 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -627,158 +627,6 @@
return HANDOFF_ENABLED_CLK;
}
-int pll_vote_clk_enable(struct clk *clk)
-{
- u32 ena;
- unsigned long flags;
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- ena = readl_relaxed(pll->en_reg);
- ena |= pll->en_mask;
- writel_relaxed(ena, pll->en_reg);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-
- /* Wait until PLL is enabled */
- while ((readl_relaxed(pll->status_reg) & BIT(16)) == 0)
- cpu_relax();
-
- return 0;
-}
-
-void pll_vote_clk_disable(struct clk *clk)
-{
- u32 ena;
- unsigned long flags;
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- ena = readl_relaxed(pll->en_reg);
- ena &= ~(pll->en_mask);
- writel_relaxed(ena, pll->en_reg);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
-struct clk *pll_vote_clk_get_parent(struct clk *clk)
-{
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
- return pll->parent;
-}
-
-int pll_vote_clk_is_enabled(struct clk *clk)
-{
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
- return !!(readl_relaxed(pll->status_reg) & BIT(16));
-}
-
-struct clk_ops clk_ops_pll_vote = {
- .enable = pll_vote_clk_enable,
- .disable = pll_vote_clk_disable,
- .auto_off = pll_vote_clk_disable,
- .is_enabled = pll_vote_clk_is_enabled,
- .get_parent = pll_vote_clk_get_parent,
-};
-
-static int pll_clk_enable(struct clk *clk)
-{
- u32 mode;
- unsigned long flags;
- struct pll_clk *pll = to_pll_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- mode = readl_relaxed(pll->mode_reg);
- /* Disable PLL bypass mode. */
- mode |= BIT(1);
- writel_relaxed(mode, pll->mode_reg);
-
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- udelay(10);
-
- /* De-assert active-low PLL reset. */
- mode |= BIT(2);
- writel_relaxed(mode, pll->mode_reg);
-
- /* Wait until PLL is locked. */
- mb();
- udelay(50);
-
- /* Enable PLL output. */
- mode |= BIT(0);
- writel_relaxed(mode, pll->mode_reg);
-
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
- return 0;
-}
-
-static void pll_clk_disable(struct clk *clk)
-{
- u32 mode;
- unsigned long flags;
- struct pll_clk *pll = to_pll_clk(clk);
-
- /*
- * Disable the PLL output, disable test mode, enable
- * the bypass mode, and assert the reset.
- */
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- mode = readl_relaxed(pll->mode_reg);
- mode &= ~BM(3, 0);
- writel_relaxed(mode, pll->mode_reg);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
-static struct clk *pll_clk_get_parent(struct clk *clk)
-{
- struct pll_clk *pll = to_pll_clk(clk);
- return pll->parent;
-}
-
-int sr_pll_clk_enable(struct clk *clk)
-{
- u32 mode;
- unsigned long flags;
- struct pll_clk *pll = to_pll_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- mode = readl_relaxed(pll->mode_reg);
- /* De-assert active-low PLL reset. */
- mode |= BIT(2);
- writel_relaxed(mode, pll->mode_reg);
-
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- udelay(10);
-
- /* Disable PLL bypass mode. */
- mode |= BIT(1);
- writel_relaxed(mode, pll->mode_reg);
-
- /* Wait until PLL is locked. */
- mb();
- udelay(60);
-
- /* Enable PLL output. */
- mode |= BIT(0);
- writel_relaxed(mode, pll->mode_reg);
-
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
- return 0;
-}
-
-struct clk_ops clk_ops_pll = {
- .enable = pll_clk_enable,
- .disable = pll_clk_disable,
- .auto_off = pll_clk_disable,
- .get_parent = pll_clk_get_parent,
-};
-
struct clk_ops clk_ops_gnd = {
};
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index 3dd849a..0419ede 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -17,12 +17,6 @@
#include <linux/spinlock.h>
#include "clock.h"
-/*
- * Bit manipulation macros
- */
-#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
-#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
-
#define MN_MODE_DUAL_EDGE 0x2
/* MD Registers */
@@ -257,57 +251,6 @@
};
/**
- * struct pll_vote_clk - phase locked loop (HW voteable)
- * @soft_vote: soft voting variable for multiple PLL software instances
- * @soft_vote_mask: soft voting mask for multiple PLL software instances
- * @en_reg: enable register
- * @en_mask: ORed with @en_reg to enable the clock
- * @status_reg: status register
- * @parent: clock source
- * @c: clk
- */
-struct pll_vote_clk {
- u32 *soft_vote;
- const u32 soft_vote_mask;
- void __iomem *const en_reg;
- const u32 en_mask;
-
- void __iomem *const status_reg;
-
- struct clk *parent;
- struct clk c;
-};
-
-extern struct clk_ops clk_ops_pll_vote;
-
-static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
-{
- return container_of(clk, struct pll_vote_clk, c);
-}
-
-/**
- * struct pll_clk - phase locked loop
- * @mode_reg: enable register
- * @parent: clock source
- * @c: clk
- */
-struct pll_clk {
- void __iomem *const mode_reg;
-
- struct clk *parent;
- struct clk c;
-};
-
-extern struct clk_ops clk_ops_pll;
-
-static inline struct pll_clk *to_pll_clk(struct clk *clk)
-{
- return container_of(clk, struct pll_clk, c);
-}
-
-int sr_pll_clk_enable(struct clk *clk);
-
-/**
* struct branch_clk - branch
* @enabled: true if clock is on, false otherwise
* @b: branch
@@ -365,14 +308,6 @@
extern struct fixed_clk gnd_clk;
/*
- * PLL vote clock APIs
- */
-int pll_vote_clk_enable(struct clk *clk);
-void pll_vote_clk_disable(struct clk *clk);
-struct clk *pll_vote_clk_get_parent(struct clk *clk);
-int pll_vote_clk_is_enabled(struct clk *clk);
-
-/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 2d98895..d842d45 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -395,6 +395,7 @@
CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
CLK_LOOKUP("bus_clk", ebi_grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "lcdc.0"),
+ CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "mipi_dsi.1"),
CLK_LOOKUP("mem_clk", ebi_mddi_clk.c, "mddi.0"),
CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index 68c390a..e83f17a 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -17,13 +17,201 @@
#include <linux/err.h>
#include <linux/remote_spinlock.h>
-#include <mach/socinfo.h>
+#include <mach/scm-io.h>
#include <mach/msm_iomap.h>
#include "clock.h"
#include "clock-pll.h"
#include "smd_private.h"
+#ifdef CONFIG_MSM_SECURE_IO
+#undef readl_relaxed
+#undef writel_relaxed
+#define readl_relaxed secure_readl
+#define writel_relaxed secure_writel
+#endif
+
+#define PLL_OUTCTRL BIT(0)
+#define PLL_BYPASSNL BIT(1)
+#define PLL_RESET_N BIT(2)
+#define PLL_MODE_MASK BM(3, 0)
+
+#define PLL_EN_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->en_reg)) : \
+ ((x)->en_reg))
+#define PLL_STATUS_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->status_reg)) : \
+ ((x)->status_reg))
+#define PLL_MODE_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->mode_reg)) : \
+ ((x)->mode_reg))
+
+static DEFINE_SPINLOCK(pll_reg_lock);
+
+int pll_vote_clk_enable(struct clk *clk)
+{
+ u32 ena;
+ unsigned long flags;
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ ena = readl_relaxed(PLL_EN_REG(pll));
+ ena |= pll->en_mask;
+ writel_relaxed(ena, PLL_EN_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+
+ /* Wait until PLL is enabled */
+ while ((readl_relaxed(PLL_STATUS_REG(pll)) & pll->status_mask) == 0)
+ cpu_relax();
+
+ return 0;
+}
+
+void pll_vote_clk_disable(struct clk *clk)
+{
+ u32 ena;
+ unsigned long flags;
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ ena = readl_relaxed(PLL_EN_REG(pll));
+ ena &= ~(pll->en_mask);
+ writel_relaxed(ena, PLL_EN_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+}
+
+struct clk *pll_vote_clk_get_parent(struct clk *clk)
+{
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+ return pll->parent;
+}
+
+int pll_vote_clk_is_enabled(struct clk *clk)
+{
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+ return !!(readl_relaxed(PLL_STATUS_REG(pll)) & pll->status_mask);
+}
+
+struct clk_ops clk_ops_pll_vote = {
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+ .get_parent = pll_vote_clk_get_parent,
+};
+
+static void __pll_clk_enable_reg(void __iomem *mode_reg)
+{
+ u32 mode = readl_relaxed(mode_reg);
+ /* Disable PLL bypass mode. */
+ mode |= PLL_BYPASSNL;
+ writel_relaxed(mode, mode_reg);
+
+ /*
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
+ mb();
+ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ mode |= PLL_RESET_N;
+ writel_relaxed(mode, mode_reg);
+
+ /* Wait until PLL is locked. */
+ mb();
+ udelay(50);
+
+ /* Enable PLL output. */
+ mode |= PLL_OUTCTRL;
+ writel_relaxed(mode, mode_reg);
+
+ /* Ensure that the write above goes through before returning. */
+ mb();
+}
+
+static int local_pll_clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+ struct pll_clk *pll = to_pll_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ __pll_clk_enable_reg(PLL_MODE_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+
+ return 0;
+}
+
+static void __pll_clk_disable_reg(void __iomem *mode_reg)
+{
+ u32 mode = readl_relaxed(mode_reg);
+ mode &= ~PLL_MODE_MASK;
+ writel_relaxed(mode, mode_reg);
+}
+
+static void local_pll_clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+ struct pll_clk *pll = to_pll_clk(clk);
+
+ /*
+ * Disable the PLL output, disable test mode, enable
+ * the bypass mode, and assert the reset.
+ */
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ __pll_clk_disable_reg(PLL_MODE_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+}
+
+static struct clk *local_pll_clk_get_parent(struct clk *clk)
+{
+ struct pll_clk *pll = to_pll_clk(clk);
+ return pll->parent;
+}
+
+int sr_pll_clk_enable(struct clk *clk)
+{
+ u32 mode;
+ unsigned long flags;
+ struct pll_clk *pll = to_pll_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ mode = readl_relaxed(PLL_MODE_REG(pll));
+ /* De-assert active-low PLL reset. */
+ mode |= PLL_RESET_N;
+ writel_relaxed(mode, PLL_MODE_REG(pll));
+
+ /*
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
+ mb();
+ udelay(10);
+
+ /* Disable PLL bypass mode. */
+ mode |= PLL_BYPASSNL;
+ writel_relaxed(mode, PLL_MODE_REG(pll));
+
+ /* Wait until PLL is locked. */
+ mb();
+ udelay(60);
+
+ /* Enable PLL output. */
+ mode |= PLL_OUTCTRL;
+ writel_relaxed(mode, PLL_MODE_REG(pll));
+
+ /* Ensure that the write above goes through before returning. */
+ mb();
+
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+
+ return 0;
+}
+
+struct clk_ops clk_ops_local_pll = {
+ .enable = local_pll_clk_enable,
+ .disable = local_pll_clk_disable,
+ .auto_off = local_pll_clk_disable,
+ .get_parent = local_pll_clk_get_parent,
+};
+
struct pll_rate {
unsigned int lvalue;
unsigned long rate;
@@ -95,21 +283,6 @@
}
-static void pll_enable(void __iomem *addr, unsigned on)
-{
- if (on) {
- writel_relaxed(2, addr);
- mb();
- udelay(5);
- writel_relaxed(6, addr);
- mb();
- udelay(50);
- writel_relaxed(7, addr);
- } else {
- writel_relaxed(0, addr);
- }
-}
-
static int pll_clk_enable(struct clk *clk)
{
struct pll_shared_clk *pll = to_pll_shared_clk(clk);
@@ -119,7 +292,7 @@
pll_control->pll[PLL_BASE + pll_id].votes |= BIT(1);
if (!pll_control->pll[PLL_BASE + pll_id].on) {
- pll_enable(pll->mode_reg, 1);
+ __pll_clk_enable_reg(PLL_MODE_REG(pll));
pll_control->pll[PLL_BASE + pll_id].on = 1;
}
@@ -137,7 +310,7 @@
pll_control->pll[PLL_BASE + pll_id].votes &= ~BIT(1);
if (pll_control->pll[PLL_BASE + pll_id].on
&& !pll_control->pll[PLL_BASE + pll_id].votes) {
- pll_enable(pll->mode_reg, 0);
+ __pll_clk_disable_reg(PLL_MODE_REG(pll));
pll_control->pll[PLL_BASE + pll_id].on = 0;
}
@@ -148,12 +321,7 @@
{
struct pll_shared_clk *pll = to_pll_shared_clk(clk);
- return readl_relaxed(pll->mode_reg) & BIT(0);
-}
-
-static bool pll_clk_is_local(struct clk *clk)
-{
- return true;
+ return readl_relaxed(PLL_MODE_REG(pll)) & BIT(0);
}
static enum handoff pll_clk_handoff(struct clk *clk)
@@ -166,7 +334,7 @@
* Wait for the PLLs to be initialized and then read their frequency.
*/
do {
- pll_lval = readl_relaxed(pll->mode_reg + 4) & 0x3ff;
+ pll_lval = readl_relaxed(PLL_MODE_REG(pll) + 4) & 0x3ff;
cpu_relax();
udelay(50);
} while (pll_lval == 0);
@@ -191,6 +359,5 @@
.enable = pll_clk_enable,
.disable = pll_clk_disable,
.handoff = pll_clk_handoff,
- .is_local = pll_clk_is_local,
.is_enabled = pll_clk_is_enabled,
};
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index ae0ca17..26bfc68 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -12,6 +12,9 @@
*
*/
+#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PLL_H
+#define __ARCH_ARM_MACH_MSM_CLOCK_PLL_H
+
/**
* enum - For PLL IDs
*/
@@ -37,6 +40,7 @@
unsigned int id;
void __iomem *const mode_reg;
struct clk c;
+ void *const __iomem *base;
};
extern struct clk_ops clk_pll_ops;
@@ -50,3 +54,67 @@
* msm_shared_pll_control_init() - Initialize shared pll control structure
*/
void msm_shared_pll_control_init(void);
+
+/**
+ * struct pll_vote_clk - phase locked loop (HW voteable)
+ * @soft_vote: soft voting variable for multiple PLL software instances
+ * @soft_vote_mask: soft voting mask for multiple PLL software instances
+ * @en_reg: enable register
+ * @en_mask: ORed with @en_reg to enable the clock
+ * @status_mask: ANDed with @status_reg to determine if PLL is active.
+ * @status_reg: status register
+ * @parent: clock source
+ * @c: clk
+ */
+struct pll_vote_clk {
+ u32 *soft_vote;
+ const u32 soft_vote_mask;
+ void __iomem *const en_reg;
+ const u32 en_mask;
+ void __iomem *const status_reg;
+ const u32 status_mask;
+
+ struct clk *parent;
+ struct clk c;
+ void *const __iomem *base;
+};
+
+extern struct clk_ops clk_ops_pll_vote;
+
+static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
+{
+ return container_of(clk, struct pll_vote_clk, c);
+}
+
+/**
+ * struct pll_clk - phase locked loop
+ * @mode_reg: enable register
+ * @parent: clock source
+ * @c: clk
+ */
+struct pll_clk {
+ void __iomem *const mode_reg;
+
+ struct clk *parent;
+ struct clk c;
+ void *const __iomem *base;
+};
+
+extern struct clk_ops clk_ops_local_pll;
+
+static inline struct pll_clk *to_pll_clk(struct clk *clk)
+{
+ return container_of(clk, struct pll_clk, c);
+}
+
+int sr_pll_clk_enable(struct clk *clk);
+
+/*
+ * PLL vote clock APIs
+ */
+int pll_vote_clk_enable(struct clk *clk);
+void pll_vote_clk_disable(struct clk *clk);
+struct clk *pll_vote_clk_get_parent(struct clk *clk);
+int pll_vote_clk_is_enabled(struct clk *clk);
+
+#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 09bf036..fb5b580 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -132,8 +132,11 @@
{
int ret = 0;
struct clk *parent;
+
if (!clk)
return 0;
+ if (IS_ERR(clk))
+ return -EINVAL;
mutex_lock(&clk->prepare_lock);
if (clk->prepare_count == 0) {
@@ -174,6 +177,8 @@
if (!clk)
return 0;
+ if (IS_ERR(clk))
+ return -EINVAL;
spin_lock_irqsave(&clk->lock, flags);
if (WARN(!clk->warned && !clk->prepare_count,
@@ -230,7 +235,7 @@
{
unsigned long flags;
- if (!clk)
+ if (IS_ERR_OR_NULL(clk))
return;
spin_lock_irqsave(&clk->lock, flags);
@@ -259,7 +264,7 @@
void clk_unprepare(struct clk *clk)
{
- if (!clk)
+ if (IS_ERR_OR_NULL(clk))
return;
mutex_lock(&clk->prepare_lock);
@@ -290,6 +295,9 @@
int clk_reset(struct clk *clk, enum clk_reset_action action)
{
+ if (IS_ERR_OR_NULL(clk))
+ return -EINVAL;
+
if (!clk->ops->reset)
return -ENOSYS;
@@ -299,6 +307,9 @@
unsigned long clk_get_rate(struct clk *clk)
{
+ if (IS_ERR_OR_NULL(clk))
+ return 0;
+
if (!clk->ops->get_rate)
return clk->rate;
@@ -311,6 +322,9 @@
unsigned long start_rate, flags;
int rc;
+ if (IS_ERR_OR_NULL(clk))
+ return -EINVAL;
+
if (!clk->ops->set_rate)
return -ENOSYS;
@@ -347,6 +361,9 @@
long clk_round_rate(struct clk *clk, unsigned long rate)
{
+ if (IS_ERR_OR_NULL(clk))
+ return -EINVAL;
+
if (!clk->ops->round_rate)
return -ENOSYS;
@@ -356,6 +373,9 @@
int clk_set_max_rate(struct clk *clk, unsigned long rate)
{
+ if (IS_ERR_OR_NULL(clk))
+ return -EINVAL;
+
if (!clk->ops->set_max_rate)
return -ENOSYS;
@@ -374,6 +394,9 @@
struct clk *clk_get_parent(struct clk *clk)
{
+ if (IS_ERR_OR_NULL(clk))
+ return NULL;
+
if (!clk->ops->get_parent)
return NULL;
@@ -383,7 +406,7 @@
int clk_set_flags(struct clk *clk, unsigned long flags)
{
- if (clk == NULL || IS_ERR(clk))
+ if (IS_ERR_OR_NULL(clk))
return -EINVAL;
if (!clk->ops->set_flags)
return -ENOSYS;
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 60be654..d5a3e8f 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -37,6 +37,12 @@
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
+/*
+ * Bit manipulation macros
+ */
+#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
+#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
+
#define MAX_VDD_LEVELS 4
/**
@@ -146,14 +152,12 @@
extern struct clock_init_data msm9615_clock_init_data;
extern struct clock_init_data apq8064_clock_init_data;
-extern struct clock_init_data apq8064_dummy_clock_init_data;
extern struct clock_init_data fsm9xxx_clock_init_data;
extern struct clock_init_data msm7x01a_clock_init_data;
extern struct clock_init_data msm7x27_clock_init_data;
extern struct clock_init_data msm7x27a_clock_init_data;
extern struct clock_init_data msm7x30_clock_init_data;
extern struct clock_init_data msm8960_clock_init_data;
-extern struct clock_init_data msm8960_dummy_clock_init_data;
extern struct clock_init_data msm8x60_clock_init_data;
extern struct clock_init_data qds8x50_clock_init_data;
extern struct clock_init_data msm8625_dummy_clock_init_data;
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 5d6a3ae..aa62810 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -440,6 +440,16 @@
.id = 0x3005,
};
+struct platform_device apq_cpudai_slim_4_rx = {
+ .name = "msm-dai-q6",
+ .id = 0x4008,
+};
+
+struct platform_device apq_cpudai_slim_4_tx = {
+ .name = "msm-dai-q6",
+ .id = 0x4009,
+};
+
/*
* Machine specific data for AUX PCM Interface
* which the driver will be unware of.
@@ -551,6 +561,11 @@
.id = 0x4003,
};
+struct platform_device apq_cpudai_slimbus_2_tx = {
+ .name = "msm-dai-q6",
+ .id = 0x4005,
+};
+
static struct resource resources_ssbi_pmic1[] = {
{
.start = MSM_PMIC1_SSBI_CMD_PHYS,
@@ -1528,199 +1543,6 @@
};
unsigned apq8064_num_fs_devices = ARRAY_SIZE(apq8064_fs_devices);
-static struct clk_lookup msm_clocks_8064_dummy[] = {
- CLK_DUMMY("pll2", PLL2, NULL, 0),
- CLK_DUMMY("pll8", PLL8, NULL, 0),
- CLK_DUMMY("pll4", PLL4, NULL, 0),
-
- CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
- CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
- CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
- CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
- CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
- CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
- CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
- CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
- CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
- CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
- CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
- CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
- CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
- CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
- CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
- CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
-
- CLK_DUMMY("core_clk", GSBI1_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI2_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI3_UART_CLK,
- NULL, OFF),
- CLK_DUMMY("core_clk", GSBI4_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI5_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI6_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI7_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI8_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI9_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI10_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI11_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI12_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI1_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI2_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI3_QUP_CLK, "qup_i2c.3", OFF),
- CLK_DUMMY("core_clk", GSBI4_QUP_CLK, "qup_i2c.4", OFF),
- CLK_DUMMY("core_clk", GSBI5_QUP_CLK, "spi_qsd.0", OFF),
- CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
- CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", PRNG_CLK, "msm_rng.0", OFF),
- CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC2_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
- CLK_DUMMY("ref_clk", TSIF_REF_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_HS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_HS3_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_HS4_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("phy_clk", USB_PHY0_CLK, NULL, OFF),
- CLK_DUMMY("src_clk", USB_FS1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_FS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", CE2_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", CE1_CORE_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", CE3_CORE_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", CE3_P_CLK, NULL, OFF),
- CLK_DUMMY("pcie_pclk", PCIE_P_CLK, NULL, OFF),
- CLK_DUMMY("pcie_alt_ref_clk", PCIE_ALT_REF_CLK, NULL, OFF),
- CLK_DUMMY("sata_rxoob_clk", SATA_RXOOB_CLK, NULL, OFF),
- CLK_DUMMY("sata_pmalive_clk", SATA_PMALIVE_CLK, NULL, OFF),
- CLK_DUMMY("ref_clk", SATA_PHY_REF_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI2_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI3_P_CLK, "qup_i2c.3", OFF),
- CLK_DUMMY("iface_clk", GSBI4_P_CLK, "qup_i2c.4", OFF),
- CLK_DUMMY("iface_clk", GSBI5_P_CLK, "spi_qsd.0", OFF),
- CLK_DUMMY("iface_clk", GSBI6_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI7_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", TSIF_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_FS1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_HS1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_HS3_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_HS4_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC2_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", ADM0_CLK, "msm_dmov", OFF),
- CLK_DUMMY("iface_clk", ADM0_P_CLK, "msm_dmov", OFF),
- CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
- CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
- CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
- CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
- CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
- CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
- CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
- CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
- CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
- CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
- CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
- CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
- CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, NULL, OFF),
- CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, NULL, OFF),
- CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, NULL, OFF),
- CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", VCAP_CLK, NULL, OFF),
- CLK_DUMMY("npl_clk", VCAP_NPL_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GFX3D_CLK, "kgsl-3d0.0", OFF),
- CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
- CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
- CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
- CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
- CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", ROT_CLK, NULL, OFF),
- CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
- CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
- CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
- CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
- CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", HDMI_APP_CLK, "hdmi_msm.1", OFF),
- CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
- CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
- CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
- CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
- CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
- CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
- CLK_DUMMY("bus_clk", ROT_AXI_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
- CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
- CLK_DUMMY("bus_clk", GFX3D_AXI_CLK, NULL, OFF),
- CLK_DUMMY("vcap_axi_clk", VCAP_AXI_CLK, NULL, OFF),
- CLK_DUMMY("vcap_ahb_clk", VCAP_AHB_CLK, NULL, OFF),
- CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
- CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
- CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, NULL, OFF),
- CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, NULL, OFF),
- CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, NULL, OFF),
- CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, NULL, OFF),
- CLK_DUMMY("lvds_clk", LVDS_CLK, NULL, OFF),
- CLK_DUMMY("mdp_p2clk", MDP_P2CLK, NULL, OFF),
- CLK_DUMMY("dsi2_pixel_clk", DSI2_PIXEL_CLK, NULL, OFF),
- CLK_DUMMY("lvds_ref_clk", LVDS_REF_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GFX3D_P_CLK, "kgsl-3d0.0", OFF),
- CLK_DUMMY("master_iface_clk", HDMI_M_P_CLK, "hdmi_msm.1", OFF),
- CLK_DUMMY("slave_iface_clk", HDMI_S_P_CLK, "hdmi_msm.1", OFF),
- CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
- CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
- CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
- CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SMMU_P_CLK, "msm_smmu", OFF),
- CLK_DUMMY("iface_clk", ROT_P_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
- CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
- CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
- CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
-
- CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
- CLK_DUMMY("core_clk", DFAB_USB_HS_CLK, NULL, 0),
- CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
- CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0),
- CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0),
- CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0),
- CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
- CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
- CLK_DUMMY("mem_clk", EBI1_ADM_CLK, "msm_dmov", 0),
- CLK_DUMMY("ce3_core_src_clk", CE3_SRC_CLK, "qce.0", OFF),
- CLK_DUMMY("ce3_core_src_clk", CE3_SRC_CLK, "qcrypto.0", OFF),
- CLK_DUMMY("core_clk", CE3_CORE_CLK, "qce.0", OFF),
- CLK_DUMMY("core_clk", CE3_CORE_CLK, "qcrypto.0", OFF),
- CLK_DUMMY("iface_clk", CE3_P_CLK, "qce0.0", OFF),
- CLK_DUMMY("iface_clk", CE3_P_CLK, "qcrypto.0", OFF),
-};
-
-struct clock_init_data apq8064_dummy_clock_init_data __initdata = {
- .table = msm_clocks_8064_dummy,
- .size = ARRAY_SIZE(msm_clocks_8064_dummy),
-};
-
struct msm_rpm_platform_data apq8064_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
@@ -2253,6 +2075,109 @@
},
};
+#ifdef CONFIG_MSM_VCAP
+#define VCAP_HW_BASE 0x05900000
+
+static struct msm_bus_vectors vcap_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_CAP,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
+
+static struct msm_bus_vectors vcap_480_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_CAP,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 1280 * 720 * 3 * 60 / 16,
+ .ib = 1280 * 720 * 3 * 60 / 16 * 1.5,
+ },
+};
+
+static struct msm_bus_vectors vcap_720_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_CAP,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 1280 * 720 * 3 * 60 / 16,
+ .ib = 1280 * 720 * 3 * 60 / 16 * 1.5,
+ },
+};
+
+static struct msm_bus_vectors vcap_1080_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_CAP,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 1920 * 1080 * 3 * 60 / 16,
+ .ib = 1920 * 1080 * 3 * 60 / 16 * 1.5,
+ },
+};
+
+static struct msm_bus_paths vcap_bus_usecases[] = {
+ {
+ ARRAY_SIZE(vcap_init_vectors),
+ vcap_init_vectors,
+ },
+ {
+ ARRAY_SIZE(vcap_480_vectors),
+ vcap_480_vectors,
+ },
+ {
+ ARRAY_SIZE(vcap_720_vectors),
+ vcap_720_vectors,
+ },
+ {
+ ARRAY_SIZE(vcap_1080_vectors),
+ vcap_1080_vectors,
+ },
+};
+
+static struct msm_bus_scale_pdata vcap_axi_client_pdata = {
+ vcap_bus_usecases,
+ ARRAY_SIZE(vcap_bus_usecases),
+};
+
+static struct resource msm_vcap_resources[] = {
+ {
+ .name = "vcap",
+ .start = VCAP_HW_BASE,
+ .end = VCAP_HW_BASE + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "vcap",
+ .start = VCAP_VC,
+ .end = VCAP_VC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static unsigned vcap_gpios[] = {
+ 2, 3, 4, 5, 6, 7, 8, 9, 10,
+ 11, 12, 13, 18, 19, 20, 21,
+ 22, 23, 24, 25, 26, 80, 82,
+ 83, 84, 85, 86, 87,
+};
+
+static struct vcap_platform_data vcap_pdata = {
+ .gpios = vcap_gpios,
+ .num_gpios = ARRAY_SIZE(vcap_gpios),
+ .bus_client_pdata = &vcap_axi_client_pdata
+};
+
+struct platform_device msm8064_device_vcap = {
+ .name = "msm_vcap",
+ .id = 0,
+ .resource = msm_vcap_resources,
+ .num_resources = ARRAY_SIZE(msm_vcap_resources),
+ .dev = {
+ .platform_data = &vcap_pdata,
+ },
+};
+#endif
+
static struct resource msm_cache_erp_resources[] = {
{
.name = "l1_irq",
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 375aa8d..894c13f 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -74,6 +74,7 @@
#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
#define MSM_UART6DM_PHYS (MSM_GSBI6_PHYS + 0x40000)
#define MSM_UART8DM_PHYS (MSM_GSBI8_PHYS + 0x40000)
+#define MSM_UART9DM_PHYS (MSM_GSBI9_PHYS + 0x40000)
/* GSBI QUP devices */
#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
@@ -283,6 +284,52 @@
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
+/*
+ * GSBI 9 used into UARTDM Mode
+ * For 8960 Fusion 2.2 Primary IPC
+ */
+static struct resource msm_uart_dm9_resources[] = {
+ {
+ .start = MSM_UART9DM_PHYS,
+ .end = MSM_UART9DM_PHYS + PAGE_SIZE - 1,
+ .name = "uartdm_resource",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = GSBI9_UARTDM_IRQ,
+ .end = GSBI9_UARTDM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MSM_GSBI9_PHYS,
+ .end = MSM_GSBI9_PHYS + 4 - 1,
+ .name = "gsbi_resource",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DMOV_HSUART_GSBI9_TX_CHAN,
+ .end = DMOV_HSUART_GSBI9_RX_CHAN,
+ .name = "uartdm_channels",
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMOV_HSUART_GSBI9_TX_CRCI,
+ .end = DMOV_HSUART_GSBI9_RX_CRCI,
+ .name = "uartdm_crci",
+ .flags = IORESOURCE_DMA,
+ },
+};
+static u64 msm_uart_dm9_dma_mask = DMA_BIT_MASK(32);
+struct platform_device msm_device_uart_dm9 = {
+ .name = "msm_serial_hs",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(msm_uart_dm9_resources),
+ .resource = msm_uart_dm9_resources,
+ .dev = {
+ .dma_mask = &msm_uart_dm9_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
static struct resource resources_uart_gsbi5[] = {
{
@@ -1790,6 +1837,11 @@
.id = 0x4001,
};
+struct platform_device msm8960_cpudai_slimbus_2_tx = {
+ .name = "msm-dai-q6",
+ .id = 0x4005,
+};
+
struct platform_device msm_cpudai_hdmi_rx = {
.name = "msm-dai-q6-hdmi",
.id = 8,
@@ -2284,200 +2336,6 @@
};
#endif
-static struct clk_lookup msm_clocks_8960_dummy[] = {
- CLK_DUMMY("pll2", PLL2, NULL, 0),
- CLK_DUMMY("pll8", PLL8, NULL, 0),
- CLK_DUMMY("pll4", PLL4, NULL, 0),
-
- CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
- CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
- CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
- CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
- CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
- CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
- CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
- CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
- CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
- CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
- CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
- CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
- CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
- CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
- CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
- CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
-
- CLK_DUMMY("core_clk", GSBI1_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI2_UART_CLK, "msm_serial_hsl.0", OFF),
- CLK_DUMMY("core_clk", GSBI3_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI4_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI5_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI6_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI7_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI8_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI9_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI10_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI11_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI12_UART_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI1_QUP_CLK, "spi_qsd.0", OFF),
- CLK_DUMMY("core_clk", GSBI2_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI3_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI4_QUP_CLK, "qup_i2c.4", OFF),
- CLK_DUMMY("core_clk", GSBI5_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI8_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI9_QUP_CLK, "qup_i2c.0", OFF),
- CLK_DUMMY("core_clk", GSBI10_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI11_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GSBI12_QUP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
- CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC2_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", SDC5_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", TSIF_REF_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_HS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("phy_clk", USB_PHY0_CLK, NULL, OFF),
- CLK_DUMMY("src_clk", USB_FS1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_FS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
- CLK_DUMMY("src_clk", USB_FS2_SRC_CLK, NULL, OFF),
- CLK_DUMMY("alt_core_clk", USB_FS2_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("sys_clk", USB_FS2_SYS_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", CE2_CLK, "qce.0", OFF),
- CLK_DUMMY("core_clk", CE1_CORE_CLK, "qce.0", OFF),
- CLK_DUMMY("iface_clk", GSBI1_P_CLK, "spi_qsd.0", OFF),
- CLK_DUMMY("iface_clk", GSBI2_P_CLK,
- "msm_serial_hsl.0", OFF),
- CLK_DUMMY("iface_clk", GSBI3_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI4_P_CLK, "qup_i2c.4", OFF),
- CLK_DUMMY("iface_clk", GSBI5_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI6_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI7_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI8_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI9_P_CLK, "qup_i2c.0", OFF),
- CLK_DUMMY("iface_clk", GSBI10_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI11_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI12_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GSBI12_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", TSIF_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_FS1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_FS2_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", USB_HS1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC2_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SDC5_P_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", ADM0_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", ADM0_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
- CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
- CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
- CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
- CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
- CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
- CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
- CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
- CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
- CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
- CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
- CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
- CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, "mipi_dsi.1", OFF),
- CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, "mipi_dsi.2", OFF),
- CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, "mipi_dsi.1", OFF),
- CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, "mipi_dsi.2", OFF),
- CLK_DUMMY("core_clk", GFX2D0_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GFX2D1_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", GFX3D_CLK, NULL, OFF),
- CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
- CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
- CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
- CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
- CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", ROT_CLK, NULL, OFF),
- CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
- CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
- CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
- CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
- CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
- CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
- CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
- CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
- CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
- CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
- CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
- CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
- CLK_DUMMY("bus_clk", ROT_AXI_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
- CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
- CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
- CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
- CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, "mipi_dsi.1", OFF),
- CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, "mipi_dsi.1", OFF),
- CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, "mipi_dsi.2", OFF),
- CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, "mipi_dsi.2", OFF),
- CLK_DUMMY("iface_clk", GFX2D0_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GFX2D1_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", GFX3D_P_CLK, NULL, OFF),
- CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL, OFF),
- CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL, OFF),
- CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
- CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
- CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
- CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", SMMU_P_CLK, NULL, OFF),
- CLK_DUMMY("iface_clk", ROT_P_CLK, NULL, OFF),
- CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
- CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
- CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
- CLK_DUMMY("core_clk", JPEGD_AXI_CLK, NULL, 0),
- CLK_DUMMY("core_clk", VFE_AXI_CLK, NULL, 0),
- CLK_DUMMY("core_clk", VCODEC_AXI_CLK, NULL, 0),
- CLK_DUMMY("core_clk", GFX3D_CLK, NULL, 0),
- CLK_DUMMY("core_clk", GFX2D0_CLK, NULL, 0),
- CLK_DUMMY("core_clk", GFX2D1_CLK, NULL, 0),
-
- CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
- CLK_DUMMY("core_clk", DFAB_USB_HS_CLK, "msm_otg", NULL),
- CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, "msm_sdcc.1", 0),
- CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, "msm_sdcc.2", 0),
- CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, "msm_sdcc.3", 0),
- CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, "msm_sdcc.4", 0),
- CLK_DUMMY("bus_clk", DFAB_SDC5_CLK, "msm_sdcc.5", 0),
- CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
- CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
-};
-
-struct clock_init_data msm8960_dummy_clock_init_data __initdata = {
- .table = msm_clocks_8960_dummy,
- .size = ARRAY_SIZE(msm_clocks_8960_dummy),
-};
-
#define LPASS_SLIMBUS_PHYS 0x28080000
#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
#define LPASS_SLIMBUS_SLEW (MSM8960_TLMM_PHYS + 0x207C)
@@ -2796,7 +2654,7 @@
.bus_freq = 0,
},
},
- .init_level = 0,
+ .init_level = 1,
.num_levels = ARRAY_SIZE(grp3d_freq) + 1,
.set_grp_async = NULL,
.idle_timeout = HZ/12,
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 608ca27..614f6ff 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -1591,7 +1591,7 @@
static struct dsps_clk_info dsps_clks[] = {
{
- .name = "ppss_pclk",
+ .name = "iface_clk",
.rate = 0, /* no rate just on/off */
},
{
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index f110a33..c396faa 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -52,6 +52,7 @@
extern struct platform_device msm_device_uart_dm12;
extern struct platform_device *msm_device_uart_gsbi9;
extern struct platform_device msm_device_uart_dm6;
+extern struct platform_device msm_device_uart_dm9;
extern struct platform_device msm8960_device_uart_gsbi2;
extern struct platform_device msm8960_device_uart_gsbi5;
@@ -170,6 +171,9 @@
extern struct platform_device msm_device_tssc;
extern struct platform_device msm_rotator_device;
+#ifdef CONFIG_MSM_VCAP
+extern struct platform_device msm8064_device_vcap;
+#endif
#ifdef CONFIG_MSM_BUS_SCALING
extern struct msm_bus_scale_pdata rotator_bus_scale_pdata;
@@ -195,6 +199,7 @@
extern struct platform_device msm_cpudai0;
extern struct platform_device msm_cpudai1;
extern struct platform_device mpq_cpudai_sec_i2s_rx;
+extern struct platform_device msm8960_cpudai_slimbus_2_tx;
extern struct platform_device msm_cpudai_hdmi_rx;
extern struct platform_device msm_cpudai_bt_rx;
extern struct platform_device msm_cpudai_bt_tx;
@@ -256,6 +261,9 @@
extern struct platform_device apq_cpudai_stub;
extern struct platform_device apq_cpudai_slimbus_1_rx;
extern struct platform_device apq_cpudai_slimbus_1_tx;
+extern struct platform_device apq_cpudai_slimbus_2_tx;
+extern struct platform_device apq_cpudai_slim_4_rx;
+extern struct platform_device apq_cpudai_slim_4_tx;
extern struct platform_device *msm_footswitch_devices[];
extern unsigned msm_num_footswitch_devices;
diff --git a/arch/arm/mach-msm/footswitch-8x60.c b/arch/arm/mach-msm/footswitch-8x60.c
index d5a1d3f..c92c049 100644
--- a/arch/arm/mach-msm/footswitch-8x60.c
+++ b/arch/arm/mach-msm/footswitch-8x60.c
@@ -483,12 +483,18 @@
{ 0 }
};
-static struct clk_data gfx3d_clks[] = {
+static struct clk_data gfx3d_8660_clks[] = {
{ .name = "core_clk", .reset_rate = 27000000 },
{ .name = "iface_clk" },
{ 0 }
};
+static struct clk_data gfx3d_8064_clks[] = {
+ { .name = "core_clk", .reset_rate = 27000000 },
+ { .name = "iface_clk" },
+ { .name = "bus_clk" },
+ { 0 }
+};
static struct clk_data ijpeg_clks[] = {
{ .name = "core_clk" },
@@ -579,7 +585,7 @@
GFX2D1_GFS_CTL_REG, 31, gfx2d1_clks,
MSM_BUS_MASTER_GRAPHICS_2D_CORE1, 0),
FOOTSWITCH(FS_GFX3D, "fs_gfx3d", &standard_fs_ops,
- GFX3D_GFS_CTL_REG, 31, gfx3d_clks,
+ GFX3D_GFS_CTL_REG, 31, gfx3d_8660_clks,
MSM_BUS_MASTER_GRAPHICS_3D, 0),
FOOTSWITCH(FS_IJPEG, "fs_ijpeg", &standard_fs_ops,
GEMINI_GFS_CTL_REG, 31, ijpeg_clks,
@@ -625,10 +631,13 @@
if (pdev->id == FS_MDP) {
if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_apq8064())
fs->clk_data = mdp_8960_clks;
- else if (cpu_is_msm8x60())
- fs->clk_data = mdp_8660_clks;
else
- BUG();
+ fs->clk_data = mdp_8660_clks;
+ } else if (pdev->id == FS_GFX3D) {
+ if (cpu_is_msm8930() || cpu_is_apq8064())
+ fs->clk_data = gfx3d_8064_clks;
+ else
+ fs->clk_data = gfx3d_8660_clks;
}
for (clock = fs->clk_data; clock->name; clock++) {
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index d1766a3..4e21a86 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -490,6 +490,12 @@
.irq_disable = msm_gpio_irq_disable,
};
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key msm_gpio_lock_class;
+
static int __devinit msm_gpio_probe(void)
{
int i, irq, ret;
@@ -504,6 +510,7 @@
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
+ irq_set_lockdep_class(irq, &msm_gpio_lock_class);
irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/mach-msm/hsic_sysmon.c b/arch/arm/mach-msm/hsic_sysmon.c
new file mode 100644
index 0000000..2dedbac
--- /dev/null
+++ b/arch/arm/mach-msm/hsic_sysmon.c
@@ -0,0 +1,449 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* add additional information to our printk's */
+#define pr_fmt(fmt) "%s: " fmt "\n", __func__
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/usb.h>
+#include <linux/debugfs.h>
+
+#include "hsic_sysmon.h"
+#include "sysmon.h"
+
+#define DRIVER_DESC "HSIC System monitor driver"
+
+enum hsic_sysmon_op {
+ HSIC_SYSMON_OP_READ = 0,
+ HSIC_SYSMON_OP_WRITE,
+ NUM_OPS
+};
+
+struct hsic_sysmon {
+ struct usb_device *udev;
+ struct usb_interface *ifc;
+ __u8 in_epaddr;
+ __u8 out_epaddr;
+ unsigned int pipe[NUM_OPS];
+ struct kref kref;
+ struct platform_device pdev;
+ int id;
+
+ /* debugging counters */
+ atomic_t dbg_bytecnt[NUM_OPS];
+ atomic_t dbg_pending[NUM_OPS];
+};
+static struct hsic_sysmon *hsic_sysmon_devices[NUM_HSIC_SYSMON_DEVS];
+
+static void hsic_sysmon_delete(struct kref *kref)
+{
+ struct hsic_sysmon *hs = container_of(kref, struct hsic_sysmon, kref);
+
+ usb_put_dev(hs->udev);
+ hsic_sysmon_devices[hs->id] = NULL;
+ kfree(hs);
+}
+
+/**
+ * hsic_sysmon_open() - Opens the system monitor bridge.
+ * @id: the HSIC system monitor device to open
+ *
+ * This should only be called after the platform_device "sys_mon" with id
+ * SYSMON_SS_EXT_MODEM has been added. The simplest way to do that is to
+ * register a platform_driver and its probe will be called when the HSIC
+ * device is ready.
+ */
+int hsic_sysmon_open(enum hsic_sysmon_device_id id)
+{
+ struct hsic_sysmon *hs;
+
+ if (id >= NUM_HSIC_SYSMON_DEVS) {
+ pr_err("invalid dev id(%d)", id);
+ return -ENODEV;
+ }
+
+ hs = hsic_sysmon_devices[id];
+ if (!hs) {
+ pr_err("dev is null");
+ return -ENODEV;
+ }
+
+ kref_get(&hs->kref);
+
+ return 0;
+}
+EXPORT_SYMBOL(hsic_sysmon_open);
+
+/**
+ * hsic_sysmon_close() - Closes the system monitor bridge.
+ * @id: the HSIC system monitor device to close
+ */
+void hsic_sysmon_close(enum hsic_sysmon_device_id id)
+{
+ struct hsic_sysmon *hs;
+
+ if (id >= NUM_HSIC_SYSMON_DEVS) {
+ pr_err("invalid dev id(%d)", id);
+ return;
+ }
+
+ hs = hsic_sysmon_devices[id];
+ kref_put(&hs->kref, hsic_sysmon_delete);
+}
+EXPORT_SYMBOL(hsic_sysmon_close);
+
+/**
+ * hsic_sysmon_readwrite() - Common function to send read/write over HSIC
+ */
+static int hsic_sysmon_readwrite(enum hsic_sysmon_device_id id, void *data,
+ size_t len, size_t *actual_len, int timeout,
+ enum hsic_sysmon_op op)
+{
+ struct hsic_sysmon *hs;
+ int ret;
+ const char *opstr = (op == HSIC_SYSMON_OP_READ) ?
+ "read" : "write";
+
+ pr_debug("%s: id:%d, data len:%d, timeout:%d", opstr, id, len, timeout);
+
+ if (id >= NUM_HSIC_SYSMON_DEVS) {
+ pr_err("invalid dev id(%d)", id);
+ return -ENODEV;
+ }
+
+ if (!len) {
+ pr_err("length(%d) must be greater than 0", len);
+ return -EINVAL;
+ }
+
+ hs = hsic_sysmon_devices[id];
+ if (!hs) {
+ pr_err("device was not opened");
+ return -ENODEV;
+ }
+
+ if (!hs->ifc) {
+ dev_err(&hs->udev->dev, "can't %s, device disconnected\n",
+ opstr);
+ return -ENODEV;
+ }
+
+ ret = usb_autopm_get_interface(hs->ifc);
+ if (ret < 0) {
+ dev_err(&hs->udev->dev, "can't %s, autopm_get failed:%d\n",
+ opstr, ret);
+ return ret;
+ }
+
+ atomic_inc(&hs->dbg_pending[op]);
+
+ ret = usb_bulk_msg(hs->udev, hs->pipe[op], data, len, actual_len,
+ timeout);
+
+ atomic_dec(&hs->dbg_pending[op]);
+
+ if (ret)
+ dev_err(&hs->udev->dev,
+ "can't %s, usb_bulk_msg failed, err:%d\n", opstr, ret);
+ else
+ atomic_add(*actual_len, &hs->dbg_bytecnt[op]);
+
+ usb_autopm_put_interface(hs->ifc);
+ return ret;
+}
+
+/**
+ * hsic_sysmon_read() - Read data from the HSIC sysmon interface.
+ * @id: the HSIC system monitor device to open
+ * @data: pointer to caller-allocated buffer to fill in
+ * @len: length in bytes of the buffer
+ * @actual_len: pointer to a location to put the actual length read
+ * in bytes
+ * @timeout: time in msecs to wait for the message to complete before
+ * timing out (if 0 the wait is forever)
+ *
+ * Context: !in_interrupt ()
+ *
+ * Synchronously reads data from the HSIC interface. The call will return
+ * after the read has completed, encountered an error, or timed out. Upon
+ * successful return actual_len will reflect the number of bytes read.
+ *
+ * If successful, it returns 0, otherwise a negative error number. The number
+ * of actual bytes transferred will be stored in the actual_len paramater.
+ */
+int hsic_sysmon_read(enum hsic_sysmon_device_id id, char *data, size_t len,
+ size_t *actual_len, int timeout)
+{
+ return hsic_sysmon_readwrite(id, data, len, actual_len,
+ timeout, HSIC_SYSMON_OP_READ);
+}
+EXPORT_SYMBOL(hsic_sysmon_read);
+
+/**
+ * hsic_sysmon_write() - Write data to the HSIC sysmon interface.
+ * @id: the HSIC system monitor device to open
+ * @data: pointer to caller-allocated buffer to write
+ * @len: length in bytes of the data in buffer to write
+ * @actual_len: pointer to a location to put the actual length written
+ * in bytes
+ * @timeout: time in msecs to wait for the message to complete before
+ * timing out (if 0 the wait is forever)
+ *
+ * Context: !in_interrupt ()
+ *
+ * Synchronously writes data to the HSIC interface. The call will return
+ * after the write has completed, encountered an error, or timed out. Upon
+ * successful return actual_len will reflect the number of bytes written.
+ *
+ * If successful, it returns 0, otherwise a negative error number. The number
+ * of actual bytes transferred will be stored in the actual_len paramater.
+ */
+int hsic_sysmon_write(enum hsic_sysmon_device_id id, const char *data,
+ size_t len, int timeout)
+{
+ size_t actual_len;
+ return hsic_sysmon_readwrite(id, (void *)data, len, &actual_len,
+ timeout, HSIC_SYSMON_OP_WRITE);
+}
+EXPORT_SYMBOL(hsic_sysmon_write);
+
+#if defined(CONFIG_DEBUG_FS)
+#define DEBUG_BUF_SIZE 512
+static ssize_t sysmon_debug_read_stats(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char *buf;
+ int i, ret = 0;
+
+ buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ for (i = 0; i < NUM_HSIC_SYSMON_DEVS; i++) {
+ struct hsic_sysmon *hs = hsic_sysmon_devices[i];
+ if (!hs)
+ continue;
+
+ ret += scnprintf(buf, DEBUG_BUF_SIZE,
+ "---HSIC Sysmon #%d---\n"
+ "epin:%d, epout:%d\n"
+ "bytes to host: %d\n"
+ "bytes to mdm: %d\n"
+ "pending reads: %d\n"
+ "pending writes: %d\n",
+ i, hs->in_epaddr & ~0x80, hs->out_epaddr,
+ atomic_read(
+ &hs->dbg_bytecnt[HSIC_SYSMON_OP_READ]),
+ atomic_read(
+ &hs->dbg_bytecnt[HSIC_SYSMON_OP_WRITE]),
+ atomic_read(
+ &hs->dbg_pending[HSIC_SYSMON_OP_READ]),
+ atomic_read(
+ &hs->dbg_pending[HSIC_SYSMON_OP_WRITE])
+ );
+ }
+
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
+ kfree(buf);
+ return ret;
+}
+
+static ssize_t sysmon_debug_reset_stats(struct file *file,
+ const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int i;
+
+ for (i = 0; i < NUM_HSIC_SYSMON_DEVS; i++) {
+ struct hsic_sysmon *hs = hsic_sysmon_devices[i];
+ if (hs) {
+ atomic_set(&hs->dbg_bytecnt[HSIC_SYSMON_OP_READ], 0);
+ atomic_set(&hs->dbg_bytecnt[HSIC_SYSMON_OP_WRITE], 0);
+ atomic_set(&hs->dbg_pending[HSIC_SYSMON_OP_READ], 0);
+ atomic_set(&hs->dbg_pending[HSIC_SYSMON_OP_WRITE], 0);
+ }
+ }
+
+ return count;
+}
+
+const struct file_operations sysmon_stats_ops = {
+ .read = sysmon_debug_read_stats,
+ .write = sysmon_debug_reset_stats,
+};
+
+static struct dentry *dent;
+
+static void hsic_sysmon_debugfs_init(void)
+{
+ struct dentry *dfile;
+
+ dent = debugfs_create_dir("hsic_sysmon", 0);
+ if (IS_ERR(dent))
+ return;
+
+ dfile = debugfs_create_file("status", 0444, dent, 0, &sysmon_stats_ops);
+ if (!dfile || IS_ERR(dfile))
+ debugfs_remove(dent);
+}
+
+static void hsic_sysmon_debugfs_cleanup(void)
+{
+ if (dent) {
+ debugfs_remove_recursive(dent);
+ dent = NULL;
+ }
+}
+#else
+static inline void hsic_sysmon_debugfs_init(void) { }
+static inline void hsic_sysmon_debugfs_cleanup(void) { }
+#endif
+
+static int
+hsic_sysmon_probe(struct usb_interface *ifc, const struct usb_device_id *id)
+{
+ struct hsic_sysmon *hs;
+ struct usb_host_interface *ifc_desc;
+ struct usb_endpoint_descriptor *ep_desc;
+ int i;
+ int ret = -ENOMEM;
+ __u8 ifc_num;
+
+ pr_debug("id:%lu", id->driver_info);
+
+ ifc_num = ifc->cur_altsetting->desc.bInterfaceNumber;
+
+ /* is this the interface we're looking for? */
+ if (ifc_num != id->driver_info)
+ return -ENODEV;
+
+ hs = kzalloc(sizeof(*hs), GFP_KERNEL);
+ if (!hs) {
+ pr_err("unable to allocate hsic_sysmon");
+ return -ENOMEM;
+ }
+
+ hs->udev = usb_get_dev(interface_to_usbdev(ifc));
+ hs->ifc = ifc;
+ kref_init(&hs->kref);
+
+ ifc_desc = ifc->cur_altsetting;
+ for (i = 0; i < ifc_desc->desc.bNumEndpoints; i++) {
+ ep_desc = &ifc_desc->endpoint[i].desc;
+
+ if (!hs->in_epaddr && usb_endpoint_is_bulk_in(ep_desc)) {
+ hs->in_epaddr = ep_desc->bEndpointAddress;
+ hs->pipe[HSIC_SYSMON_OP_READ] =
+ usb_rcvbulkpipe(hs->udev, hs->in_epaddr);
+ }
+
+ if (!hs->out_epaddr && usb_endpoint_is_bulk_out(ep_desc)) {
+ hs->out_epaddr = ep_desc->bEndpointAddress;
+ hs->pipe[HSIC_SYSMON_OP_WRITE] =
+ usb_sndbulkpipe(hs->udev, hs->out_epaddr);
+ }
+ }
+
+ if (!(hs->in_epaddr && hs->out_epaddr)) {
+ pr_err("could not find bulk in and bulk out endpoints");
+ ret = -ENODEV;
+ goto error;
+ }
+
+ hs->id = HSIC_SYSMON_DEV_EXT_MODEM;
+ hsic_sysmon_devices[HSIC_SYSMON_DEV_EXT_MODEM] = hs;
+ usb_set_intfdata(ifc, hs);
+
+ hs->pdev.name = "sys_mon";
+ hs->pdev.id = SYSMON_SS_EXT_MODEM;
+ platform_device_register(&hs->pdev);
+
+ pr_debug("complete");
+
+ return 0;
+
+error:
+ if (hs)
+ kref_put(&hs->kref, hsic_sysmon_delete);
+
+ return ret;
+}
+
+static void hsic_sysmon_disconnect(struct usb_interface *ifc)
+{
+ struct hsic_sysmon *hs = usb_get_intfdata(ifc);
+
+ platform_device_unregister(&hs->pdev);
+ kref_put(&hs->kref, hsic_sysmon_delete);
+ usb_set_intfdata(ifc, NULL);
+}
+
+static int hsic_sysmon_suspend(struct usb_interface *ifc, pm_message_t message)
+{
+ return 0;
+}
+
+static int hsic_sysmon_resume(struct usb_interface *ifc)
+{
+ return 0;
+}
+
+/* driver_info maps to the interface number corresponding to sysmon */
+static const struct usb_device_id hsic_sysmon_ids[] = {
+ { USB_DEVICE(0x5c6, 0x9048), .driver_info = 1, },
+ { USB_DEVICE(0x5c6, 0x904C), .driver_info = 1, },
+ {} /* terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, hsic_sysmon_ids);
+
+static struct usb_driver hsic_sysmon_driver = {
+ .name = "hsic_sysmon",
+ .probe = hsic_sysmon_probe,
+ .disconnect = hsic_sysmon_disconnect,
+ .suspend = hsic_sysmon_suspend,
+ .resume = hsic_sysmon_resume,
+ .id_table = hsic_sysmon_ids,
+ .supports_autosuspend = 1,
+};
+
+static int __init hsic_sysmon_init(void)
+{
+ int ret;
+
+ ret = usb_register(&hsic_sysmon_driver);
+ if (ret) {
+ pr_err("unable to register " DRIVER_DESC);
+ return ret;
+ }
+
+ hsic_sysmon_debugfs_init();
+ return 0;
+}
+
+static void __exit hsic_sysmon_exit(void)
+{
+ hsic_sysmon_debugfs_cleanup();
+ usb_deregister(&hsic_sysmon_driver);
+}
+
+module_init(hsic_sysmon_init);
+module_exit(hsic_sysmon_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/hsic_sysmon.h b/arch/arm/mach-msm/hsic_sysmon.h
new file mode 100644
index 0000000..aa57b93
--- /dev/null
+++ b/arch/arm/mach-msm/hsic_sysmon.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HSIC_SYSMON_H__
+#define __HSIC_SYSMON_H__
+
+/**
+ * enum hsic_sysmon_device_id - Supported HSIC subsystem devices
+ */
+enum hsic_sysmon_device_id {
+ HSIC_SYSMON_DEV_EXT_MODEM,
+ NUM_HSIC_SYSMON_DEVS
+};
+
+#if defined(CONFIG_MSM_HSIC_SYSMON) || defined(CONFIG_MSM_HSIC_SYSMON_MODULE)
+
+extern int hsic_sysmon_open(enum hsic_sysmon_device_id id);
+extern void hsic_sysmon_close(enum hsic_sysmon_device_id id);
+extern int hsic_sysmon_read(enum hsic_sysmon_device_id id, char *data,
+ size_t len, size_t *actual_len, int timeout);
+extern int hsic_sysmon_write(enum hsic_sysmon_device_id id, const char *data,
+ size_t len, int timeout);
+
+#else /* CONFIG_MSM_HSIC_SYSMON || CONFIG_MSM_HSIC_SYSMON_MODULE */
+
+static inline int hsic_sysmon_open(enum hsic_sysmon_device_id id)
+{
+ return -ENODEV;
+}
+
+static inline void hsic_sysmon_close(enum hsic_sysmon_device_id id) { }
+
+static inline int hsic_sysmon_read(enum hsic_sysmon_device_id id, char *data,
+ size_t len, size_t *actual_len, int timeout)
+{
+ return -ENODEV;
+}
+
+static inline int hsic_sysmon_write(enum hsic_sysmon_device_id id,
+ const char *data, size_t len, int timeout)
+{
+ return -ENODEV;
+}
+
+#endif /* CONFIG_MSM_HSIC_SYSMON || CONFIG_MSM_HSIC_SYSMON_MODULE */
+
+#endif /* __HSIC_SYSMON_H__ */
diff --git a/arch/arm/mach-msm/hsic_sysmon_test.c b/arch/arm/mach-msm/hsic_sysmon_test.c
new file mode 100644
index 0000000..9929cb7
--- /dev/null
+++ b/arch/arm/mach-msm/hsic_sysmon_test.c
@@ -0,0 +1,118 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* add additional information to our printk's */
+#define pr_fmt(fmt) "%s: " fmt "\n", __func__
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#include "hsic_sysmon.h"
+#include "sysmon.h"
+
+#define DRIVER_DESC "HSIC System monitor driver test"
+
+#define RD_BUF_SIZE 4096
+
+struct sysmon_test_dev {
+ int buflen;
+ char buf[RD_BUF_SIZE];
+};
+static struct sysmon_test_dev *sysmon_dev;
+
+static ssize_t sysmon_test_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct sysmon_test_dev *dev = sysmon_dev;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ ret = hsic_sysmon_read(HSIC_SYSMON_DEV_EXT_MODEM, dev->buf, RD_BUF_SIZE,
+ &dev->buflen, 3000);
+ if (!ret)
+ return simple_read_from_buffer(ubuf, count, ppos,
+ dev->buf, dev->buflen);
+
+ return 0;
+}
+
+static ssize_t sysmon_test_write(struct file *file, const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct sysmon_test_dev *dev = sysmon_dev;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (copy_from_user(dev->buf, ubuf, count)) {
+ pr_err("error copying for writing");
+ return 0;
+ }
+
+ ret = hsic_sysmon_write(HSIC_SYSMON_DEV_EXT_MODEM,
+ dev->buf, count, 1000);
+ if (ret < 0) {
+ pr_err("error writing to hsic_sysmon");
+ return ret;
+ }
+
+ return count;
+}
+
+static int sysmon_test_open(struct inode *inode, struct file *file)
+{
+ return hsic_sysmon_open(HSIC_SYSMON_DEV_EXT_MODEM);
+}
+
+static int sysmon_test_release(struct inode *inode, struct file *file)
+{
+ hsic_sysmon_close(HSIC_SYSMON_DEV_EXT_MODEM);
+ return 0;
+}
+
+static struct dentry *dfile;
+const struct file_operations sysmon_test_ops = {
+ .read = sysmon_test_read,
+ .write = sysmon_test_write,
+ .open = sysmon_test_open,
+ .release = sysmon_test_release
+};
+
+static int __init sysmon_test_init(void)
+{
+ sysmon_dev = kzalloc(sizeof(*sysmon_dev), GFP_KERNEL);
+ if (!sysmon_dev)
+ return -ENOMEM;
+
+ dfile = debugfs_create_file("hsic_sysmon_test", 0666, NULL,
+ 0, &sysmon_test_ops);
+ return 0;
+}
+
+static void __exit sysmon_test_exit(void)
+{
+ if (dfile)
+ debugfs_remove(dfile);
+ kfree(sysmon_dev);
+}
+
+module_init(sysmon_test_init);
+module_exit(sysmon_test_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index d0235f3..36cdd86 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -423,6 +423,7 @@
int (*dsi_power_save)(int on);
int (*dsi_client_reset)(void);
int (*get_lane_config)(void);
+ char (*splash_is_enabled)(void);
int target_type;
};
@@ -503,6 +504,12 @@
#endif
};
+struct vcap_platform_data {
+ unsigned *gpios;
+ int num_gpios;
+ struct msm_bus_scale_pdata *bus_client_pdata;
+};
+
#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
struct isp1763_platform_data {
unsigned reset_gpio;
@@ -532,6 +539,7 @@
void vic_handle_irq(struct pt_regs *regs);
void msm_copper_reserve(void);
void msm_copper_very_early(void);
+void msm_copper_init_gpiomux(void);
struct mmc_platform_data;
int msm_add_sdcc(unsigned int controller,
diff --git a/arch/arm/mach-msm/include/mach/camera.h b/arch/arm/mach-msm/include/mach/camera.h
index ef9fbc1..e6a0175 100644
--- a/arch/arm/mach-msm/include/mach/camera.h
+++ b/arch/arm/mach-msm/include/mach/camera.h
@@ -210,6 +210,7 @@
#endif
#define CSI_EMBED_DATA 0x12
+#define CSI_RESERVED_DATA_0 0x13
#define CSI_YUV422_8 0x1E
#define CSI_RAW8 0x2A
#define CSI_RAW10 0x2B
@@ -669,16 +670,16 @@
int msm_camio_csi_config(struct msm_camera_csi_params *csi_params);
int msm_camio_csiphy_config(struct msm_camera_csiphy_params *csiphy_params);
int msm_camio_csid_config(struct msm_camera_csid_params *csid_params);
-void msm_io_read_interrupt(void);
int add_axi_qos(void);
int update_axi_qos(uint32_t freq);
void release_axi_qos(void);
-void msm_io_w(u32 data, void __iomem *addr);
-void msm_io_w_mb(u32 data, void __iomem *addr);
-u32 msm_io_r(void __iomem *addr);
-u32 msm_io_r_mb(void __iomem *addr);
-void msm_io_dump(void __iomem *addr, int size);
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len);
+void msm_camera_io_w(u32 data, void __iomem *addr);
+void msm_camera_io_w_mb(u32 data, void __iomem *addr);
+u32 msm_camera_io_r(void __iomem *addr);
+u32 msm_camera_io_r_mb(void __iomem *addr);
+void msm_camera_io_dump(void __iomem *addr, int size);
+void msm_camera_io_memcpy(void __iomem *dest_addr,
+ void __iomem *src_addr, u32 len);
void msm_camio_set_perf_lvl(enum msm_bus_perf_setting);
void msm_camio_bus_scale_cfg(
struct msm_bus_scale_pdata *, enum msm_bus_perf_setting);
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index d170f5f..fb7f977 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -186,6 +186,12 @@
#define DMOV_HSUART_GSBI6_RX_CHAN 8
#define DMOV_HSUART_GSBI6_RX_CRCI 11
+#define DMOV_HSUART_GSBI9_TX_CHAN 4
+#define DMOV_HSUART_GSBI9_TX_CRCI 13
+
+#define DMOV_HSUART_GSBI9_RX_CHAN 3
+#define DMOV_HSUART_GSBI9_RX_CRCI 12
+
#elif defined(CONFIG_ARCH_MSM9615)
#define DMOV_GP_CHAN 4
diff --git a/arch/arm/mach-msm/include/mach/mpm.h b/arch/arm/mach-msm/include/mach/mpm.h
index 5cf52b9..10a6fb0 100644
--- a/arch/arm/mach-msm/include/mach/mpm.h
+++ b/arch/arm/mach-msm/include/mach/mpm.h
@@ -17,13 +17,6 @@
#include <linux/types.h>
#include <linux/list.h>
-enum msm_mpm_pin {
- MSM_MPM_PIN_SDC3_DAT1 = 21,
- MSM_MPM_PIN_SDC3_DAT3 = 22,
- MSM_MPM_PIN_SDC4_DAT1 = 23,
- MSM_MPM_PIN_SDC4_DAT3 = 24,
-};
-
#define MSM_MPM_NR_MPM_IRQS 64
struct msm_mpm_device_data {
@@ -46,9 +39,9 @@
void msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data);
#ifdef CONFIG_MSM_MPM
-int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable);
-int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on);
-int msm_mpm_set_pin_type(enum msm_mpm_pin pin, unsigned int flow_type);
+int msm_mpm_enable_pin(unsigned int pin, unsigned int enable);
+int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on);
+int msm_mpm_set_pin_type(unsigned int pin, unsigned int flow_type);
bool msm_mpm_irqs_detectable(bool from_idle);
bool msm_mpm_gpio_irqs_detectable(bool from_idle);
void msm_mpm_enter_sleep(bool from_idle);
@@ -60,11 +53,11 @@
{ return -ENODEV; }
static inline int msm_mpm_set_irq_type(unsigned int irq, unsigned int flow_type)
{ return -ENODEV; }
-static inline int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable)
+static inline int msm_mpm_enable_pin(unsigned int pin, unsigned int enable)
{ return -ENODEV; }
-static inline int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on)
+static inline int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on)
{ return -ENODEV; }
-static inline int msm_mpm_set_pin_type(enum msm_mpm_pin pin,
+static inline int msm_mpm_set_pin_type(unsigned int pin,
unsigned int flow_type)
{ return -ENODEV; }
static inline bool msm_mpm_irqs_detectable(bool from_idle)
diff --git a/arch/arm/mach-msm/include/mach/msm_memtypes.h b/arch/arm/mach-msm/include/mach/msm_memtypes.h
index 29a9d4a..6f9bed1 100644
--- a/arch/arm/mach-msm/include/mach/msm_memtypes.h
+++ b/arch/arm/mach-msm/include/mach/msm_memtypes.h
@@ -55,10 +55,13 @@
struct reserve_info {
struct memtype_reserve *memtype_reserve_table;
void (*calculate_reserve_sizes)(void);
+ void (*reserve_fixed_area)(unsigned long);
int (*paddr_to_memtype)(unsigned int);
unsigned long low_unstable_address;
unsigned long max_unstable_size;
unsigned long bank_size;
+ unsigned long fixed_area_start;
+ unsigned long fixed_area_size;
};
extern struct reserve_info *reserve_info;
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
index d896013..4934c0f 100644
--- a/arch/arm/mach-msm/include/mach/msm_smd.h
+++ b/arch/arm/mach-msm/include/mach/msm_smd.h
@@ -132,10 +132,25 @@
int disable_smsm_reset_handshake;
};
+/*
+ * Shared Memory Regions
+ *
+ * the array of these regions is expected to be in ascending order by phys_addr
+ *
+ * @phys_addr: physical base address of the region
+ * @size: size of the region in bytes
+ */
+struct smd_smem_regions {
+ void *phys_addr;
+ unsigned size;
+};
+
struct smd_platform {
uint32_t num_ss_configs;
struct smd_subsystem_config *smd_ss_configs;
struct smd_subsystem_restart_config *smd_ssr_config;
+ uint32_t num_smem_areas;
+ struct smd_smem_regions *smd_smem_areas;
};
#ifdef CONFIG_MSM_SMD
diff --git a/arch/arm/mach-msm/ipc_router.c b/arch/arm/mach-msm/ipc_router.c
index 538dbbe..6fa435a 100644
--- a/arch/arm/mach-msm/ipc_router.c
+++ b/arch/arm/mach-msm/ipc_router.c
@@ -457,8 +457,12 @@
INIT_LIST_HEAD(&port_ptr->port_rx_q);
mutex_init(&port_ptr->port_rx_q_lock);
init_waitqueue_head(&port_ptr->port_rx_wait_q);
+ snprintf(port_ptr->rx_wakelock_name, MAX_WAKELOCK_NAME_SZ,
+ "msm_ipc_read%08x:%08x",
+ port_ptr->this_port.node_id,
+ port_ptr->this_port.port_id);
wake_lock_init(&port_ptr->port_rx_wake_lock,
- WAKE_LOCK_SUSPEND, "msm_ipc_read");
+ WAKE_LOCK_SUSPEND, port_ptr->rx_wakelock_name);
port_ptr->endpoint = endpoint;
port_ptr->notify = notify;
diff --git a/arch/arm/mach-msm/ipc_router.h b/arch/arm/mach-msm/ipc_router.h
index bd10ea7..a90be23 100644
--- a/arch/arm/mach-msm/ipc_router.h
+++ b/arch/arm/mach-msm/ipc_router.h
@@ -95,6 +95,7 @@
/* internals */
#define IPC_ROUTER_MAX_REMOTE_SERVERS 100
+#define MAX_WAKELOCK_NAME_SZ 32
struct rr_packet {
struct list_head list;
@@ -116,6 +117,7 @@
struct list_head port_rx_q;
struct mutex port_rx_q_lock;
+ char rx_wakelock_name[MAX_WAKELOCK_NAME_SZ];
struct wake_lock port_rx_wake_lock;
wait_queue_head_t port_rx_wait_q;
@@ -136,7 +138,7 @@
struct msm_ipc_sock {
struct sock sk;
struct msm_ipc_port *port;
- void *modem_pil;
+ void *default_pil;
};
enum write_data_type {
@@ -204,4 +206,15 @@
int msm_ipc_router_init_sockets(void);
void msm_ipc_router_exit_sockets(void);
+#if defined CONFIG_MSM_IPC_ROUTER_SMD_XPRT
+extern void *msm_ipc_load_default_node(void);
+
+extern void msm_ipc_unload_default_node(void *pil);
+#else
+static inline void *msm_ipc_load_default_node(void)
+{ return NULL; }
+
+static inline void msm_ipc_unload_default_node(void *pil) { }
+#endif
+
#endif
diff --git a/arch/arm/mach-msm/ipc_router_smd_xprt.c b/arch/arm/mach-msm/ipc_router_smd_xprt.c
index 0cde393..307b6ae 100644
--- a/arch/arm/mach-msm/ipc_router_smd_xprt.c
+++ b/arch/arm/mach-msm/ipc_router_smd_xprt.c
@@ -19,6 +19,7 @@
#include <linux/types.h>
#include <mach/msm_smd.h>
+#include <mach/peripheral-loader.h>
#include "ipc_router.h"
#include "smd_private.h"
@@ -442,6 +443,31 @@
return 0;
}
+void *msm_ipc_load_default_node(void)
+{
+ void *pil = NULL;
+ const char *peripheral;
+
+ peripheral = smd_edge_to_subsystem(SMD_APPS_MODEM);
+ if (peripheral && !strncmp(peripheral, "modem", 6)) {
+ pil = pil_get(peripheral);
+ if (IS_ERR(pil)) {
+ pr_err("%s: Failed to load %s\n",
+ __func__, peripheral);
+ pil = NULL;
+ }
+ }
+ return pil;
+}
+EXPORT_SYMBOL(msm_ipc_load_default_node);
+
+void msm_ipc_unload_default_node(void *pil)
+{
+ if (pil)
+ pil_put(pil);
+}
+EXPORT_SYMBOL(msm_ipc_unload_default_node);
+
static struct platform_driver msm_ipc_router_smd_remote_driver[] = {
{
.probe = msm_ipc_router_smd_remote_probe,
diff --git a/arch/arm/mach-msm/ipc_socket.c b/arch/arm/mach-msm/ipc_socket.c
index 6e8c99e..d1ed538 100644
--- a/arch/arm/mach-msm/ipc_socket.c
+++ b/arch/arm/mach-msm/ipc_socket.c
@@ -26,58 +26,15 @@
#include <net/sock.h>
-#include <mach/peripheral-loader.h>
-#include <mach/socinfo.h>
-
#include "ipc_router.h"
#define msm_ipc_sk(sk) ((struct msm_ipc_sock *)(sk))
#define msm_ipc_sk_port(sk) ((struct msm_ipc_port *)(msm_ipc_sk(sk)->port))
-#define MODEM_LOAD_TIMEOUT (10 * HZ)
static int sockets_enabled;
static struct proto msm_ipc_proto;
static const struct proto_ops msm_ipc_proto_ops;
-static void msm_ipc_router_unload_modem(void *pil)
-{
- if (pil)
- pil_put(pil);
-}
-
-static void *msm_ipc_router_load_modem(void)
-{
- void *pil = NULL;
- int rc;
-
- /* Load GNSS for Standalone 8064 but not for Fusion 3 */
- if (cpu_is_apq8064()) {
- if (socinfo_get_platform_subtype() == 0x0)
- pil = pil_get("gss");
- } else {
- pil = pil_get("modem");
- }
-
- if (IS_ERR(pil) || !pil) {
- pr_debug("%s: modem load failed\n", __func__);
- pil = NULL;
- } else {
- rc = wait_for_completion_interruptible_timeout(
- &msm_ipc_remote_router_up,
- MODEM_LOAD_TIMEOUT);
- if (!rc)
- rc = -ETIMEDOUT;
- if (rc < 0) {
- pr_err("%s: wait for remote router failed %d\n",
- __func__, rc);
- msm_ipc_router_unload_modem(pil);
- pil = NULL;
- }
- }
-
- return pil;
-}
-
static struct sk_buff_head *msm_ipc_router_build_msg(unsigned int num_sect,
struct iovec const *msg_sect,
size_t total_len)
@@ -244,9 +201,9 @@
sock_init_data(sock, sk);
sk->sk_rcvtimeo = DEFAULT_RCV_TIMEO;
- pil = msm_ipc_router_load_modem();
+ pil = msm_ipc_load_default_node();
msm_ipc_sk(sk)->port = port_ptr;
- msm_ipc_sk(sk)->modem_pil = pil;
+ msm_ipc_sk(sk)->default_pil = pil;
return 0;
}
@@ -495,12 +452,12 @@
{
struct sock *sk = sock->sk;
struct msm_ipc_port *port_ptr = msm_ipc_sk_port(sk);
- void *pil = msm_ipc_sk(sk)->modem_pil;
+ void *pil = msm_ipc_sk(sk)->default_pil;
int ret;
lock_sock(sk);
ret = msm_ipc_router_close_port(port_ptr);
- msm_ipc_router_unload_modem(pil);
+ msm_ipc_unload_default_node(pil);
release_sock(sk);
sock_put(sk);
sock->sk = NULL;
diff --git a/arch/arm/mach-msm/memory.c b/arch/arm/mach-msm/memory.c
index 8dbf304..0db160e 100644
--- a/arch/arm/mach-msm/memory.c
+++ b/arch/arm/mach-msm/memory.c
@@ -317,6 +317,8 @@
if (size >= mt->size) {
size = stable_size(mb,
reserve_info->low_unstable_address);
+ if (!size)
+ continue;
/* mt->size may be larger than size, all this
* means is that we are carving the memory pool
* out of multiple contiguous memory banks.
@@ -370,10 +372,24 @@
}
}
+#define MAX_FIXED_AREA_SIZE 0x11000000
+
void __init msm_reserve(void)
{
+ unsigned long msm_fixed_area_size;
+ unsigned long msm_fixed_area_start;
+
memory_pool_init();
reserve_info->calculate_reserve_sizes();
+
+ msm_fixed_area_size = reserve_info->fixed_area_size;
+ msm_fixed_area_start = reserve_info->fixed_area_start;
+ if (msm_fixed_area_size)
+ if (msm_fixed_area_start > reserve_info->low_unstable_address
+ - MAX_FIXED_AREA_SIZE)
+ reserve_info->low_unstable_address =
+ msm_fixed_area_start;
+
calculate_reserve_limits();
adjust_reserve_sizes();
reserve_memory_for_mempools();
diff --git a/arch/arm/mach-msm/mpm.c b/arch/arm/mach-msm/mpm.c
index dccdc8b..b395b61 100644
--- a/arch/arm/mach-msm/mpm.c
+++ b/arch/arm/mach-msm/mpm.c
@@ -328,7 +328,7 @@
/******************************************************************************
* Public functions
*****************************************************************************/
-int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable)
+int msm_mpm_enable_pin(unsigned int pin, unsigned int enable)
{
uint32_t index = MSM_MPM_IRQ_INDEX(pin);
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
@@ -345,7 +345,7 @@
return 0;
}
-int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on)
+int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on)
{
uint32_t index = MSM_MPM_IRQ_INDEX(pin);
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
@@ -362,7 +362,7 @@
return 0;
}
-int msm_mpm_set_pin_type(enum msm_mpm_pin pin, unsigned int flow_type)
+int msm_mpm_set_pin_type(unsigned int pin, unsigned int flow_type)
{
uint32_t index = MSM_MPM_IRQ_INDEX(pin);
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
diff --git a/arch/arm/mach-msm/msm_rtb.c b/arch/arm/mach-msm/msm_rtb.c
index 403c13d..9dbf9c1 100644
--- a/arch/arm/mach-msm/msm_rtb.c
+++ b/arch/arm/mach-msm/msm_rtb.c
@@ -74,6 +74,17 @@
module_param_named(filter, msm_rtb.filter, uint, 0644);
module_param_named(enable, msm_rtb.enabled, int, 0644);
+static int msm_rtb_panic_notifier(struct notifier_block *this,
+ unsigned long event, void *ptr)
+{
+ msm_rtb.enabled = 0;
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block msm_rtb_panic_blk = {
+ .notifier_call = msm_rtb_panic_notifier,
+};
+
int msm_rtb_event_should_log(enum logk_event_type log_type)
{
return msm_rtb.initialized && msm_rtb.enabled &&
@@ -258,7 +269,8 @@
msm_rtb.step_size = 1;
#endif
-
+ atomic_notifier_chain_register(&panic_notifier_list,
+ &msm_rtb_panic_blk);
msm_rtb.initialized = 1;
return 0;
}
diff --git a/arch/arm/mach-msm/pil-modem.c b/arch/arm/mach-msm/pil-modem.c
index 998e606..8344496 100644
--- a/arch/arm/mach-msm/pil-modem.c
+++ b/arch/arm/mach-msm/pil-modem.c
@@ -251,7 +251,7 @@
if (!drv->base)
return -ENOMEM;
- drv->xo = clk_get(&pdev->dev, "xo");
+ drv->xo = devm_clk_get(&pdev->dev, "xo");
if (IS_ERR(drv->xo))
return PTR_ERR(drv->xo);
@@ -274,7 +274,6 @@
}
drv->pil = msm_pil_register(desc);
if (IS_ERR(drv->pil)) {
- clk_put(drv->xo);
return PTR_ERR(drv->pil);
}
return 0;
@@ -284,7 +283,6 @@
{
struct modem_data *drv = platform_get_drvdata(pdev);
msm_pil_unregister(drv->pil);
- clk_put(drv->xo);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v3.c b/arch/arm/mach-msm/pil-q6v3.c
index 235d881..28b9dee 100644
--- a/arch/arm/mach-msm/pil-q6v3.c
+++ b/arch/arm/mach-msm/pil-q6v3.c
@@ -221,7 +221,7 @@
if (!drv)
return -ENOMEM;
- drv->pll = clk_get(&pdev->dev, "pll4");
+ drv->pll = devm_clk_get(&pdev->dev, "pll4");
if (IS_ERR(drv->pll))
return PTR_ERR(drv->pll);
diff --git a/arch/arm/mach-msm/pil-riva.c b/arch/arm/mach-msm/pil-riva.c
index ecbbcb9..8a16b43 100644
--- a/arch/arm/mach-msm/pil-riva.c
+++ b/arch/arm/mach-msm/pil-riva.c
@@ -318,14 +318,14 @@
if (ret) {
dev_err(&pdev->dev,
"failed to set pll supply voltage\n");
- goto err;
+ return ret;
}
ret = regulator_set_optimum_mode(drv->pll_supply, 100000);
if (ret < 0) {
dev_err(&pdev->dev,
"failed to set pll supply optimum mode\n");
- goto err;
+ return ret;
}
}
@@ -342,29 +342,20 @@
dev_info(&pdev->dev, "using non-secure boot\n");
}
- drv->xo = clk_get(&pdev->dev, "cxo");
- if (IS_ERR(drv->xo)) {
- ret = PTR_ERR(drv->xo);
- goto err;
- }
+ drv->xo = devm_clk_get(&pdev->dev, "cxo");
+ if (IS_ERR(drv->xo))
+ return PTR_ERR(drv->xo);
drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil)) {
- ret = PTR_ERR(drv->pil);
- goto err_register;
- }
+ if (IS_ERR(drv->pil))
+ return PTR_ERR(drv->pil);
return 0;
-err_register:
- clk_put(drv->xo);
-err:
- return ret;
}
static int __devexit pil_riva_remove(struct platform_device *pdev)
{
struct riva_data *drv = platform_get_drvdata(pdev);
msm_pil_unregister(drv->pil);
- clk_put(drv->xo);
return 0;
}
diff --git a/arch/arm/mach-msm/platsmp-8625.c b/arch/arm/mach-msm/platsmp-8625.c
index 82aeb16..23ca454 100644
--- a/arch/arm/mach-msm/platsmp-8625.c
+++ b/arch/arm/mach-msm/platsmp-8625.c
@@ -120,16 +120,11 @@
raw_spin_unlock(&irq_controller_lock);
}
-void clear_pending_spi(unsigned int irq)
+static void clear_pending_spi(unsigned int irq)
{
- struct irq_data *d = irq_get_irq_data(irq);
- struct irq_chip *c = irq_data_get_irq_chip(d);
-
/* Clear the IRQ from the ENABLE_SET */
- c->irq_mask(d);
local_irq_disable();
gic_clear_spi_pending(irq);
- c->irq_unmask(d);
local_irq_enable();
}
@@ -152,6 +147,13 @@
*/
write_pen_release(-1);
+ /* clear the IPC1(SPI-8) pending SPI */
+ if (power_collapsed) {
+ raise_clear_spi(1, false);
+ clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
+ power_collapsed = 0;
+ }
+
/*
* Synchronise with the boot thread.
*/
@@ -246,13 +248,6 @@
udelay(10);
}
- /* Now we should clear the pending SPI */
- if (power_collapsed) {
- raise_clear_spi(1, false);
- clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
- power_collapsed = 0;
- }
-
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_mp3.c b/arch/arm/mach-msm/qdsp6v2/audio_mp3.c
index c1a90bd..eff41cc 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_mp3.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_mp3.c
@@ -127,8 +127,14 @@
audio->buf_cfg.meta_info_enable = 0x01;
} else if ((file->f_mode & FMODE_WRITE) &&
!(file->f_mode & FMODE_READ)) {
- pr_err("%s: Tunnel Mode not supported\n", __func__);
- return -EACCES;
+ rc = q6asm_open_write(audio->ac, FORMAT_MP3);
+ if (rc < 0) {
+ pr_err("T mode Open failed rc=%d\n", rc);
+ rc = -ENODEV;
+ goto fail;
+ }
+ audio->feedback = TUNNEL_MODE;
+ audio->buf_cfg.meta_info_enable = 0x00;
} else {
pr_err("Not supported mode\n");
rc = -EACCES;
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 839f932..c1e4118 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -34,6 +34,7 @@
#include <linux/kfifo.h>
#include <linux/wakelock.h>
#include <linux/notifier.h>
+#include <linux/sort.h>
#include <mach/msm_smd.h>
#include <mach/msm_iomap.h>
#include <mach/system.h>
@@ -138,6 +139,7 @@
static irqreturn_t smsm_dsps_irq_handler(int irq, void *data);
static irqreturn_t smd_wcnss_irq_handler(int irq, void *data);
static irqreturn_t smsm_wcnss_irq_handler(int irq, void *data);
+static irqreturn_t smd_rpm_irq_handler(int irq, void *data);
static irqreturn_t smsm_irq_handler(int irq, void *data);
static struct interrupt_config private_intr_config[NUM_SMD_SUBSYSTEMS] = {
@@ -157,7 +159,21 @@
.smd.irq_handler = smd_wcnss_irq_handler,
.smsm.irq_handler = smsm_wcnss_irq_handler,
},
+ [SMD_RPM] = {
+ .smd.irq_handler = smd_rpm_irq_handler,
+ .smsm.irq_handler = NULL, /* does not support smsm */
+ },
};
+
+struct smem_area {
+ void *phys_addr;
+ unsigned size;
+ void __iomem *virt_addr;
+};
+static uint32_t num_smem_areas;
+static struct smem_area *smem_areas;
+static void *smem_range_check(void *base, unsigned offset);
+
struct interrupt_stat interrupt_stats[NUM_SMD_SUBSYSTEMS];
#define SMSM_STATE_ADDR(entry) (smsm_info.state + entry)
@@ -430,6 +446,18 @@
}
}
+static inline void notify_rpm_smd(void)
+{
+ static const struct interrupt_config_item *intr
+ = &private_intr_config[SMD_RPM].smd;
+
+ if (intr->out_base) {
+ ++interrupt_stats[SMD_RPM].smd_out_config_count;
+ smd_write_intr(intr->out_bit_pos,
+ intr->out_base + intr->out_offset);
+ }
+}
+
static inline void notify_modem_smsm(void)
{
static const struct interrupt_config_item *intr
@@ -608,9 +636,14 @@
struct smd_half_channel ch1;
};
+struct smd_shared_v2_word_access {
+ struct smd_half_channel_word_access ch0;
+ struct smd_half_channel_word_access ch1;
+};
+
struct smd_channel {
- volatile struct smd_half_channel *send;
- volatile struct smd_half_channel *recv;
+ volatile void *send; /* some variant of smd_half_channel */
+ volatile void *recv; /* some variant of smd_half_channel */
unsigned char *send_data;
unsigned char *recv_data;
unsigned fifo_size;
@@ -641,6 +674,12 @@
int pending_pkt_sz;
char is_pkt_ch;
+
+ /*
+ * private internal functions to access *send and *recv.
+ * never to be exported outside of smd
+ */
+ struct smd_half_channel_access *half_ch;
};
struct edge_to_pid {
@@ -668,6 +707,10 @@
[SMD_QDSP_Q6FW] = {SMD_Q6, SMD_MODEM_Q6_FW},
[SMD_DSPS_Q6FW] = {SMD_DSPS, SMD_MODEM_Q6_FW},
[SMD_WCNSS_Q6FW] = {SMD_WCNSS, SMD_MODEM_Q6_FW},
+ [SMD_APPS_RPM] = {SMD_APPS, SMD_RPM},
+ [SMD_MODEM_RPM] = {SMD_MODEM, SMD_RPM},
+ [SMD_QDSP_RPM] = {SMD_Q6, SMD_RPM},
+ [SMD_WCNSS_RPM] = {SMD_WCNSS, SMD_RPM},
};
struct restart_notifier_block {
@@ -686,6 +729,7 @@
static LIST_HEAD(smd_ch_list_dsp);
static LIST_HEAD(smd_ch_list_dsps);
static LIST_HEAD(smd_ch_list_wcnss);
+static LIST_HEAD(smd_ch_list_rpm);
static unsigned char smd_ch_allocated[64];
static struct work_struct probe_work;
@@ -721,8 +765,8 @@
/* channel should be allocated only if APPS
processor is involved */
type = SMD_CHANNEL_TYPE(shared[n].type);
- if ((type != SMD_APPS_MODEM) && (type != SMD_APPS_QDSP) &&
- (type != SMD_APPS_DSPS) && (type != SMD_APPS_WCNSS))
+ if (type >= ARRAY_SIZE(edge_to_pids) ||
+ edge_to_pids[type].local_pid != SMD_APPS)
continue;
if (!shared[n].ref_count)
continue;
@@ -941,14 +985,15 @@
/* how many bytes are available for reading */
static int smd_stream_read_avail(struct smd_channel *ch)
{
- return (ch->recv->head - ch->recv->tail) & ch->fifo_mask;
+ return (ch->half_ch->get_head(ch->recv) -
+ ch->half_ch->get_tail(ch->recv)) & ch->fifo_mask;
}
/* how many bytes we are free to write */
static int smd_stream_write_avail(struct smd_channel *ch)
{
- return ch->fifo_mask -
- ((ch->send->head - ch->send->tail) & ch->fifo_mask);
+ return ch->fifo_mask - ((ch->half_ch->get_head(ch->send) -
+ ch->half_ch->get_tail(ch->send)) & ch->fifo_mask);
}
static int smd_packet_read_avail(struct smd_channel *ch)
@@ -971,16 +1016,16 @@
static int ch_is_open(struct smd_channel *ch)
{
- return (ch->recv->state == SMD_SS_OPENED ||
- ch->recv->state == SMD_SS_FLUSHING)
- && (ch->send->state == SMD_SS_OPENED);
+ return (ch->half_ch->get_state(ch->recv) == SMD_SS_OPENED ||
+ ch->half_ch->get_state(ch->recv) == SMD_SS_FLUSHING)
+ && (ch->half_ch->get_state(ch->send) == SMD_SS_OPENED);
}
/* provide a pointer and length to readable data in the fifo */
static unsigned ch_read_buffer(struct smd_channel *ch, void **ptr)
{
- unsigned head = ch->recv->head;
- unsigned tail = ch->recv->tail;
+ unsigned head = ch->half_ch->get_head(ch->recv);
+ unsigned tail = ch->half_ch->get_tail(ch->recv);
*ptr = (void *) (ch->recv_data + tail);
if (tail <= head)
@@ -991,16 +1036,17 @@
static int read_intr_blocked(struct smd_channel *ch)
{
- return ch->recv->fBLOCKREADINTR;
+ return ch->half_ch->get_fBLOCKREADINTR(ch->recv);
}
/* advance the fifo read pointer after data from ch_read_buffer is consumed */
static void ch_read_done(struct smd_channel *ch, unsigned count)
{
BUG_ON(count > smd_stream_read_avail(ch));
- ch->recv->tail = (ch->recv->tail + count) & ch->fifo_mask;
+ ch->half_ch->set_tail(ch->recv,
+ (ch->half_ch->get_tail(ch->recv) + count) & ch->fifo_mask);
wmb();
- ch->send->fTAIL = 1;
+ ch->half_ch->set_fTAIL(ch->send, 1);
}
/* basic read interface to ch_read_{buffer,done} used
@@ -1072,8 +1118,8 @@
/* provide a pointer and length to next free space in the fifo */
static unsigned ch_write_buffer(struct smd_channel *ch, void **ptr)
{
- unsigned head = ch->send->head;
- unsigned tail = ch->send->tail;
+ unsigned head = ch->half_ch->get_head(ch->send);
+ unsigned tail = ch->half_ch->get_tail(ch->send);
*ptr = (void *) (ch->send_data + head);
if (head < tail) {
@@ -1092,24 +1138,25 @@
static void ch_write_done(struct smd_channel *ch, unsigned count)
{
BUG_ON(count > smd_stream_write_avail(ch));
- ch->send->head = (ch->send->head + count) & ch->fifo_mask;
+ ch->half_ch->set_head(ch->send,
+ (ch->half_ch->get_head(ch->send) + count) & ch->fifo_mask);
wmb();
- ch->send->fHEAD = 1;
+ ch->half_ch->set_fHEAD(ch->send, 1);
}
static void ch_set_state(struct smd_channel *ch, unsigned n)
{
if (n == SMD_SS_OPENED) {
- ch->send->fDSR = 1;
- ch->send->fCTS = 1;
- ch->send->fCD = 1;
+ ch->half_ch->set_fDSR(ch->send, 1);
+ ch->half_ch->set_fCTS(ch->send, 1);
+ ch->half_ch->set_fCD(ch->send, 1);
} else {
- ch->send->fDSR = 0;
- ch->send->fCTS = 0;
- ch->send->fCD = 0;
+ ch->half_ch->set_fDSR(ch->send, 0);
+ ch->half_ch->set_fCTS(ch->send, 0);
+ ch->half_ch->set_fCD(ch->send, 0);
}
- ch->send->state = n;
- ch->send->fSTATE = 1;
+ ch->half_ch->set_state(ch->send, n);
+ ch->half_ch->set_fSTATE(ch->send, 1);
ch->notify_other_cpu();
}
@@ -1131,16 +1178,16 @@
switch (next) {
case SMD_SS_OPENING:
- if (ch->send->state == SMD_SS_CLOSING ||
- ch->send->state == SMD_SS_CLOSED) {
- ch->recv->tail = 0;
- ch->send->head = 0;
- ch->send->fBLOCKREADINTR = 0;
+ if (ch->half_ch->get_state(ch->send) == SMD_SS_CLOSING ||
+ ch->half_ch->get_state(ch->send) == SMD_SS_CLOSED) {
+ ch->half_ch->set_tail(ch->recv, 0);
+ ch->half_ch->set_head(ch->send, 0);
+ ch->half_ch->set_fBLOCKREADINTR(ch->send, 0);
ch_set_state(ch, SMD_SS_OPENING);
}
break;
case SMD_SS_OPENED:
- if (ch->send->state == SMD_SS_OPENING) {
+ if (ch->half_ch->get_state(ch->send) == SMD_SS_OPENING) {
ch_set_state(ch, SMD_SS_OPENED);
ch->notify(ch->priv, SMD_EVENT_OPEN);
}
@@ -1150,7 +1197,7 @@
/* we should force them to close? */
break;
case SMD_SS_CLOSED:
- if (ch->send->state == SMD_SS_OPENED) {
+ if (ch->half_ch->get_state(ch->send) == SMD_SS_OPENED) {
ch_set_state(ch, SMD_SS_CLOSING);
ch->current_packet = 0;
ch->pending_pkt_sz = 0;
@@ -1158,7 +1205,7 @@
}
break;
case SMD_SS_CLOSING:
- if (ch->send->state == SMD_SS_CLOSED) {
+ if (ch->half_ch->get_state(ch->send) == SMD_SS_CLOSED) {
list_move(&ch->ch_list,
&smd_ch_to_close_list);
queue_work(channel_close_wq,
@@ -1177,9 +1224,9 @@
spin_lock_irqsave(&smd_lock, flags);
list_for_each_entry_safe(ch, index, &smd_ch_closing_list, ch_list) {
- if (ch->recv->fSTATE)
- ch->recv->fSTATE = 0;
- tmp = ch->recv->state;
+ if (ch->half_ch->get_fSTATE(ch->recv))
+ ch->half_ch->set_fSTATE(ch->recv, 0);
+ tmp = ch->half_ch->get_state(ch->recv);
if (tmp != ch->last_state)
smd_state_change(ch, ch->last_state, tmp);
}
@@ -1199,20 +1246,20 @@
state_change = 0;
ch_flags = 0;
if (ch_is_open(ch)) {
- if (ch->recv->fHEAD) {
- ch->recv->fHEAD = 0;
+ if (ch->half_ch->get_fHEAD(ch->recv)) {
+ ch->half_ch->set_fHEAD(ch->recv, 0);
ch_flags |= 1;
}
- if (ch->recv->fTAIL) {
- ch->recv->fTAIL = 0;
+ if (ch->half_ch->get_fTAIL(ch->recv)) {
+ ch->half_ch->set_fTAIL(ch->recv, 0);
ch_flags |= 2;
}
- if (ch->recv->fSTATE) {
- ch->recv->fSTATE = 0;
+ if (ch->half_ch->get_fSTATE(ch->recv)) {
+ ch->half_ch->set_fSTATE(ch->recv, 0);
ch_flags |= 4;
}
}
- tmp = ch->recv->state;
+ tmp = ch->half_ch->get_state(ch->recv);
if (tmp != ch->last_state) {
SMx_POWER_INFO("SMD ch%d '%s' State change %d->%d\n",
ch->n, ch->name, ch->last_state, tmp);
@@ -1273,12 +1320,22 @@
return IRQ_HANDLED;
}
+static irqreturn_t smd_rpm_irq_handler(int irq, void *data)
+{
+ SMx_POWER_INFO("SMD Int RPM->Apps\n");
+ ++interrupt_stats[SMD_RPM].smd_in_count;
+ handle_smd_irq(&smd_ch_list_rpm, notify_rpm_smd);
+ handle_smd_irq_closing_list();
+ return IRQ_HANDLED;
+}
+
static void smd_fake_irq_handler(unsigned long arg)
{
handle_smd_irq(&smd_ch_list_modem, notify_modem_smd);
handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd);
handle_smd_irq(&smd_ch_list_dsps, notify_dsps_smd);
handle_smd_irq(&smd_ch_list_wcnss, notify_wcnss_smd);
+ handle_smd_irq(&smd_ch_list_rpm, notify_rpm_smd);
handle_smd_irq_closing_list();
}
@@ -1287,9 +1344,11 @@
static inline int smd_need_int(struct smd_channel *ch)
{
if (ch_is_open(ch)) {
- if (ch->recv->fHEAD || ch->recv->fTAIL || ch->recv->fSTATE)
+ if (ch->half_ch->get_fHEAD(ch->recv) ||
+ ch->half_ch->get_fTAIL(ch->recv) ||
+ ch->half_ch->get_fSTATE(ch->recv))
return 1;
- if (ch->recv->state != ch->last_state)
+ if (ch->half_ch->get_state(ch->recv) != ch->last_state)
return 1;
}
return 0;
@@ -1504,15 +1563,32 @@
#if (defined(CONFIG_MSM_SMD_PKG4) || defined(CONFIG_MSM_SMD_PKG3))
static int smd_alloc_v2(struct smd_channel *ch)
{
- struct smd_shared_v2 *shared2;
void *buffer;
unsigned buffer_sz;
- shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
- if (!shared2) {
- SMD_INFO("smem_alloc failed ch=%d\n", ch->n);
- return -EINVAL;
+ if (is_word_access_ch(ch->type)) {
+ struct smd_shared_v2_word_access *shared2;
+ shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n,
+ sizeof(*shared2));
+ if (!shared2) {
+ SMD_INFO("smem_alloc failed ch=%d\n", ch->n);
+ return -EINVAL;
+ }
+ ch->send = &shared2->ch0;
+ ch->recv = &shared2->ch1;
+ } else {
+ struct smd_shared_v2 *shared2;
+ shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n,
+ sizeof(*shared2));
+ if (!shared2) {
+ SMD_INFO("smem_alloc failed ch=%d\n", ch->n);
+ return -EINVAL;
+ }
+ ch->send = &shared2->ch0;
+ ch->recv = &shared2->ch1;
}
+ ch->half_ch = get_half_ch_funcs(ch->type);
+
buffer = smem_get_entry(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
if (!buffer) {
SMD_INFO("smem_get_entry failed\n");
@@ -1525,11 +1601,10 @@
return -EINVAL;
}
buffer_sz /= 2;
- ch->send = &shared2->ch0;
- ch->recv = &shared2->ch1;
ch->send_data = buffer;
ch->recv_data = buffer + buffer_sz;
ch->fifo_size = buffer_sz;
+
return 0;
}
@@ -1557,6 +1632,7 @@
ch->send_data = shared1->data0;
ch->recv_data = shared1->data1;
ch->fifo_size = SMD_BUF_SIZE;
+ ch->half_ch = get_half_ch_funcs(ch->type);
return 0;
}
@@ -1572,6 +1648,7 @@
return -1;
}
ch->n = alloc_elm->cid;
+ ch->type = SMD_CHANNEL_TYPE(alloc_elm->type);
if (smd_alloc_v2(ch) && smd_alloc_v1(ch)) {
kfree(ch);
@@ -1579,16 +1656,18 @@
}
ch->fifo_mask = ch->fifo_size - 1;
- ch->type = SMD_CHANNEL_TYPE(alloc_elm->type);
+ /* probe_worker guarentees ch->type will be a valid type */
if (ch->type == SMD_APPS_MODEM)
ch->notify_other_cpu = notify_modem_smd;
else if (ch->type == SMD_APPS_QDSP)
ch->notify_other_cpu = notify_dsp_smd;
else if (ch->type == SMD_APPS_DSPS)
ch->notify_other_cpu = notify_dsps_smd;
- else
+ else if (ch->type == SMD_APPS_WCNSS)
ch->notify_other_cpu = notify_wcnss_smd;
+ else if (ch->type == SMD_APPS_RPM)
+ ch->notify_other_cpu = notify_rpm_smd;
if (smd_is_packet(alloc_elm)) {
ch->read = smd_packet_read;
@@ -1783,10 +1862,10 @@
if (edge == SMD_LOOPBACK_TYPE) {
ch->last_state = SMD_SS_OPENED;
- ch->send->state = SMD_SS_OPENED;
- ch->send->fDSR = 1;
- ch->send->fCTS = 1;
- ch->send->fCD = 1;
+ ch->half_ch->set_state(ch->send, SMD_SS_OPENED);
+ ch->half_ch->set_fDSR(ch->send, 1);
+ ch->half_ch->set_fCTS(ch->send, 1);
+ ch->half_ch->set_fCD(ch->send, 1);
}
*_ch = ch;
@@ -1802,6 +1881,8 @@
list_add(&ch->ch_list, &smd_ch_list_dsps);
else if (SMD_CHANNEL_TYPE(ch->type) == SMD_APPS_WCNSS)
list_add(&ch->ch_list, &smd_ch_list_wcnss);
+ else if (SMD_CHANNEL_TYPE(ch->type) == SMD_APPS_RPM)
+ list_add(&ch->ch_list, &smd_ch_list_rpm);
else
list_add(&ch->ch_list, &smd_ch_list_loopback);
@@ -1837,14 +1918,14 @@
spin_lock_irqsave(&smd_lock, flags);
list_del(&ch->ch_list);
if (ch->n == SMD_LOOPBACK_CID) {
- ch->send->fDSR = 0;
- ch->send->fCTS = 0;
- ch->send->fCD = 0;
- ch->send->state = SMD_SS_CLOSED;
+ ch->half_ch->set_fDSR(ch->send, 0);
+ ch->half_ch->set_fCTS(ch->send, 0);
+ ch->half_ch->set_fCD(ch->send, 0);
+ ch->half_ch->set_state(ch->send, SMD_SS_CLOSED);
} else
ch_set_state(ch, SMD_SS_CLOSED);
- if (ch->recv->state == SMD_SS_OPENED) {
+ if (ch->half_ch->get_state(ch->recv) == SMD_SS_OPENED) {
list_add(&ch->ch_list, &smd_ch_closing_list);
spin_unlock_irqrestore(&smd_lock, flags);
} else {
@@ -2031,14 +2112,14 @@
void smd_enable_read_intr(smd_channel_t *ch)
{
if (ch)
- ch->send->fBLOCKREADINTR = 0;
+ ch->half_ch->set_fBLOCKREADINTR(ch->send, 0);
}
EXPORT_SYMBOL(smd_enable_read_intr);
void smd_disable_read_intr(smd_channel_t *ch)
{
if (ch)
- ch->send->fBLOCKREADINTR = 1;
+ ch->half_ch->set_fBLOCKREADINTR(ch->send, 1);
}
EXPORT_SYMBOL(smd_disable_read_intr);
@@ -2070,12 +2151,12 @@
return -ENODEV;
}
- return (ch->recv->fDSR ? TIOCM_DSR : 0) |
- (ch->recv->fCTS ? TIOCM_CTS : 0) |
- (ch->recv->fCD ? TIOCM_CD : 0) |
- (ch->recv->fRI ? TIOCM_RI : 0) |
- (ch->send->fCTS ? TIOCM_RTS : 0) |
- (ch->send->fDSR ? TIOCM_DTR : 0);
+ return (ch->half_ch->get_fDSR(ch->recv) ? TIOCM_DSR : 0) |
+ (ch->half_ch->get_fCTS(ch->recv) ? TIOCM_CTS : 0) |
+ (ch->half_ch->get_fCD(ch->recv) ? TIOCM_CD : 0) |
+ (ch->half_ch->get_fRI(ch->recv) ? TIOCM_RI : 0) |
+ (ch->half_ch->get_fCTS(ch->send) ? TIOCM_RTS : 0) |
+ (ch->half_ch->get_fDSR(ch->send) ? TIOCM_DTR : 0);
}
EXPORT_SYMBOL(smd_tiocmget);
@@ -2089,18 +2170,18 @@
}
if (set & TIOCM_DTR)
- ch->send->fDSR = 1;
+ ch->half_ch->set_fDSR(ch->send, 1);
if (set & TIOCM_RTS)
- ch->send->fCTS = 1;
+ ch->half_ch->set_fCTS(ch->send, 1);
if (clear & TIOCM_DTR)
- ch->send->fDSR = 0;
+ ch->half_ch->set_fDSR(ch->send, 0);
if (clear & TIOCM_RTS)
- ch->send->fCTS = 0;
+ ch->half_ch->set_fCTS(ch->send, 0);
- ch->send->fSTATE = 1;
+ ch->half_ch->set_fSTATE(ch->send, 1);
barrier();
ch->notify_other_cpu();
@@ -2128,6 +2209,37 @@
/* -------------------------------------------------------------------------- */
+/*
+ * Shared Memory Range Check
+ *
+ * Takes a physical address and an offset and checks if the resulting physical
+ * address would fit into one of the aux smem regions. If so, returns the
+ * corresponding virtual address. Otherwise returns NULL. Expects the array
+ * of smem regions to be in ascending physical address order.
+ *
+ * @base: physical base address to check
+ * @offset: offset from the base to get the final address
+ */
+static void *smem_range_check(void *base, unsigned offset)
+{
+ int i;
+ void *phys_addr;
+ unsigned size;
+
+ for (i = 0; i < num_smem_areas; ++i) {
+ phys_addr = smem_areas[i].phys_addr;
+ size = smem_areas[i].size;
+ if (base < phys_addr)
+ return NULL;
+ if (base > phys_addr + size)
+ continue;
+ if (base >= phys_addr && base + offset < phys_addr + size)
+ return smem_areas[i].virt_addr + offset;
+ }
+
+ return NULL;
+}
+
/* smem_alloc returns the pointer to smem item if it is already allocated.
* Otherwise, it returns NULL.
*/
@@ -2203,7 +2315,12 @@
if (toc[id].allocated) {
*size = toc[id].size;
barrier();
- ret = (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
+ if (!(toc[id].reserved & BASE_ADDR_MASK))
+ ret = (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
+ else
+ ret = smem_range_check(
+ (void *)(toc[id].reserved & BASE_ADDR_MASK),
+ toc[id].offset);
} else {
*size = 0;
}
@@ -3114,6 +3231,14 @@
return ret;
}
+int sort_cmp_func(const void *a, const void *b)
+{
+ struct smem_area *left = (struct smem_area *)(a);
+ struct smem_area *right = (struct smem_area *)(b);
+
+ return left->phys_addr - right->phys_addr;
+}
+
int smd_core_platform_init(struct platform_device *pdev)
{
int i;
@@ -3123,6 +3248,8 @@
struct smd_subsystem_config *smd_ss_config_list;
struct smd_subsystem_config *cfg;
int err_ret = 0;
+ struct smd_smem_regions *smd_smem_areas;
+ int smem_idx = 0;
smd_platform_data = pdev->dev.platform_data;
num_ss = smd_platform_data->num_ss_configs;
@@ -3132,6 +3259,40 @@
disable_smsm_reset_handshake = smd_platform_data->
smd_ssr_config->disable_smsm_reset_handshake;
+ smd_smem_areas = smd_platform_data->smd_smem_areas;
+ if (smd_smem_areas) {
+ num_smem_areas = smd_platform_data->num_smem_areas;
+ smem_areas = kmalloc(sizeof(struct smem_area) * num_smem_areas,
+ GFP_KERNEL);
+ if (!smem_areas) {
+ pr_err("%s: smem_areas kmalloc failed\n", __func__);
+ err_ret = -ENOMEM;
+ goto smem_areas_alloc_fail;
+ }
+
+ for (smem_idx = 0; smem_idx < num_smem_areas; ++smem_idx) {
+ smem_areas[smem_idx].phys_addr =
+ smd_smem_areas[smem_idx].phys_addr;
+ smem_areas[smem_idx].size =
+ smd_smem_areas[smem_idx].size;
+ smem_areas[smem_idx].virt_addr = ioremap_nocache(
+ (unsigned long)(smem_areas[smem_idx].phys_addr),
+ smem_areas[smem_idx].size);
+ if (!smem_areas[smem_idx].virt_addr) {
+ pr_err("%s: ioremap_nocache() of addr:%p"
+ " size: %x\n", __func__,
+ smem_areas[smem_idx].phys_addr,
+ smem_areas[smem_idx].size);
+ err_ret = -ENOMEM;
+ ++smem_idx;
+ goto smem_failed;
+ }
+ }
+ sort(smem_areas, num_smem_areas,
+ sizeof(struct smem_area),
+ sort_cmp_func, NULL);
+ }
+
for (i = 0; i < num_ss; i++) {
cfg = &smd_ss_config_list[i];
@@ -3145,46 +3306,53 @@
err_ret = ret;
pr_err("smd: register irq failed on %s\n",
cfg->smd_int.irq_name);
- break;
+ goto intr_failed;
}
- ret = intr_init(
- &private_intr_config[cfg->irq_config_id].smsm,
- &cfg->smsm_int,
- pdev
- );
+ /* only init smsm structs if this edge supports smsm */
+ if (cfg->smsm_int.irq_id)
+ ret = intr_init(
+ &private_intr_config[cfg->irq_config_id].smsm,
+ &cfg->smsm_int,
+ pdev
+ );
if (ret < 0) {
err_ret = ret;
pr_err("smd: register irq failed on %s\n",
cfg->smsm_int.irq_name);
- break;
+ goto intr_failed;
}
- strncpy(edge_to_pids[cfg->edge].subsys_name,
+ if (cfg->subsys_name)
+ strlcpy(edge_to_pids[cfg->edge].subsys_name,
cfg->subsys_name, SMD_MAX_CH_NAME_LEN);
}
- if (err_ret < 0) {
- pr_err("smd: deregistering IRQs\n");
- for (i = 0; i < num_ss; ++i) {
- cfg = &smd_ss_config_list[i];
-
- if (cfg->smd_int.irq_id >= 0)
- free_irq(cfg->smd_int.irq_id,
- (void *)cfg->smd_int.dev_id
- );
- if (cfg->smsm_int.irq_id >= 0)
- free_irq(cfg->smsm_int.irq_id,
- (void *)cfg->smsm_int.dev_id
- );
- }
- return err_ret;
- }
SMD_INFO("smd_core_platform_init() done\n");
return 0;
+intr_failed:
+ pr_err("smd: deregistering IRQs\n");
+ for (i = 0; i < num_ss; ++i) {
+ cfg = &smd_ss_config_list[i];
+
+ if (cfg->smd_int.irq_id >= 0)
+ free_irq(cfg->smd_int.irq_id,
+ (void *)cfg->smd_int.dev_id
+ );
+ if (cfg->smsm_int.irq_id >= 0)
+ free_irq(cfg->smsm_int.irq_id,
+ (void *)cfg->smsm_int.dev_id
+ );
+ }
+smem_failed:
+ for (smem_idx = smem_idx - 1; smem_idx >= 0; --smem_idx)
+ iounmap(smem_areas[smem_idx].virt_addr);
+ kfree(smem_areas);
+smem_areas_alloc_fail:
+ return err_ret;
}
static int __devinit msm_smd_probe(struct platform_device *pdev)
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
index 764102d..5dce1ac 100644
--- a/arch/arm/mach-msm/smd_debug.c
+++ b/arch/arm/mach-msm/smd_debug.c
@@ -248,8 +248,9 @@
}
static int dump_ch(char *buf, int max, int n,
- struct smd_half_channel *s,
- struct smd_half_channel *r,
+ void *half_ch_s,
+ void *half_ch_r,
+ struct smd_half_channel_access *half_ch_funcs,
unsigned size)
{
return scnprintf(
@@ -257,24 +258,28 @@
"ch%02d:"
" %8s(%04d/%04d) %c%c%c%c%c%c%c%c <->"
" %8s(%04d/%04d) %c%c%c%c%c%c%c%c : %5x\n", n,
- chstate(s->state), s->tail, s->head,
- s->fDSR ? 'D' : 'd',
- s->fCTS ? 'C' : 'c',
- s->fCD ? 'C' : 'c',
- s->fRI ? 'I' : 'i',
- s->fHEAD ? 'W' : 'w',
- s->fTAIL ? 'R' : 'r',
- s->fSTATE ? 'S' : 's',
- s->fBLOCKREADINTR ? 'B' : 'b',
- chstate(r->state), r->tail, r->head,
- r->fDSR ? 'D' : 'd',
- r->fCTS ? 'R' : 'r',
- r->fCD ? 'C' : 'c',
- r->fRI ? 'I' : 'i',
- r->fHEAD ? 'W' : 'w',
- r->fTAIL ? 'R' : 'r',
- r->fSTATE ? 'S' : 's',
- r->fBLOCKREADINTR ? 'B' : 'b',
+ chstate(half_ch_funcs->get_state(half_ch_s)),
+ half_ch_funcs->get_tail(half_ch_s),
+ half_ch_funcs->get_head(half_ch_s),
+ half_ch_funcs->get_fDSR(half_ch_s) ? 'D' : 'd',
+ half_ch_funcs->get_fCTS(half_ch_s) ? 'C' : 'c',
+ half_ch_funcs->get_fCD(half_ch_s) ? 'C' : 'c',
+ half_ch_funcs->get_fRI(half_ch_s) ? 'I' : 'i',
+ half_ch_funcs->get_fHEAD(half_ch_s) ? 'W' : 'w',
+ half_ch_funcs->get_fTAIL(half_ch_s) ? 'R' : 'r',
+ half_ch_funcs->get_fSTATE(half_ch_s) ? 'S' : 's',
+ half_ch_funcs->get_fBLOCKREADINTR(half_ch_s) ? 'B' : 'b',
+ chstate(half_ch_funcs->get_state(half_ch_r)),
+ half_ch_funcs->get_tail(half_ch_r),
+ half_ch_funcs->get_head(half_ch_r),
+ half_ch_funcs->get_fDSR(half_ch_r) ? 'D' : 'd',
+ half_ch_funcs->get_fCTS(half_ch_r) ? 'C' : 'c',
+ half_ch_funcs->get_fCD(half_ch_r) ? 'C' : 'c',
+ half_ch_funcs->get_fRI(half_ch_r) ? 'I' : 'i',
+ half_ch_funcs->get_fHEAD(half_ch_r) ? 'W' : 'w',
+ half_ch_funcs->get_fTAIL(half_ch_r) ? 'R' : 'r',
+ half_ch_funcs->get_fSTATE(half_ch_r) ? 'S' : 's',
+ half_ch_funcs->get_fBLOCKREADINTR(half_ch_r) ? 'B' : 'b',
size
);
}
@@ -542,19 +547,33 @@
{
void *shared;
int n, i = 0;
+ struct smd_alloc_elm *ch_tbl;
+ unsigned ch_type;
+ unsigned shared_size;
+
+ ch_tbl = smem_find(ID_CH_ALLOC_TBL, sizeof(*ch_tbl) * 64);
+ if (!ch_tbl)
+ goto fail;
for (n = 0; n < SMD_CHANNELS; n++) {
+ ch_type = SMD_CHANNEL_TYPE(ch_tbl[n].type);
+ if (is_word_access_ch(ch_type))
+ shared_size =
+ sizeof(struct smd_half_channel_word_access);
+ else
+ shared_size = sizeof(struct smd_half_channel);
shared = smem_find(ID_SMD_CHANNELS + n,
- 2 * (sizeof(struct smd_half_channel) +
- SMD_BUF_SIZE));
+ 2 * shared_size + SMD_BUF_SIZE);
if (shared == 0)
continue;
i += dump_ch(buf + i, max - i, n, shared,
- (shared + sizeof(struct smd_half_channel) +
- SMD_BUF_SIZE), SMD_BUF_SIZE);
+ (shared + shared_size +
+ SMD_BUF_SIZE), get_half_ch_funcs(ch_type),
+ SMD_BUF_SIZE);
}
+fail:
return i;
}
#else
@@ -563,10 +582,23 @@
void *shared, *buffer;
unsigned buffer_sz;
int n, i = 0;
+ struct smd_alloc_elm *ch_tbl;
+ unsigned ch_type;
+ unsigned shared_size;
+
+ ch_tbl = smem_find(ID_CH_ALLOC_TBL, sizeof(*ch_tbl) * 64);
+ if (!ch_tbl)
+ goto fail;
for (n = 0; n < SMD_CHANNELS; n++) {
- shared = smem_find(ID_SMD_CHANNELS + n,
- 2 * sizeof(struct smd_half_channel));
+ ch_type = SMD_CHANNEL_TYPE(ch_tbl[n].type);
+ if (is_word_access_ch(ch_type))
+ shared_size =
+ sizeof(struct smd_half_channel_word_access);
+ else
+ shared_size = sizeof(struct smd_half_channel);
+
+ shared = smem_find(ID_SMD_CHANNELS + n, 2 * shared_size);
if (shared == 0)
continue;
@@ -577,10 +609,12 @@
continue;
i += dump_ch(buf + i, max - i, n, shared,
- (shared + sizeof(struct smd_half_channel)),
+ (shared + shared_size),
+ get_half_ch_funcs(ch_type),
buffer_sz / 2);
}
+fail:
return i;
}
#endif
diff --git a/arch/arm/mach-msm/smd_private.c b/arch/arm/mach-msm/smd_private.c
new file mode 100644
index 0000000..5a78b6f
--- /dev/null
+++ b/arch/arm/mach-msm/smd_private.c
@@ -0,0 +1,303 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "smd_private.h"
+
+void set_state(volatile void *half_channel, unsigned data)
+{
+ ((struct smd_half_channel *)(half_channel))->state = data;
+}
+
+unsigned get_state(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->state;
+}
+
+void set_fDSR(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fDSR = data;
+}
+
+unsigned get_fDSR(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fDSR;
+}
+
+void set_fCTS(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fCTS = data;
+}
+
+unsigned get_fCTS(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fCTS;
+}
+
+void set_fCD(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fCD = data;
+}
+
+unsigned get_fCD(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fCD;
+}
+
+void set_fRI(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fRI = data;
+}
+
+unsigned get_fRI(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fRI;
+}
+
+void set_fHEAD(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fHEAD = data;
+}
+
+unsigned get_fHEAD(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fHEAD;
+}
+
+void set_fTAIL(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fTAIL = data;
+}
+
+unsigned get_fTAIL(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fTAIL;
+}
+
+void set_fSTATE(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fSTATE = data;
+}
+
+unsigned get_fSTATE(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fSTATE;
+}
+
+void set_fBLOCKREADINTR(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel *)(half_channel))->fBLOCKREADINTR = data;
+}
+
+unsigned get_fBLOCKREADINTR(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->fBLOCKREADINTR;
+}
+
+void set_tail(volatile void *half_channel, unsigned data)
+{
+ ((struct smd_half_channel *)(half_channel))->tail = data;
+}
+
+unsigned get_tail(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->tail;
+}
+
+void set_head(volatile void *half_channel, unsigned data)
+{
+ ((struct smd_half_channel *)(half_channel))->head = data;
+}
+
+unsigned get_head(volatile void *half_channel)
+{
+ return ((struct smd_half_channel *)(half_channel))->head;
+}
+
+void set_state_word_access(volatile void *half_channel, unsigned data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->state = data;
+}
+
+unsigned get_state_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->state;
+}
+
+void set_fDSR_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fDSR = data;
+}
+
+unsigned get_fDSR_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fDSR;
+}
+
+void set_fCTS_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fCTS = data;
+}
+
+unsigned get_fCTS_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fCTS;
+}
+
+void set_fCD_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fCD = data;
+}
+
+unsigned get_fCD_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fCD;
+}
+
+void set_fRI_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fRI = data;
+}
+
+unsigned get_fRI_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fRI;
+}
+
+void set_fHEAD_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fHEAD = data;
+}
+
+unsigned get_fHEAD_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fHEAD;
+}
+
+void set_fTAIL_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fTAIL = data;
+}
+
+unsigned get_fTAIL_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fTAIL;
+}
+
+void set_fSTATE_word_access(volatile void *half_channel, unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->fSTATE = data;
+}
+
+unsigned get_fSTATE_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->fSTATE;
+}
+
+void set_fBLOCKREADINTR_word_access(volatile void *half_channel,
+ unsigned char data)
+{
+ ((struct smd_half_channel_word_access *)
+ (half_channel))->fBLOCKREADINTR = data;
+}
+
+unsigned get_fBLOCKREADINTR_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)
+ (half_channel))->fBLOCKREADINTR;
+}
+
+void set_tail_word_access(volatile void *half_channel, unsigned data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->tail = data;
+}
+
+unsigned get_tail_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->tail;
+}
+
+void set_head_word_access(volatile void *half_channel, unsigned data)
+{
+ ((struct smd_half_channel_word_access *)(half_channel))->head = data;
+}
+
+unsigned get_head_word_access(volatile void *half_channel)
+{
+ return ((struct smd_half_channel_word_access *)(half_channel))->head;
+}
+
+int is_word_access_ch(unsigned ch_type)
+{
+ if (ch_type == SMD_APPS_RPM || ch_type == SMD_MODEM_RPM ||
+ ch_type == SMD_QDSP_RPM || ch_type == SMD_WCNSS_RPM)
+ return 1;
+ else
+ return 0;
+}
+
+struct smd_half_channel_access *get_half_ch_funcs(unsigned ch_type)
+{
+ static struct smd_half_channel_access byte_access = {
+ .set_state = set_state,
+ .get_state = get_state,
+ .set_fDSR = set_fDSR,
+ .get_fDSR = get_fDSR,
+ .set_fCTS = set_fCTS,
+ .get_fCTS = get_fCTS,
+ .set_fCD = set_fCD,
+ .get_fCD = get_fCD,
+ .set_fRI = set_fRI,
+ .get_fRI = get_fRI,
+ .set_fHEAD = set_fHEAD,
+ .get_fHEAD = get_fHEAD,
+ .set_fTAIL = set_fTAIL,
+ .get_fTAIL = get_fTAIL,
+ .set_fSTATE = set_fSTATE,
+ .get_fSTATE = get_fSTATE,
+ .set_fBLOCKREADINTR = set_fBLOCKREADINTR,
+ .get_fBLOCKREADINTR = get_fBLOCKREADINTR,
+ .set_tail = set_tail,
+ .get_tail = get_tail,
+ .set_head = set_head,
+ .get_head = get_head,
+ };
+ static struct smd_half_channel_access word_access = {
+ .set_state = set_state_word_access,
+ .get_state = get_state_word_access,
+ .set_fDSR = set_fDSR_word_access,
+ .get_fDSR = get_fDSR_word_access,
+ .set_fCTS = set_fCTS_word_access,
+ .get_fCTS = get_fCTS_word_access,
+ .set_fCD = set_fCD_word_access,
+ .get_fCD = get_fCD_word_access,
+ .set_fRI = set_fRI_word_access,
+ .get_fRI = get_fRI_word_access,
+ .set_fHEAD = set_fHEAD_word_access,
+ .get_fHEAD = get_fHEAD_word_access,
+ .set_fTAIL = set_fTAIL_word_access,
+ .get_fTAIL = get_fTAIL_word_access,
+ .set_fSTATE = set_fSTATE_word_access,
+ .get_fSTATE = get_fSTATE_word_access,
+ .set_fBLOCKREADINTR = set_fBLOCKREADINTR_word_access,
+ .get_fBLOCKREADINTR = get_fBLOCKREADINTR_word_access,
+ .set_tail = set_tail_word_access,
+ .get_tail = get_tail_word_access,
+ .set_head = set_head_word_access,
+ .get_head = get_head_word_access,
+ };
+
+ if (is_word_access_ch(ch_type))
+ return &word_access;
+ else
+ return &byte_access;
+}
+
diff --git a/arch/arm/mach-msm/smd_private.h b/arch/arm/mach-msm/smd_private.h
index e39c57b..6ffd5d2 100644
--- a/arch/arm/mach-msm/smd_private.h
+++ b/arch/arm/mach-msm/smd_private.h
@@ -44,8 +44,9 @@
unsigned allocated;
unsigned offset;
unsigned size;
- unsigned reserved;
+ unsigned reserved; /* bits 1:0 reserved, bits 31:2 aux smem base addr */
};
+#define BASE_ADDR_MASK 0xfffffffc
struct smem_proc_comm {
unsigned command;
@@ -134,6 +135,50 @@
unsigned head;
};
+struct smd_half_channel_word_access {
+ unsigned state;
+ unsigned fDSR;
+ unsigned fCTS;
+ unsigned fCD;
+ unsigned fRI;
+ unsigned fHEAD;
+ unsigned fTAIL;
+ unsigned fSTATE;
+ unsigned fBLOCKREADINTR;
+ unsigned tail;
+ unsigned head;
+};
+
+struct smd_half_channel_access {
+ void (*set_state)(volatile void *half_channel, unsigned data);
+ unsigned (*get_state)(volatile void *half_channel);
+ void (*set_fDSR)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fDSR)(volatile void *half_channel);
+ void (*set_fCTS)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fCTS)(volatile void *half_channel);
+ void (*set_fCD)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fCD)(volatile void *half_channel);
+ void (*set_fRI)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fRI)(volatile void *half_channel);
+ void (*set_fHEAD)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fHEAD)(volatile void *half_channel);
+ void (*set_fTAIL)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fTAIL)(volatile void *half_channel);
+ void (*set_fSTATE)(volatile void *half_channel, unsigned char data);
+ unsigned (*get_fSTATE)(volatile void *half_channel);
+ void (*set_fBLOCKREADINTR)(volatile void *half_channel,
+ unsigned char data);
+ unsigned (*get_fBLOCKREADINTR)(volatile void *half_channel);
+ void (*set_tail)(volatile void *half_channel, unsigned data);
+ unsigned (*get_tail)(volatile void *half_channel);
+ void (*set_head)(volatile void *half_channel, unsigned data);
+ unsigned (*get_head)(volatile void *half_channel);
+};
+
+int is_word_access_ch(unsigned ch_type);
+
+struct smd_half_channel_access *get_half_ch_funcs(unsigned ch_type);
+
struct smem_ram_ptn {
char name[16];
unsigned start;
diff --git a/arch/arm/mach-msm/sysmon.c b/arch/arm/mach-msm/sysmon.c
index 3d3824a..ddb8502 100644
--- a/arch/arm/mach-msm/sysmon.c
+++ b/arch/arm/mach-msm/sysmon.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -24,20 +24,34 @@
#include <mach/msm_smd.h>
#include <mach/subsystem_notif.h>
+#include "hsic_sysmon.h"
#include "sysmon.h"
#define MAX_MSG_LENGTH 50
#define TIMEOUT_MS 5000
+enum transports {
+ TRANSPORT_SMD,
+ TRANSPORT_HSIC,
+};
+
struct sysmon_subsys {
struct mutex lock;
struct smd_channel *chan;
bool chan_open;
struct completion resp_ready;
char rx_buf[MAX_MSG_LENGTH];
+ enum transports transport;
};
-static struct sysmon_subsys subsys[SYSMON_NUM_SS];
+static struct sysmon_subsys subsys[SYSMON_NUM_SS] = {
+ [SYSMON_SS_MODEM].transport = TRANSPORT_SMD,
+ [SYSMON_SS_LPASS].transport = TRANSPORT_SMD,
+ [SYSMON_SS_WCNSS].transport = TRANSPORT_SMD,
+ [SYSMON_SS_DSPS].transport = TRANSPORT_SMD,
+ [SYSMON_SS_Q6FW].transport = TRANSPORT_SMD,
+ [SYSMON_SS_EXT_MODEM].transport = TRANSPORT_HSIC,
+};
static const char *notif_name[SUBSYS_NOTIF_TYPE_COUNT] = {
[SUBSYS_BEFORE_SHUTDOWN] = "before_shutdown",
@@ -46,6 +60,39 @@
[SUBSYS_AFTER_POWERUP] = "after_powerup",
};
+static int sysmon_send_smd(struct sysmon_subsys *ss, char *tx_buf, size_t len)
+{
+ int ret;
+
+ if (!ss->chan_open)
+ return -ENODEV;
+
+ init_completion(&ss->resp_ready);
+ pr_debug("Sending SMD message: %s\n", tx_buf);
+ smd_write(ss->chan, tx_buf, len);
+ ret = wait_for_completion_timeout(&ss->resp_ready,
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int sysmon_send_hsic(struct sysmon_subsys *ss, char *tx_buf, size_t len)
+{
+ int ret;
+ size_t actual_len;
+
+ pr_debug("Sending HSIC message: %s\n", tx_buf);
+ ret = hsic_sysmon_write(HSIC_SYSMON_DEV_EXT_MODEM,
+ tx_buf, len, TIMEOUT_MS);
+ if (ret)
+ return ret;
+ ret = hsic_sysmon_read(HSIC_SYSMON_DEV_EXT_MODEM, ss->rx_buf,
+ ARRAY_SIZE(ss->rx_buf), &actual_len, TIMEOUT_MS);
+ return ret;
+}
+
int sysmon_send_event(enum subsys_id dest_ss, const char *event_ss,
enum subsys_notif_type notif)
{
@@ -58,31 +105,34 @@
event_ss == NULL)
return -EINVAL;
- if (!ss->chan_open)
- return -ENODEV;
-
- mutex_lock(&ss->lock);
- init_completion(&ss->resp_ready);
snprintf(tx_buf, ARRAY_SIZE(tx_buf), "ssr:%s:%s", event_ss,
notif_name[notif]);
- pr_debug("Sending message: %s\n", tx_buf);
- smd_write(ss->chan, tx_buf, ARRAY_SIZE(tx_buf));
- ret = wait_for_completion_timeout(&ss->resp_ready,
- msecs_to_jiffies(TIMEOUT_MS));
- if (!ret) {
- ret = -ETIMEDOUT;
- } else if (strncmp(ss->rx_buf, "ssr:ack", ARRAY_SIZE(ss->rx_buf))) {
- pr_debug("Received response: %s\n", ss->rx_buf);
- ret = -ENOSYS;
- } else {
- ret = 0;
- }
- mutex_unlock(&ss->lock);
+ mutex_lock(&ss->lock);
+ switch (ss->transport) {
+ case TRANSPORT_SMD:
+ ret = sysmon_send_smd(ss, tx_buf, ARRAY_SIZE(tx_buf));
+ break;
+ case TRANSPORT_HSIC:
+ ret = sysmon_send_hsic(ss, tx_buf, ARRAY_SIZE(tx_buf));
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ if (ret)
+ goto out;
+
+ pr_debug("Received response: %s\n", ss->rx_buf);
+ if (strncmp(ss->rx_buf, "ssr:ack", ARRAY_SIZE(ss->rx_buf)))
+ ret = -ENOSYS;
+ else
+ ret = 0;
+out:
+ mutex_unlock(&ss->lock);
return ret;
}
-static void sysmon_notify(void *priv, unsigned int smd_event)
+static void sysmon_smd_notify(void *priv, unsigned int smd_event)
{
struct sysmon_subsys *ss = priv;
@@ -104,44 +154,61 @@
}
}
-static const uint32_t ss_map[SMD_NUM_TYPE] = {
- [SMD_APPS_MODEM] = SYSMON_SS_MODEM,
- [SMD_APPS_QDSP] = SYSMON_SS_LPASS,
- [SMD_APPS_WCNSS] = SYSMON_SS_WCNSS,
- [SMD_APPS_DSPS] = SYSMON_SS_DSPS,
- [SMD_APPS_Q6FW] = SYSMON_SS_Q6FW,
-};
-
static int sysmon_probe(struct platform_device *pdev)
{
struct sysmon_subsys *ss;
int ret;
- if (pdev == NULL)
- return -EINVAL;
-
- if (pdev->id < 0 || pdev->id >= SMD_NUM_TYPE ||
- ss_map[pdev->id] < 0 || ss_map[pdev->id] >= SYSMON_NUM_SS)
+ if (pdev->id < 0 || pdev->id >= SYSMON_NUM_SS)
return -ENODEV;
- ss = &subsys[ss_map[pdev->id]];
+ ss = &subsys[pdev->id];
mutex_init(&ss->lock);
- /* Open and configure the SMD channel */
- ret = smd_named_open_on_edge("sys_mon", pdev->id, &ss->chan,
- ss, sysmon_notify);
- if (ret) {
- pr_err("SMD open failed\n");
- return -ENOSYS;
+ switch (ss->transport) {
+ case TRANSPORT_SMD:
+ if (pdev->id >= SMD_NUM_TYPE)
+ return -EINVAL;
+
+ ret = smd_named_open_on_edge("sys_mon", pdev->id, &ss->chan, ss,
+ sysmon_smd_notify);
+ if (ret) {
+ pr_err("SMD open failed\n");
+ return ret;
+ }
+
+ smd_disable_read_intr(ss->chan);
+ break;
+ case TRANSPORT_HSIC:
+ if (pdev->id < SMD_NUM_TYPE)
+ return -EINVAL;
+
+ ret = hsic_sysmon_open(HSIC_SYSMON_DEV_EXT_MODEM);
+ if (ret) {
+ pr_err("HSIC open failed\n");
+ return ret;
+ }
+ break;
+ default:
+ return -EINVAL;
}
- smd_disable_read_intr(ss->chan);
return 0;
}
static int __devexit sysmon_remove(struct platform_device *pdev)
{
- smd_close(subsys[ss_map[pdev->id]].chan);
+ struct sysmon_subsys *ss = &subsys[pdev->id];
+
+ switch (ss->transport) {
+ case TRANSPORT_SMD:
+ smd_close(ss->chan);
+ break;
+ case TRANSPORT_HSIC:
+ hsic_sysmon_close(HSIC_SYSMON_DEV_EXT_MODEM);
+ break;
+ }
+
return 0;
}
diff --git a/arch/arm/mach-msm/sysmon.h b/arch/arm/mach-msm/sysmon.h
index 429a155..d014187 100644
--- a/arch/arm/mach-msm/sysmon.h
+++ b/arch/arm/mach-msm/sysmon.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -15,21 +15,25 @@
#ifndef __MSM_SYSMON_H
#define __MSM_SYSMON_H
+#include <mach/msm_smd.h>
#include <mach/subsystem_notif.h>
/**
* enum subsys_id - Destination subsystems for events.
*/
enum subsys_id {
- SYSMON_SS_MODEM,
- SYSMON_SS_LPASS,
- SYSMON_SS_WCNSS,
- SYSMON_SS_DSPS,
- SYSMON_SS_Q6FW,
+ /* SMD subsystems */
+ SYSMON_SS_MODEM = SMD_APPS_MODEM,
+ SYSMON_SS_LPASS = SMD_APPS_QDSP,
+ SYSMON_SS_WCNSS = SMD_APPS_WCNSS,
+ SYSMON_SS_DSPS = SMD_APPS_DSPS,
+ SYSMON_SS_Q6FW = SMD_APPS_Q6FW,
+
+ /* Non-SMD subsystems */
+ SYSMON_SS_EXT_MODEM = SMD_NUM_TYPE,
SYSMON_NUM_SS
};
-
/**
* sysmon_send_event() - Notify a subsystem of another's state change.
* @dest_ss: ID of subsystem the notification should be sent to.
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index b3b2b52..2e422c4 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -358,8 +358,6 @@
membank0_size = meminfo.bank[0].size;
membank1_start = meminfo.bank[1].start;
-
- pr_info("m0 size %lx m1 start %lx\n", membank0_size, membank1_start);
}
#endif
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 14cdf13..0364b06 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -1745,8 +1745,10 @@
*/
list_del_init(&dev->kobj.entry);
spin_unlock(&devices_kset->list_lock);
- /* Disable all device's runtime power management */
- pm_runtime_disable(dev);
+
+ /* Don't allow any more runtime suspends */
+ pm_runtime_get_noresume(dev);
+ pm_runtime_barrier(dev);
if (dev->bus && dev->bus->shutdown) {
dev_dbg(dev, "shutdown\n");
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 42befd1..8a46a2e 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -248,13 +248,16 @@
*/
if (action == MEM_ONLINE) {
for (i = 0; i < nr_pages; i++) {
- if (PageReserved(first_page+i))
- continue;
-
- printk(KERN_WARNING "section number %ld page number %d "
- "not reserved, was it already online?\n",
- phys_index, i);
- return -EBUSY;
+ if (page_is_ram(page_to_pfn(first_page+i))) {
+ if (PageReserved(first_page+i))
+ continue;
+ printk(KERN_WARNING
+ "section number %ld page number"
+ " %d not reserved, was it "
+ " already online?\n",
+ phys_index, i);
+ return -EBUSY;
+ }
}
}
diff --git a/drivers/char/diag/Makefile b/drivers/char/diag/Makefile
index c62b7fd..3181d29 100644
--- a/drivers/char/diag/Makefile
+++ b/drivers/char/diag/Makefile
@@ -1,4 +1,4 @@
obj-$(CONFIG_DIAG_CHAR) := diagchar.o
obj-$(CONFIG_DIAG_SDIO_PIPE) += diagfwd_sdio.o
obj-$(CONFIG_DIAG_HSIC_PIPE) += diagfwd_hsic.o
-diagchar-objs := diagchar_core.o diagchar_hdlc.o diagfwd.o diagmem.o diagfwd_cntl.o
+diagchar-objs := diagchar_core.o diagchar_hdlc.o diagfwd.o diagmem.o diagfwd_cntl.o diag_dci.o
diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c
new file mode 100644
index 0000000..5cbf888
--- /dev/null
+++ b/drivers/char/diag/diag_dci.c
@@ -0,0 +1,335 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/diagchar.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+#include <linux/workqueue.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <asm/current.h>
+#ifdef CONFIG_DIAG_OVER_USB
+#include <mach/usbdiag.h>
+#endif
+#include "diagchar_hdlc.h"
+#include "diagmem.h"
+#include "diagchar.h"
+#include "diagfwd.h"
+#include "diag_dci.h"
+
+unsigned int dci_max_reg = 100;
+unsigned int dci_max_clients = 10;
+
+static void diag_smd_dci_send_req(int proc_num)
+{
+ void *buf = NULL;
+ smd_channel_t *smd_ch = NULL;
+ int i, r, found = 1;
+ int cmd_code_len = 1;
+
+ if (driver->in_busy_dci)
+ return;
+
+ if (proc_num == MODEM_PROC) {
+ buf = driver->buf_in_dci;
+ smd_ch = driver->ch_dci;
+ }
+
+ if (!smd_ch || !buf)
+ return;
+
+ r = smd_read_avail(smd_ch);
+ if (r > IN_BUF_SIZE) {
+ if (r < MAX_IN_BUF_SIZE) {
+ pr_err("diag: SMD DCI sending pkt upto %d bytes", r);
+ buf = krealloc(buf, r, GFP_KERNEL);
+ } else {
+ pr_err("diag: DCI pkt > %d bytes", MAX_IN_BUF_SIZE);
+ return;
+ }
+ }
+ if (buf && r > 0) {
+ smd_read(smd_ch, buf, r);
+ pr_debug("diag: data received ---\n");
+ for (i = 0; i < r; i++)
+ pr_debug("\t %x \t", *(((unsigned char *)buf)+i));
+
+ if (*(uint8_t *)(buf+4) != DCI_CMD_CODE)
+ cmd_code_len = 4; /* delayed response */
+ driver->write_ptr_dci->length =
+ (int)(*(uint16_t *)(buf+2)) - (4+cmd_code_len);
+ pr_debug("diag: len = %d\n", (int)(*(uint16_t *)(buf+2))
+ - (4+cmd_code_len));
+ /* look up DCI client with tag */
+ for (i = 0; i < dci_max_reg; i++) {
+ if (driver->dci_tbl[i].tag ==
+ *(int *)(buf+(4+cmd_code_len))) {
+ found = 0;
+ break;
+ }
+ }
+ if (found)
+ pr_alert("diag: No matching PID for DCI data\n");
+ pr_debug("\n diag PID = %d", driver->dci_tbl[i].pid);
+ if (driver->dci_tbl[i].pid == 0)
+ pr_alert("diag: Receiving DCI process deleted\n");
+ *(int *)(buf+4+cmd_code_len) = driver->dci_tbl[i].uid;
+ /* update len after adding UID */
+ driver->write_ptr_dci->length =
+ driver->write_ptr_dci->length + 4;
+ pr_debug("diag: data receivd, wake process\n");
+ driver->in_busy_dci = 1;
+ diag_update_sleeping_process(driver->dci_tbl[i].pid,
+ DCI_DATA_TYPE);
+ /* delete immediate response entry */
+ if (driver->buf_in_dci[8+cmd_code_len] != 0x80)
+ driver->dci_tbl[i].pid = 0;
+ for (i = 0; i < dci_max_reg; i++)
+ if (driver->dci_tbl[i].pid != 0)
+ pr_debug("diag: PID = %d, UID = %d, tag = %d\n",
+ driver->dci_tbl[i].pid, driver->dci_tbl[i].uid,
+ driver->dci_tbl[i].tag);
+ pr_debug("diag: completed clearing table\n");
+ }
+}
+
+void diag_read_smd_dci_work_fn(struct work_struct *work)
+{
+ diag_smd_dci_send_req(MODEM_PROC);
+}
+
+static void diag_smd_dci_notify(void *ctxt, unsigned event)
+{
+ queue_work(driver->diag_wq, &(driver->diag_read_smd_dci_work));
+}
+
+static int diag_dci_probe(struct platform_device *pdev)
+{
+ int err = 0;
+
+ if (pdev->id == SMD_APPS_MODEM) {
+ err = smd_open("DIAG_2", &driver->ch_dci, driver,
+ diag_smd_dci_notify);
+ if (err)
+ pr_err("diag: cannot open DCI port, Id = %d, err ="
+ " %d\n", pdev->id, err);
+ }
+ return err;
+}
+
+
+int diag_send_dci_pkt(struct diag_master_table entry, unsigned char *buf,
+ int len, int index)
+{
+ int i;
+
+ /* remove UID from user space pkt before sending to peripheral */
+ buf = buf + 4;
+ len = len - 4;
+ mutex_lock(&driver->dci_mutex);
+ /* prepare DCI packet */
+ driver->apps_dci_buf[0] = CONTROL_CHAR; /* start */
+ driver->apps_dci_buf[1] = 1; /* version */
+ *(uint16_t *)(driver->apps_dci_buf + 2) = len + 4 + 1; /* length */
+ driver->apps_dci_buf[4] = DCI_CMD_CODE; /* DCI ID */
+ *(int *)(driver->apps_dci_buf + 5) = driver->dci_tbl[index].tag;
+ for (i = 0; i < len; i++)
+ driver->apps_dci_buf[i+9] = *(buf+i);
+ driver->apps_dci_buf[9+len] = CONTROL_CHAR; /* end */
+
+ if (entry.client_id == MODEM_PROC && driver->ch_dci) {
+ smd_write(driver->ch_dci, driver->apps_dci_buf, len + 10);
+ i = DIAG_DCI_NO_ERROR;
+ } else {
+ pr_alert("diag: check DCI channel\n");
+ i = DIAG_DCI_SEND_DATA_FAIL;
+ }
+ mutex_unlock(&driver->dci_mutex);
+ return i;
+}
+
+int diag_register_dci_transaction(int uid)
+{
+ int i, new_dci_client = 1, ret = -1;
+
+ for (i = 0; i < dci_max_reg; i++) {
+ if (driver->dci_tbl[i].pid == current->tgid) {
+ new_dci_client = 0;
+ break;
+ }
+ }
+ mutex_lock(&driver->dci_mutex);
+ if (new_dci_client)
+ driver->num_dci_client++;
+ if (driver->num_dci_client > MAX_DCI_CLIENT) {
+ pr_info("diag: Max DCI Client limit reached\n");
+ driver->num_dci_client--;
+ mutex_unlock(&driver->dci_mutex);
+ return ret;
+ }
+ /* Make an entry in kernel DCI table */
+ driver->dci_tag++;
+ for (i = 0; i < dci_max_reg; i++) {
+ if (driver->dci_tbl[i].pid == 0) {
+ driver->dci_tbl[i].pid = current->tgid;
+ driver->dci_tbl[i].uid = uid;
+ driver->dci_tbl[i].tag = driver->dci_tag;
+ ret = i;
+ break;
+ }
+ }
+ mutex_unlock(&driver->dci_mutex);
+ return ret;
+}
+
+int diag_process_dci_client(unsigned char *buf, int len)
+{
+ unsigned char *temp = buf;
+ uint16_t subsys_cmd_code;
+ int subsys_id, cmd_code, i, ret = -1, index = -1;
+ struct diag_master_table entry;
+
+ /* enter this UID into kernel table and return index */
+ index = diag_register_dci_transaction(*(int *)temp);
+ if (index < 0) {
+ pr_alert("diag: registering new DCI transaction failed\n");
+ return DIAG_DCI_NO_REG;
+ }
+ temp += 4;
+ /* Check for registered peripheral and fwd pkt to apropriate proc */
+ cmd_code = (int)(*(char *)buf);
+ temp++;
+ subsys_id = (int)(*(char *)temp);
+ temp++;
+ subsys_cmd_code = *(uint16_t *)temp;
+ temp += 2;
+ pr_debug("diag: %d %d %d", cmd_code, subsys_id, subsys_cmd_code);
+ for (i = 0; i < diag_max_reg; i++) {
+ entry = driver->table[i];
+ if (entry.process_id != NO_PROCESS) {
+ if (entry.cmd_code == cmd_code && entry.subsys_id ==
+ subsys_id && entry.cmd_code_lo <=
+ subsys_cmd_code &&
+ entry.cmd_code_hi >= subsys_cmd_code) {
+ ret = diag_send_dci_pkt(entry, buf, len, index);
+ } else if (entry.cmd_code == 255
+ && cmd_code == 75) {
+ if (entry.subsys_id ==
+ subsys_id &&
+ entry.cmd_code_lo <=
+ subsys_cmd_code &&
+ entry.cmd_code_hi >=
+ subsys_cmd_code) {
+ ret = diag_send_dci_pkt(entry, buf, len,
+ index);
+ }
+ } else if (entry.cmd_code == 255 &&
+ entry.subsys_id == 255) {
+ if (entry.cmd_code_lo <=
+ cmd_code &&
+ entry.
+ cmd_code_hi >= cmd_code) {
+ ret = diag_send_dci_pkt(entry, buf, len,
+ index);
+ }
+ }
+ }
+ }
+ return ret;
+}
+
+static int diag_dci_runtime_suspend(struct device *dev)
+{
+ dev_dbg(dev, "pm_runtime: suspending...\n");
+ return 0;
+}
+
+static int diag_dci_runtime_resume(struct device *dev)
+{
+ dev_dbg(dev, "pm_runtime: resuming...\n");
+ return 0;
+}
+
+static const struct dev_pm_ops diag_dci_dev_pm_ops = {
+ .runtime_suspend = diag_dci_runtime_suspend,
+ .runtime_resume = diag_dci_runtime_resume,
+};
+
+struct platform_driver msm_diag_dci_driver = {
+ .probe = diag_dci_probe,
+ .driver = {
+ .name = "DIAG_2",
+ .owner = THIS_MODULE,
+ .pm = &diag_dci_dev_pm_ops,
+ },
+};
+
+int diag_dci_init(void)
+{
+ int success = 0;
+
+ driver->dci_tag = 0;
+ driver->dci_client_id = 0;
+ driver->num_dci_client = 0;
+ driver->in_busy_dci = 0;
+ mutex_init(&driver->dci_mutex);
+ if (driver->buf_in_dci == NULL) {
+ driver->buf_in_dci = kzalloc(IN_BUF_SIZE, GFP_KERNEL);
+ if (driver->buf_in_dci == NULL)
+ goto err;
+ }
+ if (driver->write_ptr_dci == NULL) {
+ driver->write_ptr_dci = kzalloc(
+ sizeof(struct diag_write_device), GFP_KERNEL);
+ if (driver->write_ptr_dci == NULL)
+ goto err;
+ }
+ if (driver->dci_tbl == NULL) {
+ driver->dci_tbl = kzalloc(dci_max_reg *
+ sizeof(struct diag_dci_tbl), GFP_KERNEL);
+ if (driver->dci_tbl == NULL)
+ goto err;
+ }
+ if (driver->apps_dci_buf == NULL) {
+ driver->apps_dci_buf = kzalloc(APPS_BUF_SIZE, GFP_KERNEL);
+ if (driver->apps_dci_buf == NULL)
+ goto err;
+ }
+ success = platform_driver_register(&msm_diag_dci_driver);
+ if (success) {
+ pr_err("diag: Could not register DCI driver\n");
+ goto err;
+ }
+ return DIAG_DCI_NO_ERROR;
+err:
+ pr_err("diag: Could not initialize diag DCI buffers");
+ kfree(driver->dci_tbl);
+ kfree(driver->apps_dci_buf);
+ kfree(driver->buf_in_dci);
+ kfree(driver->write_ptr_dci);
+ return DIAG_DCI_NO_REG;
+}
+
+void diag_dci_exit(void)
+{
+ smd_close(driver->ch_dci);
+ driver->ch_dci = 0;
+ platform_driver_unregister(&msm_diag_dci_driver);
+ kfree(driver->dci_tbl);
+ kfree(driver->apps_dci_buf);
+ kfree(driver->buf_in_dci);
+ kfree(driver->write_ptr_dci);
+}
+
diff --git a/drivers/char/diag/diag_dci.h b/drivers/char/diag/diag_dci.h
new file mode 100644
index 0000000..cc6e0cf
--- /dev/null
+++ b/drivers/char/diag/diag_dci.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef DIAG_DCI_H
+#define DIAG_DCI_H
+#define MAX_DCI_CLIENT 10
+#define DCI_CMD_CODE 0x93
+
+extern unsigned int dci_max_reg;
+extern unsigned int dci_max_clients;
+struct diag_dci_tbl {
+ int pid;
+ int uid;
+ int tag;
+};
+
+#define DIAG_CON_APSS (0x0001) /* Bit mask for APSS */
+#define DIAG_CON_MPSS (0x0002) /* Bit mask for MPSS */
+#define DIAG_CON_LPASS (0x0004) /* Bit mask for LPASS */
+#define DIAG_CON_WCNSS (0x0008) /* Bit mask for WCNSS */
+
+enum {
+ DIAG_DCI_NO_ERROR = 1001, /* No error */
+ DIAG_DCI_NO_REG, /* Could not register */
+ DIAG_DCI_NO_MEM, /* Failed memory allocation */
+ DIAG_DCI_NOT_SUPPORTED, /* This particular client is not supported */
+ DIAG_DCI_HUGE_PACKET, /* Request/Response Packet too huge */
+ DIAG_DCI_SEND_DATA_FAIL,/* writing to kernel or peripheral fails */
+ DIAG_DCI_TABLE_ERR /* Error dealing with registration tables */
+};
+
+int diag_dci_init(void);
+void diag_dci_exit(void);
+void diag_read_smd_dci_work_fn(struct work_struct *);
+int diag_process_dci_client(unsigned char *buf, int len);
+int diag_send_dci_pkt(struct diag_master_table entry, unsigned char *buf,
+ int len, int index);
+#endif
diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h
index 7b63610..d547121 100644
--- a/drivers/char/diag/diagchar.h
+++ b/drivers/char/diag/diagchar.h
@@ -54,6 +54,7 @@
#define DIAG_CTRL_MSG_LOG_MASK 9
#define DIAG_CTRL_MSG_EVENT_MASK 10
#define DIAG_CTRL_MSG_F3_MASK 11
+#define CONTROL_CHAR 0x7E
/* Maximum number of pkt reg supported at initialization*/
extern unsigned int diag_max_reg;
@@ -135,7 +136,14 @@
int polling_reg_flag;
struct diag_write_device *buf_tbl;
int use_device_tree;
-
+ /* DCI related variables */
+ struct diag_dci_tbl *dci_tbl;
+ int dci_tag;
+ int dci_client_id;
+ struct mutex dci_mutex;
+ int num_dci_client;
+ unsigned char *apps_dci_buf;
+ int dci_state;
/* Memory pool parameters */
unsigned int itemsize;
unsigned int poolsize;
@@ -167,6 +175,7 @@
unsigned char *buf_in_wcnss_1;
unsigned char *buf_in_wcnss_2;
unsigned char *buf_in_wcnss_cntl;
+ unsigned char *buf_in_dci;
unsigned char *usb_buf_out;
unsigned char *apps_rsp_buf;
unsigned char *user_space_data;
@@ -176,6 +185,7 @@
unsigned char *buf_event_mask_update;
smd_channel_t *ch;
smd_channel_t *ch_cntl;
+ smd_channel_t *ch_dci;
smd_channel_t *chqdsp;
smd_channel_t *chqdsp_cntl;
smd_channel_t *ch_wcnss;
@@ -186,6 +196,7 @@
int in_busy_qdsp_2;
int in_busy_wcnss_1;
int in_busy_wcnss_2;
+ int in_busy_dci;
int read_len_legacy;
unsigned char *hdlc_buf;
unsigned hdlc_count;
@@ -208,6 +219,7 @@
struct work_struct diag_modem_mask_update_work;
struct work_struct diag_qdsp_mask_update_work;
struct work_struct diag_wcnss_mask_update_work;
+ struct work_struct diag_read_smd_dci_work;
uint8_t *msg_masks;
uint8_t *log_masks;
int log_masks_length;
@@ -223,6 +235,7 @@
struct diag_request *write_ptr_qdsp_2;
struct diag_request *write_ptr_wcnss_1;
struct diag_request *write_ptr_wcnss_2;
+ struct diag_write_device *write_ptr_dci;
int logging_mode;
int mask_check;
int logging_process_id;
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 7e2333a..0a156de 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -28,6 +28,7 @@
#include "diagchar.h"
#include "diagfwd.h"
#include "diagfwd_cntl.h"
+#include "diag_dci.h"
#ifdef CONFIG_DIAG_SDIO_PIPE
#include "diagfwd_sdio.h"
#endif
@@ -222,6 +223,11 @@
return -ENOMEM;
}
+ /* clean up any DCI registrations for this client
+ * This will specially help in case of ungraceful exit of any DCI client
+ * This call will remove any pending registrations of such client
+ */
+ diagchar_ioctl(NULL, DIAG_IOCTL_DCI_DEINIT, 0);
#ifdef CONFIG_DIAG_OVER_USB
/* If the SD logging process exits, change logging to USB mode */
if (driver->logging_process_id == current->tgid) {
@@ -330,6 +336,7 @@
int i, j, count_entries = 0, temp;
int success = -1;
void *temp_buf;
+ uint16_t support_list = 0;
if (iocmd == DIAG_IOCTL_COMMAND_REG) {
struct bindpkt_params_per_process *pkt_params =
@@ -397,6 +404,46 @@
*(delay_params->num_bytes_ptr) = sizeof(delayed_rsp_id);
success = 0;
}
+ } else if (iocmd == DIAG_IOCTL_DCI_REG) {
+ if (driver->dci_state == DIAG_DCI_NO_REG)
+ return DIAG_DCI_NO_REG;
+ /* use the 'list' later on to notify user space */
+ if (driver->num_dci_client >= MAX_DCI_CLIENT)
+ return DIAG_DCI_NO_REG;
+ mutex_lock(&driver->dci_mutex);
+ driver->num_dci_client++;
+ pr_debug("diag: id = %d\n", driver->dci_client_id);
+ driver->dci_client_id++;
+ mutex_unlock(&driver->dci_mutex);
+ return driver->dci_client_id;
+ } else if (iocmd == DIAG_IOCTL_DCI_DEINIT) {
+ success = -1;
+ /* Delete this process from DCI table */
+ mutex_lock(&driver->dci_mutex);
+ for (i = 0; i < dci_max_reg; i++) {
+ if (driver->dci_tbl[i].pid == current->tgid) {
+ pr_debug("diag: delete %d\n", current->tgid);
+ driver->dci_tbl[i].pid = 0;
+ success = i;
+ }
+ }
+ /* if any registrations were deleted successfully OR a valid
+ client_id was sent in DEINIT call , then its DCI client */
+ if (success >= 0 || ioarg)
+ driver->num_dci_client--;
+ driver->num_dci_client--;
+ mutex_unlock(&driver->dci_mutex);
+ for (i = 0; i < dci_max_reg; i++)
+ if (driver->dci_tbl[i].pid != 0)
+ pr_debug("diag: PID = %d, UID = %d, tag = %d\n",
+ driver->dci_tbl[i].pid, driver->dci_tbl[i].uid, driver->dci_tbl[i].tag);
+ pr_debug("diag: complete deleting registrations\n");
+ return success;
+ } else if (iocmd == DIAG_IOCTL_DCI_SUPPORT) {
+ if (driver->ch_dci)
+ support_list = support_list | DIAG_CON_MPSS;
+ *(uint16_t *)ioarg = support_list;
+ return DIAG_DCI_NO_ERROR;
} else if (iocmd == DIAG_IOCTL_LSM_DEINIT) {
for (i = 0; i < driver->num_clients; i++)
if (driver->client_map[i].pid == current->tgid)
@@ -720,6 +767,26 @@
goto exit;
}
+ if (driver->data_ready[index] & DCI_DATA_TYPE) {
+ /*Copy the type of data being passed*/
+ data_type = driver->data_ready[index] & DCI_DATA_TYPE;
+ COPY_USER_SPACE_OR_EXIT(buf, data_type, 4);
+ COPY_USER_SPACE_OR_EXIT(buf+4,
+ driver->write_ptr_dci->length, 4);
+ /* check delayed vs immediate response */
+ if (*(uint8_t *)(driver->buf_in_dci+4) == DCI_CMD_CODE)
+ COPY_USER_SPACE_OR_EXIT(buf+8,
+ *(driver->buf_in_dci + 5), driver->write_ptr_dci->length);
+ else
+ COPY_USER_SPACE_OR_EXIT(buf+8,
+ *(driver->buf_in_dci + 8), driver->write_ptr_dci->length);
+ driver->in_busy_dci = 0;
+ driver->data_ready[index] ^= DCI_DATA_TYPE;
+ if (driver->ch_dci)
+ queue_work(driver->diag_wq,
+ &(driver->diag_read_smd_dci_work));
+ goto exit;
+ }
exit:
mutex_unlock(&driver->diagchar_mutex);
return ret;
@@ -748,6 +815,17 @@
/* First 4 bytes indicate the type of payload - ignore these */
payload_size = count - 4;
+ if (pkt_type == DCI_DATA_TYPE) {
+ err = copy_from_user(driver->user_space_data, buf + 4,
+ payload_size);
+ if (err) {
+ pr_alert("diag: copy failed for DCI data\n");
+ return DIAG_DCI_SEND_DATA_FAIL;
+ }
+ err = diag_process_dci_client(driver->user_space_data,
+ payload_size);
+ return err;
+ }
if (pkt_type == USER_SPACE_LOG_TYPE) {
err = copy_from_user(driver->user_space_data, buf + 4,
payload_size);
@@ -1076,6 +1154,7 @@
driver->used = 0;
timer_in_progress = 0;
driver->debug_flag = 1;
+ driver->dci_state = DIAG_DCI_NO_ERROR;
setup_timer(&drain_timer, drain_timer_func, 1234);
driver->itemsize = itemsize;
driver->poolsize = poolsize;
@@ -1100,8 +1179,11 @@
diag_read_smd_wcnss_work_fn);
INIT_WORK(&(driver->diag_read_smd_wcnss_cntl_work),
diag_read_smd_wcnss_cntl_work_fn);
+ INIT_WORK(&(driver->diag_read_smd_dci_work),
+ diag_read_smd_dci_work_fn);
diagfwd_init();
diagfwd_cntl_init();
+ driver->dci_state = diag_dci_init();
diag_sdio_fn(INIT);
diag_hsic_fn(INIT);
pr_debug("diagchar initializing ..\n");
diff --git a/drivers/char/diag/diagchar_hdlc.c b/drivers/char/diag/diagchar_hdlc.c
index ef57d52..74dcb6b 100644
--- a/drivers/char/diag/diagchar_hdlc.c
+++ b/drivers/char/diag/diagchar_hdlc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2008-2009, 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,7 @@
#include <linux/uaccess.h>
#include <linux/crc-ccitt.h>
#include "diagchar_hdlc.h"
+#include "diagchar.h"
MODULE_LICENSE("GPL v2");
diff --git a/drivers/char/diag/diagchar_hdlc.h b/drivers/char/diag/diagchar_hdlc.h
index 2df81de..116c980 100644
--- a/drivers/char/diag/diagchar_hdlc.h
+++ b/drivers/char/diag/diagchar_hdlc.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2008-2009, 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -54,7 +54,6 @@
int diag_hdlc_decode(struct diag_hdlc_decode_type *hdlc);
#define ESC_CHAR 0x7D
-#define CONTROL_CHAR 0x7E
#define ESC_MASK 0x20
#endif
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index 77d84fd..7066141 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -37,6 +37,8 @@
#ifdef CONFIG_DIAG_SDIO_PIPE
#include "diagfwd_sdio.h"
#endif
+#include "diag_dci.h"
+
#define MODE_CMD 41
#define RESET_ID 2
#define ALL_EQUIP_ID 100
@@ -497,6 +499,29 @@
CREATE_MSG_MASK_TBL_ROW(21);
CREATE_MSG_MASK_TBL_ROW(22);
}
+
+static void diag_set_msg_mask(int rt_mask)
+{
+ int first_ssid, last_ssid, i;
+ uint8_t *parse_ptr, *ptr = driver->msg_masks;
+
+ mutex_lock(&driver->diagchar_mutex);
+ while (*(uint32_t *)(ptr + 4)) {
+ first_ssid = *(uint32_t *)ptr;
+ ptr += 4;
+ last_ssid = *(uint32_t *)ptr;
+ ptr += 4;
+ parse_ptr = ptr;
+ pr_debug("diag: updating range %d %d\n", first_ssid, last_ssid);
+ for (i = 0; i < last_ssid - first_ssid + 1; i++) {
+ *(int *)parse_ptr = rt_mask;
+ parse_ptr += 4;
+ }
+ ptr += MAX_SSID_PER_RANGE * 4;
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
static void diag_update_msg_mask(int start, int end , uint8_t *buf)
{
int found = 0;
@@ -587,6 +612,24 @@
mutex_unlock(&driver->diagchar_mutex);
}
+static void diag_disable_log_mask(void)
+{
+ int i = 0;
+ struct mask_info *parse_ptr = (struct mask_info *)(driver->log_masks);
+
+ pr_debug("diag: disable log masks\n");
+ mutex_lock(&driver->diagchar_mutex);
+ for (i = 0; i < MAX_EQUIP_ID; i++) {
+ pr_debug("diag: equip id %d\n", parse_ptr->equip_id);
+ if (!(parse_ptr->equip_id)) /* Reached a null entry */
+ break;
+ memset(driver->log_masks + parse_ptr->index, 0,
+ (parse_ptr->num_items + 7)/8);
+ parse_ptr++;
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
static void diag_update_log_mask(int equip_id, uint8_t *buf, int num_items)
{
uint8_t *temp = buf;
@@ -648,14 +691,14 @@
mutex_unlock(&driver->diagchar_mutex);
}
-void diag_update_sleeping_process(int process_id)
+void diag_update_sleeping_process(int process_id, int data_type)
{
int i;
mutex_lock(&driver->diagchar_mutex);
for (i = 0; i < driver->num_clients; i++)
if (driver->client_map[i].pid == process_id) {
- driver->data_ready[i] |= PKT_TYPE;
+ driver->data_ready[i] |= data_type;
break;
}
wake_up_interruptible(&driver->wait_q);
@@ -668,7 +711,7 @@
driver->pkt_length = len;
if (entry.process_id != NON_APPS_PROC && type != MODEM_DATA) {
diag_update_pkt_buffer(buf);
- diag_update_sleeping_process(entry.process_id);
+ diag_update_sleeping_process(entry.process_id, PKT_TYPE);
} else {
if (len > 0) {
if (entry.client_id == MODEM_PROC && driver->ch) {
@@ -777,6 +820,10 @@
int wr_size = -ENOMEM, retry_count = 0;
unsigned long flags = 0;
+ if (num_bytes == 0) {
+ pr_debug("diag: event mask not set yet, so no update\n");
+ return;
+ }
/* send event mask update */
driver->event_mask->cmd_type = DIAG_CTRL_MSG_EVENT_MASK;
driver->event_mask->data_len = 7 + num_bytes;
@@ -866,7 +913,7 @@
{
uint16_t subsys_cmd_code;
int subsys_id, ssid_first, ssid_last, ssid_range;
- int packet_type = 1, i, cmd_code;
+ int packet_type = 1, i, cmd_code, rt_mask;
unsigned char *temp = buf;
int data_type;
#if defined(CONFIG_DIAG_OVER_USB)
@@ -902,7 +949,34 @@
} else
buf = temp;
#endif
- } /* Check for set message mask */
+ } /* Disable log masks */
+ else if (*buf == 0x73 && *(int *)(buf+4) == 0) {
+ buf += 8;
+ /* Disable mask for each log code */
+ diag_disable_log_mask();
+ diag_update_userspace_clients(LOG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x73;
+ driver->apps_rsp_buf[1] = 0x0;
+ driver->apps_rsp_buf[2] = 0x0;
+ driver->apps_rsp_buf[3] = 0x0;
+ *(int *)(driver->apps_rsp_buf + 4) = 0x0;
+ if (driver->ch_cntl)
+ diag_send_log_mask_update(driver->ch_cntl,
+ *(int *)buf);
+ if (driver->chqdsp_cntl)
+ diag_send_log_mask_update(driver->chqdsp_cntl,
+ *(int *)buf);
+ if (driver->ch_wcnss_cntl)
+ diag_send_log_mask_update(driver->ch_wcnss_cntl,
+ *(int *)buf);
+ ENCODE_RSP_AND_SEND(7);
+ return 0;
+ } else
+ buf = temp;
+#endif
+ } /* Set runtime message mask */
else if ((*buf == 0x7d) && (*(buf+1) == 0x4)) {
ssid_first = *(uint16_t *)(buf + 2);
ssid_last = *(uint16_t *)(buf + 4);
@@ -930,6 +1004,33 @@
} else
buf = temp;
#endif
+ } /* Set ALL runtime message mask */
+ else if ((*buf == 0x7d) && (*(buf+1) == 0x5)) {
+ rt_mask = *(int *)(buf + 4);
+ diag_set_msg_mask(rt_mask);
+ diag_update_userspace_clients(MSG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x7d; /* cmd_code */
+ driver->apps_rsp_buf[1] = 0x5; /* set subcommand */
+ driver->apps_rsp_buf[2] = 1; /* success */
+ driver->apps_rsp_buf[3] = 0; /* rsvd */
+ *(int *)(driver->apps_rsp_buf + 4) = rt_mask;
+ /* send msg mask update to peripheral */
+ if (driver->ch_cntl)
+ diag_send_msg_mask_update(driver->ch_cntl,
+ ALL_SSID, ALL_SSID, MODEM_PROC);
+ if (driver->chqdsp_cntl)
+ diag_send_msg_mask_update(driver->chqdsp_cntl,
+ ALL_SSID, ALL_SSID, QDSP_PROC);
+ if (driver->ch_wcnss_cntl)
+ diag_send_msg_mask_update(driver->ch_wcnss_cntl,
+ ALL_SSID, ALL_SSID, WCNSS_PROC);
+ ENCODE_RSP_AND_SEND(7);
+ return 0;
+ } else
+ buf = temp;
+#endif
} else if (*buf == 0x82) { /* event mask change */
buf += 4;
diag_event_num_bytes = (*(uint16_t *)buf)/8+1;
@@ -1680,6 +1781,7 @@
diag_debug_buf_idx = 0;
driver->read_len_legacy = 0;
driver->use_device_tree = has_device_tree();
+ spin_lock_init(&diag_cntl_lock);
if (driver->event_mask == NULL) {
driver->event_mask = kzalloc(sizeof(
@@ -1764,6 +1866,7 @@
GFP_KERNEL)) == NULL)
goto err;
diag_create_msg_mask_table();
+ diag_event_num_bytes = 0;
if (driver->log_masks == NULL &&
(driver->log_masks = kzalloc(LOG_MASK_SIZE, GFP_KERNEL)) == NULL)
goto err;
@@ -1915,6 +2018,7 @@
usb_diag_close(driver->legacy_ch);
#endif
platform_driver_unregister(&msm_smd_ch1_driver);
+ platform_driver_unregister(&msm_diag_dci_driver);
platform_driver_unregister(&diag_smd_lite_driver);
kfree(driver->event_mask);
kfree(driver->log_mask);
diff --git a/drivers/char/diag/diagfwd.h b/drivers/char/diag/diagfwd.h
index 5744459..0780a8e 100644
--- a/drivers/char/diag/diagfwd.h
+++ b/drivers/char/diag/diagfwd.h
@@ -32,6 +32,7 @@
void diag_send_msg_mask_update(smd_channel_t *, int ssid_first,
int ssid_last, int proc);
void diag_send_log_mask_update(smd_channel_t *, int);
+void diag_update_sleeping_process(int process_id, int data_type);
/* State for diag forwarding */
#ifdef CONFIG_DIAG_OVER_USB
int diagfwd_connect(void);
@@ -40,4 +41,5 @@
extern int diag_debug_buf_idx;
extern unsigned char diag_debug_buf[1024];
extern int diag_event_num_bytes;
+extern struct platform_driver msm_diag_dci_driver;
#endif
diff --git a/drivers/char/diag/diagfwd_hsic.c b/drivers/char/diag/diagfwd_hsic.c
index b2080b3..4ecf000 100644
--- a/drivers/char/diag/diagfwd_hsic.c
+++ b/drivers/char/diag/diagfwd_hsic.c
@@ -511,7 +511,7 @@
};
-void __init diagfwd_hsic_init(void)
+void diagfwd_hsic_init(void)
{
int ret;
@@ -540,7 +540,7 @@
pr_err("DIAG could not initialize for HSIC execution\n");
}
-void __exit diagfwd_hsic_exit(void)
+void diagfwd_hsic_exit(void)
{
pr_debug("DIAG in %s\n", __func__);
diff --git a/drivers/char/diag/diagfwd_hsic.h b/drivers/char/diag/diagfwd_hsic.h
index 6769052..3cfb260 100644
--- a/drivers/char/diag/diagfwd_hsic.h
+++ b/drivers/char/diag/diagfwd_hsic.h
@@ -17,7 +17,7 @@
#define N_MDM_WRITE 1 /* Upgrade to 2 with ping pong buffer */
#define N_MDM_READ 1
-void __init diagfwd_hsic_init(void);
-void __exit diagfwd_hsic_exit(void);
+void diagfwd_hsic_init(void);
+void diagfwd_hsic_exit(void);
#endif
diff --git a/drivers/char/msm_rotator.c b/drivers/char/msm_rotator.c
index be6c8e4..47bc750 100644
--- a/drivers/char/msm_rotator.c
+++ b/drivers/char/msm_rotator.c
@@ -90,6 +90,20 @@
#define VERSION_KEY_MASK 0xFFFFFF00
#define MAX_DOWNSCALE_RATIO 3
+#define ROTATOR_REVISION_V0 0
+#define ROTATOR_REVISION_V1 1
+#define ROTATOR_REVISION_V2 2
+#define ROTATOR_REVISION_NONE 0xffffffff
+
+uint32_t rotator_hw_revision;
+
+/*
+ * rotator_hw_revision:
+ * 0 == 7x30
+ * 1 == 8x60
+ * 2 == 8960
+ *
+ */
struct tile_parm {
unsigned int width; /* tile's width */
unsigned int height; /* tile's height */
@@ -211,7 +225,7 @@
cancel_delayed_work(&msm_rotator_dev->imem_clk_work);
if (msm_rotator_dev->imem_clk_state != CLK_EN
&& msm_rotator_dev->imem_clk) {
- clk_enable(msm_rotator_dev->imem_clk);
+ clk_prepare_enable(msm_rotator_dev->imem_clk);
msm_rotator_dev->imem_clk_state = CLK_EN;
}
}
@@ -240,7 +254,7 @@
if (mutex_trylock(&msm_rotator_dev->imem_lock)) {
if (msm_rotator_dev->imem_clk_state == CLK_EN
&& msm_rotator_dev->imem_clk) {
- clk_disable(msm_rotator_dev->imem_clk);
+ clk_disable_unprepare(msm_rotator_dev->imem_clk);
msm_rotator_dev->imem_clk_state = CLK_DIS;
} else if (msm_rotator_dev->imem_clk_state == CLK_SUSPEND)
msm_rotator_dev->imem_clk_state = CLK_DIS;
@@ -255,18 +269,18 @@
if (msm_rotator_dev->regulator)
regulator_enable(msm_rotator_dev->regulator);
if (msm_rotator_dev->core_clk != NULL)
- clk_enable(msm_rotator_dev->core_clk);
+ clk_prepare_enable(msm_rotator_dev->core_clk);
if (msm_rotator_dev->pclk != NULL)
- clk_enable(msm_rotator_dev->pclk);
+ clk_prepare_enable(msm_rotator_dev->pclk);
}
/* disable clocks needed by rotator block */
static void disable_rot_clks(void)
{
if (msm_rotator_dev->core_clk != NULL)
- clk_disable(msm_rotator_dev->core_clk);
+ clk_disable_unprepare(msm_rotator_dev->core_clk);
if (msm_rotator_dev->pclk != NULL)
- clk_disable(msm_rotator_dev->pclk);
+ clk_disable_unprepare(msm_rotator_dev->pclk);
if (msm_rotator_dev->regulator)
regulator_disable(msm_rotator_dev->regulator);
}
@@ -331,6 +345,8 @@
return 1;
case MDP_RGB_888:
+ case MDP_YCBCR_H1V1:
+ case MDP_YCRCB_H1V1:
return 3;
case MDP_YCRYCB_H2V1:
@@ -527,8 +543,9 @@
return -EINVAL;
/* rotator expects YCbCr for planar input format */
- if (info->src.format == MDP_Y_CR_CB_H2V2 ||
- info->src.format == MDP_Y_CR_CB_GH2V2)
+ if ((info->src.format == MDP_Y_CR_CB_H2V2 ||
+ info->src.format == MDP_Y_CR_CB_GH2V2) &&
+ rotator_hw_revision < ROTATOR_REVISION_V2)
swap(in_chroma_paddr, in_chroma2_paddr);
iowrite32(in_paddr, MSM_ROTATOR_SRCP0_ADDR);
@@ -724,6 +741,8 @@
break;
case MDP_RGB_888:
+ case MDP_YCBCR_H1V1:
+ case MDP_YCRCB_H1V1:
iowrite32(GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8),
MSM_ROTATOR_SRC_UNPACK_PATTERN1);
iowrite32(GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8),
@@ -1068,6 +1087,8 @@
case MDP_XRGB_8888:
case MDP_BGRA_8888:
case MDP_RGBX_8888:
+ case MDP_YCBCR_H1V1:
+ case MDP_YCRCB_H1V1:
rc = msm_rotator_rgb_types(msm_rotator_dev->img_info[s],
in_paddr, out_paddr,
use_imem,
@@ -1217,38 +1238,27 @@
case MDP_RGBX_8888:
case MDP_BGRA_8888:
is_rgb = 1;
+ info.dst.format = info.src.format;
break;
case MDP_Y_CBCR_H2V2:
case MDP_Y_CRCB_H2V2:
+ case MDP_Y_CBCR_H2V1:
+ case MDP_Y_CRCB_H2V1:
+ case MDP_YCBCR_H1V1:
+ case MDP_YCRCB_H1V1:
+ info.dst.format = info.src.format;
+ break;
+ case MDP_YCRYCB_H2V1:
+ info.dst.format = MDP_Y_CRCB_H2V1;
+ break;
case MDP_Y_CB_CR_H2V2:
+ case MDP_Y_CBCR_H2V2_TILE:
+ info.dst.format = MDP_Y_CBCR_H2V2;
+ break;
case MDP_Y_CR_CB_H2V2:
case MDP_Y_CR_CB_GH2V2:
- case MDP_Y_CBCR_H2V1:
- case MDP_Y_CRCB_H2V1:
- case MDP_YCRYCB_H2V1:
case MDP_Y_CRCB_H2V2_TILE:
- case MDP_Y_CBCR_H2V2_TILE:
- break;
- default:
- return -EINVAL;
- }
-
- switch (info.dst.format) {
- case MDP_RGB_565:
- case MDP_BGR_565:
- case MDP_RGB_888:
- case MDP_ARGB_8888:
- case MDP_RGBA_8888:
- case MDP_XRGB_8888:
- case MDP_RGBX_8888:
- case MDP_BGRA_8888:
- case MDP_Y_CBCR_H2V2:
- case MDP_Y_CRCB_H2V2:
- case MDP_Y_CB_CR_H2V2:
- case MDP_Y_CR_CB_H2V2:
- case MDP_Y_CBCR_H2V1:
- case MDP_Y_CRCB_H2V1:
- case MDP_YCRYCB_H2V1:
+ info.dst.format = MDP_Y_CRCB_H2V2;
break;
default:
return -EINVAL;
@@ -1579,7 +1589,7 @@
#ifdef CONFIG_MSM_ROTATOR_USE_IMEM
if (msm_rotator_dev->imem_clk)
- clk_enable(msm_rotator_dev->imem_clk);
+ clk_prepare_enable(msm_rotator_dev->imem_clk);
#endif
enable_rot_clks();
ver = ioread32(MSM_ROTATOR_HW_VERSION);
@@ -1587,12 +1597,19 @@
#ifdef CONFIG_MSM_ROTATOR_USE_IMEM
if (msm_rotator_dev->imem_clk)
- clk_disable(msm_rotator_dev->imem_clk);
+ clk_disable_unprepare(msm_rotator_dev->imem_clk);
#endif
if (ver != pdata->hardware_version_number)
- pr_info("%s: invalid HW version ver 0x%x\n",
+ pr_debug("%s: invalid HW version ver 0x%x\n",
DRIVER_NAME, ver);
+ rotator_hw_revision = ver;
+ rotator_hw_revision >>= 16; /* bit 31:16 */
+ rotator_hw_revision &= 0xff;
+
+ pr_info("%s: rotator_hw_revision=%x\n",
+ __func__, rotator_hw_revision);
+
msm_rotator_dev->irq = platform_get_irq(pdev, 0);
if (msm_rotator_dev->irq < 0) {
printk(KERN_ALERT "%s: could not get IORESOURCE_IRQ\n",
@@ -1688,7 +1705,7 @@
iounmap(msm_rotator_dev->io_base);
if (msm_rotator_dev->imem_clk) {
if (msm_rotator_dev->imem_clk_state == CLK_EN)
- clk_disable(msm_rotator_dev->imem_clk);
+ clk_disable_unprepare(msm_rotator_dev->imem_clk);
clk_put(msm_rotator_dev->imem_clk);
msm_rotator_dev->imem_clk = NULL;
}
@@ -1714,7 +1731,7 @@
mutex_lock(&msm_rotator_dev->imem_lock);
if (msm_rotator_dev->imem_clk_state == CLK_EN
&& msm_rotator_dev->imem_clk) {
- clk_disable(msm_rotator_dev->imem_clk);
+ clk_disable_unprepare(msm_rotator_dev->imem_clk);
msm_rotator_dev->imem_clk_state = CLK_SUSPEND;
}
mutex_unlock(&msm_rotator_dev->imem_lock);
@@ -1732,7 +1749,7 @@
mutex_lock(&msm_rotator_dev->imem_lock);
if (msm_rotator_dev->imem_clk_state == CLK_SUSPEND
&& msm_rotator_dev->imem_clk) {
- clk_enable(msm_rotator_dev->imem_clk);
+ clk_prepare_enable(msm_rotator_dev->imem_clk);
msm_rotator_dev->imem_clk_state = CLK_EN;
}
mutex_unlock(&msm_rotator_dev->imem_lock);
diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c
index 6aed95c..2d33096 100644
--- a/drivers/cpufreq/cpufreq_ondemand.c
+++ b/drivers/cpufreq/cpufreq_ondemand.c
@@ -412,9 +412,12 @@
{
int input = 0;
int bypass = 0;
- int ret, cpu, reenable_timer;
+ int ret, cpu, reenable_timer, j;
struct cpu_dbs_info_s *dbs_info;
+ struct cpumask cpus_timer_done;
+ cpumask_clear(&cpus_timer_done);
+
ret = sscanf(buf, "%d", &input);
if (ret != 1)
@@ -447,10 +450,23 @@
continue;
dbs_info = &per_cpu(od_cpu_dbs_info, cpu);
+
+ for_each_cpu(j, &cpus_timer_done) {
+ if (!dbs_info->cur_policy) {
+ pr_err("Dbs policy is NULL\n");
+ goto skip_this_cpu;
+ }
+ if (cpumask_test_cpu(j, dbs_info->
+ cur_policy->cpus))
+ goto skip_this_cpu;
+ }
+
+ cpumask_set_cpu(cpu, &cpus_timer_done);
if (dbs_info->cur_policy) {
/* restart dbs timer */
dbs_timer_init(dbs_info);
}
+skip_this_cpu:
unlock_policy_rwsem_write(cpu);
}
}
@@ -463,6 +479,19 @@
continue;
dbs_info = &per_cpu(od_cpu_dbs_info, cpu);
+
+ for_each_cpu(j, &cpus_timer_done) {
+ if (!dbs_info->cur_policy) {
+ pr_err("Dbs policy is NULL\n");
+ goto skip_this_cpu_bypass;
+ }
+ if (cpumask_test_cpu(j, dbs_info->
+ cur_policy->cpus))
+ goto skip_this_cpu_bypass;
+ }
+
+ cpumask_set_cpu(cpu, &cpus_timer_done);
+
if (dbs_info->cur_policy) {
/* cpu using ondemand, cancel dbs timer */
mutex_lock(&dbs_info->timer_mutex);
@@ -475,6 +504,7 @@
mutex_unlock(&dbs_info->timer_mutex);
}
+skip_this_cpu_bypass:
unlock_policy_rwsem_write(cpu);
}
}
diff --git a/drivers/gpu/ion/ion_cp_heap.c b/drivers/gpu/ion/ion_cp_heap.c
index 7d99482..b383e68 100644
--- a/drivers/gpu/ion/ion_cp_heap.c
+++ b/drivers/gpu/ion/ion_cp_heap.c
@@ -224,8 +224,9 @@
if (!offset) {
mutex_lock(&cp_heap->lock);
+ cp_heap->allocated_bytes -= size;
if ((cp_heap->total_size -
- cp_heap->allocated_bytes) > size)
+ cp_heap->allocated_bytes) >= size)
pr_debug("%s: heap %s has enough memory (%lx) but"
" the allocation of size %lx still failed."
" Memory is probably fragmented.\n",
@@ -233,8 +234,6 @@
cp_heap->total_size -
cp_heap->allocated_bytes, size);
- cp_heap->allocated_bytes -= size;
-
if (cp_heap->reusable && !cp_heap->allocated_bytes) {
if (fmem_set_state(FMEM_T_STATE) != 0)
pr_err("%s: unable to transition heap to T-state\n",
diff --git a/drivers/gpu/ion/msm/msm_ion.c b/drivers/gpu/ion/msm/msm_ion.c
index 203b41a..15c0ec5 100644
--- a/drivers/gpu/ion/msm/msm_ion.c
+++ b/drivers/gpu/ion/msm/msm_ion.c
@@ -81,12 +81,44 @@
return 0;
}
+static void ion_set_base_address(struct ion_platform_heap *heap,
+ struct ion_platform_heap *shared_heap,
+ struct ion_co_heap_pdata *co_heap_data,
+ struct ion_cp_heap_pdata *cp_data)
+{
+ if (cp_data->reusable) {
+ const struct fmem_data *fmem_info = fmem_get_info();
+
+ if (!fmem_info) {
+ pr_err("fmem info pointer NULL!\n");
+ BUG();
+ }
+
+ heap->base = fmem_info->phys - fmem_info->reserved_size_low;
+ cp_data->virt_addr = fmem_info->virt;
+ pr_info("ION heap %s using FMEM\n", shared_heap->name);
+ } else {
+ heap->base = msm_ion_get_base(heap->size + shared_heap->size,
+ shared_heap->memory_type,
+ co_heap_data->align);
+ }
+ if (heap->base) {
+ shared_heap->base = heap->base + heap->size;
+ cp_data->secure_base = heap->base;
+ cp_data->secure_size = heap->size + shared_heap->size;
+ } else {
+ pr_err("%s: could not get memory for heap %s (id %x)\n",
+ __func__, heap->name, heap->id);
+ }
+}
+
static void allocate_co_memory(struct ion_platform_heap *heap,
struct ion_platform_heap heap_data[],
unsigned int nr_heaps)
{
struct ion_co_heap_pdata *co_heap_data =
(struct ion_co_heap_pdata *) heap->extra_data;
+
if (co_heap_data->adjacent_mem_id != INVALID_HEAP_ID) {
struct ion_platform_heap *shared_heap =
find_heap(heap_data, nr_heaps,
@@ -94,30 +126,23 @@
if (shared_heap) {
struct ion_cp_heap_pdata *cp_data =
(struct ion_cp_heap_pdata *) shared_heap->extra_data;
- if (cp_data->reusable) {
+ if (cp_data->fixed_position == FIXED_MIDDLE) {
const struct fmem_data *fmem_info =
fmem_get_info();
- heap->base = fmem_info->phys -
- fmem_info->reserved_size_low;
+
+ if (!fmem_info) {
+ pr_err("fmem info pointer NULL!\n");
+ BUG();
+ }
+
cp_data->virt_addr = fmem_info->virt;
- pr_info("ION heap %s using FMEM\n",
- shared_heap->name);
- } else {
- heap->base = msm_ion_get_base(
- heap->size + shared_heap->size,
- shared_heap->memory_type,
- co_heap_data->align);
- }
- if (heap->base) {
- shared_heap->base = heap->base + heap->size;
cp_data->secure_base = heap->base;
cp_data->secure_size =
heap->size + shared_heap->size;
- } else {
- pr_err("%s: could not get memory for heap %s "
- "(id %x)\n", __func__, heap->name, heap->id);
+ } else if (!heap->base) {
+ ion_set_base_address(heap, shared_heap,
+ co_heap_data, cp_data);
}
-
}
}
}
@@ -138,7 +163,7 @@
for (i = 0; i < nr_heaps; i++) {
struct ion_platform_heap *heap = &heap_data[i];
- if (!heap->base && heap->type == ION_HEAP_TYPE_CARVEOUT) {
+ if (heap->type == ION_HEAP_TYPE_CARVEOUT) {
if (heap->extra_data)
allocate_co_memory(heap, heap_data, nr_heaps);
}
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index c76bfd0..87f259d 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -106,10 +106,8 @@
},
#endif
},
- .gmemspace = {
- .gpu_base = 0,
- .sizebytes = SZ_256K,
- },
+ .gmem_base = 0,
+ .gmem_size = SZ_256K,
.pfp_fw = NULL,
.pm4_fw = NULL,
.wait_timeout = 10000, /* in milliseconds */
@@ -472,7 +470,7 @@
adreno_dev->istore_size = adreno_gpulist[i].istore_size;
adreno_dev->pix_shader_start = adreno_gpulist[i].pix_shader_start;
adreno_dev->instruction_size = adreno_gpulist[i].instruction_size;
- adreno_dev->gmemspace.sizebytes = adreno_gpulist[i].gmem_size;
+ adreno_dev->gmem_size = adreno_gpulist[i].gmem_size;
}
static int __devinit
@@ -792,10 +790,8 @@
devinfo.chip_id = adreno_dev->chip_id;
devinfo.mmu_enabled = kgsl_mmu_enabled();
devinfo.gpu_id = adreno_dev->gpurev;
- devinfo.gmem_gpubaseaddr = adreno_dev->gmemspace.
- gpu_base;
- devinfo.gmem_sizebytes = adreno_dev->gmemspace.
- sizebytes;
+ devinfo.gmem_gpubaseaddr = adreno_dev->gmem_base;
+ devinfo.gmem_sizebytes = adreno_dev->gmem_size;
if (copy_to_user(value, &devinfo, sizeof(devinfo)) !=
0) {
@@ -869,6 +865,48 @@
return status;
}
+static int adreno_setproperty(struct kgsl_device *device,
+ enum kgsl_property_type type,
+ void *value,
+ unsigned int sizebytes)
+{
+ int status = -EINVAL;
+
+ switch (type) {
+ case KGSL_PROP_PWRCTRL: {
+ unsigned int enable;
+ struct kgsl_device_platform_data *pdata =
+ kgsl_device_get_drvdata(device);
+
+ if (sizebytes != sizeof(enable))
+ break;
+
+ if (copy_from_user(&enable, (void __user *) value,
+ sizeof(enable))) {
+ status = -EFAULT;
+ break;
+ }
+
+ if (enable) {
+ if (pdata->nap_allowed)
+ device->pwrctrl.nap_allowed = true;
+
+ kgsl_pwrscale_enable(device);
+ } else {
+ device->pwrctrl.nap_allowed = false;
+ kgsl_pwrscale_disable(device);
+ }
+
+ status = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return status;
+}
+
static inline void adreno_poke(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
@@ -988,17 +1026,47 @@
return status;
}
+/* Find a memory structure attached to an adreno context */
+
+struct kgsl_memdesc *adreno_find_ctxtmem(struct kgsl_device *device,
+ unsigned int pt_base, unsigned int gpuaddr, unsigned int size)
+{
+ struct kgsl_context *context;
+ struct adreno_context *adreno_context = NULL;
+ int next = 0;
+
+ while (1) {
+ context = idr_get_next(&device->context_idr, &next);
+ if (context == NULL)
+ break;
+
+ adreno_context = (struct adreno_context *)context->devctxt;
+
+ if (kgsl_mmu_pt_equal(adreno_context->pagetable, pt_base)) {
+ struct kgsl_memdesc *desc;
+
+ desc = &adreno_context->gpustate;
+ if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size))
+ return desc;
+
+ desc = &adreno_context->context_gmem_shadow.gmemshadow;
+ if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size))
+ return desc;
+ }
+ next = next + 1;
+ }
+
+ return NULL;
+}
+
struct kgsl_memdesc *adreno_find_region(struct kgsl_device *device,
unsigned int pt_base,
unsigned int gpuaddr,
unsigned int size)
{
- struct kgsl_memdesc *result = NULL;
struct kgsl_mem_entry *entry;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_ringbuffer *ringbuffer = &adreno_dev->ringbuffer;
- struct kgsl_context *context;
- int next = 0;
if (kgsl_gpuaddr_in_memdesc(&ringbuffer->buffer_desc, gpuaddr, size))
return &ringbuffer->buffer_desc;
@@ -1018,34 +1086,7 @@
if (entry)
return &entry->memdesc;
- while (1) {
- struct adreno_context *adreno_context = NULL;
- context = idr_get_next(&device->context_idr, &next);
- if (context == NULL)
- break;
-
- adreno_context = (struct adreno_context *)context->devctxt;
-
- if (kgsl_mmu_pt_equal(adreno_context->pagetable, pt_base)) {
- struct kgsl_memdesc *desc;
-
- desc = &adreno_context->gpustate;
- if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size)) {
- result = desc;
- return result;
- }
-
- desc = &adreno_context->context_gmem_shadow.gmemshadow;
- if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size)) {
- result = desc;
- return result;
- }
- }
- next = next + 1;
- }
-
- return NULL;
-
+ return adreno_find_ctxtmem(device, pt_base, gpuaddr, size);
}
uint8_t *adreno_convertaddr(struct kgsl_device *device, unsigned int pt_base,
@@ -1062,9 +1103,8 @@
unsigned int *value)
{
unsigned int *reg;
- BUG_ON(offsetwords*sizeof(uint32_t) >= device->regspace.sizebytes);
- reg = (unsigned int *)(device->regspace.mmio_virt_base
- + (offsetwords << 2));
+ BUG_ON(offsetwords*sizeof(uint32_t) >= device->reg_len);
+ reg = (unsigned int *)(device->reg_virt + (offsetwords << 2));
if (!in_interrupt())
kgsl_pre_hwaccess(device);
@@ -1080,14 +1120,13 @@
{
unsigned int *reg;
- BUG_ON(offsetwords*sizeof(uint32_t) >= device->regspace.sizebytes);
+ BUG_ON(offsetwords*sizeof(uint32_t) >= device->reg_len);
if (!in_interrupt())
kgsl_pre_hwaccess(device);
kgsl_cffdump_regwrite(device->id, offsetwords << 2, value);
- reg = (unsigned int *)(device->regspace.mmio_virt_base
- + (offsetwords << 2));
+ reg = (unsigned int *)(device->reg_virt + (offsetwords << 2));
/*ensure previous writes post before this one,
* i.e. act like normal writel() */
@@ -1277,12 +1316,23 @@
unsigned int timestamp = 0;
unsigned int context_id = _get_context_id(context);
- if (type == KGSL_TIMESTAMP_CONSUMED)
+ switch (type) {
+ case KGSL_TIMESTAMP_QUEUED: {
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ struct adreno_ringbuffer *rb = &adreno_dev->ringbuffer;
+
+ timestamp = rb->timestamp[context_id];
+ break;
+ }
+ case KGSL_TIMESTAMP_CONSUMED:
adreno_regread(device, REG_CP_TIMESTAMP, ×tamp);
- else if (type == KGSL_TIMESTAMP_RETIRED)
+ break;
+ case KGSL_TIMESTAMP_RETIRED:
kgsl_sharedmem_readl(&device->memstore, ×tamp,
- KGSL_MEMSTORE_OFFSET(context_id,
- eoptimestamp));
+ KGSL_MEMSTORE_OFFSET(context_id, eoptimestamp));
+ break;
+ }
+
rmb();
return timestamp;
@@ -1398,6 +1448,7 @@
.setstate = adreno_setstate,
.drawctxt_create = adreno_drawctxt_create,
.drawctxt_destroy = adreno_drawctxt_destroy,
+ .setproperty = adreno_setproperty,
};
static struct platform_device_id adreno_id_table[] = {
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 4885312..491cf62 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -62,7 +62,8 @@
struct kgsl_device dev; /* Must be first field in this struct */
unsigned int chip_id;
enum adreno_gpurev gpurev;
- struct kgsl_memregion gmemspace;
+ unsigned long gmem_base;
+ unsigned int gmem_size;
struct adreno_context *drawctxt_active;
const char *pfp_fwfile;
unsigned int *pfp_fw;
@@ -128,6 +129,9 @@
uint8_t *adreno_convertaddr(struct kgsl_device *device,
unsigned int pt_base, unsigned int gpuaddr, unsigned int size);
+struct kgsl_memdesc *adreno_find_ctxtmem(struct kgsl_device *device,
+ unsigned int pt_base, unsigned int gpuaddr, unsigned int size);
+
void *adreno_snapshot(struct kgsl_device *device, void *snapshot, int *remain,
int hang);
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index 18d0e83..6fa053b 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -1325,9 +1325,8 @@
{
int result;
- calc_gmemsize(&drawctxt->context_gmem_shadow,
- adreno_dev->gmemspace.sizebytes);
- tmp_ctx.gmem_base = adreno_dev->gmemspace.gpu_base;
+ calc_gmemsize(&drawctxt->context_gmem_shadow, adreno_dev->gmem_base);
+ tmp_ctx.gmem_base = adreno_dev->gmem_base;
result = kgsl_allocate(&drawctxt->context_gmem_shadow.gmemshadow,
drawctxt->pagetable, drawctxt->context_gmem_shadow.size);
@@ -1849,12 +1848,8 @@
unsigned int gmem_size;
unsigned int edram_value = 0;
- /* make sure edram range is aligned to size */
- BUG_ON(adreno_dev->gmemspace.gpu_base &
- (adreno_dev->gmemspace.sizebytes - 1));
-
/* get edram_size value equivalent */
- gmem_size = (adreno_dev->gmemspace.sizebytes >> 14);
+ gmem_size = (adreno_dev->gmem_size >> 14);
while (gmem_size >>= 1)
edram_value++;
@@ -1864,7 +1859,7 @@
rb_edram_info.f.edram_mapping_mode = 0; /* EDRAM_MAP_UPPER */
/* must be aligned to size */
- rb_edram_info.f.edram_range = (adreno_dev->gmemspace.gpu_base >> 14);
+ rb_edram_info.f.edram_range = (adreno_dev->gmem_base >> 14);
adreno_regwrite(device, REG_RB_EDRAM_INFO, rb_edram_info.val);
}
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index 32603bd..6b58545 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -2138,9 +2138,8 @@
{
int result;
- calc_gmemsize(&drawctxt->context_gmem_shadow,
- adreno_dev->gmemspace.sizebytes);
- tmp_ctx.gmem_base = adreno_dev->gmemspace.gpu_base;
+ calc_gmemsize(&drawctxt->context_gmem_shadow, adreno_dev->gmem_size);
+ tmp_ctx.gmem_base = adreno_dev->gmem_base;
result = kgsl_allocate(&drawctxt->context_gmem_shadow.gmemshadow,
drawctxt->pagetable, drawctxt->context_gmem_shadow.size);
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index be0fc1d..5f16ff7 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -339,7 +339,6 @@
if (status != 0)
return status;
- adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000C0804);
rb->rptr = 0;
rb->wptr = 0;
diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c
index bca7040..2dc6f6c 100644
--- a/drivers/gpu/msm/adreno_snapshot.c
+++ b/drivers/gpu/msm/adreno_snapshot.c
@@ -454,33 +454,36 @@
static void ib_add_gpu_object(struct kgsl_device *device, unsigned int ptbase,
unsigned int gpuaddr, unsigned int dwords)
{
- int i = 0, ret;
+ int i, ret, rem = dwords;
unsigned int *src = (unsigned int *) adreno_convertaddr(device, ptbase,
gpuaddr, dwords << 2);
if (src == NULL)
return;
- while (i < dwords) {
+ for (i = 0; rem != 0; rem--, i++) {
+ int pktsize;
+
+ if (!pkt_is_type0(src[i]) && !pkt_is_type3(src[i]))
+ continue;
+
+ pktsize = type3_pkt_size(src[i]);
+
+ if ((pktsize + 1) > rem)
+ break;
if (pkt_is_type3(src[i])) {
- if ((dwords - i) < type3_pkt_size(src[i]) + 1)
- goto skip;
-
if (adreno_cmd_is_ib(src[i]))
ib_add_gpu_object(device, ptbase,
src[i + 1], src[i + 2]);
else
ib_parse_type3(device, &src[i], ptbase);
-
- i += type3_pkt_size(src[i]);
} else if (pkt_is_type0(src[i])) {
ib_parse_type0(device, &src[i], ptbase);
- i += type0_pkt_size(src[i]);
}
-skip:
- i++;
+ i += pktsize;
+ rem -= pktsize;
}
ret = kgsl_snapshot_get_object(device, ptbase, gpuaddr, dwords << 2,
@@ -571,7 +574,7 @@
while (index != rb->wptr) {
index--;
- if (index < 0) {
+ if (index < 0) {
index = rb->sizedwords - 2;
/*
@@ -587,7 +590,8 @@
}
/* Break if the current packet is a context switch identifier */
- if (adreno_rb_ctxtswitch(&rbptr[index]))
+ if ((rbptr[index] == cp_nop_packet(1)) &&
+ (rbptr[index + 1] == KGSL_CONTEXT_TO_MEM_IDENTIFIER))
break;
}
@@ -657,17 +661,31 @@
parse_ibs = 0;
if (parse_ibs && adreno_cmd_is_ib(rbptr[index])) {
+ unsigned int ibaddr = rbptr[index + 1];
+ unsigned int ibsize = rbptr[index + 2];
+
/*
- * The IB from CP_IB1_BASE goes into the snapshot, all
+ * This will return non NULL if the IB happens to be
+ * part of the context memory (i.e - context switch
+ * command buffers)
+ */
+
+ struct kgsl_memdesc *memdesc =
+ adreno_find_ctxtmem(device, ptbase, ibaddr,
+ ibsize);
+
+ /*
+ * The IB from CP_IB1_BASE and the IBs for legacy
+ * context switch go into the snapshot all
* others get marked at GPU objects
*/
- if (rbptr[index + 1] == ibbase)
+
+ if (ibaddr == ibbase || memdesc != NULL)
push_object(device, SNAPSHOT_OBJ_TYPE_IB,
- ptbase, rbptr[index + 1],
- rbptr[index + 2]);
+ ptbase, ibaddr, ibsize);
else
- ib_add_gpu_object(device, ptbase,
- rbptr[index + 1], rbptr[index + 2]);
+ ib_add_gpu_object(device, ptbase, ibaddr,
+ ibsize);
}
index = index + 1;
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 693aa74..7e84692 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -617,7 +617,6 @@
mutex_lock(&device->mutex);
device->pwrctrl.restore_slumber = 0;
kgsl_pwrctrl_wake(device);
- kgsl_pwrctrl_pwrlevel_change(device, KGSL_PWRLEVEL_TURBO);
mutex_unlock(&device->mutex);
kgsl_check_idle(device);
KGSL_PWR_WARN(device, "late resume end\n");
@@ -719,6 +718,11 @@
mutex_lock(&device->mutex);
kgsl_check_suspended(device);
+ /* clean up any to-be-freed entries that belong to this
+ * process and this device
+ */
+ kgsl_cancel_events(device, dev_priv);
+
while (1) {
context = idr_get_next(&device->context_idr, &next);
if (context == NULL)
@@ -737,10 +741,6 @@
result = device->ftbl->stop(device);
kgsl_pwrctrl_set_state(device, KGSL_STATE_INIT);
}
- /* clean up any to-be-freed entries that belong to this
- * process and this device
- */
- kgsl_cancel_events(device, dev_priv);
mutex_unlock(&device->mutex);
kfree(dev_priv);
@@ -1349,7 +1349,7 @@
goto error;
}
- result = kgsl_sharedmem_vmalloc_user(&entry->memdesc,
+ result = kgsl_sharedmem_page_alloc_user(&entry->memdesc,
private->pagetable, len,
param->flags);
if (result != 0)
@@ -1360,7 +1360,7 @@
result = kgsl_sharedmem_map_vma(vma, &entry->memdesc);
if (result) {
KGSL_CORE_ERR("kgsl_sharedmem_map_vma failed: %d\n", result);
- goto error_free_vmalloc;
+ goto error_free_alloc;
}
param->gpuaddr = entry->memdesc.gpuaddr;
@@ -1376,7 +1376,7 @@
kgsl_check_idle(dev_priv->device);
return 0;
-error_free_vmalloc:
+error_free_alloc:
kgsl_sharedmem_free(&entry->memdesc);
error_free_entry:
@@ -1675,11 +1675,8 @@
struct scatterlist *s;
unsigned long flags;
- if (kgsl_ion_client == NULL) {
- kgsl_ion_client = msm_ion_client_create(UINT_MAX, KGSL_NAME);
- if (kgsl_ion_client == NULL)
- return -ENODEV;
- }
+ if (IS_ERR_OR_NULL(kgsl_ion_client))
+ return -ENODEV;
handle = ion_import_fd(kgsl_ion_client, fd);
if (IS_ERR_OR_NULL(handle))
@@ -2430,7 +2427,6 @@
{
int result;
int status = -EINVAL;
- struct kgsl_memregion *regspace = NULL;
struct resource *res;
struct platform_device *pdev =
container_of(device->parentdev, struct platform_device, dev);
@@ -2441,6 +2437,8 @@
if (status)
goto error;
+ kgsl_ion_client = msm_ion_client_create(UINT_MAX, KGSL_NAME);
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
device->iomemname);
if (res == NULL) {
@@ -2449,26 +2447,25 @@
goto error_pwrctrl_close;
}
if (res->start == 0 || resource_size(res) == 0) {
- KGSL_DRV_ERR(device, "dev %d invalid regspace\n", device->id);
+ KGSL_DRV_ERR(device, "dev %d invalid register region\n",
+ device->id);
status = -EINVAL;
goto error_pwrctrl_close;
}
- regspace = &device->regspace;
- regspace->mmio_phys_base = res->start;
- regspace->sizebytes = resource_size(res);
+ device->reg_phys = res->start;
+ device->reg_len = resource_size(res);
- if (!request_mem_region(regspace->mmio_phys_base,
- regspace->sizebytes, device->name)) {
+ if (!request_mem_region(device->reg_phys, device->reg_len,
+ device->name)) {
KGSL_DRV_ERR(device, "request_mem_region failed\n");
status = -ENODEV;
goto error_pwrctrl_close;
}
- regspace->mmio_virt_base = ioremap(regspace->mmio_phys_base,
- regspace->sizebytes);
+ device->reg_virt = ioremap(device->reg_phys, device->reg_len);
- if (regspace->mmio_virt_base == NULL) {
+ if (device->reg_virt == NULL) {
KGSL_DRV_ERR(device, "ioremap failed\n");
status = -ENODEV;
goto error_release_mem;
@@ -2485,9 +2482,9 @@
disable_irq(device->pwrctrl.interrupt_num);
KGSL_DRV_INFO(device,
- "dev_id %d regs phys 0x%08x size 0x%08x virt %p\n",
- device->id, regspace->mmio_phys_base,
- regspace->sizebytes, regspace->mmio_virt_base);
+ "dev_id %d regs phys 0x%08lx size 0x%08x virt %p\n",
+ device->id, device->reg_phys, device->reg_len,
+ device->reg_virt);
result = kgsl_drm_init(pdev);
if (result)
@@ -2500,10 +2497,10 @@
free_irq(device->pwrctrl.interrupt_num, NULL);
device->pwrctrl.have_irq = 0;
error_iounmap:
- iounmap(regspace->mmio_virt_base);
- regspace->mmio_virt_base = NULL;
+ iounmap(device->reg_virt);
+ device->reg_virt = NULL;
error_release_mem:
- release_mem_region(regspace->mmio_phys_base, regspace->sizebytes);
+ release_mem_region(device->reg_phys, device->reg_len);
error_pwrctrl_close:
kgsl_pwrctrl_close(device);
error:
@@ -2513,15 +2510,12 @@
void kgsl_device_platform_remove(struct kgsl_device *device)
{
- struct kgsl_memregion *regspace = &device->regspace;
-
kgsl_unregister_device(device);
- if (regspace->mmio_virt_base != NULL) {
- iounmap(regspace->mmio_virt_base);
- regspace->mmio_virt_base = NULL;
- release_mem_region(regspace->mmio_phys_base,
- regspace->sizebytes);
+ if (device->reg_virt != NULL) {
+ iounmap(device->reg_virt);
+ device->reg_virt = NULL;
+ release_mem_region(device->reg_phys, device->reg_len);
}
kgsl_pwrctrl_close(device);
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index fcd8448..5212d0f 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -33,6 +33,9 @@
#define KGSL_MEMSTORE_MAX (KGSL_MEMSTORE_SIZE / \
sizeof(struct kgsl_devmemstore) - 1)
+/* Timestamp window used to detect rollovers */
+#define KGSL_TIMESTAMP_WINDOW 0x80000000
+
/*cache coherency ops */
#define DRM_KGSL_GEM_CACHE_OP_TO_DEV 0x0001
#define DRM_KGSL_GEM_CACHE_OP_FROM_DEV 0x0002
@@ -96,6 +99,8 @@
struct {
unsigned int vmalloc;
unsigned int vmalloc_max;
+ unsigned int page_alloc;
+ unsigned int page_alloc_max;
unsigned int coherent;
unsigned int coherent_max;
unsigned int mapped;
@@ -203,17 +208,25 @@
}
return 0;
}
+
+static inline void *kgsl_memdesc_map(struct kgsl_memdesc *memdesc)
+{
+ if (memdesc->hostptr == NULL && memdesc->ops->map_kernel_mem)
+ memdesc->ops->map_kernel_mem(memdesc);
+
+ return memdesc->hostptr;
+}
+
static inline uint8_t *kgsl_gpuaddr_to_vaddr(struct kgsl_memdesc *memdesc,
unsigned int gpuaddr)
{
- if (memdesc->gpuaddr == 0 ||
- gpuaddr < memdesc->gpuaddr ||
- gpuaddr >= (memdesc->gpuaddr + memdesc->size) ||
- (NULL == memdesc->hostptr && memdesc->ops->map_kernel_mem &&
- memdesc->ops->map_kernel_mem(memdesc)))
- return NULL;
+ void *hostptr = NULL;
- return memdesc->hostptr + (gpuaddr - memdesc->gpuaddr);
+ if ((gpuaddr >= memdesc->gpuaddr) &&
+ (gpuaddr < (memdesc->gpuaddr + memdesc->size)))
+ hostptr = kgsl_memdesc_map(memdesc);
+
+ return hostptr != NULL ? hostptr + (gpuaddr - memdesc->gpuaddr) : NULL;
}
static inline int timestamp_cmp(unsigned int new, unsigned int old)
@@ -223,7 +236,7 @@
if (ts_diff == 0)
return 0;
- return ((ts_diff > 0) || (ts_diff < -25000)) ? 1 : -1;
+ return ((ts_diff > 0) || (ts_diff < -KGSL_TIMESTAMP_WINDOW)) ? 1 : -1;
}
static inline void
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index fece715..7d3cfca 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -110,13 +110,6 @@
unsigned int sizebytes);
};
-struct kgsl_memregion {
- unsigned char *mmio_virt_base;
- unsigned int mmio_phys_base;
- uint32_t gpu_base;
- unsigned int sizebytes;
-};
-
/* MH register values */
struct kgsl_mh {
unsigned int mharb;
@@ -143,7 +136,9 @@
unsigned int ver_minor;
uint32_t flags;
enum kgsl_deviceid id;
- struct kgsl_memregion regspace;
+ unsigned long reg_phys;
+ void *reg_virt;
+ unsigned int reg_len;
struct kgsl_memdesc memstore;
const char *iomemname;
diff --git a/drivers/gpu/msm/kgsl_drm.c b/drivers/gpu/msm/kgsl_drm.c
index 33f4b95..66ac08f 100644
--- a/drivers/gpu/msm/kgsl_drm.c
+++ b/drivers/gpu/msm/kgsl_drm.c
@@ -263,7 +263,7 @@
priv->type & DRM_KGSL_GEM_CACHE_MASK)
list_add(&priv->list, &kgsl_mem_list);
- result = kgsl_sharedmem_vmalloc_user(&priv->memdesc,
+ result = kgsl_sharedmem_page_alloc_user(&priv->memdesc,
priv->pagetable,
obj->size * priv->bufcount, 0);
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 17f978e..6fa7da2 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -505,6 +505,7 @@
}
pwr->num_pwrlevels = pdata->num_levels;
pwr->active_pwrlevel = pdata->init_level;
+ pwr->default_pwrlevel = pdata->init_level;
for (i = 0; i < pdata->num_levels; i++) {
pwr->pwrlevels[i].gpu_freq =
(pdata->pwrlevel[i].gpu_freq > 0) ?
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index 7dd429f..a677fec 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -46,6 +46,7 @@
struct kgsl_pwrlevel pwrlevels[KGSL_MAX_PWRLEVELS];
unsigned int active_pwrlevel;
int thermal_pwrlevel;
+ unsigned int default_pwrlevel;
unsigned int num_pwrlevels;
unsigned int interval_timeout;
bool strtstp_sleepwake;
diff --git a/drivers/gpu/msm/kgsl_pwrscale_trustzone.c b/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
index 4b8c938..e0825c3 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -116,7 +116,7 @@
priv->governor == TZ_GOVERNOR_ONDEMAND &&
device->pwrctrl.restore_slumber == 0)
kgsl_pwrctrl_pwrlevel_change(device,
- device->pwrctrl.thermal_pwrlevel);
+ device->pwrctrl.default_pwrlevel);
}
static void tz_idle(struct kgsl_device *device, struct kgsl_pwrscale *pwrscale)
diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c
index 63c24f1..a51f29f 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.c
+++ b/drivers/gpu/msm/kgsl_sharedmem.c
@@ -203,6 +203,10 @@
val = kgsl_driver.stats.vmalloc;
else if (!strncmp(attr->attr.name, "vmalloc_max", 11))
val = kgsl_driver.stats.vmalloc_max;
+ else if (!strncmp(attr->attr.name, "page_alloc", 10))
+ val = kgsl_driver.stats.page_alloc;
+ else if (!strncmp(attr->attr.name, "page_alloc_max", 14))
+ val = kgsl_driver.stats.page_alloc_max;
else if (!strncmp(attr->attr.name, "coherent", 8))
val = kgsl_driver.stats.coherent;
else if (!strncmp(attr->attr.name, "coherent_max", 12))
@@ -232,6 +236,8 @@
DEVICE_ATTR(vmalloc, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(vmalloc_max, 0444, kgsl_drv_memstat_show, NULL);
+DEVICE_ATTR(page_alloc, 0444, kgsl_drv_memstat_show, NULL);
+DEVICE_ATTR(page_alloc_max, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(coherent, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(coherent_max, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(mapped, 0444, kgsl_drv_memstat_show, NULL);
@@ -241,6 +247,8 @@
static const struct device_attribute *drv_attr_list[] = {
&dev_attr_vmalloc,
&dev_attr_vmalloc_max,
+ &dev_attr_page_alloc,
+ &dev_attr_page_alloc_max,
&dev_attr_coherent,
&dev_attr_coherent_max,
&dev_attr_mapped,
@@ -295,7 +303,7 @@
}
#endif
-static int kgsl_vmalloc_vmfault(struct kgsl_memdesc *memdesc,
+static int kgsl_page_alloc_vmfault(struct kgsl_memdesc *memdesc,
struct vm_area_struct *vma,
struct vm_fault *vmf)
{
@@ -316,18 +324,20 @@
return 0;
}
-static int kgsl_vmalloc_vmflags(struct kgsl_memdesc *memdesc)
+static int kgsl_page_alloc_vmflags(struct kgsl_memdesc *memdesc)
{
return VM_RESERVED | VM_DONTEXPAND;
}
-static void kgsl_vmalloc_free(struct kgsl_memdesc *memdesc)
+static void kgsl_page_alloc_free(struct kgsl_memdesc *memdesc)
{
int i = 0;
struct scatterlist *sg;
- kgsl_driver.stats.vmalloc -= memdesc->size;
- if (memdesc->hostptr)
+ kgsl_driver.stats.page_alloc -= memdesc->size;
+ if (memdesc->hostptr) {
vunmap(memdesc->hostptr);
+ kgsl_driver.stats.vmalloc -= memdesc->size;
+ }
if (memdesc->sg)
for_each_sg(memdesc->sg, sg, memdesc->sglen, i)
__free_page(sg_page(sg));
@@ -339,13 +349,14 @@
}
/*
- * kgsl_vmalloc_map_kernel - Map the memory in memdesc to kernel address space
+ * kgsl_page_alloc_map_kernel - Map the memory in memdesc to kernel address
+ * space
*
* @memdesc - The memory descriptor which contains information about the memory
*
* Return: 0 on success else error code
*/
-static int kgsl_vmalloc_map_kernel(struct kgsl_memdesc *memdesc)
+static int kgsl_page_alloc_map_kernel(struct kgsl_memdesc *memdesc)
{
if (!memdesc->hostptr) {
pgprot_t page_prot = pgprot_writecombine(PAGE_KERNEL);
@@ -363,6 +374,8 @@
pages[i] = sg_page(sg);
memdesc->hostptr = vmap(pages, memdesc->sglen,
VM_IOREMAP, page_prot);
+ KGSL_STATS_ADD(memdesc->size, kgsl_driver.stats.vmalloc,
+ kgsl_driver.stats.vmalloc_max);
vfree(pages);
}
if (!memdesc->hostptr)
@@ -410,13 +423,13 @@
}
/* Global - also used by kgsl_drm.c */
-struct kgsl_memdesc_ops kgsl_vmalloc_ops = {
- .free = kgsl_vmalloc_free,
- .vmflags = kgsl_vmalloc_vmflags,
- .vmfault = kgsl_vmalloc_vmfault,
- .map_kernel_mem = kgsl_vmalloc_map_kernel,
+struct kgsl_memdesc_ops kgsl_page_alloc_ops = {
+ .free = kgsl_page_alloc_free,
+ .vmflags = kgsl_page_alloc_vmflags,
+ .vmfault = kgsl_page_alloc_vmfault,
+ .map_kernel_mem = kgsl_page_alloc_map_kernel,
};
-EXPORT_SYMBOL(kgsl_vmalloc_ops);
+EXPORT_SYMBOL(kgsl_page_alloc_ops);
static struct kgsl_memdesc_ops kgsl_ebimem_ops = {
.free = kgsl_ebimem_free,
@@ -450,7 +463,7 @@
EXPORT_SYMBOL(kgsl_cache_range_op);
static int
-_kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
+_kgsl_sharedmem_page_alloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable,
size_t size, unsigned int protflags)
{
@@ -461,11 +474,13 @@
memdesc->size = size;
memdesc->pagetable = pagetable;
memdesc->priv = KGSL_MEMFLAGS_CACHED;
- memdesc->ops = &kgsl_vmalloc_ops;
+ memdesc->ops = &kgsl_page_alloc_ops;
memdesc->sg = kgsl_sg_alloc(sglen);
if (memdesc->sg == NULL) {
+ KGSL_CORE_ERR("vmalloc(%d) failed\n",
+ sglen * sizeof(struct scatterlist));
ret = -ENOMEM;
goto done;
}
@@ -494,8 +509,8 @@
if (ret)
goto done;
- KGSL_STATS_ADD(size, kgsl_driver.stats.vmalloc,
- kgsl_driver.stats.vmalloc_max);
+ KGSL_STATS_ADD(size, kgsl_driver.stats.page_alloc,
+ kgsl_driver.stats.page_alloc_max);
order = get_order(size);
@@ -510,7 +525,7 @@
}
int
-kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
+kgsl_sharedmem_page_alloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size)
{
int ret = 0;
@@ -518,18 +533,18 @@
size = ALIGN(size, PAGE_SIZE * 2);
- ret = _kgsl_sharedmem_vmalloc(memdesc, pagetable, size,
+ ret = _kgsl_sharedmem_page_alloc(memdesc, pagetable, size,
GSL_PT_PAGE_RV | GSL_PT_PAGE_WV);
if (!ret)
- ret = kgsl_vmalloc_map_kernel(memdesc);
+ ret = kgsl_page_alloc_map_kernel(memdesc);
if (ret)
kgsl_sharedmem_free(memdesc);
return ret;
}
-EXPORT_SYMBOL(kgsl_sharedmem_vmalloc);
+EXPORT_SYMBOL(kgsl_sharedmem_page_alloc);
int
-kgsl_sharedmem_vmalloc_user(struct kgsl_memdesc *memdesc,
+kgsl_sharedmem_page_alloc_user(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable,
size_t size, int flags)
{
@@ -541,10 +556,10 @@
if (!(flags & KGSL_MEMFLAGS_GPUREADONLY))
protflags |= GSL_PT_PAGE_WV;
- return _kgsl_sharedmem_vmalloc(memdesc, pagetable, size,
+ return _kgsl_sharedmem_page_alloc(memdesc, pagetable, size,
protflags);
}
-EXPORT_SYMBOL(kgsl_sharedmem_vmalloc_user);
+EXPORT_SYMBOL(kgsl_sharedmem_page_alloc_user);
int
kgsl_sharedmem_alloc_coherent(struct kgsl_memdesc *memdesc, size_t size)
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index def29b3..fb8dd95 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -32,12 +32,12 @@
/** Set if the memdesc is mapped into all pagetables */
#define KGSL_MEMFLAGS_GLOBAL 0x00000002
-extern struct kgsl_memdesc_ops kgsl_vmalloc_ops;
+extern struct kgsl_memdesc_ops kgsl_page_alloc_ops;
-int kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
+int kgsl_sharedmem_page_alloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size);
-int kgsl_sharedmem_vmalloc_user(struct kgsl_memdesc *memdesc,
+int kgsl_sharedmem_page_alloc_user(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable,
size_t size, int flags);
@@ -134,7 +134,7 @@
{
if (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_NONE)
return kgsl_sharedmem_ebimem(memdesc, pagetable, size);
- return kgsl_sharedmem_vmalloc(memdesc, pagetable, size);
+ return kgsl_sharedmem_page_alloc(memdesc, pagetable, size);
}
static inline int
@@ -145,7 +145,7 @@
if (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_NONE)
return kgsl_sharedmem_ebimem_user(memdesc, pagetable, size,
flags);
- return kgsl_sharedmem_vmalloc_user(memdesc, pagetable, size, flags);
+ return kgsl_sharedmem_page_alloc_user(memdesc, pagetable, size, flags);
}
static inline int
diff --git a/drivers/gpu/msm/kgsl_snapshot.c b/drivers/gpu/msm/kgsl_snapshot.c
index c24576d..c8db702 100644
--- a/drivers/gpu/msm/kgsl_snapshot.c
+++ b/drivers/gpu/msm/kgsl_snapshot.c
@@ -28,6 +28,7 @@
unsigned int gpuaddr;
unsigned int ptbase;
unsigned int size;
+ unsigned int offset;
int type;
struct kgsl_mem_entry *entry;
struct list_head node;
@@ -62,7 +63,8 @@
* return the global timestamp for all contexts
*/
- header->timestamp_queued = -1;
+ header->timestamp_queued = device->ftbl->readtimestamp(device,
+ context, KGSL_TIMESTAMP_QUEUED);
header->timestamp_retired = device->ftbl->readtimestamp(device,
context, KGSL_TIMESTAMP_RETIRED);
@@ -229,7 +231,7 @@
* then offset the source pointer
*/
- offset = obj->gpuaddr - obj->entry->memdesc.gpuaddr;
+ offset = obj->offset;
/*
* Then adjust it to account for the offset for the output
@@ -333,6 +335,12 @@
}
}
+ if (kgsl_memdesc_map(&entry->memdesc) == NULL) {
+ KGSL_DRV_ERR(device, "Unable to map GPU buffer %X\n",
+ gpuaddr);
+ return 0;
+ }
+
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
if (obj == NULL) {
@@ -348,6 +356,7 @@
obj->gpuaddr = gpuaddr;
obj->ptbase = ptbase;
obj->size = size;
+ obj->offset = offset;
list_add(&obj->node, &device->snapshot_obj_list);
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index bc5c960..8c29535 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -304,15 +304,22 @@
return result;
}
-static inline unsigned int rb_offset(unsigned int index)
+static inline unsigned int rb_offset(unsigned int timestamp)
{
- return index*sizeof(unsigned int)*(Z180_PACKET_SIZE);
+ return (timestamp % Z180_PACKET_COUNT)
+ *sizeof(unsigned int)*(Z180_PACKET_SIZE);
}
-static void addmarker(struct z180_ringbuffer *rb, unsigned int index)
+static inline unsigned int rb_gpuaddr(struct z180_device *z180_dev,
+ unsigned int timestamp)
+{
+ return z180_dev->ringbuffer.cmdbufdesc.gpuaddr + rb_offset(timestamp);
+}
+
+static void addmarker(struct z180_ringbuffer *rb, unsigned int timestamp)
{
char *ptr = (char *)(rb->cmdbufdesc.hostptr);
- unsigned int *p = (unsigned int *)(ptr + rb_offset(index));
+ unsigned int *p = (unsigned int *)(ptr + rb_offset(timestamp));
*p++ = Z180_STREAM_PACKET;
*p++ = (Z180_MARKER_CMD | 5);
@@ -326,11 +333,11 @@
*p++ = ADDR_VGV3_LAST << 24;
}
-static void addcmd(struct z180_ringbuffer *rb, unsigned int index,
+static void addcmd(struct z180_ringbuffer *rb, unsigned int timestamp,
unsigned int cmd, unsigned int nextcnt)
{
char * ptr = (char *)(rb->cmdbufdesc.hostptr);
- unsigned int *p = (unsigned int *)(ptr + (rb_offset(index)
+ unsigned int *p = (unsigned int *)(ptr + (rb_offset(timestamp)
+ (Z180_MARKER_SIZE * sizeof(unsigned int))));
*p++ = Z180_STREAM_PACKET_CALL;
@@ -355,7 +362,7 @@
z180_cmdwindow_write(device, ADDR_VGV3_MODE, 4);
z180_cmdwindow_write(device, ADDR_VGV3_NEXTADDR,
- z180_dev->ringbuffer.cmdbufdesc.gpuaddr);
+ rb_gpuaddr(z180_dev, z180_dev->current_timestamp));
z180_cmdwindow_write(device, ADDR_VGV3_NEXTCMD, cmd | 5);
@@ -406,9 +413,7 @@
long result = 0;
unsigned int ofs = PACKETSIZE_STATESTREAM * sizeof(unsigned int);
unsigned int cnt = 5;
- unsigned int nextaddr = 0;
- unsigned int index = 0;
- unsigned int nextindex;
+ unsigned int old_timestamp = 0;
unsigned int nextcnt = Z180_STREAM_END_CMD | 5;
struct kgsl_mem_entry *entry = NULL;
unsigned int cmd;
@@ -477,26 +482,22 @@
}
result = 0;
- index = z180_dev->current_timestamp % Z180_PACKET_COUNT;
+ old_timestamp = z180_dev->current_timestamp;
z180_dev->current_timestamp++;
- nextindex = z180_dev->current_timestamp % Z180_PACKET_COUNT;
*timestamp = z180_dev->current_timestamp;
z180_dev->ringbuffer.prevctx = context->id;
- addcmd(&z180_dev->ringbuffer, index, cmd + ofs, cnt);
+ addcmd(&z180_dev->ringbuffer, old_timestamp, cmd + ofs, cnt);
kgsl_pwrscale_busy(device);
/* Make sure the next ringbuffer entry has a marker */
- addmarker(&z180_dev->ringbuffer, nextindex);
-
- nextaddr = z180_dev->ringbuffer.cmdbufdesc.gpuaddr
- + rb_offset(nextindex);
+ addmarker(&z180_dev->ringbuffer, z180_dev->current_timestamp);
/* monkey patch the IB so that it jumps back to the ringbuffer */
kgsl_sharedmem_writel(&entry->memdesc,
- ((sizedwords + 1) * sizeof(unsigned int)),
- nextaddr);
+ ((sizedwords + 1) * sizeof(unsigned int)),
+ rb_gpuaddr(z180_dev, z180_dev->current_timestamp));
kgsl_sharedmem_writel(&entry->memdesc,
((sizedwords + 2) * sizeof(unsigned int)),
nextcnt);
@@ -700,10 +701,9 @@
{
unsigned int *reg;
- BUG_ON(offsetwords * sizeof(uint32_t) >= device->regspace.sizebytes);
+ BUG_ON(offsetwords * sizeof(uint32_t) >= device->reg_len);
- reg = (unsigned int *)(device->regspace.mmio_virt_base
- + (offsetwords << 2));
+ reg = (unsigned int *)(device->reg_virt + (offsetwords << 2));
/*ensure this read finishes before the next one.
* i.e. act like normal readl() */
@@ -718,10 +718,9 @@
{
unsigned int *reg;
- BUG_ON(offsetwords*sizeof(uint32_t) >= device->regspace.sizebytes);
+ BUG_ON(offsetwords*sizeof(uint32_t) >= device->reg_len);
- reg = (unsigned int *)(device->regspace.mmio_virt_base
- + (offsetwords << 2));
+ reg = (unsigned int *)(device->reg_virt + (offsetwords << 2));
kgsl_cffdump_regwrite(device->id, offsetwords << 2, value);
/*ensure previous writes post before this one,
* i.e. act like normal writel() */
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 36c370e..3762bac 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -777,7 +777,7 @@
config SENSORS_MSM_ADC
tristate "MSM ADC Driver for current measurement"
- depends on ARCH_MSM7X30 || ARCH_MSM8X60 || ARCH_FSM9XXX
+ depends on ARCH_MSM7X30 || ARCH_MSM8X60 || ARCH_FSM9XXX || ARCH_MSM7X27A
default n
help
Provides interface for measuring the ADC's on AMUX channels of XOADC,
diff --git a/drivers/hwmon/msm_adc.c b/drivers/hwmon/msm_adc.c
index 39bfc3a..e4a607f 100644
--- a/drivers/hwmon/msm_adc.c
+++ b/drivers/hwmon/msm_adc.c
@@ -41,6 +41,9 @@
#define MSM_ADC_DALRC_CONV_TIMEOUT (5 * HZ) /* 5 seconds */
+#define MSM_8x25_ADC_DEV_ID 0
+#define MSM_8x25_CHAN_ID 16
+
enum dal_error {
DAL_ERROR_INVALID_DEVICE_IDX = 1,
DAL_ERROR_INVALID_CHANNEL_IDX,
@@ -1171,18 +1174,26 @@
goto dev_init_err;
}
- /* DAL device lookup */
- rc = msm_adc_getinputproperties(msm_adc, adc_dev->name,
+ if (!pdata->target_hw == MSM_8x25) {
+ /* DAL device lookup */
+ rc = msm_adc_getinputproperties(msm_adc, adc_dev->name,
&target);
- if (rc) {
- dev_err(&pdev->dev, "No such DAL device[%s]\n",
+ if (rc) {
+ dev_err(&pdev->dev, "No such DAL device[%s]\n",
adc_dev->name);
- goto dev_init_err;
+ goto dev_init_err;
+ }
+
+ adc_dev->transl.dal_dev_idx = target.dal.dev_idx;
+ adc_dev->nchans = target.dal.chan_idx;
+ } else {
+ /* On targets prior to MSM7x30 the remote driver has
+ only the channel list and no device id. */
+ adc_dev->transl.dal_dev_idx = MSM_8x25_ADC_DEV_ID;
+ adc_dev->nchans = MSM_8x25_CHAN_ID;
}
- adc_dev->transl.dal_dev_idx = target.dal.dev_idx;
adc_dev->transl.hwmon_dev_idx = i;
- adc_dev->nchans = target.dal.chan_idx;
adc_dev->transl.hwmon_start = hwmon_cntr;
adc_dev->transl.hwmon_end = hwmon_cntr + adc_dev->nchans - 1;
hwmon_cntr += adc_dev->nchans;
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index 212e5d5..acf551e 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -1465,6 +1465,7 @@
xfr_buf[1] = GET_ABS_VAL(band_low);
xfr_buf[2] = RSH_DATA(band_high, 8);
xfr_buf[3] = GET_ABS_VAL(band_high);
+ xfr_buf[4] = 0; /* Active LOW */
retval = sync_write_xfr(radio, RADIO_CONFIG, xfr_buf);
if (retval < 0) {
FMDERR("Could not set regional settings\n");
@@ -2156,6 +2157,7 @@
marimba_set_fm_status(radio->marimba, false);
wait_for_completion(&radio->shutdown_done);
radio->handle_irq = 1;
+ radio->lp_mode = 1;
atomic_inc(&radio->users);
radio->marimba->mod_id = SLAVE_ID_BAHAMA;
flush_workqueue(radio->wqueue);
@@ -3037,8 +3039,8 @@
} else if (ctrl->value == FM_ANALOG_PATH) {
FMDBG("Analog audio path enabled ...\n");
retval = tavarua_set_audio_path(
- TAVARUA_AUDIO_OUT_ANALOG_ON,
- TAVARUA_AUDIO_OUT_DIGITAL_OFF);
+ TAVARUA_AUDIO_OUT_DIGITAL_OFF,
+ TAVARUA_AUDIO_OUT_ANALOG_ON);
if (retval < 0) {
FMDERR("Error in tavarua_set_audio_path"
" %d\n", retval);
@@ -3891,10 +3893,27 @@
{
struct tavarua_device *radio = private_data;
int rx_on = radio->registers[RDCTRL] & FM_RECV;
+ int retval = 0;
if (!radio)
return -ENOMEM;
/* RX */
FMDBG("%s: digital: %d analog: %d\n", __func__, digital_on, analog_on);
+ if ((radio->pdata != NULL) && (radio->pdata->config_i2s_gpio != NULL)) {
+ if (digital_on) {
+ retval = radio->pdata->config_i2s_gpio(FM_I2S_ON);
+ if (retval) {
+ pr_err("%s: config_i2s_gpio failed\n",
+ __func__);
+ }
+ } else {
+ retval = radio->pdata->config_i2s_gpio(FM_I2S_OFF);
+ if (retval) {
+ pr_err("%s: config_i2s_gpio failed\n",
+ __func__);
+ }
+ }
+ }
+
SET_REG_FIELD(radio->registers[AUDIOCTRL],
((rx_on && analog_on) ? 1 : 0),
AUDIORX_ANALOG_OFFSET,
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 95255fe..07a31a3 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -569,6 +569,14 @@
Say Y here if you want to test video apps or debug V4L devices.
In doubt, say N.
+config MSM_VCAP
+ tristate "Qualcomm MSM VCAP"
+ depends on VIDEO_DEV && VIDEO_V4L2
+ default n
+ ---help---
+ Enables VCAP driver. This device allows for video capture and
+ video processing using the v4l2 api
+
source "drivers/media/video/davinci/Kconfig"
source "drivers/media/video/omap/Kconfig"
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index c4b240f..65a2348 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -156,6 +156,8 @@
obj-$(CONFIG_VIDEO_MEM2MEM_TESTDEV) += mem2mem_testdev.o
obj-$(CONFIG_VIDEO_CX23885) += cx23885/
+obj-$(CONFIG_MSM_VCAP) += vcap_v4l2.o
+obj-$(CONFIG_MSM_VCAP) += vcap_vc.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_OMAP2) += omap2cam.o
diff --git a/drivers/media/video/msm/Makefile b/drivers/media/video/msm/Makefile
index ca80fc1..3dea4e9 100644
--- a/drivers/media/video/msm/Makefile
+++ b/drivers/media/video/msm/Makefile
@@ -3,32 +3,33 @@
CFLAGS_REMOVE_msm_vfe8x.o = -Wframe-larger-than=1024
endif
+obj-$(CONFIG_MSM_CAMERA) += io/
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
EXTRA_CFLAGS += -Idrivers/media/video/msm/csi
EXTRA_CFLAGS += -Idrivers/media/video/msm/io
EXTRA_CFLAGS += -Idrivers/media/video/msm/sensors
obj-$(CONFIG_MSM_CAMERA) += msm_isp.o msm.o msm_mem.o msm_mctl.o msm_mctl_buf.o msm_mctl_pp.o
- obj-$(CONFIG_MSM_CAMERA) += io/ sensors/ actuators/ csi/
+ obj-$(CONFIG_MSM_CAMERA) += sensors/ actuators/ csi/
else
obj-$(CONFIG_MSM_CAMERA) += msm_camera.o
endif
obj-$(CONFIG_MSM_CAMERA) += msm_axi_qos.o gemini/
obj-$(CONFIG_MSM_CAMERA_FLASH) += flash.o
-obj-$(CONFIG_ARCH_MSM_ARM11) += msm_vfe7x.o msm_io7x.o
+obj-$(CONFIG_ARCH_MSM_ARM11) += msm_vfe7x.o
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
- obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a_v4l2.o msm_io_7x27a_v4l2.o
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a_v4l2.o
else
- obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a.o msm_io_7x27a.o
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a.o
endif
-obj-$(CONFIG_ARCH_QSD8X50) += msm_vfe8x.o msm_vfe8x_proc.o msm_io8x.o
+obj-$(CONFIG_ARCH_QSD8X50) += msm_vfe8x.o msm_vfe8x_proc.o
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
- obj-$(CONFIG_ARCH_MSM8X60) += msm_io_vfe31_v4l2.o msm_vfe31_v4l2.o msm_vpe.o
- obj-$(CONFIG_ARCH_MSM7X30) += msm_io_vfe31_v4l2.o msm_vfe31_v4l2.o msm_vpe.o msm_axi_qos.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_vfe31_v4l2.o msm_vpe.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_vfe31_v4l2.o msm_vpe.o msm_axi_qos.o
else
- obj-$(CONFIG_ARCH_MSM8X60) += msm_vfe31.o msm_io_8x60.o msm_vpe1.o
- obj-$(CONFIG_ARCH_MSM7X30) += msm_vfe31.o msm_io_vfe31.o msm_vpe1.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_vfe31.o msm_vpe1.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_vfe31.o msm_vpe1.o
endif
-obj-$(CONFIG_ARCH_MSM8960) += msm_io_8960.o msm_vfe32.o msm_vpe.o
+obj-$(CONFIG_ARCH_MSM8960) += msm_vfe32.o msm_vpe.o
obj-$(CONFIG_MT9T013) += mt9t013.o mt9t013_reg.o
obj-$(CONFIG_SN12M0PZ) += sn12m0pz.o sn12m0pz_reg.o
obj-$(CONFIG_MT9P012) += mt9p012_reg.o
diff --git a/drivers/media/video/msm/csi/msm_csic.c b/drivers/media/video/msm/csi/msm_csic.c
index 1ca4fa3..b4adbaf 100644
--- a/drivers/media/video/msm/csi/msm_csic.c
+++ b/drivers/media/video/msm/csi/msm_csic.c
@@ -150,9 +150,9 @@
csic_params = cfg_params->parms;
/* Enable error correction for DATA lane. Applies to all data lanes */
- msm_io_w(0x4, csicbase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csicbase + MIPI_PHY_CONTROL);
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csicbase + MIPI_PROTOCOL_CONTROL);
val = MIPI_PROTOCOL_CONTROL_LONG_PACKET_HEADER_CAPTURE_BMSK |
@@ -163,7 +163,7 @@
val |= csic_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csicbase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PROTOCOL_CONTROL);
val = (csic_params->settle_cnt <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
@@ -172,48 +172,48 @@
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
for (i = 0; i < csic_params->lane_cnt; i++)
- msm_io_w(val, csicbase + MIPI_PHY_D0_CONTROL2 + i * 4);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csicbase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csicbase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_D0_CONTROL);
val = (0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csicbase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csicbase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csicbase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csicbase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csicbase + MIPI_PHY_D3_CONTROL);
/* program number of lanes and lane mapping */
switch (csic_params->lane_cnt) {
case 1:
- msm_io_w(csic_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x4,
csicbase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csic_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x5,
csicbase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csic_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x6,
csicbase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csic_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x7,
csicbase + MIPI_CAMERA_CNTL);
break;
}
- msm_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits*/
- msm_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_STATUS);
return rc;
}
@@ -224,11 +224,11 @@
struct csic_device *csic_dev = data;
pr_info("msm_csic_irq: %x\n", (unsigned int)csic_dev->base);
- irq = msm_io_r(csic_dev->base + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csic_dev->base + MIPI_INTERRUPT_STATUS);
pr_info("%s MIPI_INTERRUPT_STATUS = 0x%x 0x%x\n",
- __func__, irq,
- msm_io_r(csic_dev->base + MIPI_PROTOCOL_CONTROL));
- msm_io_w(irq, csic_dev->base + MIPI_INTERRUPT_STATUS);
+ __func__, irq,
+ msm_camera_io_r(csic_dev->base + MIPI_PROTOCOL_CONTROL));
+ msm_camera_io_w(irq, csic_dev->base + MIPI_INTERRUPT_STATUS);
/* TODO: Needs to send this info to upper layers */
if ((irq >> 19) & 0x1)
@@ -285,6 +285,7 @@
if (rc < 0) {
csic_dev->hw_version = 0;
iounmap(csic_dev->base);
+ csic_dev->base = NULL;
return rc;
}
}
@@ -305,26 +306,26 @@
val = 0x0;
if (csic_dev->base != NULL) {
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csic_dev->base + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_CL_CONTROL);
msleep(20);
- val = msm_io_r(csic_dev->base + MIPI_PHY_D1_CONTROL);
+ val = msm_camera_io_r(csic_dev->base + MIPI_PHY_D1_CONTROL);
val &=
~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT)
|(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
- msm_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_MASK);
- msm_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_STATUS);
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csic_dev->base + MIPI_PROTOCOL_CONTROL);
- msm_io_w(0xE400, csic_dev->base + MIPI_CAMERA_CNTL);
+ msm_camera_io_w(0xE400, csic_dev->base + MIPI_CAMERA_CNTL);
}
}
@@ -427,6 +428,7 @@
}
disable_irq(new_csic_dev->irq->start);
iounmap(new_csic_dev->base);
+ new_csic_dev->base = NULL;
new_csic_dev->pdev = pdev;
return 0;
diff --git a/drivers/media/video/msm/csi/msm_csid.c b/drivers/media/video/msm/csi/msm_csid.c
index e531089..0cd2cf0 100644
--- a/drivers/media/video/msm/csi/msm_csid.c
+++ b/drivers/media/video/msm/csi/msm_csid.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -54,6 +54,8 @@
#define CSID_RST_DONE_IRQ_BITSHIFT 11
#define CSID_RST_STB_ALL 0x7FFF
+#define DBG_CSID 0
+
static int msm_csid_cid_lut(
struct msm_camera_csid_lut_params *csid_lut_params,
void __iomem *csidbase)
@@ -68,20 +70,34 @@
__func__, csid_lut_params->vc_cfg[i].dt);
return rc;
}
- val = msm_io_r(csidbase + CSID_CID_LUT_VC_0_ADDR +
+ val = msm_camera_io_r(csidbase + CSID_CID_LUT_VC_0_ADDR +
(csid_lut_params->vc_cfg[i].cid >> 2) * 4)
& ~(0xFF << csid_lut_params->vc_cfg[i].cid * 8);
val |= csid_lut_params->vc_cfg[i].dt <<
csid_lut_params->vc_cfg[i].cid * 8;
- msm_io_w(val, csidbase + CSID_CID_LUT_VC_0_ADDR +
+ msm_camera_io_w(val, csidbase + CSID_CID_LUT_VC_0_ADDR +
(csid_lut_params->vc_cfg[i].cid >> 2) * 4);
val = csid_lut_params->vc_cfg[i].decode_format << 4 | 0x3;
- msm_io_w(val, csidbase + CSID_CID_n_CFG_ADDR +
+ msm_camera_io_w(val, csidbase + CSID_CID_n_CFG_ADDR +
(csid_lut_params->vc_cfg[i].cid * 4));
}
return rc;
}
+#if DBG_CSID
+static void msm_csid_set_debug_reg(void __iomem *csidbase,
+ struct msm_camera_csid_params *csid_params)
+{
+ uint32_t val = 0;
+ val = ((1 << csid_params->lane_cnt) - 1) << 20;
+ msm_camera_io_w(0x7f010800 | val, csidbase + CSID_IRQ_MASK_ADDR);
+ msm_camera_io_w(0x7f010800 | val, csidbase + CSID_IRQ_CLEAR_CMD_ADDR);
+}
+#else
+static void msm_csid_set_debug_reg(void __iomem *csidbase,
+ struct msm_camera_csid_params *csid_params) {}
+#endif
+
static int msm_csid_config(struct csid_cfg_params *cfg_params)
{
int rc = 0;
@@ -100,17 +116,14 @@
val |= 0x1 << 12;
val |= 0x1 << 13;
val |= 0x1 << 28;
- msm_io_w(val, csidbase + CSID_CORE_CTRL_ADDR);
+ msm_camera_io_w(val, csidbase + CSID_CORE_CTRL_ADDR);
rc = msm_csid_cid_lut(&csid_params->lut_params, csidbase);
if (rc < 0)
return rc;
- val = ((1 << csid_params->lane_cnt) - 1) << 20;
- msm_io_w(0x7f010800 | val, csidbase + CSID_IRQ_MASK_ADDR);
- msm_io_w(0x7f010800 | val, csidbase + CSID_IRQ_CLEAR_CMD_ADDR);
+ msm_csid_set_debug_reg(csidbase, csid_params);
- msleep(20);
return rc;
}
@@ -118,18 +131,18 @@
{
uint32_t irq;
struct csid_device *csid_dev = data;
- irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
+ irq = msm_camera_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID%d_IRQ_STATUS_ADDR = 0x%x\n",
__func__, csid_dev->pdev->id, irq);
if (irq & (0x1 << CSID_RST_DONE_IRQ_BITSHIFT))
complete(&csid_dev->reset_complete);
- msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
+ msm_camera_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
return IRQ_HANDLED;
}
static void msm_csid_reset(struct csid_device *csid_dev)
{
- msm_io_w(CSID_RST_STB_ALL, csid_dev->base + CSID_RST_CMD_ADDR);
+ msm_camera_io_w(CSID_RST_STB_ALL, csid_dev->base + CSID_RST_CMD_ADDR);
wait_for_completion_interruptible(&csid_dev->reset_complete);
return;
}
@@ -193,7 +206,7 @@
}
csid_dev->hw_version =
- msm_io_r(csid_dev->base + CSID_HW_VERSION_ADDR);
+ msm_camera_io_r(csid_dev->base + CSID_HW_VERSION_ADDR);
*csid_version = csid_dev->hw_version;
init_completion(&csid_dev->reset_complete);
@@ -211,6 +224,7 @@
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 0);
vreg_config_failed:
iounmap(csid_dev->base);
+ csid_dev->base = NULL;
return rc;
}
@@ -231,6 +245,7 @@
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 0);
iounmap(csid_dev->base);
+ csid_dev->base = NULL;
return 0;
}
diff --git a/drivers/media/video/msm/csi/msm_csiphy.c b/drivers/media/video/msm/csi/msm_csiphy.c
index 0c1e0a4..aef017f 100644
--- a/drivers/media/video/msm/csi/msm_csiphy.c
+++ b/drivers/media/video/msm/csi/msm_csiphy.c
@@ -78,10 +78,10 @@
}
val = 0x3;
- msm_io_w((csiphy_params->lane_mask << 2) | val,
+ msm_camera_io_w((csiphy_params->lane_mask << 2) | val,
csiphybase + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
- msm_io_w(0x1, csiphybase + MIPI_CSIPHY_GLBL_T_INIT_CFG0_ADDR);
- msm_io_w(0x1, csiphybase + MIPI_CSIPHY_T_WAKEUP_CFG0_ADDR);
+ msm_camera_io_w(0x1, csiphybase + MIPI_CSIPHY_GLBL_T_INIT_CFG0_ADDR);
+ msm_camera_io_w(0x1, csiphybase + MIPI_CSIPHY_T_WAKEUP_CFG0_ADDR);
while (lane_mask & 0xf) {
if (!(lane_mask & 0x1)) {
@@ -89,26 +89,27 @@
lane_mask >>= 1;
continue;
}
- msm_io_w(0x10, csiphybase + MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*j);
- msm_io_w(csiphy_params->settle_cnt,
+ msm_camera_io_w(0x10,
+ csiphybase + MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*j);
+ msm_camera_io_w(csiphy_params->settle_cnt,
csiphybase + MIPI_CSIPHY_LNn_CFG3_ADDR + 0x40*j);
- msm_io_w(0x6F,
+ msm_camera_io_w(0x6F,
csiphybase + MIPI_CSIPHY_INTERRUPT_MASK0_ADDR +
0x4*(j+1));
- msm_io_w(0x6F,
+ msm_camera_io_w(0x6F,
csiphybase + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR +
0x4*(j+1));
j++;
lane_mask >>= 1;
}
- msm_io_w(0x10, csiphybase + MIPI_CSIPHY_LNCK_CFG2_ADDR);
- msm_io_w(csiphy_params->settle_cnt,
+ msm_camera_io_w(0x10, csiphybase + MIPI_CSIPHY_LNCK_CFG2_ADDR);
+ msm_camera_io_w(csiphy_params->settle_cnt,
csiphybase + MIPI_CSIPHY_LNCK_CFG3_ADDR);
- msm_io_w(0x24,
+ msm_camera_io_w(0x24,
csiphybase + MIPI_CSIPHY_INTERRUPT_MASK0_ADDR);
- msm_io_w(0x24,
+ msm_camera_io_w(0x24,
csiphybase + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
return rc;
}
@@ -117,36 +118,51 @@
{
uint32_t irq;
struct csiphy_device *csiphy_dev = data;
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS0_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS0_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS0 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS1_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR1_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS1_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR1_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS1 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS2_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR2_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS2_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR2_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS2 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS3_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR3_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS3_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR3_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS3 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS4_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS4_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS4 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- msm_io_w(0x1, csiphy_dev->base + 0x164);
- msm_io_w(0x0, csiphy_dev->base + 0x164);
+ msm_camera_io_w(0x1, csiphy_dev->base + 0x164);
+ msm_camera_io_w(0x0, csiphy_dev->base + 0x164);
return IRQ_HANDLED;
}
static void msm_csiphy_reset(struct csiphy_device *csiphy_dev)
{
- msm_io_w(0x1, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
+ msm_camera_io_w(0x1, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
usleep_range(5000, 8000);
- msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
+ msm_camera_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
}
static int msm_csiphy_subdev_g_chip_ident(struct v4l2_subdev *sd,
@@ -185,6 +201,7 @@
if (rc < 0) {
iounmap(csiphy_dev->base);
+ csiphy_dev->base = NULL;
return rc;
}
@@ -202,11 +219,11 @@
int i;
csiphy_dev = v4l2_get_subdevdata(sd);
for (i = 0; i < 4; i++)
- msm_io_w(0x0, csiphy_dev->base +
+ msm_camera_io_w(0x0, csiphy_dev->base +
MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*i);
- msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_LNCK_CFG2_ADDR);
- msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
+ msm_camera_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_LNCK_CFG2_ADDR);
+ msm_camera_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
#if DBG_CSIPHY
disable_irq(csiphy_dev->irq->start);
@@ -215,6 +232,7 @@
csiphy_dev->csiphy_clk, ARRAY_SIZE(csiphy_clk_info), 0);
iounmap(csiphy_dev->base);
+ csiphy_dev->base = NULL;
return 0;
}
diff --git a/drivers/media/video/msm/csi/msm_ispif.c b/drivers/media/video/msm/csi/msm_ispif.c
index f4dde2a..cbb9e03 100644
--- a/drivers/media/video/msm/csi/msm_ispif.c
+++ b/drivers/media/video/msm/csi/msm_ispif.c
@@ -118,7 +118,7 @@
intfnum++;
} /*end while */
if (rc >= 0) {
- msm_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
+ msm_camera_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
rc = wait_for_completion_interruptible(&ispif->reset_complete);
}
@@ -136,7 +136,7 @@
(0x1 << RDI_CSID_RST_STB) +
(0x1 << RDI_1_VFE_RST_STB) +
(0x1 << RDI_1_CSID_RST_STB);
- msm_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
+ msm_camera_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
return wait_for_completion_interruptible(&ispif->reset_complete);
}
@@ -162,9 +162,9 @@
if (rc < 0)
pr_err("%s: clk_set_rate failed %d\n", __func__, rc);
- data = msm_io_r(ispif->base + ISPIF_INPUT_SEL_ADDR);
+ data = msm_camera_io_r(ispif->base + ISPIF_INPUT_SEL_ADDR);
data |= csid<<(intftype*4);
- msm_io_w(data, ispif->base + ISPIF_INPUT_SEL_ADDR);
+ msm_camera_io_w(data, ispif->base + ISPIF_INPUT_SEL_ADDR);
}
static void msm_ispif_enable_intf_cids(uint8_t intftype, uint16_t cid_mask)
@@ -173,26 +173,26 @@
mutex_lock(&ispif->mutex);
switch (intftype) {
case PIX0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
data |= cid_mask;
- msm_io_w(data, ispif->base +
+ msm_camera_io_w(data, ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
data |= cid_mask;
- msm_io_w(data, ispif->base +
+ msm_camera_io_w(data, ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
data |= cid_mask;
- msm_io_w(data, ispif->base +
+ msm_camera_io_w(data, ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
}
@@ -208,11 +208,11 @@
params_len = params_list->len;
ispif_params = params_list->params;
CDBG("Enable interface\n");
- data = msm_io_r(ispif->base + ISPIF_PIX_STATUS_ADDR);
- data1 = msm_io_r(ispif->base + ISPIF_RDI_STATUS_ADDR);
+ data = msm_camera_io_r(ispif->base + ISPIF_PIX_STATUS_ADDR);
+ data1 = msm_camera_io_r(ispif->base + ISPIF_RDI_STATUS_ADDR);
if (((data & 0xf) != 0xf) || ((data1 & 0xf) != 0xf))
return -EBUSY;
- msm_io_w(0x00000000, ispif->base + ISPIF_IRQ_MASK_ADDR);
+ msm_camera_io_w(0x00000000, ispif->base + ISPIF_IRQ_MASK_ADDR);
for (i = 0; i < params_len; i++) {
msm_ispif_sel_csid_core(ispif_params[i].intftype,
ispif_params[i].csid);
@@ -220,11 +220,11 @@
ispif_params[i].cid_mask);
}
- msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_MASK_ADDR);
- msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_CLEAR_ADDR);
- msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
return rc;
}
@@ -234,17 +234,17 @@
uint32_t mask = 0;
switch (intftype) {
case PIX0:
- mask = msm_io_r(ispif->base +
+ mask = msm_camera_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
- mask = msm_io_r(ispif->base +
+ mask = msm_camera_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
- mask = msm_io_r(ispif->base +
+ mask = msm_camera_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
@@ -285,7 +285,8 @@
mask >>= 1;
intfnum++;
}
- msm_io_w(global_intf_cmd_mask, ispif->base + ISPIF_INTF_CMD_ADDR);
+ msm_camera_io_w(global_intf_cmd_mask,
+ ispif->base + ISPIF_INTF_CMD_ADDR);
}
static int msm_ispif_abort_intf_transfer(uint8_t intfmask)
@@ -327,7 +328,7 @@
if (intfmask & (0x1 << intfnum)) {
switch (intfnum) {
case PIX0:
- while ((msm_io_r(ispif->base +
+ while ((msm_camera_io_r(ispif->base +
ISPIF_PIX_STATUS_ADDR)
& 0xf) != 0xf) {
CDBG("Wait for pix0 Idle\n");
@@ -335,7 +336,7 @@
break;
case RDI0:
- while ((msm_io_r(ispif->base +
+ while ((msm_camera_io_r(ispif->base +
ISPIF_RDI_STATUS_ADDR)
& 0xf) != 0xf) {
CDBG("Wait for rdi0 Idle\n");
@@ -343,7 +344,7 @@
break;
case RDI1:
- while ((msm_io_r(ispif->base +
+ while ((msm_camera_io_r(ispif->base +
ISPIF_RDI_1_STATUS_ADDR)
& 0xf) != 0xf) {
CDBG("Wait for rdi1 Idle\n");
@@ -449,13 +450,13 @@
static inline void msm_ispif_read_irq_status(struct ispif_irq_status *out)
{
- out->ispifIrqStatus0 = msm_io_r(ispif->base +
+ out->ispifIrqStatus0 = msm_camera_io_r(ispif->base +
ISPIF_IRQ_STATUS_ADDR);
- out->ispifIrqStatus1 = msm_io_r(ispif->base +
+ out->ispifIrqStatus1 = msm_camera_io_r(ispif->base +
ISPIF_IRQ_STATUS_1_ADDR);
- msm_io_w(out->ispifIrqStatus0,
+ msm_camera_io_w(out->ispifIrqStatus0,
ispif->base + ISPIF_IRQ_CLEAR_ADDR);
- msm_io_w(out->ispifIrqStatus1,
+ msm_camera_io_w(out->ispifIrqStatus1,
ispif->base + ISPIF_IRQ_CLEAR_1_ADDR);
CDBG("ispif->irq: Irq_status0 = 0x%x\n",
@@ -473,7 +474,7 @@
ispif_process_irq(out);
}
}
- msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
}
@@ -543,17 +544,17 @@
int i = 0, j = 0;
switch (intftype) {
case PIX0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
diff --git a/drivers/media/video/msm/io/Makefile b/drivers/media/video/msm/io/Makefile
index c567be2..dddcbf6 100644
--- a/drivers/media/video/msm/io/Makefile
+++ b/drivers/media/video/msm/io/Makefile
@@ -1,4 +1,17 @@
GCC_VERSION := $(shell $(CONFIG_SHELL) $(PWD)/scripts/gcc-version.sh $(CROSS_COMPILE)gcc)
+
+obj-$(CONFIG_MSM_CAMERA) += msm_camera_io_util.o
EXTRA_CFLAGS += -Idrivers/media/video/msm
-obj-$(CONFIG_MSM_CAMERA) += msm_camera_i2c.o msm_camera_eeprom.o msm_camera_i2c_mux.o
-obj-$(CONFIG_MSM_CAMERA) += msm_io_util.o
+ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
+ obj-$(CONFIG_MSM_CAMERA) += msm_camera_i2c.o msm_camera_eeprom.o msm_camera_i2c_mux.o
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_io_7x27a_v4l2.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_io_vfe31_v4l2.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_io_vfe31_v4l2.o
+else
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_io_7x27a.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_io_8x60.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_io_vfe31.o
+endif
+obj-$(CONFIG_ARCH_MSM_ARM11) += msm_io7x.o
+obj-$(CONFIG_ARCH_QSD8X50) += msm_io8x.o
+obj-$(CONFIG_ARCH_MSM8960) += msm_io_8960.o
diff --git a/drivers/media/video/msm/io/msm_camera_i2c_mux.c b/drivers/media/video/msm/io/msm_camera_i2c_mux.c
index ad3128b..a6fbaf5 100644
--- a/drivers/media/video/msm/io/msm_camera_i2c_mux.c
+++ b/drivers/media/video/msm/io/msm_camera_i2c_mux.c
@@ -21,16 +21,16 @@
static int msm_i2c_mux_config(struct i2c_mux_device *mux_device, uint8_t *mode)
{
uint32_t val;
- val = msm_io_r(mux_device->ctl_base);
+ val = msm_camera_io_r(mux_device->ctl_base);
if (*mode == MODE_DUAL) {
- msm_io_w(val | 0x3, mux_device->ctl_base);
+ msm_camera_io_w(val | 0x3, mux_device->ctl_base);
} else if (*mode == MODE_L) {
- msm_io_w(((val | 0x2) & ~(0x1)), mux_device->ctl_base);
- val = msm_io_r(mux_device->ctl_base);
+ msm_camera_io_w(((val | 0x2) & ~(0x1)), mux_device->ctl_base);
+ val = msm_camera_io_r(mux_device->ctl_base);
CDBG("the camio mode config left value is %d\n", val);
} else {
- msm_io_w(((val | 0x1) & ~(0x2)), mux_device->ctl_base);
- val = msm_io_r(mux_device->ctl_base);
+ msm_camera_io_w(((val | 0x1) & ~(0x2)), mux_device->ctl_base);
+ val = msm_camera_io_r(mux_device->ctl_base);
CDBG("the camio mode config right value is %d\n", val);
}
return 0;
@@ -53,8 +53,8 @@
iounmap(mux_device->ctl_base);
return rc;
}
- val = msm_io_r(mux_device->rw_base);
- msm_io_w((val | 0x200), mux_device->rw_base);
+ val = msm_camera_io_r(mux_device->rw_base);
+ msm_camera_io_w((val | 0x200), mux_device->rw_base);
}
mux_device->use_count++;
return 0;
@@ -65,8 +65,8 @@
int val = 0;
mux_device->use_count--;
if (mux_device->use_count == 0) {
- val = msm_io_r(mux_device->rw_base);
- msm_io_w((val & ~0x200), mux_device->rw_base);
+ val = msm_camera_io_r(mux_device->rw_base);
+ msm_camera_io_w((val & ~0x200), mux_device->rw_base);
iounmap(mux_device->rw_base);
iounmap(mux_device->ctl_base);
}
diff --git a/drivers/media/video/msm/io/msm_io_util.c b/drivers/media/video/msm/io/msm_camera_io_util.c
similarity index 80%
rename from drivers/media/video/msm/io/msm_io_util.c
rename to drivers/media/video/msm/io/msm_camera_io_util.c
index cc6bab2..af60426 100644
--- a/drivers/media/video/msm/io/msm_io_util.c
+++ b/drivers/media/video/msm/io/msm_camera_io_util.c
@@ -14,10 +14,90 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
+#include <linux/io.h>
#include <mach/board.h>
#include <mach/camera.h>
#include <mach/gpiomux.h>
+#define BUFF_SIZE_128 128
+
+void msm_camera_io_w(u32 data, void __iomem *addr)
+{
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ writel_relaxed((data), (addr));
+}
+
+void msm_camera_io_w_mb(u32 data, void __iomem *addr)
+{
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ wmb();
+ writel_relaxed((data), (addr));
+ wmb();
+}
+
+u32 msm_camera_io_r(void __iomem *addr)
+{
+ uint32_t data = readl_relaxed(addr);
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ return data;
+}
+
+u32 msm_camera_io_r_mb(void __iomem *addr)
+{
+ uint32_t data;
+ rmb();
+ data = readl_relaxed(addr);
+ rmb();
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ return data;
+}
+
+void msm_camera_io_memcpy_toio(void __iomem *dest_addr,
+ void __iomem *src_addr, u32 len)
+{
+ int i;
+ u32 *d = (u32 *) dest_addr;
+ u32 *s = (u32 *) src_addr;
+
+ for (i = 0; i < len; i++)
+ writel_relaxed(*s++, d++);
+}
+
+void msm_camera_io_dump(void __iomem *addr, int size)
+{
+ char line_str[BUFF_SIZE_128], *p_str;
+ int i;
+ u32 *p = (u32 *) addr;
+ u32 data;
+ CDBG("%s: %p %d\n", __func__, addr, size);
+ line_str[0] = '\0';
+ p_str = line_str;
+ for (i = 0; i < size/4; i++) {
+ if (i % 4 == 0) {
+ snprintf(p_str, 12, "%08x: ", (u32) p);
+ p_str += 10;
+ }
+ data = readl_relaxed(p++);
+ snprintf(p_str, 12, "%08x ", data);
+ p_str += 9;
+ if ((i + 1) % 4 == 0) {
+ CDBG("%s\n", line_str);
+ line_str[0] = '\0';
+ p_str = line_str;
+ }
+ }
+ if (line_str[0] != '\0')
+ CDBG("%s\n", line_str);
+}
+
+void msm_camera_io_memcpy(void __iomem *dest_addr,
+ void __iomem *src_addr, u32 len)
+{
+ CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
+ msm_camera_io_memcpy_toio(dest_addr, src_addr, len / 4);
+ msm_camera_io_dump(dest_addr, len);
+}
+
int msm_cam_clk_enable(struct device *dev, struct msm_cam_clk_info *clk_info,
struct clk **clk_ptr, int num_clk, int enable)
{
diff --git a/drivers/media/video/msm/msm_io7x.c b/drivers/media/video/msm/io/msm_io7x.c
similarity index 82%
rename from drivers/media/video/msm/msm_io7x.c
rename to drivers/media/video/msm/io/msm_io7x.c
index 1befec6..8804106 100644
--- a/drivers/media/video/msm/msm_io7x.c
+++ b/drivers/media/video/msm/io/msm_io7x.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -205,7 +205,7 @@
/* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_SEL_BMSK |
CAM_PCLK_SRC_SEL_BMSK |
@@ -215,23 +215,23 @@
3 << CAM_PCLK_SRC_SEL_SHFT |
0 << CAM_PCLK_INVERT_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
- msleep(10);
+ usleep_range(10000, 11000);
}
void msm_camio_vfe_blk_reset(void)
@@ -239,26 +239,26 @@
uint32_t val;
/* do apps reset */
- val = readl(appbase + 0x00000210);
+ val = msm_camera_io_r_mb(appbase + 0x00000210);
val |= 0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000210);
+ usleep_range(10000, 11000);
- val = readl(appbase + 0x00000210);
+ val = msm_camera_io_r_mb(appbase + 0x00000210);
val &= ~0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000210);
+ usleep_range(10000, 11000);
/* do axi reset */
- val = readl(appbase + 0x00000208);
+ val = msm_camera_io_r_mb(appbase + 0x00000208);
val |= 0x1;
- writel(val, appbase + 0x00000208);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000208);
+ usleep_range(10000, 11000);
- val = readl(appbase + 0x00000208);
+ val = msm_camera_io_r_mb(appbase + 0x00000208);
val &= ~0x1;
- writel(val, appbase + 0x00000208);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000208);
+ usleep_range(10000, 11000);
}
void msm_camio_camif_pad_reg_reset_2(void)
@@ -266,17 +266,17 @@
uint32_t reg;
uint32_t mask, value;
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
}
void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
diff --git a/drivers/media/video/msm/msm_io8x.c b/drivers/media/video/msm/io/msm_io8x.c
similarity index 85%
rename from drivers/media/video/msm/msm_io8x.c
rename to drivers/media/video/msm/io/msm_io8x.c
index 6bc92b0..5f1f34f 100644
--- a/drivers/media/video/msm/msm_io8x.c
+++ b/drivers/media/video/msm/io/msm_io8x.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -213,7 +213,7 @@
/* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_SEL_BMSK |
CAM_PCLK_SRC_SEL_BMSK |
@@ -226,24 +226,24 @@
0 << CAM_PCLK_INVERT_SHFT |
0 << EXT_CAM_HSYNC_POL_SEL_SHFT |
0 << EXT_CAM_VSYNC_POL_SEL_SHFT | 0 << MDDI_CLK_CHICKEN_BIT_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
- msleep(10);
+ usleep_range(10000, 11000);
/* todo: check return */
if (camio_vfe_clk)
@@ -254,15 +254,15 @@
{
uint32_t val;
- val = readl(appbase + APPS_RESET_OFFSET);
+ val = msm_camera_io_r_mb(appbase + APPS_RESET_OFFSET);
val |= 0x1;
- writel(val, appbase + APPS_RESET_OFFSET);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + APPS_RESET_OFFSET);
+ usleep_range(10000, 11000);
- val = readl(appbase + APPS_RESET_OFFSET);
+ val = msm_camera_io_r_mb(appbase + APPS_RESET_OFFSET);
val &= ~0x1;
- writel(val, appbase + APPS_RESET_OFFSET);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + APPS_RESET_OFFSET);
+ usleep_range(10000, 11000);
}
void msm_camio_camif_pad_reg_reset_2(void)
@@ -270,17 +270,17 @@
uint32_t reg;
uint32_t mask, value;
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
}
void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
diff --git a/drivers/media/video/msm/msm_io_7x27a.c b/drivers/media/video/msm/io/msm_io_7x27a.c
similarity index 86%
rename from drivers/media/video/msm/msm_io_7x27a.c
rename to drivers/media/video/msm/io/msm_io_7x27a.c
index 7a83721..5ddf504 100644
--- a/drivers/media/video/msm/msm_io_7x27a.c
+++ b/drivers/media/video/msm/io/msm_io_7x27a.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -153,20 +153,6 @@
void __iomem *appbase;
-
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel((data), (addr));
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
int msm_camio_vfe_clk_rate_set(int rate)
{
int rc = 0;
@@ -292,9 +278,9 @@
{
uint32_t irq;
- irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
- msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
/* TODO: Needs to send this info to upper layers */
if ((irq >> 19) & 0x1)
@@ -338,15 +324,15 @@
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
appbase = ioremap(camio_ext.appphy,
camio_ext.appsz);
@@ -381,15 +367,15 @@
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(20);
free_irq(camio_ext.csiirq, 0);
@@ -435,25 +421,25 @@
uint32_t val;
/* do apps reset */
- val = readl_relaxed(appbase + 0x00000210);
+ val = msm_camera_io_r(appbase + 0x00000210);
val |= 0x1;
- writel_relaxed(val, appbase + 0x00000210);
+ msm_camera_io_w(val, appbase + 0x00000210);
usleep_range(10000, 11000);
- val = readl_relaxed(appbase + 0x00000210);
+ val = msm_camera_io_r(appbase + 0x00000210);
val &= ~0x1;
- writel_relaxed(val, appbase + 0x00000210);
+ msm_camera_io_w(val, appbase + 0x00000210);
usleep_range(10000, 11000);
/* do axi reset */
- val = readl_relaxed(appbase + 0x00000208);
+ val = msm_camera_io_r(appbase + 0x00000208);
val |= 0x1;
- writel_relaxed(val, appbase + 0x00000208);
+ msm_camera_io_w(val, appbase + 0x00000208);
usleep_range(10000, 11000);
- val = readl_relaxed(appbase + 0x00000208);
+ val = msm_camera_io_r(appbase + 0x00000208);
val &= ~0x1;
- writel_relaxed(val, appbase + 0x00000208);
+ msm_camera_io_w(val, appbase + 0x00000208);
mb();
usleep_range(10000, 11000);
return;
@@ -488,7 +474,7 @@
pr_err("ioremap failed for CSIBASE\n");
goto ioremap_fail;
}
- msm_io_w(MIPI_PWR_CNTL_DIS, csibase + MIPI_PWR_CNTL);
+ msm_camera_io_w(MIPI_PWR_CNTL_DIS, csibase + MIPI_PWR_CNTL);
iounmap(csibase);
ioremap_fail:
msm_camio_clk_disable(CAMIO_CSI0_PCLK);
@@ -504,9 +490,9 @@
CDBG("msm_camio_csi_config\n");
/* Enable error correction for DATA lane. Applies to all data lanes */
- msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csibase + MIPI_PHY_CONTROL);
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csibase + MIPI_PROTOCOL_CONTROL);
val = MIPI_PROTOCOL_CONTROL_LONG_PACKET_HEADER_CAPTURE_BMSK |
@@ -517,7 +503,7 @@
val |= csi_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
(0x1 <<
@@ -525,7 +511,7 @@
(0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
(0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
val = (csi_params->settle_cnt <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
@@ -533,51 +519,51 @@
(0x1 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
val = (0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
/* program number of lanes and lane mapping */
switch (csi_params->lane_cnt) {
case 1:
- msm_io_w(csi_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x4,
csibase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csi_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x5,
csibase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csi_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x6,
csibase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csi_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x7,
csibase + MIPI_CAMERA_CNTL);
break;
}
- msm_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits - write 1 clears the status*/
- msm_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_STATUS);
return rc;
}
diff --git a/drivers/media/video/msm/msm_io_7x27a_v4l2.c b/drivers/media/video/msm/io/msm_io_7x27a_v4l2.c
similarity index 93%
rename from drivers/media/video/msm/msm_io_7x27a_v4l2.c
rename to drivers/media/video/msm/io/msm_io_7x27a_v4l2.c
index 8b977ba..45761d5 100644
--- a/drivers/media/video/msm/msm_io_7x27a_v4l2.c
+++ b/drivers/media/video/msm/io/msm_io_7x27a_v4l2.c
@@ -32,19 +32,6 @@
static int apps_reset;
void __iomem *appbase;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
void msm_camio_clk_rate_set_2(struct clk *clk, int rate)
{
clk_set_rate(clk, rate);
diff --git a/drivers/media/video/msm/msm_io_8960.c b/drivers/media/video/msm/io/msm_io_8960.c
similarity index 74%
rename from drivers/media/video/msm/msm_io_8960.c
rename to drivers/media/video/msm/io/msm_io_8960.c
index 9bfc239..1ab4223 100644
--- a/drivers/media/video/msm/msm_io_8960.c
+++ b/drivers/media/video/msm/io/msm_io_8960.c
@@ -32,82 +32,6 @@
static struct clk *camio_imem_clk;
static struct regulator *fs_ijpeg;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel_relaxed for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[BUFF_SIZE_128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- snprintf(p_str, 12, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- snprintf(p_str, 12, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
-
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
int rc = 0;
diff --git a/drivers/media/video/msm/msm_io_8x60.c b/drivers/media/video/msm/io/msm_io_8x60.c
similarity index 87%
rename from drivers/media/video/msm/msm_io_8x60.c
rename to drivers/media/video/msm/io/msm_io_8x60.c
index 49ec461..4e8dc25 100644
--- a/drivers/media/video/msm/msm_io_8x60.c
+++ b/drivers/media/video/msm/io/msm_io_8x60.c
@@ -104,82 +104,6 @@
static int vpe_clk_rate;
struct msm_bus_scale_pdata *cam_bus_scale_table;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- sprintf(p_str, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- sprintf(p_str, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
-
static void msm_camera_vreg_enable(void)
{
ldo15 = regulator_get(NULL, "8058_l15");
@@ -462,10 +386,10 @@
{
uint32_t irq = 0;
if (csibase != NULL)
- irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
if (csibase != NULL)
- msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
@@ -631,22 +555,22 @@
val = 0x0;
if (csibase != NULL) {
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(20);
- val = msm_io_r(csibase + MIPI_PHY_D1_CONTROL);
+ val = msm_camera_io_r(csibase + MIPI_PHY_D1_CONTROL);
val &=
~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT)
|(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
- msm_io_w(0x0, csibase + MIPI_INTERRUPT_MASK);
- msm_io_w(0x0, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0x0, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0x0, csibase + MIPI_INTERRUPT_STATUS);
csi_free_irq();
iounmap(csibase);
csibase = NULL;
@@ -679,7 +603,7 @@
camio_clk = camdev->ioclk;
msm_camera_vreg_enable();
- msleep(10);
+ usleep_range(10000, 11000);
rc = camdev->camera_gpio_on();
if (rc < 0)
return rc;
@@ -735,10 +659,10 @@
CDBG("msm_camio_csi_config\n");
if (csibase != NULL) {
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
- msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csibase + MIPI_PHY_CONTROL);
/* SW_RST to the CSI core */
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csibase + MIPI_PROTOCOL_CONTROL);
/* PROTOCOL CONTROL */
@@ -750,7 +674,7 @@
val |= csi_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
@@ -761,50 +685,51 @@
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
for (i = 0; i < csi_params->lane_cnt; i++)
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
+ msm_camera_io_w(val,
+ csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
val =
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT)
|(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
/* halcyon only supports 1 or 2 lane */
switch (csi_params->lane_cnt) {
case 1:
- msm_io_w(csi_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x4,
csibase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csi_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x5,
csibase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csi_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x6,
csibase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csi_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x7,
csibase + MIPI_CAMERA_CNTL);
break;
}
/* mask out ID_ERROR[19], DATA_CMM_ERR[11]
and CLK_CMM_ERR[10] - de-featured */
- msm_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits*/
- msm_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_STATUS);
} else {
pr_info("CSIBASE is NULL");
}
diff --git a/drivers/media/video/msm/msm_io_vfe31.c b/drivers/media/video/msm/io/msm_io_vfe31.c
similarity index 85%
rename from drivers/media/video/msm/msm_io_vfe31.c
rename to drivers/media/video/msm/io/msm_io_vfe31.c
index e5b370c..7f3b7ae 100644
--- a/drivers/media/video/msm/msm_io_vfe31.c
+++ b/drivers/media/video/msm/io/msm_io_vfe31.c
@@ -130,82 +130,6 @@
static int reg_count;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- sprintf(p_str, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- sprintf(p_str, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
-
static void msm_camera_vreg_enable(struct platform_device *pdev)
{
int count, rc;
@@ -426,9 +350,9 @@
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
- irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
- msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
@@ -523,13 +447,13 @@
uint32_t val;
val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
usleep_range(9000, 10000);
free_irq(camio_ext.csiirq, 0);
iounmap(csibase);
@@ -558,23 +482,23 @@
uint32_t reg;
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
- msleep(10);
+ usleep_range(10000, 11000);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x3;
- msm_io_w(reg, camifpadbase);
- msleep(10);
+ msm_camera_io_w(reg, camifpadbase);
+ usleep_range(10000, 11000);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x10;
- msm_io_w(reg, camifpadbase);
- msleep(10);
+ msm_camera_io_w(reg, camifpadbase);
+ usleep_range(10000, 11000);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
/* Need to be uninverted*/
reg &= 0x03;
- msm_io_w(reg, camifpadbase);
- msleep(10);
+ msm_camera_io_w(reg, camifpadbase);
+ usleep_range(10000, 11000);
}
void msm_camio_vfe_blk_reset(void)
@@ -588,16 +512,16 @@
{
uint32_t reg;
uint32_t mask, value;
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
- mdelay(10);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ msm_camera_io_w((reg & (~mask)) | (value & mask), camifpadbase);
+ usleep_range(10000, 11000);
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
- mdelay(10);
+ msm_camera_io_w((reg & (~mask)) | (value & mask), camifpadbase);
+ usleep_range(10000, 11000);
}
void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
@@ -707,10 +631,10 @@
CDBG("msm_camio_csi_config\n");
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
- msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csibase + MIPI_PHY_CONTROL);
/* SW_RST to the CSI core */
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csibase + MIPI_PROTOCOL_CONTROL);
/* PROTOCOL CONTROL */
@@ -722,7 +646,7 @@
val |= csi_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
/* SW CAL EN */
val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
@@ -731,7 +655,7 @@
(0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
(0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
@@ -742,49 +666,49 @@
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
for (i = 0; i < csi_params->lane_cnt; i++)
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
val = (0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
/* halcyon only supports 1 or 2 lane */
switch (csi_params->lane_cnt) {
case 1:
- msm_io_w(csi_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x4,
csibase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csi_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x5,
csibase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csi_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x6,
csibase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csi_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x7,
csibase + MIPI_CAMERA_CNTL);
break;
}
/* mask out ID_ERROR[19], DATA_CMM_ERR[11]
and CLK_CMM_ERR[10] - de-featured */
- msm_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits*/
- msm_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_STATUS);
return rc;
}
diff --git a/drivers/media/video/msm/msm_io_vfe31_v4l2.c b/drivers/media/video/msm/io/msm_io_vfe31_v4l2.c
similarity index 81%
rename from drivers/media/video/msm/msm_io_vfe31_v4l2.c
rename to drivers/media/video/msm/io/msm_io_vfe31_v4l2.c
index 03810f4..451cb5a 100644
--- a/drivers/media/video/msm/msm_io_vfe31_v4l2.c
+++ b/drivers/media/video/msm/io/msm_io_vfe31_v4l2.c
@@ -42,81 +42,6 @@
static struct regulator *fs_vpe;
static int vpe_clk_rate;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[BUFF_SIZE_128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- snprintf(p_str, 12, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- snprintf(p_str, 12, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
diff --git a/drivers/media/video/msm/msm_axi_qos.c b/drivers/media/video/msm/msm_axi_qos.c
index 3969547..eaceceb 100644
--- a/drivers/media/video/msm/msm_axi_qos.c
+++ b/drivers/media/video/msm/msm_axi_qos.c
@@ -22,8 +22,10 @@
ebi1_clk = clk_get(NULL, "ebi1_vfe_clk");
if (IS_ERR(ebi1_clk))
ebi1_clk = NULL;
- else
+ else {
+ clk_prepare(ebi1_clk);
clk_enable(ebi1_clk);
+ }
return 0;
}
@@ -42,6 +44,7 @@
return;
clk_disable(ebi1_clk);
+ clk_unprepare(ebi1_clk);
clk_put(ebi1_clk);
ebi1_clk = NULL;
}
diff --git a/drivers/media/video/msm/msm_vfe31.c b/drivers/media/video/msm/msm_vfe31.c
index 1c9fd03..2929538 100644
--- a/drivers/media/video/msm/msm_vfe31.c
+++ b/drivers/media/video/msm/msm_vfe31.c
@@ -23,14 +23,6 @@
#include "msm_vpe1.h"
atomic_t irq_cnt;
-#define CHECKED_COPY_FROM_USER(in) { \
- if (copy_from_user((in), (void __user *)cmd->value, \
- cmd->length)) { \
- rc = -EFAULT; \
- break; \
- } \
-}
-
static struct vfe31_ctrl_type *vfe31_ctrl;
static struct msm_camera_io_clk camio_clk;
static void *vfe_syncdata;
@@ -505,33 +497,33 @@
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* now enable only halt_irq & reset_irq */
- msm_io_w(0xf0000000, /* this is for async timer. */
+ msm_camera_io_w(0xf0000000, /* this is for async timer. */
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_AXI_HALT,
+ msm_camera_io_w(VFE_IMASK_AXI_HALT,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* then apply axi halt command. */
- msm_io_w_mb(AXI_HALT,
+ msm_camera_io_w_mb(AXI_HALT,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
}
@@ -1020,7 +1012,8 @@
default:
break;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[V31_AXI_OUT_CFG].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[V31_AXI_OUT_CFG].offset,
ao, vfe31_cmd[V31_AXI_OUT_CFG].length - V31_AXI_CH_INF_LEN);
return 0;
@@ -1098,26 +1091,28 @@
vfe31_reset_internal_variables();
vfe31_reset_hist_cfg();
- vfe_version = msm_io_r(vfe31_ctrl->vfebase);
+ vfe_version = msm_camera_io_r(vfe31_ctrl->vfebase);
CDBG("vfe_version = 0x%x\n", vfe_version);
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
- msm_io_w(VFE_IMASK_RESET,
+ msm_camera_io_w(VFE_IMASK_RESET,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
@@ -1127,7 +1122,7 @@
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_RESET_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -1142,11 +1137,11 @@
vfe31_ctrl->stats_comp = *(++p);
vfe31_ctrl->hfr_mode = *(++p);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG_OFF);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG_OFF);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
wmb();
return 0;
}
@@ -1156,9 +1151,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe31_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
@@ -1170,9 +1167,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe31_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1184,9 +1183,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe31_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1198,9 +1199,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe31_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1212,9 +1215,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe31_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1225,9 +1230,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe31_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1249,23 +1256,23 @@
if (VFE_MODE_OF_OPERATION_VIDEO == vfe31_ctrl->operation_mode)
irq_mask |= 0x4;
- msm_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_RESET,
+ msm_camera_io_w(VFE_IMASK_RESET,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* enable out of order option */
- msm_io_w(0x80000000, vfe31_ctrl->vfebase + VFE_AXI_CFG);
+ msm_camera_io_w(0x80000000, vfe31_ctrl->vfebase + VFE_AXI_CFG);
/* enable performance monitor */
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CFG);
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CMD);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CFG);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CMD);
- msm_io_dump(vfe31_ctrl->vfebase, 0x600);
+ msm_camera_io_dump(vfe31_ctrl->vfebase, 0x600);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
wmb();
atomic_set(&vfe31_ctrl->vstate, 1);
@@ -1276,14 +1283,14 @@
msm_camio_set_perf_lvl(S_VIDEO);
usleep(1000);
vfe31_ctrl->recording_state = VFE_REC_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
static int vfe31_stop_recording(void)
{
vfe31_ctrl->recording_state = VFE_REC_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_set_perf_lvl(S_PREVIEW);
return 0;
}
@@ -1309,7 +1316,7 @@
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
vfe31_ctrl->operation_mode, vfe31_ctrl->outpath.output_mode);
@@ -1335,39 +1342,39 @@
(0x1 << (vfe31_ctrl->outpath.out2.ch1 + 8)));
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_P) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_P_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_T) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_S) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch1]);
}
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
vfe31_start_common();
msm_camio_set_perf_lvl(S_ZSL);
usleep(1000);
/* for debug */
- msm_io_w(1, vfe31_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x188);
return 0;
}
@@ -1384,7 +1391,7 @@
}
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if ((vfe31_ctrl->operation_mode ==
VFE_MODE_OF_OPERATION_SNAPSHOT) ||
@@ -1401,15 +1408,15 @@
(0x1 << (vfe31_ctrl->outpath.out1.ch1 + 8)));
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PT) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_S) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
} else { /* this is raw snapshot mode. */
@@ -1417,11 +1424,11 @@
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_S) {
irq_comp_mask |=
(0x1 << (vfe31_ctrl->outpath.out1.ch0 + 8));
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
}
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (p_sync->stereocam_enabled)
msm_camio_set_perf_lvl(S_STEREO_CAPTURE);
else
@@ -1441,7 +1448,7 @@
(vfe31_ctrl->operation_mode != VFE_MODE_OF_OPERATION_VIDEO))
return 0;
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PT) {
irq_comp_mask |= (0x1 << vfe31_ctrl->outpath.out0.ch0 |
@@ -1463,24 +1470,24 @@
0x1 << (vfe31_ctrl->outpath.out2.ch1 + 16));
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PT) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
if (vfe31_ctrl->outpath.out0.ch2 >= 0)
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_P_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
@@ -1500,17 +1507,21 @@
CDBG("vfe31_update\n");
if (vfe31_ctrl->update_gamma) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF))
- msm_io_w(7, vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF))
+ msm_camera_io_w(7,
+ vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
+ msm_camera_io_w(0,
+ vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
vfe31_ctrl->update_gamma = false;
}
if (vfe31_ctrl->update_luma) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF))
- msm_io_w(1, vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF))
+ msm_camera_io_w(1,
+ vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
+ msm_camera_io_w(0,
+ vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
vfe31_ctrl->update_luma = false;
}
spin_lock_irqsave(&vfe31_ctrl->update_ack_lock, flags);
@@ -1518,7 +1529,7 @@
spin_unlock_irqrestore(&vfe31_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
@@ -1534,7 +1545,7 @@
value = 0x40000;
/* Timer Stop */
- msm_io_w_mb(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w_mb(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
}
static void vfe31_sync_timer_start(const uint32_t *tbl)
@@ -1559,29 +1570,30 @@
}
/* Timer Start */
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
4 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
8 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
val = camio_clk.vfe_clk_rate / 10000;
val = 10000000 / val;
val = value * 10000 / val;
- CDBG("%s: Pixel Clk Cycles!!! %d \n", __func__, val);
- msm_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
+ msm_camera_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
12 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
+ msm_camera_io_w(value,
+ vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
wmb();
}
@@ -1591,9 +1603,9 @@
uint32_t value = VFE_DMI_CFG_DEFAULT;
value += (uint32_t)bankSel;
- msm_io_w_mb(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w_mb(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
wmb();
}
static void vfe31_write_gamma_cfg(enum VFE31_DMI_RAM_SEL channel_sel,
@@ -1607,8 +1619,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1620,7 +1634,7 @@
vfe31_program_dmi_cfg(STATS_HIST_RAM);
for (i = 0 ; i < VFE31_HIST_TABLE_LENGTH ; i++)
- msm_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1636,8 +1650,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1725,11 +1741,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1745,11 +1762,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1765,12 +1783,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1786,12 +1805,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1839,14 +1859,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= RS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- */
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1862,14 +1877,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= CS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- */
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1878,7 +1888,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1894,20 +1904,23 @@
new_val = *cmdp_local;
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
- &new_val, 4);
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
+ &new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
- &new_val, 4);
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
+ &new_val, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp_local, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp_local, (vfe31_cmd[cmd->id].length));
}
break;
case V31_DEMOSAIC_2_UPDATE: /* 38 BPC update */
@@ -1926,15 +1939,17 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
old_val &= BPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1954,17 +1969,19 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp_local, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp_local, (vfe31_cmd[cmd->id].length));
}
break;
case V31_ROLL_OFF_CFG: {
@@ -1979,23 +1996,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, 16);
cmdp_local += 4;
vfe31_program_dmi_cfg(ROLLOFF_RAM);
/* for loop for extrcting init table. */
for (i = 0 ; i < (VFE31_ROLL_OFF_INIT_TABLE_SIZE * 2) ; i++) {
- msm_io_w(*cmdp_local ,
+ msm_camera_io_w(*cmdp_local ,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
- CDBG("done writing init table \n");
+ CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
- msm_io_w(LENS_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(LENS_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe31_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0 ; i < (VFE31_ROLL_OFF_DELTA_TABLE_SIZE * 2) ; i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
@@ -2018,8 +2036,9 @@
}
/* Select Bank 0*/
*cmdp = 0;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
cmdp += 1;
vfe31_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0 , cmdp);
cmdp -= 1;
@@ -2039,7 +2058,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
cmdp += 1;
if (old_val != 0x0)
vfe31_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0 , cmdp);
@@ -2063,7 +2083,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
cmdp, V31_SCE_LEN);
}
break;
@@ -2095,7 +2115,7 @@
}
/* Select Bank 0*/
*cmdp = 0;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
vfe31_write_gamma_cfg(RGBLUT_CHX_BANK0, cmdp);
@@ -2114,7 +2134,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF);
cmdp += 1;
if (!old_val) {
@@ -2128,47 +2149,47 @@
break;
case V31_STATS_AWB_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_AE_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_AF_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_IHIST_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_RS_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_CS_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
@@ -2205,11 +2226,12 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -2224,8 +2246,15 @@
goto proc_general_done;
}
- CHECKED_COPY_FROM_USER(cmdp);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ if (copy_from_user(cmdp, (void __user *)cmd->value,
+ cmd->length)) {
+ rc = -EFAULT;
+ pr_err("%s copy from user failed for cmd %d",
+ __func__, cmd->id);
+ goto proc_general_done;
+ }
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -2672,34 +2701,34 @@
unsigned long flags;
if (vfe31_ctrl->recording_state == VFE_REC_STATE_START_REQUESTED) {
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_V) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch1]);
}
vfe31_ctrl->recording_state = VFE_REC_STATE_STARTED;
if (vpe_ctrl->dis_en) {
- old_val = msm_io_r(
+ old_val = msm_camera_io_r(
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= RS_CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe31_ctrl->recording_state
== VFE_REC_STATE_STOP_REQUESTED) {
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_V) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch1]);
}
/*disable rs& cs when stop recording. */
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= (~RS_CS_ENABLE_MASK);
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
CDBG("stop video triggered\n");
}
@@ -2710,7 +2739,7 @@
if (vfe31_ctrl->recording_state ==
VFE_REC_STATE_STOP_REQUESTED) {
vfe31_ctrl->recording_state = VFE_REC_STATE_STOPPED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
} else if (vfe31_ctrl->recording_state ==
VFE_REC_STATE_STOPPED) {
@@ -2741,67 +2770,74 @@
/* stop the bus output: write master enable = 0*/
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PT) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[
vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_S) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch1]);
}
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* Ensure the read order while reading
to the command register using the barrier */
- temp = msm_io_r_mb(vfe31_ctrl->vfebase +
+ temp = msm_camera_io_r_mb(vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
/* then do reg_update. */
- msm_io_w_mb(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
static void vfe31_set_default_reg_values(void)
{
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
- msm_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- msm_io_w(0xFFFFFFFF, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0xFFFFFFFF,
+ vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
- msm_io_w(0x3980007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
- msm_io_w(0x3A00007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
- msm_io_w(0x3A8000F, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
- msm_io_w(0x3B80007, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
- msm_io_w(0x3C0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
- msm_io_w(0x3E0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ msm_camera_io_w(0x3980007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ msm_camera_io_w(0x3A00007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ msm_camera_io_w(0x3A8000F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ msm_camera_io_w(0x3B80007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ msm_camera_io_w(0x3C0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ msm_camera_io_w(0x3E0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
static void vfe31_process_reset_irq(void)
@@ -2817,7 +2853,7 @@
vfe31_set_default_reg_values();
/* reload all write masters. (frame & line)*/
- msm_io_w_mb(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
+ msm_camera_io_w_mb(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
vfe31_send_msg_no_payload(MSG_ID_RESET_ACK);
}
}
@@ -2827,36 +2863,36 @@
{
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(AXI_HALT_CLEAR,
+ msm_camera_io_w_mb(AXI_HALT_CLEAR,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
vfe31_ctrl->while_stopping_mask = VFE_IMASK_RESET;
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* now enable only halt_irq & reset_irq */
- msm_io_w(0xf0000000, /* this is for async timer. */
+ msm_camera_io_w(0xf0000000, /* this is for async timer. */
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_RESET,
+ msm_camera_io_w(VFE_IMASK_RESET,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
CDBG("%s: about to reset vfe...\n", __func__);
- msm_io_w_mb(VFE_RESET_UPON_STOP_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -2878,9 +2914,9 @@
if (vfe31_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
- temp = msm_io_r_mb(vfe31_ctrl->vfebase +
+ temp = msm_camera_io_r_mb(vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
@@ -2912,7 +2948,7 @@
if (errStatus & VFE31_IMASK_CAMIF_ERROR) {
pr_err("vfe31_irq: camif errors\n");
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
- camifStatus = msm_io_r(temp);
+ camifStatus = msm_camera_io_r(temp);
pr_err("camifStatus = 0x%x\n", camifStatus);
vfe31_send_msg_no_payload(MSG_ID_CAMIF_ERROR);
}
@@ -2980,21 +3016,21 @@
if (errStatus & VFE31_IMASK_AXI_ERROR) {
pr_err("vfe31_irq: axi error\n");
/* read status too when overflow happens.*/
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
pr_debug("VFE_BUS_PING_PONG_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_OPERATION_STATUS);
pr_debug("VFE_BUS_OPERATION_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_AXI_STATUS);
pr_debug("VFE_AXI_STATUS = 0x%x\n", read_val);
}
@@ -3002,17 +3038,18 @@
#define VFE31_AXI_OFFSET 0x0050
#define vfe31_get_ch_ping_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_get_ch_pong_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_get_ch_addr(ping_pong, chn) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_get_ch_pong_addr(chn) : vfe31_get_ch_ping_addr(chn))
#define vfe31_put_ch_ping_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_put_ch_pong_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_w((addr), \
+ vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_put_ch_addr(ping_pong, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_put_ch_pong_addr((chn), (addr)) : \
@@ -3171,7 +3208,7 @@
vfe31_send_msg_no_payload(MSG_ID_SNAPSHOT_DONE);
/* Ensure the write order while writing
to the cmd register using barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
@@ -3215,7 +3252,7 @@
vfe31_send_msg_no_payload(MSG_ID_SNAPSHOT_DONE);
/* Ensure the write order while writing
to the cmd register using barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
@@ -3443,7 +3480,7 @@
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_io_r(vfe31_ctrl->vfebase +
+ ((msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
@@ -3452,8 +3489,8 @@
((uint32_t)(vfe31_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
- returnAddr = msm_io_r((uint32_t *)pingpongAddr);
- msm_io_w(newAddr, (uint32_t *)pingpongAddr);
+ returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
+ msm_camera_io_w(newAddr, (uint32_t *)pingpongAddr);
return returnAddr;
}
@@ -3475,7 +3512,7 @@
msg._u.msgStats.buff.rs = vfe31_ctrl->rsStatsControl.bufToRender;
msg._u.msgStats.buff.cs = vfe31_ctrl->csStatsControl.bufToRender;
- temp = msm_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msg._u.msgStats.buff.awb_ymin = (0xFF00 & temp) >> 8;
vfe31_proc_ops(msg._d,
@@ -3736,32 +3773,34 @@
memset(&irq, 0, sizeof(struct vfe31_irq_status));
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_0);
- irq.vfeIrqStatus0 = msm_io_r(val);
+ irq.vfeIrqStatus0 = msm_camera_io_r(val);
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_1);
- irq.vfeIrqStatus1 = msm_io_r(val);
+ irq.vfeIrqStatus1 = msm_camera_io_r(val);
if (irq.vfeIrqStatus1 & VFE_IMASK_AXI_HALT) {
- msm_io_w(VFE_IMASK_RESET, vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
-
- msm_io_w_mb(AXI_HALT_CLEAR,
+ msm_camera_io_w(VFE_IMASK_RESET,
+ vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
+ msm_camera_io_w_mb(AXI_HALT_CLEAR,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
}
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
- irq.camifStatus = msm_io_r(val);
+ irq.camifStatus = msm_camera_io_r(val);
CDBG("camifStatus = 0x%x\n", irq.camifStatus);
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_BUS_PING_PONG_STATUS);
- irq.vfePingPongStatus = msm_io_r(val);
+ irq.vfePingPongStatus = msm_camera_io_r(val);
/* clear the pending interrupt of the same kind.*/
- msm_io_w(irq.vfeIrqStatus0, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(irq.vfeIrqStatus1, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(irq.vfeIrqStatus0,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(irq.vfeIrqStatus1,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
if ((irq.vfeIrqStatus0 == 0) && (irq.vfeIrqStatus1 == 0)) {
CDBG("vfe_parse_irq: vfeIrqStatus0 & 1 are both 0!\n");
@@ -3785,7 +3824,7 @@
VFE_IRQ_STATUS0_CAMIF_EOF_MASK) &&
vfe31_ctrl->xbar_update_pending) {
CDBG("irq camifEofIrq\n");
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_XBAR_CFG_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_XBAR_CFG_OFF,
(void *)vfe31_ctrl->xbar_cfg, V31_XBAR_CFG_LEN);
vfe31_ctrl->xbar_update_pending = 0;
}
diff --git a/drivers/media/video/msm/msm_vfe31_v4l2.c b/drivers/media/video/msm/msm_vfe31_v4l2.c
index ea181df..da9e071 100644
--- a/drivers/media/video/msm/msm_vfe31_v4l2.c
+++ b/drivers/media/video/msm/msm_vfe31_v4l2.c
@@ -33,17 +33,18 @@
#define VFE31_AXI_OFFSET 0x0050
#define vfe31_get_ch_ping_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_get_ch_pong_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_get_ch_addr(ping_pong, chn) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_get_ch_pong_addr(chn) : vfe31_get_ch_ping_addr(chn))
#define vfe31_put_ch_ping_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_put_ch_pong_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_w((addr), \
+ vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_put_ch_addr(ping_pong, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_put_ch_pong_addr((chn), (addr)) : \
@@ -378,36 +379,36 @@
/* disable all interrupts. */
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* now enable only halt_irq & reset_irq */
- msm_io_w(0xf0000000, /* this is for async timer. */
+ msm_camera_io_w(0xf0000000, /* this is for async timer. */
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* then apply axi halt command. */
- msm_io_w_mb(AXI_HALT,
+ msm_camera_io_w_mb(AXI_HALT,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
- msm_io_w_mb(VFE_RESET_UPON_STOP_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -478,7 +479,7 @@
return -EINVAL;
}
- msm_io_memcpy(vfe31_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase +
vfe31_cmd[VFE_CMD_AXI_OUT_CFG].offset, axi_cfg,
vfe31_cmd[VFE_CMD_AXI_OUT_CFG].length - V31_AXI_CH_INF_LEN -
V31_AXI_RESERVED);
@@ -544,22 +545,24 @@
vfe31_reset_internal_variables();
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
@@ -569,7 +572,7 @@
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_RESET_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -581,11 +584,11 @@
vfe31_ctrl->stats_comp = *(++p);
vfe31_ctrl->hfr_mode = *(++p);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
return 0;
}
@@ -595,9 +598,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe31_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
@@ -608,9 +613,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe31_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -622,9 +629,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe31_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -636,9 +645,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe31_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -650,9 +661,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe31_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -664,15 +677,17 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe31_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static void msm_io_dump2(void __iomem *addr, int size)
+static void msm_camera_io_dump2(void __iomem *addr, int size)
{
char line_str[BUFF_SIZE_128], *p_str;
int i;
@@ -710,16 +725,16 @@
else
irq_mask |= 0x000FE000;
- msm_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
- msm_io_dump2(vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
+ msm_camera_io_dump2(vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
atomic_set(&vfe31_ctrl->vstate, 1);
}
@@ -729,7 +744,7 @@
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_VIDEO);
vfe31_ctrl->recording_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
@@ -737,7 +752,7 @@
{
struct msm_sync *sync = vfe_syncdata;
vfe31_ctrl->recording_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
return 0;
@@ -753,7 +768,7 @@
vfe31_ctrl->vfe_capture_count = vfe31_ctrl->outpath.out0.capture_cnt;
vfe31_ctrl->liveshot_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
}
static int vfe31_zsl(void)
@@ -762,7 +777,7 @@
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
vfe31_ctrl->operation_mode, vfe31_ctrl->outpath.output_mode);
@@ -788,42 +803,42 @@
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch2]);
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
vfe31_start_common();
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_ZSL);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x188);
return 0;
}
static int vfe31_capture_raw(uint32_t num_frames_capture)
@@ -835,15 +850,15 @@
vfe31_ctrl->vfe_capture_count = num_frames_capture;
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << (vfe31_ctrl->outpath.out0.ch0));
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe31_start_common();
@@ -869,7 +884,8 @@
}
vfe31_ctrl->vfe_capture_count = num_frames_capture;
- irq_comp_mask = msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ irq_comp_mask = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
vfe31_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
@@ -887,31 +903,31 @@
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
}
vfe31_ctrl->vfe_capture_count = num_frames_capture;
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe31_start_common();
/* for debug */
- msm_io_w(1, vfe31_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x188);
return 0;
}
@@ -921,7 +937,7 @@
struct msm_sync *sync = vfe_syncdata;
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << vfe31_ctrl->outpath.out0.ch0 |
@@ -941,41 +957,41 @@
0x1 << (vfe31_ctrl->outpath.out1.ch1 + 8) |
0x1 << (vfe31_ctrl->outpath.out1.ch2 + 8));
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
switch (vfe31_ctrl->operation_mode) {
case VFE_OUTPUTS_PREVIEW:
case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
break;
default:
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch2]);
}
break;
@@ -991,18 +1007,18 @@
unsigned long flags;
if (vfe31_ctrl->update_la) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
- msm_io_w(1, vfe31_ctrl->vfebase + V31_LA_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + V31_LA_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase + V31_LA_OFF);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + V31_LA_OFF);
vfe31_ctrl->update_la = false;
}
if (vfe31_ctrl->update_gamma) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF))
- msm_io_w(7, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF))
+ msm_camera_io_w(7, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
vfe31_ctrl->update_gamma = false;
}
@@ -1011,7 +1027,7 @@
spin_unlock_irqrestore(&vfe31_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
@@ -1027,7 +1043,7 @@
value = 0x40000;
/* Timer Stop */
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
}
static void vfe31_sync_timer_start(const uint32_t *tbl)
@@ -1052,14 +1068,14 @@
}
/* Timer Start */
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
4 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
8 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
@@ -1067,14 +1083,15 @@
val = 10000000 / val;
val = value * 10000 / val;
CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
- msm_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
12 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
+ msm_camera_io_w(value,
+ vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
}
static void vfe31_program_dmi_cfg(enum VFE31_DMI_RAM_SEL bankSel)
@@ -1084,9 +1101,9 @@
value += (uint32_t)bankSel;
CDBG("%s: banksel = %d\n", __func__, bankSel);
- msm_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
}
static void vfe31_write_gamma_cfg(enum VFE31_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
@@ -1098,8 +1115,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1111,7 +1130,7 @@
vfe31_program_dmi_cfg(channel_sel);
CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
for (i = 0 ; i < VFE31_GAMMA_NUM_ENTRIES ; i++) {
- *tbl = msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *tbl = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *tbl);
tbl++;
}
@@ -1129,8 +1148,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1363,11 +1384,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_STATS_AF_START:
@@ -1382,11 +1404,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_STATS_AWB_START:
@@ -1401,12 +1424,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_STATS_IHIST_START:
@@ -1421,11 +1445,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -1441,7 +1466,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -1457,7 +1483,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -1466,7 +1493,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1482,19 +1509,22 @@
new_val = *cmdp_local;
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
&new_val, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_CHROMA_SUP_UPDATE:
@@ -1511,7 +1541,7 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF,
cmdp_local, 4);
cmdp_local += 1;
@@ -1519,20 +1549,22 @@
/* Incrementing with 4 so as to point to the 2nd Register as
* the 2nd register has the mce_enable bit
*/
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 4);
old_val &= ~MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= ~MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
&new_val, 4);
break;
@@ -1548,23 +1580,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, 16);
cmdp_local += 4;
vfe31_program_dmi_cfg(ROLLOFF_RAM);
/* for loop for extrcting init table. */
for (i = 0; i < (V31_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local ,
+ msm_camera_io_w(*cmdp_local ,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
- msm_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe31_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0; i < (V31_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
@@ -1587,17 +1620,17 @@
vfe31_program_dmi_cfg(ROLLOFF_RAM);
CDBG("%s: Mesh Rolloff init Table\n", __func__);
for (i = 0; i < (V31_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
- *cmdp_local =
- msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
- msm_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe31_ctrl->vfebase + VFE_DMI_ADDR);
CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
for (i = 0; i < (V31_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
- *cmdp_local =
- msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
@@ -1623,7 +1656,8 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
cmdp_local += 1;
@@ -1645,7 +1679,7 @@
}
cmdp_local = cmdp + 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_LA_OFF);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + V31_LA_OFF);
if (old_val != 0x0)
vfe31_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
cmdp_local);
@@ -1667,14 +1701,14 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
+ if (msm_camera_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
vfe31_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
else
vfe31_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
for (i = 0 ; i < (VFE31_LA_TABLE_LENGTH / 2) ; i++) {
- *cmdp_local =
- msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- *cmdp_local |= (msm_io_r(vfe31_ctrl->vfebase +
+ *cmdp_local = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_DMI_DATA_LO)) << 16;
cmdp_local++;
}
@@ -1698,7 +1732,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
cmdp, V31_SCE_LEN);
break;
@@ -1734,12 +1768,13 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, V31_DEMOSAICV3_LEN);
break;
@@ -1763,12 +1798,13 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, V31_DEMOSAICV3_LEN);
break;
@@ -1793,16 +1829,18 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
break;
@@ -1826,15 +1864,17 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= BPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, V31_DEMOSAICV3_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_DBPC_CFG_OFF,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_DBPC_CFG_OFF,
cmdp_local, V31_DEMOSAICV3_DBPC_LEN);
break;
@@ -1850,7 +1890,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
@@ -1872,7 +1912,7 @@
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
cmdp += 1;
if (old_val != 0x0) {
vfe31_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp);
@@ -1900,7 +1940,7 @@
}
cmdp_local = cmdp;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
RGBLUT_RAM_CH0_BANK0;
for (i = 0; i < 3; i++) {
@@ -1916,42 +1956,42 @@
break;
case VFE_CMD_STATS_AWB_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_AE_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_AF_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_IHIST_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_RS_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_CS_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
@@ -1988,11 +2028,12 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -2021,7 +2062,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
cmdp_local = cmdp + V31_ASF_LEN/4;
break;
@@ -2036,7 +2078,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- *cmdp = msm_io_r(vfe31_ctrl->vfebase+V31_GET_HW_VERSION_OFF);
+ *cmdp = msm_camera_io_r(
+ vfe31_ctrl->vfebase+V31_GET_HW_VERSION_OFF);
if (copy_to_user((void __user *)(cmd->value), cmdp,
V31_GET_HW_VERSION_LEN)) {
rc = -EFAULT;
@@ -2054,7 +2097,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- msm_io_dump(vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
+ msm_camera_io_dump(
+ vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
vfe31_ctrl->vfebase, temp1);
memcpy_fromio((void *)cmdp, vfe31_ctrl->vfebase, temp1);
@@ -2078,7 +2122,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
vfe31_ctrl->frame_skip_cnt = ((uint32_t)
*cmdp & VFE_FRAME_SKIP_PERIOD_MASK) + 1;
@@ -2099,7 +2144,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -2186,22 +2232,24 @@
uint32_t *temp;
memset(out, 0, sizeof(struct vfe31_irq_status));
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_0);
- out->vfeIrqStatus0 = msm_io_r(temp);
+ out->vfeIrqStatus0 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_1);
- out->vfeIrqStatus1 = msm_io_r(temp);
+ out->vfeIrqStatus1 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
- out->camifStatus = msm_io_r(temp);
+ out->camifStatus = msm_camera_io_r(temp);
CDBG("camifStatus = 0x%x\n", out->camifStatus);
/* clear the pending interrupt of the same kind.*/
- msm_io_w(out->vfeIrqStatus0, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(out->vfeIrqStatus1, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(out->vfeIrqStatus0,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(out->vfeIrqStatus1,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
}
@@ -2212,33 +2260,33 @@
if (vfe31_ctrl->recording_state == VFE_STATE_START_REQUESTED) {
if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
vfe31_ctrl->recording_state = VFE_STATE_STARTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe31_ctrl->recording_state ==
VFE_STATE_STOP_REQUESTED) {
if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
CDBG("stop video triggered .\n");
@@ -2254,7 +2302,7 @@
/* request a reg update and send STOP_REC_ACK
* when we process the next reg update irq.
*/
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe31_ctrl->recording_state ==
VFE_STATE_STOPPED) {
@@ -2277,9 +2325,9 @@
pr_info("%s enabling liveshot output\n", __func__);
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
vfe31_ctrl->liveshot_state = VFE_STATE_STARTED;
}
@@ -2289,17 +2337,17 @@
vfe31_ctrl->vfe_capture_count--;
if (!vfe31_ctrl->vfe_capture_count)
vfe31_ctrl->liveshot_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe31_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED) {
CDBG("%s: disabling liveshot output\n", __func__);
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
vfe31_ctrl->liveshot_state = VFE_STATE_STOPPED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
}
} else if (vfe31_ctrl->liveshot_state == VFE_STATE_STOPPED) {
@@ -2321,23 +2369,23 @@
/* stop the bus output:write master enable = 0*/
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch1]);
}
- msm_io_w_mb
+ msm_camera_io_w_mb
(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
vfe31_ctrl->snapshot_frame_cnt = -1;
@@ -2347,39 +2395,46 @@
} /*if frame is not being dropped*/
vfe31_ctrl->snapshot_frame_cnt++;
/* then do reg_update. */
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
static void vfe31_set_default_reg_values(void)
{
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
/* What value should we program CGC_OVERRIDE to? */
- msm_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- msm_io_w(0xFFFFFFFF, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0xFFFFFFFF,
+ vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
- msm_io_w(0x3980007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
- msm_io_w(0x3A00007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
- msm_io_w(0x3A8000F, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
- msm_io_w(0x3B80007, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
- msm_io_w(0x3C0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
- msm_io_w(0x3E0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ msm_camera_io_w(0x3980007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ msm_camera_io_w(0x3A00007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ msm_camera_io_w(0x3A8000F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ msm_camera_io_w(0x3B80007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ msm_camera_io_w(0x3C0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ msm_camera_io_w(0x3E0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
static void vfe31_process_reset_irq(void)
@@ -2399,7 +2454,7 @@
vfe31_set_default_reg_values();
/* reload all write masters. (frame & line)*/
- msm_io_w(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
+ msm_camera_io_w(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
vfe31_send_isp_msg(vfe31_ctrl, MSG_ID_RESET_ACK);
}
}
@@ -2417,7 +2472,7 @@
if (vfe31_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
@@ -2446,7 +2501,8 @@
if (errStatus & VFE31_IMASK_CAMIF_ERROR) {
pr_err("vfe31_irq: camif errors\n");
- reg_value = msm_io_r(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
+ reg_value = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
pr_err("camifStatus = 0x%x\n", reg_value);
vfe31_send_isp_msg(vfe31_ctrl, MSG_ID_CAMIF_ERROR);
}
@@ -2514,21 +2570,21 @@
if (errStatus & VFE31_IMASK_AXI_ERROR) {
pr_err("vfe31_irq: axi error\n");
/* read status too when overflow happens.*/
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
pr_debug("VFE_BUS_PING_PONG_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_OPERATION_STATUS);
pr_debug("VFE_BUS_OPERATION_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_AXI_STATUS);
pr_debug("VFE_AXI_STATUS = 0x%x\n", read_val);
}
@@ -2576,7 +2632,7 @@
(vfe31_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe31_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Channel 0*/
@@ -2652,7 +2708,7 @@
(vfe31_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe31_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Y channel */
@@ -2709,7 +2765,7 @@
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_io_r(vfe31_ctrl->vfebase +
+ ((msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
@@ -2718,8 +2774,8 @@
((uint32_t)(vfe31_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
- returnAddr = msm_io_r((uint32_t *)pingpongAddr);
- msm_io_w(newAddr, (uint32_t *)pingpongAddr);
+ returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
+ msm_camera_io_w(newAddr, (uint32_t *)pingpongAddr);
return returnAddr;
}
@@ -2807,7 +2863,7 @@
msgStats.rs.buff = vfe31_ctrl->rsStatsControl.bufToRender;
msgStats.cs.buff = vfe31_ctrl->csStatsControl.bufToRender;
- temp = msm_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msgStats.awb_ymin = (0xFF00 & temp) >> 8;
v4l2_subdev_notify(&vfe31_ctrl->subdev,
@@ -3118,7 +3174,7 @@
if ((vfe31_ctrl->outpath.out0.capture_cnt == 0)
&& (vfe31_ctrl->outpath.out1.
capture_cnt == 0)) {
- msm_io_w_mb(
+ msm_camera_io_w_mb(
CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
@@ -3593,20 +3649,20 @@
msm_vfe_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
usleep_range(10000, 15000);
- reg = (msm_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
reg |= 0x3;
- msm_io_w(reg, vfe31_ctrl->camifbase);
+ msm_camera_io_w(reg, vfe31_ctrl->camifbase);
usleep_range(10000, 15000);
- reg = (msm_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
reg |= 0x10;
- msm_io_w(reg, vfe31_ctrl->camifbase);
+ msm_camera_io_w(reg, vfe31_ctrl->camifbase);
usleep_range(10000, 15000);
- reg = (msm_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
/* Need to be uninverted*/
reg &= 0x03;
- msm_io_w(reg, vfe31_ctrl->camifbase);
+ msm_camera_io_w(reg, vfe31_ctrl->camifbase);
usleep_range(10000, 15000);
}
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 84b9b28..b8344fb 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -28,27 +28,20 @@
atomic_t irq_cnt;
-#define CHECKED_COPY_FROM_USER(in) { \
- if (copy_from_user((in), (void __user *)cmd->value, \
- cmd->length)) { \
- rc = -EFAULT; \
- break; \
- } \
-}
-
#define VFE32_AXI_OFFSET 0x0050
#define vfe32_get_ch_ping_addr(chn) \
- (msm_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe32_get_ch_pong_addr(chn) \
- (msm_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe32_get_ch_addr(ping_pong, chn) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe32_get_ch_pong_addr(chn) : vfe32_get_ch_ping_addr(chn))
#define vfe32_put_ch_ping_addr(chn, addr) \
- (msm_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe32_put_ch_pong_addr(chn, addr) \
- (msm_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_w((addr), \
+ vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe32_put_ch_addr(ping_pong, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe32_put_ch_pong_addr((chn), (addr)) : \
@@ -377,50 +370,50 @@
spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe32_ctrl->vfebase + VFE_IRQ_CMD);
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
- msm_io_w(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* axi halt command. */
- msm_io_w(AXI_HALT,
+ msm_camera_io_w(AXI_HALT,
vfe32_ctrl->vfebase + VFE_AXI_CMD);
wmb();
while (axiBusyFlag) {
- if (msm_io_r(vfe32_ctrl->vfebase + VFE_AXI_STATUS) & 0x1)
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + VFE_AXI_STATUS) & 0x1)
axiBusyFlag = false;
}
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(AXI_HALT_CLEAR,
+ msm_camera_io_w_mb(AXI_HALT_CLEAR,
vfe32_ctrl->vfebase + VFE_AXI_CMD);
/* after axi halt, then ok to apply global reset. */
/* enable reset_ack and async timer interrupt only while
stopping the pipeline.*/
- msm_io_w(0xf0000000,
+ msm_camera_io_w(0xf0000000,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_STOP_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
vfe32_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -490,9 +483,9 @@
pr_err("%s Invalid AXI mode %d ", __func__, mode);
return -EINVAL;
}
- msm_io_w(*ao, vfe32_ctrl->vfebase +
+ msm_camera_io_w(*ao, vfe32_ctrl->vfebase +
VFE_BUS_IO_FORMAT_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
vfe32_cmd[VFE_CMD_AXI_OUT_CFG].offset, axi_cfg,
vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length - V32_AXI_CH_INF_LEN
- V32_AXI_BUS_FMT_LEN);
@@ -558,22 +551,24 @@
vfe32_reset_internal_variables();
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
@@ -583,7 +578,7 @@
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_RESET_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
vfe32_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -595,20 +590,20 @@
vfe32_ctrl->stats_comp = *(++p);
vfe32_ctrl->hfr_mode = *(++p);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CFG);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_PIXEL_IF_CFG);
- if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_PIXEL_IF_CFG);
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
VFE33_HW_NUMBER) {
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI0_CFG);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI1_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI0_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI1_CFG);
} else {
++p;
++p;
}
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CHROMA_UP);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_STATS_CFG);
return 0;
}
@@ -618,9 +613,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe32_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
@@ -631,9 +628,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe32_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -645,9 +644,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe32_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -659,9 +660,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe32_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -673,9 +676,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe32_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -687,9 +692,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe32_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -706,14 +713,14 @@
else
irq_mask |= 0x000FE000;
- msm_io_w(irq_mask, vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(irq_mask, vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
atomic_set(&vfe32_ctrl->vstate, 1);
@@ -725,7 +732,7 @@
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_VIDEO);
vfe32_ctrl->recording_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
@@ -733,7 +740,7 @@
{
struct msm_sync *sync = vfe_syncdata;
vfe32_ctrl->recording_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
return 0;
@@ -749,7 +756,7 @@
vfe32_ctrl->vfe_capture_count = vfe32_ctrl->outpath.out0.capture_cnt;
vfe32_ctrl->liveshot_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
}
static int vfe32_zsl(void)
@@ -758,7 +765,7 @@
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
vfe32_ctrl->operation_mode, vfe32_ctrl->outpath.output_mode);
@@ -784,42 +791,42 @@
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch2]);
}
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
vfe32_start_common();
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_ZSL);
- msm_io_w(1, vfe32_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe32_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x188);
return 0;
}
static int vfe32_capture_raw(uint32_t num_frames_capture)
@@ -831,15 +838,15 @@
vfe32_ctrl->vfe_capture_count = num_frames_capture;
irq_comp_mask =
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << (vfe32_ctrl->outpath.out0.ch0));
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
}
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe32_start_common();
@@ -865,7 +872,8 @@
}
vfe32_ctrl->vfe_capture_count = num_frames_capture;
- irq_comp_mask = msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ irq_comp_mask = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
@@ -883,31 +891,31 @@
}
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
}
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
}
vfe32_ctrl->vfe_capture_count = num_frames_capture;
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe32_start_common();
/* for debug */
- msm_io_w(1, vfe32_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe32_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x188);
return 0;
}
@@ -917,7 +925,7 @@
struct msm_sync *sync = vfe_syncdata;
irq_comp_mask =
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
@@ -937,41 +945,41 @@
0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8) |
0x1 << (vfe32_ctrl->outpath.out1.ch2 + 8));
}
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
switch (vfe32_ctrl->operation_mode) {
case VFE_OUTPUTS_PREVIEW:
case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
}
break;
default:
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch2]);
}
break;
@@ -988,38 +996,39 @@
unsigned long flags;
uint32_t value = 0;
if (vfe32_ctrl->update_linear) {
- if (!msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
- msm_io_w(1,
+ if (!msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ msm_camera_io_w(1,
vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
else
- msm_io_w(0,
+ msm_camera_io_w(0,
vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
vfe32_ctrl->update_linear = false;
}
if (vfe32_ctrl->update_rolloff) {
- value = msm_io_r(vfe32_ctrl->vfebase +
+ value = msm_camera_io_r(vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1);
value ^= V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
- msm_io_w(value, vfe32_ctrl->vfebase +
+ msm_camera_io_w(value, vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1);
vfe32_ctrl->update_rolloff = false;
}
if (vfe32_ctrl->update_la) {
- if (!msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
- msm_io_w(1,
+ if (!msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ msm_camera_io_w(1,
vfe32_ctrl->vfebase + V32_LA_OFF);
else
- msm_io_w(0,
+ msm_camera_io_w(0,
vfe32_ctrl->vfebase + V32_LA_OFF);
vfe32_ctrl->update_la = false;
}
if (vfe32_ctrl->update_gamma) {
- value = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ value = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
value ^= V32_GAMMA_LUT_BANK_SEL_MASK;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_RGB_G_OFF);
vfe32_ctrl->update_gamma = false;
}
@@ -1028,7 +1037,7 @@
spin_unlock_irqrestore(&vfe32_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
@@ -1044,7 +1053,7 @@
value = 0x40000;
/* Timer Stop */
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
}
static void vfe32_sync_timer_start(const uint32_t *tbl)
@@ -1069,14 +1078,14 @@
}
/* Timer Start */
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
4 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
8 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
@@ -1084,14 +1093,15 @@
val = 10000000 / val;
val = value * 10000 / val;
CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
- msm_io_w(val, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(val, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
12 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_POLARITY_OFF);
+ msm_camera_io_w(value,
+ vfe32_ctrl->vfebase + V32_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_TIMER_SELECT_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_TIMER_SELECT_OFF);
}
static void vfe32_program_dmi_cfg(enum VFE32_DMI_RAM_SEL bankSel)
@@ -1101,9 +1111,9 @@
value += (uint32_t)bankSel;
CDBG("%s: banksel = %d\n", __func__, bankSel);
- msm_io_w(value, vfe32_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_io_w(0, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
}
static void vfe32_write_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
@@ -1115,8 +1125,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1128,7 +1140,7 @@
vfe32_program_dmi_cfg(channel_sel);
CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
for (i = 0 ; i < VFE32_GAMMA_NUM_ENTRIES ; i++) {
- *tbl = msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *tbl = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *tbl);
tbl++;
}
@@ -1146,8 +1158,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1225,7 +1239,7 @@
vfe32_program_dmi_cfg(channel_sel);
/* for loop for configuring LUT. */
for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
- msm_io_w(*tbl, vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w(*tbl, vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
tbl++;
}
CDBG("done writing to linearization table\n");
@@ -1399,12 +1413,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_STATS_AF_START: {
@@ -1419,12 +1434,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_STATS_AWB_START: {
@@ -1439,12 +1455,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1460,12 +1477,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1482,8 +1500,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1499,8 +1518,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1509,7 +1529,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1525,20 +1545,23 @@
new_val = *cmdp_local;
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
- &new_val, 4);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
+ &new_val, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp_local, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp_local, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_CHROMA_SUP_UPDATE:
@@ -1555,7 +1578,7 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF,
cmdp_local, 4);
cmdp_local += 1;
@@ -1563,20 +1586,22 @@
/* Incrementing with 4 so as to point to the 2nd Register as
* the 2nd register has the mce_enable bit
*/
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 4);
old_val &= ~MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= ~MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
&new_val, 4);
}
break;
@@ -1596,23 +1621,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp_local, 16);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp_local, 16);
cmdp_local += 4;
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
/* for loop for extrcting init table. */
for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local ,
+ msm_camera_io_w(*cmdp_local ,
vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
- msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe32_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
@@ -1637,16 +1663,18 @@
CDBG("%s: Mesh Rolloff init Table\n", __func__);
for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
*cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
- msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe32_ctrl->vfebase + VFE_DMI_ADDR);
CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
*cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
@@ -1672,7 +1700,8 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
cmdp_local += 1;
@@ -1694,7 +1723,7 @@
}
cmdp_local = cmdp + 1;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF);
if (old_val != 0x0)
vfe32_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
cmdp_local);
@@ -1717,14 +1746,15 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
else
vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH / 2) ; i++) {
*cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- *cmdp_local |= (msm_io_r(vfe32_ctrl->vfebase +
+ msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_DMI_DATA_LO)) << 16;
cmdp_local++;
}
@@ -1748,7 +1778,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_SCE_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_SCE_OFF,
cmdp, V32_SCE_LEN);
}
break;
@@ -1778,10 +1808,12 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1,
cmdp_local, V32_LINEARIZATION_LEN1);
cmdp_local += 4;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
cmdp_local, V32_LINEARIZATION_LEN2);
cmdp_local = cmdp + 17;
@@ -1801,15 +1833,17 @@
}
cmdp_local = cmdp;
cmdp_local++;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1 + 4,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1 + 4,
cmdp_local, (V32_LINEARIZATION_LEN1 - 4));
cmdp_local += 3;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
cmdp_local, V32_LINEARIZATION_LEN2);
cmdp_local = cmdp + 17;
/*extracting the bank select*/
- old_val =
- msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
if (old_val != 0x0)
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
@@ -1830,14 +1864,15 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ if (msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1);
else
vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0);
CDBG("%s: Linearization Table\n", __func__);
for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
- *cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
@@ -1868,15 +1903,16 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
cmdp_local, V32_DEMOSAICV3_1_LEN);
break;
@@ -1900,22 +1936,23 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
/* As the address space is not contiguous increment by 2
* before copying to next address space */
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
/* As the address space is not contiguous increment by 2
* before copying to next address space */
cmdp_local += 2;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
break;
@@ -1939,16 +1976,18 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1969,15 +2008,17 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DBCC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
break;
@@ -1997,28 +2038,29 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DBPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF0,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF1,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF2,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
break;
@@ -2035,7 +2077,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_RGB_G_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
@@ -2058,7 +2100,7 @@
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
cmdp += 1;
if (old_val != 0x0) {
vfe32_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp);
@@ -2087,7 +2129,7 @@
}
cmdp_local = cmdp;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
RGBLUT_RAM_CH0_BANK0;
for (i = 0; i < 3; i++) {
@@ -2103,47 +2145,47 @@
break;
case VFE_CMD_STATS_AWB_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_AE_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_AF_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_IHIST_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_RS_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_CS_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
@@ -2180,11 +2222,12 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -2214,10 +2257,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
cmdp_local = cmdp + V32_ASF_LEN/4;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_ASF_SPECIAL_EFX_CFG_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_ASF_SPECIAL_EFX_CFG_OFF,
cmdp_local, V32_ASF_SPECIAL_EFX_CFG_LEN);
break;
@@ -2238,20 +2283,22 @@
temp1 = *cmdp_local;
cmdp_local++;
- msm_io_memcpy(vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF1,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF1,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN1);
cmdp_local += 4;
- msm_io_memcpy(vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF2,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF2,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN2);
cmdp_local += 3;
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*(cmdp_local + 1),
+ msm_camera_io_w(*(cmdp_local + 1),
vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2259,9 +2306,9 @@
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2287,7 +2334,7 @@
temp1 = *cmdp_local;
cmdp_local += 8;
- temp2 = msm_io_r(vfe32_ctrl->vfebase +
+ temp2 = msm_camera_io_r(vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1)
& V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
@@ -2297,11 +2344,11 @@
else
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*(cmdp_local + 1),
+ msm_camera_io_w(*(cmdp_local + 1),
vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2313,9 +2360,9 @@
else
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2336,7 +2383,7 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1) &
V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
@@ -2353,10 +2400,10 @@
else if (!old_val && temp2)
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- *cmdp_local = msm_io_r(vfe32_ctrl->vfebase +
+ *cmdp_local = msm_camera_io_r(vfe32_ctrl->vfebase +
VFE33_DMI_DATA_LO);
*(cmdp_local + 1) =
- msm_io_r(vfe32_ctrl->vfebase +
+ msm_camera_io_r(vfe32_ctrl->vfebase +
VFE33_DMI_DATA_HI);
CDBG("%s: %08x%08x\n", __func__,
*(cmdp_local + 1), *cmdp_local);
@@ -2379,7 +2426,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
+ *cmdp = msm_camera_io_r(
+ vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
if (copy_to_user((void __user *)(cmd->value), cmdp,
V32_GET_HW_VERSION_LEN)) {
rc = -EFAULT;
@@ -2397,7 +2445,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
+ msm_camera_io_dump(
+ vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
vfe32_ctrl->vfebase, temp1);
memcpy_fromio((void *)cmdp, vfe32_ctrl->vfebase, temp1);
@@ -2416,8 +2465,16 @@
goto proc_general_done;
}
- CHECKED_COPY_FROM_USER(cmdp);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ if (copy_from_user((cmdp), (void __user *)cmd->value,
+ cmd->length)) {
+ rc = -EFAULT;
+ pr_err("%s copy from user failed for cmd %d",
+ __func__, cmd->id);
+ break;
+ }
+
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
vfe32_ctrl->frame_skip_cnt = ((uint32_t)
*cmdp & VFE_FRAME_SKIP_PERIOD_MASK) + 1;
@@ -2433,8 +2490,15 @@
goto proc_general_done;
}
- CHECKED_COPY_FROM_USER(cmdp);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ if (copy_from_user((cmdp), (void __user *)cmd->value,
+ cmd->length)) {
+ rc = -EFAULT;
+ pr_err("%s copy from user failed for cmd %d",
+ __func__, cmd->id);
+ goto proc_general_done;
+ }
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
break;
@@ -2521,22 +2585,24 @@
uint32_t *temp;
memset(out, 0, sizeof(struct vfe32_irq_status));
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_IRQ_STATUS_0);
- out->vfeIrqStatus0 = msm_io_r(temp);
+ out->vfeIrqStatus0 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_IRQ_STATUS_1);
- out->vfeIrqStatus1 = msm_io_r(temp);
+ out->vfeIrqStatus1 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
- out->camifStatus = msm_io_r(temp);
+ out->camifStatus = msm_camera_io_r(temp);
CDBG("camifStatus = 0x%x\n", out->camifStatus);
/* clear the pending interrupt of the same kind.*/
- msm_io_w(out->vfeIrqStatus0, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(out->vfeIrqStatus1, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(out->vfeIrqStatus0,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(out->vfeIrqStatus1,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
}
@@ -2547,33 +2613,33 @@
if (vfe32_ctrl->recording_state == VFE_STATE_START_REQUESTED) {
if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
vfe32_ctrl->recording_state = VFE_STATE_STARTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe32_ctrl->recording_state ==
VFE_STATE_STOP_REQUESTED) {
if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
CDBG("stop video triggered .\n");
@@ -2589,7 +2655,7 @@
/* request a reg update and send STOP_REC_ACK
* when we process the next reg update irq.
*/
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->recording_state ==
VFE_STATE_STOPPED) {
@@ -2612,9 +2678,9 @@
pr_info("%s enabling liveshot output\n", __func__);
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
vfe32_ctrl->liveshot_state = VFE_STATE_STARTED;
}
@@ -2624,17 +2690,17 @@
vfe32_ctrl->vfe_capture_count--;
if (!vfe32_ctrl->vfe_capture_count)
vfe32_ctrl->liveshot_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED) {
CDBG("%s: disabling liveshot output\n", __func__);
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
vfe32_ctrl->liveshot_state = VFE_STATE_STOPPED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
}
} else if (vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED) {
@@ -2656,23 +2722,23 @@
/* stop the bus output:write master enable = 0*/
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out0.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out0.ch1]);
}
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out1.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out1.ch1]);
}
- msm_io_w_mb
+ msm_camera_io_w_mb
(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
vfe32_ctrl->snapshot_frame_cnt = -1;
@@ -2682,39 +2748,46 @@
} /*if frame is not being dropped*/
vfe32_ctrl->snapshot_frame_cnt++;
/* then do reg_update. */
- msm_io_w(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
static void vfe32_set_default_reg_values(void)
{
- msm_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_1);
/* What value should we program CGC_OVERRIDE to? */
- msm_io_w(0xFFFFF, vfe32_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0xFFFFF, vfe32_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- msm_io_w(0xFFFFFFFF, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0xFFFFFFFF,
+ vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ msm_camera_io_w(0xFFFFFFFF,
vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ msm_camera_io_w(0xFFFFFFFF,
vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0xFFFFFFFF,
vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_io_w(0, vfe32_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_io_w(0xFFFFFF, vfe32_ctrl->vfebase + VFE_CLAMP_MAX);
+ msm_camera_io_w(0, vfe32_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF, vfe32_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
- msm_io_w(0x3980007, vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
- msm_io_w(0x3A00007, vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
- msm_io_w(0x3A8000F, vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
- msm_io_w(0x3B80007, vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
- msm_io_w(0x3C0001F, vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
- msm_io_w(0x3E0001F, vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ msm_camera_io_w(0x3980007,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ msm_camera_io_w(0x3A00007,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ msm_camera_io_w(0x3A8000F,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ msm_camera_io_w(0x3B80007,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ msm_camera_io_w(0x3C0001F,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ msm_camera_io_w(0x3E0001F,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
static void vfe32_process_reset_irq(void)
@@ -2734,7 +2807,7 @@
vfe32_set_default_reg_values();
/* reload all write masters. (frame & line)*/
- msm_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
+ msm_camera_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_RESET_ACK);
}
}
@@ -2752,7 +2825,7 @@
if (vfe32_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
@@ -2781,7 +2854,8 @@
if (errStatus & VFE32_IMASK_CAMIF_ERROR) {
pr_err("vfe32_irq: camif errors\n");
- reg_value = msm_io_r(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
+ reg_value = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
pr_err("camifStatus = 0x%x\n", reg_value);
vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_CAMIF_ERROR);
}
@@ -2806,8 +2880,8 @@
if (errStatus & VFE32_IMASK_VIOLATION) {
pr_err("vfe32_irq: violation interrupt\n");
- reg_value =
- msm_io_r(vfe32_ctrl->vfebase + VFE_VIOLATION_STATUS);
+ reg_value = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_VIOLATION_STATUS);
pr_err("%s: violationStatus = 0x%x\n", __func__, reg_value);
}
@@ -2901,7 +2975,7 @@
(vfe32_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe32_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Channel 0*/
@@ -2977,7 +3051,7 @@
(vfe32_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe32_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Y channel */
@@ -3033,7 +3107,7 @@
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_io_r(vfe32_ctrl->vfebase +
+ ((msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
@@ -3042,8 +3116,8 @@
((uint32_t)(vfe32_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
- returnAddr = msm_io_r((uint32_t *)pingpongAddr);
- msm_io_w(newAddr, (uint32_t *)pingpongAddr);
+ returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
+ msm_camera_io_w(newAddr, (uint32_t *)pingpongAddr);
return returnAddr;
}
@@ -3131,7 +3205,7 @@
msgStats.rs.buff = vfe32_ctrl->rsStatsControl.bufToRender;
msgStats.cs.buff = vfe32_ctrl->csStatsControl.bufToRender;
- temp = msm_io_r(vfe32_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msgStats.awb_ymin = (0xFF00 & temp) >> 8;
v4l2_subdev_notify(&vfe32_ctrl->subdev,
@@ -3443,7 +3517,7 @@
if ((vfe32_ctrl->outpath.out0.capture_cnt == 0)
&& (vfe32_ctrl->outpath.out1.
capture_cnt == 0)) {
- msm_io_w_mb(
+ msm_camera_io_w_mb(
CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe32_ctrl->vfebase +
VFE_CAMIF_COMMAND);
@@ -3934,7 +4008,7 @@
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
- if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
VFE32_HW_NUMBER)
vfe32_ctrl->register_total = VFE32_REGISTER_TOTAL;
else
@@ -3948,6 +4022,7 @@
vfe32_ctrl->fs_vfe = NULL;
vfe_fs_failed:
iounmap(vfe32_ctrl->vfebase);
+ vfe32_ctrl->vfebase = NULL;
vfe_remap_failed:
disable_irq(vfe32_ctrl->vfeirq->start);
return rc;
@@ -3967,6 +4042,7 @@
vfe32_ctrl->fs_vfe = NULL;
}
iounmap(vfe32_ctrl->vfebase);
+ vfe32_ctrl->vfebase = NULL;
if (atomic_read(&irq_cnt))
pr_warning("%s, Warning IRQ Count not ZERO\n", __func__);
diff --git a/drivers/media/video/msm/msm_vpe.c b/drivers/media/video/msm/msm_vpe.c
index 5919553..8567fb3 100644
--- a/drivers/media/video/msm/msm_vpe.c
+++ b/drivers/media/video/msm/msm_vpe.c
@@ -48,14 +48,14 @@
static int vpe_start(void)
{
/* enable the frame irq, bit 0 = Display list 0 ROI done */
- msm_io_w_mb(1, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
- msm_io_dump(vpe_ctrl->vpebase, 0x120);
- msm_io_dump(vpe_ctrl->vpebase + 0x10000, 0x250);
- msm_io_dump(vpe_ctrl->vpebase + 0x30000, 0x20);
- msm_io_dump(vpe_ctrl->vpebase + 0x50000, 0x30);
- msm_io_dump(vpe_ctrl->vpebase + 0x50400, 0x10);
+ msm_camera_io_w_mb(1, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_dump(vpe_ctrl->vpebase, 0x120);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x10000, 0x250);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x30000, 0x20);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x50000, 0x30);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x50400, 0x10);
/* this triggers the operation. */
- msm_io_w(1, vpe_ctrl->vpebase + VPE_DL0_START_OFFSET);
+ msm_camera_io_w(1, vpe_ctrl->vpebase + VPE_DL0_START_OFFSET);
wmb();
return 0;
}
@@ -69,15 +69,15 @@
static void vpe_config_axi_default(void)
{
- msm_io_w(0x25, vpe_ctrl->vpebase + VPE_AXI_ARB_2_OFFSET);
+ msm_camera_io_w(0x25, vpe_ctrl->vpebase + VPE_AXI_ARB_2_OFFSET);
CDBG("%s: yaddr %ld cbcraddr %ld", __func__,
vpe_ctrl->out_y_addr, vpe_ctrl->out_cbcr_addr);
if (!vpe_ctrl->out_y_addr || !vpe_ctrl->out_cbcr_addr)
return;
- msm_io_w(vpe_ctrl->out_y_addr,
+ msm_camera_io_w(vpe_ctrl->out_y_addr,
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
- msm_io_w(vpe_ctrl->out_cbcr_addr,
+ msm_camera_io_w(vpe_ctrl->out_cbcr_addr,
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
}
@@ -88,32 +88,33 @@
uint32_t rc = 0;
vpe_reset_state_variables();
- vpe_version = msm_io_r(vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
+ vpe_version = msm_camera_io_r(
+ vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
- msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
- msm_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
+ msm_camera_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
- msm_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
+ msm_camera_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
rc =
- msm_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
+ msm_camera_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
- msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
+ msm_camera_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_ctrl->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
- msm_io_w(VPE_CGC_ENABLE_VALUE,
+ msm_camera_io_w(VPE_CGC_ENABLE_VALUE,
vpe_ctrl->vpebase + VPE_CGC_EN_OFFSET);
- msm_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
+ msm_camera_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
+ msm_camera_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
+ msm_camera_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_ctrl->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return rc;
@@ -124,7 +125,7 @@
uint32_t rot_flag, rc = 0;
struct msm_pp_crop *pcrop = (struct msm_pp_crop *)pinfo;
- rot_flag = msm_io_r(vpe_ctrl->vpebase +
+ rot_flag = msm_camera_io_r(vpe_ctrl->vpebase +
VPE_OP_MODE_OFFSET) & 0xE00;
if (pinfo != NULL) {
CDBG("%s: Crop info in2_w = %d, in2_h = %d "
@@ -144,36 +145,40 @@
uint32_t i, offset;
offset = *p;
for (i = offset; i < (VPE_SCALE_COEFF_NUM + offset); i++) {
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SCALE_COEFF_LSBn(i));
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SCALE_COEFF_MSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_SCALE_COEFF_LSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_SCALE_COEFF_MSBn(i));
}
}
void vpe_input_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_ctrl->vpebase + VPE_SRC_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(*p, vpe_ctrl->vpebase + VPE_SRC_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_XY_OFFSET);
}
void vpe_output_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_ctrl->vpebase + VPE_OUT_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_XY_OFFSET);
+ msm_camera_io_w(*p, vpe_ctrl->vpebase + VPE_OUT_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_XY_OFFSET);
}
static int vpe_operation_config(uint32_t *p)
{
uint32_t w, h, temp;
- msm_io_w(*p, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(*p, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
- temp = msm_io_r(vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
+ temp = msm_camera_io_r(vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
w = temp & 0xFFF;
h = (temp & 0xFFF0000) >> 16;
if (*p++ & 0xE00) {
@@ -215,8 +220,8 @@
/* assumption is both direction need zoom. this can be
improved. */
temp =
- msm_io_r(vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
- msm_io_w(temp, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_r(vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
+ msm_camera_io_w(temp, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
src_ROI_width = pcrop->src_w;
src_ROI_height = pcrop->src_h;
@@ -228,7 +233,7 @@
out_ROI_height);
src_roi = (src_ROI_height << 16) + src_ROI_width;
- msm_io_w(src_roi, vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(src_roi, vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
src_x = pcrop->src_x;
src_y = pcrop->src_y;
@@ -236,7 +241,7 @@
CDBG("src_x = %d, src_y=%d.\n", src_x, src_y);
src_xy = src_y*(1<<16) + src_x;
- msm_io_w(src_xy, vpe_ctrl->vpebase +
+ msm_camera_io_w(src_xy, vpe_ctrl->vpebase +
VPE_SRC_XY_OFFSET);
CDBG("src_xy = %d, src_roi=%d.\n", src_xy, src_roi);
@@ -376,15 +381,15 @@
CDBG("phase init x = %d, init y = %d.\n",
phase_init_x, phase_init_y);
- msm_io_w(phase_step_x, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_step_x, vpe_ctrl->vpebase +
VPE_SCALE_PHASEX_STEP_OFFSET);
- msm_io_w(phase_step_y, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_step_y, vpe_ctrl->vpebase +
VPE_SCALE_PHASEY_STEP_OFFSET);
- msm_io_w(phase_init_x, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_init_x, vpe_ctrl->vpebase +
VPE_SCALE_PHASEX_INIT_OFFSET);
- msm_io_w(phase_init_y, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_init_y, vpe_ctrl->vpebase +
VPE_SCALE_PHASEY_INIT_OFFSET);
return 1;
@@ -406,16 +411,16 @@
unsigned long flags;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
- msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_SRCP0_ADDR_OFFSET);
- msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_SRCP1_ADDR_OFFSET);
- msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
- msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
vpe_ctrl->state = VPE_STATE_ACTIVE;
@@ -457,11 +462,11 @@
static irqreturn_t vpe_parse_irq(int irq_num, void *data)
{
- vpe_ctrl->irq_status = msm_io_r_mb(vpe_ctrl->vpebase +
+ vpe_ctrl->irq_status = msm_camera_io_r_mb(vpe_ctrl->vpebase +
VPE_INTR_STATUS_OFFSET);
- msm_io_w_mb(vpe_ctrl->irq_status, vpe_ctrl->vpebase +
+ msm_camera_io_w_mb(vpe_ctrl->irq_status, vpe_ctrl->vpebase +
VPE_INTR_CLEAR_OFFSET);
- msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
CDBG("%s: vpe_parse_irq =0x%x.\n", __func__, vpe_ctrl->irq_status);
tasklet_schedule(&vpe_tasklet);
return IRQ_HANDLED;
diff --git a/drivers/media/video/msm/msm_vpe1.c b/drivers/media/video/msm/msm_vpe1.c
index 5f128e1..984aea5 100644
--- a/drivers/media/video/msm/msm_vpe1.c
+++ b/drivers/media/video/msm/msm_vpe1.c
@@ -97,10 +97,10 @@
static int vpe_start(void)
{
/* enable the frame irq, bit 0 = Display list 0 ROI done */
- msm_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
- msm_io_dump(vpe_device->vpebase + 0x10000, 0x250);
+ msm_camera_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_dump(vpe_device->vpebase + 0x10000, 0x250);
/* this triggers the operation. */
- msm_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET);
+ msm_camera_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET);
return 0;
}
@@ -117,7 +117,7 @@
static void vpe_config_axi_default(void)
{
- msm_io_w(0x25, vpe_device->vpebase + VPE_AXI_ARB_2_OFFSET);
+ msm_camera_io_w(0x25, vpe_device->vpebase + VPE_AXI_ARB_2_OFFSET);
CDBG("%s: yaddr %ld cbcraddr %ld", __func__,
vpe_ctrl->out_y_addr, vpe_ctrl->out_cbcr_addr);
@@ -125,10 +125,10 @@
if (!vpe_ctrl->out_y_addr || !vpe_ctrl->out_cbcr_addr)
return;
- msm_io_w(vpe_ctrl->out_y_addr,
+ msm_camera_io_w(vpe_ctrl->out_y_addr,
vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
- msm_io_w(vpe_ctrl->out_cbcr_addr,
+ msm_camera_io_w(vpe_ctrl->out_cbcr_addr,
vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
}
@@ -139,39 +139,40 @@
uint32_t rc;
vpe_reset_state_variables();
- vpe_version = msm_io_r(vpe_device->vpebase + VPE_HW_VERSION_OFFSET);
+ vpe_version = msm_camera_io_r(
+ vpe_device->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
- msm_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
- msm_io_w(0x1fffff, vpe_device->vpebase + VPE_INTR_CLEAR_OFFSET);
+ msm_camera_io_w(0x1fffff, vpe_device->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
- msm_io_w(0x10, vpe_device->vpebase + VPE_SW_RESET_OFFSET);
+ msm_camera_io_w(0x10, vpe_device->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
- rc =
- msm_io_r(vpe_device->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
+ rc = msm_camera_io_r(vpe_device->vpebase + VPE_SW_RESET_OFFSET)
+ & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
- msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
+ msm_camera_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_device->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
- msm_io_w(VPE_CGC_ENABLE_VALUE,
+ msm_camera_io_w(VPE_CGC_ENABLE_VALUE,
vpe_device->vpebase + VPE_CGC_EN_OFFSET);
- msm_io_w(1, vpe_device->vpebase + VPE_CMD_MODE_OFFSET);
+ msm_camera_io_w(1, vpe_device->vpebase + VPE_CMD_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
+ msm_camera_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_device->vpebase + VPE_OP_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
+ msm_camera_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_device->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
@@ -183,7 +184,7 @@
uint32_t rot_flag, rc = 0;
struct video_crop_t *pcrop = (struct video_crop_t *)pinfo;
- rot_flag = msm_io_r(vpe_device->vpebase +
+ rot_flag = msm_camera_io_r(vpe_device->vpebase +
VPE_OP_MODE_OFFSET) & 0xE00;
if (pinfo != NULL) {
CDBG("Crop info in2_w = %d, in2_h = %d "
@@ -203,38 +204,51 @@
uint32_t i, offset;
offset = *p;
for (i = offset; i < (VPE_SCALE_COEFF_NUM + offset); i++) {
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SCALE_COEFF_LSBn(i));
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SCALE_COEFF_MSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SCALE_COEFF_LSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SCALE_COEFF_MSBn(i));
}
}
void vpe_input_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_device->vpebase + VPE_SRC_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(*p,
+ vpe_device->vpebase + VPE_SRC_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
vpe_ctrl->in_h_w = *p;
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_XY_OFFSET);
}
void vpe_output_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_device->vpebase + VPE_OUT_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_XY_OFFSET);
+ msm_camera_io_w(*p,
+ vpe_device->vpebase + VPE_OUT_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_XY_OFFSET);
vpe_ctrl->pcbcr_dis_offset = *(++p);
}
static int vpe_operation_config(uint32_t *p)
{
uint32_t outw, outh, temp;
- msm_io_w(*p, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(*p, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
- temp = msm_io_r(vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
outw = temp & 0xFFF;
outh = (temp & 0xFFF0000) >> 16;
@@ -278,15 +292,15 @@
(pcrop->in2_h >= pcrop->out2_h)) {
CDBG(" =======VPE no zoom needed.\n");
- temp = msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
& 0xfffffffc;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
- msm_io_w(0, vpe_device->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(0, vpe_device->vpebase + VPE_SRC_XY_OFFSET);
- CDBG("vpe_ctrl->in_h_w = %d \n", vpe_ctrl->in_h_w);
- msm_io_w(vpe_ctrl->in_h_w , vpe_device->vpebase +
+ CDBG("vpe_ctrl->in_h_w = %d\n", vpe_ctrl->in_h_w);
+ msm_camera_io_w(vpe_ctrl->in_h_w , vpe_device->vpebase +
VPE_SRC_SIZE_OFFSET);
return rc;
@@ -297,8 +311,8 @@
/* assumption is both direction need zoom. this can be
improved. */
temp =
- msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
src_ROI_width = pcrop->in2_w;
src_ROI_height = pcrop->in2_h;
@@ -310,7 +324,7 @@
out_ROI_height);
src_roi = (src_ROI_height << 16) + src_ROI_width;
- msm_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
src_x = (out_ROI_width - src_ROI_width)/2;
src_y = (out_ROI_height - src_ROI_height)/2;
@@ -318,7 +332,7 @@
CDBG("src_x = %d, src_y=%d.\n", src_x, src_y);
src_xy = src_y*(1<<16) + src_x;
- msm_io_w(src_xy, vpe_device->vpebase +
+ msm_camera_io_w(src_xy, vpe_device->vpebase +
VPE_SRC_XY_OFFSET);
CDBG("src_xy = %d, src_roi=%d.\n", src_xy, src_roi);
@@ -458,15 +472,15 @@
CDBG("phase init x = %d, init y = %d.\n",
phase_init_x, phase_init_y);
- msm_io_w(phase_step_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_STEP_OFFSET);
- msm_io_w(phase_step_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_STEP_OFFSET);
- msm_io_w(phase_init_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_INIT_OFFSET);
- msm_io_w(phase_init_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_INIT_OFFSET);
return 1;
@@ -502,21 +516,22 @@
if ((pcrop->in2_w >= pcrop->out2_w) &&
(pcrop->in2_h >= pcrop->out2_h)) {
- CDBG(" =======VPE no zoom needed, DIS is still enabled. \n");
+ CDBG(" =======VPE no zoom needed, DIS is still enabled.\n");
- temp = msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
& 0xfffffffc;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
/* no zoom, use dis offset directly. */
src_xy = dis_offset->dis_offset_y * (1<<16) +
dis_offset->dis_offset_x;
- msm_io_w(src_xy, vpe_device->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(src_xy,
+ vpe_device->vpebase + VPE_SRC_XY_OFFSET);
- CDBG("vpe_ctrl->in_h_w = 0x%x \n", vpe_ctrl->in_h_w);
- msm_io_w(vpe_ctrl->in_h_w, vpe_device->vpebase +
- VPE_SRC_SIZE_OFFSET);
+ CDBG("vpe_ctrl->in_h_w = 0x%x\n", vpe_ctrl->in_h_w);
+ msm_camera_io_w(vpe_ctrl->in_h_w,
+ vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
return rc;
}
/* If fall through then scaler is needed.*/
@@ -524,9 +539,9 @@
CDBG("========VPE zoom needed + DIS enabled.\n");
/* assumption is both direction need zoom. this can be
improved. */
- temp = msm_io_r(vpe_device->vpebase +
+ temp = msm_camera_io_r(vpe_device->vpebase +
VPE_OP_MODE_OFFSET) | 0x3;
- msm_io_w(temp, vpe_device->vpebase +
+ msm_camera_io_w(temp, vpe_device->vpebase +
VPE_OP_MODE_OFFSET);
zoom_dis_x = dis_offset->dis_offset_x *
pcrop->in2_w / pcrop->out2_w;
@@ -554,12 +569,12 @@
src_roi = (src_ROI_height << 16) + src_ROI_width;
- msm_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
CDBG("src_x = %d, src_y=%d.\n", src_x, src_y);
src_xy = src_y*(1<<16) + src_x;
- msm_io_w(src_xy, vpe_device->vpebase +
+ msm_camera_io_w(src_xy, vpe_device->vpebase +
VPE_SRC_XY_OFFSET);
CDBG("src_xy = 0x%x, src_roi=0x%x.\n", src_xy, src_roi);
@@ -694,16 +709,16 @@
CDBG("phase init x = %d, init y = %d.\n",
phase_init_x, phase_init_y);
- msm_io_w(phase_step_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_STEP_OFFSET);
- msm_io_w(phase_step_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_STEP_OFFSET);
- msm_io_w(phase_init_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_INIT_OFFSET);
- msm_io_w(phase_init_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_INIT_OFFSET);
return 1;
@@ -716,8 +731,10 @@
CDBG("vpe input, p0_phy_add = 0x%x, p1_phy_add = 0x%x\n",
p0_phy_add, p1_phy_add);
- msm_io_w(p0_phy_add, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
- msm_io_w(p1_phy_add, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
+ msm_camera_io_w(p0_phy_add,
+ vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
+ msm_camera_io_w(p1_phy_add,
+ vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == VPE_STATE_ACTIVE)
CDBG(" =====VPE is busy!!! Wrong!========\n");
@@ -726,25 +743,27 @@
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
- vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->pcbcr_before_dis =
+ msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
- temp_pyaddr = msm_io_r(vpe_device->vpebase +
+ temp_pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + PAD_TO_2K(vpe_ctrl->out_w *
vpe_ctrl->out_h * 2, vpe_ctrl->pad_2k_bool);
- msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
+ msm_camera_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
- vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->pcbcr_before_dis =
+ msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
- temp_pyaddr = msm_io_r(vpe_device->vpebase +
+ temp_pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
- msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
+ msm_camera_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
@@ -988,10 +1007,10 @@
regp1 = &(ad->region[0]);
/* for video Y address */
p1 = (regp1->paddr + regp1->info.planar0_off);
- msm_io_w(p1, vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
+ msm_camera_io_w(p1, vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
p1 = (regp1->paddr + regp1->info.planar1_off);
- msm_io_w(p1, vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
+ msm_camera_io_w(p1, vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
return 0;
}
@@ -1051,7 +1070,8 @@
input_stride = (st_half.buf_p1_stride * (1<<16)) +
st_half.buf_p0_stride;
- msm_io_w(input_stride, vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
+ msm_camera_io_w(input_stride,
+ vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
vpe_update_scaler_with_dis(&(vpe_buf.vpe_crop),
&(vpe_ctrl->dis_offset));
@@ -1118,34 +1138,34 @@
CDBG("vpe left frame done.\n");
vpe_ctrl->output_type = 0;
CDBG("vpe send out msg.\n");
- orig_src_y = msm_io_r(vpe_device->vpebase +
+ orig_src_y = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP0_ADDR_OFFSET);
- orig_src_cbcr = msm_io_r(vpe_device->vpebase +
+ orig_src_cbcr = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP1_ADDR_OFFSET);
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- pcbcraddr = msm_io_r(vpe_device->vpebase +
+ pcbcraddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
CDBG("%s: out_w = %d, out_h = %d\n", __func__,
vpe_ctrl->out_w, vpe_ctrl->out_h);
if ((vpe_ctrl->frame_pack == TOP_DOWN_FULL) ||
(vpe_ctrl->frame_pack == TOP_DOWN_HALF)) {
- msm_io_w(pyaddr + (vpe_ctrl->out_w *
+ msm_camera_io_w(pyaddr + (vpe_ctrl->out_w *
vpe_ctrl->out_h), vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- msm_io_w(pcbcraddr + (vpe_ctrl->out_w *
+ msm_camera_io_w(pcbcraddr + (vpe_ctrl->out_w *
vpe_ctrl->out_h/2),
vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
} else if ((vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_HALF) || (vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_FULL)) {
- msm_io_w(pyaddr + vpe_ctrl->out_w,
+ msm_camera_io_w(pyaddr + vpe_ctrl->out_w,
vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- msm_io_w(pcbcraddr + vpe_ctrl->out_w,
+ msm_camera_io_w(pcbcraddr + vpe_ctrl->out_w,
vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
} else
@@ -1164,13 +1184,13 @@
if ((vpe_ctrl->frame_pack == TOP_DOWN_FULL) ||
(vpe_ctrl->frame_pack == TOP_DOWN_HALF)) {
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET) -
(vpe_ctrl->out_w * vpe_ctrl->out_h);
} else if ((vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_HALF) || (vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_FULL)) {
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET) - vpe_ctrl->out_w;
} else
CDBG("%s: Invalid packing = %d\n", __func__,
@@ -1178,27 +1198,27 @@
pcbcraddr = vpe_ctrl->pcbcr_before_dis;
} else {
- src_y = msm_io_r(vpe_device->vpebase +
+ src_y = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP0_ADDR_OFFSET);
- src_cbcr = msm_io_r(vpe_device->vpebase +
+ src_cbcr = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP1_ADDR_OFFSET);
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- pcbcraddr = msm_io_r(vpe_device->vpebase +
+ pcbcraddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en)
pcbcraddr = vpe_ctrl->pcbcr_before_dis;
- msm_io_w(src_y,
+ msm_camera_io_w(src_y,
vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
- msm_io_w(src_cbcr,
+ msm_camera_io_w(src_cbcr,
vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
- temp = msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET) &
- 0xFFFFFFFC;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
+ & 0xFFFFFFFC;
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
/* now pass this frame to msm_camera.c. */
if (vpe_ctrl->output_type == OUTPUT_TYPE_ST_R) {
@@ -1227,12 +1247,12 @@
CDBG("vpe_parse_irq.\n");
/* read and clear back-to-back. */
- irq_status = msm_io_r_mb(vpe_device->vpebase +
+ irq_status = msm_camera_io_r_mb(vpe_device->vpebase +
VPE_INTR_STATUS_OFFSET);
- msm_io_w_mb(irq_status, vpe_device->vpebase +
+ msm_camera_io_w_mb(irq_status, vpe_device->vpebase +
VPE_INTR_CLEAR_OFFSET);
- msm_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
if (irq_status == 0) {
pr_err("%s: irq_status = 0,Something is wrong!\n", __func__);
@@ -1343,9 +1363,9 @@
}
vpe_ctrl->state = VPE_STATE_IDLE;
spin_unlock_irqrestore(&vpe_ctrl->ops_lock, flags);
- vpe_ctrl->out_y_addr = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->out_y_addr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- vpe_ctrl->out_cbcr_addr = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->out_cbcr_addr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
free_irq(vpe_device->vpeirq, 0);
tasklet_kill(&vpe_tasklet);
@@ -1402,7 +1422,7 @@
return rc; /* this rc should be zero.*/
iounmap(vpe_device->vpebase); /* this path should never occur */
-
+ vpe_device->vpebase = NULL;
/* from this part it is error handling. */
vpe_release_mem_region:
release_mem_region(vpemem->start, (vpemem->end - vpemem->start) + 1);
@@ -1416,6 +1436,7 @@
vpemem = vpe_device->vpemem;
iounmap(vpe_device->vpebase);
+ vpe_device->vpebase = NULL;
release_mem_region(vpemem->start,
(vpemem->end - vpemem->start) + 1);
return 0;
diff --git a/drivers/media/video/msm/sensors/imx074_v4l2.c b/drivers/media/video/msm/sensors/imx074_v4l2.c
index 5330d7b..67b7140 100644
--- a/drivers/media/video/msm/sensors/imx074_v4l2.c
+++ b/drivers/media/video/msm/sensors/imx074_v4l2.c
@@ -184,13 +184,14 @@
static struct msm_camera_csid_vc_cfg imx074_cid_cfg[] = {
{0, CSI_RAW10, CSI_DECODE_10BIT},
{1, CSI_EMBED_DATA, CSI_DECODE_8BIT},
+ {2, CSI_RESERVED_DATA_0, CSI_DECODE_8BIT},
};
static struct msm_camera_csi2_params imx074_csi_params = {
.csid_params = {
.lane_cnt = 4,
.lut_params = {
- .num_cid = 2,
+ .num_cid = ARRAY_SIZE(imx074_cid_cfg),
.vc_cfg = imx074_cid_cfg,
},
},
diff --git a/drivers/media/video/msm/sensors/imx091.c b/drivers/media/video/msm/sensors/imx091.c
index 34f0820..62e97ac 100644
--- a/drivers/media/video/msm/sensors/imx091.c
+++ b/drivers/media/video/msm/sensors/imx091.c
@@ -211,13 +211,14 @@
static struct msm_camera_csid_vc_cfg imx091_cid_cfg[] = {
{0, CSI_RAW10, CSI_DECODE_10BIT},
{1, CSI_EMBED_DATA, CSI_DECODE_8BIT},
+ {2, CSI_RESERVED_DATA_0, CSI_DECODE_8BIT},
};
static struct msm_camera_csi2_params imx091_csi_params = {
.csid_params = {
.lane_cnt = 4,
.lut_params = {
- .num_cid = 2,
+ .num_cid = ARRAY_SIZE(imx091_cid_cfg),
.vc_cfg = imx091_cid_cfg,
},
},
diff --git a/drivers/media/video/msm/sensors/mt9e013_v4l2.c b/drivers/media/video/msm/sensors/mt9e013_v4l2.c
index e6e2d52..7f0fbc3 100644
--- a/drivers/media/video/msm/sensors/mt9e013_v4l2.c
+++ b/drivers/media/video/msm/sensors/mt9e013_v4l2.c
@@ -271,6 +271,8 @@
ARRAY_SIZE(mt9e013_prev_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
{&mt9e013_hfr60_settings[0],
ARRAY_SIZE(mt9e013_hfr60_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
+ {&mt9e013_hfr60_settings[0],
+ ARRAY_SIZE(mt9e013_hfr60_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
{&mt9e013_hfr90_settings[0],
ARRAY_SIZE(mt9e013_hfr90_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
{&mt9e013_hfr120_settings[0],
@@ -310,6 +312,15 @@
.y_output = 0x212,
.line_length_pclk = 0x970,
.frame_length_lines = 0x2A1,
+ .vt_pixel_clk = 98400000,
+ .op_pixel_clk = 98400000,
+ .binning_factor = 1,
+ },
+ {
+ .x_output = 0x340,
+ .y_output = 0x212,
+ .line_length_pclk = 0x970,
+ .frame_length_lines = 0x2A1,
.vt_pixel_clk = 146400000,
.op_pixel_clk = 146400000,
.binning_factor = 1,
@@ -339,6 +350,7 @@
&mt9e013_csi_params,
&mt9e013_csi_params,
&mt9e013_csi_params,
+ &mt9e013_csi_params,
};
static struct msm_sensor_output_reg_addr_t mt9e013_reg_addr = {
diff --git a/drivers/media/video/msm/sensors/s5k3l1yx.c b/drivers/media/video/msm/sensors/s5k3l1yx.c
index 4a790f8..8d022b6 100644
--- a/drivers/media/video/msm/sensors/s5k3l1yx.c
+++ b/drivers/media/video/msm/sensors/s5k3l1yx.c
@@ -538,6 +538,7 @@
static struct msm_camera_csid_vc_cfg s5k3l1yx_cid_cfg[] = {
{0, CSI_RAW10, CSI_DECODE_10BIT},
+ {1, CSI_EMBED_DATA, CSI_DECODE_8BIT},
};
static struct msm_camera_csi2_params s5k3l1yx_csi_params = {
diff --git a/drivers/media/video/vcap_v4l2.c b/drivers/media/video/vcap_v4l2.c
new file mode 100644
index 0000000..6443250
--- /dev/null
+++ b/drivers/media/video/vcap_v4l2.c
@@ -0,0 +1,908 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <linux/memory_alloc.h>
+
+#include <mach/msm_subsystem_map.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+#include <media/videobuf2-msm-mem.h>
+
+#include <media/videobuf2-vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-common.h>
+#include <linux/regulator/consumer.h>
+#include <mach/clk.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <mach/msm_bus.h>
+#include <mach/msm_bus_board.h>
+
+#include <media/vcap_v4l2.h>
+#include <media/vcap_fmt.h>
+#include "vcap_vc.h"
+
+#define NUM_INPUTS 1
+#define MSM_VCAP_DRV_NAME "msm_vcap"
+
+static struct vcap_dev *vcap_ctrl;
+
+static unsigned debug;
+
+#define dprintk(level, fmt, arg...) \
+ do { \
+ if (debug >= level) \
+ printk(KERN_DEBUG "VCAP: " fmt, ## arg); \
+ } while (0)
+
+int get_phys_addr(struct vcap_dev *dev, struct vb2_queue *q,
+ struct v4l2_buffer *b)
+{
+ struct vb2_buffer *vb;
+ struct vcap_buffer *buf;
+ unsigned long len, offset;
+ int rc;
+
+ if (q->fileio) {
+ dprintk(1, "%s: file io in progress\n", __func__);
+ return -EBUSY;
+ }
+
+ if (b->type != q->type) {
+ dprintk(1, "%s: invalid buffer type\n", __func__);
+ return -EINVAL;
+ }
+
+ if (b->index >= q->num_buffers) {
+ dprintk(1, "%s: buffer index out of range\n", __func__);
+ return -EINVAL;
+ }
+
+ vb = q->bufs[b->index];
+ if (NULL == vb) {
+ dprintk(1, "%s: buffer is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if (vb->state != VB2_BUF_STATE_DEQUEUED) {
+ dprintk(1, "%s: buffer already in use\n", __func__);
+ return -EINVAL;
+ }
+
+ buf = container_of(vb, struct vcap_buffer, vb);
+
+ buf->ion_handle = ion_import_fd(dev->ion_client, b->m.userptr);
+ if (IS_ERR((void *)buf->ion_handle)) {
+ pr_err("%s: Could not alloc memory\n", __func__);
+ buf->ion_handle = NULL;
+ return -ENOMEM;
+ }
+ rc = ion_phys(dev->ion_client, buf->ion_handle,
+ &buf->paddr, (size_t *)&len);
+ if (rc < 0) {
+ pr_err("%s: Could not get phys addr\n", __func__);
+ return -EFAULT;
+ }
+
+ offset = b->reserved;
+ buf->paddr += offset;
+ return 0;
+}
+
+void free_ion_handle_work(struct vcap_dev *dev, struct vb2_buffer *vb)
+{
+ struct vcap_buffer *buf;
+
+ buf = container_of(vb, struct vcap_buffer, vb);
+ if (buf->ion_handle == NULL) {
+ dprintk(1, "%s: no ION handle to free\n", __func__);
+ return;
+ }
+ buf->paddr = 0;
+ ion_free(dev->ion_client, buf->ion_handle);
+ buf->ion_handle = NULL;
+ return;
+}
+
+int free_ion_handle(struct vcap_dev *dev, struct vb2_queue *q,
+ struct v4l2_buffer *b)
+{
+ struct vb2_buffer *vb;
+
+ if (q->fileio)
+ return -EBUSY;
+
+ if (b->type != q->type)
+ return -EINVAL;
+
+ if (b->index >= q->num_buffers)
+ return -EINVAL;
+
+ vb = q->bufs[b->index];
+ if (NULL == vb)
+ return -EINVAL;
+
+ free_ion_handle_work(dev, vb);
+ return 0;
+}
+
+/* Videobuf operations */
+
+static int capture_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
+ unsigned int *nplanes, unsigned long sizes[],
+ void *alloc_ctxs[])
+{
+ *nbuffers = 3;
+ *nplanes = 1;
+ return 0;
+}
+
+static int capture_buffer_init(struct vb2_buffer *vb)
+{
+ return 0;
+}
+
+static int capture_buffer_prepare(struct vb2_buffer *vb)
+{
+ return 0;
+}
+
+static void capture_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(vb->vb2_queue);
+ struct vcap_buffer *buf = container_of(vb, struct vcap_buffer, vb);
+ struct vcap_action *vid_vc_action = &c_data->vid_vc_action;
+ struct vb2_queue *q = vb->vb2_queue;
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(&c_data->cap_slock, flags);
+ list_add_tail(&buf->list, &vid_vc_action->active);
+ spin_unlock_irqrestore(&c_data->cap_slock, flags);
+
+ if (atomic_read(&c_data->dev->vc_enabled) == 0) {
+
+ if (atomic_read(&q->queued_count) > 1)
+ if (vc_hw_kick_off(c_data) == 0)
+ atomic_set(&c_data->dev->vc_enabled, 1);
+ }
+}
+
+static int capture_start_streaming(struct vb2_queue *vq)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(vq);
+ dprintk(2, "VC start streaming\n");
+ return vc_start_capture(c_data);
+}
+
+static int capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(vq);
+ struct vb2_buffer *vb;
+
+ vc_stop_capture(c_data);
+
+ while (!list_empty(&c_data->vid_vc_action.active)) {
+ struct vcap_buffer *buf;
+ buf = list_entry(c_data->vid_vc_action.active.next,
+ struct vcap_buffer, list);
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+ }
+
+ /* clean ion handles */
+ list_for_each_entry(vb, &vq->queued_list, queued_entry)
+ free_ion_handle_work(c_data->dev, vb);
+ return 0;
+}
+
+static int capture_buffer_finish(struct vb2_buffer *vb)
+{
+ return 0;
+}
+
+static void capture_buffer_cleanup(struct vb2_buffer *vb)
+{
+}
+
+static struct vb2_ops capture_video_qops = {
+ .queue_setup = capture_queue_setup,
+ .buf_init = capture_buffer_init,
+ .buf_prepare = capture_buffer_prepare,
+ .buf_queue = capture_buffer_queue,
+ .start_streaming = capture_start_streaming,
+ .stop_streaming = capture_stop_streaming,
+ .buf_finish = capture_buffer_finish,
+ .buf_cleanup = capture_buffer_cleanup,
+};
+
+/* IOCTL vidioc handling */
+
+static int vidioc_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ struct vcap_dev *dev = video_drvdata(file);
+
+ strlcpy(cap->driver, MSM_VCAP_DRV_NAME, sizeof(cap->driver));
+ strlcpy(cap->card, MSM_VCAP_DRV_NAME, sizeof(cap->card));
+ strlcpy(cap->bus_info, dev->v4l2_dev.name, sizeof(cap->bus_info));
+ cap->version = 0x10000000;
+ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
+ return 0;
+}
+
+static int vidioc_enum_input(struct file *file, void *priv,
+ struct v4l2_input *inp)
+{
+ if (inp->index >= NUM_INPUTS)
+ return -EINVAL;
+ return 0;
+}
+
+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ return 0;
+}
+
+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ return 0;
+}
+
+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ int size;
+#ifdef NEW_S_FMT
+ struct v4l2_format_vc_ext *vc_format;
+#endif
+ struct vcap_client_data *c_data = file->private_data;
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+#ifdef NEW_S_FMT
+ vc_format = (struct v4l2_format_vc_ext *) f->fmt.raw_data;
+ c_data->vc_format = *vc_format;
+#else
+ c_data->vc_format =
+ vcap_vc_lut[f->fmt.pix.priv];
+#endif
+
+ config_vc_format(c_data);
+
+ size = (c_data->vc_format.hactive_end -
+ c_data->vc_format.hactive_start);
+
+ if (c_data->vc_format.color_space)
+ size *= 3;
+ else
+ size *= 2;
+
+#ifndef NEW_S_FMT
+ f->fmt.pix.bytesperline = size;
+ size *= (c_data->vc_format.vactive_end -
+ c_data->vc_format.vactive_start);
+ f->fmt.pix.sizeimage = size;
+#endif
+ vcap_ctrl->vc_client = c_data;
+ break;
+ case V4L2_BUF_TYPE_INTERLACED_IN_DECODER:
+ c_data->vp_buf_type_field = V4L2_BUF_TYPE_INTERLACED_IN_DECODER;
+ c_data->vp_format.field = f->fmt.pix.field;
+ c_data->vp_format.height = f->fmt.pix.height;
+ c_data->vp_format.width = f->fmt.pix.width;
+ c_data->vp_format.pixelformat = f->fmt.pix.pixelformat;
+ break;
+ case V4L2_BUF_TYPE_INTERLACED_IN_AFE:
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int vidioc_reqbufs(struct file *file, void *priv,
+ struct v4l2_requestbuffers *rb)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ switch (rb->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return vb2_reqbufs(&c_data->vc_vidq, rb);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+ struct vcap_client_data *c_data = file->private_data;
+
+ switch (p->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return vb2_querybuf(&c_data->vc_vidq, p);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ int rc;
+
+ switch (p->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ if (get_phys_addr(c_data->dev, &c_data->vc_vidq, p))
+ return -EINVAL;
+ rc = vb2_qbuf(&c_data->vc_vidq, p);
+ if (rc < 0)
+ free_ion_handle(c_data->dev, &c_data->vc_vidq, p);
+ return rc;
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ int rc;
+
+ switch (p->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ rc = vb2_dqbuf(&c_data->vc_vidq, p, file->f_flags & O_NONBLOCK);
+ if (rc < 0)
+ return rc;
+ return free_ion_handle(c_data->dev, &c_data->vc_vidq, p);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+ struct vcap_client_data *c_data = file->private_data;
+
+ switch (i) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return vb2_streamon(&c_data->vc_vidq, i);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ int rc;
+
+ switch (i) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ rc = vb2_streamoff(&c_data->vc_vidq, i);
+ if (rc >= 0)
+ atomic_set(&c_data->dev->vc_enabled, 0);
+ return rc;
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type", __func__);
+ break;
+ }
+ return 0;
+}
+
+/* VCAP fops */
+
+static void *vcap_ops_get_userptr(void *alloc_ctx, unsigned long vaddr,
+ unsigned long size, int write)
+{
+ struct vcap_buf_info *mem;
+ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+ if (!mem)
+ return ERR_PTR(-ENOMEM);
+ mem->vaddr = vaddr;
+ mem->size = size;
+ return mem;
+}
+
+static void vcap_ops_put_userptr(void *buf_priv)
+{
+ kfree(buf_priv);
+}
+
+const struct vb2_mem_ops vcap_mem_ops = {
+ .get_userptr = vcap_ops_get_userptr,
+ .put_userptr = vcap_ops_put_userptr,
+};
+
+static int vcap_open(struct file *file)
+{
+ struct vcap_dev *dev = video_drvdata(file);
+ struct vcap_client_data *c_data;
+ struct vb2_queue *q;
+ int ret;
+ c_data = kzalloc(sizeof(*c_data), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ c_data->dev = dev;
+
+ spin_lock_init(&c_data->cap_slock);
+
+ /* initialize queue */
+ q = &c_data->vc_vidq;
+ memset(q, 0, sizeof(c_data->vc_vidq));
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ q->io_modes = VB2_USERPTR;
+ q->drv_priv = c_data;
+ q->buf_struct_size = sizeof(struct vcap_buffer);
+ q->ops = &capture_video_qops;
+ q->mem_ops = &vcap_mem_ops;
+
+ ret = vb2_queue_init(q);
+ if (ret < 0)
+ goto open_failed;
+
+ INIT_LIST_HEAD(&c_data->vid_vc_action.active);
+ file->private_data = c_data;
+
+ return 0;
+
+open_failed:
+ kfree(c_data);
+ return ret;
+}
+
+static int vcap_close(struct file *file)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ vb2_queue_release(&c_data->vc_vidq);
+ c_data->dev->vc_client = NULL;
+ c_data->dev->vp_client = NULL;
+ kfree(c_data);
+ return 0;
+}
+
+static unsigned int vcap_poll(struct file *file,
+ struct poll_table_struct *wait)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ struct vb2_queue *q = &c_data->vc_vidq;
+
+ return vb2_poll(q, file, wait);
+}
+/* V4L2 and video device structures */
+
+static const struct v4l2_file_operations vcap_fops = {
+ .owner = THIS_MODULE,
+ .open = vcap_open,
+ .release = vcap_close,
+ .poll = vcap_poll,
+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
+};
+
+static const struct v4l2_ioctl_ops vcap_ioctl_ops = {
+ .vidioc_querycap = vidioc_querycap,
+ .vidioc_enum_input = vidioc_enum_input,
+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
+ .vidioc_reqbufs = vidioc_reqbufs,
+ .vidioc_querybuf = vidioc_querybuf,
+ .vidioc_qbuf = vidioc_qbuf,
+ .vidioc_dqbuf = vidioc_dqbuf,
+ .vidioc_streamon = vidioc_streamon,
+ .vidioc_streamoff = vidioc_streamoff,
+};
+
+static struct video_device vcap_template = {
+ .name = "vcap",
+ .fops = &vcap_fops,
+ .ioctl_ops = &vcap_ioctl_ops,
+ .release = video_device_release,
+};
+
+int vcap_reg_powerup(struct vcap_dev *dev)
+{
+ dev->fs_vcap = regulator_get(NULL, "fs_vcap");
+ if (IS_ERR(dev->fs_vcap)) {
+ pr_err("%s: Regulator FS_VCAP get failed %ld\n", __func__,
+ PTR_ERR(dev->fs_vcap));
+ dev->fs_vcap = NULL;
+ return -EINVAL;
+ } else if (regulator_enable(dev->fs_vcap)) {
+ pr_err("%s: Regulator FS_VCAP enable failed\n", __func__);
+ regulator_put(dev->fs_vcap);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void vcap_reg_powerdown(struct vcap_dev *dev)
+{
+ if (dev->fs_vcap == NULL)
+ return;
+ regulator_disable(dev->fs_vcap);
+ regulator_put(dev->fs_vcap);
+ dev->fs_vcap = NULL;
+ return;
+}
+
+int config_gpios(int on, struct vcap_platform_data *pdata)
+{
+ int i, ret;
+ int num_gpios = pdata->num_gpios;
+ unsigned *gpios = pdata->gpios;
+
+ if (on) {
+ for (i = 0; i < num_gpios; i++) {
+ ret = gpio_request(gpios[i], "vcap:vc");
+ if (ret) {
+ pr_err("VCAP: failed at GPIO %d to request\n",
+ gpios[i]);
+ goto gpio_failed;
+ }
+ ret = gpio_direction_input(gpios[i]);
+ if (ret) {
+ pr_err("VCAP: failed at GPIO %d to set to input\n",
+ gpios[i]);
+ i++;
+ goto gpio_failed;
+ }
+ }
+ } else {
+ for (i = 0; i < num_gpios; i++)
+ gpio_free(gpios[i]);
+ }
+ dprintk(2, "GPIO config done\n");
+ return 0;
+gpio_failed:
+ for (i--; i >= 0; i--)
+ gpio_free(gpios[i]);
+ return -EINVAL;
+}
+
+int vcap_clk_powerup(struct vcap_dev *dev, struct device *ddev)
+{
+ int ret = 0;
+
+ dev->vcap_clk = clk_get(ddev, "core_clk");
+ if (IS_ERR(dev->vcap_clk)) {
+ dev->vcap_clk = NULL;
+ pr_err("%s: Could not clk_get core_clk\n", __func__);
+ clk_put(dev->vcap_clk);
+ dev->vcap_clk = NULL;
+ return -EINVAL;
+ }
+
+ clk_prepare(dev->vcap_clk);
+ ret = clk_enable(dev->vcap_clk);
+ if (ret) {
+ pr_err("%s: Failed core clk_enable %d\n", __func__, ret);
+ goto fail_vcap_clk_unprep;
+ }
+
+ clk_set_rate(dev->vcap_clk, 160000000);
+ if (ret) {
+ pr_err("%s: Failed core set_rate %d\n", __func__, ret);
+ goto fail_vcap_clk;
+ }
+
+ dev->vcap_npl_clk = clk_get(ddev, "vcap_npl_clk");
+ if (IS_ERR(dev->vcap_npl_clk)) {
+ dev->vcap_npl_clk = NULL;
+ pr_err("%s: Could not clk_get npl\n", __func__);
+ clk_put(dev->vcap_npl_clk);
+ dev->vcap_npl_clk = NULL;
+ goto fail_vcap_clk;
+ }
+
+ clk_prepare(dev->vcap_npl_clk);
+ ret = clk_enable(dev->vcap_npl_clk);
+ if (ret) {
+ pr_err("%s:Failed npl clk_enable %d\n", __func__, ret);
+ goto fail_vcap_npl_clk_unprep;
+ }
+
+ dev->vcap_p_clk = clk_get(ddev, "iface_clk");
+ if (IS_ERR(dev->vcap_p_clk)) {
+ dev->vcap_p_clk = NULL;
+ pr_err("%s: Could not clk_get pix(AHB)\n", __func__);
+ clk_put(dev->vcap_p_clk);
+ dev->vcap_p_clk = NULL;
+ goto fail_vcap_npl_clk;
+ }
+
+ clk_prepare(dev->vcap_p_clk);
+ ret = clk_enable(dev->vcap_p_clk);
+ if (ret) {
+ pr_err("%s: Failed pix(AHB) clk_enable %d\n", __func__, ret);
+ goto fail_vcap_p_clk_unprep;
+ }
+ return 0;
+
+fail_vcap_p_clk_unprep:
+ clk_unprepare(dev->vcap_p_clk);
+ clk_put(dev->vcap_p_clk);
+ dev->vcap_p_clk = NULL;
+
+fail_vcap_npl_clk:
+ clk_disable(dev->vcap_npl_clk);
+fail_vcap_npl_clk_unprep:
+ clk_unprepare(dev->vcap_npl_clk);
+ clk_put(dev->vcap_npl_clk);
+ dev->vcap_npl_clk = NULL;
+
+fail_vcap_clk:
+ clk_disable(dev->vcap_clk);
+fail_vcap_clk_unprep:
+ clk_unprepare(dev->vcap_clk);
+ clk_put(dev->vcap_clk);
+ dev->vcap_clk = NULL;
+ return -EINVAL;
+}
+
+void vcap_clk_powerdown(struct vcap_dev *dev)
+{
+ if (dev->vcap_p_clk != NULL) {
+ clk_disable(dev->vcap_p_clk);
+ clk_unprepare(dev->vcap_p_clk);
+ clk_put(dev->vcap_p_clk);
+ dev->vcap_p_clk = NULL;
+ }
+
+ if (dev->vcap_npl_clk != NULL) {
+ clk_disable(dev->vcap_npl_clk);
+ clk_unprepare(dev->vcap_npl_clk);
+ clk_put(dev->vcap_npl_clk);
+ dev->vcap_npl_clk = NULL;
+ }
+
+ if (dev->vcap_clk != NULL) {
+ clk_disable(dev->vcap_clk);
+ clk_unprepare(dev->vcap_clk);
+ clk_put(dev->vcap_clk);
+ dev->vcap_clk = NULL;
+ }
+}
+
+int vcap_get_bus_client_handle(struct vcap_dev *dev)
+{
+ struct msm_bus_scale_pdata *vcap_axi_client_pdata =
+ dev->vcap_pdata->bus_client_pdata;
+ dev->bus_client_handle =
+ msm_bus_scale_register_client(vcap_axi_client_pdata);
+
+ return 0;
+}
+
+int vcap_enable(struct vcap_dev *dev, struct device *ddev)
+{
+ int rc;
+
+ rc = vcap_reg_powerup(dev);
+ if (rc < 0)
+ goto reg_failed;
+ rc = vcap_clk_powerup(dev, ddev);
+ if (rc < 0)
+ goto clk_failed;
+ rc = vcap_get_bus_client_handle(dev);
+ if (rc < 0)
+ goto bus_r_failed;
+ config_gpios(1, dev->vcap_pdata);
+ if (rc < 0)
+ goto gpio_failed;
+ return 0;
+
+gpio_failed:
+ msm_bus_scale_unregister_client(dev->bus_client_handle);
+ dev->bus_client_handle = 0;
+bus_r_failed:
+ vcap_clk_powerdown(dev);
+clk_failed:
+ vcap_reg_powerdown(dev);
+reg_failed:
+ return rc;
+}
+
+int vcap_disable(struct vcap_dev *dev)
+{
+ config_gpios(0, dev->vcap_pdata);
+
+ msm_bus_scale_unregister_client(dev->bus_client_handle);
+ dev->bus_client_handle = 0;
+ vcap_clk_powerdown(dev);
+ vcap_reg_powerdown(dev);
+ return 0;
+}
+
+static irqreturn_t vcap_vc_handler(int irq_num, void *data)
+{
+ return vc_handler(vcap_ctrl);
+}
+
+static int __devinit vcap_probe(struct platform_device *pdev)
+{
+ struct vcap_dev *dev;
+ struct video_device *vfd;
+ int ret;
+
+ dprintk(1, "Probe started\n");
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+ vcap_ctrl = dev;
+ dev->vcap_pdata = pdev->dev.platform_data;
+
+ dev->vcapmem = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "vcap");
+ if (!dev->vcapmem) {
+ pr_err("VCAP: %s: no mem resource?\n", __func__);
+ ret = -ENODEV;
+ goto free_dev;
+ }
+
+ dev->vcapio = request_mem_region(dev->vcapmem->start,
+ resource_size(dev->vcapmem), pdev->name);
+ if (!dev->vcapio) {
+ pr_err("VCAP: %s: no valid mem region\n", __func__);
+ ret = -EBUSY;
+ goto free_dev;
+ }
+
+ dev->vcapbase = ioremap(dev->vcapmem->start,
+ resource_size(dev->vcapmem));
+ if (!dev->vcapbase) {
+ ret = -ENOMEM;
+ pr_err("VCAP: %s: vcap ioremap failed\n", __func__);
+ goto free_resource;
+ }
+
+ dev->vcapirq = platform_get_resource_byname(pdev,
+ IORESOURCE_IRQ, "vcap");
+ if (!dev->vcapirq) {
+ pr_err("%s: no irq resource?\n", __func__);
+ ret = -ENODEV;
+ goto free_resource;
+ }
+
+ ret = request_irq(dev->vcapirq->start, vcap_vc_handler,
+ IRQF_TRIGGER_RISING, "vcap", 0);
+ if (ret < 0) {
+ pr_err("%s: irq request fail\n", __func__);
+ ret = -EBUSY;
+ goto free_resource;
+ }
+
+ disable_irq(dev->vcapirq->start);
+
+ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
+ "%s", MSM_VCAP_DRV_NAME);
+ ret = v4l2_device_register(NULL, &dev->v4l2_dev);
+ if (ret)
+ goto free_resource;
+
+ ret = vcap_enable(dev, &pdev->dev);
+ if (ret)
+ goto unreg_dev;
+ msm_bus_scale_client_update_request(dev->bus_client_handle, 3);
+
+ ret = detect_vc(dev);
+
+ if (ret)
+ goto power_down;
+
+ /* init video device*/
+ vfd = video_device_alloc();
+ if (!vfd)
+ goto deinit_vc;
+
+ *vfd = vcap_template;
+ vfd->v4l2_dev = &dev->v4l2_dev;
+
+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+ if (ret < 0)
+ goto rel_vdev;
+
+ dev->vfd = vfd;
+ video_set_drvdata(vfd, dev);
+
+ dev->ion_client = msm_ion_client_create(-1, "vcap");
+ if (IS_ERR((void *)dev->ion_client)) {
+ pr_err("could not get ion client");
+ goto rel_vdev;
+ }
+
+ atomic_set(&dev->vc_enabled, 0);
+
+ dprintk(1, "Exit probe succesfully");
+ return 0;
+
+rel_vdev:
+ video_device_release(vfd);
+deinit_vc:
+ deinit_vc();
+power_down:
+ vcap_disable(dev);
+unreg_dev:
+ v4l2_device_unregister(&dev->v4l2_dev);
+free_resource:
+ iounmap(dev->vcapbase);
+ release_mem_region(dev->vcapmem->start, resource_size(dev->vcapmem));
+free_dev:
+ vcap_ctrl = NULL;
+ kfree(dev);
+ return ret;
+}
+
+static int __devexit vcap_remove(struct platform_device *pdev)
+{
+ struct vcap_dev *dev = vcap_ctrl;
+ ion_client_destroy(dev->ion_client);
+ video_device_release(dev->vfd);
+ deinit_vc();
+ vcap_disable(dev);
+ v4l2_device_unregister(&dev->v4l2_dev);
+ iounmap(dev->vcapbase);
+ release_mem_region(dev->vcapmem->start, resource_size(dev->vcapmem));
+ vcap_ctrl = NULL;
+ kfree(dev);
+
+ return 0;
+}
+
+struct platform_driver vcap_platform_driver = {
+ .driver = {
+ .name = MSM_VCAP_DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+ .probe = vcap_probe,
+ .remove = vcap_remove,
+};
+
+static int __init vcap_init_module(void)
+{
+ return platform_driver_register(&vcap_platform_driver);
+}
+
+static void __exit vcap_exit_module(void)
+{
+ platform_driver_unregister(&vcap_platform_driver);
+}
+
+module_init(vcap_init_module);
+module_exit(vcap_exit_module);
+MODULE_DESCRIPTION("VCAP driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/vcap_vc.c b/drivers/media/video/vcap_vc.c
new file mode 100644
index 0000000..ed0bc25
--- /dev/null
+++ b/drivers/media/video/vcap_vc.c
@@ -0,0 +1,715 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kthread.h>
+#include <linux/freezer.h>
+#include <mach/camera.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <mach/clk.h>
+#include <linux/clk.h>
+
+#include <media/vcap_v4l2.h>
+#include <media/vcap_fmt.h>
+#include "vcap_vc.h"
+
+static unsigned debug;
+
+#define dprintk(level, fmt, arg...) \
+ do { \
+ if (debug >= level) \
+ printk(KERN_DEBUG "VC: " fmt, ## arg); \
+ } while (0)
+
+struct v4l2_format_vc_ext vcap_vc_lut[] = {
+ /* 1080p */
+ {
+ HAL_VCAP_YUV_1080p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 32, 2200, 192, 2112, 4, 24, 0, 2, 0, 44, 0, 0, 0, 0,
+ 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 1125, 2200, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_1080p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 148.5,
+ 1125, 2200, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_24_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2750, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_24_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 112, 2750, 192, 2112, 4, 110, 0, 2, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_24_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 275, 19, 211, 41, 1121, 0, 5, 0, 16, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_60_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 1125, 200, 22, 182, 41, 1121, 0, 5, 0, 16, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 1125, 2640, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_50_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 15, 2640, 192, 2112, 6, 13, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_25_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2640, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0,
+ 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_25_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 10, 2640, 192, 2112, 4, 8, 0, 2, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_30_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2200, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_1080p_25_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 74.25,
+ 1125, 2640, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_1080p_25_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 74.25,
+ 10, 2640, 192, 2112, 4, 8, 0, 2, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ /* 1080i */
+ {
+ HAL_VCAP_YUV_1080i_60_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2200, 192, 2112, 20, 560, 0, 5, 0, 44, 583, 1123, 1100,
+ 1100, 563, 568
+ },
+ {
+ HAL_VCAP_YUV_1080i_60_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 18, 2200, 192, 2112, 3, 7, 0, 2, 0, 44, 11, 15, 1100,
+ 1100, 8, 10
+ },
+ {
+ HAL_VCAP_YUV_1080i_60_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 220, 19, 211, 20, 560, 0, 5, 0, 4, 583, 1123, 110,
+ 110, 563, 568
+ },
+ {
+ HAL_VCAP_YUV_1080i_50_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 72.00,
+ 1125, 2640, 192, 2112, 20, 560, 0, 5, 0, 44, 583, 1123, 1320,
+ 1320, 563, 568
+ },
+ {
+ HAL_VCAP_YUV_1080i_50_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 72.00,
+ 52, 2640, 192, 2112, 4, 24, 0, 2, 0, 44, 30, 50, 1320,
+ 1320, 26, 28},
+ {
+ HAL_VCAP_YUV_1080i_50_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 72.00,
+ 1125, 264, 19, 211, 20, 560, 0, 5, 0, 4, 583, 1123, 110,
+ 110, 563, 568
+ },
+ {
+ HAL_VCAP_RGB_1080i_50_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 72.00,
+ 1125, 2640, 192, 2112, 20, 560, 0, 5, 0, 44, 583, 1123, 1320,
+ 1320, 563, 568
+ },
+ {
+ HAL_VCAP_RGB_1080i_50_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 72.00,
+ 52, 2640, 192, 2112, 4, 24, 0, 2, 0, 44, 30, 50, 1320,
+ 1320, 26, 28
+ },
+ /* 480i */
+ {
+ HAL_VCAP_YUV_480i_60_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 20, 1716, 238, 1678, 3, 7, 0, 2, 0, 124, 14, 18, 820,
+ 820, 10, 12
+ },
+ {
+ HAL_VCAP_YUV_480i_60_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 1716, 238, 1678, 18, 258, 0, 3, 0, 124, 281, 521, 858,
+ 858, 262, 265
+ },
+ {
+ HAL_VCAP_YUV_480i_60_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 172, 24, 168, 18, 258, 0, 3, 0, 12, 281, 521, 86,
+ 86, 262, 265
+ },
+ {
+ HAL_VCAP_YUV_2880_480i_60_FL, HAL_VCAP_MODE_INT,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 54.000, 525, 3432, 476, 3356, 18, 258, 0, 3,
+ 0, 248, 281, 521, 1716, 1716, 262, 265
+ },
+ {
+ HAL_VCAP_YUV_2880_480i_60_RH, HAL_VCAP_MODE_INT,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 54.000, 32, 3432, 476, 3356, 4, 14, 0, 3, 0,
+ 248, 20, 30, 1716, 1716, 16, 19
+ },
+ /* 480p */
+ {
+ HAL_VCAP_YUV_480p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 8, 858, 122, 842, 2, 5, 0, 1, 0, 62, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_480p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 27.027,
+ 52, 858, 122, 842, 3, 50, 0, 2, 0, 62, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_480p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 27.027,
+ 525, 858, 122, 842, 36, 516, 0, 6, 0, 62, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_480p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 858, 122, 842, 36, 516, 0, 6, 0, 62, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_480p_60_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 86, 12, 84, 36, 516, 0, 6, 0, 6, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_480p_60_FL, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 525, 3432, 488, 3368, 36, 516, 0, 6,
+ 0, 248, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_480p_60_RH, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 25, 3432, 488, 3368, 8, 22, 0, 6, 0,
+ 248, 0, 0, 0, 0, 0, 0
+ },
+ /* 720p */
+ {
+ HAL_VCAP_YUV_720p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 1650, 260, 1540, 25, 745, 0, 5, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_720p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 74.25,
+ 750, 1650, 260, 1540, 25, 745, 0, 5, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_60_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 165, 26, 154, 25, 745, 0, 5, 0, 4, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 35, 1650, 260, 1540, 5, 32, 0, 3, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 1980, 260, 1540, 25, 745, 0, 5, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_50_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 198, 26, 154, 25, 745, 0, 5, 0, 4, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_50_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 6, 1980, 260, 1540, 2, 5, 0, 1, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ /* 576p */
+ {
+ HAL_VCAP_YUV_576p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 864, 132, 852, 44, 620, 0, 5, 0, 64, 0, 0, 0,
+ 0, 0, 0},
+ {
+ HAL_VCAP_RGB_576p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 27.0,
+ 625, 864, 132, 852, 44, 620, 0, 5, 0, 64, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_576p_50_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 86, 13, 85, 44, 620, 0, 5, 0, 6, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_576p_50_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 25, 864, 132, 852, 4, 23, 0, 3, 0, 64, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1440_576p_50_RH, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 54.000, 25, 1728, 264, 1704, 6, 23, 0, 5, 0,
+ 128, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_576p_50_FL, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 625, 3456, 528, 3408, 44, 620, 0, 5,
+ 0, 256, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_576p_50_RH, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 25, 3456, 528, 3408, 6, 23, 0, 5, 0,
+ 256, 0, 0, 0, 0, 0, 0
+ },
+ /* 576i */
+ {
+ HAL_VCAP_YUV_576i_50_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 1728, 264, 1704, 22, 310, 0, 3, 0, 126, 335, 623, 864,
+ 864, 313, 316
+ },
+ {
+ HAL_VCAP_YUV_576i_50_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 172, 26, 170, 22, 310, 0, 3, 0, 13, 335, 623, 86,
+ 86, 313, 316
+ },
+ {
+ HAL_VCAP_YUV_576i_50_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 29, 1728, 264, 1704, 3, 13, 0, 1, 0, 126, 16, 26, 864, 864,
+ 14, 15
+ },
+ /* XGA 1024x768 */
+ {
+ HAL_VCAP_YUV_XGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 63.5,
+ 798, 1328, 256, 1280, 27, 795, 0, 4, 0, 104, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_XGA_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 63.5,
+ 12, 1328, 256, 1280, 6, 10, 0, 4, 0, 104, 0, 0, 0, 0,
+ 0, 0
+ },
+ {
+ HAL_VCAP_YUV_XGA_RB, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 63.5,
+ 12, 1216, 112, 1136, 6, 10, 0, 4, 0, 32, 0, 0, 0, 0,
+ 0, 0
+ },
+ /* SXGA 1280x1024 */
+ {
+ HAL_VCAP_YUV_SXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 109.0,
+ 1063, 1712, 352, 1632, 36, 1060, 0, 7, 0, 136, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_SXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 109.0,
+ 1063, 1712, 352, 1632, 36, 1060, 0, 7, 0, 136, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_SXGA_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 109.0,
+ 17, 1712, 352, 1632, 8, 15, 0, 7, 0, 136, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_SXGA_RB, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 109.0,
+ 17, 1440, 112, 1392, 8, 15, 0, 7, 0, 32, 0, 0, 0, 0,
+ 0, 0
+ },
+ /* UXGA 1600x1200 */
+ {
+ HAL_VCAP_YUV_UXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 161.0,
+ 1245, 2160, 448, 2048, 42, 1242, 0, 4, 0, 168, 0,
+ 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_UXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 161.0,
+ 1245, 2160, 448, 2048, 42, 1242, 0, 4, 0, 168, 0,
+ 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_UXGA_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 161.0,
+ 12, 2160, 448, 2048, 6, 10, 0, 4, 0, 168, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_UXGA_RB, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 161.0,
+ 12, 1808, 112, 1712, 6, 10, 0, 4, 0, 32, 0, 0, 0, 0,
+ 0, 0
+ },
+ /* test odd height */
+ {
+ HAL_VCAP_ODD_HEIGHT, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_NEG, HAL_VCAP_YUV, 148.5,
+ 65, 1728, 264, 1704, 5, 20, 0, 3, 0, 126, 25, 40, 864,
+ 864, 21, 24
+ },
+ /* test odd width RGB only */
+ {
+ HAL_VCAP_ODD_WIDTH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_NEG, HAL_VCAP_RGB, 148.5,
+ 52, 859, 122, 843, 3, 50, 0, 2, 0, 62, 0, 0, 0, 0, 0, 0
+ },
+};
+
+void config_buffer(struct vcap_client_data *c_data,
+ struct vcap_buffer *buf,
+ void __iomem *y_addr,
+ void __iomem *c_addr)
+{
+ if (c_data->vc_format.color_space == HAL_VCAP_RGB) {
+ writel_relaxed(buf->paddr, y_addr);
+ } else {
+ int size = ((c_data->vc_format.hactive_end -
+ c_data->vc_format.hactive_start) *
+ (c_data->vc_format.vactive_end -
+ c_data->vc_format.vactive_start));
+ writel_relaxed(buf->paddr, y_addr);
+ writel_relaxed(buf->paddr + size, c_addr);
+ }
+}
+
+irqreturn_t vc_handler(struct vcap_dev *dev)
+{
+ uint32_t irq, timestamp;
+ enum rdy_buf vc_buf_status, buf_ind;
+ struct vcap_buffer *buf;
+ struct vb2_buffer *vb = NULL;
+ struct vcap_client_data *c_data;
+
+ irq = readl_relaxed(VCAP_VC_INT_STATUS);
+
+ dprintk(1, "%s: irq=0x%08x\n", __func__, irq);
+
+ vc_buf_status = irq & VC_BUFFER_WRITTEN;
+
+ dprintk(1, "Done buf status = %d\n", vc_buf_status);
+
+ if (vc_buf_status == VC_NO_BUF) {
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ pr_err("VC IRQ shows some error\n");
+ return IRQ_HANDLED;
+ }
+
+ if (dev->vc_client == NULL) {
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ pr_err("VC: There is no active vc client\n");
+ return IRQ_HANDLED;
+ }
+ c_data = dev->vc_client;
+
+ spin_lock(&dev->vc_client->cap_slock);
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ /* Just leave we have no new queued buffers */
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ spin_unlock(&dev->vc_client->cap_slock);
+ dprintk(1, "We have no more avilable buffers\n");
+ return IRQ_HANDLED;
+ }
+ spin_unlock(&dev->vc_client->cap_slock);
+
+ timestamp = readl_relaxed(VCAP_VC_TIMESTAMP);
+
+ buf_ind = dev->vc_client->vid_vc_action.buf_ind;
+
+ if (vc_buf_status == VC_BUF1N2) {
+ /* There are 2 buffer ready */
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ return IRQ_HANDLED;
+ } else if (buf_ind != vc_buf_status) {
+ /* buffer is out of sync */
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ return IRQ_HANDLED;
+ }
+
+ if (buf_ind == VC_BUF1) {
+ dprintk(1, "Got BUF1\n");
+ vb = &dev->vc_client->vid_vc_action.buf1->vb;
+ spin_lock(&dev->vc_client->cap_slock);
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ spin_unlock(&dev->vc_client->cap_slock);
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ return IRQ_HANDLED;
+ }
+ buf = list_entry(dev->vc_client->vid_vc_action.active.next,
+ struct vcap_buffer, list);
+ list_del(&buf->list);
+ spin_unlock(&dev->vc_client->cap_slock);
+ /* Config vc with this new buffer */
+ config_buffer(c_data, buf, VCAP_VC_Y_ADDR_1,
+ VCAP_VC_C_ADDR_1);
+
+ vb->v4l2_buf.timestamp.tv_usec = timestamp;
+ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+ dev->vc_client->vid_vc_action.buf1 = buf;
+ dev->vc_client->vid_vc_action.buf_ind = VC_BUF2;
+ irq = VC_BUF1;
+ } else {
+ dprintk(1, "Got BUF2\n");
+ spin_lock(&dev->vc_client->cap_slock);
+ vb = &dev->vc_client->vid_vc_action.buf2->vb;
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ spin_unlock(&dev->vc_client->cap_slock);
+ return IRQ_HANDLED;
+ }
+ buf = list_entry(dev->vc_client->vid_vc_action.active.next,
+ struct vcap_buffer, list);
+ list_del(&buf->list);
+ spin_unlock(&dev->vc_client->cap_slock);
+ /* Config vc with this new buffer */
+ config_buffer(c_data, buf, VCAP_VC_Y_ADDR_2,
+ VCAP_VC_C_ADDR_2);
+
+ vb->v4l2_buf.timestamp.tv_usec = timestamp;
+ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+
+ dev->vc_client->vid_vc_action.buf2 = buf;
+ dev->vc_client->vid_vc_action.buf_ind = VC_BUF1;
+ irq = VC_BUF2;
+ }
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+
+ return IRQ_HANDLED;
+}
+
+int vc_start_capture(struct vcap_client_data *c_data)
+{
+ return 0;
+}
+
+int vc_hw_kick_off(struct vcap_client_data *c_data)
+{
+ struct vcap_action *vid_vc_action = &c_data->vid_vc_action;
+ struct vcap_dev *dev;
+ unsigned long flags = 0;
+ int rc, counter = 0;
+ struct vcap_buffer *buf;
+
+ dev = c_data->dev;
+ vid_vc_action->buf_ind = VC_BUF1;
+ dprintk(2, "Start Kickoff\n");
+
+ if (dev->vc_client == NULL) {
+ pr_err("No active vc client\n");
+ return -ENODEV;
+ }
+ spin_lock_irqsave(&dev->vc_client->cap_slock, flags);
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ spin_unlock_irqrestore(&dev->vc_client->cap_slock, flags);
+ pr_err("%s: VC We have no more avilable buffers\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ list_for_each_entry(buf, &vid_vc_action->active, list)
+ counter++;
+
+ if (counter < 2) {
+ /* not enough buffers have been queued */
+ spin_unlock_irqrestore(&dev->vc_client->cap_slock, flags);
+ return -EINVAL;
+ }
+
+ vid_vc_action->buf1 = list_entry(vid_vc_action->active.next,
+ struct vcap_buffer, list);
+ list_del(&vid_vc_action->buf1->list);
+
+ vid_vc_action->buf2 = list_entry(vid_vc_action->active.next,
+ struct vcap_buffer, list);
+ list_del(&vid_vc_action->buf2->list);
+
+ spin_unlock_irqrestore(&dev->vc_client->cap_slock, flags);
+
+ config_buffer(c_data, vid_vc_action->buf1, VCAP_VC_Y_ADDR_1,
+ VCAP_VC_C_ADDR_1);
+ config_buffer(c_data, vid_vc_action->buf2, VCAP_VC_Y_ADDR_2,
+ VCAP_VC_C_ADDR_2);
+
+ rc = readl_relaxed(VCAP_VC_CTRL);
+ writel_relaxed(rc | 0x1, VCAP_VC_CTRL);
+
+ writel_relaxed(0x6, VCAP_VC_INT_MASK);
+
+ enable_irq(dev->vcapirq->start);
+ return 0;
+}
+
+void vc_stop_capture(struct vcap_client_data *c_data)
+{
+ struct vcap_dev *dev = c_data->dev;
+ int rc;
+
+ rc = readl_relaxed(VCAP_VC_CTRL);
+ writel_relaxed(rc & ~(0x1), VCAP_VC_CTRL);
+
+ disable_irq(c_data->dev->vcapirq->start);
+}
+
+int config_vc_format(struct vcap_client_data *c_data)
+{
+ struct vcap_dev *dev;
+ unsigned int rc;
+ int timeout;
+ struct v4l2_format_vc_ext *vc_format = &c_data->vc_format;
+ dev = c_data->dev;
+
+ /* restart VC */
+ writel_relaxed(0x00000001, VCAP_SW_RESET_REQ);
+ timeout = 10000;
+ while (1) {
+ rc = (readl_relaxed(VCAP_SW_RESET_STATUS) & 0x1);
+ if (!rc)
+ break;
+ timeout--;
+ if (timeout == 0) {
+ pr_err("VC is not resetting properly\n");
+ return -EINVAL;
+ }
+ }
+ writel_relaxed(0x00000000, VCAP_SW_RESET_REQ);
+
+ writel_relaxed(0x00000102, VCAP_VC_NPL_CTRL);
+ rc = readl_relaxed(VCAP_VC_NPL_CTRL);
+ rc = readl_relaxed(VCAP_VC_NPL_CTRL);
+ writel_relaxed(0x00000002, VCAP_VC_NPL_CTRL);
+
+ dprintk(2, "%s: Starting VC configuration\n", __func__);
+ writel_relaxed(0x00000002, VCAP_VC_NPL_CTRL);
+ writel_relaxed(0x00000004 | vc_format->color_space << 1, VCAP_VC_CTRL);
+
+ writel_relaxed(vc_format->h_polar << 4 |
+ vc_format->v_polar << 0, VCAP_VC_POLARITY);
+
+ writel_relaxed(vc_format->h_polar << 4 |
+ vc_format->v_polar << 0, VCAP_VC_POLARITY);
+ writel_relaxed(((vc_format->htotal << 16) | vc_format->vtotal),
+ VCAP_VC_V_H_TOTAL);
+ writel_relaxed(((vc_format->hactive_end << 16) |
+ vc_format->hactive_start), VCAP_VC_H_ACTIVE);
+
+ writel_relaxed(((vc_format->vactive_end << 16) |
+ vc_format->vactive_start), VCAP_VC_V_ACTIVE);
+ writel_relaxed(((vc_format->f2_vactive_end << 16) |
+ vc_format->f2_vactive_start), VCAP_VC_V_ACTIVE_F2);
+ writel_relaxed(((vc_format->vsync_end << 16) | vc_format->vsync_start),
+ VCAP_VC_VSYNC_VPOS);
+ writel_relaxed(((vc_format->f2_vsync_v_end << 16) |
+ vc_format->f2_vsync_v_start), VCAP_VC_VSYNC_F2_VPOS);
+ writel_relaxed(((vc_format->hsync_end << 16) |
+ vc_format->hsync_start), VCAP_VC_HSYNC_HPOS);
+ writel_relaxed(((vc_format->f2_vsync_h_end << 16) |
+ vc_format->f2_vsync_h_start), VCAP_VC_VSYNC_F2_HPOS);
+ writel_relaxed(0x000033FF, VCAP_VC_BUF_CTRL);
+
+ rc = vc_format->hactive_end - vc_format->hactive_start;
+ if (vc_format->color_space)
+ rc *= 3;
+
+ writel_relaxed(rc, VCAP_VC_Y_STRIDE);
+ writel_relaxed(rc, VCAP_VC_C_STRIDE);
+
+ writel_relaxed(0x00010033 , VCAP_OFFSET(0x0898));
+ writel_relaxed(0x00010fff , VCAP_OFFSET(0x089c));
+ writel_relaxed(0x0a418820, VCAP_VC_IN_CTRL1);
+ writel_relaxed(0x16a4a0e6, VCAP_VC_IN_CTRL2);
+ writel_relaxed(0x2307b9ac, VCAP_VC_IN_CTRL3);
+ writel_relaxed(0x2f6ad272, VCAP_VC_IN_CTRL4);
+ writel_relaxed(0x00006b38, VCAP_VC_IN_CTRL5);
+
+ dprintk(2, "%s: Done VC configuration\n", __func__);
+
+ return 0;
+}
+
+int detect_vc(struct vcap_dev *dev)
+{
+ int result;
+ result = readl_relaxed(VCAP_HARDWARE_VERSION_REG);
+ dprintk(1, "Hardware version: %08x\n", result);
+ if (result != VCAP_HARDWARE_VERSION)
+ return -ENODEV;
+ return 0;
+}
+
+int deinit_vc(void)
+{
+ return 0;
+}
diff --git a/drivers/media/video/vcap_vc.h b/drivers/media/video/vcap_vc.h
new file mode 100644
index 0000000..e431038
--- /dev/null
+++ b/drivers/media/video/vcap_vc.h
@@ -0,0 +1,86 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef VCAP_VC_H
+#define VCAP_VC_H
+
+/* #define NEW_S_FMT */
+#include <linux/interrupt.h>
+
+#include <media/vcap_v4l2.h>
+extern struct v4l2_format_vc_ext vcap_vc_lut[];
+
+#define VCAP_HARDWARE_VERSION 0x10000000
+
+#define VCAP_BASE (dev->vcapbase)
+#define VCAP_OFFSET(off) (VCAP_BASE + off)
+
+#define VCAP_HARDWARE_VERSION_REG (VCAP_BASE + 0x0000)
+
+#define VCAP_SW_RESET_REQ (VCAP_BASE + 0x0024)
+#define VCAP_SW_RESET_STATUS (VCAP_BASE + 0x0028)
+
+#define VCAP_VC_CTRL (VCAP_BASE + 0x0800)
+#define VCAP_VC_NPL_CTRL (VCAP_BASE + 0x0804)
+#define VCAP_VC_POLARITY (VCAP_BASE + 0x081c)
+#define VCAP_VC_V_H_TOTAL (VCAP_BASE + 0x0820)
+#define VCAP_VC_H_ACTIVE (VCAP_BASE + 0x0824)
+#define VCAP_VC_V_ACTIVE (VCAP_BASE + 0x0828)
+#define VCAP_VC_V_ACTIVE_F2 (VCAP_BASE + 0x0830)
+#define VCAP_VC_VSYNC_VPOS (VCAP_BASE + 0x0834)
+#define VCAP_VC_VSYNC_F2_VPOS (VCAP_BASE + 0x0838)
+#define VCAP_VC_HSYNC_HPOS (VCAP_BASE + 0x0840)
+#define VCAP_VC_VSYNC_F2_HPOS (VCAP_BASE + 0x083c)
+#define VCAP_VC_BUF_CTRL (VCAP_BASE + 0x0848)
+
+#define VCAP_VC_Y_STRIDE (VCAP_BASE + 0x084c)
+#define VCAP_VC_C_STRIDE (VCAP_BASE + 0x0850)
+
+#define VCAP_VC_Y_ADDR_1 (VCAP_BASE + 0x0854)
+#define VCAP_VC_C_ADDR_1 (VCAP_BASE + 0x0858)
+#define VCAP_VC_Y_ADDR_2 (VCAP_BASE + 0x085c)
+#define VCAP_VC_C_ADDR_2 (VCAP_BASE + 0x0860)
+#define VCAP_VC_Y_ADDR_3 (VCAP_BASE + 0x0864)
+#define VCAP_VC_C_ADDR_3 (VCAP_BASE + 0x0868)
+#define VCAP_VC_Y_ADDR_4 (VCAP_BASE + 0x086c)
+#define VCAP_VC_C_ADDR_4 (VCAP_BASE + 0x0870)
+#define VCAP_VC_Y_ADDR_5 (VCAP_BASE + 0x0874)
+#define VCAP_VC_C_ADDR_5 (VCAP_BASE + 0x0878)
+#define VCAP_VC_Y_ADDR_6 (VCAP_BASE + 0x087c)
+#define VCAP_VC_C_ADDR_6 (VCAP_BASE + 0x0880)
+
+#define VCAP_VC_IN_CTRL1 (VCAP_BASE + 0x0808)
+#define VCAP_VC_IN_CTRL2 (VCAP_BASE + 0x080c)
+#define VCAP_VC_IN_CTRL3 (VCAP_BASE + 0x0810)
+#define VCAP_VC_IN_CTRL4 (VCAP_BASE + 0x0814)
+#define VCAP_VC_IN_CTRL5 (VCAP_BASE + 0x0818)
+
+#define VCAP_VC_INT_MASK (VCAP_BASE + 0x0884)
+#define VCAP_VC_INT_CLEAR (VCAP_BASE + 0x0888)
+#define VCAP_VC_INT_STATUS (VCAP_BASE + 0x088c)
+#define VCAP_VC_TIMESTAMP (VCAP_BASE + 0x0034)
+
+#define VC_BUFFER_WRITTEN (0x3 << 1)
+
+struct vc_reg_data {
+ unsigned data;
+ unsigned addr;
+};
+
+int vc_start_capture(struct vcap_client_data *c_data);
+int vc_hw_kick_off(struct vcap_client_data *c_data);
+void vc_stop_capture(struct vcap_client_data *c_data);
+int config_vc_format(struct vcap_client_data *c_data);
+int detect_vc(struct vcap_dev *dev);
+int deinit_vc(void);
+irqreturn_t vc_handler(struct vcap_dev *dev);
+#endif
diff --git a/drivers/mfd/pm8018-core.c b/drivers/mfd/pm8018-core.c
index 041815776..efe4fbf 100644
--- a/drivers/mfd/pm8018-core.c
+++ b/drivers/mfd/pm8018-core.c
@@ -529,8 +529,8 @@
static const char * const pm8018_rev_names[] = {
[PM8XXX_REVISION_8018_TEST] = "test",
[PM8XXX_REVISION_8018_1p0] = "1.0",
- [PM8XXX_REVISION_8018_1p1] = "1.1",
[PM8XXX_REVISION_8018_2p0] = "2.0",
+ [PM8XXX_REVISION_8018_2p1] = "2.1",
};
static int __devinit pm8018_probe(struct platform_device *pdev)
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index 0f41ba7..71fc3f7 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -831,6 +831,7 @@
[PM8XXX_REVISION_8921_1p1] = "1.1",
[PM8XXX_REVISION_8921_2p0] = "2.0",
[PM8XXX_REVISION_8921_3p0] = "3.0",
+ [PM8XXX_REVISION_8921_3p1] = "3.1",
};
static const char * const pm8922_rev_names[] = {
diff --git a/drivers/mfd/timpani-codec.c b/drivers/mfd/timpani-codec.c
index 4b9aef2..1e0a839 100644
--- a/drivers/mfd/timpani-codec.c
+++ b/drivers/mfd/timpani-codec.c
@@ -2756,6 +2756,7 @@
case TIMPANI_A_CDC_ANC2_CTL2:
case TIMPANI_A_CDC_ANC2_FF_FB_SHIFT:
case TIMPANI_A_AUXPGA_LR_GAIN:
+ case TIMPANI_A_CDC_ANC_INPUT_MUX:
return false;
default:
return true;
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
index 59a4283..2a25089 100644
--- a/drivers/mfd/wcd9xxx-core.c
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -59,8 +59,8 @@
dev_err(wcd9xxx->dev, "Codec read failed\n");
return ret;
} else
- dev_dbg(wcd9xxx->dev, "Read 0x%02x from R%d(0x%x)\n",
- *buf, reg, reg);
+ dev_dbg(wcd9xxx->dev, "Read 0x%02x from 0x%x\n",
+ *buf, reg);
return 0;
}
@@ -90,8 +90,8 @@
return -EINVAL;
}
- dev_dbg(wcd9xxx->dev, "Write %02x to R%d(0x%x)\n",
- *buf, reg, reg);
+ dev_dbg(wcd9xxx->dev, "Write %02x to 0x%x\n",
+ *buf, reg);
return wcd9xxx->write_dev(wcd9xxx, reg, bytes, src, interface_reg);
}
diff --git a/drivers/mfd/wcd9xxx-slimslave.c b/drivers/mfd/wcd9xxx-slimslave.c
index 6e23930..3b7bdc8 100644
--- a/drivers/mfd/wcd9xxx-slimslave.c
+++ b/drivers/mfd/wcd9xxx-slimslave.c
@@ -356,7 +356,7 @@
if (slave_port_id <=
SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID) {
payload_tx_0 = payload_tx_0 | (1 << slave_port_id);
- } else if (slave_port_id <
+ } else if (slave_port_id <=
SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID) {
payload_tx_1 = payload_tx_1 |
(1 <<
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 999bd0d..2c42bc7 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -33,6 +33,7 @@
#include <linux/clk.h>
#include <linux/qseecom.h>
#include <linux/freezer.h>
+#include <mach/board.h>
#include <mach/msm_bus.h>
#include <mach/msm_bus_board.h>
#include <mach/scm.h>
@@ -57,6 +58,8 @@
QSEOS_DEREGISTER_LISTENER,
QSEOS_CLIENT_SEND_DATA_COMMAND,
QSEOS_LISTENER_DATA_RSP_COMMAND,
+ QSEOS_LOAD_EXTERNAL_ELF_COMMAND,
+ QSEOS_UNLOAD_EXTERNAL_ELF_COMMAND,
QSEOS_CMD_MAX = 0xEFFFFFFF
};
@@ -66,6 +69,11 @@
QSEOS_RESULT_FAILURE = 0xFFFFFFFF
};
+enum qseecom_clk_definitions {
+ CLK_DFAB = 0,
+ CLK_SFPB,
+};
+
__packed struct qseecom_check_app_ireq {
uint32_t qsee_cmd_id;
char app_name[MAX_APP_NAME_SIZE];
@@ -135,9 +143,11 @@
static DEFINE_MUTEX(send_msg_lock);
static DEFINE_MUTEX(qsee_bw_mutex);
+static DEFINE_MUTEX(qsee_sfpb_bw_mutex);
static DEFINE_MUTEX(app_access_lock);
static int qsee_bw_count;
+static int qsee_sfpb_bw_count;
static struct clk *qseecom_bus_clk;
static uint32_t qsee_perf_client;
@@ -201,6 +211,10 @@
atomic_t ioctl_count;
};
+/* Function proto types */
+static int qsee_vote_for_clock(int32_t);
+static void qsee_disable_clock_vote(int32_t);
+
static int __qseecom_is_svc_unique(struct qseecom_dev_handle *data,
struct qseecom_register_listener_req *svc)
{
@@ -599,6 +613,10 @@
pr_err("copy_from_user failed\n");
return -EFAULT;
}
+ /* Vote for the SFPB clock */
+ ret = qsee_vote_for_clock(CLK_SFPB);
+ if (ret)
+ pr_warning("Unable to vote for SFPB clock");
req.qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND;
memcpy(req.app_name, load_img_req.img_name, MAX_APP_NAME_SIZE);
@@ -640,6 +658,7 @@
load_img_req.ifd_data_fd);
if (IS_ERR_OR_NULL(ihandle)) {
pr_err("Ion client could not retrieve the handle\n");
+ qsee_disable_clock_vote(CLK_SFPB);
return -ENOMEM;
}
@@ -665,6 +684,7 @@
pr_err("scm_call rsp.result is QSEOS_RESULT_FAILURE\n");
if (!IS_ERR_OR_NULL(ihandle))
ion_free(qseecom.ion_clnt, ihandle);
+ qsee_disable_clock_vote(CLK_SFPB);
return -EFAULT;
}
@@ -675,6 +695,7 @@
ret);
if (!IS_ERR_OR_NULL(ihandle))
ion_free(qseecom.ion_clnt, ihandle);
+ qsee_disable_clock_vote(CLK_SFPB);
return ret;
}
}
@@ -683,6 +704,7 @@
resp.result);
if (!IS_ERR_OR_NULL(ihandle))
ion_free(qseecom.ion_clnt, ihandle);
+ qsee_disable_clock_vote(CLK_SFPB);
return -EFAULT;
}
@@ -691,6 +713,7 @@
entry = kmalloc(sizeof(*entry), GFP_KERNEL);
if (!entry) {
pr_err("kmalloc failed\n");
+ qsee_disable_clock_vote(CLK_SFPB);
return -ENOMEM;
}
entry->app_id = app_id;
@@ -713,8 +736,10 @@
if (copy_to_user(argp, &load_img_req, sizeof(load_img_req))) {
pr_err("copy_to_user failed\n");
kzfree(entry);
+ qsee_disable_clock_vote(CLK_SFPB);
return -EFAULT;
}
+ qsee_disable_clock_vote(CLK_SFPB);
return 0;
}
@@ -1149,63 +1174,194 @@
return 0;
}
-static int qsee_vote_for_clock(void)
+static int qsee_vote_for_clock(int32_t clk_type)
{
int ret = 0;
if (!qsee_perf_client)
return ret;
- /* Check if the clk is valid */
- if (IS_ERR_OR_NULL(qseecom_bus_clk)) {
- pr_warn("qseecom bus clock is null or error");
- return -EINVAL;
- }
-
- mutex_lock(&qsee_bw_mutex);
- if (!qsee_bw_count) {
- ret = msm_bus_scale_client_update_request(
- qsee_perf_client, 1);
- if (ret) {
- pr_err("Bandwidth request failed (%d)\n", ret);
- } else {
- ret = clk_enable(qseecom_bus_clk);
- if (ret)
- pr_err("Clock enable failed\n");
+ switch (clk_type) {
+ case CLK_DFAB:
+ /* Check if the clk is valid */
+ if (IS_ERR_OR_NULL(qseecom_bus_clk)) {
+ pr_warn("qseecom bus clock is null or error");
+ return -EINVAL;
}
+ mutex_lock(&qsee_bw_mutex);
+ if (!qsee_bw_count) {
+ ret = msm_bus_scale_client_update_request(
+ qsee_perf_client, 1);
+ if (ret)
+ pr_err("DFAB Bandwidth req failed (%d)\n",
+ ret);
+ else
+ qsee_bw_count++;
+ }
+ mutex_unlock(&qsee_bw_mutex);
+ break;
+ case CLK_SFPB:
+ mutex_lock(&qsee_sfpb_bw_mutex);
+ if (!qsee_sfpb_bw_count) {
+ ret = msm_bus_scale_client_update_request(
+ qsee_perf_client, 2);
+ if (ret)
+ pr_err("SFPB Bandwidth req failed (%d)\n",
+ ret);
+ else
+ qsee_sfpb_bw_count++;
+ }
+ mutex_unlock(&qsee_sfpb_bw_mutex);
+ break;
+ default:
+ pr_err("Clock type not defined\n");
+ break;
}
- if (ret)
- msm_bus_scale_client_update_request(qsee_perf_client, 0);
- else
- qsee_bw_count++;
-
- mutex_unlock(&qsee_bw_mutex);
return ret;
}
-static void qsee_disable_clock_vote(void)
+static void qsee_disable_clock_vote(int32_t clk_type)
{
+ int32_t ret = 0;
if (!qsee_perf_client)
return;
- /* Check if the clk is valid */
- if (IS_ERR_OR_NULL(qseecom_bus_clk)) {
- pr_warn("qseecom bus clock is null or error");
- return;
+ switch (clk_type) {
+ case CLK_DFAB:
+ /* Check if the DFAB clk is valid */
+ if (IS_ERR_OR_NULL(qseecom_bus_clk)) {
+ pr_warn("qseecom bus clock is null or error");
+ return;
+ }
+ mutex_lock(&qsee_bw_mutex);
+ if (qsee_bw_count > 0) {
+ if (qsee_bw_count-- == 1) {
+ ret = msm_bus_scale_client_update_request(
+ qsee_perf_client, 0);
+ if (ret)
+ pr_err("SFPB Bandwidth req fail (%d)\n",
+ ret);
+ }
+ }
+ mutex_unlock(&qsee_bw_mutex);
+ break;
+ case CLK_SFPB:
+ mutex_lock(&qsee_sfpb_bw_mutex);
+ if (qsee_sfpb_bw_count > 0) {
+ if (qsee_sfpb_bw_count-- == 1) {
+ ret = msm_bus_scale_client_update_request(
+ qsee_perf_client, 0);
+ if (ret)
+ pr_err("SFPB Bandwidth req fail (%d)\n",
+ ret);
+ }
+ }
+ mutex_unlock(&qsee_sfpb_bw_mutex);
+ break;
+ default:
+ pr_err("Clock type not defined\n");
+ break;
}
- mutex_lock(&qsee_bw_mutex);
- if (qsee_bw_count > 0) {
- if (qsee_bw_count-- == 1) {
- msm_bus_scale_client_update_request(qsee_perf_client,
- 0);
- clk_disable(qseecom_bus_clk);
- }
- }
- mutex_unlock(&qsee_bw_mutex);
}
+static int qseecom_load_external_elf(struct qseecom_dev_handle *data,
+ void __user *argp)
+{
+ struct ion_handle *ihandle; /* Ion handle */
+ struct qseecom_load_img_req load_img_req;
+ int32_t ret;
+ ion_phys_addr_t pa = 0;
+ uint32_t len;
+ struct qseecom_load_app_ireq load_req;
+ struct qseecom_command_scm_resp resp;
+
+ /* Copy the relevant information needed for loading the image */
+ if (__copy_from_user(&load_img_req,
+ (void __user *)argp,
+ sizeof(struct qseecom_load_img_req))) {
+ pr_err("copy_from_user failed\n");
+ return -EFAULT;
+ }
+
+ /* Get the handle of the shared fd */
+ ihandle = ion_import_fd(qseecom.ion_clnt,
+ load_img_req.ifd_data_fd);
+ if (IS_ERR_OR_NULL(ihandle)) {
+ pr_err("Ion client could not retrieve the handle\n");
+ return -ENOMEM;
+ }
+
+ /* Get the physical address of the ION BUF */
+ ret = ion_phys(qseecom.ion_clnt, ihandle, &pa, &len);
+
+ /* Populate the structure for sending scm call to load image */
+ load_req.qsee_cmd_id = QSEOS_LOAD_EXTERNAL_ELF_COMMAND;
+ load_req.mdt_len = load_img_req.mdt_len;
+ load_req.img_len = load_img_req.img_len;
+ load_req.phy_addr = pa;
+
+ /* SCM_CALL to load the external elf */
+ ret = scm_call(SCM_SVC_TZSCHEDULER, 1, &load_req,
+ sizeof(struct qseecom_load_app_ireq),
+ &resp, sizeof(resp));
+ if (ret) {
+ pr_err("scm_call to unload failed : ret %d\n",
+ ret);
+ ret = -EFAULT;
+ }
+
+ if (resp.result == QSEOS_RESULT_INCOMPLETE) {
+ ret = __qseecom_process_incomplete_cmd(data, &resp);
+ if (ret)
+ pr_err("process_incomplete_cmd failed err: %d\n",
+ ret);
+ } else {
+ if (resp.result != QSEOS_RESULT_SUCCESS) {
+ pr_err("scm_call to load image failed resp.result =%d\n",
+ resp.result);
+ ret = -EFAULT;
+ }
+ }
+ /* Deallocate the handle */
+ if (!IS_ERR_OR_NULL(ihandle))
+ ion_free(qseecom.ion_clnt, ihandle);
+
+ return ret;
+}
+
+static int qseecom_unload_external_elf(struct qseecom_dev_handle *data)
+{
+ int ret = 0;
+ struct qseecom_command_scm_resp resp;
+ struct qseecom_unload_app_ireq req;
+
+ /* Populate the structure for sending scm call to unload image */
+ req.qsee_cmd_id = QSEOS_UNLOAD_EXTERNAL_ELF_COMMAND;
+ /* SCM_CALL to unload the external elf */
+ ret = scm_call(SCM_SVC_TZSCHEDULER, 1, &req,
+ sizeof(struct qseecom_unload_app_ireq),
+ &resp, sizeof(resp));
+ if (ret) {
+ pr_err("scm_call to unload failed : ret %d\n",
+ ret);
+ return -EFAULT;
+ }
+ if (resp.result == QSEOS_RESULT_INCOMPLETE) {
+ ret = __qseecom_process_incomplete_cmd(data, &resp);
+ if (ret)
+ pr_err("process_incomplete_cmd fail err: %d\n",
+ ret);
+ } else {
+ if (resp.result != QSEOS_RESULT_SUCCESS) {
+ pr_err("scm_call to unload image failed resp.result =%d\n",
+ resp.result);
+ ret = -EFAULT;
+ }
+ }
+ return ret;
+}
static long qseecom_ioctl(struct file *file, unsigned cmd,
unsigned long arg)
@@ -1319,18 +1475,50 @@
}
case QSEECOM_IOCTL_PERF_ENABLE_REQ:{
atomic_inc(&data->ioctl_count);
- ret = qsee_vote_for_clock();
+ ret = qsee_vote_for_clock(CLK_DFAB);
if (ret)
- pr_err("Failed to vote for clock%d\n", ret);
+ pr_err("Failed to vote for DFAB clock%d\n", ret);
atomic_dec(&data->ioctl_count);
break;
}
case QSEECOM_IOCTL_PERF_DISABLE_REQ:{
atomic_inc(&data->ioctl_count);
- qsee_disable_clock_vote();
+ qsee_disable_clock_vote(CLK_DFAB);
atomic_dec(&data->ioctl_count);
break;
}
+ case QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ: {
+ data->released = true;
+ if (qseecom.qseos_version == QSEOS_VERSION_13) {
+ pr_err("Loading External elf image unsupported in rev 0x13\n");
+ ret = -EINVAL;
+ break;
+ }
+ mutex_lock(&app_access_lock);
+ atomic_inc(&data->ioctl_count);
+ ret = qseecom_load_external_elf(data, argp);
+ atomic_dec(&data->ioctl_count);
+ mutex_unlock(&app_access_lock);
+ if (ret)
+ pr_err("failed load_external_elf request: %d\n", ret);
+ break;
+ }
+ case QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ: {
+ data->released = true;
+ if (qseecom.qseos_version == QSEOS_VERSION_13) {
+ pr_err("Unloading External elf image unsupported in rev 0x13\n");
+ ret = -EINVAL;
+ break;
+ }
+ mutex_lock(&app_access_lock);
+ atomic_inc(&data->ioctl_count);
+ ret = qseecom_unload_external_elf(data);
+ atomic_dec(&data->ioctl_count);
+ mutex_unlock(&app_access_lock);
+ if (ret)
+ pr_err("failed unload_app request: %d\n", ret);
+ break;
+ }
default:
return -EINVAL;
}
@@ -1397,41 +1585,11 @@
mutex_unlock(&pil_access_lock);
}
kfree(data);
- qsee_disable_clock_vote();
+ qsee_disable_clock_vote(CLK_DFAB);
return ret;
}
-/* qseecom bus scaling */
-static struct msm_bus_paths qsee_bw_table[] = {
- {
- .vectors = (struct msm_bus_vectors[]){
- {
- .src = MSM_BUS_MASTER_SPS,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- },
- },
- .num_paths = 1,
- },
- {
- .vectors = (struct msm_bus_vectors[]){
- {
- .src = MSM_BUS_MASTER_SPS,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ib = (492 * 8) * 1000000UL,
- .ab = (492 * 8) * 100000UL,
- },
- },
- .num_paths = 1,
- },
-};
-
-static struct msm_bus_scale_pdata qsee_bus_pdata = {
- .usecase = qsee_bw_table,
- .num_usecases = ARRAY_SIZE(qsee_bw_table),
- .name = "qsee",
-};
-
static const struct file_operations qseecom_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = qseecom_ioctl,
@@ -1439,11 +1597,12 @@
.release = qseecom_release
};
-static int __init qseecom_init(void)
+static int __devinit qseecom_probe(struct platform_device *pdev)
{
int rc;
struct device *class_dev;
char qsee_not_legacy = 0;
+ struct msm_bus_scale_pdata *qseecom_platform_support;
uint32_t system_call_id = QSEOS_CHECK_VERSION_CMD;
qsee_bw_count = 0;
@@ -1509,8 +1668,10 @@
}
/* register client for bus scaling */
+ qseecom_platform_support = (struct msm_bus_scale_pdata *)
+ pdev->dev.platform_data;
qsee_perf_client = msm_bus_scale_register_client(
- &qsee_bus_pdata);
+ qseecom_platform_support);
if (!qsee_perf_client) {
pr_err("Unable to register bus client\n");
} else {
@@ -1533,7 +1694,28 @@
return rc;
}
-static void __exit qseecom_exit(void)
+static int __devinit qseecom_remove(struct platform_device *pdev)
+{
+ if (pdev->dev.platform_data != NULL)
+ msm_bus_scale_unregister_client(qsee_perf_client);
+ return 0;
+};
+
+static struct platform_driver qseecom_plat_driver = {
+ .probe = qseecom_probe,
+ .remove = qseecom_remove,
+ .driver = {
+ .name = "qseecom",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __devinit qseecom_init(void)
+{
+ return platform_driver_register(&qseecom_plat_driver);
+}
+
+static void __devexit qseecom_exit(void)
{
clk_put(qseecom_bus_clk);
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index ef4ae57..ca86323 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -2084,18 +2084,36 @@
int mmc_detect_card_removed(struct mmc_host *host)
{
struct mmc_card *card = host->card;
+ int ret;
WARN_ON(!host->claimed);
+
+ if (!card)
+ return 1;
+
+ ret = mmc_card_removed(card);
/*
* The card will be considered unchanged unless we have been asked to
* detect a change or host requires polling to provide card detection.
*/
- if (card && !host->detect_change && !(host->caps & MMC_CAP_NEEDS_POLL))
- return mmc_card_removed(card);
+ if (!host->detect_change && !(host->caps & MMC_CAP_NEEDS_POLL) &&
+ !(host->caps2 & MMC_CAP2_DETECT_ON_ERR))
+ return ret;
host->detect_change = 0;
+ if (!ret) {
+ ret = _mmc_detect_card_removed(host);
+ if (ret && (host->caps2 & MMC_CAP2_DETECT_ON_ERR)) {
+ /*
+ * Schedule a detect work as soon as possible to let a
+ * rescan handle the card removal.
+ */
+ cancel_delayed_work(&host->detect);
+ mmc_detect_change(host, 0);
+ }
+ }
- return _mmc_detect_card_removed(host);
+ return ret;
}
EXPORT_SYMBOL(mmc_detect_card_removed);
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 122c891..e1a6ffd 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -54,6 +54,7 @@
#include <mach/clk.h>
#include <mach/dma.h>
#include <mach/sdio_al.h>
+#include <mach/mpm.h>
#include "msm_sdcc.h"
#include "msm_sdcc_dml.h"
@@ -68,6 +69,8 @@
#define SPS_SDCC_CONSUMER_PIPE_INDEX 2
#define SPS_CONS_PERIPHERAL 0
#define SPS_PROD_PERIPHERAL 1
+/* Use SPS only if transfer size is more than this macro */
+#define SPS_MIN_XFER_SIZE MCI_FIFOSIZE
#if defined(CONFIG_DEBUG_FS)
static void msmsdcc_dbg_createhost(struct msmsdcc_host *);
@@ -760,13 +763,32 @@
tasklet_schedule(&host->dma_tlet);
}
-static int msmsdcc_check_dma_op_req(struct mmc_data *data)
+static bool msmsdcc_is_dma_possible(struct msmsdcc_host *host,
+ struct mmc_data *data)
{
- if (((data->blksz * data->blocks) < MCI_FIFOSIZE) ||
- ((data->blksz * data->blocks) % MCI_FIFOSIZE))
- return -EINVAL;
- else
- return 0;
+ bool ret = true;
+ u32 xfer_size = data->blksz * data->blocks;
+
+ if (host->is_sps_mode) {
+ /*
+ * BAM Mode: Fall back on PIO if size is less
+ * than or equal to SPS_MIN_XFER_SIZE bytes.
+ */
+ if (xfer_size <= SPS_MIN_XFER_SIZE)
+ ret = false;
+ } else if (host->is_dma_mode) {
+ /*
+ * ADM Mode: Fall back on PIO if size is less than FIFO size
+ * or not integer multiple of FIFO size
+ */
+ if (xfer_size % MCI_FIFOSIZE)
+ ret = false;
+ } else {
+ /* PIO Mode */
+ ret = false;
+ }
+
+ return ret;
}
static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
@@ -1075,7 +1097,7 @@
if (host->curr.wait_for_auto_prog_done)
datactrl |= MCI_AUTO_PROG_DONE;
- if (!msmsdcc_check_dma_op_req(data)) {
+ if (msmsdcc_is_dma_possible(host, data)) {
if (host->is_dma_mode && !msmsdcc_config_dma(host, data)) {
datactrl |= MCI_DPSM_DMAENABLE;
} else if (host->is_sps_mode) {
@@ -2374,6 +2396,37 @@
return rc;
}
+static int msmsdcc_cfg_mpm_sdiowakeup(struct msmsdcc_host *host,
+ unsigned mode)
+{
+ int ret = 0;
+ unsigned int pin = host->plat->mpm_sdiowakeup_int;
+
+ if (!pin)
+ return 0;
+
+ switch (mode) {
+ case SDC_DAT1_DISABLE:
+ ret = msm_mpm_enable_pin(pin, 0);
+ break;
+ case SDC_DAT1_ENABLE:
+ ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
+ ret = msm_mpm_enable_pin(pin, 1);
+ break;
+ case SDC_DAT1_ENWAKE:
+ ret = msm_mpm_set_pin_wake(pin, 1);
+ break;
+ case SDC_DAT1_DISWAKE:
+ ret = msm_mpm_set_pin_wake(pin, 0);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
static u32 msmsdcc_setup_pwr(struct msmsdcc_host *host, struct mmc_ios *ios)
{
u32 pwr = 0;
@@ -2394,9 +2447,7 @@
switch (ios->power_mode) {
case MMC_POWER_OFF:
pwr = MCI_PWR_OFF;
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_DISABLE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_DISABLE);
/*
* As VDD pad rail is always on, set low voltage for VDD
* pad rail when slot is unused (when card is not present
@@ -2408,9 +2459,7 @@
case MMC_POWER_UP:
/* writing PWR_UP bit is redundant */
pwr = MCI_PWR_UP;
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_ENABLE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_ENABLE);
msmsdcc_set_vddp_high_vol(host);
msmsdcc_setup_pins(host, true);
@@ -2498,9 +2547,7 @@
writel_relaxed(MCI_SDIOINTMASK,
host->base + MMCIMASK0);
mb();
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_ENWAKE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_ENWAKE);
/* configure sdcc core interrupt as wakeup interrupt */
msmsdcc_enable_irq_wake(host);
} else {
@@ -2522,9 +2569,7 @@
*/
writel_relaxed(MCI_SDIOINTMASK, host->base + MMCICLEAR);
msmsdcc_sync_reg_wr(host);
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_DISWAKE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_DISWAKE);
msmsdcc_disable_irq_wake(host);
} else if (!host->sdio_wakeupirq_disabled) {
disable_irq_nosync(host->plat->sdiowakeup_irq);
@@ -3887,13 +3932,11 @@
/*
* This threshold controls when the BAM publish
* the descriptor size on the sideband interface.
- * SPS HW will only be used when
- * data transfer size > MCI_FIFOSIZE (64 bytes).
- * PIO mode will be used when
- * data transfer size < MCI_FIFOSIZE (64 bytes).
- * So set this thresold value to 64 bytes.
+ * SPS HW will be used for data transfer size even
+ * less than SDCC FIFO size. So let's set BAM summing
+ * thresold to SPS_MIN_XFER_SIZE bytes.
*/
- bam.summing_threshold = 64;
+ bam.summing_threshold = SPS_MIN_XFER_SIZE;
/* SPS driver wll handle the SDCC BAM IRQ */
bam.irq = (u32)host->bam_irqres->start;
bam.manage = SPS_BAM_MGR_LOCAL;
@@ -4074,7 +4117,7 @@
msmsdcc_print_regs("SDCC-CORE", host->base, 28);
if (host->curr.data) {
- if (msmsdcc_check_dma_op_req(host->curr.data))
+ if (!msmsdcc_is_dma_possible(host, host->curr.data))
pr_info("%s: PIO mode\n", mmc_hostname(host->mmc));
else if (host->is_dma_mode)
pr_info("%s: ADM mode: busy=%d, chnl=%d, crci=%d\n",
@@ -4552,7 +4595,7 @@
mmc->caps |= (MMC_CAP_SET_XPC_330 | MMC_CAP_SET_XPC_300 |
MMC_CAP_SET_XPC_180);
- mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
+ mmc->caps2 |= (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_DETECT_ON_ERR);
if (pdev->dev.of_node) {
if (of_get_property((&pdev->dev)->of_node,
"qcom,sdcc-hs200", NULL))
@@ -4623,7 +4666,7 @@
}
}
- if (plat->cfg_mpm_sdiowakeup) {
+ if (host->plat->mpm_sdiowakeup_int) {
wake_lock_init(&host->sdio_wlock, WAKE_LOCK_SUSPEND,
mmc_hostname(mmc));
}
@@ -5069,7 +5112,7 @@
* the SDIO work will be processed.
*/
if (mmc->card && mmc_card_sdio(mmc->card)) {
- if ((host->plat->cfg_mpm_sdiowakeup ||
+ if ((host->plat->mpm_sdiowakeup_int ||
host->plat->sdiowakeup_irq) &&
wake_lock_active(&host->sdio_wlock))
wake_lock_timeout(&host->sdio_wlock, 1);
diff --git a/drivers/net/msm_rmnet_sdio.c b/drivers/net/msm_rmnet_sdio.c
index 883c649..acdffd1 100644
--- a/drivers/net/msm_rmnet_sdio.c
+++ b/drivers/net/msm_rmnet_sdio.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -78,6 +78,7 @@
#endif
struct sk_buff *skb;
spinlock_t lock;
+ spinlock_t tx_queue_lock;
struct tasklet_struct tsklt;
u32 operation_mode; /* IOCTL specified mode (protocol, QoS header) */
uint8_t device_up;
@@ -361,6 +362,7 @@
static void sdio_write_done(void *dev, struct sk_buff *skb)
{
struct rmnet_private *p = netdev_priv(dev);
+ unsigned long flags;
if (skb)
dev_kfree_skb_any(skb);
@@ -368,12 +370,14 @@
if (!p->in_reset) {
DBG1("%s: write complete skb=%p\n", __func__, skb);
+ spin_lock_irqsave(&p->tx_queue_lock, flags);
if (netif_queue_stopped(dev) &&
msm_sdio_dmux_is_ch_low(p->ch_id)) {
DBG0("%s: Low WM hit, waking queue=%p\n",
__func__, skb);
netif_wake_queue(dev);
}
+ spin_unlock_irqrestore(&p->tx_queue_lock, flags);
} else {
DBG1("%s: write in reset skb=%p\n", __func__, skb);
}
@@ -454,6 +458,7 @@
static int rmnet_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct rmnet_private *p = netdev_priv(dev);
+ unsigned long flags;
if (netif_queue_stopped(dev)) {
pr_err("[%s]fatal: rmnet_xmit called when "
@@ -463,10 +468,12 @@
_rmnet_xmit(skb, dev);
+ spin_lock_irqsave(&p->tx_queue_lock, flags);
if (msm_sdio_dmux_is_ch_full(p->ch_id)) {
netif_stop_queue(dev);
DBG0("%s: High WM hit, stopping queue=%p\n", __func__, skb);
}
+ spin_unlock_irqrestore(&p->tx_queue_lock, flags);
return 0;
}
@@ -667,6 +674,7 @@
p->operation_mode = RMNET_MODE_LLP_ETH;
p->ch_id = n;
spin_lock_init(&p->lock);
+ spin_lock_init(&p->tx_queue_lock);
#ifdef CONFIG_MSM_RMNET_DEBUG
p->timeout_us = timeout_us;
p->wakeups_xmit = p->wakeups_rcv = 0;
diff --git a/drivers/net/usb/rmnet_usb_ctrl.c b/drivers/net/usb/rmnet_usb_ctrl.c
index 5bc8e1b..cfaf53b 100644
--- a/drivers/net/usb/rmnet_usb_ctrl.c
+++ b/drivers/net/usb/rmnet_usb_ctrl.c
@@ -453,19 +453,11 @@
if (dev->is_opened)
goto already_opened;
-ctrl_open:
- if (!is_dev_connected(dev)) {
- dev_dbg(dev->devicep, "%s: Device not connected\n",
- __func__);
- return -ENODEV;
- }
-
/*block open to get first response available from mdm*/
if (dev->mdm_wait_timeout && !dev->resp_available) {
retval = wait_event_interruptible_timeout(
dev->open_wait_queue,
- dev->resp_available ||
- !is_dev_connected(dev),
+ dev->resp_available,
msecs_to_jiffies(dev->mdm_wait_timeout *
1000));
if (retval == 0) {
@@ -477,8 +469,6 @@
__func__, dev->name);
return retval;
}
-
- goto ctrl_open;
}
if (!dev->resp_available) {
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index d24ce3f..8e9d753 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -1168,7 +1168,10 @@
return 0;
/* USB charging */
- val->intval = is_usb_chg_plugged_in(the_chip);
+ if (usb_target_ma < USB_WALL_THRESHOLD_MA)
+ val->intval = is_usb_chg_plugged_in(the_chip);
+ else
+ return 0;
break;
default:
return -EINVAL;
@@ -1717,6 +1720,23 @@
}
EXPORT_SYMBOL(pm8921_is_battery_charging);
+int pm8921_set_usb_power_supply_type(enum power_supply_type type)
+{
+ if (!the_chip) {
+ pr_err("called before init\n");
+ return -EINVAL;
+ }
+
+ if (type < POWER_SUPPLY_TYPE_USB)
+ return -EINVAL;
+
+ the_chip->usb_psy.type = type;
+ power_supply_changed(&the_chip->usb_psy);
+ power_supply_changed(&the_chip->dc_psy);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8921_set_usb_power_supply_type);
+
int pm8921_batt_temperature(void)
{
if (!the_chip) {
@@ -2191,7 +2211,7 @@
reg_loop = pm_chg_get_regulation_loop(chip);
pr_debug("reg_loop=0x%x usb_ma = %d\n", reg_loop, usb_ma);
- if (reg_loop & VIN_ACTIVE_BIT) {
+ if ((reg_loop & VIN_ACTIVE_BIT) && (usb_ma > USB_WALL_THRESHOLD_MA)) {
decrease_usb_ma_value(&usb_ma);
usb_target_ma = usb_ma;
/* end AICL here */
diff --git a/drivers/power/smb349.c b/drivers/power/smb349.c
index 148f188..4c07285 100644
--- a/drivers/power/smb349.c
+++ b/drivers/power/smb349.c
@@ -415,7 +415,7 @@
debugfs_remove_recursive(smb349_chg->dent);
}
-static int __devinit smb349_hwinit(struct smb349_struct *smb349_chg)
+static int smb349_hwinit(struct smb349_struct *smb349_chg)
{
int ret;
diff --git a/drivers/usb/gadget/f_mbim.c b/drivers/usb/gadget/f_mbim.c
index 21b393e..0598c7b 100644
--- a/drivers/usb/gadget/f_mbim.c
+++ b/drivers/usb/gadget/f_mbim.c
@@ -1048,7 +1048,7 @@
pr_info("control request: %02x.%02x v%04x i%04x l%d\n",
ctrl->bRequestType, ctrl->bRequest,
w_value, w_index, w_length);
- req->zero = 0;
+ req->zero = (value < w_length);
req->length = value;
value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
if (value < 0) {
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 420f417..2f7e250 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -45,6 +45,7 @@
#include <mach/clk.h>
#include <mach/msm_xo.h>
#include <mach/msm_bus.h>
+#include <mach/rpm-regulator.h>
#define MSM_USB_BASE (motg->regs)
#define DRIVER_NAME "msm_otg"
@@ -61,6 +62,7 @@
#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
+#define USB_PHY_VDD_DIG_VOL_NONE 0 /*uV */
#define USB_PHY_VDD_DIG_VOL_MIN 1045000 /* uV */
#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
@@ -104,53 +106,25 @@
#endif
}
-static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
-{
- int ret = 0;
+enum usb_vdd_value {
+ VDD_NONE = 0,
+ VDD_MIN,
+ VDD_MAX,
+ VDD_VAL_MAX,
+};
- if (init) {
- hsusb_vddcx = devm_regulator_get(motg->otg.dev, "HSUSB_VDDCX");
- if (IS_ERR(hsusb_vddcx)) {
- dev_err(motg->otg.dev, "unable to get hsusb vddcx\n");
- return PTR_ERR(hsusb_vddcx);
- }
-
- ret = regulator_set_voltage(hsusb_vddcx,
- USB_PHY_VDD_DIG_VOL_MIN,
- USB_PHY_VDD_DIG_VOL_MAX);
- if (ret) {
- dev_err(motg->otg.dev, "unable to set the voltage "
- "for hsusb vddcx\n");
- return ret;
- }
-
- ret = regulator_enable(hsusb_vddcx);
- if (ret) {
- regulator_set_voltage(hsusb_vddcx, 0,
- USB_PHY_VDD_DIG_VOL_MIN);
- dev_err(motg->otg.dev, "unable to enable the hsusb vddcx\n");
- return ret;
- }
-
- } else {
-
- ret = regulator_disable(hsusb_vddcx);
- if (ret) {
- dev_err(motg->otg.dev, "unable to disable hsusb vddcx\n");
- return ret;
- }
-
- ret = regulator_set_voltage(hsusb_vddcx, 0,
- USB_PHY_VDD_DIG_VOL_MIN);
- if (ret) {
- dev_err(motg->otg.dev, "unable to set the voltage"
- "for hsusb vddcx\n");
- return ret;
- }
- }
-
- return ret;
-}
+static const int vdd_val[VDD_TYPE_MAX][VDD_VAL_MAX] = {
+ { /* VDD_CX CORNER Voting */
+ [VDD_NONE] = RPM_VREG_CORNER_NONE,
+ [VDD_MIN] = RPM_VREG_CORNER_NOMINAL,
+ [VDD_MAX] = RPM_VREG_CORNER_HIGH,
+ },
+ { /* VDD_CX Voltage Voting */
+ [VDD_NONE] = USB_PHY_VDD_DIG_VOL_NONE,
+ [VDD_MIN] = USB_PHY_VDD_DIG_VOL_MIN,
+ [VDD_MAX] = USB_PHY_VDD_DIG_VOL_MAX,
+ },
+};
static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
{
@@ -198,15 +172,13 @@
#define USB_PHY_SUSP_DIG_VOL 500000
static int msm_hsusb_config_vddcx(int high)
{
- int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ struct msm_otg *motg = the_msm_otg;
+ enum usb_vdd_type vdd_type = motg->vdd_type;
+ int max_vol = vdd_val[vdd_type][VDD_MAX];
int min_vol;
int ret;
- if (high)
- min_vol = USB_PHY_VDD_DIG_VOL_MIN;
- else
- min_vol = USB_PHY_SUSP_DIG_VOL;
-
+ min_vol = vdd_val[vdd_type][!!high];
ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
if (ret) {
pr_err("%s: unable to set the voltage for regulator "
@@ -400,6 +372,9 @@
{
int ret;
+ if (IS_ERR(motg->clk))
+ return 0;
+
if (assert) {
ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
if (ret)
@@ -525,7 +500,8 @@
motg->reset_counter++;
}
- clk_prepare_enable(motg->clk);
+ if (!IS_ERR(motg->clk))
+ clk_prepare_enable(motg->clk);
ret = msm_otg_phy_reset(motg);
if (ret) {
dev_err(otg->dev, "phy_reset failed\n");
@@ -545,7 +521,8 @@
/* Ensure that RESET operation is completed before turning off clock */
mb();
- clk_disable_unprepare(motg->clk);
+ if (!IS_ERR(motg->clk))
+ clk_disable_unprepare(motg->clk);
if (pdata->otg_control == OTG_PHY_CONTROL) {
val = readl_relaxed(USB_OTGSC);
@@ -1008,6 +985,33 @@
}
#endif
+static int msm_otg_notify_chg_type(struct msm_otg *motg)
+{
+ static int charger_type;
+ /*
+ * TODO
+ * Unify OTG driver charger types and power supply charger types
+ */
+ if (charger_type == motg->chg_type)
+ return 0;
+
+ if (motg->chg_type == USB_SDP_CHARGER)
+ charger_type = POWER_SUPPLY_TYPE_USB;
+ else if (motg->chg_type == USB_CDP_CHARGER)
+ charger_type = POWER_SUPPLY_TYPE_USB_CDP;
+ else if (motg->chg_type == USB_DCP_CHARGER)
+ charger_type = POWER_SUPPLY_TYPE_USB_DCP;
+ else if ((motg->chg_type == USB_ACA_DOCK_CHARGER ||
+ motg->chg_type == USB_ACA_A_CHARGER ||
+ motg->chg_type == USB_ACA_B_CHARGER ||
+ motg->chg_type == USB_ACA_C_CHARGER))
+ charger_type = POWER_SUPPLY_TYPE_USB_ACA;
+ else
+ charger_type = POWER_SUPPLY_TYPE_BATTERY;
+
+ return pm8921_set_usb_power_supply_type(charger_type);
+}
+
static int msm_otg_notify_power_supply(struct msm_otg *motg, unsigned mA)
{
struct power_supply *psy;
@@ -1051,6 +1055,11 @@
mA > IDEV_ACA_CHG_LIMIT)
mA = IDEV_ACA_CHG_LIMIT;
+ if (msm_otg_notify_chg_type(motg))
+ dev_err(motg->otg.dev,
+ "Failed notifying %d charger type to PMIC\n",
+ motg->chg_type);
+
if (motg->cur_power == mA)
return;
@@ -1956,10 +1965,13 @@
clear_bit(B_SESS_VLD, &motg->inputs);
} else if (pdata->otg_control == OTG_PMIC_CONTROL) {
if (pdata->pmic_id_irq) {
+ unsigned long flags;
+ local_irq_save(flags);
if (irq_read_line(pdata->pmic_id_irq))
set_bit(ID, &motg->inputs);
else
clear_bit(ID, &motg->inputs);
+ local_irq_restore(flags);
}
/*
* VBUS initial state is reported after PMIC
@@ -2079,9 +2091,9 @@
} else {
pr_debug("chg_work cancel");
cancel_delayed_work_sync(&motg->chg_work);
- msm_otg_notify_charger(motg, 0);
motg->chg_state = USB_CHG_STATE_UNDEFINED;
motg->chg_type = USB_INVALID_CHARGER;
+ msm_otg_notify_charger(motg, 0);
msm_otg_reset(otg);
pm_runtime_put_noidle(otg->dev);
pm_runtime_suspend(otg->dev);
@@ -2120,11 +2132,11 @@
test_bit(ID_B, &motg->inputs) ||
!test_bit(B_SESS_VLD, &motg->inputs)) {
pr_debug("!id || id_a/b || !b_sess_vld\n");
+ motg->chg_state = USB_CHG_STATE_UNDEFINED;
+ motg->chg_type = USB_INVALID_CHARGER;
msm_otg_notify_charger(motg, 0);
srp_reqd = otg->gadget->otg_srp_reqd;
msm_otg_start_peripheral(otg, 0);
- motg->chg_state = USB_CHG_STATE_UNDEFINED;
- motg->chg_type = USB_INVALID_CHARGER;
if (test_bit(ID_B, &motg->inputs))
clear_bit(ID_B, &motg->inputs);
clear_bit(B_BUS_REQ, &motg->inputs);
@@ -3204,13 +3216,15 @@
if (IS_ERR(motg->phy_reset_clk))
dev_err(&pdev->dev, "failed to get phy_clk\n");
+ /*
+ * Targets on which link uses asynchronous reset methodology,
+ * free running clock is not required during the reset.
+ */
motg->clk = clk_get(&pdev->dev, "alt_core_clk");
- if (IS_ERR(motg->clk)) {
- dev_err(&pdev->dev, "failed to get alt_core_clk\n");
- ret = PTR_ERR(motg->clk);
- goto put_phy_reset_clk;
- }
- clk_set_rate(motg->clk, 60000000);
+ if (IS_ERR(motg->clk))
+ dev_dbg(&pdev->dev, "alt_core_clk is not present\n");
+ else
+ clk_set_rate(motg->clk, 60000000);
/* pm qos request to prevent apps idle power collapse */
if (motg->pdata->swfi_latency)
@@ -3228,7 +3242,7 @@
if (IS_ERR(motg->core_clk)) {
motg->core_clk = NULL;
dev_err(&pdev->dev, "failed to get core_clk\n");
- ret = PTR_ERR(motg->clk);
+ ret = PTR_ERR(motg->core_clk);
goto put_clk;
}
clk_set_rate(motg->core_clk, INT_MAX);
@@ -3279,22 +3293,33 @@
clk_prepare_enable(motg->pclk);
- ret = msm_hsusb_init_vddcx(motg, 1);
- if (ret) {
- dev_err(&pdev->dev, "hsusb vddcx init failed\n");
- goto devote_xo_handle;
+ motg->vdd_type = VDDCX_CORNER;
+ hsusb_vddcx = devm_regulator_get(motg->otg.dev, "hsusb_vdd_dig");
+ if (IS_ERR(hsusb_vddcx)) {
+ hsusb_vddcx = devm_regulator_get(motg->otg.dev, "HSUSB_VDDCX");
+ if (IS_ERR(hsusb_vddcx)) {
+ dev_err(motg->otg.dev, "unable to get hsusb vddcx\n");
+ goto devote_xo_handle;
+ }
+ motg->vdd_type = VDDCX;
}
ret = msm_hsusb_config_vddcx(1);
if (ret) {
dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
- goto free_init_vddcx;
+ goto devote_xo_handle;
+ }
+
+ ret = regulator_enable(hsusb_vddcx);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to enable the hsusb vddcx\n");
+ goto free_config_vddcx;
}
ret = msm_hsusb_ldo_init(motg, 1);
if (ret) {
dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
- goto free_init_vddcx;
+ goto free_hsusb_vddcx;
}
if (pdata->mhl_enable) {
@@ -3418,8 +3443,12 @@
msm_hsusb_ldo_enable(motg, 0);
free_ldo_init:
msm_hsusb_ldo_init(motg, 0);
-free_init_vddcx:
- msm_hsusb_init_vddcx(motg, 0);
+free_hsusb_vddcx:
+ regulator_disable(hsusb_vddcx);
+free_config_vddcx:
+ regulator_set_voltage(hsusb_vddcx,
+ vdd_val[motg->vdd_type][VDD_NONE],
+ vdd_val[motg->vdd_type][VDD_MAX]);
devote_xo_handle:
clk_disable_unprepare(motg->pclk);
msm_xo_mode_vote(motg->xo_handle, MSM_XO_MODE_OFF);
@@ -3432,8 +3461,8 @@
put_core_clk:
clk_put(motg->core_clk);
put_clk:
- clk_put(motg->clk);
-put_phy_reset_clk:
+ if (!IS_ERR(motg->clk))
+ clk_put(motg->clk);
if (!IS_ERR(motg->phy_reset_clk))
clk_put(motg->phy_reset_clk);
free_motg:
@@ -3493,7 +3522,10 @@
msm_xo_put(motg->xo_handle);
msm_hsusb_ldo_enable(motg, 0);
msm_hsusb_ldo_init(motg, 0);
- msm_hsusb_init_vddcx(motg, 0);
+ regulator_disable(hsusb_vddcx);
+ regulator_set_voltage(hsusb_vddcx,
+ vdd_val[motg->vdd_type][VDD_NONE],
+ vdd_val[motg->vdd_type][VDD_MAX]);
iounmap(motg->regs);
pm_runtime_set_suspended(&pdev->dev);
@@ -3501,7 +3533,8 @@
if (!IS_ERR(motg->phy_reset_clk))
clk_put(motg->phy_reset_clk);
clk_put(motg->pclk);
- clk_put(motg->clk);
+ if (!IS_ERR(motg->clk))
+ clk_put(motg->clk);
clk_put(motg->core_clk);
if (motg->pdata->swfi_latency)
diff --git a/drivers/video/msm/adv7520.c b/drivers/video/msm/adv7520.c
index df501dd..c0fb370 100644
--- a/drivers/video/msm/adv7520.c
+++ b/drivers/video/msm/adv7520.c
@@ -344,7 +344,7 @@
{
struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
- clk_enable(tv_enc_clk);
+ clk_prepare_enable(tv_enc_clk);
external_common_state->dev = &pdev->dev;
if (mfd != NULL) {
DEV_INFO("adv7520_power: ON (%dx%d %d)\n",
@@ -378,7 +378,7 @@
adv7520_chip_off();
wake_unlock(&wlock);
adv7520_comm_power(0, 1);
- clk_disable(tv_enc_clk);
+ clk_disable_unprepare(tv_enc_clk);
return 0;
}
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index cf08f40..375f82f 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -4074,30 +4074,30 @@
DEV_DBG("HDMI Clk: %s\n", on ? "Enable" : "Disable");
if (on) {
- rc = clk_enable(hdmi_msm_state->hdmi_app_clk);
+ rc = clk_prepare_enable(hdmi_msm_state->hdmi_app_clk);
if (rc) {
DEV_ERR("'hdmi_app_clk' clock enable failed, rc=%d\n",
rc);
return rc;
}
- rc = clk_enable(hdmi_msm_state->hdmi_m_pclk);
+ rc = clk_prepare_enable(hdmi_msm_state->hdmi_m_pclk);
if (rc) {
DEV_ERR("'hdmi_m_pclk' clock enable failed, rc=%d\n",
rc);
return rc;
}
- rc = clk_enable(hdmi_msm_state->hdmi_s_pclk);
+ rc = clk_prepare_enable(hdmi_msm_state->hdmi_s_pclk);
if (rc) {
DEV_ERR("'hdmi_s_pclk' clock enable failed, rc=%d\n",
rc);
return rc;
}
} else {
- clk_disable(hdmi_msm_state->hdmi_app_clk);
- clk_disable(hdmi_msm_state->hdmi_m_pclk);
- clk_disable(hdmi_msm_state->hdmi_s_pclk);
+ clk_disable_unprepare(hdmi_msm_state->hdmi_app_clk);
+ clk_disable_unprepare(hdmi_msm_state->hdmi_m_pclk);
+ clk_disable_unprepare(hdmi_msm_state->hdmi_s_pclk);
}
return 0;
@@ -4200,7 +4200,7 @@
{
uint32 hpd_ctrl;
- clk_enable(hdmi_msm_state->hdmi_app_clk);
+ clk_prepare_enable(hdmi_msm_state->hdmi_app_clk);
hdmi_msm_state->pd->core_power(1, 1);
hdmi_msm_state->pd->enable_5v(1);
hdmi_msm_set_mode(FALSE);
@@ -4226,7 +4226,7 @@
hdmi_msm_set_mode(FALSE);
hdmi_msm_state->pd->core_power(0, 1);
hdmi_msm_state->pd->enable_5v(0);
- clk_disable(hdmi_msm_state->hdmi_app_clk);
+ clk_disable_unprepare(hdmi_msm_state->hdmi_app_clk);
}
static void hdmi_msm_hpd_off(void)
diff --git a/drivers/video/msm/lcdc.c b/drivers/video/msm/lcdc.c
index 9709a07..863d59d 100644
--- a/drivers/video/msm/lcdc.c
+++ b/drivers/video/msm/lcdc.c
@@ -65,8 +65,8 @@
mfd = platform_get_drvdata(pdev);
ret = panel_next_off(pdev);
- clk_disable(pixel_mdp_clk);
- clk_disable(pixel_lcdc_clk);
+ clk_disable_unprepare(pixel_mdp_clk);
+ clk_disable_unprepare(pixel_lcdc_clk);
if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
lcdc_pdata->lcdc_power_save(0);
@@ -81,7 +81,7 @@
pr_err("%s: ebi1_lcdc_clk set rate failed\n",
__func__);
}
- clk_disable(mfd->ebi1_clk);
+ clk_disable_unprepare(mfd->ebi1_clk);
}
#else
mdp_bus_scale_update_request(0);
@@ -122,7 +122,7 @@
} else {
clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000);
}
- clk_enable(mfd->ebi1_clk);
+ clk_prepare_enable(mfd->ebi1_clk);
}
#endif
@@ -137,8 +137,8 @@
goto out;
}
- clk_enable(pixel_mdp_clk);
- clk_enable(pixel_lcdc_clk);
+ clk_prepare_enable(pixel_mdp_clk);
+ clk_prepare_enable(pixel_lcdc_clk);
if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
lcdc_pdata->lcdc_power_save(1);
diff --git a/drivers/video/msm/lvds.c b/drivers/video/msm/lvds.c
index 1a7619d..8f1e510 100644
--- a/drivers/video/msm/lvds.c
+++ b/drivers/video/msm/lvds.c
@@ -208,7 +208,7 @@
ret = panel_next_off(pdev);
if (lvds_clk)
- clk_disable(lvds_clk);
+ clk_disable_unprepare(lvds_clk);
if (lvds_pdata && lvds_pdata->lcdc_power_save)
lvds_pdata->lcdc_power_save(0);
@@ -249,7 +249,7 @@
__func__, mfd->fbi->var.pixclock);
goto out;
}
- clk_enable(lvds_clk);
+ clk_prepare_enable(lvds_clk);
}
if (lvds_pdata && lvds_pdata->lcdc_power_save)
diff --git a/drivers/video/msm/mddi.c b/drivers/video/msm/mddi.c
index 7f5e125..1154913 100644
--- a/drivers/video/msm/mddi.c
+++ b/drivers/video/msm/mddi.c
@@ -156,11 +156,11 @@
}
if (mddi_clk) {
- clk_disable(mddi_clk);
+ clk_disable_unprepare(mddi_clk);
pmdh_clk_status = 0;
}
if (mddi_pclk)
- clk_disable(mddi_pclk);
+ clk_disable_unprepare(mddi_pclk);
mutex_unlock(&pmdh_clk_lock);
}
@@ -173,11 +173,11 @@
}
if (mddi_clk) {
- clk_enable(mddi_clk);
+ clk_prepare_enable(mddi_clk);
pmdh_clk_status = 1;
}
if (mddi_pclk)
- clk_enable(mddi_pclk);
+ clk_prepare_enable(mddi_pclk);
if (int_mddi_pri_flag && !irq_enabled) {
enable_irq(INT_MDDI_PRI);
@@ -216,7 +216,7 @@
mdp_bus_scale_update_request(0);
#else
if (mfd->ebi1_clk)
- clk_disable(mfd->ebi1_clk);
+ clk_disable_unprepare(mfd->ebi1_clk);
#endif
pm_runtime_put(&pdev->dev);
return ret;
@@ -279,7 +279,7 @@
mdp_bus_scale_update_request(2);
#else
if (mfd->ebi1_clk)
- clk_enable(mfd->ebi1_clk);
+ clk_prepare_enable(mfd->ebi1_clk);
#endif
ret = panel_next_on(pdev);
diff --git a/drivers/video/msm/mddi_ext.c b/drivers/video/msm/mddi_ext.c
index 09cc201..dc79fed 100644
--- a/drivers/video/msm/mddi_ext.c
+++ b/drivers/video/msm/mddi_ext.c
@@ -155,13 +155,13 @@
pr_err("can't find emdh_clk\n");
return PTR_ERR(mddi_ext_clk);
}
- clk_enable(mddi_ext_clk);
+ clk_prepare_enable(mddi_ext_clk);
mddi_ext_pclk = clk_get(&pdev->dev, "iface_clk");
if (IS_ERR(mddi_ext_pclk))
mddi_ext_pclk = NULL;
else
- clk_enable(mddi_ext_pclk);
+ clk_prepare_enable(mddi_ext_pclk);
size = resource_size(&pdev->resource[0]);
msm_emdh_base = ioremap(pdev->resource[0].start, size);
@@ -278,9 +278,9 @@
mddi_ext_is_in_suspend = 1;
- clk_disable(mddi_ext_clk);
+ clk_disable_unprepare(mddi_ext_clk);
if (mddi_ext_pclk)
- clk_disable(mddi_ext_pclk);
+ clk_disable_unprepare(mddi_ext_pclk);
disable_irq(INT_MDDI_EXT);
@@ -299,9 +299,9 @@
mddi_ext_is_in_suspend = 0;
enable_irq(INT_MDDI_EXT);
- clk_enable(mddi_ext_clk);
+ clk_prepare_enable(mddi_ext_clk);
if (mddi_ext_pclk)
- clk_enable(mddi_ext_pclk);
+ clk_prepare_enable(mddi_ext_pclk);
return 0;
}
@@ -343,12 +343,6 @@
ret = mddi_ext_register_driver();
if (ret) {
- clk_disable(mddi_ext_clk);
- clk_put(mddi_ext_clk);
- if (mddi_ext_pclk) {
- clk_disable(mddi_ext_pclk);
- clk_put(mddi_ext_pclk);
- }
printk(KERN_ERR "mddi_ext_register_driver() failed!\n");
return ret;
}
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index a339600..e749a44 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -1493,7 +1493,7 @@
}
if (mdp_clk != NULL) {
mdp_clk_rate = clk_get_rate(mdp_clk);
- clk_disable(mdp_clk);
+ clk_disable_unprepare(mdp_clk);
if (mdp_hw_revision <=
MDP4_REVISION_V2_1 &&
mdp_clk_rate > 122880000) {
@@ -1503,11 +1503,11 @@
MSM_FB_DEBUG("MDP CLK OFF\n");
}
if (mdp_pclk != NULL) {
- clk_disable(mdp_pclk);
+ clk_disable_unprepare(mdp_pclk);
MSM_FB_DEBUG("MDP PCLK OFF\n");
}
if (mdp_lut_clk != NULL)
- clk_disable(mdp_lut_clk);
+ clk_disable_unprepare(mdp_lut_clk);
} else {
/* send workqueue to turn off mdp power */
queue_delayed_work(mdp_pipe_ctrl_wq,
@@ -1531,15 +1531,15 @@
clk_set_rate(mdp_clk,
mdp_clk_rate);
}
- clk_enable(mdp_clk);
+ clk_prepare_enable(mdp_clk);
MSM_FB_DEBUG("MDP CLK ON\n");
}
if (mdp_pclk != NULL) {
- clk_enable(mdp_pclk);
+ clk_prepare_enable(mdp_pclk);
MSM_FB_DEBUG("MDP PCLK ON\n");
}
if (mdp_lut_clk != NULL)
- clk_enable(mdp_lut_clk);
+ clk_prepare_enable(mdp_lut_clk);
mdp_vsync_clk_enable();
}
up(&mdp_pipe_ctrl_mutex);
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 562c0c8..d765744 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -467,6 +467,14 @@
{
/* empty */
}
+static inline void mdp4_dtv_overlay_blt_start(struct msm_fb_data_type *mfd)
+{
+ return;
+}
+static inline void mdp4_dtv_overlay_blt_stop(struct msm_fb_data_type *mfd)
+{
+ return;
+}
#endif
void mdp4_dtv_set_black_screen(void);
@@ -529,7 +537,7 @@
void mdp4_dma_s_done_mddi(void);
void mdp4_dma_p_done_mddi(void);
void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma);
-void mdp4_dma_p_done_dsi_video(void);
+void mdp4_dma_p_done_dsi_video(struct mdp_dma_data *dma);
void mdp4_dma_p_done_lcdc(void);
void mdp4_overlay1_done_dtv(void);
void mdp4_overlay1_done_atv(void);
diff --git a/drivers/video/msm/mdp4_dtv.c b/drivers/video/msm/mdp4_dtv.c
index 9f2cf8c..f7e74e6 100644
--- a/drivers/video/msm/mdp4_dtv.c
+++ b/drivers/video/msm/mdp4_dtv.c
@@ -91,9 +91,9 @@
pr_info("%s\n", __func__);
- clk_disable(hdmi_clk);
+ clk_disable_unprepare(hdmi_clk);
if (mdp_tv_clk)
- clk_disable(mdp_tv_clk);
+ clk_disable_unprepare(mdp_tv_clk);
if (dtv_pdata && dtv_pdata->lcdc_power_save)
dtv_pdata->lcdc_power_save(0);
@@ -106,7 +106,7 @@
0);
#else
if (ebi1_clk)
- clk_disable(ebi1_clk);
+ clk_disable_unprepare(ebi1_clk);
#endif
mdp4_extn_disp = 0;
return ret;
@@ -134,7 +134,7 @@
#else
if (ebi1_clk) {
clk_set_rate(ebi1_clk, pm_qos_rate * 1000);
- clk_enable(ebi1_clk);
+ clk_prepare_enable(ebi1_clk);
}
#endif
mfd = platform_get_drvdata(pdev);
@@ -150,13 +150,13 @@
pr_info("%s: tv_src_clk=%dkHz, pm_qos_rate=%ldkHz, [%d]\n", __func__,
mfd->fbi->var.pixclock/1000, pm_qos_rate, ret);
- clk_enable(hdmi_clk);
+ clk_prepare_enable(hdmi_clk);
clk_reset(hdmi_clk, CLK_RESET_ASSERT);
udelay(20);
clk_reset(hdmi_clk, CLK_RESET_DEASSERT);
if (mdp_tv_clk)
- clk_enable(mdp_tv_clk);
+ clk_prepare_enable(mdp_tv_clk);
if (dtv_pdata && dtv_pdata->lcdc_power_save)
dtv_pdata->lcdc_power_save(1);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index f1f846f..b40d88a 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -847,6 +847,8 @@
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CRCB_H1V1:
case MDP_Y_CBCR_H1V1:
+ case MDP_YCRCB_H1V1:
+ case MDP_YCBCR_H1V1:
return OVERLAY_TYPE_VIDEO;
default:
mdp4_stat.err_format++;
@@ -891,9 +893,9 @@
pipe->unpack_tight = 1;
pipe->unpack_align_msb = 0;
pipe->unpack_count = 2;
- pipe->element2 = C2_R_Cr; /* R */
+ pipe->element2 = C1_B_Cb; /* B */
pipe->element1 = C0_G_Y; /* G */
- pipe->element0 = C1_B_Cb; /* B */
+ pipe->element0 = C2_R_Cr; /* R */
pipe->bpp = 3; /* 3 bpp */
break;
case MDP_BGR_565:
@@ -923,10 +925,10 @@
pipe->unpack_tight = 1;
pipe->unpack_align_msb = 0;
pipe->unpack_count = 3;
- pipe->element3 = C3_ALPHA; /* alpha */
- pipe->element2 = C2_R_Cr; /* R */
- pipe->element1 = C0_G_Y; /* G */
- pipe->element0 = C1_B_Cb; /* B */
+ pipe->element3 = C1_B_Cb; /* B */
+ pipe->element2 = C0_G_Y; /* G */
+ pipe->element1 = C2_R_Cr; /* R */
+ pipe->element0 = C3_ALPHA; /* alpha */
pipe->bpp = 4; /* 4 bpp */
break;
case MDP_ARGB_8888:
@@ -940,10 +942,10 @@
pipe->unpack_tight = 1;
pipe->unpack_align_msb = 0;
pipe->unpack_count = 3;
- pipe->element3 = C3_ALPHA; /* alpha */
- pipe->element2 = C2_R_Cr; /* R */
- pipe->element1 = C0_G_Y; /* G */
- pipe->element0 = C1_B_Cb; /* B */
+ pipe->element3 = C1_B_Cb; /* B */
+ pipe->element2 = C0_G_Y; /* G */
+ pipe->element1 = C2_R_Cr; /* R */
+ pipe->element0 = C3_ALPHA; /* alpha */
pipe->bpp = 4; /* 4 bpp */
break;
case MDP_RGBA_8888:
@@ -1031,37 +1033,35 @@
pipe->unpack_tight = 1;
pipe->unpack_align_msb = 0;
pipe->unpack_count = 1; /* 2 */
- pipe->element3 = C0_G_Y; /* not used */
- pipe->element2 = C0_G_Y; /* not used */
if (pipe->src_format == MDP_Y_CRCB_H2V1) {
- pipe->element1 = C2_R_Cr; /* R */
- pipe->element0 = C1_B_Cb; /* B */
+ pipe->element1 = C1_B_Cb;
+ pipe->element0 = C2_R_Cr;
pipe->chroma_sample = MDP4_CHROMA_H2V1;
} else if (pipe->src_format == MDP_Y_CRCB_H1V1) {
- pipe->element1 = C2_R_Cr; /* R */
- pipe->element0 = C1_B_Cb; /* B */
+ pipe->element1 = C1_B_Cb;
+ pipe->element0 = C2_R_Cr;
if (pipe->src_width > YUV_444_MAX_WIDTH)
pipe->chroma_sample = MDP4_CHROMA_H1V2;
else
pipe->chroma_sample = MDP4_CHROMA_RGB;
} else if (pipe->src_format == MDP_Y_CBCR_H2V1) {
- pipe->element1 = C1_B_Cb; /* B */
- pipe->element0 = C2_R_Cr; /* R */
+ pipe->element1 = C2_R_Cr;
+ pipe->element0 = C1_B_Cb;
pipe->chroma_sample = MDP4_CHROMA_H2V1;
} else if (pipe->src_format == MDP_Y_CBCR_H1V1) {
- pipe->element1 = C1_B_Cb; /* B */
- pipe->element0 = C2_R_Cr; /* R */
+ pipe->element1 = C2_R_Cr;
+ pipe->element0 = C1_B_Cb;
if (pipe->src_width > YUV_444_MAX_WIDTH)
pipe->chroma_sample = MDP4_CHROMA_H1V2;
else
pipe->chroma_sample = MDP4_CHROMA_RGB;
} else if (pipe->src_format == MDP_Y_CRCB_H2V2) {
- pipe->element1 = C2_R_Cr; /* R */
- pipe->element0 = C1_B_Cb; /* B */
+ pipe->element1 = C1_B_Cb;
+ pipe->element0 = C2_R_Cr;
pipe->chroma_sample = MDP4_CHROMA_420;
} else if (pipe->src_format == MDP_Y_CBCR_H2V2) {
- pipe->element1 = C1_B_Cb; /* B */
- pipe->element0 = C2_R_Cr; /* R */
+ pipe->element1 = C2_R_Cr;
+ pipe->element0 = C1_B_Cb;
pipe->chroma_sample = MDP4_CHROMA_420;
}
pipe->bpp = 2; /* 2 bpp */
@@ -1078,16 +1078,14 @@
pipe->unpack_tight = 1;
pipe->unpack_align_msb = 0;
pipe->unpack_count = 1; /* 2 */
- pipe->element3 = C0_G_Y; /* not used */
- pipe->element2 = C0_G_Y; /* not used */
if (pipe->src_format == MDP_Y_CRCB_H2V2_TILE) {
- pipe->element1 = C2_R_Cr; /* R */
- pipe->element0 = C1_B_Cb; /* B */
- pipe->chroma_sample = MDP4_CHROMA_420;
- } else if (pipe->src_format == MDP_Y_CBCR_H2V2_TILE) {
pipe->element1 = C1_B_Cb; /* B */
pipe->element0 = C2_R_Cr; /* R */
pipe->chroma_sample = MDP4_CHROMA_420;
+ } else if (pipe->src_format == MDP_Y_CBCR_H2V2_TILE) {
+ pipe->element1 = C2_R_Cr; /* R */
+ pipe->element0 = C1_B_Cb; /* B */
+ pipe->chroma_sample = MDP4_CHROMA_420;
}
pipe->bpp = 2; /* 2 bpp */
break;
@@ -1104,6 +1102,28 @@
pipe->chroma_sample = MDP4_CHROMA_420;
pipe->bpp = 2; /* 2 bpp */
break;
+ case MDP_YCBCR_H1V1:
+ case MDP_YCRCB_H1V1:
+ pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
+ pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
+ pipe->a_bit = 0;
+ pipe->r_bit = 3; /* R, 8 bits */
+ pipe->b_bit = 3; /* B, 8 bits */
+ pipe->g_bit = 3; /* G, 8 bits */
+ pipe->alpha_enable = 0;
+ pipe->unpack_tight = 1;
+ pipe->unpack_align_msb = 0;
+ pipe->unpack_count = 2;
+ pipe->element0 = C0_G_Y; /* G */
+ if (pipe->src_format == MDP_YCRCB_H1V1) {
+ pipe->element1 = C2_R_Cr; /* R */
+ pipe->element2 = C1_B_Cb; /* B */
+ } else {
+ pipe->element1 = C1_B_Cb; /* B */
+ pipe->element2 = C2_R_Cr; /* R */
+ }
+ pipe->bpp = 3; /* 3 bpp */
+ break;
default:
/* not likely */
mdp4_stat.err_format++;
@@ -1180,6 +1200,7 @@
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CBCR_H2V2:
case MDP_Y_CBCR_H2V1:
+ case MDP_YCBCR_H1V1:
b_start = 8;
g_start = 16;
r_start = 0;
@@ -1193,6 +1214,7 @@
case MDP_Y_CRCB_H2V1:
case MDP_Y_CRCB_H1V1:
case MDP_Y_CBCR_H1V1:
+ case MDP_YCRCB_H1V1:
b_start = 0;
g_start = 16;
r_start = 8;
@@ -2532,10 +2554,7 @@
#endif
}
- if (mfd->mdp_rev >= MDP_REV_42 && !mfd->use_ov0_blt &&
- (pipe->mixer_num == MDP4_MIXER0 || hdmi_prim_display)) {
- ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = NULL;
- } else if (mfd->mdp_rev == MDP_REV_41 &&
+ if (mfd->mdp_rev >= MDP_REV_41 &&
mdp4_overlay_is_rgb_type(pipe->src_format) &&
!mfd->use_ov0_blt && (pipe->mixer_num == MDP4_MIXER0 ||
hdmi_prim_display)) {
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index d120071..8ab12590 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -40,6 +40,7 @@
static struct mdp4_overlay_pipe *dsi_pipe;
static struct completion dsi_video_comp;
+static int blt_cfg_changed;
static cmd_fxn_t display_on;
@@ -550,8 +551,26 @@
/*
* mdp4_dma_p_done_dsi_video: called from isr
*/
-void mdp4_dma_p_done_dsi_video(void)
+void mdp4_dma_p_done_dsi_video(struct mdp_dma_data *dma)
{
+ if (blt_cfg_changed) {
+ mdp_is_in_isr = TRUE;
+ mdp4_overlayproc_cfg(dsi_pipe);
+ mdp4_overlay_dmap_xy(dsi_pipe);
+ mdp_is_in_isr = FALSE;
+ if (dsi_pipe->blt_addr) {
+ mdp4_dsi_video_blt_ov_update(dsi_pipe);
+ dsi_pipe->ov_cnt++;
+ outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
+ mdp_intr_mask |= INTR_OVERLAY0_DONE;
+ outp32(MDP_INTR_ENABLE, mdp_intr_mask);
+ dma->busy = TRUE;
+ mdp_enable_irq(MDP_OVERLAY0_TERM);
+ /* kickoff overlay engine */
+ outpdw(MDP_BASE + 0x0004, 0);
+ }
+ blt_cfg_changed = 0;
+ }
complete_all(&dsi_video_comp);
}
@@ -573,30 +592,6 @@
complete(&dma->comp);
}
-static void mdp4_overlay_dsi_video_prefill(struct msm_fb_data_type *mfd)
-{
- unsigned long flag;
-
- if (dsi_pipe->blt_addr) {
- mdp4_overlay_dsi_video_dma_busy_wait(mfd);
-
- mdp4_dsi_video_blt_ov_update(dsi_pipe);
- dsi_pipe->ov_cnt++;
-
- spin_lock_irqsave(&mdp_spin_lock, flag);
- outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
- mdp_intr_mask |= INTR_OVERLAY0_DONE;
- outp32(MDP_INTR_ENABLE, mdp_intr_mask);
- mdp_enable_irq(MDP_OVERLAY0_TERM);
- mfd->dma->busy = TRUE;
- mb(); /* make sure all registers updated */
- spin_unlock_irqrestore(&mdp_spin_lock, flag);
- outpdw(MDP_BASE + 0x0004, 0); /* kickoff overlay engine */
- mdp4_stat.kickoff_ov0++;
- mb();
- }
-}
-
/*
* make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
* has enough space h * w * 3 * 2
@@ -626,12 +621,18 @@
dsi_pipe->blt_addr = 0;
change++;
}
+
+ if (!change) {
+ spin_unlock_irqrestore(&mdp_spin_lock, flag);
+ return;
+ }
+
pr_debug("%s: enable=%d blt_addr=%x\n", __func__,
- enable, (int)dsi_pipe->blt_addr);
+ enable, (int)dsi_pipe->blt_addr);
+ blt_cfg_changed = 1;
+
spin_unlock_irqrestore(&mdp_spin_lock, flag);
- if (!change)
- return;
/*
* may need mutex here to sync with whom dsiable
@@ -641,24 +642,10 @@
data &= 0x01;
if (data) { /* timing generator enabled */
mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
- msleep(20); /* make sure last frame is finished */
- mipi_dsi_controller_cfg(0);
+ mdp4_overlay_dsi_video_wait4event(mfd, INTR_PRIMARY_VSYNC);
}
- mdp4_overlayproc_cfg(dsi_pipe);
- mdp4_overlay_dmap_xy(dsi_pipe);
- if (data) { /* timing generator enabled */
- if (dsi_pipe->blt_addr) {
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
- mdp4_overlay_dsi_video_prefill(mfd);
- mdp4_overlay_dsi_video_prefill(mfd);
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
- }
- mipi_dsi_sw_reset();
- mipi_dsi_controller_cfg(1);
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
- }
+
}
int mdp4_dsi_video_overlay_blt_offset(struct msm_fb_data_type *mfd,
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index 3aa848c..9f8b5c6 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -515,7 +515,7 @@
mdp_intr_mask &= ~INTR_DMA_P_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
dma->waiting = FALSE;
- mdp4_dma_p_done_dsi_video();
+ mdp4_dma_p_done_dsi_video(dma);
spin_unlock(&mdp_spin_lock);
} else if (panel & MDP4_PANEL_DSI_CMD) {
mdp4_dma_p_done_dsi(dma);
diff --git a/drivers/video/msm/mdp_lcdc.c b/drivers/video/msm/mdp_lcdc.c
index be8d39d..62b0975 100644
--- a/drivers/video/msm/mdp_lcdc.c
+++ b/drivers/video/msm/mdp_lcdc.c
@@ -91,9 +91,9 @@
pr_info("%s: suspending\n", __func__);
mdp_writel(lcdc->mdp, 0, MDP_LCDC_EN);
- clk_disable(lcdc->pad_pclk);
- clk_disable(lcdc->pclk);
- clk_disable(lcdc->mdp_clk);
+ clk_disable_unprepare(lcdc->pad_pclk);
+ clk_disable_unprepare(lcdc->pclk);
+ clk_disable_unprepare(lcdc->mdp_clk);
return 0;
}
@@ -104,9 +104,9 @@
pr_info("%s: resuming\n", __func__);
- clk_enable(lcdc->mdp_clk);
- clk_enable(lcdc->pclk);
- clk_enable(lcdc->pad_pclk);
+ clk_prepare_enable(lcdc->mdp_clk);
+ clk_prepare_enable(lcdc->pclk);
+ clk_prepare_enable(lcdc->pad_pclk);
mdp_writel(lcdc->mdp, 1, MDP_LCDC_EN);
return 0;
@@ -117,9 +117,9 @@
struct msm_panel_data *fb_panel = &lcdc->fb_panel_data;
uint32_t dma_cfg;
- clk_enable(lcdc->mdp_clk);
- clk_enable(lcdc->pclk);
- clk_enable(lcdc->pad_pclk);
+ clk_prepare_enable(lcdc->mdp_clk);
+ clk_prepare_enable(lcdc->pclk);
+ clk_prepare_enable(lcdc->pad_pclk);
clk_set_rate(lcdc->pclk, lcdc->parms.clk_rate);
clk_set_rate(lcdc->pad_pclk, lcdc->parms.clk_rate);
diff --git a/drivers/video/msm/mdp_vsync.c b/drivers/video/msm/mdp_vsync.c
index c73de92..87e74d9 100644
--- a/drivers/video/msm/mdp_vsync.c
+++ b/drivers/video/msm/mdp_vsync.c
@@ -79,7 +79,7 @@
return;
mutex_lock(&vsync_clk_lock);
if (mfd->use_mdp_vsync) {
- clk_enable(mdp_vsync_clk);
+ clk_prepare_enable(mdp_vsync_clk);
vsync_clk_status = 1;
}
mutex_unlock(&vsync_clk_lock);
@@ -91,7 +91,7 @@
return;
mutex_lock(&vsync_clk_lock);
if (mfd->use_mdp_vsync) {
- clk_disable(mdp_vsync_clk);
+ clk_disable_unprepare(mdp_vsync_clk);
vsync_clk_status = 0;
}
mutex_unlock(&vsync_clk_lock);
diff --git a/drivers/video/msm/mipi_NT35510.c b/drivers/video/msm/mipi_NT35510.c
index b84072b..eaf1868 100644
--- a/drivers/video/msm/mipi_NT35510.c
+++ b/drivers/video/msm/mipi_NT35510.c
@@ -384,7 +384,7 @@
0xB6, 0x02,
};
static char video19[3] = {
- 0xB1, 0xFC, 0x06,
+ 0xB1, 0xFC, 0x00,
};
static char video20[4] = {
0xBC, 0x05, 0x05, 0x05,
diff --git a/drivers/video/msm/mipi_dsi.c b/drivers/video/msm/mipi_dsi.c
index 7e3eb19..baad0a8 100644
--- a/drivers/video/msm/mipi_dsi.c
+++ b/drivers/video/msm/mipi_dsi.c
@@ -132,6 +132,7 @@
mipi_dsi_ahb_ctrl(0);
local_bh_enable();
+ mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
@@ -168,6 +169,8 @@
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
+ mipi_dsi_prepare_clocks();
+
local_bh_disable();
mipi_dsi_ahb_ctrl(1);
local_bh_enable();
@@ -429,6 +432,14 @@
if (mipi_dsi_clk_init(pdev))
return -EPERM;
+ if (mipi_dsi_pdata->splash_is_enabled &&
+ !mipi_dsi_pdata->splash_is_enabled()) {
+ mipi_dsi_ahb_ctrl(1);
+ MIPI_OUTP(MIPI_DSI_BASE + 0x118, 0);
+ MIPI_OUTP(MIPI_DSI_BASE + 0x0, 0);
+ MIPI_OUTP(MIPI_DSI_BASE + 0x200, 0);
+ mipi_dsi_ahb_ctrl(0);
+ }
mipi_dsi_resource_initialized = 1;
return 0;
diff --git a/drivers/video/msm/mipi_dsi.h b/drivers/video/msm/mipi_dsi.h
index 31ce3ba..ff2910f 100644
--- a/drivers/video/msm/mipi_dsi.h
+++ b/drivers/video/msm/mipi_dsi.h
@@ -301,6 +301,8 @@
uint32 *expected_dsi_pclk);
int mipi_dsi_clk_init(struct platform_device *pdev);
void mipi_dsi_clk_deinit(struct device *dev);
+void mipi_dsi_prepare_clocks(void);
+void mipi_dsi_unprepare_clocks(void);
void mipi_dsi_ahb_ctrl(u32 enable);
void cont_splash_clk_ctrl(int enable);
void mipi_dsi_turn_on_clks(void);
diff --git a/drivers/video/msm/msm_dss_io_7x27a.c b/drivers/video/msm/msm_dss_io_7x27a.c
index 70f8982..28204a5 100644
--- a/drivers/video/msm/msm_dss_io_7x27a.c
+++ b/drivers/video/msm/msm_dss_io_7x27a.c
@@ -316,6 +316,32 @@
{
}
+void mipi_dsi_prepare_clocks(void)
+{
+ clk_prepare(dsi_ref_clk);
+ clk_prepare(ahb_m_clk);
+ clk_prepare(ahb_s_clk);
+ clk_prepare(ebi1_dsi_clk);
+ clk_prepare(mdp_dsi_pclk);
+ clk_prepare(dsi_byte_div_clk);
+ clk_prepare(dsi_esc_clk);
+ clk_prepare(dsi_clk);
+ clk_prepare(dsi_pixel_clk);
+}
+
+void mipi_dsi_unprepare_clocks(void)
+{
+ clk_unprepare(dsi_esc_clk);
+ clk_unprepare(dsi_byte_div_clk);
+ clk_unprepare(mdp_dsi_pclk);
+ clk_unprepare(ebi1_dsi_clk);
+ clk_unprepare(ahb_m_clk);
+ clk_unprepare(ahb_s_clk);
+ clk_unprepare(dsi_ref_clk);
+ clk_unprepare(dsi_clk);
+ clk_unprepare(dsi_pixel_clk);
+}
+
void mipi_dsi_ahb_ctrl(u32 enable)
{
static int ahb_ctrl_done;
diff --git a/drivers/video/msm/msm_dss_io_8960.c b/drivers/video/msm/msm_dss_io_8960.c
index eb30448..30edbd1 100644
--- a/drivers/video/msm/msm_dss_io_8960.c
+++ b/drivers/video/msm/msm_dss_io_8960.c
@@ -548,16 +548,34 @@
{
static int cont_splash_clks_enabled;
if (enable && !cont_splash_clks_enabled) {
- clk_enable(dsi_byte_div_clk);
- clk_enable(dsi_esc_clk);
+ clk_prepare_enable(dsi_byte_div_clk);
+ clk_prepare_enable(dsi_esc_clk);
cont_splash_clks_enabled = 1;
} else if (!enable && cont_splash_clks_enabled) {
- clk_disable(dsi_byte_div_clk);
- clk_disable(dsi_esc_clk);
+ clk_disable_unprepare(dsi_byte_div_clk);
+ clk_disable_unprepare(dsi_esc_clk);
cont_splash_clks_enabled = 0;
}
}
+void mipi_dsi_prepare_clocks(void)
+{
+ clk_prepare(amp_pclk);
+ clk_prepare(dsi_m_pclk);
+ clk_prepare(dsi_s_pclk);
+ clk_prepare(dsi_byte_div_clk);
+ clk_prepare(dsi_esc_clk);
+}
+
+void mipi_dsi_unprepare_clocks(void)
+{
+ clk_unprepare(dsi_esc_clk);
+ clk_unprepare(dsi_byte_div_clk);
+ clk_unprepare(dsi_m_pclk);
+ clk_unprepare(dsi_s_pclk);
+ clk_unprepare(amp_pclk);
+}
+
void mipi_dsi_ahb_ctrl(u32 enable)
{
static int ahb_ctrl_done;
diff --git a/drivers/video/msm/msm_dss_io_8x60.c b/drivers/video/msm/msm_dss_io_8x60.c
index 72d7960..bbee726 100644
--- a/drivers/video/msm/msm_dss_io_8x60.c
+++ b/drivers/video/msm/msm_dss_io_8x60.c
@@ -407,6 +407,24 @@
{
}
+void mipi_dsi_prepare_clocks(void)
+{
+ clk_prepare(amp_pclk);
+ clk_prepare(dsi_m_pclk);
+ clk_prepare(dsi_s_pclk);
+ clk_prepare(dsi_byte_div_clk);
+ clk_prepare(dsi_esc_clk);
+}
+
+void mipi_dsi_unprepare_clocks(void)
+{
+ clk_unprepare(dsi_esc_clk);
+ clk_unprepare(dsi_byte_div_clk);
+ clk_unprepare(dsi_m_pclk);
+ clk_unprepare(dsi_s_pclk);
+ clk_unprepare(amp_pclk);
+}
+
void mipi_dsi_ahb_ctrl(u32 enable)
{
static int ahb_ctrl_done;
diff --git a/drivers/video/msm/tvenc.c b/drivers/video/msm/tvenc.c
index e494cfa..30dc854 100644
--- a/drivers/video/msm/tvenc.c
+++ b/drivers/video/msm/tvenc.c
@@ -101,7 +101,7 @@
goto tvsrc_err;
}
#endif
- ret = clk_enable(tvenc_clk);
+ ret = clk_prepare_enable(tvenc_clk);
if (ret) {
pr_err("%s: tvenc_clk enable failed! %d\n",
__func__, ret);
@@ -109,7 +109,7 @@
}
if (!IS_ERR(tvenc_pclk)) {
- ret = clk_enable(tvenc_pclk);
+ ret = clk_prepare_enable(tvenc_pclk);
if (ret) {
pr_err("%s: tvenc_pclk enable failed! %d\n",
__func__, ret);
@@ -119,12 +119,12 @@
return ret;
} else {
if (!IS_ERR(tvenc_pclk))
- clk_disable(tvenc_pclk);
- clk_disable(tvenc_clk);
+ clk_disable_unprepare(tvenc_pclk);
+ clk_disable_unprepare(tvenc_clk);
return ret;
}
tvencp_err:
- clk_disable(tvenc_clk);
+ clk_disable_unprepare(tvenc_clk);
tvsrc_err:
return ret;
}
@@ -141,14 +141,14 @@
goto tvenc_err;
}
}
- ret = clk_enable(tvdac_clk);
+ ret = clk_prepare_enable(tvdac_clk);
if (ret) {
pr_err("%s: tvdac_clk enable failed! %d\n",
__func__, ret);
goto tvdac_err;
}
if (!IS_ERR(mdp_tv_clk)) {
- ret = clk_enable(mdp_tv_clk);
+ ret = clk_prepare_enable(mdp_tv_clk);
if (ret) {
pr_err("%s: mdp_tv_clk enable failed! %d\n",
__func__, ret);
@@ -158,15 +158,15 @@
return ret;
} else {
if (!IS_ERR(mdp_tv_clk))
- clk_disable(mdp_tv_clk);
- clk_disable(tvdac_clk);
+ clk_disable_unprepare(mdp_tv_clk);
+ clk_disable_unprepare(tvdac_clk);
if (tvenc_pdata->poll)
tvenc_set_encoder_clock(CLOCK_OFF);
return ret;
}
mdptv_err:
- clk_disable(tvdac_clk);
+ clk_disable_unprepare(tvdac_clk);
tvdac_err:
tvenc_set_encoder_clock(CLOCK_OFF);
tvenc_err:
@@ -196,7 +196,7 @@
0);
#else
if (mfd->ebi1_clk)
- clk_disable(mfd->ebi1_clk);
+ clk_disable_unprepare(mfd->ebi1_clk);
#endif
if (ret)
@@ -220,7 +220,7 @@
1);
#else
if (mfd->ebi1_clk)
- clk_enable(mfd->ebi1_clk);
+ clk_prepare_enable(mfd->ebi1_clk);
#endif
mdp4_extn_disp = 1;
if (tvenc_pdata && tvenc_pdata->pm_vid_en)
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
index 15737d6..e50a054 100644
--- a/include/linux/diagchar.h
+++ b/include/linux/diagchar.h
@@ -19,6 +19,7 @@
#define PKT_TYPE 8
#define DEINIT_TYPE 16
#define USER_SPACE_LOG_TYPE 32
+#define DCI_DATA_TYPE 64
#define USB_MODE 1
#define MEMORY_DEVICE_MODE 2
#define NO_LOGGING_MODE 3
@@ -35,6 +36,10 @@
#define DIAG_IOCTL_SWITCH_LOGGING 7
#define DIAG_IOCTL_GET_DELAYED_RSP_ID 8
#define DIAG_IOCTL_LSM_DEINIT 9
+#define DIAG_IOCTL_DCI_INIT 20
+#define DIAG_IOCTL_DCI_DEINIT 21
+#define DIAG_IOCTL_DCI_SUPPORT 22
+#define DIAG_IOCTL_DCI_REG 23
/* PC Tools IDs */
#define APQ8060_TOOLS_ID 4062
diff --git a/include/linux/ion.h b/include/linux/ion.h
index d761e1e..ae49bce 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -79,6 +79,13 @@
ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_SECURE flag */
};
+enum ion_fixed_position {
+ NOT_FIXED,
+ FIXED_LOW,
+ FIXED_MIDDLE,
+ FIXED_HIGH,
+};
+
/**
* Flag to use when allocating to indicate that a heap is secure.
*/
@@ -168,6 +175,7 @@
* (see FMEM)
* @mem_is_fmem Flag indicating whether this memory is coming from fmem
* or not.
+ * @fixed_position If nonzero, position in the fixed area.
* @virt_addr: Virtual address used when using fmem.
* @request_region: function to be called when the number of allocations
* goes from 0 -> 1
@@ -183,6 +191,7 @@
size_t secure_size; /* Size used for securing heap when heap is shared*/
int reusable;
int mem_is_fmem;
+ enum ion_fixed_position fixed_position;
ion_virt_addr_t *virt_addr;
int (*request_region)(void *);
int (*release_region)(void *);
@@ -195,6 +204,7 @@
* @align: Alignment requirement for the memory
* @mem_is_fmem Flag indicating whether this memory is coming from fmem
* or not.
+ * @fixed_position If nonzero, position in the fixed area.
* @request_region: function to be called when the number of allocations
* goes from 0 -> 1
* @release_region: function to be called when the number of allocations
@@ -206,6 +216,7 @@
int adjacent_mem_id;
unsigned int align;
int mem_is_fmem;
+ enum ion_fixed_position fixed_position;
int (*request_region)(void *);
int (*release_region)(void *);
void *(*setup_region)(void);
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index 0df513b..bdd6b2a 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -36,6 +36,7 @@
/* Look up a kernel symbol and return it in a text buffer. */
extern int sprint_symbol(char *buffer, unsigned long address);
+extern int sprint_symbol_no_offset(char *buffer, unsigned long address);
extern int sprint_backtrace(char *buffer, unsigned long address);
/* Look up a kernel symbol and print it to the kernel messages. */
@@ -80,6 +81,12 @@
return 0;
}
+static inline int sprint_symbol_no_offset(char *buffer, unsigned long addr)
+{
+ *buffer = '\0';
+ return 0;
+}
+
static inline int sprint_backtrace(char *buffer, unsigned long addr)
{
*buffer = '\0';
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
index b907219..08e9014 100644
--- a/include/linux/mfd/pm8xxx/core.h
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -50,6 +50,7 @@
#define PM8XXX_REVISION_8921_1p1 2
#define PM8XXX_REVISION_8921_2p0 3
#define PM8XXX_REVISION_8921_3p0 4
+#define PM8XXX_REVISION_8921_3p1 5
#define PM8XXX_REVISION_8821_TEST 0
#define PM8XXX_REVISION_8821_1p0 1
@@ -58,8 +59,8 @@
#define PM8XXX_REVISION_8018_TEST 0
#define PM8XXX_REVISION_8018_1p0 1
-#define PM8XXX_REVISION_8018_1p1 2
-#define PM8XXX_REVISION_8018_2p0 3
+#define PM8XXX_REVISION_8018_2p0 2
+#define PM8XXX_REVISION_8018_2p1 3
#define PM8XXX_REVISION_8922_TEST 0
#define PM8XXX_REVISION_8922_1p0 1
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index e19225e..a2ee306 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -249,6 +249,7 @@
#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
MMC_CAP2_HS200_1_2V_SDR)
+#define MMC_CAP2_DETECT_ON_ERR (1 << 8) /* On I/O err check card removal */
mmc_pm_flag_t pm_caps; /* supported pm features */
unsigned int power_notify_type;
#define MMC_HOST_PW_NOTIFY_NONE 0
diff --git a/include/linux/msm_adc.h b/include/linux/msm_adc.h
index 51371a6..c303e69 100644
--- a/include/linux/msm_adc.h
+++ b/include/linux/msm_adc.h
@@ -236,6 +236,7 @@
MSM_7x30,
MSM_8x60,
FSM_9xxx,
+ MSM_8x25,
};
enum epm_gpio_config {
@@ -344,23 +345,23 @@
int32_t adc_channel_request_conv(void *h, struct completion *conv_complete_evt);
int32_t adc_channel_read_result(void *h, struct adc_chan_result *chan_result);
#else
-static int32_t adc_channel_open(uint32_t channel, void **h)
+static inline int32_t adc_channel_open(uint32_t channel, void **h)
{
pr_err("%s.not supported.\n", __func__);
return -ENODEV;
}
-static int32_t adc_channel_close(void *h)
+static inline int32_t adc_channel_close(void *h)
{
pr_err("%s.not supported.\n", __func__);
return -ENODEV;
}
-static int32_t
+static inline int32_t
adc_channel_request_conv(void *h, struct completion *conv_complete_evt)
{
pr_err("%s.not supported.\n", __func__);
return -ENODEV;
}
-static int32_t
+static inline int32_t
adc_channel_read_result(void *h, struct adc_chan_result *chan_result)
{
pr_err("%s.not supported.\n", __func__);
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index ee1a22e..244b957 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -2,7 +2,7 @@
#define _MSM_KGSL_H
#define KGSL_VERSION_MAJOR 3
-#define KGSL_VERSION_MINOR 10
+#define KGSL_VERSION_MINOR 11
/*context flags */
#define KGSL_CONTEXT_SAVE_GMEM 0x00000001
@@ -112,7 +112,7 @@
enum kgsl_timestamp_type {
KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */
KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/
- KGSL_TIMESTAMP_MAX = 0x00000002,
+ KGSL_TIMESTAMP_QUEUED = 0x00000003,
};
/* property types - used with kgsl_device_getproperty */
@@ -125,7 +125,8 @@
KGSL_PROP_MMU_ENABLE = 0x00000006,
KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
KGSL_PROP_VERSION = 0x00000008,
- KGSL_PROP_GPU_RESET_STAT = 0x00000009
+ KGSL_PROP_GPU_RESET_STAT = 0x00000009,
+ KGSL_PROP_PWRCTRL = 0x0000000E,
};
struct kgsl_shadowprop {
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index e57df1a..84c8bfe 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -96,6 +96,8 @@
MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
+ MDP_YCRCB_H1V1, /* YCrCb interleave */
+ MDP_YCBCR_H1V1, /* YCbCr interleave */
MDP_IMGTYPE_LIMIT,
MDP_BGR_565 = MDP_IMGTYPE2_START, /* BGR 565 planer */
MDP_FB_FORMAT, /* framebuffer format */
@@ -434,10 +436,20 @@
} data;
};
+struct mdp_qseed_cfg_data {
+ uint32_t block;
+ uint32_t table_num;
+ uint32_t ops;
+ uint32_t len;
+ uint32_t *data;
+};
+
+
enum {
mdp_op_pcc_cfg,
mdp_op_csc_cfg,
mdp_op_lut_cfg,
+ mdp_op_qseed_cfg,
mdp_op_max,
};
@@ -447,6 +459,7 @@
struct mdp_pcc_cfg_data pcc_cfg_data;
struct mdp_csc_cfg_data csc_cfg_data;
struct mdp_lut_cfg_data lut_cfg_data;
+ struct mdp_qseed_cfg_data qseed_cfg_data;
} data;
};
diff --git a/include/linux/qseecom.h b/include/linux/qseecom.h
index 6d39026..62b5efe 100644
--- a/include/linux/qseecom.h
+++ b/include/linux/qseecom.h
@@ -146,4 +146,10 @@
#define QSEECOM_IOCTL_PERF_DISABLE_REQ \
_IO(QSEECOM_IOC_MAGIC, 12)
+#define QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ \
+ _IOWR(QSEECOM_IOC_MAGIC, 13, struct qseecom_load_img_req)
+
+#define QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ \
+ _IO(QSEECOM_IOC_MAGIC, 14)
+
#endif /* __QSEECOM_H_ */
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index a731774..e84884c 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -149,6 +149,17 @@
};
/**
+ * Used different VDDCX voltage voting mechnism
+ * VDDCX_CORNER Vote for VDDCX Corner voltage
+ * VDDCX Vote for VDDCX Absolute voltage
+ */
+enum usb_vdd_type {
+ VDDCX_CORNER = 0,
+ VDDCX,
+ VDD_TYPE_MAX,
+};
+
+/**
* SPS Pipes direction.
*
* USB_TO_PEER_PERIPHERAL USB (as Producer) to other
@@ -342,6 +353,7 @@
unsigned long tmouts;
u8 active_tmout;
struct hrtimer timer;
+ enum usb_vdd_type vdd_type;
};
struct msm_hsic_host_platform_data {
diff --git a/include/media/Kbuild b/include/media/Kbuild
index a60b86c..8dfb0fc 100644
--- a/include/media/Kbuild
+++ b/include/media/Kbuild
@@ -1,6 +1,7 @@
header-y += tavarua.h
header-y += msm_camera.h
+header-y += vcap_fmt.h
header-y += msm_isp.h
header-y += msm_gemini.h
header-y += msm_v4l2_overlay.h
diff --git a/include/media/vcap_fmt.h b/include/media/vcap_fmt.h
new file mode 100644
index 0000000..4a62bc3
--- /dev/null
+++ b/include/media/vcap_fmt.h
@@ -0,0 +1,140 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef VCAP_FMT_H
+#define VCAP_FMT_H
+
+#define V4L2_BUF_TYPE_INTERLACED_IN_AFE (V4L2_BUF_TYPE_PRIVATE)
+#define V4L2_BUF_TYPE_INTERLACED_IN_DECODER (V4L2_BUF_TYPE_PRIVATE + 1)
+
+enum hal_vcap_mode {
+ HAL_VCAP_MODE_PRO = 0,
+ HAL_VCAP_MODE_INT,
+};
+
+enum hal_vcap_polar {
+ HAL_VCAP_POLAR_NEG = 0,
+ HAL_VCAP_POLAR_POS,
+};
+
+enum hal_vcap_color {
+ HAL_VCAP_YUV = 0,
+ HAL_VCAP_RGB,
+};
+
+enum hal_vcap_vc_fmt {
+ /* 1080p */
+ HAL_VCAP_YUV_1080p_60_RH = 0,
+ HAL_VCAP_YUV_1080p_60_FL,
+ HAL_VCAP_RGB_1080p_60_FL,
+ HAL_VCAP_YUV_1080p_24_FL,
+ HAL_VCAP_YUV_1080p_24_RH,
+ HAL_VCAP_YUV_1080p_24_RW,
+ HAL_VCAP_YUV_1080p_60_RW,
+ HAL_VCAP_YUV_1080p_50_FL,
+ HAL_VCAP_YUV_1080p_50_RH,
+ HAL_VCAP_YUV_1080p_25_FL,
+ HAL_VCAP_YUV_1080p_25_RH,
+ HAL_VCAP_YUV_1080p_30_RH,
+ HAL_VCAP_RGB_1080p_25_FL,
+ HAL_VCAP_RGB_1080p_25_RH,
+ /* 1080i */
+ HAL_VCAP_YUV_1080i_60_FL,
+ HAL_VCAP_YUV_1080i_60_RH,
+ HAL_VCAP_YUV_1080i_60_RW,
+ HAL_VCAP_YUV_1080i_50_FL,
+ HAL_VCAP_YUV_1080i_50_RH,
+ HAL_VCAP_YUV_1080i_50_RW,
+ HAL_VCAP_RGB_1080i_50_FL,
+ HAL_VCAP_RGB_1080i_50_RH,
+ /* 480i */
+ HAL_VCAP_YUV_480i_60_RH,
+ HAL_VCAP_YUV_480i_60_FL,
+ HAL_VCAP_YUV_480i_60_RW,
+ HAL_VCAP_YUV_2880_480i_60_FL,
+ HAL_VCAP_YUV_2880_480i_60_RH,
+ /* 480p */
+ HAL_VCAP_YUV_480p_60_RH,
+ HAL_VCAP_RGB_480p_60_RH,
+ HAL_VCAP_RGB_480p_60_FL,
+ HAL_VCAP_YUV_480p_60_FL,
+ HAL_VCAP_YUV_480p_60_RW,
+ HAL_VCAP_YUV_2880_480p_60_FL,
+ HAL_VCAP_YUV_2880_480p_60_RH,
+ /* 720p */
+ HAL_VCAP_YUV_720p_60_FL,
+ HAL_VCAP_RGB_720p_60_FL,
+ HAL_VCAP_YUV_720p_60_RW,
+ HAL_VCAP_YUV_720p_60_RH,
+ HAL_VCAP_YUV_720p_50_FL,
+ HAL_VCAP_YUV_720p_50_RW,
+ HAL_VCAP_YUV_720p_50_RH,
+ /* 576p */
+ HAL_VCAP_YUV_576p_50_FL,
+ HAL_VCAP_RGB_576p_50_FL,
+ HAL_VCAP_YUV_576p_50_RW,
+ HAL_VCAP_YUV_576p_50_RH,
+ HAL_VCAP_YUV_1440_576p_50_RH,
+ HAL_VCAP_YUV_2880_576p_50_FL,
+ HAL_VCAP_YUV_2880_576p_50_RH,
+ /* 576i */
+ HAL_VCAP_YUV_576i_50_FL,
+ HAL_VCAP_YUV_576i_50_RW,
+ HAL_VCAP_YUV_576i_50_RH,
+ /* XGA 1024x768 */
+ HAL_VCAP_YUV_XGA_FL,
+ HAL_VCAP_YUV_XGA_RH,
+ HAL_VCAP_YUV_XGA_RB,
+ /* SXGA 1280x1024 */
+ HAL_VCAP_YUV_SXGA_FL,
+ HAL_VCAP_RGB_SXGA_FL,
+ HAL_VCAP_YUV_SXGA_RH,
+ HAL_VCAP_YUV_SXGA_RB,
+ /* UXGA 1600x1200 */
+ HAL_VCAP_YUV_UXGA_FL,
+ HAL_VCAP_RGB_UXGA_FL,
+ HAL_VCAP_YUV_UXGA_RH,
+ HAL_VCAP_YUV_UXGA_RB,
+ /* test odd height */
+ HAL_VCAP_ODD_HEIGHT,
+ /* test odd width RGB only */
+ HAL_VCAP_ODD_WIDTH,
+};
+
+struct v4l2_format_vc_ext {
+ enum hal_vcap_vc_fmt format;
+ enum hal_vcap_mode mode;
+ enum hal_vcap_polar h_polar;
+ enum hal_vcap_polar v_polar;
+ enum hal_vcap_polar d_polar;
+ enum hal_vcap_color color_space;
+
+ float clk_freq;
+ uint32_t vtotal;
+ uint32_t htotal;
+ uint32_t hactive_start;
+ uint32_t hactive_end;
+ uint32_t vactive_start;
+ uint32_t vactive_end;
+ uint32_t vsync_start;
+ uint32_t vsync_end;
+ uint32_t hsync_start;
+ uint32_t hsync_end;
+ uint32_t f2_vactive_start;
+ uint32_t f2_vactive_end;
+ uint32_t f2_vsync_h_start;
+ uint32_t f2_vsync_h_end;
+ uint32_t f2_vsync_v_start;
+ uint32_t f2_vsync_v_end;
+};
+#endif
diff --git a/include/media/vcap_v4l2.h b/include/media/vcap_v4l2.h
new file mode 100644
index 0000000..57f9703
--- /dev/null
+++ b/include/media/vcap_v4l2.h
@@ -0,0 +1,132 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef VCAP_V4L2_H
+#define VCAP_V4L2_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <media/videobuf2-vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-common.h>
+#include <media/vcap_fmt.h>
+#include <mach/board.h>
+
+struct vcap_client_data;
+
+enum rdy_buf {
+ VC_NO_BUF = 0,
+ VC_BUF1 = 1 << 1,
+ VC_BUF2 = 1 << 2,
+ VC_BUF1N2 = 0x11 << 1,
+};
+
+struct vcap_buf_info {
+ unsigned long vaddr;
+ unsigned long size;
+};
+
+struct vcap_action {
+ struct list_head active;
+
+ /* thread for generating video stream*/
+ struct task_struct *kthread;
+ wait_queue_head_t wq;
+
+ /* Buffer index */
+ enum rdy_buf buf_ind;
+
+ /* Buffers inside vc */
+ struct vcap_buffer *buf1;
+ struct vcap_buffer *buf2;
+
+ /* Counters to control fps rate */
+ int frame;
+ int ini_jiffies;
+};
+
+struct vcap_dev {
+ struct v4l2_device v4l2_dev;
+
+ struct video_device *vfd;
+ struct ion_client *ion_client;
+
+ struct resource *vcapirq;
+
+ struct resource *vcapmem;
+ struct resource *vcapio;
+ void __iomem *vcapbase;
+
+ struct vcap_platform_data *vcap_pdata;
+
+ struct regulator *fs_vcap;
+ struct clk *vcap_clk;
+ struct clk *vcap_p_clk;
+ struct clk *vcap_npl_clk;
+ /*struct platform_device *pdev;*/
+
+ uint32_t bus_client_handle;
+
+ struct vcap_client_data *vc_client;
+ struct vcap_client_data *vp_client;
+
+ atomic_t vc_enabled;
+ atomic_t vc_resource;
+ atomic_t vp_resource;
+};
+
+struct vp_format_data {
+ unsigned int width, height;
+ unsigned int pixelformat;
+ enum v4l2_field field;
+
+};
+
+struct vcap_buffer {
+ /* common v4l buffer stuff -- must be first */
+ struct vb2_buffer vb;
+ struct list_head list;
+ unsigned long paddr;
+ struct ion_handle *ion_handle;
+};
+
+struct vcap_client_data {
+ struct vcap_dev *dev;
+
+ struct vb2_queue vc_vidq;
+ /*struct vb2_queue vb__vidq;*/
+ /*struct vb2_queue vb_cap_vidq;*/
+
+ struct v4l2_format_vc_ext vc_format;
+
+ enum v4l2_buf_type vp_buf_type_field;
+ struct vp_format_data vp_format;
+
+ struct vcap_action vid_vc_action;
+ struct workqueue_struct *vcap_work_q;
+ struct ion_handle *vc_ion_handle;
+
+ uint32_t hold_vc;
+ uint32_t hold_vp;
+
+ spinlock_t cap_slock;
+};
+
+#endif
+#endif
diff --git a/kernel/kallsyms.c b/kernel/kallsyms.c
index 079f1d3..2169fee 100644
--- a/kernel/kallsyms.c
+++ b/kernel/kallsyms.c
@@ -343,7 +343,7 @@
/* Look up a kernel symbol and return it in a text buffer. */
static int __sprint_symbol(char *buffer, unsigned long address,
- int symbol_offset)
+ int symbol_offset, int add_offset)
{
char *modname;
const char *name;
@@ -358,13 +358,13 @@
if (name != buffer)
strcpy(buffer, name);
len = strlen(buffer);
- buffer += len;
offset -= symbol_offset;
+ if (add_offset)
+ len += sprintf(buffer + len, "+%#lx/%#lx", offset, size);
+
if (modname)
- len += sprintf(buffer, "+%#lx/%#lx [%s]", offset, size, modname);
- else
- len += sprintf(buffer, "+%#lx/%#lx", offset, size);
+ len += sprintf(buffer + len, " [%s]", modname);
return len;
}
@@ -382,12 +382,28 @@
*/
int sprint_symbol(char *buffer, unsigned long address)
{
- return __sprint_symbol(buffer, address, 0);
+ return __sprint_symbol(buffer, address, 0, 1);
}
-
EXPORT_SYMBOL_GPL(sprint_symbol);
/**
+ * sprint_symbol_no_offset - Look up a kernel symbol and return it in a text buffer
+ * @buffer: buffer to be stored
+ * @address: address to lookup
+ *
+ * This function looks up a kernel symbol with @address and stores its name
+ * and module name to @buffer if possible. If no symbol was found, just saves
+ * its @address as is.
+ *
+ * This function returns the number of bytes stored in @buffer.
+ */
+int sprint_symbol_no_offset(char *buffer, unsigned long address)
+{
+ return __sprint_symbol(buffer, address, 0, 0);
+}
+EXPORT_SYMBOL_GPL(sprint_symbol_no_offset);
+
+/**
* sprint_backtrace - Look up a backtrace symbol and return it in a text buffer
* @buffer: buffer to be stored
* @address: address to lookup
@@ -403,7 +419,7 @@
*/
int sprint_backtrace(char *buffer, unsigned long address)
{
- return __sprint_symbol(buffer, address, -1);
+ return __sprint_symbol(buffer, address, -1, 1);
}
/* Look up a kernel symbol and print it to the kernel messages. */
diff --git a/kernel/resource.c b/kernel/resource.c
index fdd3939..ef4beab 100644
--- a/kernel/resource.c
+++ b/kernel/resource.c
@@ -357,12 +357,18 @@
while ((res.start < res.end) &&
(find_next_system_ram(&res, "System RAM") >= 0)) {
pfn = (res.start + PAGE_SIZE - 1) >> PAGE_SHIFT;
- end_pfn = (res.end + 1) >> PAGE_SHIFT;
+ if (res.end + 1 <= 0)
+ end_pfn = res.end >> PAGE_SHIFT;
+ else
+ end_pfn = (res.end + 1) >> PAGE_SHIFT;
if (end_pfn > pfn)
ret = (*func)(pfn, end_pfn - pfn, arg);
if (ret)
break;
- res.start = res.end + 1;
+ if (res.end + 1 > res.start)
+ res.start = res.end + 1;
+ else
+ res.start = res.end;
res.end = orig_end;
}
return ret;
diff --git a/lib/spinlock_debug.c b/lib/spinlock_debug.c
index 4755b98..fb4e88d 100644
--- a/lib/spinlock_debug.c
+++ b/lib/spinlock_debug.c
@@ -61,7 +61,7 @@
printk(KERN_EMERG "BUG: spinlock %s on CPU#%d, %s/%d\n",
msg, raw_smp_processor_id(),
current->comm, task_pid_nr(current));
- printk(KERN_EMERG " lock: %p, .magic: %08x, .owner: %s/%d, "
+ printk(KERN_EMERG " lock: %ps, .magic: %08x, .owner: %s/%d, "
".owner_cpu: %d\n",
lock, lock->magic,
owner ? owner->comm : "<none>",
@@ -114,7 +114,7 @@
if (print_once) {
print_once = 0;
printk(KERN_EMERG "BUG: spinlock lockup on CPU#%d, "
- "%s/%d, %p\n",
+ "%s/%d, %ps\n",
raw_smp_processor_id(), current->comm,
task_pid_nr(current), lock);
dump_stack();
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 4365df3..44657bc 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -438,7 +438,7 @@
else if (ext != 'f' && ext != 's')
sprint_symbol(sym, value);
else
- kallsyms_lookup(value, NULL, NULL, NULL, sym);
+ sprint_symbol_no_offset(sym, value);
return string(buf, end, sym, spec);
#else
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
old mode 100755
new mode 100644
index f4f833b..598c310
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -1852,11 +1852,29 @@
if (test_bit(HCI_CONN_ENCRYPT_PEND, &conn->pend)) {
if (!ev->status) {
- struct hci_cp_set_conn_encrypt cp;
- cp.handle = ev->handle;
- cp.encrypt = 0x01;
- hci_send_cmd(hdev, HCI_OP_SET_CONN_ENCRYPT,
- sizeof(cp), &cp);
+ if (conn->link_mode & HCI_LM_ENCRYPT) {
+ /* Encryption implies authentication */
+ conn->link_mode |= HCI_LM_AUTH;
+ conn->link_mode |= HCI_LM_ENCRYPT;
+ conn->sec_level =
+ conn->pending_sec_level;
+ clear_bit(HCI_CONN_ENCRYPT_PEND,
+ &conn->pend);
+ hci_encrypt_cfm(conn, ev->status, 1);
+
+ if (test_bit(HCI_MGMT, &hdev->flags))
+ mgmt_encrypt_change(hdev->id,
+ &conn->dst,
+ ev->status);
+
+ } else {
+ struct hci_cp_set_conn_encrypt cp;
+ cp.handle = ev->handle;
+ cp.encrypt = 0x01;
+ hci_send_cmd(hdev,
+ HCI_OP_SET_CONN_ENCRYPT,
+ sizeof(cp), &cp);
+ }
} else {
clear_bit(HCI_CONN_ENCRYPT_PEND, &conn->pend);
hci_encrypt_cfm(conn, ev->status, 0x00);
@@ -2653,6 +2671,7 @@
conn->key_type = ev->key_type;
hci_disconnect_amp(conn, 0x06);
+ conn->link_mode &= ~HCI_LM_ENCRYPT;
pin_len = conn->pin_length;
hci_conn_put(conn);
hci_conn_enter_active_mode(conn, 0);
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index bcd0dd7..8b6f23e 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -1823,7 +1823,7 @@
return cmd_status(sk, index, MGMT_OP_SET_RSSI_REPORTER,
ENODEV);
- hci_dev_lock(hdev);
+ hci_dev_lock_bh(hdev);
conn = hci_conn_hash_lookup_ba(hdev, LE_LINK, &cp->bdaddr);
@@ -1838,7 +1838,7 @@
__le16_to_cpu(cp->interval), cp->updateOnThreshExceed);
failed:
- hci_dev_unlock(hdev);
+ hci_dev_unlock_bh(hdev);
hci_dev_put(hdev);
return err;
@@ -1862,7 +1862,7 @@
return cmd_status(sk, index, MGMT_OP_UNSET_RSSI_REPORTER,
ENODEV);
- hci_dev_lock(hdev);
+ hci_dev_lock_bh(hdev);
conn = hci_conn_hash_lookup_ba(hdev, LE_LINK, &cp->bdaddr);
@@ -1875,7 +1875,7 @@
hci_conn_unset_rssi_reporter(conn);
failed:
- hci_dev_unlock(hdev);
+ hci_dev_unlock_bh(hdev);
hci_dev_put(hdev);
return err;
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index a78380b..d2f58a5 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -34,8 +34,10 @@
#include <linux/gpio.h>
#include "wcd9310.h"
-#define WCD9310_RATES (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|\
- SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_48000)
+#define WCD9310_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
+
#define NUM_DECIMATORS 10
#define NUM_INTERPOLATORS 7
@@ -63,7 +65,9 @@
#define AIF1_PB 1
#define AIF1_CAP 2
#define AIF2_PB 3
-#define NUM_CODEC_DAIS 3
+#define AIF2_CAP 4
+
+#define NUM_CODEC_DAIS 4
#define TABLA_COMP_DIGITAL_GAIN_OFFSET 3
struct tabla_codec_dai_data {
@@ -148,6 +152,8 @@
COMPANDER_FS_16KHZ,
COMPANDER_FS_32KHZ,
COMPANDER_FS_48KHZ,
+ COMPANDER_FS_96KHZ,
+ COMPANDER_FS_192KHZ,
COMPANDER_FS_MAX,
};
@@ -202,7 +208,8 @@
};
enum tabla_mbhc_plug_type {
- PLUG_TYPE_NONE = 0,
+ PLUG_TYPE_INVALID = -1,
+ PLUG_TYPE_NONE,
PLUG_TYPE_HEADSET,
PLUG_TYPE_HEADPHONE,
PLUG_TYPE_HIGH_HPH,
@@ -302,11 +309,6 @@
*/
struct mutex codec_resource_lock;
- /* Used to override the rule "invalid headset
- * when microphone voltage is too high"
- */
- bool mbhc_inval_hs_range_override;
-
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_poke;
struct dentry *debugfs_mbhc;
@@ -1068,6 +1070,10 @@
"RX5", "RX6", "RX7"
};
+static const char *rx_mix2_text[] = {
+ "ZERO", "SRC1", "SRC2", "IIR1", "IIR2"
+};
+
static const char *rx_dsm_text[] = {
"CIC_OUT", "DSM_INV"
};
@@ -1077,6 +1083,21 @@
"DEC1"
};
+static const char *sb_tx2_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC2"
+};
+
+static const char *sb_tx3_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC3"
+};
+
+static const char *sb_tx4_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC4"
+};
+
static const char *sb_tx5_mux_text[] = {
"ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
"DEC5"
@@ -1189,12 +1210,42 @@
static const struct soc_enum rx7_mix1_inp2_chain_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX7_B1_CTL, 4, 12, rx_mix1_text);
+static const struct soc_enum rx1_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx1_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B3_CTL, 3, 5, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX2_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX2_B3_CTL, 3, 5, rx_mix2_text);
+
+static const struct soc_enum rx3_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX3_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx3_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX3_B3_CTL, 3, 5, rx_mix2_text);
+
static const struct soc_enum rx4_dsm_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_RX4_B6_CTL, 4, 2, rx_dsm_text);
static const struct soc_enum rx6_dsm_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_RX6_B6_CTL, 4, 2, rx_dsm_text);
+static const struct soc_enum sb_tx1_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
+
+static const struct soc_enum sb_tx2_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B2_CTL, 0, 9, sb_tx2_mux_text);
+
+static const struct soc_enum sb_tx3_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B3_CTL, 0, 9, sb_tx3_mux_text);
+
+static const struct soc_enum sb_tx4_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B4_CTL, 0, 9, sb_tx4_mux_text);
+
static const struct soc_enum sb_tx5_mux_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B5_CTL, 0, 9, sb_tx5_mux_text);
@@ -1217,9 +1268,6 @@
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B10_CTL, 0, 18,
sb_tx7_to_tx10_mux_text);
-static const struct soc_enum sb_tx1_mux_enum =
- SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
-
static const struct soc_enum dec1_mux_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B1_CTL, 0, 3, dec1_mux_text);
@@ -1304,12 +1352,42 @@
static const struct snd_kcontrol_new rx7_mix1_inp2_mux =
SOC_DAPM_ENUM("RX7 MIX1 INP2 Mux", rx7_mix1_inp2_chain_enum);
+static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP2 Mux", rx1_mix2_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP2 Mux", rx2_mix2_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX3 MIX2 INP1 Mux", rx3_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX3 MIX2 INP2 Mux", rx3_mix2_inp2_chain_enum);
+
static const struct snd_kcontrol_new rx4_dsm_mux =
SOC_DAPM_ENUM("RX4 DSM MUX Mux", rx4_dsm_enum);
static const struct snd_kcontrol_new rx6_dsm_mux =
SOC_DAPM_ENUM("RX6 DSM MUX Mux", rx6_dsm_enum);
+static const struct snd_kcontrol_new sb_tx1_mux =
+ SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx2_mux =
+ SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx3_mux =
+ SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx4_mux =
+ SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
+
static const struct snd_kcontrol_new sb_tx5_mux =
SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
@@ -1328,8 +1406,6 @@
static const struct snd_kcontrol_new sb_tx10_mux =
SOC_DAPM_ENUM("SLIM TX10 MUX Mux", sb_tx10_mux_enum);
-static const struct snd_kcontrol_new sb_tx1_mux =
- SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
static int wcd9310_put_dec_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
@@ -2328,14 +2404,17 @@
int vddio_switch, bool restartpolling,
bool checkpolling)
{
- struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
int cfilt_k_val;
+ bool override;
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
if (vddio_switch && !tabla->mbhc_micbias_switched &&
(!checkpolling || tabla->mbhc_polling_active)) {
if (restartpolling)
tabla_codec_pause_hs_polling(codec);
- tabla_turn_onoff_override(codec, true);
+ override = snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x04;
+ if (!override)
+ tabla_turn_onoff_override(codec, true);
/* Adjust threshold if Mic Bias voltage changes */
if (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) {
cfilt_k_val = tabla_find_k_value(
@@ -2360,7 +2439,8 @@
0x80, 0x80);
snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
0x10, 0x00);
- tabla_turn_onoff_override(codec, false);
+ if (!override)
+ tabla_turn_onoff_override(codec, false);
if (restartpolling)
tabla_codec_start_hs_polling(codec);
@@ -2953,6 +3033,15 @@
{"SLIM TX1", NULL, "SLIM TX1 MUX"},
{"SLIM TX1 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX2", NULL, "SLIM TX2 MUX"},
+ {"SLIM TX2 MUX", "DEC2", "DEC2 MUX"},
+
+ {"SLIM TX3", NULL, "SLIM TX3 MUX"},
+ {"SLIM TX3 MUX", "DEC3", "DEC3 MUX"},
+
+ {"SLIM TX4", NULL, "SLIM TX4 MUX"},
+ {"SLIM TX4 MUX", "DEC4", "DEC4 MUX"},
+
{"SLIM TX5", NULL, "SLIM TX5 MUX"},
{"SLIM TX5 MUX", "DEC5", "DEC5 MUX"},
@@ -2978,6 +3067,10 @@
{"SLIM TX8 MUX", "DEC4", "DEC4 MUX"},
{"SLIM TX8 MUX", "DEC5", "DEC5 MUX"},
{"SLIM TX8 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX8 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX8 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX8 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX8 MUX", "DEC10", "DEC10 MUX"},
{"SLIM TX9", NULL, "SLIM TX9 MUX"},
{"SLIM TX9 MUX", "DEC1", "DEC1 MUX"},
@@ -3009,8 +3102,8 @@
{"EAR_PA_MIXER", NULL, "DAC1"},
{"DAC1", NULL, "CP"},
- {"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX1"},
- {"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX1"},
+ {"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX2"},
+ {"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX2"},
{"ANC", NULL, "ANC1 FB MUX"},
/* Headset (RX MIX1 and RX MIX2) */
@@ -3060,11 +3153,11 @@
{"LINEOUT5 PA", NULL, "LINEOUT5_PA_MIXER"},
{"LINEOUT5_PA_MIXER", NULL, "LINEOUT5 DAC"},
- {"LINEOUT1 DAC", NULL, "RX3 MIX1"},
+ {"LINEOUT1 DAC", NULL, "RX3 MIX2"},
{"LINEOUT5 DAC", NULL, "RX7 MIX1"},
- {"RX1 CHAIN", NULL, "RX1 MIX1"},
- {"RX2 CHAIN", NULL, "RX2 MIX1"},
+ {"RX1 CHAIN", NULL, "RX1 MIX2"},
+ {"RX2 CHAIN", NULL, "RX2 MIX2"},
{"RX1 CHAIN", NULL, "ANC"},
{"RX2 CHAIN", NULL, "ANC"},
@@ -3095,6 +3188,15 @@
{"RX6 MIX1", NULL, "RX6 MIX1 INP2"},
{"RX7 MIX1", NULL, "RX7 MIX1 INP1"},
{"RX7 MIX1", NULL, "RX7 MIX1 INP2"},
+ {"RX1 MIX2", NULL, "RX1 MIX1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP2"},
+ {"RX2 MIX2", NULL, "RX2 MIX1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP2"},
+ {"RX3 MIX2", NULL, "RX3 MIX1"},
+ {"RX3 MIX2", NULL, "RX3 MIX2 INP1"},
+ {"RX3 MIX2", NULL, "RX3 MIX2 INP2"},
{"RX1 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX1 MIX1 INP1", "RX2", "SLIM RX2"},
@@ -3194,6 +3296,12 @@
{"RX7 MIX1 INP2", "RX6", "SLIM RX6"},
{"RX7 MIX1 INP2", "RX7", "SLIM RX7"},
{"RX7 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX2 INP2", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP2", "IIR1", "IIR1"},
+ {"RX3 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX3 MIX2 INP2", "IIR1", "IIR1"},
/* Decimator Inputs */
{"DEC1 MUX", "DMIC1", "DMIC1"},
@@ -3215,12 +3323,23 @@
{"DEC6 MUX", "ADC1", "ADC1"},
{"DEC6 MUX", NULL, "CDC_CONN"},
{"DEC7 MUX", "DMIC1", "DMIC1"},
+ {"DEC7 MUX", "DMIC6", "DMIC6"},
+ {"DEC7 MUX", "ADC1", "ADC1"},
{"DEC7 MUX", "ADC6", "ADC6"},
{"DEC7 MUX", NULL, "CDC_CONN"},
+ {"DEC8 MUX", "DMIC2", "DMIC2"},
+ {"DEC8 MUX", "DMIC5", "DMIC5"},
+ {"DEC8 MUX", "ADC2", "ADC2"},
{"DEC8 MUX", "ADC5", "ADC5"},
{"DEC8 MUX", NULL, "CDC_CONN"},
+ {"DEC9 MUX", "DMIC4", "DMIC4"},
+ {"DEC9 MUX", "DMIC5", "DMIC5"},
+ {"DEC9 MUX", "ADC2", "ADC2"},
{"DEC9 MUX", "ADC3", "ADC3"},
{"DEC9 MUX", NULL, "CDC_CONN"},
+ {"DEC10 MUX", "DMIC3", "DMIC3"},
+ {"DEC10 MUX", "DMIC6", "DMIC6"},
+ {"DEC10 MUX", "ADC1", "ADC1"},
{"DEC10 MUX", "ADC4", "ADC4"},
{"DEC10 MUX", NULL, "CDC_CONN"},
@@ -3295,13 +3414,13 @@
static const struct snd_soc_dapm_route tabla_1_x_lineout_2_to_4_map[] = {
- {"RX4 DSM MUX", "DSM_INV", "RX3 MIX1"},
+ {"RX4 DSM MUX", "DSM_INV", "RX3 MIX2"},
{"RX4 DSM MUX", "CIC_OUT", "RX4 MIX1"},
{"LINEOUT2 DAC", NULL, "RX4 DSM MUX"},
{"LINEOUT3 DAC", NULL, "RX5 MIX1"},
- {"LINEOUT3 DAC GROUND", "Switch", "RX3 MIX1"},
+ {"LINEOUT3 DAC GROUND", "Switch", "RX3 MIX2"},
{"LINEOUT3 DAC", NULL, "LINEOUT3 DAC GROUND"},
{"RX6 DSM MUX", "DSM_INV", "RX5 MIX1"},
@@ -3315,7 +3434,7 @@
static const struct snd_soc_dapm_route tabla_2_x_lineout_2_to_4_map[] = {
- {"RX4 DSM MUX", "DSM_INV", "RX3 MIX1"},
+ {"RX4 DSM MUX", "DSM_INV", "RX3 MIX2"},
{"RX4 DSM MUX", "CIC_OUT", "RX4 MIX1"},
{"LINEOUT3 DAC", NULL, "RX4 DSM MUX"},
@@ -3657,7 +3776,7 @@
tabla->dai[dai->id - 1].ch_act = 0;
tabla->dai[dai->id - 1].ch_tot = rx_num;
}
- } else if (dai->id == AIF1_CAP) {
+ } else if (dai->id == AIF1_CAP || dai->id == AIF2_CAP) {
for (i = 0; i < tx_num; i++) {
tabla->dai[dai->id - 1].ch_num[i] = tx_slot[i];
tabla->dai[dai->id - 1].ch_act = 0;
@@ -3705,7 +3824,14 @@
rx_slot[cnt] = rx_ch[5 + cnt];
cnt++;
}
+ } else if (dai->id == AIF2_CAP) {
+ *tx_num = tabla_dai[dai->id - 1].capture.channels_max;
+ tx_slot[0] = tx_ch[cnt];
+ tx_slot[1] = tx_ch[1 + cnt];
+ tx_slot[2] = tx_ch[3 + cnt];
+ tx_slot[3] = tx_ch[5 + cnt];
}
+
return 0;
}
@@ -3744,6 +3870,16 @@
rx_fs_rate = 0x60;
compander_fs = COMPANDER_FS_48KHZ;
break;
+ case 96000:
+ tx_fs_rate = 0x04;
+ rx_fs_rate = 0x80;
+ compander_fs = COMPANDER_FS_96KHZ;
+ break;
+ case 192000:
+ tx_fs_rate = 0x05;
+ rx_fs_rate = 0xA0;
+ compander_fs = COMPANDER_FS_192KHZ;
+ break;
default:
pr_err("%s: Invalid sampling rate %d\n", __func__,
params_rate(params));
@@ -3755,7 +3891,7 @@
* If current dai is a tx dai, set sample rate to
* all the txfe paths that are currently not active
*/
- if (dai->id == AIF1_CAP) {
+ if ((dai->id == AIF1_CAP) || (dai->id == AIF2_CAP)) {
tx_state = snd_soc_read(codec,
TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL);
@@ -3773,7 +3909,7 @@
tx_fs_reg = TABLA_A_CDC_TX1_CLK_FS_CTL
+ (BITS_PER_REG*(path-1));
snd_soc_update_bits(codec, tx_fs_reg,
- 0x03, tx_fs_rate);
+ 0x07, tx_fs_rate);
}
}
if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
@@ -3793,7 +3929,7 @@
break;
}
snd_soc_update_bits(codec, TABLA_A_CDC_CLK_TX_I2S_CTL,
- 0x03, tx_fs_rate);
+ 0x07, tx_fs_rate);
} else {
tabla->dai[dai->id - 1].rate = params_rate(params);
}
@@ -3869,7 +4005,7 @@
.stream_name = "AIF1 Playback",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
@@ -3883,7 +4019,7 @@
.stream_name = "AIF1 Capture",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
@@ -3898,12 +4034,26 @@
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
.rate_min = 8000,
- .rate_max = 48000,
+ .rate_max = 192000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &tabla_dai_ops,
},
+ {
+ .name = "tabla_tx2",
+ .id = AIF2_CAP,
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .rates = WCD9310_RATES,
+ .formats = TABLA_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tabla_dai_ops,
+ },
};
static struct snd_soc_dai_driver tabla_i2s_dai[] = {
@@ -3914,7 +4064,7 @@
.stream_name = "AIF1 Playback",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
@@ -3928,7 +4078,7 @@
.stream_name = "AIF1 Capture",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
@@ -3953,7 +4103,8 @@
switch (event) {
case SND_SOC_DAPM_POST_PMU:
for (j = 0; j < ARRAY_SIZE(tabla_dai); j++) {
- if (tabla_dai[j].id == AIF1_CAP)
+ if ((tabla_dai[j].id == AIF1_CAP) ||
+ (tabla_dai[j].id == AIF2_CAP))
continue;
if (!strncmp(w->sname,
tabla_dai[j].playback.stream_name, 13)) {
@@ -3969,7 +4120,8 @@
break;
case SND_SOC_DAPM_POST_PMD:
for (j = 0; j < ARRAY_SIZE(tabla_dai); j++) {
- if (tabla_dai[j].id == AIF1_CAP)
+ if ((tabla_dai[j].id == AIF1_CAP) ||
+ (tabla_dai[j].id == AIF2_CAP))
continue;
if (!strncmp(w->sname,
tabla_dai[j].playback.stream_name, 13)) {
@@ -4007,6 +4159,9 @@
/* Execute the callback only if interface type is slimbus */
if (tabla_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
return 0;
+
+ pr_debug("%s(): %s %d\n", __func__, w->name, event);
+
switch (event) {
case SND_SOC_DAPM_POST_PMU:
for (j = 0; j < ARRAY_SIZE(tabla_dai); j++) {
@@ -4137,13 +4292,13 @@
, tabla_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MIXER_E("RX1 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
+ SND_SOC_DAPM_MIXER_E("RX1 MIX2", TABLA_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
- SND_SOC_DAPM_MIXER_E("RX2 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
+ SND_SOC_DAPM_MIXER_E("RX2 MIX2", TABLA_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
- SND_SOC_DAPM_MIXER_E("RX3 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
+ SND_SOC_DAPM_MIXER_E("RX3 MIX2", TABLA_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER_E("RX4 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 3, 0, NULL,
@@ -4159,6 +4314,10 @@
0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+
SND_SOC_DAPM_MUX_E("RX4 DSM MUX", TABLA_A_CDC_CLK_RX_B1_CTL, 3, 0,
&rx4_dsm_mux, tabla_codec_reset_interpolator,
SND_SOC_DAPM_PRE_PMU),
@@ -4198,6 +4357,18 @@
&rx7_mix1_inp1_mux),
SND_SOC_DAPM_MUX("RX7 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx7_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp2_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp2_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx3_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx3_mix2_inp2_mux),
SND_SOC_DAPM_SUPPLY("CP", TABLA_A_CP_EN, 0, 0,
tabla_codec_enable_charge_pump, SND_SOC_DAPM_POST_PMU |
@@ -4340,16 +4511,34 @@
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, 0, 0, &sb_tx1_mux),
- SND_SOC_DAPM_AIF_OUT("SLIM TX1", "AIF1 Capture", NULL, SND_SOC_NOPM,
- 0, 0),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX1", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, 0, 0, &sb_tx2_mux),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX2", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, 0, 0, &sb_tx3_mux),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX3", "AIF1 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, 0, 0, &sb_tx4_mux),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX4", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, 0, 0, &sb_tx5_mux),
- SND_SOC_DAPM_AIF_OUT("SLIM TX5", "AIF1 Capture", NULL, SND_SOC_NOPM,
- 4, 0),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX5", "AIF1 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, 0, 0, &sb_tx6_mux),
- SND_SOC_DAPM_AIF_OUT("SLIM TX6", "AIF1 Capture", NULL, SND_SOC_NOPM,
- 5, 0),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX6", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, 0, 0, &sb_tx7_mux),
SND_SOC_DAPM_AIF_OUT_E("SLIM TX7", "AIF1 Capture", 0, SND_SOC_NOPM, 0,
@@ -5238,8 +5427,9 @@
return true;
}
+/* called under codec_resource_lock acquisition */
static int tabla_determine_button(const struct tabla_priv *priv,
- const s32 bias_mv)
+ const s32 micmv)
{
s16 *v_btn_low, *v_btn_high;
struct tabla_mbhc_btn_detect_cfg *btn_det;
@@ -5249,8 +5439,9 @@
v_btn_low = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_V_BTN_LOW);
v_btn_high = tabla_mbhc_cal_btn_det_mp(btn_det,
TABLA_BTN_DET_V_BTN_HIGH);
+
for (i = 0; i < btn_det->num_btn; i++) {
- if ((v_btn_low[i] <= bias_mv) && (v_btn_high[i] >= bias_mv)) {
+ if ((v_btn_low[i] <= micmv) && (v_btn_high[i] >= micmv)) {
btn = i;
break;
}
@@ -5258,7 +5449,7 @@
if (btn == -1)
pr_debug("%s: couldn't find button number for mic mv %d\n",
- __func__, bias_mv);
+ __func__, micmv);
return btn;
}
@@ -5298,8 +5489,9 @@
static irqreturn_t tabla_dce_handler(int irq, void *data)
{
int i, mask;
- short dce, sta, bias_value_dce;
- s32 mv, stamv, bias_mv_dce;
+ short dce, sta;
+ s32 mv, mv_s, stamv_s;
+ bool vddio;
int btn = -1, meas = 0;
struct tabla_priv *priv = data;
const struct tabla_mbhc_btn_detect_cfg *d =
@@ -5338,6 +5530,10 @@
goto done;
}
+ vddio = (priv->mbhc_data.micb_mv != VDDIO_MICBIAS_MV &&
+ priv->mbhc_micbias_switched);
+ mv_s = vddio ? tabla_scale_v_micb_vddio(priv, mv, false) : mv;
+
if (mbhc_status != TABLA_MBHC_STATUS_REL_DETECTION) {
if (priv->mbhc_last_resume &&
!time_after(jiffies, priv->mbhc_last_resume + HZ)) {
@@ -5348,27 +5544,32 @@
pr_debug("%s: Button is already released without "
"resume", __func__);
sta = tabla_codec_read_sta_result(codec);
- stamv = tabla_codec_sta_dce_v(codec, 0, sta);
- btn = tabla_determine_button(priv, mv);
- if (btn != tabla_determine_button(priv, stamv))
+ stamv_s = tabla_codec_sta_dce_v(codec, 0, sta);
+ if (vddio)
+ stamv_s = tabla_scale_v_micb_vddio(priv,
+ stamv_s,
+ false);
+ btn = tabla_determine_button(priv, mv_s);
+ if (btn != tabla_determine_button(priv, stamv_s))
btn = -1;
goto done;
}
}
/* determine pressed button */
- btnmeas[meas++] = tabla_determine_button(priv, mv);
- pr_debug("%s: meas %d - DCE %d,%d, button %d\n", __func__,
- meas - 1, dce, mv, btnmeas[meas - 1]);
+ btnmeas[meas++] = tabla_determine_button(priv, mv_s);
+ pr_debug("%s: meas %d - DCE %d,%d,%d button %d\n", __func__,
+ meas - 1, dce, mv, mv_s, btnmeas[meas - 1]);
if (n_btn_meas == 0)
btn = btnmeas[0];
for (; ((d->n_btn_meas) && (meas < (d->n_btn_meas + 1))); meas++) {
- bias_value_dce = tabla_codec_sta_dce(codec, 1, false);
- bias_mv_dce = tabla_codec_sta_dce_v(codec, 1, bias_value_dce);
- btnmeas[meas] = tabla_determine_button(priv, bias_mv_dce);
- pr_debug("%s: meas %d - DCE %d,%d, button %d\n",
- __func__, meas, bias_value_dce, bias_mv_dce,
- btnmeas[meas]);
+ dce = tabla_codec_sta_dce(codec, 1, false);
+ mv = tabla_codec_sta_dce_v(codec, 1, dce);
+ mv_s = vddio ? tabla_scale_v_micb_vddio(priv, mv, false) : mv;
+
+ btnmeas[meas] = tabla_determine_button(priv, mv_s);
+ pr_debug("%s: meas %d - DCE %d,%d,%d button %d\n",
+ __func__, meas, dce, mv, mv_s, btnmeas[meas]);
/* if large enough measurements are collected,
* start to check if last all n_btn_con measurements were
* in same button low/high range */
@@ -5618,7 +5819,7 @@
}
static bool tabla_is_invalid_insertion_range(struct snd_soc_codec *codec,
- s32 mic_volt)
+ s32 mic_volt, bool highhph)
{
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
bool invalid = false;
@@ -5628,7 +5829,7 @@
* needs to be considered as invalid
*/
v_hs_max = tabla_get_current_v_hs_max(tabla);
- if (!tabla->mbhc_inval_hs_range_override && (mic_volt > v_hs_max))
+ if (!highhph && (mic_volt > v_hs_max))
invalid = true;
else if (mic_volt < tabla->mbhc_data.v_inval_ins_high &&
(mic_volt > tabla->mbhc_data.v_inval_ins_low))
@@ -5649,40 +5850,6 @@
return false;
}
-static bool tabla_codec_is_invalid_plug(struct snd_soc_codec *codec,
- s32 mic_mv[MBHC_NUM_DCE_PLUG_DETECT],
- enum tabla_mbhc_plug_type
- plug_type[MBHC_NUM_DCE_PLUG_DETECT])
-{
- int i;
- bool r = false;
- struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
- struct tabla_mbhc_plug_type_cfg *plug_type_ptr =
- TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
- s16 v_hs_max = tabla_get_current_v_hs_max(tabla);
-
- for (i = 0 ; i < MBHC_NUM_DCE_PLUG_DETECT && !r; i++) {
- if (mic_mv[i] < plug_type_ptr->v_no_mic)
- plug_type[i] = PLUG_TYPE_HEADPHONE;
- else if (mic_mv[i] < v_hs_max)
- plug_type[i] = PLUG_TYPE_HEADSET;
- else if (mic_mv[i] > v_hs_max)
- plug_type[i] = PLUG_TYPE_HIGH_HPH;
-
- r = tabla_is_invalid_insertion_range(codec, mic_mv[i]);
- if (!r && i > 0) {
- if (plug_type[i-1] != plug_type[i])
- r = true;
- else
- r = tabla_is_inval_insert_delta(codec,
- mic_mv[i], mic_mv[i - 1],
- TABLA_MBHC_FAKE_INS_DELTA_MV);
- }
- }
-
- return r;
-}
-
/* called under codec_resource_lock acquisition */
void tabla_find_plug_and_report(struct snd_soc_codec *codec,
enum tabla_mbhc_plug_type plug_type)
@@ -5745,15 +5912,127 @@
tabla->mbhc_cfg.gpio_level_insert);
}
+/* called under codec_resource_lock acquisition */
+static void tabla_codec_hphr_gnd_switch(struct snd_soc_codec *codec, bool on)
+{
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x01, on);
+ if (on)
+ usleep_range(5000, 5000);
+}
+
+/* called under codec_resource_lock acquisition and mbhc override = 1 */
+static enum tabla_mbhc_plug_type
+tabla_codec_get_plug_type(struct snd_soc_codec *codec, bool highhph)
+{
+ int i;
+ bool gndswitch, vddioswitch;
+ int scaled;
+ struct tabla_mbhc_plug_type_cfg *plug_type_ptr;
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ const bool vddio = (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV);
+ int num_det = (MBHC_NUM_DCE_PLUG_DETECT + vddio);
+ enum tabla_mbhc_plug_type plug_type[num_det];
+ s16 mb_v[num_det];
+ s32 mic_mv[num_det];
+ bool inval = false;
+
+ /* make sure override is on */
+ WARN_ON(!(snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x04));
+
+ /* performs DCEs for N times
+ * 1st: check if voltage is in invalid range
+ * 2nd - N-2nd: check voltage range and delta
+ * N-1st: check voltage range, delta with HPHR GND switch
+ * Nth: check voltage range with VDDIO switch if micbias V != vddio V*/
+ for (i = 0; i < num_det && !inval; i++) {
+ gndswitch = (i == (num_det - 1 - vddio));
+ vddioswitch = (vddio && (i == num_det - 1));
+ if (i == 0) {
+ mb_v[i] = tabla_codec_setup_hs_polling(codec);
+ mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
+ inval = tabla_is_invalid_insertion_range(codec,
+ mic_mv[i],
+ highhph);
+ scaled = mic_mv[i];
+ } else if (vddioswitch) {
+ __tabla_codec_switch_micbias(tabla->codec, 1, false,
+ false);
+ mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
+ mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
+ scaled = tabla_scale_v_micb_vddio(tabla, mic_mv[i],
+ false);
+ inval = (tabla_is_invalid_insertion_range(codec,
+ mic_mv[i],
+ highhph) ||
+ tabla_is_inval_insert_delta(codec, scaled,
+ mic_mv[i - 1],
+ TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV));
+ __tabla_codec_switch_micbias(tabla->codec, 0, false,
+ false);
+ } else {
+ if (gndswitch)
+ tabla_codec_hphr_gnd_switch(codec, true);
+ mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
+ mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
+ inval = (tabla_is_invalid_insertion_range(codec,
+ mic_mv[i],
+ highhph) ||
+ tabla_is_inval_insert_delta(codec, mic_mv[i],
+ mic_mv[i - 1],
+ TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV));
+ if (gndswitch)
+ tabla_codec_hphr_gnd_switch(codec, false);
+ scaled = mic_mv[i];
+ }
+ pr_debug("%s: DCE #%d, %04x, V %d, scaled V %d, GND %d, "
+ "invalid %d\n", __func__,
+ i + 1, mb_v[i] & 0xffff, mic_mv[i], scaled, gndswitch,
+ inval);
+ }
+
+ plug_type_ptr =
+ TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
+ plug_type[0] = PLUG_TYPE_INVALID;
+ for (i = 0; !inval && i < num_det; i++) {
+ /*
+ * If we are here, means none of the all
+ * measurements are fake, continue plug type detection.
+ * If all three measurements do not produce same
+ * plug type, restart insertion detection
+ */
+ if (mic_mv[i] < plug_type_ptr->v_no_mic) {
+ plug_type[i] = PLUG_TYPE_HEADPHONE;
+ pr_debug("%s: Detect attempt %d, detected Headphone\n",
+ __func__, i);
+ } else if (highhph && (mic_mv[i] > plug_type_ptr->v_hs_max)) {
+ plug_type[i] = PLUG_TYPE_HIGH_HPH;
+ pr_debug("%s: Detect attempt %d, detected High "
+ "Headphone\n", __func__, i);
+ } else {
+ plug_type[i] = PLUG_TYPE_HEADSET;
+ pr_debug("%s: Detect attempt %d, detected Headset\n",
+ __func__, i);
+ }
+
+ if (i > 0 && (plug_type[i - 1] != plug_type[i])) {
+ pr_err("%s: Detect attempt %d and %d are not same",
+ __func__, i - 1, i);
+ plug_type[0] = PLUG_TYPE_INVALID;
+ inval = true;
+ break;
+ }
+ }
+
+ return plug_type[0];
+}
+
static void tabla_hs_correct_gpio_plug(struct work_struct *work)
{
struct tabla_priv *tabla;
struct snd_soc_codec *codec;
- int retry = 0, i;
+ int retry = 0;
bool correction = false;
- s32 mic_mv[MBHC_NUM_DCE_PLUG_DETECT];
- short mb_v[MBHC_NUM_DCE_PLUG_DETECT];
- enum tabla_mbhc_plug_type plug_type[MBHC_NUM_DCE_PLUG_DETECT];
+ enum tabla_mbhc_plug_type plug_type;
unsigned long timeout;
tabla = container_of(work, struct tabla_priv, hs_correct_plug_work);
@@ -5790,24 +6069,17 @@
/* can race with removal interrupt */
TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
- for (i = 0; i < MBHC_NUM_DCE_PLUG_DETECT; i++) {
- mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
- mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
- pr_debug("%s : DCE run %d, mic_mv = %d(%x)\n",
- __func__, retry, mic_mv[i], mb_v[i]);
- }
+ plug_type = tabla_codec_get_plug_type(codec, true);
TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
- if (tabla_codec_is_invalid_plug(codec, mic_mv, plug_type)) {
+ if (plug_type == PLUG_TYPE_INVALID) {
pr_debug("Invalid plug in attempt # %d\n", retry);
if (retry == NUM_ATTEMPTS_TO_REPORT &&
tabla->current_plug == PLUG_TYPE_NONE) {
tabla_codec_report_plug(codec, 1,
SND_JACK_HEADPHONE);
}
- } else if (!tabla_codec_is_invalid_plug(codec, mic_mv,
- plug_type) &&
- plug_type[0] == PLUG_TYPE_HEADPHONE) {
+ } else if (plug_type == PLUG_TYPE_HEADPHONE) {
pr_debug("Good headphone detected, continue polling mic\n");
if (tabla->current_plug == PLUG_TYPE_NONE) {
tabla_codec_report_plug(codec, 1,
@@ -5817,10 +6089,10 @@
TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
/* Turn off override */
tabla_turn_onoff_override(codec, false);
- tabla_find_plug_and_report(codec, plug_type[0]);
+ tabla_find_plug_and_report(codec, plug_type);
TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
pr_debug("Attempt %d found correct plug %d\n", retry,
- plug_type[0]);
+ plug_type);
correction = true;
break;
}
@@ -5840,24 +6112,12 @@
static void tabla_codec_decide_gpio_plug(struct snd_soc_codec *codec)
{
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
- short mb_v[MBHC_NUM_DCE_PLUG_DETECT];
- s32 mic_mv[MBHC_NUM_DCE_PLUG_DETECT];
- enum tabla_mbhc_plug_type plug_type[MBHC_NUM_DCE_PLUG_DETECT];
- int i;
+ enum tabla_mbhc_plug_type plug_type;
pr_debug("%s: enter\n", __func__);
tabla_turn_onoff_override(codec, true);
- mb_v[0] = tabla_codec_setup_hs_polling(codec);
- mic_mv[0] = tabla_codec_sta_dce_v(codec, 1, mb_v[0]);
- pr_debug("%s: DCE run 1, mic_mv = %d\n", __func__, mic_mv[0]);
-
- for (i = 1; i < MBHC_NUM_DCE_PLUG_DETECT; i++) {
- mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
- mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
- pr_debug("%s: DCE run %d, mic_mv = %d\n", __func__, i + 1,
- mic_mv[i]);
- }
+ plug_type = tabla_codec_get_plug_type(codec, true);
tabla_turn_onoff_override(codec, false);
if (tabla_hs_gpio_level_remove(tabla)) {
@@ -5866,48 +6126,26 @@
return;
}
- if (tabla_codec_is_invalid_plug(codec, mic_mv, plug_type)) {
+ if (plug_type == PLUG_TYPE_INVALID) {
tabla_schedule_hs_detect_plug(tabla);
- } else if (plug_type[0] == PLUG_TYPE_HEADPHONE) {
+ } else if (plug_type == PLUG_TYPE_HEADPHONE) {
tabla_codec_report_plug(codec, 1, SND_JACK_HEADPHONE);
tabla_schedule_hs_detect_plug(tabla);
} else {
- pr_debug("%s: Valid plug found, determine plug type\n",
- __func__);
- tabla_find_plug_and_report(codec, plug_type[0]);
- }
-}
-
-/* called under codec_resource_lock acquisition */
-static void tabla_codec_hphr_gnd_switch(struct snd_soc_codec *codec, bool on)
-{
- struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
-
- if (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) {
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x01, on);
- if (on)
- usleep_range(5000, 5000);
+ pr_debug("%s: Valid plug found, determine plug type %d\n",
+ __func__, plug_type);
+ tabla_find_plug_and_report(codec, plug_type);
}
}
/* called under codec_resource_lock acquisition */
static void tabla_codec_detect_plug_type(struct snd_soc_codec *codec)
{
- int i;
- bool gndswitch, vddioswitch;
- int scaled;
+ enum tabla_mbhc_plug_type plug_type;
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
const struct tabla_mbhc_plug_detect_cfg *plug_det =
TABLA_MBHC_CAL_PLUG_DET_PTR(tabla->mbhc_cfg.calibration);
- struct tabla_mbhc_plug_type_cfg *plug_type_ptr;
- const bool vddio = (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV &&
- !tabla->mbhc_micbias_switched);
- int num_det = (MBHC_NUM_DCE_PLUG_DETECT + vddio);
- enum tabla_mbhc_plug_type plug_type[num_det];
- short mb_v[num_det];
- s32 mic_mv[num_det];
- bool inval = false;
/* Turn on the override,
* tabla_codec_setup_hs_polling requires override on */
@@ -5930,84 +6168,11 @@
return;
}
- /* performs DCEs for N times
- * 1st: check if voltage is in invalid range
- * 2nd - N-2nd: check voltage range and delta
- * N-1st: check voltage range, delta with HPHR GND switch
- * Nth: check voltage range with VDDIO switch if micbias V != vddio V*/
- for (i = 0; i < num_det && !inval; i++) {
- gndswitch = (i == (num_det - 1 - vddio));
- vddioswitch = (vddio && (i == num_det - 1));
- if (i == 0) {
- mb_v[i] = tabla_codec_setup_hs_polling(codec);
- mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
- inval = tabla_is_invalid_insertion_range(codec,
- mic_mv[i]);
- scaled = mic_mv[i];
- } else if (vddioswitch) {
- __tabla_codec_switch_micbias(tabla->codec, 1, false,
- false);
- mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
- mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
- scaled = tabla_scale_v_micb_vddio(tabla, mic_mv[i],
- false);
- inval = (tabla_is_invalid_insertion_range(codec,
- mic_mv[i]) ||
- tabla_is_inval_insert_delta(codec, scaled,
- mic_mv[i - 1],
- TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV));
- __tabla_codec_switch_micbias(tabla->codec, 0, false,
- false);
- } else {
- if (gndswitch)
- tabla_codec_hphr_gnd_switch(codec, true);
- mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
- mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
- inval = (tabla_is_invalid_insertion_range(codec,
- mic_mv[i]) ||
- tabla_is_inval_insert_delta(codec, mic_mv[i],
- mic_mv[i - 1],
- TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV));
- if (gndswitch)
- tabla_codec_hphr_gnd_switch(codec, false);
- scaled = mic_mv[i];
- }
- pr_debug("%s: DCE #%d, %04x, V %d, scaled V %d, GND %d, "
- "invalid %d\n", __func__,
- i + 1, mb_v[i] & 0xffff, mic_mv[i], scaled, gndswitch,
- inval);
- }
+ plug_type = tabla_codec_get_plug_type(codec, tabla->mbhc_cfg.gpio ?
+ true : false);
tabla_turn_onoff_override(codec, false);
- plug_type_ptr =
- TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
-
- for (i = 0; !inval && i < num_det; i++) {
- /*
- * If we are here, means none of the all
- * measurements are fake, continue plug type detection.
- * If all three measurements do not produce same
- * plug type, restart insertion detection
- */
- if (mic_mv[i] < plug_type_ptr->v_no_mic) {
- plug_type[i] = PLUG_TYPE_HEADPHONE;
- pr_debug("%s: Detect attempt %d, detected Headphone\n",
- __func__, i);
- } else {
- plug_type[i] = PLUG_TYPE_HEADSET;
- pr_debug("%s: Detect attempt %d, detected Headset\n",
- __func__, i);
- }
-
- if (i > 0 && (plug_type[i - 1] != plug_type[i])) {
- pr_err("%s: Detect attempt %d and %d are not same",
- __func__, i - 1, i);
- inval = true;
- break;
- }
- }
-
- if (inval) {
+ if (plug_type == PLUG_TYPE_INVALID) {
pr_debug("%s: Invalid plug type detected\n", __func__);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL,
0x02, 0x02);
@@ -6015,12 +6180,12 @@
tabla_codec_enable_hs_detect(codec, 1,
MBHC_USE_MB_TRIGGER |
MBHC_USE_HPHL_TRIGGER, false);
- } else if (plug_type[0] == PLUG_TYPE_HEADPHONE) {
+ } else if (plug_type == PLUG_TYPE_HEADPHONE) {
pr_debug("%s: Headphone Detected\n", __func__);
tabla_codec_report_plug(codec, 1, SND_JACK_HEADPHONE);
tabla_codec_cleanup_hs_polling(codec);
tabla_codec_enable_hs_detect(codec, 0, 0, false);
- } else if (plug_type[0] == PLUG_TYPE_HEADSET) {
+ } else if (plug_type == PLUG_TYPE_HEADSET) {
pr_debug("%s: Headset detected\n", __func__);
tabla_codec_report_plug(codec, 1, SND_JACK_HEADSET);
@@ -6490,7 +6655,6 @@
tabla->mbhc_cfg.mclk_cb_fn(codec, 0, false);
tabla_codec_calibrate_hs_polling(codec);
if (!tabla->mbhc_cfg.gpio) {
- tabla->mbhc_inval_hs_range_override = false;
rc = tabla_codec_enable_hs_detect(codec, 1,
MBHC_USE_MB_TRIGGER |
MBHC_USE_HPHL_TRIGGER,
@@ -6500,7 +6664,6 @@
pr_err("%s: Failed to setup MBHC detection\n",
__func__);
} else {
- tabla->mbhc_inval_hs_range_override = true;
/* Enable Mic Bias pull down and HPH Switch to GND */
snd_soc_update_bits(codec,
tabla->mbhc_bias_regs.ctl_reg, 0x01,
@@ -6558,13 +6721,11 @@
tabla->mbhc_cfg.mclk_cb_fn(codec, 0, false);
tabla_codec_calibrate_hs_polling(codec);
if (!tabla->mbhc_cfg.gpio) {
- tabla->mbhc_inval_hs_range_override = false;
rc = tabla_codec_enable_hs_detect(codec, 1,
MBHC_USE_MB_TRIGGER |
MBHC_USE_HPHL_TRIGGER,
false);
} else {
- tabla->mbhc_inval_hs_range_override = true;
/* Enable Mic Bias pull down and HPH Switch to GND */
snd_soc_update_bits(codec,
tabla->mbhc_bias_regs.ctl_reg, 0x01,
@@ -7242,6 +7403,9 @@
case AIF2_PB:
ch_cnt = tabla_dai[i].playback.channels_max;
break;
+ case AIF2_CAP:
+ ch_cnt = tabla_dai[i].capture.channels_max;
+ break;
default:
continue;
}
diff --git a/sound/soc/msm/apq8064.c b/sound/soc/msm/apq8064.c
index 26e4263..3d489ff 100644
--- a/sound/soc/msm/apq8064.c
+++ b/sound/soc/msm/apq8064.c
@@ -63,9 +63,14 @@
SLIM_1_RX_1 = 145, /* BT-SCO and USB TX */
SLIM_1_TX_1 = 146, /* BT-SCO and USB RX */
SLIM_2_RX_1 = 147, /* HDMI RX */
- SLIM_3_RX_1 = 148, /* In-call recording RX */
- SLIM_3_RX_2 = 149, /* In-call recording RX */
- SLIM_4_TX_1 = 150, /* In-call musid delivery TX */
+ SLIM_4_TX_1 = 148, /* In-call recording RX */
+ SLIM_4_TX_2 = 149, /* In-call recording RX */
+ SLIM_4_RX_1 = 150, /* In-call music delivery TX */
+};
+
+enum {
+ INCALL_REC_MONO,
+ INCALL_REC_STEREO,
};
static u32 top_spk_pamp_gpio = PM8921_GPIO_PM_TO_SYS(18);
@@ -79,6 +84,8 @@
static int msm_btsco_rate = BTSCO_RATE_8KHZ;
static int msm_btsco_ch = 1;
+static int rec_mode = INCALL_REC_MONO;
+
static struct clk *codec_clk;
static int clk_users;
@@ -404,7 +411,7 @@
return 0;
}
-static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
+static const struct snd_soc_dapm_widget apq8064_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
msm_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
@@ -415,26 +422,33 @@
SND_SOC_DAPM_SPK("Ext Spk Top Pos", msm_spkramp_event),
SND_SOC_DAPM_SPK("Ext Spk Top Neg", msm_spkramp_event),
- SND_SOC_DAPM_MIC("Handset Mic", NULL),
+ /************ Analog MICs ************/
+ /**
+ * Analog mic7 (Front Top) on Liquid.
+ * Used as Handset mic on CDP.
+ */
+ SND_SOC_DAPM_MIC("Analog mic7", NULL),
+
SND_SOC_DAPM_MIC("Headset Mic", NULL),
- SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL),
SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL),
+ /*********** Digital Mics ***************/
SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("Digital Mic2", NULL),
SND_SOC_DAPM_MIC("Digital Mic3", NULL),
SND_SOC_DAPM_MIC("Digital Mic4", NULL),
SND_SOC_DAPM_MIC("Digital Mic5", NULL),
SND_SOC_DAPM_MIC("Digital Mic6", NULL),
-
};
-static const struct snd_soc_dapm_route common_audio_map[] = {
+static const struct snd_soc_dapm_route apq8064_audio_map[] = {
{"RX_BIAS", NULL, "MCLK"},
{"LDO_H", NULL, "MCLK"},
+ {"HEADPHONE", NULL, "LDO_H"},
+
/* Speaker path */
{"Ext Spk Bottom Pos", NULL, "LINEOUT1"},
{"Ext Spk Bottom Neg", NULL, "LINEOUT3"},
@@ -442,77 +456,85 @@
{"Ext Spk Top Pos", NULL, "LINEOUT2"},
{"Ext Spk Top Neg", NULL, "LINEOUT4"},
- /* Microphone path */
- {"AMIC1", NULL, "MIC BIAS1 Internal1"},
- {"MIC BIAS1 Internal1", NULL, "Handset Mic"},
+ /************ Analog MIC Paths ************/
+ /**
+ * Analog mic7 (Front Top Mic) on Liquid.
+ * Used as Handset mic on CDP.
+ * Not there on MTP.
+ */
+ {"AMIC1", NULL, "MIC BIAS1 External"},
+ {"MIC BIAS1 External", NULL, "Analog mic7"},
+ /* Headset Mic */
{"AMIC2", NULL, "MIC BIAS2 External"},
{"MIC BIAS2 External", NULL, "Headset Mic"},
- /**
- * AMIC3 and AMIC4 inputs are connected to ANC microphones
- * These mics are biased differently on CDP and FLUID
- * routing entries below are based on bias arrangement
- * on FLUID.
- */
+ /* Headset ANC microphones */
{"AMIC3", NULL, "MIC BIAS3 Internal1"},
{"MIC BIAS3 Internal1", NULL, "ANCRight Headset Mic"},
{"AMIC4", NULL, "MIC BIAS1 Internal2"},
{"MIC BIAS1 Internal2", NULL, "ANCLeft Headset Mic"},
- {"HEADPHONE", NULL, "LDO_H"},
+ /************ Digital MIC Paths ************/
/**
* The digital Mic routes are setup considering
- * fluid as default device.
+ * Liquid as default device.
*/
/**
- * Digital Mic1. Front Bottom left Digital Mic on Fluid and MTP.
- * Digital Mic GM5 on CDP mainboard.
+ * Digital Mic1 (Front bottom left corner) on Liquid.
+ * Digital Mic2 (Front bottom right) on MTP.
+ * Digital Mic GM1 on CDP mainboard.
* Conncted to DMIC2 Input on Tabla codec.
*/
{"DMIC2", NULL, "MIC BIAS1 External"},
{"MIC BIAS1 External", NULL, "Digital Mic1"},
/**
- * Digital Mic2. Front Bottom right Digital Mic on Fluid and MTP.
- * Digital Mic GM6 on CDP mainboard.
- * Conncted to DMIC1 Input on Tabla codec.
- */
- {"DMIC1", NULL, "MIC BIAS1 External"},
- {"MIC BIAS1 External", NULL, "Digital Mic2"},
-
- /**
- * Digital Mic3. Back Bottom Digital Mic on Fluid.
- * Digital Mic GM1 on CDP mainboard.
- * Conncted to DMIC4 Input on Tabla codec.
- */
- {"DMIC4", NULL, "MIC BIAS3 External"},
- {"MIC BIAS3 External", NULL, "Digital Mic3"},
-
- /**
- * Digital Mic4. Back top Digital Mic on Fluid.
+ * Digital Mic2 (Front left side) on Liquid.
* Digital Mic GM2 on CDP mainboard.
+ * Not there on MTP.
* Conncted to DMIC3 Input on Tabla codec.
*/
{"DMIC3", NULL, "MIC BIAS3 External"},
- {"MIC BIAS3 External", NULL, "Digital Mic4"},
+ {"MIC BIAS3 External", NULL, "Digital Mic2"},
/**
- * Digital Mic5. Front top Digital Mic on Fluid.
+ * Digital Mic3. Front bottom left of middle on Liquid.
+ * Digital Mic5 (Top front Mic) on MTP.
+ * Digital Mic GM5 on CDP mainboard.
+ * Conncted to DMIC6 Input on Tabla codec.
+ */
+ {"DMIC6", NULL, "MIC BIAS4 External"},
+ {"MIC BIAS4 External", NULL, "Digital Mic3"},
+
+ /**
+ * Digital Mic4. Back bottom on Liquid.
* Digital Mic GM3 on CDP mainboard.
+ * Top Front Mic on MTP.
* Conncted to DMIC5 Input on Tabla codec.
*/
{"DMIC5", NULL, "MIC BIAS4 External"},
- {"MIC BIAS4 External", NULL, "Digital Mic5"},
+ {"MIC BIAS4 External", NULL, "Digital Mic4"},
- /* Tabla digital Mic6 - back bottom digital Mic on Liquid and
- * bottom mic on CDP. FLUID/MTP do not have dmic6 installed.
+ /**
+ * Digital Mic5. Front bottom right of middle on Liquid.
+ * Digital Mic GM6 on CDP mainboard.
+ * Not there on MTP.
+ * Conncted to DMIC4 Input on Tabla codec.
*/
- {"DMIC6", NULL, "MIC BIAS4 External"},
- {"MIC BIAS4 External", NULL, "Digital Mic6"},
+ {"DMIC4", NULL, "MIC BIAS3 External"},
+ {"MIC BIAS3 External", NULL, "Digital Mic5"},
+
+ /* Digital Mic6 (Front bottom right corner) on Liquid.
+ * Digital Mic1 (Front bottom Left) on MTP.
+ * Digital Mic GM4 on CDP.
+ * Conncted to DMIC1 Input on Tabla codec.
+ */
+ {"DMIC1", NULL, "MIC BIAS1 External"},
+ {"MIC BIAS1 External", NULL, "Digital Mic6"},
};
static const char *spk_function[] = {"Off", "On"};
@@ -596,6 +618,23 @@
return 0;
}
+static int msm_incall_rec_mode_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = rec_mode;
+ return 0;
+}
+
+static int msm_incall_rec_mode_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+
+ rec_mode = ucontrol->value.integer.value[0];
+ pr_debug("%s: rec_mode:%d\n", __func__, rec_mode);
+
+ return 0;
+}
+
static const struct snd_kcontrol_new tabla_msm_controls[] = {
SOC_ENUM_EXT("Speaker Function", msm_enum[0], msm_get_spk,
msm_set_spk),
@@ -610,6 +649,11 @@
msm_btsco_rate_get, msm_btsco_rate_put),
};
+static const struct snd_kcontrol_new incall_rec_mode_mixer_controls[] = {
+ SOC_SINGLE_EXT("Incall Rec Mode", SND_SOC_NOPM, 0, 1, 0,
+ msm_incall_rec_mode_get, msm_incall_rec_mode_put),
+};
+
static int msm_btsco_init(struct snd_soc_pcm_runtime *rtd)
{
int err = 0;
@@ -623,6 +667,19 @@
return 0;
}
+static int msm_incall_rec_init(struct snd_soc_pcm_runtime *rtd)
+{
+ int err = 0;
+ struct snd_soc_platform *platform = rtd->platform;
+
+ err = snd_soc_add_platform_controls(platform,
+ incall_rec_mode_mixer_controls,
+ ARRAY_SIZE(incall_rec_mode_mixer_controls));
+ if (err < 0)
+ return err;
+ return 0;
+}
+
static void *def_tabla_mbhc_cal(void)
{
void *tabla_cal;
@@ -709,10 +766,13 @@
int ret = 0;
unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
+ unsigned int user_set_tx_ch = 0;
- pr_debug("%s: ch=%d\n", __func__,
- msm_slim_0_rx_ch);
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+
+ pr_debug("%s: rx_0_ch=%d\n", __func__, msm_slim_0_rx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
@@ -734,20 +794,30 @@
goto end;
}
} else {
+
+ if (codec_dai->id == 2)
+ user_set_tx_ch = msm_slim_0_tx_ch;
+ else if (codec_dai->id == 4)
+ user_set_tx_ch = params_channels(params);
+
+ pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
+ codec_dai->name, codec_dai->id, user_set_tx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
pr_err("%s: failed to get codec chan map\n", __func__);
goto end;
}
+
ret = snd_soc_dai_set_channel_map(cpu_dai,
- msm_slim_0_tx_ch, tx_ch, 0 , 0);
+ user_set_tx_ch, tx_ch, 0 , 0);
if (ret < 0) {
pr_err("%s: failed to set cpu chan map\n", __func__);
goto end;
}
ret = snd_soc_dai_set_channel_map(codec_dai,
- msm_slim_0_tx_ch, tx_ch, 0, 0);
+ user_set_tx_ch, tx_ch, 0, 0);
if (ret < 0) {
pr_err("%s: failed to set codec channel map\n",
__func__);
@@ -803,6 +873,49 @@
return ret;
}
+static int msm_slimbus_4_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ int ret = 0;
+ unsigned int rx_ch = SLIM_4_RX_1, tx_ch[2];
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ pr_debug("%s: APQ Incall Playback SLIMBUS_4_RX -> MDM TX shared ch %d\n",
+ __func__, rx_ch);
+
+ ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, 1, &rx_ch);
+ if (ret < 0) {
+ pr_err("%s: Erorr %d setting SLIM_4 RX channel map\n",
+ __func__, ret);
+
+ }
+ } else {
+ if (rec_mode == INCALL_REC_STEREO) {
+ tx_ch[0] = SLIM_4_TX_1;
+ tx_ch[1] = SLIM_4_TX_2;
+ ret = snd_soc_dai_set_channel_map(cpu_dai, 2,
+ tx_ch, 0, 0);
+ } else {
+ tx_ch[0] = SLIM_4_TX_1;
+ ret = snd_soc_dai_set_channel_map(cpu_dai, 1,
+ tx_ch, 0, 0);
+ }
+ pr_debug("%s: Incall Record shared tx_ch[0]:%d, tx_ch[1]:%d\n",
+ __func__, tx_ch[0], tx_ch[1]);
+
+ if (ret < 0) {
+ pr_err("%s: Erorr %d setting SLIM_4 TX channel map\n",
+ __func__, ret);
+
+ }
+ }
+
+ return ret;
+}
+
+
static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
{
int err;
@@ -824,11 +937,11 @@
if (err < 0)
return err;
- snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
- ARRAY_SIZE(msm_dapm_widgets));
+ snd_soc_dapm_new_controls(dapm, apq8064_dapm_widgets,
+ ARRAY_SIZE(apq8064_dapm_widgets));
- snd_soc_dapm_add_routes(dapm, common_audio_map,
- ARRAY_SIZE(common_audio_map));
+ snd_soc_dapm_add_routes(dapm, apq8064_audio_map,
+ ARRAY_SIZE(apq8064_audio_map));
snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
@@ -1090,6 +1203,12 @@
.shutdown = msm_shutdown,
};
+static struct snd_soc_ops msm_slimbus_4_be_ops = {
+ .startup = msm_startup,
+ .hw_params = msm_slimbus_4_hw_params,
+ .shutdown = msm_shutdown,
+};
+
/* Digital audio interface glue - connects codec <---> CPU */
static struct snd_soc_dai_link msm_dai[] = {
/* FrontEnd DAI Links */
@@ -1374,6 +1493,46 @@
.be_hw_params_fixup = msm_btsco_be_hw_params_fixup,
.ops = &msm_slimbus_1_be_ops,
},
+ {
+ .name = "SLIMBUS_2 Hostless",
+ .stream_name = "SLIMBUS_2 Hostless",
+ .cpu_dai_name = "msm-dai-q6.16389",
+ .platform_name = "msm-pcm-hostless",
+ .codec_name = "tabla_codec",
+ .codec_dai_name = "tabla_tx2",
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ops = &msm_be_ops,
+ },
+
+ /* Incall Music Back End DAI Link */
+ {
+ .name = LPASS_BE_SLIMBUS_4_RX,
+ .stream_name = "Slimbus4 Playback",
+ .cpu_dai_name = "msm-dai-q6.16392",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-rx",
+ .no_pcm = 1,
+ .no_codec = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
+ .be_hw_params_fixup = msm_be_hw_params_fixup,
+ .ops = &msm_slimbus_4_be_ops,
+ },
+ /* Incall Record Back End DAI Link */
+ {
+ .name = LPASS_BE_SLIMBUS_4_TX,
+ .stream_name = "Slimbus4 Capture",
+ .cpu_dai_name = "msm-dai-q6.16393",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .no_pcm = 1,
+ .no_codec = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
+ .be_hw_params_fixup = msm_be_hw_params_fixup,
+ .init = &msm_incall_rec_init,
+ .ops = &msm_slimbus_4_be_ops,
+ },
};
struct snd_soc_card snd_soc_card_msm = {
diff --git a/sound/soc/msm/msm-dai-q6.c b/sound/soc/msm/msm-dai-q6.c
index c876940..b0cfd34 100644
--- a/sound/soc/msm/msm-dai-q6.c
+++ b/sound/soc/msm/msm-dai-q6.c
@@ -281,7 +281,7 @@
dev_dbg(dai->dev, "%s:slimbus_dev_id[%hu] bit_wd[%hu] format[%hu]\n"
"num_channel %hu slave_ch_mapping[0] %hu\n"
"slave_port_mapping[1] %hu slave_port_mapping[2] %hu\n"
- "sample_rate %d\n", __func__,
+ "slave_port_mapping[3] %hu\n sample_rate %d\n", __func__,
dai_data->port_config.slim_sch.slimbus_dev_id,
dai_data->port_config.slim_sch.bit_width,
dai_data->port_config.slim_sch.data_format,
@@ -289,6 +289,7 @@
dai_data->port_config.slim_sch.slave_ch_mapping[0],
dai_data->port_config.slim_sch.slave_ch_mapping[1],
dai_data->port_config.slim_sch.slave_ch_mapping[2],
+ dai_data->port_config.slim_sch.slave_ch_mapping[3],
dai_data->rate);
return 0;
@@ -386,6 +387,9 @@
case SLIMBUS_1_RX:
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
+ case SLIMBUS_4_RX:
+ case SLIMBUS_4_TX:
rc = msm_dai_q6_slim_bus_hw_params(params, dai,
substream->stream);
break;
@@ -883,6 +887,7 @@
switch (dai->id) {
case SLIMBUS_0_RX:
case SLIMBUS_1_RX:
+ case SLIMBUS_4_RX:
/* channel number to be between 128 and 255. For RX port
* use channel numbers from 138 to 144, for TX port
* use channel numbers from 128 to 137
@@ -898,13 +903,16 @@
rx_slot[i]);
}
dai_data->port_config.slim_sch.num_channels = rx_num;
- pr_debug("%s:SLIMBUS_0_RX cnt[%d] ch[%d %d]\n", __func__,
+ pr_debug("%s:SLIMBUS_%d_RX cnt[%d] ch[%d %d]\n", __func__,
+ (dai->id - SLIMBUS_0_RX) / 2,
rx_num, dai_data->port_config.slim_sch.slave_ch_mapping[0],
dai_data->port_config.slim_sch.slave_ch_mapping[1]);
break;
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
+ case SLIMBUS_4_TX:
/* channel number to be between 128 and 255. For RX port
* use channel numbers from 138 to 144, for TX port
* use channel numbers from 128 to 137
@@ -919,7 +927,8 @@
__func__, i, tx_slot[i]);
}
dai_data->port_config.slim_sch.num_channels = tx_num;
- pr_debug("%s:SLIMBUS_0_TX cnt[%d] ch[%d %d]\n", __func__,
+ pr_debug("%s:SLIMBUS_%d_TX cnt[%d] ch[%d %d]\n", __func__,
+ (dai->id - SLIMBUS_0_TX) / 2,
tx_num, dai_data->port_config.slim_sch.slave_ch_mapping[0],
dai_data->port_config.slim_sch.slave_ch_mapping[1]);
break;
@@ -1195,6 +1204,22 @@
.remove = msm_dai_q6_dai_remove,
};
+static struct snd_soc_dai_driver msm_dai_q6_slimbus_2_tx_dai = {
+ .capture = {
+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
+ SNDRV_PCM_RATE_192000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 4,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
+
/* To do: change to register DAIs as batch */
static __devinit int msm_dai_q6_dev_probe(struct platform_device *pdev)
{
@@ -1223,14 +1248,15 @@
&msm_dai_q6_mi2s_rx_dai);
break;
case SLIMBUS_0_RX:
+ case SLIMBUS_4_RX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_rx_dai);
break;
case SLIMBUS_0_TX:
+ case SLIMBUS_4_TX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_tx_dai);
break;
-
case SLIMBUS_1_RX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_rx_dai);
@@ -1239,6 +1265,10 @@
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_tx_dai);
break;
+ case SLIMBUS_2_TX:
+ rc = snd_soc_register_dai(&pdev->dev,
+ &msm_dai_q6_slimbus_2_tx_dai);
+ break;
case INT_BT_SCO_RX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_bt_sco_rx_dai);
diff --git a/sound/soc/msm/msm-pcm-routing.c b/sound/soc/msm/msm-pcm-routing.c
index 4bb9282..c58bdf5 100644
--- a/sound/soc/msm/msm-pcm-routing.c
+++ b/sound/soc/msm/msm-pcm-routing.c
@@ -47,6 +47,7 @@
static struct mutex routing_lock;
static int fm_switch_enable;
+static int fm_pcmrx_switch_enable;
#define INT_RX_VOL_MAX_STEPS 0x2000
#define INT_RX_VOL_GAIN 0x2000
@@ -130,6 +131,8 @@
{ SECONDARY_I2S_RX, 0, 0, 0, 0, 0},
{ SLIMBUS_1_RX, 0, 0, 0, 0, 0},
{ SLIMBUS_1_TX, 0, 0, 0, 0, 0},
+ { SLIMBUS_4_RX, 0, 0, 0, 0, 0},
+ { SLIMBUS_4_TX, 0, 0, 0, 0, 0},
{ SLIMBUS_INVALID, 0, 0, 0, 0, 0},
};
@@ -594,6 +597,31 @@
return 1;
}
+static int msm_routing_get_fm_pcmrx_switch_mixer(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = fm_pcmrx_switch_enable;
+ pr_debug("%s: FM Switch enable %ld\n", __func__,
+ ucontrol->value.integer.value[0]);
+ return 0;
+}
+
+static int msm_routing_put_fm_pcmrx_switch_mixer(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ pr_debug("%s: FM Switch enable %ld\n", __func__,
+ ucontrol->value.integer.value[0]);
+ if (ucontrol->value.integer.value[0])
+ snd_soc_dapm_mixer_update_power(widget, kcontrol, 1);
+ else
+ snd_soc_dapm_mixer_update_power(widget, kcontrol, 0);
+ fm_pcmrx_switch_enable = ucontrol->value.integer.value[0];
+ return 1;
+}
+
static int msm_routing_get_port_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -920,6 +948,15 @@
msm_routing_put_audio_mixer),
};
+static const struct snd_kcontrol_new slimbus_4_rx_mixer_controls[] = {
+ SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_4_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_4_RX,
+ MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+};
+
static const struct snd_kcontrol_new int_bt_sco_rx_mixer_controls[] = {
SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_INT_BT_SCO_RX,
MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
@@ -1005,6 +1042,9 @@
SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX,
MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("SLIM_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX,
+ MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
static const struct snd_kcontrol_new mmul2_mixer_controls[] = {
@@ -1178,11 +1218,22 @@
msm_routing_put_port_mixer),
};
+static const struct snd_kcontrol_new afe_pcm_rx_port_mixer_controls[] = {
+ SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_AFE_PCM_RX,
+ MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer,
+ msm_routing_put_port_mixer),
+};
+
static const struct snd_kcontrol_new fm_switch_mixer_controls =
SOC_SINGLE_EXT("Switch", SND_SOC_NOPM,
0, 1, 0, msm_routing_get_switch_mixer,
msm_routing_put_switch_mixer);
+static const struct snd_kcontrol_new pcm_rx_switch_mixer_controls =
+ SOC_SINGLE_EXT("Switch", SND_SOC_NOPM,
+ 0, 1, 0, msm_routing_get_fm_pcmrx_switch_mixer,
+ msm_routing_put_fm_pcmrx_switch_mixer);
+
static const struct snd_kcontrol_new int_fm_vol_mixer_controls[] = {
SOC_SINGLE_EXT_TLV("Internal FM RX Volume", SND_SOC_NOPM, 0,
INT_RX_VOL_GAIN, 0, msm_routing_get_fm_vol_mixer,
@@ -1436,10 +1487,15 @@
/* incall */
SND_SOC_DAPM_AIF_OUT("VOICE_PLAYBACK_TX", "Voice Farend Playback",
0, 0, 0 , 0),
+ SND_SOC_DAPM_AIF_OUT("SLIMBUS_4_RX", "Slimbus4 Playback",
+ 0, 0, 0 , 0),
SND_SOC_DAPM_AIF_IN("INCALL_RECORD_TX", "Voice Uplink Capture",
0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("INCALL_RECORD_RX", "Voice Downlink Capture",
0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SLIMBUS_4_TX", "Slimbus4 Capture",
+ 0, 0, 0, 0),
+
SND_SOC_DAPM_AIF_OUT("AUX_PCM_RX", "AUX PCM Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("AUX_PCM_TX", "AUX PCM Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("VOICE_STUB_DL", "VOICE_STUB Playback", 0, 0, 0, 0),
@@ -1452,6 +1508,8 @@
/* Switch Definitions */
SND_SOC_DAPM_SWITCH("SLIMBUS_DL_HL", SND_SOC_NOPM, 0, 0,
&fm_switch_mixer_controls),
+ SND_SOC_DAPM_SWITCH("PCM_RX_DL_HL", SND_SOC_NOPM, 0, 0,
+ &pcm_rx_switch_mixer_controls),
/* Mixer definitions */
SND_SOC_DAPM_MIXER("PRI_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_i2s_rx_mixer_controls, ARRAY_SIZE(pri_i2s_rx_mixer_controls)),
@@ -1473,6 +1531,9 @@
SND_SOC_DAPM_MIXER("Incall_Music Audio Mixer", SND_SOC_NOPM, 0, 0,
incall_music_delivery_mixer_controls,
ARRAY_SIZE(incall_music_delivery_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SLIMBUS_4_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
+ slimbus_4_rx_mixer_controls,
+ ARRAY_SIZE(slimbus_4_rx_mixer_controls)),
/* Voice Mixer */
SND_SOC_DAPM_MIXER("PRI_RX_Voice Mixer",
SND_SOC_NOPM, 0, 0, pri_rx_voice_mixer_controls,
@@ -1531,6 +1592,9 @@
SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX Port Mixer", SND_SOC_NOPM, 0, 0,
bt_sco_rx_port_mixer_controls,
ARRAY_SIZE(bt_sco_rx_port_mixer_controls)),
+ SND_SOC_DAPM_MIXER("AFE_PCM_RX Port Mixer",
+ SND_SOC_NOPM, 0, 0, afe_pcm_rx_port_mixer_controls,
+ ARRAY_SIZE(afe_pcm_rx_port_mixer_controls)),
};
static const struct snd_soc_dapm_route intercon[] = {
@@ -1562,9 +1626,13 @@
{"Incall_Music Audio Mixer", "MultiMedia1", "MM_DL1"},
{"Incall_Music Audio Mixer", "MultiMedia2", "MM_DL2"},
{"VOICE_PLAYBACK_TX", NULL, "Incall_Music Audio Mixer"},
+ {"SLIMBUS_4_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
+ {"SLIMBUS_4_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
+ {"SLIMBUS_4_RX", NULL, "SLIMBUS_4_RX Audio Mixer"},
{"MultiMedia1 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"},
{"MultiMedia1 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"},
+ {"MultiMedia1 Mixer", "SLIM_4_TX", "SLIMBUS_4_TX"},
{"MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
{"MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
{"MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
@@ -1656,11 +1724,16 @@
{"INTFM_UL_HL", NULL, "INT_FM_TX"},
{"AUX_PCM_RX", NULL, "AUXPCM_DL_HL"},
{"AUXPCM_UL_HL", NULL, "AUX_PCM_TX"},
+ {"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"},
+ {"PCM_RX", NULL, "PCM_RX_DL_HL"},
{"SLIMBUS_0_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"},
{"SLIMBUS_0_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"},
{"SLIMBUS_0_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"},
{"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Port Mixer"},
+ {"AFE_PCM_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"},
+ {"PCM_RX", NULL, "AFE_PCM_RX Port Mixer"},
+
{"AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"},
{"AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"},
{"AUX_PCM_RX", NULL, "AUXPCM_RX Port Mixer"},
diff --git a/sound/soc/msm/msm-pcm-routing.h b/sound/soc/msm/msm-pcm-routing.h
index eb6db4b..b254381 100644
--- a/sound/soc/msm/msm-pcm-routing.h
+++ b/sound/soc/msm/msm-pcm-routing.h
@@ -37,6 +37,9 @@
#define LPASS_BE_SLIMBUS_1_RX "(Backend) SLIMBUS_1_RX"
#define LPASS_BE_SLIMBUS_1_TX "(Backend) SLIMBUS_1_TX"
+#define LPASS_BE_SLIMBUS_4_RX "(Backend) SLIMBUS_4_RX"
+#define LPASS_BE_SLIMBUS_4_TX "(Backend) SLIMBUS_4_TX"
+
/* For multimedia front-ends, asm session is allocated dynamically.
* Hence, asm session/multimedia front-end mapping has to be maintained.
* Due to this reason, additional multimedia front-end must be placed before
@@ -80,6 +83,8 @@
MSM_BACKEND_DAI_SEC_I2S_RX,
MSM_BACKEND_DAI_SLIMBUS_1_RX,
MSM_BACKEND_DAI_SLIMBUS_1_TX,
+ MSM_BACKEND_DAI_SLIMBUS_4_RX,
+ MSM_BACKEND_DAI_SLIMBUS_4_TX,
MSM_BACKEND_DAI_INVALID,
MSM_BACKEND_DAI_MAX,
};
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 9f70ee2..de98aa3 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -61,7 +61,6 @@
#define JACK_DETECT_GPIO 38
#define JACK_DETECT_INT PM8921_GPIO_IRQ(PM8921_IRQ_BASE, JACK_DETECT_GPIO)
-#define GPIO_DETECT_USED false
static u32 top_spk_pamp_gpio = PM8921_GPIO_PM_TO_SYS(18);
static u32 bottom_spk_pamp_gpio = PM8921_GPIO_PM_TO_SYS(19);
@@ -82,6 +81,14 @@
static struct snd_soc_jack hs_jack;
static struct snd_soc_jack button_jack;
+static bool hs_detect_use_gpio;
+module_param(hs_detect_use_gpio, bool, 0444);
+MODULE_PARM_DESC(hs_detect_use_gpio, "Use GPIO for headset detection");
+
+static bool hs_detect_use_firmware;
+module_param(hs_detect_use_firmware, bool, 0444);
+MODULE_PARM_DESC(hs_detect_use_firmware, "Use firmware for headset detection");
+
static int msm8960_enable_codec_ext_clk(struct snd_soc_codec *codec, int enable,
bool dapm);
@@ -642,21 +649,21 @@
btn_low = tabla_mbhc_cal_btn_det_mp(btn_cfg, TABLA_BTN_DET_V_BTN_LOW);
btn_high = tabla_mbhc_cal_btn_det_mp(btn_cfg, TABLA_BTN_DET_V_BTN_HIGH);
btn_low[0] = -50;
- btn_high[0] = 10;
- btn_low[1] = 11;
- btn_high[1] = 38;
- btn_low[2] = 39;
- btn_high[2] = 64;
- btn_low[3] = 65;
- btn_high[3] = 91;
- btn_low[4] = 92;
- btn_high[4] = 115;
- btn_low[5] = 116;
- btn_high[5] = 141;
- btn_low[6] = 142;
- btn_high[6] = 163;
- btn_low[7] = 164;
- btn_high[7] = 250;
+ btn_high[0] = 20;
+ btn_low[1] = 21;
+ btn_high[1] = 62;
+ btn_low[2] = 63;
+ btn_high[2] = 104;
+ btn_low[3] = 105;
+ btn_high[3] = 143;
+ btn_low[4] = 144;
+ btn_high[4] = 181;
+ btn_low[5] = 182;
+ btn_high[5] = 218;
+ btn_low[6] = 219;
+ btn_high[6] = 254;
+ btn_low[7] = 255;
+ btn_high[7] = 330;
n_ready = tabla_mbhc_cal_btn_det_mp(btn_cfg, TABLA_BTN_DET_N_READY);
n_ready[0] = 80;
n_ready[1] = 68;
@@ -679,10 +686,13 @@
int ret = 0;
unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
+ unsigned int user_set_tx_ch = 0;
- pr_debug("%s: ch=%d\n", __func__,
- msm8960_slim_0_rx_ch);
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+
+ pr_debug("%s: rx_0_ch=%d\n", __func__, msm8960_slim_0_rx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
@@ -704,6 +714,15 @@
goto end;
}
} else {
+
+ if (codec_dai->id == 2)
+ user_set_tx_ch = msm8960_slim_0_tx_ch;
+ else if (codec_dai->id == 4)
+ user_set_tx_ch = params_channels(params);
+
+ pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
+ codec_dai->name, codec_dai->id, user_set_tx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
@@ -711,13 +730,13 @@
goto end;
}
ret = snd_soc_dai_set_channel_map(cpu_dai,
- msm8960_slim_0_tx_ch, tx_ch, 0 , 0);
+ user_set_tx_ch, tx_ch, 0 , 0);
if (ret < 0) {
pr_err("%s: failed to set cpu chan map\n", __func__);
goto end;
}
ret = snd_soc_dai_set_channel_map(codec_dai,
- msm8960_slim_0_tx_ch, tx_ch, 0, 0);
+ user_set_tx_ch, tx_ch, 0, 0);
if (ret < 0) {
pr_err("%s: failed to set codec channel map\n",
__func__);
@@ -789,7 +808,7 @@
codec_clk = clk_get(cpu_dai->dev, "osr_clk");
- if (GPIO_DETECT_USED) {
+ if (hs_detect_use_gpio) {
mbhc_cfg.gpio = PM8921_GPIO_PM_TO_SYS(JACK_DETECT_GPIO);
mbhc_cfg.gpio_irq = JACK_DETECT_INT;
}
@@ -802,6 +821,9 @@
return err;
}
}
+
+ mbhc_cfg.read_fw_bin = hs_detect_use_firmware;
+
err = tabla_hs_detect(codec, &mbhc_cfg);
return err;
@@ -1327,6 +1349,16 @@
.be_hw_params_fixup = msm8960_slim_0_tx_be_hw_params_fixup,
.ops = &msm8960_be_ops,
},
+ {
+ .name = "SLIMBUS_2 Hostless",
+ .stream_name = "SLIMBUS_2 Hostless",
+ .cpu_dai_name = "msm-dai-q6.16389",
+ .platform_name = "msm-pcm-hostless",
+ .codec_name = "tabla1x_codec",
+ .codec_dai_name = "tabla_tx2",
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ops = &msm8960_be_ops,
+ },
};
@@ -1357,6 +1389,16 @@
.be_hw_params_fixup = msm8960_slim_0_tx_be_hw_params_fixup,
.ops = &msm8960_be_ops,
},
+ {
+ .name = "SLIMBUS_2 Hostless",
+ .stream_name = "SLIMBUS_2 Hostless",
+ .cpu_dai_name = "msm-dai-q6.16389",
+ .platform_name = "msm-pcm-hostless",
+ .codec_name = "tabla_codec",
+ .codec_dai_name = "tabla_tx2",
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ops = &msm8960_be_ops,
+ },
};
static struct snd_soc_dai_link msm8960_tabla1x_dai[
diff --git a/sound/soc/msm/qdsp6/q6afe.c b/sound/soc/msm/qdsp6/q6afe.c
index 535f39b..dc120b08 100644
--- a/sound/soc/msm/qdsp6/q6afe.c
+++ b/sound/soc/msm/qdsp6/q6afe.c
@@ -152,6 +152,7 @@
case INT_FM_RX:
case VOICE_PLAYBACK_TX:
case RT_PROXY_PORT_001_RX:
+ case SLIMBUS_4_RX:
ret = MSM_AFE_PORT_TYPE_RX;
break;
@@ -163,10 +164,12 @@
case VOICE_RECORD_TX:
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
case INT_FM_TX:
case VOICE_RECORD_RX:
case INT_BT_SCO_TX:
case RT_PROXY_PORT_001_TX:
+ case SLIMBUS_4_TX:
ret = MSM_AFE_PORT_TYPE_TX;
break;
@@ -202,6 +205,7 @@
case SLIMBUS_0_TX:
case SLIMBUS_1_RX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
case INT_BT_SCO_RX:
case INT_BT_SCO_TX:
case INT_BT_A2DP_RX:
@@ -209,6 +213,8 @@
case INT_FM_TX:
case RT_PROXY_PORT_001_RX:
case RT_PROXY_PORT_001_TX:
+ case SLIMBUS_4_RX:
+ case SLIMBUS_4_TX:
{
ret = 0;
break;
@@ -264,6 +270,7 @@
case SLIMBUS_0_TX: return IDX_SLIMBUS_0_TX;
case SLIMBUS_1_RX: return IDX_SLIMBUS_1_RX;
case SLIMBUS_1_TX: return IDX_SLIMBUS_1_TX;
+ case SLIMBUS_2_TX: return IDX_SLIMBUS_2_TX;
case INT_BT_SCO_RX: return IDX_INT_BT_SCO_RX;
case INT_BT_SCO_TX: return IDX_INT_BT_SCO_TX;
case INT_BT_A2DP_RX: return IDX_INT_BT_A2DP_RX;
@@ -271,6 +278,8 @@
case INT_FM_TX: return IDX_INT_FM_TX;
case RT_PROXY_PORT_001_RX: return IDX_RT_PROXY_PORT_001_RX;
case RT_PROXY_PORT_001_TX: return IDX_RT_PROXY_PORT_001_TX;
+ case SLIMBUS_4_RX: return IDX_SLIMBUS_4_RX;
+ case SLIMBUS_4_TX: return IDX_SLIMBUS_4_TX;
default: return -EINVAL;
}
@@ -295,6 +304,9 @@
case SLIMBUS_0_TX:
case SLIMBUS_1_RX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
+ case SLIMBUS_4_RX:
+ case SLIMBUS_4_TX:
ret_size = SIZEOF_CFG_CMD(afe_port_slimbus_sch_cfg);
break;
case RT_PROXY_PORT_001_RX:
diff --git a/sound/soc/msm/qdsp6/q6voice.c b/sound/soc/msm/qdsp6/q6voice.c
index 728d856..6050929 100644
--- a/sound/soc/msm/qdsp6/q6voice.c
+++ b/sound/soc/msm/qdsp6/q6voice.c
@@ -3707,6 +3707,7 @@
case VSS_IVOCPROC_CMD_DEREGISTER_CALIBRATION_DATA:
case VSS_ICOMMON_CMD_MAP_MEMORY:
case VSS_ICOMMON_CMD_UNMAP_MEMORY:
+ case VSS_IVOCPROC_CMD_SET_MUTE:
v->cvp_state = CMD_STATUS_SUCCESS;
wake_up(&v->cvp_wait);
break;
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index 04d4ca4..0068c2a 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -67,7 +67,7 @@
* It can be used to eliminate pops between different playback streams, e.g.
* between two audio tracks.
*/
-static int pmdown_time = 5000;
+static int pmdown_time;
module_param(pmdown_time, int, 0);
MODULE_PARM_DESC(pmdown_time, "DAPM stream powerdown time (msecs)");
diff --git a/sound/usb/card.c b/sound/usb/card.c
index 57a8e2d..12dfa0a 100644
--- a/sound/usb/card.c
+++ b/sound/usb/card.c
@@ -47,6 +47,7 @@
#include <linux/mutex.h>
#include <linux/usb/audio.h>
#include <linux/usb/audio-v2.h>
+#include <linux/switch.h>
#include <sound/control.h>
#include <sound/core.h>
@@ -85,6 +86,7 @@
static int async_unlink = 1;
static int device_setup[SNDRV_CARDS]; /* device parameter for this card */
static int ignore_ctl_error;
+struct switch_dev *usbaudiosdev;
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for the USB audio adapter.");
@@ -418,6 +420,7 @@
}
snd_usb_audio_create_proc(chip);
+ switch_set_state(usbaudiosdev, 1);
*rchip = chip;
return 0;
@@ -580,6 +583,7 @@
mutex_unlock(&chip->shutdown_mutex);
mutex_unlock(®ister_mutex);
}
+ switch_set_state(usbaudiosdev, 0);
}
/*
@@ -712,16 +716,27 @@
static int __init snd_usb_audio_init(void)
{
+ int err;
if (nrpacks < 1 || nrpacks > MAX_PACKS) {
printk(KERN_WARNING "invalid nrpacks value.\n");
return -EINVAL;
}
+
+ usbaudiosdev = kzalloc(sizeof(usbaudiosdev), GFP_KERNEL);
+ usbaudiosdev->name = "usb_audio";
+
+ err = switch_dev_register(usbaudiosdev);
+ if (err)
+ pr_err("Usb-audio switch registration failed\n");
+ else
+ pr_debug("usb hs_detected\n");
return usb_register(&usb_audio_driver);
}
static void __exit snd_usb_audio_cleanup(void)
{
usb_deregister(&usb_audio_driver);
+ kfree(usbaudiosdev);
}
module_init(snd_usb_audio_init);