mmc: msm_sdcc: Set CPU_DMA latency for acceptable QOS
To prevent speed degradation in high throughput
scenarios, specify CPU_DMA latency which gives
acceptable QOS. This should be derived without
knowledge of specific low power mode latencies.
For MMC/SD cards, reads tend to be the fastest
transactions, and suffer most from latency. To
ensure acceptable QOS, the average chunk size read
is used with typical best-in-class read speeds
seen across targets and cards.
With an average chunk size of 128KiB transferred
at 30MB/s, a 5% degradation in speed allows for
an additional 200us latency. This default can
be overridden by newer targets with more stringent
latency requirements.
Change-Id: I77d320d2b5e34e3b72ba41ed25454ece042eeddb
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8064-storage.c b/arch/arm/mach-msm/board-8064-storage.c
index 275c893..d91408a 100644
--- a/arch/arm/mach-msm/board-8064-storage.c
+++ b/arch/arm/mach-msm/board-8064-storage.c
@@ -271,14 +271,11 @@
apq8064_sdc3_pdata->disable_cmd23 = true;
}
}
- if (apq8064_sdc1_pdata) {
- apq8064_sdc1_pdata->swfi_latency =
- apq8064_rpm_get_swfi_latency();
+
+ if (apq8064_sdc1_pdata)
apq8064_add_sdcc(1, apq8064_sdc1_pdata);
- }
+
if (apq8064_sdc3_pdata) {
- apq8064_sdc3_pdata->swfi_latency =
- apq8064_rpm_get_swfi_latency();
if (!machine_is_apq8064_cdp()) {
apq8064_sdc3_pdata->wpswitch_gpio = 0;
apq8064_sdc3_pdata->wpswitch_polarity = 0;