msm: acpuclock-krait: Update HFPLL vdd_dig requirements for all SoCs
Updated hardware recommendations have been released. Capture these.
Although the voltage requirements are higher than was previously
specified, this is not expected to affect actual voltage levels
because the vdd_dig requirements of the of the L2 cache (as
enforced by acpuclock) are already higher than the new HFPLL
requirements.
Change-Id: I4087b35f07276d063d09756067ce7166093f65dc
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index f9bdc14..37ece0a 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -31,10 +31,12 @@
.has_droop_ctl = true,
.droop_offset = 0x14,
.droop_val = 0x0108C000,
- .low_vdd_l_max = 40,
- .vdd[HFPLL_VDD_NONE] = 0,
- .vdd[HFPLL_VDD_LOW] = 945000,
+ .low_vdd_l_max = 22,
+ .nom_vdd_l_max = 42,
+ .vdd[HFPLL_VDD_NONE] = 0,
+ .vdd[HFPLL_VDD_LOW] = 945000,
.vdd[HFPLL_VDD_NOM] = 1050000,
+ .vdd[HFPLL_VDD_HIGH] = 1150000,
};
static struct scalable scalable[] __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-8627.c b/arch/arm/mach-msm/acpuclock-8627.c
index b10359d..4ae8753 100644
--- a/arch/arm/mach-msm/acpuclock-8627.c
+++ b/arch/arm/mach-msm/acpuclock-8627.c
@@ -37,10 +37,12 @@
.has_droop_ctl = true,
.droop_offset = 0x14,
.droop_val = 0x0108C000,
- .low_vdd_l_max = 40,
+ .low_vdd_l_max = 22,
+ .nom_vdd_l_max = 42,
.vdd[HFPLL_VDD_NONE] = LVL_NONE,
.vdd[HFPLL_VDD_LOW] = LVL_LOW,
.vdd[HFPLL_VDD_NOM] = LVL_NOM,
+ .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
};
static struct scalable scalable[] __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
index c5d8145..d8a5356 100644
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ b/arch/arm/mach-msm/acpuclock-8930.c
@@ -37,10 +37,12 @@
.has_droop_ctl = true,
.droop_offset = 0x14,
.droop_val = 0x0108C000,
- .low_vdd_l_max = 40,
+ .low_vdd_l_max = 22,
+ .nom_vdd_l_max = 42,
.vdd[HFPLL_VDD_NONE] = LVL_NONE,
.vdd[HFPLL_VDD_LOW] = LVL_LOW,
.vdd[HFPLL_VDD_NOM] = LVL_NOM,
+ .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
};
static struct scalable scalable[] __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-8930aa.c b/arch/arm/mach-msm/acpuclock-8930aa.c
index 157a08a..a8a2e6c 100644
--- a/arch/arm/mach-msm/acpuclock-8930aa.c
+++ b/arch/arm/mach-msm/acpuclock-8930aa.c
@@ -37,10 +37,12 @@
.has_droop_ctl = true,
.droop_offset = 0x14,
.droop_val = 0x0108C000,
- .low_vdd_l_max = 40,
+ .low_vdd_l_max = 22,
+ .nom_vdd_l_max = 42,
.vdd[HFPLL_VDD_NONE] = LVL_NONE,
.vdd[HFPLL_VDD_LOW] = LVL_LOW,
.vdd[HFPLL_VDD_NOM] = LVL_NOM,
+ .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
};
static struct scalable scalable[] __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index 9c2e169..a20d91d 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -31,10 +31,12 @@
.has_droop_ctl = true,
.droop_offset = 0x14,
.droop_val = 0x0108C000,
- .low_vdd_l_max = 40,
- .vdd[HFPLL_VDD_NONE] = 0,
- .vdd[HFPLL_VDD_LOW] = 850000,
+ .low_vdd_l_max = 22,
+ .nom_vdd_l_max = 42,
+ .vdd[HFPLL_VDD_NONE] = 0,
+ .vdd[HFPLL_VDD_LOW] = 945000,
.vdd[HFPLL_VDD_NOM] = 1050000,
+ .vdd[HFPLL_VDD_HIGH] = 1150000,
};
static struct scalable scalable[] __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 53c4b08..9555fd24 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -37,9 +37,11 @@
/* TODO: Verify magic number for 8974 when available. */
.config_val = 0x7845C665,
.low_vdd_l_max = 52,
+ .nom_vdd_l_max = 104,
.vdd[HFPLL_VDD_NONE] = LVL_NONE,
.vdd[HFPLL_VDD_LOW] = LVL_LOW,
.vdd[HFPLL_VDD_NOM] = LVL_NOM,
+ .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
};
static struct scalable scalable[] __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index f796c5f..79922e6 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -387,9 +387,12 @@
{
const int *hfpll_vdd = drv.hfpll_data->vdd;
const u32 low_vdd_l_max = drv.hfpll_data->low_vdd_l_max;
+ const u32 nom_vdd_l_max = drv.hfpll_data->nom_vdd_l_max;
if (s->src != HFPLL)
return hfpll_vdd[HFPLL_VDD_NONE];
+ else if (s->pll_l_val > nom_vdd_l_max)
+ return hfpll_vdd[HFPLL_VDD_HIGH];
else if (s->pll_l_val > low_vdd_l_max)
return hfpll_vdd[HFPLL_VDD_NOM];
else
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
index d4c3aa5..d9aca5c 100644
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ b/arch/arm/mach-msm/acpuclock-krait.h
@@ -74,6 +74,7 @@
HFPLL_VDD_NONE,
HFPLL_VDD_LOW,
HFPLL_VDD_NOM,
+ HFPLL_VDD_HIGH,
NUM_HFPLL_VDD
};
@@ -165,6 +166,7 @@
* @droop_offset: Droop controller register offset from base address.
* @droop_val: Value to initialize the @config_offset register to.
* @low_vdd_l_max: Maximum "L" value supported at HFPLL_VDD_LOW.
+ * @nom_vdd_l_max: Maximum "L" value supported at HFPLL_VDD_NOM.
* @vdd: voltage requirements for each VDD level for the L2 PLL.
*/
struct hfpll_data {
@@ -178,6 +180,7 @@
const u32 droop_offset;
const u32 droop_val;
const u32 low_vdd_l_max;
+ const u32 nom_vdd_l_max;
const int vdd[NUM_HFPLL_VDD];
};