msm: pil-q6v5: Update clock calls to fix MSS PIL with full bootchain
LPASS and MSS have different requirements related to the order that
their clocks are enable/disabled and resets are asserted/de-asserted.
Currently, this causes 'clock stuck off' warnings in the kernel logs
when MSS is booted multiple times.
Fix this by reordering the MSS clock calls so that the core_clk reset
is de-asserted prior to enabling its iface_clk. Because doing this
would break LPASS (which requires iface_clk to be on for the core_clk
reset de-assertion to work), we are forced to separate the MSS and
LPASS clock sequences into separate functions and move them into their
respective PIL files.
MSS PIL also requires an additional clock that is added as part of
this fixup. The gcc_mss_q6_bimc_axi_clk is needed for the MSS Q6
to access memory.
Change-Id: Id877781f201a7267f72b52045ed2b87ebf7b4e05
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
5 files changed