Merge changes I4ac6f9ef,I96bc377c,Ia5fdfb02,I601d24ef into msm-3.0
* changes:
mmc: core: use non-reentrant workqueue for clock gating
mmc: core: prevent aggressive clock gating racing with ios updates
mmc: rename mmc_host_clk_{ungate|gate} to mmc_host_clk_{hold|release}
Revert "mmc: fix a race between card-detect rescan and clock-gate work instances"
diff --git a/arch/arm/configs/apq8064_defconfig b/arch/arm/configs/apq8064_defconfig
deleted file mode 100644
index 2f3d37a..0000000
--- a/arch/arm/configs/apq8064_defconfig
+++ /dev/null
@@ -1,224 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_EMBEDDED=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_ASHMEM=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_MSM=y
-CONFIG_ARCH_APQ8064=y
-# CONFIG_MSM_STACKED_MEMORY is not set
-CONFIG_CPU_HAS_L2_PMU=y
-# CONFIG_MSM_JTAG_V7 is not set
-# CONFIG_MSM_FIQ_SUPPORT is not set
-# CONFIG_MSM_PROC_COMM is not set
-# CONFIG_MSM_DALRPC is not set
-# CONFIG_MSM_HW3D is not set
-CONFIG_MSM_DIRECT_SCLK_ACCESS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_VMALLOC_RESERVE=0x19000000
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIAL_MSM=y
-# CONFIG_SERIAL_MSM_CLOCK_CONTROL is not set
-CONFIG_SERIAL_MSM_HSL=y
-CONFIG_SERIAL_MSM_HSL_CONSOLE=y
-CONFIG_SERIAL_MSM_HS=y
-#
-# Diag Support
-#
-# CONFIG_DIAG_CHAR is not set
-#
-# DIAG traffic over USB
-#
-CONFIG_DIAG_OVER_USB=y
-CONFIG_HW_RANDOM=y
-CONFIG_DCC_TTY=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_MSM is not set
-CONFIG_I2C_QUP=y
-CONFIG_SLIMBUS_MSM_CTRL=y
-CONFIG_GPIOLIB=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_PM8921_CORE=y
-CONFIG_MFD_PM8821_CORE=y
-CONFIG_REGULATOR=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MUSB_HDRC is not set
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-CONFIG_USB_GADGET_DEBUG_FILES=y
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA_U2O is not set
-# CONFIG_USB_GADGET_M66592 is not set
-CONFIG_USB_GADGET_CI13XXX_MSM=y
-CONFIG_USB_CI13XXX_MSM=y
-# CONFIG_USB_GADGET_MSM_72K is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FUNCTIONFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_MASS_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_ANDROID=y
-# CONFIG_USB_ANDROID_ACM is not set
-CONFIG_USB_ANDROID_ADB=y
-CONFIG_USB_ANDROID_DIAG=y
-# CONFIG_USB_ANDROID_MASS_STORAGE is not set
-# CONFIG_USB_CSW_HACK is not set
-# CONFIG_USB_ANDROID_MTP is not set
-# CONFIG_USB_ANDROID_RNDIS is not set
-# CONFIG_USB_ANDROID_RMNET is not set
-# CONFIG_USB_F_SERIAL is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_QCOM_MAEMO is not set
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ULPI is not set
-# CONFIG_USB_MSM_OTG_72K is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_USB_MSM_OTG=y
-# CONFIG_USB_MSM_ACA is not set
-CONFIG_MMC=y
-CONFIG_MMC_MSM=y
-# CONFIG_MMC_MSM_SDC2_SUPPORT is not set
-CONFIG_MMC_MSM_SDC3_SUPPORT=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-# CONFIG_LEDS_MSM_PMIC is not set
-CONFIG_SWITCH=y
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_RAM_CONSOLE=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-CONFIG_MSM_SSBI=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT4_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_KEYS=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y
-CONFIG_MSM_SMD=y
-CONFIG_MSM_SMD_PKG4=y
-CONFIG_MSM_SMD_PKT=y
-CONFIG_MSM_SMD_DEBUG=y
-CONFIG_MSM_SMD_TTY=y
-CONFIG_MSM_N_WAY_SMD=y
-CONFIG_MSM_N_WAY_SMSM=y
-CONFIG_MSM_SMD_LOGGING=y
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 06d04f7..4322baf 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -193,6 +193,8 @@
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C=y
+CONFIG_SYNA_MULTI_TOUCH=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_GPIO=y
@@ -219,6 +221,8 @@
CONFIG_VIDEO_DEV=y
# CONFIG_MT9T013 is not set
# CONFIG_MT9D112 is not set
+CONFIG_OV5640=y
+CONFIG_WEBCAM_OV7692_QRD=y
CONFIG_WEBCAM_OV9726=y
# CONFIG_MT9P012 is not set
# CONFIG_MT9P012_KM is not set
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index 909a0bf..be8ade5 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -191,6 +191,8 @@
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C=y
+CONFIG_SYNA_MULTI_TOUCH=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_GPIO=y
@@ -217,6 +219,8 @@
CONFIG_VIDEO_DEV=y
# CONFIG_MT9T013 is not set
# CONFIG_MT9D112 is not set
+CONFIG_OV5640=y
+CONFIG_WEBCAM_OV7692_QRD=y
CONFIG_WEBCAM_OV9726=y
# CONFIG_MT9P012 is not set
# CONFIG_MT9P012_KM is not set
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index 5b52404..fb0f106 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -71,7 +71,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm7630_defconfig b/arch/arm/configs/msm7630_defconfig
index 9ad0b5a..cde4048 100644
--- a/arch/arm/configs/msm7630_defconfig
+++ b/arch/arm/configs/msm7630_defconfig
@@ -70,7 +70,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 0f41c0a..c9082f0 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -104,7 +104,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index e900062..2569f82 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -95,7 +95,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index 73d0756..12f946c 100755
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -97,7 +97,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index f8ccbb3..953f088 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -99,7 +99,8 @@
CONFIG_SPI_SPIDEV=m
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+CONFIG_SENSORS_PM8XXX_ADC=y
CONFIG_THERMAL=y
CONFIG_THERMAL_TSENS8960=y
CONFIG_MFD_PM8018_CORE=y
@@ -112,6 +113,7 @@
CONFIG_USB_G_ANDROID=y
CONFIG_SWITCH=y
CONFIG_NET=y
+CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
@@ -150,7 +152,7 @@
# CONFIG_MMC_SDHCI is not set
CONFIG_MMC_MSM=y
CONFIG_MMC_MSM_SDIO_SUPPORT=y
-# CONFIG_MMC_MSM_CARD_HW_DETECTION is not set
+CONFIG_MMC_MSM_CARD_HW_DETECTION=y
CONFIG_MMC_MSM_SDC1_SUPPORT=y
# CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT is not set
CONFIG_MMC_MSM_SDC2_SUPPORT=y
@@ -198,6 +200,27 @@
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_QCRYPTO=m
+CONFIG_CRYPTO_DEV_QCE=m
+CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
+
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_NETDEVICES=y
+CONFIG_WLAN=y
+CONFIG_MSM_RMNET=y
+CONFIG_HOSTAP=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index e42d96a..787b12d 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -33,6 +33,11 @@
asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
/*
+ * Called from C code, this handles an IPI.
+ */
+void handle_IPI(int ipinr, struct pt_regs *regs);
+
+/*
* Setup the set of possible CPUs (via set_cpu_possible)
*/
extern void smp_init_cpus(void);
diff --git a/arch/arm/kernel/perf_event_msm_krait.c b/arch/arm/kernel/perf_event_msm_krait.c
index cb94d64..62509b4 100644
--- a/arch/arm/kernel/perf_event_msm_krait.c
+++ b/arch/arm/kernel/perf_event_msm_krait.c
@@ -365,7 +365,7 @@
static struct arm_pmu krait_pmu = {
.handle_irq = armv7pmu_handle_irq,
-#ifdef CONFIG_ARCH_MSM_SMP
+#ifdef CONFIG_MSM_SMP
.secondary_enable = scorpion_secondary_enable,
.secondary_disable = scorpion_secondary_disable,
#endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 5478f55..1455efe 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -562,6 +562,11 @@
*/
asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
{
+ handle_IPI(ipinr, regs);
+}
+
+void handle_IPI(int ipinr, struct pt_regs *regs)
+{
unsigned int cpu = smp_processor_id();
struct pt_regs *old_regs = set_irq_regs(regs);
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index cfc7dd0..47da48e 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -509,7 +509,6 @@
/* Move CPU to HFPLL source. */
set_pri_clk_src(sc, tgt_s->pri_src_sel);
} else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
- /* TODO: Enable source. */
/*
* If responding to CPU_DEAD we must be running on another
* CPU. Therefore, we can't access the downed CPU's CP15
@@ -533,12 +532,9 @@
*/
if (reason != SETRATE_HOTPLUG || sc == &scalable[L2])
set_pri_clk_src(sc, tgt_s->pri_src_sel);
- /* TODO: Disable source. */
} else {
- /* TODO: Enable source. */
if (reason != SETRATE_HOTPLUG || sc == &scalable[L2])
set_sec_clk_src(sc, tgt_s->sec_src_sel);
- /* TODO: Disable source. */
}
sc->current_speed = tgt_s;
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 304a687..603b031 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -147,6 +147,7 @@
uint16_t pkt_len;
};
+static void notify_all(int event, unsigned long data);
static void bam_mux_write_done(struct work_struct *work);
static void handle_bam_mux_cmd(struct work_struct *work);
static void rx_timer_work_func(struct work_struct *work);
@@ -166,6 +167,7 @@
static void ul_timeout(struct work_struct *work);
static void vote_dfab(void);
static void unvote_dfab(void);
+static void kickoff_ul_wakeup_func(struct work_struct *work);
static int bam_is_connected;
static DEFINE_MUTEX(wakeup_lock);
@@ -175,6 +177,7 @@
static int ul_packet_written;
static struct clk *dfab_clk;
static DEFINE_RWLOCK(ul_wakeup_lock);
+static DECLARE_WORK(kickoff_ul_wakeup, kickoff_ul_wakeup_func);
/* End A2 power collaspe */
#define bam_ch_is_open(x) \
@@ -389,8 +392,12 @@
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
read_lock(&ul_wakeup_lock);
- if (!bam_is_connected)
+ if (!bam_is_connected) {
+ read_unlock(&ul_wakeup_lock);
ul_wakeup();
+ read_lock(&ul_wakeup_lock);
+ notify_all(BAM_DMUX_UL_CONNECTED, (unsigned long)(NULL));
+ }
/* if skb do not have any tailroom for padding,
copy the skb into a new expanded skb */
@@ -494,8 +501,12 @@
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
read_lock(&ul_wakeup_lock);
- if (!bam_is_connected)
+ if (!bam_is_connected) {
+ read_unlock(&ul_wakeup_lock);
ul_wakeup();
+ read_lock(&ul_wakeup_lock);
+ notify_all(BAM_DMUX_UL_CONNECTED, (unsigned long)(NULL));
+ }
hdr->magic_num = BAM_MUX_HDR_MAGIC_NO;
hdr->cmd = BAM_MUX_HDR_CMD_OPEN;
@@ -523,12 +534,16 @@
DBG("%s: closing ch %d\n", __func__, id);
if (!bam_mux_initialized)
return -ENODEV;
- spin_lock_irqsave(&bam_ch[id].lock, flags);
read_lock(&ul_wakeup_lock);
- if (!bam_is_connected)
+ if (!bam_is_connected) {
+ read_unlock(&ul_wakeup_lock);
ul_wakeup();
+ read_lock(&ul_wakeup_lock);
+ notify_all(BAM_DMUX_UL_CONNECTED, (unsigned long)(NULL));
+ }
+ spin_lock_irqsave(&bam_ch[id].lock, flags);
bam_ch[id].notify = NULL;
bam_ch[id].priv = NULL;
bam_ch[id].status &= ~BAM_CH_LOCAL_OPEN;
@@ -747,6 +762,34 @@
#endif
+static void notify_all(int event, unsigned long data)
+{
+ int i;
+
+ for (i = 0; i < BAM_DMUX_NUM_CHANNELS; ++i) {
+ if (bam_ch_is_open(i))
+ bam_ch[i].notify(bam_ch[i].priv, event, data);
+ }
+}
+
+static void kickoff_ul_wakeup_func(struct work_struct *work)
+{
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected) {
+ read_unlock(&ul_wakeup_lock);
+ ul_wakeup();
+ read_lock(&ul_wakeup_lock);
+ ul_packet_written = 1;
+ notify_all(BAM_DMUX_UL_CONNECTED, (unsigned long)(NULL));
+ }
+ read_unlock(&ul_wakeup_lock);
+}
+
+void msm_bam_dmux_kickoff_ul_wakeup(void)
+{
+ queue_work(bam_mux_tx_workqueue, &kickoff_ul_wakeup);
+}
+
static void ul_timeout(struct work_struct *work)
{
write_lock(&ul_wakeup_lock);
@@ -757,6 +800,7 @@
} else {
smsm_change_state(SMSM_APPS_STATE, SMSM_A2_POWER_CONTROL, 0);
bam_is_connected = 0;
+ notify_all(BAM_DMUX_UL_DISCONNECTED, (unsigned long)(NULL));
}
write_unlock(&ul_wakeup_lock);
}
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 40cbee0..5f0480b 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -24,6 +24,7 @@
#include <mach/msm_spi.h>
#include <linux/usb/android.h>
#include <linux/usb/msm_hsusb.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
#include "timer.h"
#include "devices.h"
#include "board-9615.h"
@@ -31,6 +32,39 @@
#include "pm.h"
#include "acpuclock.h"
+static struct pm8xxx_adc_amux pm8018_adc_channels_data[] = {
+ {"vcoin", CHANNEL_VCOIN, CHAN_PATH_SCALING2, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
+ {"vbat", CHANNEL_VBAT, CHAN_PATH_SCALING2, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
+ {"vph_pwr", CHANNEL_VPH_PWR, CHAN_PATH_SCALING2, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
+ {"batt_therm", CHANNEL_BATT_THERM, CHAN_PATH_SCALING1, AMUX_RSV2,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_BATT_THERM},
+ {"batt_id", CHANNEL_BATT_ID, CHAN_PATH_SCALING1, AMUX_RSV2,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
+ {"pmic_therm", CHANNEL_DIE_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_PMIC_THERM},
+ {"625mv", CHANNEL_625MV, CHAN_PATH_SCALING1, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
+ {"125v", CHANNEL_125V, CHAN_PATH_SCALING1, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
+ {"pa_therm0", ADC_MPP_1_AMUX3, CHAN_PATH_SCALING1, AMUX_RSV1,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_PA_THERM},
+};
+
+static struct pm8xxx_adc_properties pm8018_adc_data = {
+ .adc_vdd_reference = 1800, /* milli-voltage for this adc */
+ .bitresolution = 15,
+ .bipolar = 0,
+};
+
+static struct pm8xxx_adc_platform_data pm8018_adc_pdata = {
+ .adc_channel = pm8018_adc_channels_data,
+ .adc_num_board_channel = ARRAY_SIZE(pm8018_adc_channels_data),
+ .adc_prop = &pm8018_adc_data,
+};
+
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
.irq_base = PM8018_IRQ_BASE,
.devirq = MSM_GPIO_TO_INT(87),
@@ -68,6 +102,7 @@
.pwrkey_pdata = &pm8xxx_pwrkey_pdata,
.misc_pdata = &pm8xxx_misc_pdata,
.regulator_pdatas = msm_pm8018_regulator_pdata,
+ .adc_pdata = &pm8018_adc_pdata,
};
static struct msm_ssbi_platform_data msm9615_ssbi_pm8018_pdata __devinitdata = {
@@ -198,7 +233,9 @@
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
-#define GPIO_SDCARD_PWR_EN 18
+#define GPIO_SDCARD_PWR_EN 18
+#define GPIO_SDC1_HW_DET 80
+#define GPIO_SDC2_DAT1_WAKEUP 26
/* MDM9x15 have 2 SDCC controllers */
enum sdcc_controllers {
@@ -371,8 +408,14 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
+ .pclk_src_dfab = 1,
.sdcc_v4_sup = true,
.pin_data = &mmc_slot_pin_data[SDCC1],
+#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
+ .status_gpio = GPIO_SDC1_HW_DET,
+ .status_irq = MSM_GPIO_TO_INT(GPIO_SDC1_HW_DET),
+ .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+#endif
};
static struct mmc_platform_data *msm9615_sdc1_pdata = &sdc1_data;
#else
@@ -389,8 +432,12 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc2_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
+ .pclk_src_dfab = 1,
.sdcc_v4_sup = true,
.pin_data = &mmc_slot_pin_data[SDCC2],
+#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
+ .sdiowakeup_irq = MSM_GPIO_TO_INT(GPIO_SDC2_DAT1_WAKEUP),
+#endif
};
static struct mmc_platform_data *msm9615_sdc2_pdata = &sdc2_data;
#else
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 44939e7..cd590c3 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -1847,7 +1847,7 @@
if (!strncmp(name, "lcdc_toshiba_fwvga_pt", 21) ||
!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
ret = 0;
- } else if (machine_is_msm7x27a_ffa()) {
+ } else if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa()) {
if (!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
ret = 0;
}
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 10d1cd5..a19cf27 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -223,7 +223,7 @@
/* The SPI configurations apply to GSBI 1*/
static struct gpiomux_setting spi_active = {
.func = GPIOMUX_FUNC_1,
- .drv = GPIOMUX_DRV_8MA,
+ .drv = GPIOMUX_DRV_12MA,
.pull = GPIOMUX_PULL_NONE,
};
@@ -2643,6 +2643,17 @@
pr_err("socinfo_init() failed!\n");
}
+#ifdef CONFIG_ARCH_MSM8930
+static void __init msm8930_map_io(void)
+{
+ msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
+ msm_map_msm8930_io();
+
+ if (socinfo_init() < 0)
+ pr_err("socinfo_init() failed!\n");
+}
+#endif
+
static void __init msm8960_init_irq(void)
{
unsigned int i;
@@ -2919,17 +2930,16 @@
static void __init msm8960_init_buses(void)
{
#ifdef CONFIG_MSM_BUS_SCALING
- msm_bus_apps_fabric_pdata.rpm_enabled = 1;
- msm_bus_sys_fabric_pdata.rpm_enabled = 1;
- msm_bus_mm_fabric_pdata.rpm_enabled = 1;
- msm_bus_sys_fpb_pdata.rpm_enabled = 1;
- msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
- msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
- msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
- msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
- msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
- msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
msm_bus_rpm_set_mt_mask();
+ msm_bus_8960_apps_fabric_pdata.rpm_enabled = 1;
+ msm_bus_8960_sys_fabric_pdata.rpm_enabled = 1;
+ msm_bus_8960_mm_fabric_pdata.rpm_enabled = 1;
+ msm_bus_apps_fabric.dev.platform_data =
+ &msm_bus_8960_apps_fabric_pdata;
+ msm_bus_sys_fabric.dev.platform_data = &msm_bus_8960_sys_fabric_pdata;
+ msm_bus_mm_fabric.dev.platform_data = &msm_bus_8960_mm_fabric_pdata;
+ msm_bus_sys_fpb.dev.platform_data = &msm_bus_8960_sys_fpb_pdata;
+ msm_bus_cpss_fpb.dev.platform_data = &msm_bus_8960_cpss_fpb_pdata;
#endif
}
@@ -4039,15 +4049,22 @@
};
#define PM8921_LC_LED_MAX_CURRENT 4 /* I = 4mA */
+#define PM8XXX_LED_PWM_PERIOD 1000
+#define PM8XXX_LED_PWM_DUTY_MS 20
+/**
+ * PM8XXX_PWM_CHANNEL_NONE shall be used when LED shall not be
+ * driven using PWM feature.
+ */
+#define PM8XXX_PWM_CHANNEL_NONE -1
static struct led_info pm8921_led_info[] = {
[0] = {
- .name = "led:usb",
- .default_trigger = "usb-online",
+ .name = "led:battery_charging",
+ .default_trigger = "battery-charging",
},
[1] = {
- .name = "led:ac",
- .default_trigger = "ac-online",
+ .name = "led:battery_full",
+ .default_trigger = "battery-full",
},
};
@@ -4056,16 +4073,37 @@
.leds = pm8921_led_info,
};
+static int pm8921_led0_pwm_duty_pcts[56] = {
+ 1, 4, 8, 12, 16, 20, 24, 28, 32, 36,
+ 40, 44, 46, 52, 56, 60, 64, 68, 72, 76,
+ 80, 84, 88, 92, 96, 100, 100, 100, 98, 95,
+ 92, 88, 84, 82, 78, 74, 70, 66, 62, 58,
+ 58, 54, 50, 48, 42, 38, 34, 30, 26, 22,
+ 14, 10, 6, 4, 1
+};
+
+static struct pm8xxx_pwm_duty_cycles pm8921_led0_pwm_duty_cycles = {
+ .duty_pcts = (int *)&pm8921_led0_pwm_duty_pcts,
+ .num_duty_pcts = ARRAY_SIZE(pm8921_led0_pwm_duty_pcts),
+ .duty_ms = PM8XXX_LED_PWM_DUTY_MS,
+ .start_idx = 0,
+};
+
static struct pm8xxx_led_config pm8921_led_configs[] = {
[0] = {
.id = PM8XXX_ID_LED_0,
- .mode = PM8XXX_LED_MODE_MANUAL,
+ .mode = PM8XXX_LED_MODE_PWM2,
.max_current = PM8921_LC_LED_MAX_CURRENT,
+ .pwm_channel = 5,
+ .pwm_period_us = PM8XXX_LED_PWM_PERIOD,
+ .pwm_duty_cycles = &pm8921_led0_pwm_duty_cycles,
},
[1] = {
.id = PM8XXX_ID_LED_1,
- .mode = PM8XXX_LED_MODE_MANUAL,
+ .mode = PM8XXX_LED_MODE_PWM1,
.max_current = PM8921_LC_LED_MAX_CURRENT,
+ .pwm_channel = 4,
+ .pwm_period_us = PM8XXX_LED_PWM_PERIOD,
},
};
@@ -4188,56 +4226,56 @@
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
true,
- 1, 8000, 100000, 1,
+ 100, 8000, 100000, 1,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
true,
- 1500, 5000, 60100000, 3000,
+ 2000, 6000, 60100000, 3000,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE),
false,
- 1800, 5000, 60350000, 3500,
+ 4200, 5000, 60350000, 3500,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
false,
- 2800, 2500, 65350000, 4800,
+ 6300, 4500, 65350000, 4800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE),
false,
- 3800, 4500, 67850000, 5500,
+ 11700, 2500, 67850000, 5500,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
false,
- 4800, 2000, 71850000, 6800,
+ 13800, 2000, 71850000, 6800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
false,
- 6800, 500, 75850000, 8800,
+ 29700, 500, 75850000, 8800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
false,
- 7800, 0, 76350000, 9800,
+ 29700, 0, 76350000, 9800,
},
};
@@ -4568,3 +4606,32 @@
.init_machine = msm8960_cdp_init,
.init_early = msm8960_allocate_memory_regions,
MACHINE_END
+
+#ifdef CONFIG_ARCH_MSM8930
+MACHINE_START(MSM8930_CDP, "QCT MSM8930 CDP")
+ .map_io = msm8930_map_io,
+ .reserve = msm8960_reserve,
+ .init_irq = msm8960_init_irq,
+ .timer = &msm_timer,
+ .init_machine = msm8960_cdp_init,
+ .init_early = msm8960_allocate_memory_regions,
+MACHINE_END
+
+MACHINE_START(MSM8930_MTP, "QCT MSM8930 MTP")
+ .map_io = msm8930_map_io,
+ .reserve = msm8960_reserve,
+ .init_irq = msm8960_init_irq,
+ .timer = &msm_timer,
+ .init_machine = msm8960_cdp_init,
+ .init_early = msm8960_allocate_memory_regions,
+MACHINE_END
+
+MACHINE_START(MSM8930_FLUID, "QCT MSM8930 FLUID")
+ .map_io = msm8930_map_io,
+ .reserve = msm8960_reserve,
+ .init_irq = msm8960_init_irq,
+ .timer = &msm_timer,
+ .init_machine = msm8960_cdp_init,
+ .init_early = msm8960_allocate_memory_regions,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 6141e1f..956387a 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -6845,6 +6845,7 @@
}
}
+static int msm_bahama_setup_power_enable;
static unsigned int msm_bahama_setup_power(void)
{
int rc = 0;
@@ -6859,64 +6860,53 @@
rc = PTR_ERR(vreg_bahama);
pr_err("%s: regulator_get %s = %d\n", __func__,
msm_bahama_regulator, rc);
+ return rc;
}
- if (!rc)
- rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
- else {
+ rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
+ if (rc) {
pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
msm_bahama_regulator, rc);
goto unget;
}
- if (!rc)
- rc = regulator_enable(vreg_bahama);
- else {
+ rc = regulator_enable(vreg_bahama);
+ if (rc) {
pr_err("%s: regulator_enable %s = %d\n", __func__,
msm_bahama_regulator, rc);
goto unget;
}
- if (!rc) {
- rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
- } else {
+ rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
+ if (rc) {
pr_err("%s: gpio_request %d = %d\n", __func__,
msm_bahama_sys_rst, rc);
goto unenable;
}
- if (!rc) {
- gpio_direction_output(msm_bahama_sys_rst, 0);
- usleep_range(1000, 1050);
- gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
- usleep_range(1000, 1050);
- } else {
- pr_err("%s: gpio_direction_output %d = %d\n", __func__,
- msm_bahama_sys_rst, rc);
- goto unrequest;
- }
-
+ gpio_direction_output(msm_bahama_sys_rst, 0);
+ usleep_range(1000, 1050);
+ gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
+ usleep_range(1000, 1050);
+ msm_bahama_setup_power_enable = 1;
return rc;
-unrequest:
- gpio_free(msm_bahama_sys_rst);
unenable:
regulator_disable(vreg_bahama);
unget:
regulator_put(vreg_bahama);
return rc;
};
+
static unsigned int msm_bahama_shutdown_power(int value)
-
-
{
- gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
-
- gpio_free(msm_bahama_sys_rst);
-
- regulator_disable(vreg_bahama);
-
- regulator_put(vreg_bahama);
+ if (msm_bahama_setup_power_enable) {
+ gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
+ gpio_free(msm_bahama_sys_rst);
+ regulator_disable(vreg_bahama);
+ regulator_put(vreg_bahama);
+ msm_bahama_setup_power_enable = 0;
+ }
return 0;
};
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 1470026..5c11af3 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -1411,7 +1411,7 @@
return rc;
}
-#define GPIO_SDC1_HW_DET 85
+#define GPIO_SDC1_HW_DET 42
#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) \
&& defined(CONFIG_MMC_MSM_CARD_HW_DETECTION)
@@ -1432,7 +1432,7 @@
} else {
status = gpio_direction_input(GPIO_SDC1_HW_DET);
if (!status)
- status = gpio_get_value(GPIO_SDC1_HW_DET);
+ status = !gpio_get_value(GPIO_SDC1_HW_DET);
gpio_free(GPIO_SDC1_HW_DET);
}
return status;
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 50be14b..73020dc 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -137,36 +137,71 @@
/*
* Clock frequency definitions and macros
*/
-#define F_BASIC(f, s, div, v) \
+#define F_BASIC(f, s, div) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = SDIV(SRC_SEL_##s, div), \
- .sys_vdd = v, \
}
-#define F_MND16(f, s, div, m, n, v) \
+#define F_MND16(f, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-#define F_MND8(f, nmsb, nlsb, s, div, m, n, v) \
+#define F_MND8(f, nmsb, nlsb, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(m, n), \
.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_ops clk_ops_rcg_7x30;
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ int rc, target_mv;
+
+ static const int mv[] = {
+ [VDD_DIG_NONE] = 1000,
+ [VDD_DIG_LOW] = 1000,
+ [VDD_DIG_NOMINAL] = 1100,
+ [VDD_DIG_HIGH] = 1200
+ };
+
+ target_mv = mv[level];
+ rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
+ if (rc)
+ return rc;
+ if (target_mv)
+ rc = -EINVAL;
+
+ return rc;
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+
#define PCOM_XO_DISABLE 0
#define PCOM_XO_ENABLE 1
#define PCOM_XO_TCXO 0
@@ -290,7 +325,7 @@
static struct clk_ops clk_ops_branch;
static struct clk_freq_tbl clk_tbl_axi[] = {
- F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -308,6 +343,7 @@
.c = {
.dbg_name = "glbl_root_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1),
CLK_INIT(glbl_root_clk.c),
},
};
@@ -948,10 +984,10 @@
};
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(153600000, 24, 17, pll1, 2, 2, 5, NOMINAL),
- F_MND8(192000000, 24, 17, pll1, 4, 0, 0, NOMINAL),
- F_MND8(384000000, 24, 17, pll1, 2, 0, 0, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(153600000, 24, 17, pll1, 2, 2, 5),
+ F_MND8(192000000, 24, 17, pll1, 4, 0, 0),
+ F_MND8(384000000, 24, 17, pll1, 2, 0, 0),
F_END,
};
@@ -973,12 +1009,13 @@
.c = {
.dbg_name = "csi0_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 384000000),
CLK_INIT(csi0_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_tcxo[] = {
- F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -997,6 +1034,7 @@
.c = {
.dbg_name = "i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_clk.c),
},
};
@@ -1016,6 +1054,7 @@
.c = {
.dbg_name = "i2c_2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_2_clk.c),
},
};
@@ -1035,6 +1074,7 @@
.c = {
.dbg_name = "qup_i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(qup_i2c_clk.c),
},
};
@@ -1054,6 +1094,7 @@
.c = {
.dbg_name = "uart1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart1_clk.c),
},
};
@@ -1073,23 +1114,24 @@
.c = {
.dbg_name = "uart2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart2_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_uartdm[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 3686400, pll3, 3, 3, 200, NOMINAL),
- F_MND16( 7372800, pll3, 3, 3, 100, NOMINAL),
- F_MND16(14745600, pll3, 3, 3, 50, NOMINAL),
- F_MND16(32000000, pll3, 3, 25, 192, NOMINAL),
- F_MND16(40000000, pll3, 3, 125, 768, NOMINAL),
- F_MND16(46400000, pll3, 3, 145, 768, NOMINAL),
- F_MND16(48000000, pll3, 3, 25, 128, NOMINAL),
- F_MND16(51200000, pll3, 3, 5, 24, NOMINAL),
- F_MND16(56000000, pll3, 3, 175, 768, NOMINAL),
- F_MND16(58982400, pll3, 3, 6, 25, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 3686400, pll3, 3, 3, 200),
+ F_MND16( 7372800, pll3, 3, 3, 100),
+ F_MND16(14745600, pll3, 3, 3, 50),
+ F_MND16(32000000, pll3, 3, 25, 192),
+ F_MND16(40000000, pll3, 3, 125, 768),
+ F_MND16(46400000, pll3, 3, 145, 768),
+ F_MND16(48000000, pll3, 3, 25, 128),
+ F_MND16(51200000, pll3, 3, 5, 24),
+ F_MND16(56000000, pll3, 3, 175, 768),
+ F_MND16(58982400, pll3, 3, 6, 25),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -1111,6 +1153,7 @@
.c = {
.dbg_name = "uart1dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart1dm_clk.c),
},
};
@@ -1133,20 +1176,21 @@
.c = {
.dbg_name = "uart2dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart2dm_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdh[] = {
- F_BASIC( 0, gnd, 1, NONE),
- F_BASIC( 49150000, pll3, 15, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, NOMINAL),
- F_BASIC(368640000, pll3, 2, NOMINAL),
- F_BASIC(384000000, pll1, 2, NOMINAL),
- F_BASIC(445500000, pll4, 2, NOMINAL),
+ F_BASIC( 0, gnd, 1),
+ F_BASIC( 49150000, pll3, 15),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(245760000, pll3, 3),
+ F_BASIC(368640000, pll3, 2),
+ F_BASIC(384000000, pll1, 2),
+ F_BASIC(445500000, pll4, 2),
F_END,
};
@@ -1166,6 +1210,7 @@
.dbg_name = "emdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(emdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1187,30 +1232,31 @@
.dbg_name = "pmdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(pmdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_grp[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52662875, pll3, 14, NOMINAL),
- F_BASIC( 56713846, pll3, 13, NOMINAL),
- F_BASIC( 61440000, pll3, 12, NOMINAL),
- F_BASIC( 67025454, pll3, 11, NOMINAL),
- F_BASIC( 73728000, pll3, 10, NOMINAL),
- F_BASIC( 81920000, pll3, 9, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(105325714, pll3, 7, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(192000000, pll1, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52662875, pll3, 14),
+ F_BASIC( 56713846, pll3, 13),
+ F_BASIC( 61440000, pll3, 12),
+ F_BASIC( 67025454, pll3, 11),
+ F_BASIC( 73728000, pll3, 10),
+ F_BASIC( 81920000, pll3, 9),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(105325714, pll3, 7),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(192000000, pll1, 4),
+ F_BASIC(245760000, pll3, 3),
/* Sync to AXI. Hence this "rate" is not fixed. */
- F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NULL),
F_END,
};
@@ -1231,6 +1277,7 @@
.c = {
.dbg_name = "grp_2d_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_2d_clk.c),
.depends = &axi_grp_2d_clk.c,
},
@@ -1250,6 +1297,7 @@
.c = {
.dbg_name = "grp_3d_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_3d_src_clk.c),
.depends = &axi_li_grp_clk.c,
},
@@ -1288,14 +1336,14 @@
};
static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 19, 12, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 19, 12, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 19, 12, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 19, 12, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 19, 12, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 19, 12, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 19, 12, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 19, 12, lpxo, 1, 1, 171),
+ F_MND8( 400000, 19, 12, lpxo, 1, 2, 123),
+ F_MND8(16027000, 19, 12, pll3, 3, 14, 215),
+ F_MND8(17000000, 19, 12, pll3, 4, 19, 206),
+ F_MND8(20480000, 19, 12, pll3, 4, 23, 212),
+ F_MND8(24576000, 19, 12, lpxo, 1, 0, 0),
+ F_MND8(49152000, 19, 12, pll3, 3, 1, 5),
F_END,
};
@@ -1317,6 +1365,7 @@
.c = {
.dbg_name = "sdc1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc1_clk.c),
},
};
@@ -1339,19 +1388,20 @@
.c = {
.dbg_name = "sdc3_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc3_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 20, 13, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 20, 13, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 20, 13, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 20, 13, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 20, 13, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 20, 13, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 20, 13, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 20, 13, lpxo, 1, 1, 171),
+ F_MND8( 400000, 20, 13, lpxo, 1, 2, 123),
+ F_MND8(16027000, 20, 13, pll3, 3, 14, 215),
+ F_MND8(17000000, 20, 13, pll3, 4, 19, 206),
+ F_MND8(20480000, 20, 13, pll3, 4, 23, 212),
+ F_MND8(24576000, 20, 13, lpxo, 1, 0, 0),
+ F_MND8(49152000, 20, 13, pll3, 3, 1, 5),
F_END,
};
@@ -1373,6 +1423,7 @@
.c = {
.dbg_name = "sdc2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc2_clk.c),
},
};
@@ -1395,20 +1446,21 @@
.c = {
.dbg_name = "sdc4_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc4_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdp_core[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52663000, pll3, 14, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(153600000, pll1, 5, NOMINAL),
- F_BASIC(192000000, pll1, 4, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52663000, pll3, 14),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(153600000, pll1, 5),
+ F_BASIC(192000000, pll1, 4),
F_END,
};
@@ -1429,18 +1481,19 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(mdp_clk.c),
.depends = &axi_mdp_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16(30720000, pll3, 4, 1, 6, NOMINAL),
- F_MND16(32768000, pll3, 3, 2, 15, NOMINAL),
- F_MND16(40960000, pll3, 2, 1, 9, NOMINAL),
- F_MND16(73728000, pll3, 2, 1, 5, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(24576000, lpxo, 1, 0, 0),
+ F_MND16(30720000, pll3, 4, 1, 6),
+ F_MND16(32768000, pll3, 3, 2, 15),
+ F_MND16(40960000, pll3, 2, 1, 9),
+ F_MND16(73728000, pll3, 2, 1, 5),
F_END,
};
@@ -1462,6 +1515,7 @@
.c = {
.dbg_name = "mdp_lcdc_pclk_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 73728000),
CLK_INIT(mdp_lcdc_pclk_clk.c),
},
};
@@ -1483,8 +1537,8 @@
};
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NONE, NULL),
- F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NOMINAL, NULL),
+ F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NULL),
+ F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NULL),
F_END,
};
@@ -1504,14 +1558,15 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 24576000),
CLK_INIT(mdp_vsync_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 2048000, lpxo, 4, 1, 3, NOMINAL),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 2048000, lpxo, 4, 1, 3),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1533,6 +1588,7 @@
.c = {
.dbg_name = "mi2s_codec_rx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_rx_m_clk.c),
},
};
@@ -1571,6 +1627,7 @@
.c = {
.dbg_name = "mi2s_codec_tx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_tx_m_clk.c),
},
};
@@ -1592,8 +1649,8 @@
};
static struct clk_freq_tbl clk_tbl_mi2s[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1615,6 +1672,7 @@
.c = {
.dbg_name = "mi2s_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_m_clk.c),
},
};
@@ -1636,8 +1694,8 @@
};
static struct clk_freq_tbl clk_tbl_midi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(98304000, 19, 12, pll3, 3, 2, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(98304000, 19, 12, pll3, 3, 2, 5),
F_END,
};
@@ -1658,30 +1716,30 @@
.c = {
.dbg_name = "midi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 98304000),
CLK_INIT(midi_clk.c),
},
};
-#define F_SDAC(f, s, div, m, n, v) \
+#define F_SDAC(f, s, div, m, n) \
{ \
.freq_hz = f, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_SDAC_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
.src_clk = &s##_clk.c, \
}
static struct clk_freq_tbl clk_tbl_sdac[] = {
- F_SDAC( 256000, lpxo, 4, 1, 24, NOMINAL),
- F_SDAC( 352800, lpxo, 1, 147, 10240, NOMINAL),
- F_SDAC( 384000, lpxo, 4, 1, 16, NOMINAL),
- F_SDAC( 512000, lpxo, 4, 1, 12, NOMINAL),
- F_SDAC( 705600, lpxo, 1, 147, 5120, NOMINAL),
- F_SDAC( 768000, lpxo, 4, 1, 8, NOMINAL),
- F_SDAC(1024000, lpxo, 4, 1, 6, NOMINAL),
- F_SDAC(1411200, lpxo, 1, 147, 2560, NOMINAL),
- F_SDAC(1536000, lpxo, 4, 1, 4, NOMINAL),
+ F_SDAC( 256000, lpxo, 4, 1, 24),
+ F_SDAC( 352800, lpxo, 1, 147, 10240),
+ F_SDAC( 384000, lpxo, 4, 1, 16),
+ F_SDAC( 512000, lpxo, 4, 1, 12),
+ F_SDAC( 705600, lpxo, 1, 147, 5120),
+ F_SDAC( 768000, lpxo, 4, 1, 8),
+ F_SDAC(1024000, lpxo, 4, 1, 6),
+ F_SDAC(1411200, lpxo, 1, 147, 2560),
+ F_SDAC(1536000, lpxo, 4, 1, 4),
F_END,
};
@@ -1703,6 +1761,7 @@
.c = {
.dbg_name = "sdac_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1536000),
CLK_INIT(sdac_clk.c),
},
};
@@ -1724,9 +1783,9 @@
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(27000000, 23, 16, pll4, 2, 2, 33, NOMINAL),
- F_MND8(74250000, 23, 16, pll4, 2, 1, 6, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(27000000, 23, 16, pll4, 2, 2, 33),
+ F_MND8(74250000, 23, 16, pll4, 2, 1, 6),
F_END,
};
@@ -1745,6 +1804,7 @@
.c = {
.dbg_name = "tv_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 74250000),
CLK_INIT(tv_clk.c),
},
};
@@ -1815,8 +1875,8 @@
};
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(60000000, 23, 16, pll1, 2, 5, 32, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(60000000, 23, 16, pll1, 2, 5, 32),
F_END,
};
@@ -1835,6 +1895,7 @@
.c = {
.dbg_name = "usb_hs_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs_src_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1936,19 +1997,19 @@
};
static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
- F_MND16( 24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16( 36864000, pll3, 4, 1, 5, NOMINAL),
- F_MND16( 46080000, pll3, 4, 1, 4, NOMINAL),
- F_MND16( 61440000, pll3, 4, 1, 3, NOMINAL),
- F_MND16( 73728000, pll3, 2, 1, 5, NOMINAL),
- F_MND16( 81920000, pll3, 3, 1, 3, NOMINAL),
- F_MND16( 92160000, pll3, 4, 1, 2, NOMINAL),
- F_MND16( 98304000, pll3, 3, 2, 5, NOMINAL),
- F_MND16(105326000, pll3, 2, 2, 7, NOMINAL),
- F_MND16(122880000, pll3, 2, 1, 3, NOMINAL),
- F_MND16(147456000, pll3, 2, 2, 5, NOMINAL),
- F_MND16(153600000, pll1, 2, 2, 5, NOMINAL),
- F_MND16(192000000, pll1, 4, 0, 0, HIGH),
+ F_MND16( 24576000, lpxo, 1, 0, 0),
+ F_MND16( 36864000, pll3, 4, 1, 5),
+ F_MND16( 46080000, pll3, 4, 1, 4),
+ F_MND16( 61440000, pll3, 4, 1, 3),
+ F_MND16( 73728000, pll3, 2, 1, 5),
+ F_MND16( 81920000, pll3, 3, 1, 3),
+ F_MND16( 92160000, pll3, 4, 1, 2),
+ F_MND16( 98304000, pll3, 3, 2, 5),
+ F_MND16(105326000, pll3, 2, 2, 7),
+ F_MND16(122880000, pll3, 2, 1, 3),
+ F_MND16(147456000, pll3, 2, 2, 5),
+ F_MND16(153600000, pll1, 2, 2, 5),
+ F_MND16(192000000, pll1, 4, 0, 0),
F_END,
};
@@ -1970,6 +2031,7 @@
.c = {
.dbg_name = "jpeg_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(jpeg_clk.c),
.depends = &axi_li_jpeg_clk.c,
},
@@ -1993,6 +2055,7 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(vfe_clk.c),
.depends = &axi_li_vfe_clk.c,
},
@@ -2047,16 +2110,16 @@
};
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 6000000, pll1, 4, 1, 32, NOMINAL),
- F_MND16( 8000000, pll1, 4, 1, 24, NOMINAL),
- F_MND16(12000000, pll1, 4, 1, 16, NOMINAL),
- F_MND16(16000000, pll1, 4, 1, 12, NOMINAL),
- F_MND16(19200000, pll1, 4, 1, 10, NOMINAL),
- F_MND16(24000000, pll1, 4, 1, 8, NOMINAL),
- F_MND16(32000000, pll1, 4, 1, 6, NOMINAL),
- F_MND16(48000000, pll1, 4, 1, 4, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 6000000, pll1, 4, 1, 32),
+ F_MND16( 8000000, pll1, 4, 1, 24),
+ F_MND16(12000000, pll1, 4, 1, 16),
+ F_MND16(16000000, pll1, 4, 1, 12),
+ F_MND16(19200000, pll1, 4, 1, 10),
+ F_MND16(24000000, pll1, 4, 1, 8),
+ F_MND16(32000000, pll1, 4, 1, 6),
+ F_MND16(48000000, pll1, 4, 1, 4),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -2076,18 +2139,19 @@
.c = {
.dbg_name = "cam_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(cam_m_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 22, 15, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 22, 15, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 22, 15, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 22, 15, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 22, 15, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 22, 15, pll1, 1, 1, 5, NOMINAL),
+ F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 22, 15, pll3, 4, 1, 6),
+ F_MND8( 61440000, 22, 15, pll3, 4, 1, 3),
+ F_MND8( 81920000, 22, 15, pll3, 3, 1, 3),
+ F_MND8(122880000, 22, 15, pll3, 3, 1, 2),
+ F_MND8(147456000, 22, 15, pll3, 1, 1, 5),
+ F_MND8(153600000, 22, 15, pll1, 1, 1, 5),
F_END,
};
@@ -2109,21 +2173,21 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 153600000),
CLK_INIT(vpe_clk.c),
.depends = &axi_vpe_clk.c,
},
};
-
static struct clk_freq_tbl clk_tbl_mfc[] = {
- F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 24, 17, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 24, 17, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 24, 17, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 24, 17, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 24, 17, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 24, 17, pll1, 1, 1, 5, NOMINAL),
- F_MND8(170667000, 24, 17, pll1, 1, 2, 9, NOMINAL),
+ F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 24, 17, pll3, 4, 1, 6),
+ F_MND8( 61440000, 24, 17, pll3, 4, 1, 3),
+ F_MND8( 81920000, 24, 17, pll3, 3, 1, 3),
+ F_MND8(122880000, 24, 17, pll3, 3, 1, 2),
+ F_MND8(147456000, 24, 17, pll3, 1, 1, 5),
+ F_MND8(153600000, 24, 17, pll1, 1, 1, 5),
+ F_MND8(170667000, 24, 17, pll1, 1, 2, 9),
F_END,
};
@@ -2145,6 +2209,7 @@
.c = {
.dbg_name = "mfc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 170667000),
CLK_INIT(mfc_clk.c),
.depends = &axi_mfc_clk.c,
},
@@ -2167,9 +2232,9 @@
};
static struct clk_freq_tbl clk_tbl_spi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 9963243, 19, 12, pll3, 4, 2, 37, NOMINAL),
- F_MND8(26331429, 19, 12, pll3, 4, 1, 7, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 9963243, 19, 12, pll3, 4, 2, 37),
+ F_MND8(26331429, 19, 12, pll3, 4, 1, 7),
F_END,
};
@@ -2191,15 +2256,16 @@
.c = {
.dbg_name = "spi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 26331429),
CLK_INIT(spi_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL), /* src MI2S_CODEC_RX */
- F_RAW(2, NULL, 0, 1, 0, 0, LOW, NULL), /* src ECODEC_CIF */
- F_RAW(3, NULL, 0, 2, 0, 0, LOW, NULL), /* src MI2S */
- F_RAW(4, NULL, 0, 3, 0, 0, LOW, NULL), /* src SDAC */
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL), /* src MI2S_CODEC_RX */
+ F_RAW(2, NULL, 0, 1, 0, 0, NULL), /* src ECODEC_CIF */
+ F_RAW(3, NULL, 0, 2, 0, 0, NULL), /* src MI2S */
+ F_RAW(4, NULL, 0, 3, 0, 0, NULL), /* src SDAC */
F_END,
};
@@ -2219,12 +2285,13 @@
.c = {
.dbg_name = "lpa_codec_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 4),
CLK_INIT(lpa_codec_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdc[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL),
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL),
F_END
};
@@ -2244,6 +2311,7 @@
.c = {
.dbg_name = "mdc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 1),
CLK_INIT(mdc_clk.c),
},
};
@@ -2368,32 +2436,6 @@
static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_fixed_clk.c);
static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_fixed_clk.c);
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm7x30_update_sys_vdd(enum sys_vdd_level level)
-{
- int rc, target_mv;
- static const int mv[NUM_SYS_VDD_LEVELS] = {
- [NONE...LOW] = 1000,
- [NOMINAL] = 1100,
- [HIGH] = 1200,
- };
-
- target_mv = mv[level];
- rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
- if (rc)
- goto out;
- if (target_mv) {
- rc = -EINVAL;
- goto out;
- }
-out:
- return rc;
-}
-
#ifdef CONFIG_DEBUG_FS
#define CLK_TEST_2(s) (s)
@@ -2739,7 +2781,7 @@
{ CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL) },
{ CLK_LOOKUP("ebi1_fixed_clk", ebi1_fixed_clk.c, NULL) },
{ CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL) },
- { CLK_LOOKUP("gp_clk", gp_clk.c, NULL) },
+ { CLK_LOOKUP("core_clk", gp_clk.c, NULL) },
{ CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2") },
{ CLK_LOOKUP("usb_phy_clk", usb_phy_clk.c, NULL) },
@@ -2947,8 +2989,6 @@
print_ownership();
set_clock_ownership();
- soc_update_sys_vdd = msm7x30_update_sys_vdd;
-
/* When we have no local clock control, the rest of the code in this
* function is a NOP since writes to shadow regions that we don't own
* are ignored. */
@@ -2990,7 +3030,7 @@
static struct clk_ops clk_ops_rcg_7x30 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
.get_rate = rcg_clk_get_rate,
@@ -3006,7 +3046,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = soc_branch_clk_reset,
.set_flags = soc_clk_set_flags,
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index ee122ec..615a6b5 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -426,6 +426,41 @@
};
#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 0,
+ [VDD_DIG_LOW] = 945000,
+ [VDD_DIG_NOMINAL] = 1050000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
+ vdd_uv[level], 1150000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
/*
* Clock Descriptions
*/
@@ -556,24 +591,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8960_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 0,
- [LOW] = 945000,
- [NOMINAL] = 1050000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -582,7 +599,7 @@
static struct clk_ops clk_ops_rcg_8960 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
@@ -598,7 +615,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -1187,34 +1204,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1251,29 +1268,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1290,17 +1307,16 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_QDSS(f, s, d, v) \
+#define F_QDSS(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_qdss[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(128000000, pll8, 3, LOW),
- F_QDSS(300000000, pll3, 4, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(128000000, pll8, 3),
+ F_QDSS(300000000, pll3, 4),
F_END
};
@@ -1416,7 +1432,7 @@
const struct qdss_bank *bank = clk->bank_info;
u32 reg, bank_sel_mask = bank->bank_sel_mask;
- rcg_clk_auto_off(c);
+ rcg_clk_disable(c);
/* Switch to bank 0 */
reg = readl_relaxed(clk->ns_reg);
reg &= ~bank_sel_mask;
@@ -1460,6 +1476,7 @@
.c = {
.dbg_name = "qdss_at_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_at_clk.c),
},
};
@@ -1506,14 +1523,15 @@
.c = {
.dbg_name = "qdss_traceclkin_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_traceclkin_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(200000000, pll3, 6, LOW),
- F_QDSS(400000000, pll3, 3, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(200000000, pll3, 6),
+ F_QDSS(400000000, pll3, 3),
F_END
};
@@ -1541,6 +1559,7 @@
.c = {
.dbg_name = "qdss_tsctr_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 200000000, NOMINAL, 400000000),
CLK_INIT(qdss_tsctr_clk.c),
},
};
@@ -1562,16 +1581,15 @@
},
};
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1593,6 +1611,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1611,14 +1630,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1636,11 +1654,12 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
-#define CLK_SDC(name, n, h_b, f_table) \
+#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
struct rcg_clk name = { \
.b = { \
.ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
@@ -1655,85 +1674,54 @@
.root_en_mask = BIT(11), \
.ns_mask = (BM(23, 16) | BM(6, 0)), \
.set_rate = set_rate_mnd, \
- .freq_tbl = f_table, \
+ .freq_tbl = clk_tbl_sdc, \
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
+static struct clk_freq_tbl clk_tbl_sdc[] = {
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
+ F_SDC( 64000000, pll8, 3, 1, 2),
+ F_SDC( 96000000, pll8, 4, 0, 0),
F_END
};
-static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
-static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
+static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
+static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
+static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
+static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
+static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
-static struct clk_freq_tbl clk_tbl_sdc3[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, LOW),
- F_SDC( 96000000, pll8, 4, 0, 0, LOW),
- F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
-
-static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
-static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
-
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1754,20 +1742,20 @@
.c = {
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
CLK_INIT(tsif_ref_clk.c),
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1786,6 +1774,7 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
@@ -1810,22 +1799,22 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1834,8 +1823,8 @@
CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, LOW),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1856,6 +1845,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 60000000),
CLK_INIT(usb_hsic_xcvr_fs_clk.c),
},
};
@@ -1877,14 +1867,13 @@
},
};
-#define F_USB_HSIC(f, s, v) \
+#define F_USB_HSIC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
- F_USB_HSIC(480000000, pll14, LOW),
+ F_USB_HSIC(480000000, pll14),
F_END
};
@@ -1900,6 +1889,7 @@
.c = {
.dbg_name = "usb_hsic_hsic_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 480000000),
CLK_INIT(usb_hsic_hsic_src_clk.c),
},
};
@@ -1919,14 +1909,13 @@
},
};
-#define F_USB_HSIO_CAL(f, s, v) \
+#define F_USB_HSIO_CAL(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
- F_USB_HSIO_CAL(9000000, pxo, LOW),
+ F_USB_HSIO_CAL(9000000, pxo),
F_END
};
@@ -1943,6 +1932,7 @@
.c = {
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 10000000),
CLK_INIT(usb_hsic_hsio_cal_clk.c),
},
};
@@ -1959,7 +1949,7 @@
},
};
-#define CLK_USB_FS(i, n) \
+#define CLK_USB_FS(i, n, fmax_nom) \
struct rcg_clk i##_clk = { \
.ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
.b = { \
@@ -1975,11 +1965,12 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
CLK_INIT(i##_clk.c), \
}, \
}
-static CLK_USB_FS(usb_fs1_src, 1);
+static CLK_USB_FS(usb_fs1_src, 1, 64000000);
static struct branch_clk usb_fs1_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
@@ -2014,7 +2005,7 @@
},
};
-static CLK_USB_FS(usb_fs2_src, 2);
+static CLK_USB_FS(usb_fs2_src, 2, 60000000);
static struct branch_clk usb_fs2_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
@@ -2078,18 +2069,17 @@
},
};
-#define F_CE3(f, s, d, v) \
+#define F_CE3(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ce3[] = {
- F_CE3( 0, gnd, 1, NONE),
- F_CE3( 48000000, pll8, 8, LOW),
- F_CE3(100000000, pll3, 12, NOMINAL),
+ F_CE3( 0, gnd, 1),
+ F_CE3( 48000000, pll8, 8),
+ F_CE3(100000000, pll3, 12),
F_END
};
@@ -2107,6 +2097,7 @@
.c = {
.dbg_name = "ce3_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
CLK_INIT(ce3_src_clk.c),
},
};
@@ -2681,10 +2672,11 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2692,21 +2684,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2714,7 +2705,7 @@
static CLK_CAM(cam1_clk, 1, 16);
static CLK_CAM(cam2_clk, 2, 31);
-#define F_CSI(f, s, d, m, n, v) \
+#define F_CSI(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2722,12 +2713,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, 0, 0, NONE),
- F_CSI( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI( 0, gnd, 1, 0, 0),
+ F_CSI( 85330000, pll8, 1, 2, 9),
+ F_CSI(177780000, pll2, 1, 2, 9),
F_END
};
@@ -2747,6 +2737,7 @@
.c = {
.dbg_name = "csi0_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi0_src_clk.c),
},
};
@@ -2801,6 +2792,7 @@
.c = {
.dbg_name = "csi1_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi1_src_clk.c),
},
};
@@ -2855,6 +2847,7 @@
.c = {
.dbg_name = "csi2_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi2_src_clk.c),
},
};
@@ -3076,7 +3069,7 @@
},
};
-#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
+#define F_CSI_PHYTIMER(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3084,12 +3077,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
- F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
- F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
+ F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
+ F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
F_END
};
@@ -3109,6 +3101,7 @@
.c = {
.dbg_name = "csiphy_timer_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csiphy_timer_src_clk.c),
},
};
@@ -3261,7 +3254,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3269,22 +3262,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -3324,6 +3316,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -3364,11 +3358,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3376,69 +3372,80 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(300000000, pll3, 1, 4),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 300000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
/* TODO: need to add 325MHz back once it is fixed in the simulation model */
static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 325000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -3475,12 +3482,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_VCAP(f, s, m, n, v) \
+#define F_VCAP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3488,18 +3497,17 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcap[] = {
- F_VCAP( 0, gnd, 0, 0, NONE),
- F_VCAP( 27000000, pxo, 0, 0, LOW),
- F_VCAP( 54860000, pll8, 1, 7, LOW),
- F_VCAP( 64000000, pll8, 1, 6, LOW),
- F_VCAP( 76800000, pll8, 1, 5, LOW),
- F_VCAP(128000000, pll8, 1, 3, NOMINAL),
- F_VCAP(160000000, pll2, 1, 5, NOMINAL),
- F_VCAP(200000000, pll2, 1, 4, NOMINAL),
+ F_VCAP( 0, gnd, 0, 0),
+ F_VCAP( 27000000, pxo, 0, 0),
+ F_VCAP( 54860000, pll8, 1, 7),
+ F_VCAP( 64000000, pll8, 1, 6),
+ F_VCAP( 76800000, pll8, 1, 5),
+ F_VCAP(128000000, pll8, 1, 3),
+ F_VCAP(160000000, pll2, 1, 5),
+ F_VCAP(200000000, pll2, 1, 4),
F_END
};
@@ -3538,6 +3546,7 @@
.dbg_name = "vcap_clk",
.ops = &clk_ops_rcg_8960,
.depends = &vcap_axi_clk.c,
+ VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
CLK_INIT(vcap_clk.c),
},
};
@@ -3557,7 +3566,7 @@
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3565,37 +3574,34 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_ijpeg_8960[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_ijpeg[] = {
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
+ F_IJPEG(266667000, pll2, 1, 1, 3),
+ F_IJPEG(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_ijpeg_8064[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, LOW),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk ijpeg_clk = {
@@ -3613,30 +3619,30 @@
.ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_ijpeg_8960,
+ .freq_tbl = clk_tbl_ijpeg,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -3658,12 +3664,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3671,44 +3678,30 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_mdp_8960[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+static struct clk_freq_tbl clk_tbl_mdp[] = {
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
+ F_MDP(266667000, pll2, 1, 3),
F_END
};
-static struct clk_freq_tbl clk_tbl_mdp_8064[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, LOW),
- F_MDP(128000000, pll8, 1, 3, LOW),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
- F_MDP(266000000, pll2, 1, 3, NOMINAL),
- F_END
+static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000
};
static struct bank_masks bmnd_info_mdp = {
@@ -3741,12 +3734,13 @@
.ns_reg = MDP_NS_REG,
.root_en_mask = BIT(2),
.set_rate = set_rate_mnd_banked,
- .freq_tbl = clk_tbl_mdp_8960,
+ .freq_tbl = clk_tbl_mdp,
.bank_info = &bmnd_info_mdp,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
@@ -3767,15 +3761,14 @@
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -3796,34 +3789,34 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, LOW),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
- F_ROT(200000000, pll2, 4, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
+ F_ROT(200000000, pll2, 4),
F_END
};
@@ -3855,6 +3848,7 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
@@ -3902,7 +3896,7 @@
CLK_INIT(hdmi_pll_clk),
};
-#define F_TV_GND(f, s, p_r, d, m, n, v) \
+#define F_TV_GND(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3910,9 +3904,8 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk, \
@@ -3920,20 +3913,24 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = (void *)p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
- F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
- F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
- F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
- F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
- F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
+ F_TV_GND( 0, gnd, 0, 1, 0, 0),
+ F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
+ F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
+ F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
+ F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
+ F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
F_END
};
+static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 74250000,
+ [VDD_DIG_NOMINAL] = 149000000
+};
+
/*
* Unlike other clocks, the TV rate is adjusted through PLL
* re-programming. It is also routed through an MND divider.
@@ -3962,6 +3959,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -4065,7 +4063,7 @@
.mode_mask = BM(12, 11),
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4073,18 +4071,17 @@
.ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
.ctl_val = CC_BANKED(6, 11, n), \
.mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -4106,28 +4103,29 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
F_END
};
@@ -4149,12 +4147,13 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4162,50 +4161,40 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_vfe_8960[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_vfe[] = {
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
+ F_VFE(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_vfe_8064[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, LOW),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk vfe_clk = {
@@ -4223,11 +4212,12 @@
.ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_vfe_8960,
+ .freq_tbl = clk_tbl_vfe,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -4253,28 +4243,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4299,6 +4288,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4323,6 +4313,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4421,28 +4412,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4466,6 +4456,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -4490,6 +4481,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -4979,25 +4971,25 @@
CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
- CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
- CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
+ CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
+ CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
- CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
- CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
- CLK_LOOKUP("sata_phy_ref_clk", sata_phy_ref_clk.c, NULL),
- CLK_LOOKUP("sata_phy_cfg_clk", sata_phy_cfg_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
+ CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
+ CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, NULL),
CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
@@ -5006,7 +4998,7 @@
CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
- CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
@@ -5021,11 +5013,11 @@
CLK_LOOKUP("iface_clk", ce3_p_clk.c, NULL),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
- CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", amp_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
@@ -5066,7 +5058,7 @@
CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, NULL),
CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
- CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
+ CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
@@ -5081,7 +5073,6 @@
CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
- CLK_LOOKUP("rot_axi_clk", rot_axi_clk.c, NULL),
CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, NULL),
CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, NULL),
CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, NULL),
@@ -5096,8 +5087,8 @@
CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
- CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
- CLK_LOOKUP("imem_pclk", imem_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
+ CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
@@ -5115,8 +5106,8 @@
CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
- CLK_DUMMY("sps_slimbus_clk", SPS_SLIMBUS_CLK, NULL, OFF),
- CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
+ CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
+ CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, NULL),
@@ -5198,9 +5189,7 @@
CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
- CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
- CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
@@ -5210,7 +5199,7 @@
CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
- CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
+ CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
@@ -5247,11 +5236,11 @@
CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
- CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", amp_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
@@ -5288,10 +5277,10 @@
CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("imem_axi_clk", imem_axi_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
+ CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
@@ -5340,11 +5329,11 @@
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
- CLK_LOOKUP("smmu_pclk", smmu_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
@@ -5367,18 +5356,18 @@
CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
- CLK_LOOKUP("iommu_clk", jpegd_axi_clk.c, "msm_iommu.0"),
- CLK_LOOKUP("iommu_clk", vpe_axi_clk.c, "msm_iommu.1"),
- CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.2"),
- CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.3"),
- CLK_LOOKUP("iommu_clk", rot_axi_clk.c, "msm_iommu.4"),
- CLK_LOOKUP("iommu_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
- CLK_LOOKUP("iommu_clk", vfe_axi_clk.c, "msm_iommu.6"),
- CLK_LOOKUP("iommu_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
- CLK_LOOKUP("iommu_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
- CLK_LOOKUP("iommu_clk", gfx3d_clk.c, "msm_iommu.9"),
- CLK_LOOKUP("iommu_clk", gfx2d0_clk.c, "msm_iommu.10"),
- CLK_LOOKUP("iommu_clk", gfx2d1_clk.c, "msm_iommu.11"),
+ CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
+ CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
+ CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
+ CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
+ CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
+ CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
+ CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
+ CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
+ CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
+ CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
+ CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
+ CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
@@ -5441,6 +5430,11 @@
writel_relaxed(regval, mode_reg);
/* Program bias count */
+ regval &= ~BM(19, 14);
+ regval |= BVAL(19, 14, 0x1);
+ writel_relaxed(regval, mode_reg);
+
+ /* Program lock count */
regval &= ~BM(13, 8);
regval |= BVAL(13, 8, 0x8);
writel_relaxed(regval, mode_reg);
@@ -5641,11 +5635,6 @@
/* Set VCO frequency */
rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000);
- /* Enable AUX output */
- regval = readl_relaxed(BB_PLL14_TEST_CTL_REG);
- regval |= BIT(12);
- writel_relaxed(regval, BB_PLL14_TEST_CTL_REG);
-
set_fsm_mode(BB_PLL14_MODE_REG);
}
/* Program PLL2 to 800MHz with ref clk = 27MHz */
@@ -5667,11 +5656,6 @@
/* Set VCO frequency */
rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000);
- /* Enable AUX output */
- regval = readl_relaxed(MM_PLL1_TEST_CTL_REG);
- regval |= BIT(12);
- writel_relaxed(regval, MM_PLL1_TEST_CTL_REG);
-
/* Program PLL15 to 975MHz with ref clk = 27MHz */
writel_relaxed(0x24, MM_PLL3_L_VAL_REG);
writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
@@ -5748,6 +5732,14 @@
sizeof(msm_clocks_8960_v1));
if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
+ sizeof(vfe_clk.c.fmax));
+
memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
num_lookups = ARRAY_SIZE(msm_clocks_8960);
@@ -5756,20 +5748,27 @@
}
/*
- * Change the freq tables for gfx3d_clk, ijpeg_clk, mdp_clk,
- * tv_src_clk and vfe_clk at runtime and chain gmem_axi_clk
- * with gfx3d_axi_clk for 8064.
+ * Change the freq tables for and voltage requirements for
+ * clocks which differ between 8960 and 8064.
*/
if (cpu_is_apq8064()) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
- ijpeg_clk.freq_tbl = clk_tbl_ijpeg_8064;
- mdp_clk.freq_tbl = clk_tbl_mdp_8064;
- vfe_clk.freq_tbl = clk_tbl_vfe_8064;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
+ sizeof(tv_src_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
+ sizeof(vfe_clk.c.fmax));
+
gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
}
- soc_update_sys_vdd = msm8960_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -5845,7 +5844,8 @@
rc = clk_enable(cfpb_a_clk);
if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
return rc;
- return local_unvote_sys_vdd(HIGH);
+
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8960_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 1273198..f6dd39e 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -313,6 +313,41 @@
| BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
* !!(n))
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 500000,
+ [VDD_DIG_LOW] = 1000000,
+ [VDD_DIG_NOMINAL] = 1100000,
+ [VDD_DIG_HIGH] = 1200000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], 1200000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
static struct msm_xo_voter *xo_pxo, *xo_cxo;
static bool xo_clk_is_local(struct clk *clk)
@@ -498,24 +533,6 @@
writel_relaxed(pll_mode, MM_PLL2_MODE_REG);
}
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8660_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 500000,
- [LOW] = 1000000,
- [NOMINAL] = 1100000,
- [HIGH] = 1200000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -524,7 +541,7 @@
static struct clk_ops clk_ops_rcg_8x60 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
@@ -540,7 +557,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -1053,34 +1070,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1117,29 +1134,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1156,16 +1173,15 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1187,6 +1203,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1205,14 +1222,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1230,6 +1246,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -1254,27 +1271,27 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC(16000000, pll8, 4, 1, 6, LOW),
- F_SDC(17070000, pll8, 1, 2, 45, LOW),
- F_SDC(20210000, pll8, 1, 1, 19, LOW),
- F_SDC(24000000, pll8, 4, 1, 4, LOW),
- F_SDC(48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC(16000000, pll8, 4, 1, 6),
+ F_SDC(17070000, pll8, 1, 2, 45),
+ F_SDC(20210000, pll8, 1, 1, 19),
+ F_SDC(24000000, pll8, 4, 1, 4),
+ F_SDC(48000000, pll8, 4, 1, 2),
F_END
};
@@ -1284,18 +1301,17 @@
static CLK_SDC(sdc4, 4, CLK_HALT_DFAB_STATE_REG, 3);
static CLK_SDC(sdc5, 5, CLK_HALT_DFAB_STATE_REG, 2);
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1320,16 +1336,15 @@
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1348,22 +1363,22 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1386,6 +1401,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -1418,6 +1434,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -2014,7 +2031,7 @@
},
};
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2022,21 +2039,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2057,21 +2073,21 @@
.c = {
.dbg_name = "cam_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000),
CLK_INIT(cam_clk.c),
},
};
-#define F_CSI(f, s, d, v) \
+#define F_CSI(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, NONE),
- F_CSI(192000000, pll8, 2, LOW),
- F_CSI(384000000, pll8, 1, NOMINAL),
+ F_CSI( 0, gnd, 1),
+ F_CSI(192000000, pll8, 2),
+ F_CSI(384000000, pll8, 1),
F_END
};
@@ -2089,6 +2105,7 @@
.c = {
.dbg_name = "csi_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 192000000, NOMINAL, 384000000),
CLK_INIT(csi_src_clk.c),
},
};
@@ -2178,7 +2195,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2186,22 +2203,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -2241,6 +2257,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -2281,11 +2299,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2293,24 +2313,23 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, HIGH),
- F_GFX3D(266667000, pll2, 1, 3, HIGH),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
@@ -2350,12 +2369,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 96000000, NOMINAL, 200000000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2363,19 +2384,18 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!n, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ijpeg[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
F_END
};
@@ -2399,25 +2419,25 @@
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 228571000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -2439,12 +2459,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2452,24 +2473,23 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
F_END
};
@@ -2509,20 +2529,21 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 85330000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -2543,11 +2564,12 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_PIXEL_MDP(f, s, d, m, n, v) \
+#define F_PIXEL_MDP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2555,21 +2577,20 @@
.ns_val = NS_MM(31, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pixel_mdp[] = {
- F_PIXEL_MDP( 0, gnd, 1, 0, 0, NONE),
- F_PIXEL_MDP( 25600000, pll8, 3, 1, 5, LOW),
- F_PIXEL_MDP( 42667000, pll8, 1, 1, 9, LOW),
- F_PIXEL_MDP( 43192000, pll8, 1, 64, 569, LOW),
- F_PIXEL_MDP( 48000000, pll8, 4, 1, 2, LOW),
- F_PIXEL_MDP( 53990000, pll8, 2, 169, 601, LOW),
- F_PIXEL_MDP( 64000000, pll8, 2, 1, 3, LOW),
- F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280, LOW),
- F_PIXEL_MDP( 76800000, pll8, 1, 1, 5, LOW),
- F_PIXEL_MDP( 85333000, pll8, 1, 2, 9, LOW),
- F_PIXEL_MDP(106500000, pll8, 1, 71, 256, NOMINAL),
- F_PIXEL_MDP(109714000, pll8, 1, 2, 7, NOMINAL),
+ F_PIXEL_MDP( 0, gnd, 1, 0, 0),
+ F_PIXEL_MDP( 25600000, pll8, 3, 1, 5),
+ F_PIXEL_MDP( 42667000, pll8, 1, 1, 9),
+ F_PIXEL_MDP( 43192000, pll8, 1, 64, 569),
+ F_PIXEL_MDP( 48000000, pll8, 4, 1, 2),
+ F_PIXEL_MDP( 53990000, pll8, 2, 169, 601),
+ F_PIXEL_MDP( 64000000, pll8, 2, 1, 3),
+ F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280),
+ F_PIXEL_MDP( 76800000, pll8, 1, 1, 5),
+ F_PIXEL_MDP( 85333000, pll8, 1, 2, 9),
+ F_PIXEL_MDP(106500000, pll8, 1, 71, 256),
+ F_PIXEL_MDP(109714000, pll8, 1, 2, 7),
F_END
};
@@ -2593,6 +2614,7 @@
.c = {
.dbg_name = "pixel_mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 85333000, NOMINAL, 170000000),
CLK_INIT(pixel_mdp_clk.c),
},
};
@@ -2612,29 +2634,28 @@
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, NOMINAL),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
F_END
};
@@ -2666,12 +2687,13 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
};
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2679,7 +2701,6 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
@@ -2691,12 +2712,12 @@
[4] = PLL_RATE(44, 0, 0, 2, 4, 0x6248F), /* 297000000 Hz */
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0, NONE),
- F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0, LOW),
- F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0, LOW),
- F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0, LOW),
- F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0, NOMINAL),
- F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0, NOMINAL),
+ F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0),
+ F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0),
+ F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0),
+ F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0),
+ F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0),
+ F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0),
F_END
};
@@ -2716,6 +2737,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -2802,7 +2824,7 @@
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2810,18 +2832,17 @@
.ns_val = NS_MM(18, 11, n, m, 0, 0, 1, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -2845,29 +2866,30 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
- F_VPE(200000000, pll2, 4, HIGH),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
+ F_VPE(200000000, pll2, 4),
F_END
};
@@ -2889,12 +2911,14 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 76800000, NOMINAL, 160000000,
+ HIGH, 200000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2902,26 +2926,25 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vfe[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, HIGH),
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
F_END
};
@@ -2945,6 +2968,8 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 228570000,
+ HIGH, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -2987,27 +3012,26 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 768000, pll4, 4, 1, 176, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 132, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 88, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 66, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 44, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 33, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 22, LOW),
- F_AIF_OSR( 8192000, pll4, 2, 1, 33, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 11, LOW),
- F_AIF_OSR(24576000, pll4, 2, 1, 11, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 768000, pll4, 4, 1, 176),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 132),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 88),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 66),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 44),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 33),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 22),
+ F_AIF_OSR( 8192000, pll4, 2, 1, 33),
+ F_AIF_OSR(12288000, pll4, 4, 1, 11),
+ F_AIF_OSR(24576000, pll4, 2, 1, 11),
F_END
};
@@ -3032,6 +3056,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -3094,28 +3119,27 @@
static CLK_AIF_BIT(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 264, LOW),
- F_PCM( 768000, pll4, 4, 1, 176, LOW),
- F_PCM( 1024000, pll4, 4, 1, 132, LOW),
- F_PCM( 1536000, pll4, 4, 1, 88, LOW),
- F_PCM( 2048000, pll4, 4, 1, 66, LOW),
- F_PCM( 3072000, pll4, 4, 1, 44, LOW),
- F_PCM( 4096000, pll4, 4, 1, 33, LOW),
- F_PCM( 6144000, pll4, 4, 1, 22, LOW),
- F_PCM( 8192000, pll4, 2, 1, 33, LOW),
- F_PCM(12288000, pll4, 4, 1, 11, LOW),
- F_PCM(24580000, pll4, 2, 1, 11, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 264),
+ F_PCM( 768000, pll4, 4, 1, 176),
+ F_PCM( 1024000, pll4, 4, 1, 132),
+ F_PCM( 1536000, pll4, 4, 1, 88),
+ F_PCM( 2048000, pll4, 4, 1, 66),
+ F_PCM( 3072000, pll4, 4, 1, 44),
+ F_PCM( 4096000, pll4, 4, 1, 33),
+ F_PCM( 6144000, pll4, 4, 1, 22),
+ F_PCM( 8192000, pll4, 2, 1, 33),
+ F_PCM(12288000, pll4, 4, 1, 11),
+ F_PCM(24580000, pll4, 2, 1, 11),
F_END
};
@@ -3139,6 +3163,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 24580000),
CLK_INIT(pcm_clk.c),
},
};
@@ -3567,7 +3592,7 @@
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("gsbi_qup_clk", gsbi12_qup_clk.c, "msm_dsps"),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.5"),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_dsps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
@@ -3577,7 +3602,7 @@
CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.1"),
- CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
+ CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
@@ -3623,11 +3648,11 @@
CLK_LOOKUP("iface_clk", adm1_p_clk.c, "msm_dmov.1"),
CLK_LOOKUP("modem_ahb1_pclk", modem_ahb1_p_clk.c, NULL),
CLK_LOOKUP("modem_ahb2_pclk", modem_ahb2_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
- CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", amp_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov7692.0"),
@@ -3643,7 +3668,7 @@
CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
+ CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
@@ -3666,8 +3691,6 @@
CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, "msm_camera_ov9726.0"),
CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
- CLK_LOOKUP("smmu_jpegd_clk", jpegd_axi_clk.c, NULL),
- CLK_LOOKUP("smmu_vfe_clk", vfe_axi_clk.c, NULL),
CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
CLK_LOOKUP("mem_clk", imem_axi_clk.c, "kgsl-3d0.0"),
@@ -3691,11 +3714,11 @@
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
- CLK_LOOKUP("smmu_pclk", smmu_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
@@ -3716,16 +3739,16 @@
CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
- CLK_LOOKUP("iommu_clk", jpegd_axi_clk.c, "msm_iommu.0"),
- CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.2"),
- CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.3"),
- CLK_LOOKUP("iommu_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
- CLK_LOOKUP("iommu_clk", vfe_axi_clk.c, "msm_iommu.6"),
- CLK_LOOKUP("iommu_clk", vcodec_axi_clk.c, "msm_iommu.7"),
- CLK_LOOKUP("iommu_clk", vcodec_axi_clk.c, "msm_iommu.8"),
- CLK_LOOKUP("iommu_clk", gfx3d_clk.c, "msm_iommu.9"),
- CLK_LOOKUP("iommu_clk", gfx2d0_clk.c, "msm_iommu.10"),
- CLK_LOOKUP("iommu_clk", gfx2d1_clk.c, "msm_iommu.11"),
+ CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
+ CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
+ CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
+ CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
+ CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
+ CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "msm_iommu.7"),
+ CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "msm_iommu.8"),
+ CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
+ CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
+ CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
@@ -3845,7 +3868,6 @@
/* Local clock driver initialization. */
static void __init msm8660_clock_init(void)
{
- soc_update_sys_vdd = msm8660_update_sys_vdd;
xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8x60");
if (IS_ERR(xo_pxo)) {
pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
@@ -3857,7 +3879,7 @@
BUG();
}
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
/* Initialize clock registers. */
reg_init();
@@ -3895,11 +3917,7 @@
if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
return rc;
- /* Remove temporary vote for HIGH vdd_dig. */
- rc = local_unvote_sys_vdd(HIGH);
- WARN(rc, "local_unvote_sys_vdd(HIGH) failed (%d)\n", rc);
-
- return rc;
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8x60_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 63d3f72..dca8268 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -185,6 +185,36 @@
#define NS_SRC_SEL(s_msb, s_lsb, s) \
BVAL(s_msb, s_lsb, s)
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ /* TODO: Update these voltages when info becomes available. */
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 1150000,
+ [VDD_DIG_LOW] = 1150000,
+ [VDD_DIG_NOMINAL] = 1150000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], vdd_uv[VDD_DIG_HIGH], 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
/*
* Clock Descriptions
@@ -283,24 +313,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* TODO: Update these voltages when info becomes available. */
-/* Update the sys_vdd voltage given a level. */
-static int msm9615_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE...LOW] = 1150000,
- [NOMINAL] = 1150000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -309,7 +321,7 @@
static struct clk_ops clk_ops_rcg_9615 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
.get_rate = rcg_clk_get_rate,
@@ -324,7 +336,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -355,33 +367,33 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -411,28 +423,28 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 960000, cxo, 4, 1, 5, LOW),
- F_GSBI_QUP( 4800000, cxo, 4, 0, 1, LOW),
- F_GSBI_QUP( 9600000, cxo, 2, 0, 1, LOW),
- F_GSBI_QUP(15058800, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 960000, cxo, 4, 1, 5),
+ F_GSBI_QUP( 4800000, cxo, 4, 0, 1),
+ F_GSBI_QUP( 9600000, cxo, 2, 0, 1),
+ F_GSBI_QUP(15058800, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -442,16 +454,15 @@
static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(19200000, cxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(19200000, cxo, 1),
F_END
};
@@ -473,6 +484,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 19200000),
CLK_INIT(pdm_clk.c),
},
};
@@ -491,14 +503,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(32000000, pll8, LOW),
+ F_PRNG(32000000, pll8),
F_END
};
@@ -516,6 +527,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -540,45 +552,44 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144300, cxo, 1, 1, 133, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144300, cxo, 1, 1, 133),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
F_END
};
static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -601,6 +612,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -624,6 +636,7 @@
.c = {
.dbg_name = "usb_hs1_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_sys_clk.c),
},
};
@@ -647,6 +660,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_xcvr_clk.c),
},
};
@@ -670,13 +684,14 @@
.c = {
.dbg_name = "usb_hsic_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_sys_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(480000000, pll14, 1, 0, 1, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(480000000, pll14, 1, 0, 1),
F_END
};
@@ -699,6 +714,7 @@
.c = {
.dbg_name = "usb_hsic_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 480000000),
CLK_INIT(usb_hsic_clk.c),
},
};
@@ -980,28 +996,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1148,28 +1163,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1193,6 +1207,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -1217,6 +1232,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -1520,13 +1536,13 @@
CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.0"),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
- CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
- CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
@@ -1547,10 +1563,10 @@
CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
@@ -1717,8 +1733,7 @@
BUG();
}
- soc_update_sys_vdd = msm9615_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -1744,7 +1759,7 @@
static int __init msm9615_clock_late_init(void)
{
- return local_unvote_sys_vdd(HIGH);
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm9615_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index c0af9b5..4e0d3e9 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -170,10 +170,25 @@
static int list_rates_show(struct seq_file *m, void *unused)
{
struct clk *clock = m->private;
- int rate, i = 0;
+ int rate, level, fmax = 0, i = 0;
- while ((rate = clock->ops->list_rate(clock, i++)) >= 0)
- seq_printf(m, "%d\n", rate);
+ /* Find max frequency supported within voltage constraints. */
+ if (!clock->vdd_class) {
+ fmax = ULONG_MAX;
+ } else {
+ for (level = 0; level < ARRAY_SIZE(clock->fmax); level++)
+ if (clock->fmax[level])
+ fmax = clock->fmax[level];
+ }
+
+ /*
+ * List supported frequencies <= fmax. Higher frequencies may appear in
+ * the frequency table, but are not valid and should not be listed.
+ */
+ while ((rate = clock->ops->list_rate(clock, i++)) >= 0) {
+ if (rate <= fmax)
+ seq_printf(m, "%u\n", rate);
+ }
return 0;
}
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index ea76512..473b439 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -48,9 +48,6 @@
DEFINE_SPINLOCK(local_clock_reg_lock);
struct clk_freq_tbl rcg_dummy_freq = F_END;
-unsigned local_sys_vdd_votes[NUM_SYS_VDD_LEVELS];
-static DEFINE_SPINLOCK(sys_vdd_vote_lock);
-
/*
* Common Set-Rate Functions
*/
@@ -264,81 +261,6 @@
clk->ns_mask = new_bank_masks->ns_mask;
}
-int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
- * SYS_VDD voting functions
- */
-
-/* Update system voltage level given the current votes. */
-static int local_update_sys_vdd(void)
-{
- static int cur_level = NUM_SYS_VDD_LEVELS;
- int level, rc = 0;
-
- if (local_sys_vdd_votes[HIGH])
- level = HIGH;
- else if (local_sys_vdd_votes[NOMINAL])
- level = NOMINAL;
- else if (local_sys_vdd_votes[LOW])
- level = LOW;
- else
- level = NONE;
-
- if (level == cur_level)
- return rc;
-
- rc = soc_update_sys_vdd(level);
- if (!rc)
- cur_level = level;
-
- return rc;
-}
-
-/* Vote for a system voltage level. */
-int local_vote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
- local_sys_vdd_votes[level]++;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]--;
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
-
- return rc;
-}
-
-/* Remove vote for a system voltage level. */
-int local_unvote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
-
- if (WARN(!local_sys_vdd_votes[level],
- "Reference counts are incorrect for level %d!\n", level))
- goto out;
-
- local_sys_vdd_votes[level]--;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]++;
-out:
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
- return rc;
-}
/*
* Clock enable/disable functions
*/
@@ -486,19 +408,25 @@
}
}
-static void _rcg_clk_enable(struct rcg_clk *clk)
+/* Enable a rate-settable clock. */
+int rcg_clk_enable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_enable_reg(clk);
clk->enabled = true;
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+ return 0;
}
-static void _rcg_clk_disable(struct rcg_clk *clk)
+/* Disable a rate-settable clock. */
+void rcg_clk_disable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_disable_reg(clk);
@@ -506,34 +434,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-/* Enable a clock and any related power rail. */
-int rcg_clk_enable(struct clk *c)
-{
- int rc;
- struct rcg_clk *clk = to_rcg_clk(c);
-
- rc = local_vote_sys_vdd(clk->current_freq->sys_vdd);
- if (rc)
- return rc;
- _rcg_clk_enable(clk);
- return rc;
-}
-
-/* Disable a clock and any related power rail. */
-void rcg_clk_disable(struct clk *c)
-{
- struct rcg_clk *clk = to_rcg_clk(c);
-
- _rcg_clk_disable(clk);
- local_unvote_sys_vdd(clk->current_freq->sys_vdd);
-}
-
-/* Turn off a clock at boot, without checking refcounts. */
-void rcg_clk_auto_off(struct clk *c)
-{
- _rcg_clk_disable(to_rcg_clk(c));
-}
-
/*
* Frequency-related functions
*/
@@ -544,25 +444,17 @@
struct clk_freq_tbl *cf;
int rc = 0;
struct clk *chld;
- unsigned long flags;
-
- spin_lock_irqsave(&clk->c.lock, flags);
/* Check if frequency is actually changed. */
cf = clk->current_freq;
if (nf == cf)
- goto unlock;
+ return 0;
if (clk->enabled) {
- /* Vote for voltage and source for new freq. */
- rc = local_vote_sys_vdd(nf->sys_vdd);
- if (rc)
- goto unlock;
+ /* Enable source clock dependency for the new freq. */
rc = clk_enable(nf->src_clk);
- if (rc) {
- local_unvote_sys_vdd(nf->sys_vdd);
- goto unlock;
- }
+ if (rc)
+ return rc;
}
spin_lock(&local_clock_reg_lock);
@@ -608,13 +500,9 @@
spin_unlock(&local_clock_reg_lock);
- /* Release requirements of the old freq. */
- if (clk->enabled) {
+ /* Release source requirements of the old freq. */
+ if (clk->enabled)
clk_disable(cf->src_clk);
- local_unvote_sys_vdd(cf->sys_vdd);
- }
-unlock:
- spin_unlock_irqrestore(&clk->c.lock, flags);
return rc;
}
@@ -985,16 +873,6 @@
return branch->enabled;
}
-void branch_clk_auto_off(struct clk *clk)
-{
- struct branch_clk *branch = to_branch_clk(clk);
- unsigned long flags;
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- __branch_clk_disable_reg(&branch->b, branch->c.dbg_name);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
int branch_reset(struct branch *clk, enum clk_reset_action action)
{
int ret = 0;
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index f62e753..ec2462a 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -74,22 +74,17 @@
const struct bank_mask_info bank1_mask;
};
-#define F_RAW(f, sc, m_v, n_v, c_v, m_m, v, e) { \
+#define F_RAW(f, sc, m_v, n_v, c_v, m_m, e) { \
.freq_hz = f, \
.src_clk = sc, \
.md_val = m_v, \
.ns_val = n_v, \
.ctl_val = c_v, \
.mnd_en_mask = m_m, \
- .sys_vdd = v, \
.extra_freq_data = e, \
}
#define FREQ_END (UINT_MAX-1)
-#define F_END \
- { \
- .freq_hz = FREQ_END, \
- .sys_vdd = LOW, \
- }
+#define F_END { .freq_hz = FREQ_END }
/**
* struct branch - branch on/off
@@ -146,7 +141,6 @@
int rcg_clk_enable(struct clk *clk);
void rcg_clk_disable(struct clk *clk);
-void rcg_clk_auto_off(struct clk *clk);
int rcg_clk_set_rate(struct clk *clk, unsigned rate);
int rcg_clk_set_min_rate(struct clk *clk, unsigned rate);
unsigned rcg_clk_get_rate(struct clk *clk);
@@ -156,17 +150,6 @@
struct clk *rcg_clk_get_parent(struct clk *c);
int rcg_clk_handoff(struct clk *c);
-/*
- * SYS_VDD voltage levels
- */
-enum sys_vdd_level {
- NONE,
- LOW,
- NOMINAL,
- HIGH,
- NUM_SYS_VDD_LEVELS
-};
-
/**
* struct fixed_clk - fixed rate clock (used for crystal oscillators)
* @rate: output rate
@@ -268,7 +251,6 @@
struct clk *branch_clk_get_parent(struct clk *clk);
int branch_clk_set_parent(struct clk *clk, struct clk *parent);
int branch_clk_is_enabled(struct clk *clk);
-void branch_clk_auto_off(struct clk *clk);
int branch_clk_reset(struct clk *c, enum clk_reset_action action);
/**
@@ -301,16 +283,9 @@
/*
* Local-clock APIs
*/
-int local_vote_sys_vdd(enum sys_vdd_level level);
-int local_unvote_sys_vdd(enum sys_vdd_level level);
bool local_clk_is_local(struct clk *clk);
/*
- * Required SoC-specific functions, implemented for every supported SoC
- */
-extern int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 9a5e644..b176301 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -149,7 +149,7 @@
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
CLK_LOOKUP("emdh_clk", emdh_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
@@ -197,7 +197,7 @@
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "footswitch-pcom.2"),
CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
@@ -274,7 +274,7 @@
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "footswitch-pcom.2"),
CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
@@ -341,7 +341,7 @@
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
CLK_LOOKUP("emdh_clk", emdh_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
diff --git a/arch/arm/mach-msm/clock-rpm.c b/arch/arm/mach-msm/clock-rpm.c
index 286b3d0..2ccebb4 100644
--- a/arch/arm/mach-msm/clock-rpm.c
+++ b/arch/arm/mach-msm/clock-rpm.c
@@ -104,11 +104,6 @@
return;
}
-static void rpm_clk_auto_off(struct clk *clk)
-{
- /* Not supported */
-}
-
static int rpm_clk_set_min_rate(struct clk *clk, unsigned rate)
{
unsigned long flags;
@@ -194,7 +189,6 @@
struct clk_ops clk_ops_rpm = {
.enable = rpm_clk_enable,
.disable = rpm_clk_disable,
- .auto_off = rpm_clk_auto_off,
.set_min_rate = rpm_clk_set_min_rate,
.get_rate = rpm_clk_get_rate,
.is_enabled = rpm_clk_is_enabled,
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 58a64a3..de89382 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -24,13 +24,116 @@
#include "clock.h"
+/* Find the voltage level required for a given rate. */
+static int find_vdd_level(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ for (level = 0; level < ARRAY_SIZE(clk->fmax); level++)
+ if (rate <= clk->fmax[level])
+ break;
+
+ if (level == ARRAY_SIZE(clk->fmax)) {
+ pr_err("Rate %lu for %s is greater than highest Fmax\n", rate,
+ clk->dbg_name);
+ return -EINVAL;
+ }
+
+ return level;
+}
+
+/* Update voltage level given the current votes. */
+static int update_vdd(struct clk_vdd_class *vdd_class)
+{
+ int level, rc;
+
+ for (level = ARRAY_SIZE(vdd_class->level_votes)-1; level > 0; level--)
+ if (vdd_class->level_votes[level])
+ break;
+
+ if (level == vdd_class->cur_level)
+ return 0;
+
+ rc = vdd_class->set_vdd(vdd_class, level);
+ if (!rc)
+ vdd_class->cur_level = level;
+
+ return rc;
+}
+
+/* Vote for a voltage level. */
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ vdd_class->level_votes[level]++;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]--;
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+
+ return rc;
+}
+
+/* Remove vote for a voltage level. */
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ if (WARN(!vdd_class->level_votes[level],
+ "Reference counts are incorrect for %s level %d\n",
+ vdd_class->class_name, level))
+ goto out;
+ vdd_class->level_votes[level]--;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]++;
+out:
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+ return rc;
+}
+
+/* Vote for a voltage level corresponding to a clock's rate. */
+static int vote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return 0;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return level;
+
+ return vote_vdd_level(clk->vdd_class, level);
+}
+
+/* Remove vote for a voltage level corresponding to a clock's rate. */
+static void unvote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return;
+
+ unvote_vdd_level(clk->vdd_class, level);
+}
+
/*
* Standard clock functions defined in include/linux/clk.h
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
- unsigned long flags;
+ unsigned long flags, rate;
struct clk *parent;
if (!clk)
@@ -39,22 +142,22 @@
spin_lock_irqsave(&clk->lock, flags);
if (clk->count == 0) {
parent = clk_get_parent(clk);
+ rate = clk_get_rate(clk);
+
ret = clk_enable(parent);
if (ret)
- goto out;
+ goto err_enable_parent;
ret = clk_enable(clk->depends);
- if (ret) {
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_depends;
+ ret = vote_rate_vdd(clk, rate);
+ if (ret)
+ goto err_vote_vdd;
if (clk->ops->enable)
ret = clk->ops->enable(clk);
- if (ret) {
- clk_disable(clk->depends);
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_clock;
} else if (clk->flags & CLKFLAG_HANDOFF_RATE) {
/*
* The clock was already enabled by handoff code so there is no
@@ -69,6 +172,16 @@
out:
spin_unlock_irqrestore(&clk->lock, flags);
+ return 0;
+
+err_enable_clock:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ clk_disable(clk->depends);
+err_enable_depends:
+ clk_disable(parent);
+err_enable_parent:
+ spin_unlock_irqrestore(&clk->lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -76,7 +189,6 @@
void clk_disable(struct clk *clk)
{
unsigned long flags;
- struct clk *parent;
if (!clk)
return;
@@ -85,10 +197,13 @@
if (WARN(clk->count == 0, "%s is unbalanced", clk->dbg_name))
goto out;
if (clk->count == 1) {
+ struct clk *parent = clk_get_parent(clk);
+ unsigned long rate = clk_get_rate(clk);
+
if (clk->ops->disable)
clk->ops->disable(clk);
+ unvote_rate_vdd(clk, rate);
clk_disable(clk->depends);
- parent = clk_get_parent(clk);
clk_disable(parent);
}
clk->count--;
@@ -117,10 +232,35 @@
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned long start_rate, flags;
+ int rc;
+
if (!clk->ops->set_rate)
return -ENOSYS;
- return clk->ops->set_rate(clk, rate);
+ spin_lock_irqsave(&clk->lock, flags);
+ if (clk->count) {
+ start_rate = clk_get_rate(clk);
+ /* Enforce vdd requirements for target frequency. */
+ rc = vote_rate_vdd(clk, rate);
+ if (rc)
+ goto err_vote_vdd;
+ rc = clk->ops->set_rate(clk, rate);
+ if (rc)
+ goto err_set_rate;
+ /* Release vdd requirements for starting frequency. */
+ unvote_rate_vdd(clk, start_rate);
+ } else {
+ rc = clk->ops->set_rate(clk, rate);
+ }
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
+
+err_set_rate:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
}
EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index f4a7363..ed5c9c6 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -33,6 +33,32 @@
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
+#define MAX_VDD_LEVELS 4
+
+/**
+ * struct clk_vdd_class - Voltage scaling class
+ * @class_name: name of the class
+ * @set_vdd: function to call when applying a new voltage setting
+ * @level_votes: array of votes for each level
+ * @cur_level: the currently set voltage level
+ * @lock: lock to protect this struct
+ */
+struct clk_vdd_class {
+ const char *class_name;
+ int (*set_vdd)(struct clk_vdd_class *v_class, int level);
+ int level_votes[MAX_VDD_LEVELS];
+ unsigned cur_level;
+ spinlock_t lock;
+};
+
+#define DEFINE_VDD_CLASS(_name, _set_vdd) \
+ struct clk_vdd_class _name = { \
+ .class_name = #_name, \
+ .set_vdd = _set_vdd, \
+ .cur_level = ARRAY_SIZE(_name.level_votes), \
+ .lock = __SPIN_LOCK_UNLOCKED(lock) \
+ }
+
struct clk_ops {
int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
@@ -57,12 +83,16 @@
* @count: enable refcount
* @lock: protects clk_enable()/clk_disable() path and @count
* @depends: non-direct parent of clock to enable when this clock is enabled
+ * @vdd_class: voltage scaling requirement class
+ * @fmax: maximum frequency in Hz supported at each voltage level
*/
struct clk {
uint32_t flags;
struct clk_ops *ops;
const char *dbg_name;
struct clk *depends;
+ struct clk_vdd_class *vdd_class;
+ unsigned long fmax[MAX_VDD_LEVELS];
struct list_head children;
struct list_head siblings;
@@ -104,6 +134,8 @@
extern struct clock_init_data qds8x50_clock_init_data;
void msm_clock_init(struct clock_init_data *data);
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level);
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level);
#ifdef CONFIG_DEBUG_FS
int clock_debug_init(struct clock_init_data *data);
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 3606c41..694a70d 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -608,7 +608,7 @@
CLK_DUMMY("core_clk", GSBI5_QUP_CLK, "spi_qsd.0", OFF),
CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF),
CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF),
- CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
@@ -616,7 +616,7 @@
CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
CLK_DUMMY("ref_clk", TSIF_REF_CLK, NULL, OFF),
- CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS3_XCVR_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS4_XCVR_CLK, NULL, OFF),
@@ -632,7 +632,7 @@
CLK_DUMMY("pcie_alt_ref_clk", PCIE_ALT_REF_CLK, NULL, OFF),
CLK_DUMMY("sata_rxoob_clk", SATA_RXOOB_CLK, NULL, OFF),
CLK_DUMMY("sata_pmalive_clk", SATA_PMALIVE_CLK, NULL, OFF),
- CLK_DUMMY("sata_phy_ref_clk", SATA_PHY_REF_CLK, NULL, OFF),
+ CLK_DUMMY("ref_clk", SATA_PHY_REF_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", GSBI1_P_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", GSBI2_P_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", GSBI3_P_CLK, "msm_serial_hsl.0", OFF),
@@ -651,11 +651,11 @@
CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF),
CLK_DUMMY("core_clk", ADM0_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", ADM0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
- CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
- CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
+ CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
@@ -676,13 +676,13 @@
CLK_DUMMY("core_clk", GFX3D_CLK, NULL, OFF),
CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
- CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
@@ -719,7 +719,7 @@
CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
- CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", SMMU_P_CLK, "msm_smmu", OFF),
CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
@@ -736,12 +736,6 @@
CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
- CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index ef7ec0b..7512414 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -1585,7 +1585,7 @@
CLK_DUMMY("core_clk", GSBI10_QUP_CLK, NULL, OFF),
CLK_DUMMY("core_clk", GSBI11_QUP_CLK, NULL, OFF),
CLK_DUMMY("core_clk", GSBI12_QUP_CLK, NULL, OFF),
- CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
@@ -1594,7 +1594,7 @@
CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC5_CLK, NULL, OFF),
CLK_DUMMY("core_clk", TSIF_REF_CLK, NULL, OFF),
- CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
@@ -1630,11 +1630,11 @@
CLK_DUMMY("iface_clk", SDC5_P_CLK, NULL, OFF),
CLK_DUMMY("core_clk", ADM0_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", ADM0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
- CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
- CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
+ CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
@@ -1655,7 +1655,7 @@
CLK_DUMMY("core_clk", GFX3D_CLK, NULL, OFF),
CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
- CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
@@ -1663,7 +1663,7 @@
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
@@ -1693,7 +1693,7 @@
CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
- CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", SMMU_P_CLK, NULL, OFF),
CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
@@ -1710,12 +1710,12 @@
CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
- CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
- CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
+ CLK_DUMMY("core_clk", JPEGD_AXI_CLK, NULL, 0),
+ CLK_DUMMY("core_clk", VFE_AXI_CLK, NULL, 0),
+ CLK_DUMMY("core_clk", VCODEC_AXI_CLK, NULL, 0),
+ CLK_DUMMY("core_clk", GFX3D_CLK, NULL, 0),
+ CLK_DUMMY("core_clk", GFX2D0_CLK, NULL, 0),
+ CLK_DUMMY("core_clk", GFX2D1_CLK, NULL, 0),
CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index 73c96fb..b04bc11 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -1060,6 +1060,12 @@
{
int ret;
+ if (cpu_is_msm8960() &&
+ SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2) {
+ pr_err("IOMMU is not supported on this SoC version.\n");
+ return -ENODEV;
+ }
+
ret = platform_device_register(&msm_root_iommu_dev);
if (ret != 0) {
pr_err("Failed to register root IOMMU device!\n");
diff --git a/arch/arm/mach-msm/devices-msm7x25.c b/arch/arm/mach-msm/devices-msm7x25.c
index c166c8d..d918315 100644
--- a/arch/arm/mach-msm/devices-msm7x25.c
+++ b/arch/arm/mach-msm/devices-msm7x25.c
@@ -942,7 +942,7 @@
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
diff --git a/arch/arm/mach-msm/devices-msm8x60.h b/arch/arm/mach-msm/devices-msm8x60.h
index 9fbe818..6b7d141 100644
--- a/arch/arm/mach-msm/devices-msm8x60.h
+++ b/arch/arm/mach-msm/devices-msm8x60.h
@@ -51,6 +51,7 @@
extern struct platform_device msm_bus_mm_fabric;
extern struct platform_device msm_bus_sys_fpb;
extern struct platform_device msm_bus_cpss_fpb;
+extern struct platform_device msm_bus_def_fab;
extern struct platform_device msm_device_smd;
extern struct platform_device msm_device_gpio;
diff --git a/arch/arm/mach-msm/footswitch-8x60.c b/arch/arm/mach-msm/footswitch-8x60.c
index 6ece538..98447fa 100644
--- a/arch/arm/mach-msm/footswitch-8x60.c
+++ b/arch/arm/mach-msm/footswitch-8x60.c
@@ -42,6 +42,7 @@
#define VED_GFS_CTL_REG REG(0x0194)
#define VFE_GFS_CTL_REG REG(0x0198)
#define VPE_GFS_CTL_REG REG(0x019C)
+#define VCAP_GFS_CTL_REG REG(0x0254)
#define CLAMP_BIT BIT(5)
#define ENABLE_BIT BIT(8)
@@ -469,6 +470,9 @@
FOOTSWITCH(FS_VPE, "fs_vpe", &standard_fs_ops,
VPE_GFS_CTL_REG, 31, true, 0,
MSM_BUS_MASTER_VPE, 0),
+ FOOTSWITCH(FS_VCAP, "fs_vcap", &standard_fs_ops,
+ VCAP_GFS_CTL_REG, 31, true, 0,
+ MSM_BUS_MASTER_VIDEO_CAP, 0),
};
static int footswitch_probe(struct platform_device *pdev)
diff --git a/arch/arm/mach-msm/footswitch.h b/arch/arm/mach-msm/footswitch.h
index 06b7c79..4882ff0 100644
--- a/arch/arm/mach-msm/footswitch.h
+++ b/arch/arm/mach-msm/footswitch.h
@@ -27,7 +27,8 @@
#define FS_VED 7
#define FS_VFE 8
#define FS_VPE 9
-#define MAX_FS 10
+#define FS_VCAP 10
+#define MAX_FS 11
#define FS_GENERIC(_drv_name, _id, _name) (&(struct platform_device){ \
.name = (_drv_name), \
diff --git a/arch/arm/mach-msm/include/mach/bam_dmux.h b/arch/arm/mach-msm/include/mach/bam_dmux.h
index e5ec166..a2b0126 100644
--- a/arch/arm/mach-msm/include/mach/bam_dmux.h
+++ b/arch/arm/mach-msm/include/mach/bam_dmux.h
@@ -35,6 +35,8 @@
enum {
BAM_DMUX_RECEIVE, /* data is struct sk_buff */
BAM_DMUX_WRITE_DONE, /* data is struct sk_buff */
+ BAM_DMUX_UL_CONNECTED, /* data is null */
+ BAM_DMUX_UL_DISCONNECTED, /*data is null */
};
/*
@@ -55,6 +57,8 @@
int msm_bam_dmux_close(uint32_t id);
int msm_bam_dmux_write(uint32_t id, struct sk_buff *skb);
+
+void msm_bam_dmux_kickoff_ul_wakeup(void);
#else
int msm_bam_dmux_open(uint32_t id, void *priv,
void (*notify)(void *priv, int event_type,
@@ -72,5 +76,9 @@
{
return -ENODEV;
}
+
+void msm_bam_dmux_kickoff_ul_wakeup(void)
+{
+}
#endif
#endif /* _BAM_DMUX_H */
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index bc41915..5a30df5 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -212,7 +212,7 @@
struct msm_actuator_info *actuator_info;
};
-int __init msm_get_cam_resources(struct msm_camera_sensor_info *);
+int msm_get_cam_resources(struct msm_camera_sensor_info *);
struct clk_lookup;
@@ -410,24 +410,24 @@
#endif
/* common init routines for use by arch/arm/mach-msm/board-*.c */
-void __init msm_add_devices(void);
-void __init msm_map_common_io(void);
-void __init msm_map_qsd8x50_io(void);
-void __init msm_map_msm8x60_io(void);
-void __init msm_map_msm8960_io(void);
-void __init msm_map_msm8930_io(void);
-void __init msm_map_apq8064_io(void);
-void __init msm_map_msm7x30_io(void);
-void __init msm_map_fsm9xxx_io(void);
-void __init msm_init_irq(void);
+void msm_add_devices(void);
+void msm_map_common_io(void);
+void msm_map_qsd8x50_io(void);
+void msm_map_msm8x60_io(void);
+void msm_map_msm8960_io(void);
+void msm_map_msm8930_io(void);
+void msm_map_apq8064_io(void);
+void msm_map_msm7x30_io(void);
+void msm_map_fsm9xxx_io(void);
+void msm_init_irq(void);
void vic_handle_irq(struct pt_regs *regs);
struct mmc_platform_data;
-int __init msm_add_sdcc(unsigned int controller,
+int msm_add_sdcc(unsigned int controller,
struct mmc_platform_data *plat);
struct msm_usb_host_platform_data;
-int __init msm_add_host(unsigned int host,
+int msm_add_host(unsigned int host,
struct msm_usb_host_platform_data *plat);
#if defined(CONFIG_USB_FUNCTION_MSM_HSUSB) \
|| defined(CONFIG_USB_MSM_72K) || defined(CONFIG_USB_MSM_72K_MODULE)
@@ -436,8 +436,8 @@
static inline void msm_hsusb_set_vbus_state(int online) {}
#endif
-void __init msm_snddev_init(void);
-void __init msm_snddev_init_timpani(void);
+void msm_snddev_init(void);
+void msm_snddev_init_timpani(void);
void msm_snddev_poweramp_on(void);
void msm_snddev_poweramp_off(void);
void msm_snddev_hsed_voltage_on(void);
diff --git a/arch/arm/mach-msm/include/mach/irqs-copper.h b/arch/arm/mach-msm/include/mach/irqs-copper.h
new file mode 100644
index 0000000..d019047
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-copper.h
@@ -0,0 +1,47 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_COPPER_H
+#define __ASM_ARCH_MSM_IRQS_COPPER_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/*
+ * 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC (GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
+#define AVS_SVICINT (GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
+#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
+/* PPI 15 is unused */
+
+#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
+#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 16)
+#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
+
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 156
+#define NR_BOARD_IRQS 100
+#define NR_TLMM_MSM_DIR_CONN_IRQ 8
+#define NR_MSM_GPIOS NR_GPIO_IRQS
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index b086bff..8c1e4ff 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -49,7 +49,9 @@
#else
-#if defined(CONFIG_ARCH_MSM9615)
+#if defined(CONFIG_ARCH_MSMCOPPER)
+#include "irqs-copper.h"
+#elif defined(CONFIG_ARCH_MSM9615)
#include "irqs-9615.h"
#elif defined(CONFIG_ARCH_MSM7X30)
#include "irqs-7x30.h"
diff --git a/arch/arm/mach-msm/include/mach/msm_bus_board.h b/arch/arm/mach-msm/include/mach/msm_bus_board.h
index 644e1b1..2eb504a 100644
--- a/arch/arm/mach-msm/include/mach/msm_bus_board.h
+++ b/arch/arm/mach-msm/include/mach/msm_bus_board.h
@@ -36,6 +36,7 @@
const unsigned int nslaves;
const unsigned int ntieredslaves;
bool il_flag;
+ const struct msm_bus_board_algorithm *board_algo;
};
enum msm_bus_bw_tier_type {
@@ -55,12 +56,23 @@
extern struct msm_bus_fabric_registration msm_bus_mm_fabric_pdata;
extern struct msm_bus_fabric_registration msm_bus_sys_fpb_pdata;
extern struct msm_bus_fabric_registration msm_bus_cpss_fpb_pdata;
+extern struct msm_bus_fabric_registration msm_bus_def_fab_pdata;
-void msm_bus_board_assign_iids(struct msm_bus_fabric_registration
- *fabreg, int fabid);
-int msm_bus_board_get_iid(int id);
+extern struct msm_bus_fabric_registration msm_bus_8960_apps_fabric_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8960_sys_fabric_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8960_mm_fabric_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8960_sys_fpb_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8960_cpss_fpb_pdata;
+
+extern struct msm_bus_fabric_registration msm_bus_8064_apps_fabric_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8064_sys_fabric_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8064_mm_fabric_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8064_sys_fpb_pdata;
+extern struct msm_bus_fabric_registration msm_bus_8064_cpss_fpb_pdata;
+
void msm_bus_rpm_set_mt_mask(void);
int msm_bus_board_rpm_get_il_ids(uint16_t *id);
+int msm_bus_board_get_iid(int id);
/*
* These macros specify the convention followed for allocating
@@ -124,6 +136,7 @@
/* Topology related enums */
enum msm_bus_fabric_type {
+ MSM_BUS_FAB_DEFAULT = 0,
MSM_BUS_FAB_APPSS = 0,
MSM_BUS_FAB_SYSTEM = 1024,
MSM_BUS_FAB_MMSS = 2048,
@@ -180,7 +193,15 @@
MSM_BUS_MASTER_MSS_SW_PROC,
MSM_BUS_MASTER_MSS_FW_PROC,
MSM_BUS_MMSS_MASTER_UNUSED_2,
+ MSM_BUS_MASTER_GSS_NAV,
+ MSM_BUS_MASTER_PCIE,
+ MSM_BUS_MASTER_SATA,
+ MSM_BUS_MASTER_CRYPTO,
+ MSM_BUS_MASTER_VIDEO_CAP,
+ MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
+ MSM_BUS_MASTER_VIDEO_ENC,
+ MSM_BUS_MASTER_VIDEO_DEC,
MSM_BUS_MASTER_LAST = MSM_BUS_MMSS_MASTER_UNUSED_2,
MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM =
@@ -263,6 +284,8 @@
MSM_BUS_SLAVE_MSM_DIMEM,
MSM_BUS_SLAVE_MSM_TCSR,
MSM_BUS_SLAVE_MSM_PRNG,
+ MSM_BUS_SLAVE_GSS,
+ MSM_BUS_SLAVE_SATA,
MSM_BUS_SLAVE_LAST = MSM_BUS_SLAVE_MSM_PRNG,
MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM =
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-copper.h b/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
new file mode 100644
index 0000000..d613671
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-copper.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_COPPER_H
+#define __ASM_ARCH_MSM_IOMAP_COPPER_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * io desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define COPPER_QGIC_DIST_PHYS 0xF9000000
+#define COPPER_QGIC_DIST_SIZE SZ_4K
+
+#define COPPER_QGIC_CPU_PHYS 0xF9002000
+#define COPPER_QGIC_CPU_SIZE SZ_4K
+
+#define COPPER_TLMM_PHYS 0xFC4A0000
+#define COPPER_TLMM_SIZE SZ_16K
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 426dbad..256099b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -44,7 +44,8 @@
#endif
#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064) || \
- defined(CONFIG_ARCH_MSM8930) || defined(CONFIG_ARCH_MSM9615)
+ defined(CONFIG_ARCH_MSM8930) || defined(CONFIG_ARCH_MSM9615) || \
+ defined(CONFIG_ARCH_MSMCOPPER)
/* Unified iomap */
#define MSM_TMR_BASE IOMEM(0xFA000000) /* 4K */
@@ -85,6 +86,7 @@
#include "msm_iomap-8930.h"
#include "msm_iomap-8064.h"
#include "msm_iomap-9615.h"
+#include "msm_iomap-copper.h"
#else
/* Legacy single-target iomap */
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/rtac.h b/arch/arm/mach-msm/include/mach/qdsp6v2/rtac.h
index 3d3653b..f5bea31 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/rtac.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/rtac.h
@@ -20,7 +20,8 @@
#define RTAC_VOICE_MODES 2
void rtac_add_adm_device(u32 port_id, u32 copp_id, u32 path_id, u32 popp_id);
-void rtac_remove_adm_device(u32 port_id, u32 popp_id);
+void rtac_remove_adm_device(u32 port_id);
+void rtac_remove_popp_from_adm_devices(u32 popp_id);
void rtac_add_voice(u32 cvs_handle, u32 cvp_handle, u32 rx_afe_port,
u32 tx_afe_port, u32 session_id);
void rtac_remove_voice(u32 cvs_handle);
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator.h b/arch/arm/mach-msm/include/mach/rpm-regulator.h
index 8b5a1e7..7ffa2985 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator.h
@@ -155,6 +155,9 @@
*
* This function may only be called for regulators which have the sleep flag
* specified in their private data.
+ *
+ * Consumers can vote to disable a regulator with this function by passing
+ * min_uV = 0 and max_uV = 0.
*/
int rpm_vreg_set_voltage(int vreg_id, enum rpm_vreg_voter voter, int min_uV,
int max_uV, int sleep_also);
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index dbfbad2..dbde068 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -44,7 +44,7 @@
MSM_CPU_7X25A,
MSM_CPU_7X25AA,
MSM_CPU_8064,
- MSM_CPU_8X30,
+ MSM_CPU_8930,
MSM_CPU_7X27AA,
MSM_CPU_9615,
};
@@ -208,9 +208,13 @@
#endif
}
-static inline int cpu_is_msm8x30(void)
+static inline int cpu_is_msm8930(void)
{
- return read_msm_cpu_type() == MSM_CPU_8X30;
+#ifdef CONFIG_ARCH_MSM8930
+ return read_msm_cpu_type() == MSM_CPU_8930;
+#else
+ return 0;
+#endif
}
static inline int cpu_is_fsm9xxx(void)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 72acab8..171f482 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -277,6 +277,19 @@
}
#endif /* CONFIG_ARCH_APQ8064 */
+#ifdef CONFIG_ARCH_MSMCOPPER
+static struct map_desc msm_copper_io_desc[] __initdata = {
+ MSM_CHIP_DEVICE(QGIC_DIST, COPPER),
+ MSM_CHIP_DEVICE(QGIC_CPU, COPPER),
+ MSM_CHIP_DEVICE(TLMM, COPPER),
+};
+
+void __init msm_map_copper_io(void)
+{
+ msm_map_io(msm_copper_io_desc, ARRAY_SIZE(msm_copper_io_desc));
+}
+#endif /* CONFIG_ARCH_MSMCOPPER */
+
#ifdef CONFIG_ARCH_MSM7X30
static struct map_desc msm7x30_io_desc[] __initdata = {
MSM_DEVICE(VIC),
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index e5fb441..0a77781 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -184,9 +184,6 @@
SET_TTBCR(base, ctx, 0);
SET_TTBR0_PA(base, ctx, (pgtable >> TTBR0_PA_SHIFT));
- /* Set interrupt number to "secure" interrupt */
- SET_IRPTNDX(base, ctx, 0);
-
/* Enable context fault interrupt */
SET_CFEIE(base, ctx, 1);
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index f0e0b33..ca2ecc6 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -151,7 +151,7 @@
goto fail;
}
- iommu_pclk = clk_get(NULL, "smmu_pclk");
+ iommu_pclk = clk_get_sys("msm_iommu", "iface_clk");
if (IS_ERR(iommu_pclk)) {
ret = -ENODEV;
goto fail;
@@ -161,7 +161,7 @@
if (ret)
goto fail_enable;
- iommu_clk = clk_get(&pdev->dev, "iommu_clk");
+ iommu_clk = clk_get(&pdev->dev, "core_clk");
if (!IS_ERR(iommu_clk)) {
if (clk_get_rate(iommu_clk) == 0)
@@ -335,6 +335,9 @@
SET_M2VCBR_N(drvdata->base, mid, 0);
SET_CBACR_N(drvdata->base, c->num, 0);
+ /* Route page faults to the non-secure interrupt */
+ SET_IRPTNDX(drvdata->base, c->num, 1);
+
/* Set VMID = 0 */
SET_VMID(drvdata->base, mid, 0);
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_arb.c b/arch/arm/mach-msm/msm_bus/msm_bus_arb.c
index 7565eb3..56bc71d 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_arb.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_arb.c
@@ -394,7 +394,7 @@
int ret = 0;
struct msm_bus_fabric_device *fabdev = to_msm_bus_fabric_device(dev);
MSM_BUS_DBG("Committing: fabid: %d\n", fabdev->id);
- ret = fabdev->algo->commit(fabdev, (int)data);
+ ret = fabdev->algo->commit(fabdev);
return ret;
}
@@ -556,7 +556,7 @@
client->curr = index;
ctx = ACTIVE_CTX;
msm_bus_dbg_client_data(client->pdata, index, cl);
- bus_for_each_dev(&msm_bus_type, NULL, (void *)ctx, msm_bus_commit_fn);
+ bus_for_each_dev(&msm_bus_type, NULL, NULL, msm_bus_commit_fn);
err:
mutex_unlock(&msm_bus_lock);
@@ -613,6 +613,19 @@
return 0;
}
+int msm_bus_board_get_iid(int id)
+{
+ struct msm_bus_fabric_device *deffab;
+
+ deffab = msm_bus_get_fabric_device(MSM_BUS_FAB_DEFAULT);
+ if (!deffab) {
+ MSM_BUS_ERR("Error finding default fabric\n");
+ return -ENXIO;
+ }
+
+ return deffab->board_algo->get_iid(id);
+}
+
void msm_bus_scale_client_reset_pnodes(uint32_t cl)
{
int i, src, pnode, index;
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
index 13b59ed..fde2322 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
@@ -805,80 +805,8 @@
},
};
-struct msm_bus_fabric_registration msm_bus_apps_fabric_pdata = {
- .id = MSM_BUS_FAB_APPSS,
- .name = "msm_apps_fab",
- .info = apps_fabric_info,
- .len = ARRAY_SIZE(apps_fabric_info),
- .ahb = 0,
- .fabclk[DUAL_CTX] = "afab_clk",
- .fabclk[ACTIVE_CTX] = "afab_a_clk",
- .haltid = MSM_RPM_ID_APPS_FABRIC_HALT_0,
- .offset = MSM_RPM_ID_APPS_FABRIC_ARB_0,
- .nmasters = 4,
- .nslaves = 4,
- .ntieredslaves = 2,
-};
-
-struct msm_bus_fabric_registration msm_bus_sys_fabric_pdata = {
- .id = MSM_BUS_FAB_SYSTEM,
- .name = "msm_sys_fab",
- system_fabric_info,
- ARRAY_SIZE(system_fabric_info),
- .ahb = 0,
- .fabclk[DUAL_CTX] = "sfab_clk",
- .fabclk[ACTIVE_CTX] = "sfab_a_clk",
- .haltid = MSM_RPM_ID_SYSTEM_FABRIC_HALT_0,
- .offset = MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
- .nmasters = 17,
- .nslaves = 9,
- .ntieredslaves = 2,
-};
-
-struct msm_bus_fabric_registration msm_bus_mm_fabric_pdata = {
- .id = MSM_BUS_FAB_MMSS,
- .name = "msm_mm_fab",
- mmss_fabric_info,
- ARRAY_SIZE(mmss_fabric_info),
- .ahb = 0,
- .fabclk[DUAL_CTX] = "mmfab_clk",
- .fabclk[ACTIVE_CTX] = "mmfab_a_clk",
- .haltid = MSM_RPM_ID_MM_FABRIC_HALT_0,
- .offset = MSM_RPM_ID_MM_FABRIC_ARB_0,
- .nmasters = 14,
- .nslaves = 4,
- .ntieredslaves = 3,
-};
-
-struct msm_bus_fabric_registration msm_bus_sys_fpb_pdata = {
- .id = MSM_BUS_FAB_SYSTEM_FPB,
- .name = "msm_sys_fpb",
- sys_fpb_fabric_info,
- ARRAY_SIZE(sys_fpb_fabric_info),
- .ahb = 1,
- .fabclk[DUAL_CTX] = "sfpb_clk",
- .fabclk[ACTIVE_CTX] = "sfpb_a_clk",
- .nmasters = 0,
- .nslaves = 0,
- .ntieredslaves = 0,
-};
-
-struct msm_bus_fabric_registration msm_bus_cpss_fpb_pdata = {
- .id = MSM_BUS_FAB_CPSS_FPB,
- .name = "msm_cpss_fpb",
- cpss_fpb_fabric_info,
- ARRAY_SIZE(cpss_fpb_fabric_info),
- .ahb = 1,
- .fabclk[DUAL_CTX] = "cfpb_clk",
- .fabclk[ACTIVE_CTX] = "cfpb_a_clk",
- .nmasters = 0,
- .nslaves = 0,
- .ntieredslaves = 0,
-};
-
-static void msm_bus_board_get_ids(
- struct msm_bus_fabric_registration *fabreg,
- int fabid)
+static void msm_bus_board_assign_iids(struct msm_bus_fabric_registration
+ *fabreg, int fabid)
{
int i;
for (i = 0; i < fabreg->len; i++) {
@@ -895,17 +823,93 @@
}
}
-void msm_bus_board_assign_iids(struct msm_bus_fabric_registration *fabreg,
- int fabid)
-{
- msm_bus_board_get_ids(fabreg, fabid);
-}
-int msm_bus_board_get_iid(int id)
+static int msm_bus_board_8660_get_iid(int id)
{
return ((id < SLAVE_ID_KEY) ? master_iids[id] : slave_iids[id -
SLAVE_ID_KEY]);
}
+static struct msm_bus_board_algorithm msm_bus_board_algo = {
+ .get_iid = msm_bus_board_8660_get_iid,
+ .assign_iids = msm_bus_board_assign_iids,
+};
+
+struct msm_bus_fabric_registration msm_bus_apps_fabric_pdata = {
+ .id = MSM_BUS_FAB_APPSS,
+ .name = "msm_apps_fab",
+ .info = apps_fabric_info,
+ .len = ARRAY_SIZE(apps_fabric_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "afab_clk",
+ .fabclk[ACTIVE_CTX] = "afab_a_clk",
+ .haltid = MSM_RPM_ID_APPS_FABRIC_HALT_0,
+ .offset = MSM_RPM_ID_APPS_FABRIC_ARB_0,
+ .nmasters = 4,
+ .nslaves = 4,
+ .ntieredslaves = 2,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_sys_fabric_pdata = {
+ .id = MSM_BUS_FAB_SYSTEM,
+ .name = "msm_sys_fab",
+ system_fabric_info,
+ ARRAY_SIZE(system_fabric_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "sfab_clk",
+ .fabclk[ACTIVE_CTX] = "sfab_a_clk",
+ .haltid = MSM_RPM_ID_SYSTEM_FABRIC_HALT_0,
+ .offset = MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
+ .nmasters = 17,
+ .nslaves = 9,
+ .ntieredslaves = 2,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_mm_fabric_pdata = {
+ .id = MSM_BUS_FAB_MMSS,
+ .name = "msm_mm_fab",
+ mmss_fabric_info,
+ ARRAY_SIZE(mmss_fabric_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "mmfab_clk",
+ .fabclk[ACTIVE_CTX] = "mmfab_a_clk",
+ .haltid = MSM_RPM_ID_MM_FABRIC_HALT_0,
+ .offset = MSM_RPM_ID_MM_FABRIC_ARB_0,
+ .nmasters = 14,
+ .nslaves = 4,
+ .ntieredslaves = 3,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_sys_fpb_pdata = {
+ .id = MSM_BUS_FAB_SYSTEM_FPB,
+ .name = "msm_sys_fpb",
+ sys_fpb_fabric_info,
+ ARRAY_SIZE(sys_fpb_fabric_info),
+ .ahb = 1,
+ .fabclk[DUAL_CTX] = "sfpb_clk",
+ .fabclk[ACTIVE_CTX] = "sfpb_a_clk",
+ .nmasters = 0,
+ .nslaves = 0,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_cpss_fpb_pdata = {
+ .id = MSM_BUS_FAB_CPSS_FPB,
+ .name = "msm_cpss_fpb",
+ cpss_fpb_fabric_info,
+ ARRAY_SIZE(cpss_fpb_fabric_info),
+ .ahb = 1,
+ .fabclk[DUAL_CTX] = "cfpb_clk",
+ .fabclk[ACTIVE_CTX] = "cfpb_a_clk",
+ .nmasters = 0,
+ .nslaves = 0,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+};
+
int msm_bus_board_rpm_get_il_ids(uint16_t id[])
{
return -ENXIO;
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
index 8ab1899..47f3c81 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
@@ -832,80 +832,8 @@
},
};
-struct msm_bus_fabric_registration msm_bus_apps_fabric_pdata = {
- .id = MSM_BUS_FAB_APPSS,
- .name = "msm_apps_fab",
- .info = apps_fabric_info,
- .len = ARRAY_SIZE(apps_fabric_info),
- .ahb = 0,
- .fabclk[DUAL_CTX] = "afab_clk",
- .fabclk[ACTIVE_CTX] = "afab_a_clk",
- .haltid = MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0,
- .offset = MSM_RPM_ID_APPS_FABRIC_ARB_0,
- .nmasters = 6,
- .nslaves = 5,
- .ntieredslaves = 3,
-};
-
-struct msm_bus_fabric_registration msm_bus_sys_fabric_pdata = {
- .id = MSM_BUS_FAB_SYSTEM,
- .name = "msm_sys_fab",
- system_fabric_info,
- ARRAY_SIZE(system_fabric_info),
- .ahb = 0,
- .fabclk[DUAL_CTX] = "sfab_clk",
- .fabclk[ACTIVE_CTX] = "sfab_a_clk",
- .haltid = MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0,
- .offset = MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
- .nmasters = 15,
- .nslaves = 12,
- .ntieredslaves = 3,
-};
-
-struct msm_bus_fabric_registration msm_bus_mm_fabric_pdata = {
- .id = MSM_BUS_FAB_MMSS,
- .name = "msm_mm_fab",
- mmss_fabric_info,
- ARRAY_SIZE(mmss_fabric_info),
- .ahb = 0,
- .fabclk[DUAL_CTX] = "mmfab_clk",
- .fabclk[ACTIVE_CTX] = "mmfab_a_clk",
- .haltid = MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0,
- .offset = MSM_RPM_ID_MM_FABRIC_ARB_0,
- .nmasters = 14,
- .nslaves = 4,
- .ntieredslaves = 3,
-};
-
-struct msm_bus_fabric_registration msm_bus_sys_fpb_pdata = {
- .id = MSM_BUS_FAB_SYSTEM_FPB,
- .name = "msm_sys_fpb",
- sys_fpb_fabric_info,
- ARRAY_SIZE(sys_fpb_fabric_info),
- .ahb = 1,
- .fabclk[DUAL_CTX] = "sfpb_clk",
- .fabclk[ACTIVE_CTX] = "sfpb_a_clk",
- .nmasters = 0,
- .nslaves = 0,
- .ntieredslaves = 0,
-};
-
-struct msm_bus_fabric_registration msm_bus_cpss_fpb_pdata = {
- .id = MSM_BUS_FAB_CPSS_FPB,
- .name = "msm_cpss_fpb",
- cpss_fpb_fabric_info,
- ARRAY_SIZE(cpss_fpb_fabric_info),
- .ahb = 1,
- .fabclk[DUAL_CTX] = "cfpb_clk",
- .fabclk[ACTIVE_CTX] = "cfpb_a_clk",
- .nmasters = 0,
- .nslaves = 0,
- .ntieredslaves = 0,
-};
-
-static void msm_bus_board_get_ids(
- struct msm_bus_fabric_registration *fabreg,
- int fabid)
+static void msm_bus_board_assign_iids(struct msm_bus_fabric_registration
+ *fabreg, int fabid)
{
int i;
for (i = 0; i < fabreg->len; i++) {
@@ -922,12 +850,7 @@
}
}
-void msm_bus_board_assign_iids(struct msm_bus_fabric_registration *fabreg,
- int fabid)
-{
- msm_bus_board_get_ids(fabreg, fabid);
-}
-int msm_bus_board_get_iid(int id)
+static int msm_bus_board_8960_get_iid(int id)
{
if ((id < SLAVE_ID_KEY && id >= NMASTERS) ||
id >= (SLAVE_ID_KEY + NSLAVES)) {
@@ -939,6 +862,87 @@
SLAVE_ID_KEY]);
}
+static struct msm_bus_board_algorithm msm_bus_board_algo = {
+ .get_iid = msm_bus_board_8960_get_iid,
+ .assign_iids = msm_bus_board_assign_iids,
+};
+
+struct msm_bus_fabric_registration msm_bus_8960_apps_fabric_pdata = {
+ .id = MSM_BUS_FAB_APPSS,
+ .name = "msm_apps_fab",
+ .info = apps_fabric_info,
+ .len = ARRAY_SIZE(apps_fabric_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "afab_clk",
+ .fabclk[ACTIVE_CTX] = "afab_a_clk",
+ .haltid = MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0,
+ .offset = MSM_RPM_ID_APPS_FABRIC_ARB_0,
+ .nmasters = 6,
+ .nslaves = 5,
+ .ntieredslaves = 3,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_8960_sys_fabric_pdata = {
+ .id = MSM_BUS_FAB_SYSTEM,
+ .name = "msm_sys_fab",
+ system_fabric_info,
+ ARRAY_SIZE(system_fabric_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "sfab_clk",
+ .fabclk[ACTIVE_CTX] = "sfab_a_clk",
+ .haltid = MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0,
+ .offset = MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
+ .nmasters = 15,
+ .nslaves = 12,
+ .ntieredslaves = 3,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_8960_mm_fabric_pdata = {
+ .id = MSM_BUS_FAB_MMSS,
+ .name = "msm_mm_fab",
+ mmss_fabric_info,
+ ARRAY_SIZE(mmss_fabric_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "mmfab_clk",
+ .fabclk[ACTIVE_CTX] = "mmfab_a_clk",
+ .haltid = MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0,
+ .offset = MSM_RPM_ID_MM_FABRIC_ARB_0,
+ .nmasters = 14,
+ .nslaves = 4,
+ .ntieredslaves = 3,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_8960_sys_fpb_pdata = {
+ .id = MSM_BUS_FAB_SYSTEM_FPB,
+ .name = "msm_sys_fpb",
+ sys_fpb_fabric_info,
+ ARRAY_SIZE(sys_fpb_fabric_info),
+ .ahb = 1,
+ .fabclk[DUAL_CTX] = "sfpb_clk",
+ .fabclk[ACTIVE_CTX] = "sfpb_a_clk",
+ .nmasters = 0,
+ .nslaves = 0,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+};
+
+struct msm_bus_fabric_registration msm_bus_8960_cpss_fpb_pdata = {
+ .id = MSM_BUS_FAB_CPSS_FPB,
+ .name = "msm_cpss_fpb",
+ cpss_fpb_fabric_info,
+ ARRAY_SIZE(cpss_fpb_fabric_info),
+ .ahb = 1,
+ .fabclk[DUAL_CTX] = "cfpb_clk",
+ .fabclk[ACTIVE_CTX] = "cfpb_a_clk",
+ .nmasters = 0,
+ .nslaves = 0,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+};
+
int msm_bus_board_rpm_get_il_ids(uint16_t id[])
{
id[0] = MSM_RPM_STATUS_ID_EBI1_CH0_RANGE;
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_core.h b/arch/arm/mach-msm/msm_bus/msm_bus_core.h
index 56a5b8da..8a46026 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_core.h
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_core.h
@@ -107,6 +107,7 @@
const char *name;
struct device dev;
const struct msm_bus_fab_algorithm *algo;
+ const struct msm_bus_board_algorithm *board_algo;
int visited;
};
#define to_msm_bus_fabric_device(d) container_of(d, \
@@ -121,8 +122,7 @@
unsigned int cl_active_flag);
int (*port_halt)(struct msm_bus_fabric_device *fabdev, int portid);
int (*port_unhalt)(struct msm_bus_fabric_device *fabdev, int portid);
- int (*commit)(struct msm_bus_fabric_device *fabdev,
- int active_only);
+ int (*commit)(struct msm_bus_fabric_device *fabdev);
struct msm_bus_inode_info *(*find_node)(struct msm_bus_fabric_device
*fabdev, int id);
struct msm_bus_inode_info *(*find_gw_node)(struct msm_bus_fabric_device
@@ -133,6 +133,12 @@
long int add_bw, int *master_tiers, int ctx);
};
+struct msm_bus_board_algorithm {
+ void (*assign_iids)(struct msm_bus_fabric_registration *fabreg,
+ int fabid);
+ int (*get_iid)(int id);
+};
+
/**
* Used to store the list of fabrics and other info to be
* maintained outside the fabric structure.
@@ -160,8 +166,7 @@
struct msm_rpm_iv_pair *allocate_rpm_data(struct msm_bus_fabric_registration
*fab_pdata);
int msm_bus_rpm_commit(struct msm_bus_fabric_registration
- *fab_pdata, int ctx, struct msm_rpm_iv_pair *rpm_data,
- void *cdata);
+ *fab_pdata, struct msm_rpm_iv_pair *rpm_data, void **cdata);
void free_commit_data(void *cdata);
void msm_bus_rpm_update_bw(struct msm_bus_inode_info *hop,
struct msm_bus_inode_info *info,
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c b/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
index fe6dbed..1747425 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
@@ -418,13 +418,10 @@
* msm_bus_fabric_rpm_commit() - Commit the arbitration data to RPM
* @fabric: Fabric for which the data should be committed
* */
-static int msm_bus_fabric_rpm_commit(struct msm_bus_fabric_device *fabdev,
- int ctx)
-
+static int msm_bus_fabric_rpm_commit(struct msm_bus_fabric_device *fabdev)
{
int status = 0;
struct msm_bus_fabric *fabric = to_msm_bus_fabric(fabdev);
- void *cdata;
/*
* For a non-zero bandwidth request, clocks should be enabled before
@@ -441,9 +438,8 @@
goto skip_arb;
}
- cdata = fabric->cdata[ctx];
- status = msm_bus_rpm_commit(fabric->pdata, ctx,
- fabric->rpm_data, cdata);
+ status = msm_bus_rpm_commit(fabric->pdata, fabric->rpm_data,
+ (void **)fabric->cdata);
if (status)
MSM_BUS_DBG("Error committing arb data for fabric: %d\n",
fabric->fabdev.id);
@@ -653,7 +649,9 @@
pdata->il_flag = msm_bus_rpm_is_mem_interleaved();
fabric->ahb = pdata->ahb;
fabric->pdata = pdata;
- msm_bus_board_assign_iids(fabric->pdata, fabric->fabdev.id);
+ fabric->pdata->board_algo->assign_iids(fabric->pdata,
+ fabric->fabdev.id);
+ fabric->fabdev.board_algo = fabric->pdata->board_algo;
for (ctx = 0; ctx < NUM_CTX; ctx++) {
if (pdata->fabclk[ctx]) {
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c b/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
index 332d3c1..84e2da5 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
@@ -325,16 +325,35 @@
#define RPM_SHIFT_VAL 16
#define RPM_SHIFT(n) ((n) << RPM_SHIFT_VAL)
-/**
- * msm_bus_rpm_commit() - Commit the arbitration data to RPM
- * @fabric: Fabric for which the data should be committed
- * */
-int msm_bus_rpm_commit(struct msm_bus_fabric_registration
+static int msm_bus_rpm_compare_cdata(
+ struct msm_bus_fabric_registration *fab_pdata,
+ struct commit_data *cd1, struct commit_data *cd2)
+{
+ size_t n;
+ int ret;
+ n = sizeof(uint16_t) * fab_pdata->nslaves;
+ ret = memcmp(cd1->bwsum, cd2->bwsum, n);
+ if (ret) {
+ MSM_BUS_DBG("Commit Data bwsum not equal\n");
+ return ret;
+ }
+
+ n = sizeof(uint16_t *) * ((fab_pdata->ntieredslaves *
+ fab_pdata->nmasters) + 1);
+ ret = memcmp(cd1->arb, cd2->arb, n);
+ if (ret) {
+ MSM_BUS_DBG("Commit Data arb[%d] not equal\n", i);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int msm_bus_rpm_commit_arb(struct msm_bus_fabric_registration
*fab_pdata, int ctx, struct msm_rpm_iv_pair *rpm_data,
- void *cdata)
+ struct commit_data *cd, bool valid)
{
int i, j, offset = 0, status = 0, count, index = 0;
- struct commit_data *cd = (struct commit_data *)cdata;
/*
* count is the number of 2-byte words required to commit the
* data to rpm. This is calculated by the following formula.
@@ -398,12 +417,33 @@
nmasters, fab_pdata->nslaves, fab_pdata->ntieredslaves,
MSM_BUS_DBG_OP);
if (fab_pdata->rpm_enabled) {
- if (ctx == ACTIVE_CTX)
- status = msm_rpm_set(MSM_RPM_CTX_SET_0, rpm_data,
- count);
+ if (valid) {
+ if (ctx == ACTIVE_CTX) {
+ status = msm_rpm_set(MSM_RPM_CTX_SET_0,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_set returned: %d\n",
+ status);
+ } else if (ctx == DUAL_CTX) {
+ status = msm_rpm_set(MSM_RPM_CTX_SET_SLEEP,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_set returned: %d\n",
+ status);
+ }
+ } else {
+ if (ctx == ACTIVE_CTX) {
+ status = msm_rpm_clear(MSM_RPM_CTX_SET_0,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_clear returned: %d\n",
+ status);
+ } else if (ctx == DUAL_CTX) {
+ status = msm_rpm_clear(MSM_RPM_CTX_SET_SLEEP,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_clear returned: %d\n",
+ status);
+ }
+ }
}
- MSM_BUS_DBG("msm_rpm_set returned: %d\n", status);
return status;
}
@@ -571,14 +611,37 @@
return rpm_data;
}
-int msm_bus_rpm_commit(struct msm_bus_fabric_registration
- *fab_pdata, int ctx, struct msm_rpm_iv_pair *rpm_data,
- void *cdata)
+static int msm_bus_rpm_compare_cdata(
+ struct msm_bus_fabric_registration *fab_pdata,
+ struct commit_data *cd1, struct commit_data *cd2)
{
+ size_t n;
+ int i, ret;
+ n = sizeof(uint16_t) * fab_pdata->nslaves;
+ ret = memcmp(cd1->bwsum, cd2->bwsum, n);
+ if (ret) {
+ MSM_BUS_DBG("Commit Data bwsum not equal\n");
+ return ret;
+ }
+ n = sizeof(uint8_t *) * ((fab_pdata->ntieredslaves *
+ fab_pdata->nmasters) + 1);
+ for (i = 0; i < NUM_TIERS; i++) {
+ ret = memcmp(cd1->arb[i], cd2->arb[i], n);
+ if (ret) {
+ MSM_BUS_DBG("Commit Data arb[%d] not equal\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int msm_bus_rpm_commit_arb(struct msm_bus_fabric_registration
+ *fab_pdata, int ctx, struct msm_rpm_iv_pair *rpm_data,
+ struct commit_data *cd, bool valid)
+{
int i, j, k, offset = 0, status = 0, count, index = 0;
- struct commit_data *cd = (struct commit_data *)cdata;
-
/*
* count is the number of 2-byte words required to commit the
* data to rpm. This is calculated by the following formula.
@@ -646,16 +709,37 @@
}
MSM_FAB_DBG("calling msm_rpm_set: %d\n", status);
- msm_bus_dbg_commit_data(fab_pdata->name, cdata, fab_pdata->
+ msm_bus_dbg_commit_data(fab_pdata->name, (void *)cd, fab_pdata->
nmasters, fab_pdata->nslaves, fab_pdata->ntieredslaves,
MSM_BUS_DBG_OP);
if (fab_pdata->rpm_enabled) {
- if (ctx == ACTIVE_CTX)
- status = msm_rpm_set(MSM_RPM_CTX_SET_0, rpm_data,
- count);
+ if (valid) {
+ if (ctx == ACTIVE_CTX) {
+ status = msm_rpm_set(MSM_RPM_CTX_SET_0,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_set returned: %d\n",
+ status);
+ } else if (ctx == DUAL_CTX) {
+ status = msm_rpm_set(MSM_RPM_CTX_SET_SLEEP,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_set returned: %d\n",
+ status);
+ }
+ } else {
+ if (ctx == ACTIVE_CTX) {
+ status = msm_rpm_clear(MSM_RPM_CTX_SET_0,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_clear returned: %d\n",
+ status);
+ } else if (ctx == DUAL_CTX) {
+ status = msm_rpm_clear(MSM_RPM_CTX_SET_SLEEP,
+ rpm_data, count);
+ MSM_BUS_DBG("msm_rpm_clear returned: %d\n",
+ status);
+ }
+ }
}
- MSM_FAB_DBG("msm_rpm_set returned: %d\n", status);
return status;
}
@@ -771,3 +855,47 @@
}
}
#endif
+
+/**
+* msm_bus_rpm_commit() - Commit the arbitration data to RPM
+* @fabric: Fabric for which the data should be committed
+**/
+int msm_bus_rpm_commit(struct msm_bus_fabric_registration
+ *fab_pdata, struct msm_rpm_iv_pair *rpm_data,
+ void **cdata)
+{
+
+ int ret;
+ bool valid;
+ struct commit_data *dual_cd, *act_cd;
+ dual_cd = (struct commit_data *)cdata[DUAL_CTX];
+ act_cd = (struct commit_data *)cdata[ACTIVE_CTX];
+
+ /*
+ * If the arb data for active set and sleep set is
+ * different, commit both sets.
+ * If the arb data for active set and sleep set is
+ * the same, invalidate the sleep set.
+ */
+ ret = msm_bus_rpm_compare_cdata(fab_pdata, act_cd, dual_cd);
+ if (!ret)
+ /* Invalidate sleep set.*/
+ valid = false;
+ else
+ valid = true;
+
+ ret = msm_bus_rpm_commit_arb(fab_pdata, DUAL_CTX, rpm_data,
+ dual_cd, valid);
+ if (ret)
+ MSM_BUS_ERR("Error comiting fabric:%d in %d ctx\n",
+ fab_pdata->id, DUAL_CTX);
+
+ valid = true;
+ ret = msm_bus_rpm_commit_arb(fab_pdata, ACTIVE_CTX, rpm_data, act_cd,
+ valid);
+ if (ret)
+ MSM_BUS_ERR("Error comiting fabric:%d in %d ctx\n",
+ fab_pdata->id, ACTIVE_CTX);
+
+ return ret;
+}
diff --git a/arch/arm/mach-msm/msm_xo.c b/arch/arm/mach-msm/msm_xo.c
index a82d4d5..1e9c05f 100644
--- a/arch/arm/mach-msm/msm_xo.c
+++ b/arch/arm/mach-msm/msm_xo.c
@@ -190,11 +190,11 @@
{
int ret;
unsigned long flags;
- /* TODO: Remove or fix this function for 8064 once xo is in */
- if (cpu_is_apq8064())
+
+ if (!xo_voter)
return 0;
- if (mode >= NUM_MSM_XO_MODES)
+ if (mode >= NUM_MSM_XO_MODES || IS_ERR(xo_voter))
return -EINVAL;
spin_lock_irqsave(&msm_xo_lock, flags);
@@ -221,7 +221,10 @@
unsigned long flags;
struct msm_xo_voter *xo_voter;
- /* TODO: Remove or fix this function for 8064 once xo is in */
+ /*
+ * TODO: Remove early return for 8064 once RPM XO voting support
+ * is available.
+ */
if (cpu_is_apq8064())
return NULL;
@@ -271,6 +274,9 @@
{
unsigned long flags;
+ if (!xo_voter || IS_ERR(xo_voter))
+ return;
+
spin_lock_irqsave(&msm_xo_lock, flags);
__msm_xo_mode_vote(xo_voter, MSM_XO_MODE_OFF);
xo_voter->xo->votes[MSM_XO_MODE_OFF]--;
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index c831d4b..911d546 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -279,7 +279,7 @@
ret = 0;
mode_sysfs_add_cpu_exit:
- if (!ret) {
+ if (ret) {
if (mode && mode->kobj)
kobject_del(mode->kobj);
kfree(mode);
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c b/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c
index 169e348..75af881 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_multi_aac.c
@@ -117,7 +117,7 @@
aac_cfg.sample_rate);
/* Configure Media format block */
- rc = q6asm_media_format_block_aac(audio->ac, &aac_cfg);
+ rc = q6asm_media_format_block_multi_aac(audio->ac, &aac_cfg);
if (rc < 0) {
pr_err("cmd media format block failed\n");
break;
@@ -249,7 +249,7 @@
/* open in T/NT mode */
if ((file->f_mode & FMODE_WRITE) && (file->f_mode & FMODE_READ)) {
rc = q6asm_open_read_write(audio->ac, FORMAT_LINEAR_PCM,
- FORMAT_MPEG4_AAC);
+ FORMAT_MPEG4_MULTI_AAC);
if (rc < 0) {
pr_err("NT mode Open failed rc=%d\n", rc);
rc = -ENODEV;
@@ -261,7 +261,7 @@
audio->buf_cfg.meta_info_enable = 0x01;
} else if ((file->f_mode & FMODE_WRITE) &&
!(file->f_mode & FMODE_READ)) {
- rc = q6asm_open_write(audio->ac, FORMAT_MPEG4_AAC);
+ rc = q6asm_open_write(audio->ac, FORMAT_MPEG4_MULTI_AAC);
if (rc < 0) {
pr_err("T mode Open failed rc=%d\n", rc);
rc = -ENODEV;
diff --git a/arch/arm/mach-msm/qdsp6v2/rtac.c b/arch/arm/mach-msm/qdsp6v2/rtac.c
index 948c66e..9823209 100644
--- a/arch/arm/mach-msm/qdsp6v2/rtac.c
+++ b/arch/arm/mach-msm/qdsp6v2/rtac.c
@@ -28,7 +28,8 @@
#ifndef CONFIG_RTAC
void rtac_add_adm_device(u32 port_id, u32 copp_id, u32 path_id, u32 popp_id) {}
-void rtac_remove_adm_device(u32 port_id, u32 popp_id) {}
+void rtac_remove_adm_device(u32 port_id) {}
+void rtac_remove_popp_from_adm_devices(u32 popp_id) {}
void rtac_set_adm_handle(void *handle) {}
bool rtac_make_adm_callback(uint32_t *payload, u32 payload_size)
{return false; }
@@ -222,44 +223,49 @@
}
}
-void rtac_remove_adm_device(u32 port_id, u32 popp_id)
+void rtac_remove_adm_device(u32 port_id)
{
- s32 i, j;
- pr_debug("%s: port_id = %d, popp_id = %d\n", __func__, port_id,
- popp_id);
+ s32 i;
+ pr_debug("%s: port_id = %d\n", __func__, port_id);
mutex_lock(&rtac_adm_mutex);
/* look for device */
for (i = 0; i < rtac_adm_data.num_of_dev; i++) {
if (rtac_adm_data.device[i].afe_port == port_id) {
- if (rtac_adm_data.device[i].num_of_popp == 1) {
- memset(&rtac_adm_data.device[i], 0,
- sizeof(rtac_adm_data.device[i]));
- rtac_adm_data.num_of_dev--;
- } else {
- for (j = 0; j <
- rtac_adm_data.device[i].num_of_popp; j++) {
- if (rtac_adm_data.device[i].popp[j] ==
- popp_id) {
- rtac_adm_data.device[i].popp[j]
- = 0;
- rtac_adm_data.device[i].num_of_popp--;
- shift_popp(i, j);
- goto done;
- }
- }
- }
+ memset(&rtac_adm_data.device[i], 0,
+ sizeof(rtac_adm_data.device[i]));
+ rtac_adm_data.num_of_dev--;
+
if (rtac_adm_data.num_of_dev >= 1) {
shift_adm_devices(i);
break;
}
}
}
-done:
+
mutex_unlock(&rtac_adm_mutex);
return;
}
+void rtac_remove_popp_from_adm_devices(u32 popp_id)
+{
+ s32 i, j;
+ pr_debug("%s: popp_id = %d\n", __func__, popp_id);
+
+ mutex_lock(&rtac_adm_mutex);
+
+ for (i = 0; i < rtac_adm_data.num_of_dev; i++) {
+ for (j = 0; j < rtac_adm_data.device[i].num_of_popp; j++) {
+ if (rtac_adm_data.device[i].popp[j] == popp_id) {
+ rtac_adm_data.device[i].popp[j] = 0;
+ rtac_adm_data.device[i].num_of_popp--;
+ shift_popp(i, j);
+ }
+ }
+ }
+
+ mutex_unlock(&rtac_adm_mutex);
+}
/* Voice Info */
static void set_rtac_voice_data(int idx, u32 cvs_handle, u32 cvp_handle,
diff --git a/arch/arm/mach-msm/rpm-regulator.c b/arch/arm/mach-msm/rpm-regulator.c
index 2494969..5c2bb8e 100644
--- a/arch/arm/mach-msm/rpm-regulator.c
+++ b/arch/arm/mach-msm/rpm-regulator.c
@@ -416,6 +416,9 @@
*
* This function may only be called for regulators which have the sleep flag
* specified in their private data.
+ *
+ * Consumers can vote to disable a regulator with this function by passing
+ * min_uV = 0 and max_uV = 0.
*/
int rpm_vreg_set_voltage(int vreg_id, enum rpm_vreg_voter voter, int min_uV,
int max_uV, int sleep_also)
@@ -452,38 +455,41 @@
return -EINVAL;
}
- /*
- * Check if request voltage is outside of allowed range. The regulator
- * core has already checked that constraint range is inside of the
- * physically allowed range.
- */
- lim_min_uV = vreg->pdata.init_data.constraints.min_uV;
- lim_max_uV = vreg->pdata.init_data.constraints.max_uV;
+ /* Allow min_uV == max_uV == 0 to represent a disable request. */
+ if (min_uV != 0 || max_uV != 0) {
+ /*
+ * Check if request voltage is outside of allowed range. The
+ * regulator core has already checked that constraint range
+ * is inside of the physically allowed range.
+ */
+ lim_min_uV = vreg->pdata.init_data.constraints.min_uV;
+ lim_max_uV = vreg->pdata.init_data.constraints.max_uV;
- if (uV < lim_min_uV && max_uV >= lim_min_uV)
- uV = lim_min_uV;
+ if (uV < lim_min_uV && max_uV >= lim_min_uV)
+ uV = lim_min_uV;
- if (uV < lim_min_uV || uV > lim_max_uV) {
- vreg_err(vreg,
- "request v=[%d, %d] is outside allowed v=[%d, %d]\n",
- min_uV, max_uV, lim_min_uV, lim_max_uV);
- return -EINVAL;
- }
-
- /* Find the range which uV is inside of. */
- for (i = vreg->set_points->count - 1; i > 0; i--) {
- if (uV > vreg->set_points->range[i - 1].max_uV) {
- range = &vreg->set_points->range[i];
- break;
+ if (uV < lim_min_uV || uV > lim_max_uV) {
+ vreg_err(vreg, "request v=[%d, %d] is outside allowed "
+ "v=[%d, %d]\n", min_uV, max_uV, lim_min_uV,
+ lim_max_uV);
+ return -EINVAL;
}
- }
- /*
- * Force uV to be an allowed set point and apply a ceiling function
- * to non-set point values.
- */
- uV = (uV - range->min_uV + range->step_uV - 1) / range->step_uV;
- uV = uV * range->step_uV + range->min_uV;
+ /* Find the range which uV is inside of. */
+ for (i = vreg->set_points->count - 1; i > 0; i--) {
+ if (uV > vreg->set_points->range[i - 1].max_uV) {
+ range = &vreg->set_points->range[i];
+ break;
+ }
+ }
+
+ /*
+ * Force uV to be an allowed set point and apply a ceiling
+ * function to non-set point values.
+ */
+ uV = (uV - range->min_uV + range->step_uV - 1) / range->step_uV;
+ uV = uV * range->step_uV + range->min_uV;
+ }
if (vreg->part->uV.mask) {
val[vreg->part->uV.word] = uV << vreg->part->uV.shift;
diff --git a/arch/arm/mach-msm/rpm_resources.c b/arch/arm/mach-msm/rpm_resources.c
index e29afa6..f2b3e88 100644
--- a/arch/arm/mach-msm/rpm_resources.c
+++ b/arch/arm/mach-msm/rpm_resources.c
@@ -64,11 +64,9 @@
static ssize_t msm_rpmrs_resource_attr_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t count);
-#ifdef CONFIG_MSM_L2_SPM
static void *msm_rpmrs_l2_counter_addr;
static int msm_rpmrs_l2_reset_count;
#define L2_PC_COUNTER_ADDR 0x660
-#endif
#define MSM_RPMRS_MAX_RS_REGISTER_COUNT 2
@@ -267,7 +265,6 @@
}
}
-#ifdef CONFIG_MSM_L2_SPM
static bool msm_spm_l2_cache_beyond_limits(struct msm_rpmrs_limits *limits)
{
struct msm_rpmrs_resource *rs = &msm_rpmrs_l2_cache;
@@ -278,7 +275,6 @@
return l2_cache > limits->l2_cache;
}
-#endif
static void msm_rpmrs_restore_l2_cache(void)
{
@@ -918,9 +914,9 @@
} else if ((sleep_us >> 10) > level->time_overhead_us) {
power = level->steady_state_power;
} else {
- power = (sleep_us - level->time_overhead_us);
- power *= level->steady_state_power;
- power /= sleep_us;
+ power = level->steady_state_power;
+ power -= (level->time_overhead_us *
+ level->steady_state_power)/sleep_us;
power += level->energy_overhead / sleep_us;
}
@@ -967,7 +963,6 @@
msm_mpm_exit_sleep(from_idle);
}
-#ifdef CONFIG_MSM_L2_SPM
static int rpmrs_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
@@ -993,7 +988,6 @@
static struct notifier_block __refdata rpmrs_cpu_notifier = {
.notifier_call = rpmrs_cpu_callback,
};
-#endif
int __init msm_rpmrs_levels_init(struct msm_rpmrs_level *levels, int size)
{
@@ -1061,20 +1055,25 @@
}
early_initcall(msm_rpmrs_early_init);
-#ifdef CONFIG_MSM_L2_SPM
static int __init msm_rpmrs_l2_counter_init(void)
{
- msm_rpmrs_l2_counter_addr = MSM_IMEM_BASE + L2_PC_COUNTER_ADDR;
- writel_relaxed(msm_rpmrs_l2_reset_count, msm_rpmrs_l2_counter_addr);
- mb();
+ if (cpu_is_msm8960()) {
+ msm_rpmrs_l2_counter_addr = MSM_IMEM_BASE + L2_PC_COUNTER_ADDR;
+ writel_relaxed(msm_rpmrs_l2_reset_count,
+ msm_rpmrs_l2_counter_addr);
+ mb();
- msm_rpmrs_l2_cache.beyond_limits = msm_spm_l2_cache_beyond_limits;
- msm_rpmrs_l2_cache.aggregate = NULL;
- msm_rpmrs_l2_cache.restore = NULL;
+ msm_rpmrs_l2_cache.beyond_limits =
+ msm_spm_l2_cache_beyond_limits;
+ msm_rpmrs_l2_cache.aggregate = NULL;
+ msm_rpmrs_l2_cache.restore = NULL;
+ register_hotcpu_notifier(&rpmrs_cpu_notifier);
- register_hotcpu_notifier(&rpmrs_cpu_notifier);
-
+ } else if (cpu_is_msm9615()) {
+ msm_rpmrs_l2_cache.beyond_limits = NULL;
+ msm_rpmrs_l2_cache.aggregate = NULL;
+ msm_rpmrs_l2_cache.restore = NULL;
+ }
return 0;
}
early_initcall(msm_rpmrs_l2_counter_init);
-#endif
diff --git a/arch/arm/mach-msm/sdio_al.c b/arch/arm/mach-msm/sdio_al.c
index ace437b..8fff2461 100644
--- a/arch/arm/mach-msm/sdio_al.c
+++ b/arch/arm/mach-msm/sdio_al.c
@@ -15,7 +15,7 @@
*
* To be used with Qualcomm's SDIO-Client connected to this host.
*/
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/module.h>
#include <linux/scatterlist.h>
diff --git a/arch/arm/mach-msm/sdio_al_dloader.c b/arch/arm/mach-msm/sdio_al_dloader.c
index a172d2b..77a06a3 100644
--- a/arch/arm/mach-msm/sdio_al_dloader.c
+++ b/arch/arm/mach-msm/sdio_al_dloader.c
@@ -25,7 +25,7 @@
#include <linux/dma-mapping.h>
#include <mach/dma.h>
#include <linux/mmc/sdio_func.h>
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/kthread.h>
diff --git a/arch/arm/mach-msm/sdio_al_test.c b/arch/arm/mach-msm/sdio_al_test.c
index 9653b9a..8b9abcf 100644
--- a/arch/arm/mach-msm/sdio_al_test.c
+++ b/arch/arm/mach-msm/sdio_al_test.c
@@ -30,7 +30,7 @@
#include <linux/wakelock.h>
#include <linux/uaccess.h>
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/debugfs.h>
#include <linux/kthread.h>
@@ -60,6 +60,7 @@
#define A2_MIN_PACKET_SIZE 5
#define RMNT_PACKET_SIZE (4*1024)
#define DUN_PACKET_SIZE (2*1024)
+#define CSVT_PACKET_SIZE 1700
#define TEST_DBG(x...) if (test_ctx->runtime_debug) pr_info(x)
@@ -70,6 +71,9 @@
#define LPM_TEST_CONFIG_SIGNATURE 0xDEADBABE
#define LPM_MSG_NAME_SIZE 20
#define MAX_STR_SIZE 10
+#define MAX_AVG_RTT_TIME_USEC 2500
+#define SDIO_RMNT_RTT_PACKET_SIZE 32
+#define SDIO_CSVT_RTT_PACKET_SIZE 1900
#define A2_HEADER_OVERHEAD 8
@@ -143,6 +147,7 @@
SDIO_DUN,
SDIO_SMEM,
SDIO_CIQ,
+ SDIO_CSVT,
SDIO_MAX_CHANNELS
};
@@ -240,6 +245,7 @@
struct dentry *dun_a2_validation_test;
struct dentry *rmnet_a2_perf_test;
struct dentry *dun_a2_perf_test;
+ struct dentry *csvt_a2_perf_test;
struct dentry *rmnet_dun_a2_perf_test;
struct dentry *rpc_sender_rmnet_a2_perf_test;
struct dentry *all_channels_test;
@@ -247,6 +253,7 @@
struct dentry *host_sender_no_lp_diag_rpc_ciq_test;
struct dentry *rmnet_small_packets_test;
struct dentry *rmnet_rtt_test;
+ struct dentry *csvt_rtt_test;
struct dentry *modem_reset_rpc_test;
struct dentry *modem_reset_rmnet_test;
struct dentry *modem_reset_channels_4bit_dev_test;
@@ -337,6 +344,11 @@
{
int i = 0;
+ if (!test_ctx) {
+ pr_err(TEST_MODULE_NAME ":%s - test_ctx is NULL.\n", __func__);
+ return;
+ }
+
for (i = 0 ; i < MAX_NUM_OF_SDIO_DEVICES ; ++i)
test_ctx->test_dev_arr[i].sdio_al_device = NULL;
@@ -937,6 +949,74 @@
.read = dun_a2_perf_test_read,
};
+/* CSVT A2 PERFORMANCE TEST */
+static ssize_t csvt_a2_perf_test_write(struct file *file,
+ const char __user *buf,
+ size_t count,
+ loff_t *ppos)
+{
+ int ret = 0;
+ int i = 0;
+ int number = -1;
+
+ pr_info(TEST_MODULE_NAME "-- CSVT A2 PERFORMANCE TEST --\n");
+
+ number = sdio_al_test_extract_number(buf, count);
+
+ if (number < 0) {
+ pr_err(TEST_MODULE_NAME " : %s - sdio_al_test_extract_number() "
+ "failed. number = %d\n", __func__, number);
+ return count;
+ }
+
+ for (i = 0 ; i < number ; ++i) {
+ pr_info(TEST_MODULE_NAME " - Cycle # %d / %d\n", i+1, number);
+ pr_info(TEST_MODULE_NAME " ===================");
+
+ sdio_al_test_initial_dev_and_chan(test_ctx);
+
+ set_params_a2_perf(test_ctx->test_ch_arr[SDIO_CSVT]);
+
+ ret = test_start();
+
+ if (ret)
+ break;
+ }
+
+ return count;
+}
+
+static ssize_t csvt_a2_perf_test_read(struct file *file,
+ char __user *buffer,
+ size_t count,
+ loff_t *offset)
+{
+ memset((void *)buffer, 0, count);
+
+ snprintf(buffer, count,
+ "\nCSVT_A2_PERFORMANCE_TEST\n"
+ "========================\n"
+ "Description:\n"
+ "Loopback test on the CSVT Channel, in order to check "
+ "throughput performance.\n"
+ "Packet size that are sent on the CSVT channel in this "
+ "test is %d.bytes\n\n"
+ "END OF DESCRIPTION\n", CSVT_PACKET_SIZE);
+
+ if (message_repeat == 1) {
+ message_repeat = 0;
+ return strnlen(buffer, count);
+ } else {
+ return 0;
+ }
+}
+
+const struct file_operations csvt_a2_perf_test_ops = {
+ .open = sdio_al_test_open,
+ .write = csvt_a2_perf_test_write,
+ .read = csvt_a2_perf_test_read,
+};
+
/* RMNET DUN A2 PERFORMANCE TEST */
static ssize_t rmnet_dun_a2_perf_test_write(struct file *file,
const char __user *buf,
@@ -1101,6 +1181,7 @@
set_params_a2_perf(test_ctx->test_ch_arr[SDIO_DUN]);
set_params_smem_test(test_ctx->test_ch_arr[SDIO_SMEM]);
set_params_loopback_9k(test_ctx->test_ch_arr[SDIO_CIQ]);
+ set_params_a2_perf(test_ctx->test_ch_arr[SDIO_CSVT]);
ret = test_start();
@@ -1399,6 +1480,72 @@
.read = rmnet_rtt_test_read,
};
+/* CSVT RTT TEST */
+static ssize_t csvt_rtt_test_write(struct file *file,
+ const char __user *buf,
+ size_t count,
+ loff_t *ppos)
+{
+ int ret = 0;
+ int i = 0;
+ int number = -1;
+
+ pr_info(TEST_MODULE_NAME "-- CSVT RTT TEST --");
+
+ number = sdio_al_test_extract_number(buf, count);
+
+ if (number < 0) {
+ pr_err(TEST_MODULE_NAME " : %s - sdio_al_test_extract_number() "
+ "failed. number = %d\n", __func__, number);
+ return count;
+ }
+
+ for (i = 0 ; i < number ; ++i) {
+ pr_info(TEST_MODULE_NAME " - Cycle # %d / %d\n", i+1, number);
+ pr_info(TEST_MODULE_NAME " ===================");
+
+ sdio_al_test_initial_dev_and_chan(test_ctx);
+
+ set_params_rtt(test_ctx->test_ch_arr[SDIO_CSVT]);
+
+ ret = test_start();
+
+ if (ret)
+ break;
+ }
+
+ return count;
+}
+
+static ssize_t csvt_rtt_test_read(struct file *file,
+ char __user *buffer,
+ size_t count,
+ loff_t *offset)
+{
+ memset((void *)buffer, 0, count);
+
+ snprintf(buffer, count,
+ "\nCSVT_RTT_TEST\n"
+ "==============\n"
+ "Description:\n"
+ "In this test the HOST send a message of %d bytes "
+ "to the CLIENT\n\n"
+ "END OF DESCRIPTION\n", SDIO_CSVT_RTT_PACKET_SIZE);
+
+ if (message_repeat == 1) {
+ message_repeat = 0;
+ return strnlen(buffer, count);
+ } else {
+ return 0;
+ }
+}
+
+const struct file_operations csvt_rtt_test_ops = {
+ .open = sdio_al_test_open,
+ .write = csvt_rtt_test_write,
+ .read = csvt_rtt_test_read,
+};
+
/* MODEM RESET RPC TEST */
static ssize_t modem_reset_rpc_test_write(struct file *file,
const char __user *buf,
@@ -1768,6 +1915,7 @@
set_params_loopback_9k_close(ch_arr[SDIO_QMI]);
set_params_loopback_9k_close(ch_arr[SDIO_RMNT]);
set_params_loopback_9k_close(ch_arr[SDIO_DUN]);
+ set_params_loopback_9k_close(ch_arr[SDIO_CSVT]);
ret = test_start();
@@ -1803,7 +1951,8 @@
"following sequence: Send a random burst of packets on "
"Diag, CIQ and Rmnet channels, read 0 or a random number "
"of packets, close and re-open the channel. At the end of the "
- "test, the channel is verified by running a loopback test\n");
+ "test, the channel is verified by running a loopback test\n\n"
+ "END OF DESCRIPTION\n");
if (message_repeat == 1) {
message_repeat = 0;
@@ -1873,7 +2022,8 @@
"In this test the host sends 5k packets to the modem in the "
"following sequence: Send a random burst of packets on "
"DUN and Rmnet channels, read 0 or a random number "
- "of packets, close and re-open the channel.\n");
+ "of packets, close and re-open the channel.\n\n"
+ "END OF DESCRIPTION\n");
if (message_repeat == 1) {
message_repeat = 0;
@@ -2345,6 +2495,13 @@
NULL,
&dun_a2_perf_test_ops);
+ test_ctx->debug.csvt_a2_perf_test =
+ debugfs_create_file("71_csvt_a2_perf_test",
+ S_IRUGO | S_IWUGO,
+ test_ctx->debug.debug_root,
+ NULL,
+ &csvt_a2_perf_test_ops);
+
test_ctx->debug.rmnet_dun_a2_perf_test =
debugfs_create_file("70_rmnet_dun_a2_perf_test",
S_IRUGO | S_IWUGO,
@@ -2408,6 +2565,13 @@
NULL,
&rmnet_rtt_test_ops);
+ test_ctx->debug.csvt_rtt_test =
+ debugfs_create_file("191_csvt_rtt_test",
+ S_IRUGO | S_IWUGO,
+ test_ctx->debug.debug_root,
+ NULL,
+ &csvt_rtt_test_ops);
+
test_ctx->debug.modem_reset_rpc_test =
debugfs_create_file("220_modem_reset_rpc_test",
S_IRUGO | S_IWUGO,
@@ -2535,6 +2699,9 @@
else if (!strncmp(name, "SDIO_CIQ_TEST",
strnlen("SDIO_CIQ_TEST", TEST_CH_NAME_SIZE)))
return SDIO_CIQ;
+ else if (!strncmp(name, "SDIO_CSVT_TEST",
+ strnlen("SDIO_CSVT_TEST", TEST_CH_NAME_SIZE)))
+ return SDIO_CSVT;
else
return SDIO_MAX_CHANNELS;
@@ -4095,10 +4262,17 @@
total_bytes , (int) time_msec, test_ch->name);
if (!test_ch->random_packet_size) {
- throughput = (total_bytes / time_msec) * 8 / 1000;
- pr_err(TEST_MODULE_NAME ":Performance = %d Mbit/sec for "
- "chan %s\n",
- throughput, test_ch->name);
+ if (time_msec) {
+ throughput = (total_bytes / time_msec) * 8 / 1000;
+ pr_err(TEST_MODULE_NAME ": %s - Performance = "
+ "%d Mbit/sec for chan %s\n",
+ __func__, throughput, test_ch->name);
+ } else {
+ pr_err(TEST_MODULE_NAME ": %s - time_msec = 0 Couldn't "
+ "calculate performence for chan %s\n",
+ __func__, test_ch->name);
+ }
+
}
#ifdef CONFIG_DEBUG_FS
@@ -4199,10 +4373,10 @@
u32 write_avail = 0;
int tx_packet_count = 0;
int rx_packet_count = 0;
- u16 *buf16 = (u16 *) test_ch->buf;
+ u16 *buf16 = NULL;
int i;
- int max_packets = test_ch->config_msg.num_packets;
- u32 packet_size = test_ch->packet_length;
+ int max_packets = 0;
+ u32 packet_size = 0;
s64 start_time, end_time;
int delta_usec = 0;
int time_average = 0;
@@ -4210,6 +4384,24 @@
int max_delta_usec = 0;
int total_time = 0;
int expected_read_size = 0;
+ int delay_ms = 0;
+ int slow_rtt_counter = 0;
+ int read_avail_so_far = 0;
+
+ if (test_ch) {
+ /*
+ * Cleanup the pending RX data (such as loopback of the
+ * config msg)
+ */
+ rx_cleanup(test_ch, &rx_packet_count);
+ rx_packet_count = 0;
+ } else {
+ return;
+ }
+
+ max_packets = test_ch->config_msg.num_packets;
+ packet_size = test_ch->packet_length;
+ buf16 = (u16 *) test_ch->buf;
for (i = 0; i < packet_size / 2; i++)
buf16[i] = (u16) (i & 0xFFFF);
@@ -4217,9 +4409,18 @@
pr_info(TEST_MODULE_NAME ": A2 RTT TEST START for chan %s\n",
test_ch->name);
- /* Cleanup the pending RX data (such as loopback of te config msg) */
- rx_cleanup(test_ch, &rx_packet_count);
- rx_packet_count = 0;
+ switch (test_ch->ch_id) {
+ case SDIO_RMNT:
+ delay_ms = 100;
+ break;
+ case SDIO_CSVT:
+ delay_ms = 0;
+ break;
+ default:
+ pr_err(TEST_MODULE_NAME ": %s - ch_id invalid.\n",
+ __func__);
+ return;
+ }
while (tx_packet_count < max_packets) {
if (test_ctx->exit_flag) {
@@ -4228,11 +4429,10 @@
}
start_time = 0;
end_time = 0;
+ read_avail_so_far = 0;
- /* Allow sdio_al to go to sleep to change the read_threshold
- * to 1
- */
- msleep(100);
+ if (delay_ms)
+ msleep(delay_ms);
/* wait for data ready event */
write_avail = sdio_write_avail(test_ch->ch);
@@ -4272,38 +4472,53 @@
expected_read_size = packet_size + A2_HEADER_OVERHEAD;
- read_avail = sdio_read_avail(test_ch->ch);
- TEST_DBG(TEST_MODULE_NAME ":channel %s, read_avail=%d\n",
- test_ch->name, read_avail);
- while (read_avail < expected_read_size) {
- wait_event(test_ch->wait_q,
- atomic_read(&test_ch->rx_notify_count));
- atomic_dec(&test_ch->rx_notify_count);
- read_avail = sdio_read_avail(test_ch->ch);
- }
+ while (read_avail_so_far < expected_read_size) {
- if (read_avail >= expected_read_size) {
- pr_debug(TEST_MODULE_NAME ":read_avail=%d for ch %s.\n",
- read_avail, test_ch->name);
+ read_avail = sdio_read_avail(test_ch->ch);
+
+ if (!read_avail) {
+ wait_event(test_ch->wait_q,
+ atomic_read(&test_ch->
+ rx_notify_count));
+
+ atomic_dec(&test_ch->rx_notify_count);
+ continue;
+ }
+
+ read_avail_so_far += read_avail;
+
+ if (read_avail_so_far > expected_read_size) {
+ pr_err(TEST_MODULE_NAME ": %s - Invalid "
+ "read_avail(%d) read_avail_so_far(%d) "
+ "can't be larger than "
+ "expected_read_size(%d).",
+ __func__,
+ read_avail,
+ read_avail_so_far,
+ expected_read_size);
+ goto exit_err;
+ }
+
+ /*
+ * must read entire pending bytes, so later, we will
+ * get a notification when more data arrives
+ */
ret = sdio_read(test_ch->ch, test_ch->buf,
- expected_read_size);
+ read_avail);
+
if (ret) {
pr_info(TEST_MODULE_NAME ": sdio_read size %d "
" err=%d for chan %s\n",
- expected_read_size, -ret,
+ read_avail, -ret,
test_ch->name);
goto exit_err;
}
- end_time = ktime_to_us(ktime_get());
- rx_packet_count++;
- test_ch->rx_bytes += expected_read_size;
- } else {
- pr_info(TEST_MODULE_NAME ": Invalid read_avail "
- "%d for chan %s\n",
- read_avail, test_ch->name);
- goto exit_err;
}
+ end_time = ktime_to_us(ktime_get());
+ rx_packet_count++;
+ test_ch->rx_bytes += expected_read_size;
+
delta_usec = (int)(end_time - start_time);
total_time += delta_usec;
if (delta_usec < min_delta_usec)
@@ -4311,24 +4526,47 @@
if (delta_usec > max_delta_usec)
max_delta_usec = delta_usec;
+ /* checking the RTT per channel criteria */
+ if (delta_usec > MAX_AVG_RTT_TIME_USEC) {
+ pr_err(TEST_MODULE_NAME ": %s - "
+ "msg # %d - rtt time (%d usec) is "
+ "longer than %d usec\n",
+ __func__,
+ tx_packet_count,
+ delta_usec,
+ MAX_AVG_RTT_TIME_USEC);
+ slow_rtt_counter++;
+ }
+
TEST_DBG(TEST_MODULE_NAME
":RTT time=%d for packet #%d for chan %s\n",
delta_usec, tx_packet_count, test_ch->name);
-
} /* while (tx_packet_count < max_packets ) */
+ pr_info(TEST_MODULE_NAME ": %s - tx_packet_count = %d\n",
+ __func__, tx_packet_count);
- pr_info(TEST_MODULE_NAME ":total rx bytes = 0x%x , rx_packet#=%d for"
- " chan %s.\n",
- test_ch->rx_bytes, rx_packet_count, test_ch->name);
- pr_info(TEST_MODULE_NAME ":total tx bytes = 0x%x , tx_packet#=%d"
- " for chan %s.\n",
- test_ch->tx_bytes, tx_packet_count, test_ch->name);
+ pr_info(TEST_MODULE_NAME ": %s - total rx bytes = 0x%x, "
+ "rx_packet# = %d for chan %s.\n",
+ __func__, test_ch->rx_bytes, rx_packet_count, test_ch->name);
- time_average = total_time / tx_packet_count;
+ pr_info(TEST_MODULE_NAME ": %s - total tx bytes = 0x%x, "
+ "tx_packet# = %d for chan %s.\n",
+ __func__, test_ch->tx_bytes, tx_packet_count, test_ch->name);
- pr_info(TEST_MODULE_NAME ":Average RTT time = %d for chan %s\n",
+ pr_info(TEST_MODULE_NAME ": %s - slow_rtt_counter = %d for "
+ "chan %s.\n",
+ __func__, slow_rtt_counter, test_ch->name);
+
+ if (tx_packet_count) {
+ time_average = total_time / tx_packet_count;
+ pr_info(TEST_MODULE_NAME ":Average RTT time = %d for chan %s\n",
time_average, test_ch->name);
+ } else {
+ pr_err(TEST_MODULE_NAME ": %s - tx_packet_count=0. couldn't "
+ "calculate average rtt time", __func__);
+ }
+
pr_info(TEST_MODULE_NAME ":MIN RTT time = %d for chan %s\n",
min_delta_usec, test_ch->name);
pr_info(TEST_MODULE_NAME ":MAX RTT time = %d for chan %s\n",
@@ -4337,6 +4575,17 @@
pr_info(TEST_MODULE_NAME ": A2 RTT TEST END for chan %s.\n",
test_ch->name);
+ if (ret)
+ goto exit_err;
+
+ if (time_average == 0 || time_average > MAX_AVG_RTT_TIME_USEC) {
+ pr_err(TEST_MODULE_NAME ": %s - average_time = %d. Invalid "
+ "value",
+ __func__, time_average);
+ goto exit_err;
+
+ }
+
pr_info(TEST_MODULE_NAME ": TEST PASS for chan %s\n", test_ch->name);
test_ch->test_completed = 1;
test_ch->test_result = TEST_PASSED;
@@ -4351,7 +4600,6 @@
return;
}
-
/**
* Process Rx Data - Helper for A2 Validation Test
* @test_ch(in/out) : Test channel that contains Rx data buffer to process.
@@ -5599,11 +5847,22 @@
tch->test_type = SDIO_TEST_PERF;
tch->config_msg.signature = TEST_CONFIG_SIGNATURE;
tch->config_msg.test_case = SDIO_TEST_LOOPBACK_CLIENT;
- tch->packet_length = MAX_XFER_SIZE;
- if (tch->ch_id == SDIO_DIAG)
+
+ switch (tch->ch_id) {
+ case SDIO_DIAG:
tch->packet_length = 512;
- else if (tch->ch_id == SDIO_DUN)
- tch->packet_length = DUN_PACKET_SIZE;
+ break;
+ case SDIO_DUN:
+ tch->packet_length = DUN_PACKET_SIZE;
+ break;
+ case SDIO_CSVT:
+ tch->packet_length = CSVT_PACKET_SIZE;
+ break;
+ default:
+ tch->packet_length = MAX_XFER_SIZE;
+ break;
+ }
+
pr_info(TEST_MODULE_NAME ": %s: packet_length=%d", __func__,
tch->packet_length);
@@ -5626,7 +5885,21 @@
tch->test_type = SDIO_TEST_RTT;
tch->config_msg.signature = TEST_CONFIG_SIGNATURE;
tch->config_msg.test_case = SDIO_TEST_LOOPBACK_CLIENT;
- tch->packet_length = 32;
+
+ switch (tch->ch_id) {
+ case SDIO_RMNT:
+ tch->packet_length = SDIO_RMNT_RTT_PACKET_SIZE;
+ break;
+ case SDIO_CSVT:
+ tch->packet_length = SDIO_CSVT_RTT_PACKET_SIZE;
+ break;
+ default:
+ pr_err(TEST_MODULE_NAME ": %s - ch_id invalid.\n", __func__);
+ return -EINVAL;
+ }
+
+ pr_info(TEST_MODULE_NAME ": %s: packet_length=%d", __func__,
+ tch->packet_length);
tch->config_msg.num_packets = 200;
tch->config_msg.num_iterations = 1;
@@ -5816,6 +6089,12 @@
struct test_channel *tch = NULL;
tch = test_ctx->test_ch_arr[channel_num];
+ if (!tch) {
+ pr_info(TEST_MODULE_NAME ":%s ch#%d is NULL\n",
+ __func__, channel_num);
+ return 0;
+ }
+
ret = open_sdio_ch(tch);
if (ret) {
pr_err(TEST_MODULE_NAME":%s open channel %s"
@@ -6108,6 +6387,15 @@
},
};
+static struct platform_driver sdio_csvt_drv = {
+ .probe = sdio_test_channel_probe,
+ .remove = sdio_test_channel_remove,
+ .driver = {
+ .name = "SDIO_CSVT_TEST",
+ .owner = THIS_MODULE,
+ },
+};
+
static struct class *test_class;
const struct file_operations test_fops = {
@@ -6177,6 +6465,7 @@
platform_driver_register(&sdio_rmnt_drv);
platform_driver_register(&sdio_dun_drv);
platform_driver_register(&sdio_ciq_drv);
+ platform_driver_register(&sdio_csvt_drv);
return ret;
}
@@ -6205,6 +6494,7 @@
platform_driver_unregister(&sdio_rmnt_drv);
platform_driver_unregister(&sdio_dun_drv);
platform_driver_unregister(&sdio_ciq_drv);
+ platform_driver_unregister(&sdio_csvt_drv);
for (i = 0; i < SDIO_MAX_CHANNELS; i++) {
struct test_channel *tch = test_ctx->test_ch_arr[i];
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 94dd8b8..532a2f7 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -1269,6 +1269,7 @@
return r;
}
+#if (defined(CONFIG_MSM_SMD_PKG4) || defined(CONFIG_MSM_SMD_PKG3))
static int smd_alloc_v2(struct smd_channel *ch)
{
struct smd_shared_v2 *shared2;
@@ -1278,18 +1279,19 @@
shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
if (!shared2) {
SMD_INFO("smem_alloc failed ch=%d\n", ch->n);
- return -1;
+ return -EINVAL;
}
buffer = smem_get_entry(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
if (!buffer) {
- SMD_INFO("smem_get_entry failed \n");
- return -1;
+ SMD_INFO("smem_get_entry failed\n");
+ return -EINVAL;
}
/* buffer must be a power-of-two size */
- if (buffer_sz & (buffer_sz - 1))
- return -1;
-
+ if (buffer_sz & (buffer_sz - 1)) {
+ SMD_INFO("Buffer size: %u not power of two\n", buffer_sz);
+ return -EINVAL;
+ }
buffer_sz /= 2;
ch->send = &shared2->ch0;
ch->recv = &shared2->ch1;
@@ -1301,11 +1303,22 @@
static int smd_alloc_v1(struct smd_channel *ch)
{
+ return -EINVAL;
+}
+
+#else /* define v1 for older targets */
+static int smd_alloc_v2(struct smd_channel *ch)
+{
+ return -EINVAL;
+}
+
+static int smd_alloc_v1(struct smd_channel *ch)
+{
struct smd_shared_v1 *shared1;
shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1));
if (!shared1) {
pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n);
- return -1;
+ return -EINVAL;
}
ch->send = &shared1->ch0;
ch->recv = &shared1->ch1;
@@ -1315,6 +1328,8 @@
return 0;
}
+#endif
+
static int smd_alloc_channel(struct smd_alloc_elm *alloc_elm)
{
struct smd_channel *ch;
@@ -2533,6 +2548,8 @@
smd_initialized = 1;
smd_alloc_loopback_channel();
+ smsm_irq_handler(0, 0);
+ tasklet_schedule(&smd_fake_irq_tasklet);
return 0;
}
diff --git a/arch/arm/mach-msm/smd_rpcrouter.c b/arch/arm/mach-msm/smd_rpcrouter.c
index 93fa244..983d0c1 100644
--- a/arch/arm/mach-msm/smd_rpcrouter.c
+++ b/arch/arm/mach-msm/smd_rpcrouter.c
@@ -2126,17 +2126,27 @@
int msm_rpcrouter_close(void)
{
- struct rpcrouter_xprt_info *xprt_info, *tmp_xprt_info;
+ struct rpcrouter_xprt_info *xprt_info;
union rr_control_msg ctl;
ctl.cmd = RPCROUTER_CTRL_CMD_BYE;
mutex_lock(&xprt_info_list_lock);
- list_for_each_entry_safe(xprt_info, tmp_xprt_info,
- &xprt_info_list, list) {
+ while (!list_empty(&xprt_info_list)) {
+ xprt_info = list_first_entry(&xprt_info_list,
+ struct rpcrouter_xprt_info, list);
+ xprt_info->abort_data_read = 1;
+ wake_up(&xprt_info->read_wait);
rpcrouter_send_control_msg(xprt_info, &ctl);
xprt_info->xprt->close();
list_del(&xprt_info->list);
+ mutex_unlock(&xprt_info_list_lock);
+
+ flush_workqueue(xprt_info->workqueue);
+ destroy_workqueue(xprt_info->workqueue);
+ wake_lock_destroy(&xprt_info->wakelock);
kfree(xprt_info);
+
+ mutex_lock(&xprt_info_list_lock);
}
mutex_unlock(&xprt_info_list_lock);
return 0;
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 33cfccc..9df1a68 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -210,9 +210,12 @@
[104] = MSM_CPU_9615,
[105] = MSM_CPU_9615,
- /* 8064 IDs*/
+ /* 8064 IDs */
[109] = MSM_CPU_8064,
+ /* 8930 IDs */
+ [116] = MSM_CPU_8930,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
considered as unknown CPU. */
@@ -700,9 +703,12 @@
const int read_msm_cpu_type(void)
{
- if (machine_is_msm8960_sim())
+ if (machine_is_msm8960_sim() || machine_is_msm8960_rumi3())
return MSM_CPU_8960;
+ if (socinfo_get_msm_cpu() != MSM_CPU_UNKNOWN)
+ return socinfo_get_msm_cpu();
+
switch (read_cpuid_id()) {
case 0x510F02D0:
case 0x510F02D2:
@@ -712,13 +718,12 @@
case 0x510F04D0:
case 0x510F04D1:
case 0x510F04D2:
+ case 0x511F04D0:
+ case 0x512F04D0:
return MSM_CPU_8960;
- case 0x511F04D0:
- if (get_core_count() == 2)
- return MSM_CPU_8960;
- else
- return MSM_CPU_8X30;
+ case 0x51404D11: /* We can't get here unless we are in bringup */
+ return MSM_CPU_8930;
case 0x510F06F0:
return MSM_CPU_8064;
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 8e4d98c..a0602f0 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -42,29 +42,13 @@
static int msm_timer_debug_mask;
module_param_named(debug_mask, msm_timer_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
-#if defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
- defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_FSM9XXX) || \
- defined(CONFIG_ARCH_APQ8064) || defined(CONFIG_ARCH_MSM9615)
-#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
-#else
-#define MSM_GPT_BASE MSM_TMR_BASE
-#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
-#endif
-
#ifdef CONFIG_MSM7X00A_USE_GP_TIMER
#define DG_TIMER_RATING 100
- #define MSM_GLOBAL_TIMER MSM_CLOCK_GPT
#else
#define DG_TIMER_RATING 300
- #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
#endif
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_ARCH_MSM7X27A)
#define MSM_DGT_SHIFT (5)
-#else
-#define MSM_DGT_SHIFT (0)
-#endif
#define TIMER_MATCH_VAL 0x0000
#define TIMER_COUNT_VAL 0x0004
@@ -88,43 +72,14 @@
* access to come from the CPU0 region.
*/
static int global_timer_offset;
-
-#if defined(CONFIG_MSM_DIRECT_SCLK_ACCESS)
-#define MPM_SCLK_COUNT_VAL 0x0024
-#endif
+static int msm_global_timer;
#define NR_TIMERS ARRAY_SIZE(msm_clocks)
-#if defined(CONFIG_ARCH_QSD8X50) || defined(CONFIG_ARCH_FSM9XXX)
-#define DGT_HZ 4800000 /* Uses TCXO/4 (19.2 MHz / 4) */
-#elif defined(CONFIG_ARCH_MSM7X30)
-#define DGT_HZ 6144000 /* Uses LPXO/4 (24.576 MHz / 4) */
-#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) || \
- defined(CONFIG_ARCH_APQ8064) || defined(CONFIG_ARCH_MSM9615)
-/* Uses PXO/4 (24.576 MHz / 4) on V1, (27 MHz / 4) on V2 */
-#define DGT_HZ 6750000
-#else
-#define DGT_HZ 19200000 /* Uses TCXO (19.2 MHz) */
-#endif
+unsigned int gpt_hz = 32768;
+unsigned int sclk_hz = 32768;
-#define GPT_HZ 32768
-#define SCLK_HZ 32768
-
-#if defined(CONFIG_MSM_N_WAY_SMSM)
-/* Time Master State Bits */
-#define MASTER_BITS_PER_CPU 1
-#define MASTER_TIME_PENDING \
- (0x01UL << (MASTER_BITS_PER_CPU * SMSM_APPS_STATE))
-
-/* Time Slave State Bits */
-#define SLAVE_TIME_REQUEST 0x0400
-#define SLAVE_TIME_POLL 0x0800
-#define SLAVE_TIME_INIT 0x1000
-#endif
-
-#ifdef CONFIG_SMP
static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt);
-#endif
static irqreturn_t msm_timer_interrupt(int irq, void *dev_id);
static cycle_t msm_gpt_read(struct clocksource *cs);
static cycle_t msm_dgt_read(struct clocksource *cs);
@@ -203,8 +158,8 @@
.dev_id = &msm_clocks[0].clockevent,
.irq = INT_GP_TIMER_EXP
},
- .regbase = MSM_GPT_BASE,
- .freq = GPT_HZ,
+ .regbase = MSM_TMR_BASE + 0x4,
+ .freq = 32768,
.index = MSM_CLOCK_GPT,
.flags =
#if defined(CONFIG_CPU_V6) || defined(CONFIG_ARCH_MSM7X27A)
@@ -219,7 +174,7 @@
.clockevent = {
.name = "dg_timer",
.features = CLOCK_EVT_FEAT_ONESHOT,
- .shift = 32 + MSM_DGT_SHIFT,
+ .shift = 32,
.rating = DG_TIMER_RATING,
.set_next_event = msm_timer_set_next_event,
.set_mode = msm_timer_set_mode,
@@ -228,8 +183,8 @@
.name = "dg_timer",
.rating = DG_TIMER_RATING,
.read = msm_dgt_read,
- .mask = CLOCKSOURCE_MASK((32-MSM_DGT_SHIFT)),
- .shift = 24 - MSM_DGT_SHIFT,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 24,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
},
.irq = {
@@ -240,10 +195,8 @@
.dev_id = &msm_clocks[1].clockevent,
.irq = INT_DEBUG_TIMER_EXP
},
- .regbase = MSM_DGT_BASE,
- .freq = DGT_HZ >> MSM_DGT_SHIFT,
+ .regbase = MSM_TMR_BASE + 0x24,
.index = MSM_CLOCK_DGT,
- .shift = MSM_DGT_SHIFT,
.write_delay = 9,
}
};
@@ -317,22 +270,23 @@
&per_cpu(msm_clocks_percpu, 0)[MSM_CLOCK_DGT];
if (clock_state->stopped)
- return clock_state->stopped_tick >> MSM_DGT_SHIFT;
+ return clock_state->stopped_tick >> clock->shift;
return (msm_read_timer_count(clock, GLOBAL_TIMER) +
- clock_state->sleep_offset) >> MSM_DGT_SHIFT;
+ clock_state->sleep_offset) >> clock->shift;
}
-#ifdef CONFIG_SMP
static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
{
+#ifdef CONFIG_SMP
int i;
for (i = 0; i < NR_TIMERS; i++)
if (evt == &(msm_clocks[i].clockevent))
return &msm_clocks[i];
- return &msm_clocks[MSM_GLOBAL_TIMER];
-}
+ return &msm_clocks[msm_global_timer];
#endif
+ return container_of(evt, struct msm_clock, clockevent);
+}
static int msm_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
@@ -344,11 +298,7 @@
uint32_t alarm;
int late;
-#ifdef CONFIG_SMP
clock = clockevent_to_clock(evt);
-#else
- clock = container_of(evt, struct msm_clock, clockevent);
-#endif
clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
if (clock_state->stopped)
return 0;
@@ -385,11 +335,7 @@
struct msm_clock_percpu_data *clock_state, *gpt_state;
unsigned long irq_flags;
-#ifdef CONFIG_SMP
clock = clockevent_to_clock(evt);
-#else
- clock = container_of(evt, struct msm_clock, clockevent);
-#endif
clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
gpt_state = &__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
@@ -453,6 +399,8 @@
return MSM_TMR_BASE + global_timer_offset;
}
+#define MPM_SCLK_COUNT_VAL 0x0024
+
#ifdef CONFIG_PM
/*
* Retrieve the cycle count from sclk and optionally synchronize local clock
@@ -480,7 +428,9 @@
uint32_t t1, t2;
int loop_count = 10;
int loop_zero_count = 3;
- int tmp = USEC_PER_SEC/SCLK_HZ/(loop_zero_count-1);
+ int tmp = USEC_PER_SEC;
+ do_div(tmp, sclk_hz);
+ tmp /= (loop_zero_count-1);
while (loop_zero_count--) {
t1 = __raw_readl(MSM_RPM_MPM_BASE + MPM_SCLK_COUNT_VAL);
@@ -507,10 +457,21 @@
}
if (update != NULL)
- update(data, t1, SCLK_HZ);
+ update(data, t1, sclk_hz);
return t1;
}
#elif defined(CONFIG_MSM_N_WAY_SMSM)
+
+/* Time Master State Bits */
+#define MASTER_BITS_PER_CPU 1
+#define MASTER_TIME_PENDING \
+ (0x01UL << (MASTER_BITS_PER_CPU * SMSM_APPS_STATE))
+
+/* Time Slave State Bits */
+#define SLAVE_TIME_REQUEST 0x0400
+#define SLAVE_TIME_POLL 0x0800
+#define SLAVE_TIME_INIT 0x1000
+
static uint32_t msm_timer_do_sync_to_sclk(
void (*time_start)(struct msm_timer_sync_data_t *data),
bool (*time_expired)(struct msm_timer_sync_data_t *data),
@@ -567,7 +528,7 @@
if (smem_clock_val) {
if (update != NULL)
- update(data, smem_clock_val, SCLK_HZ);
+ update(data, smem_clock_val, sclk_hz);
if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
printk(KERN_INFO
@@ -641,7 +602,7 @@
if (smem_clock_val) {
if (update != NULL)
- update(data, smem_clock_val, SCLK_HZ);
+ update(data, smem_clock_val, sclk_hz);
} else {
printk(KERN_EMERG
"get_smem_clock: timeout state %x clock %u\n",
@@ -761,9 +722,11 @@
&__get_cpu_var(msm_clocks_percpu)[clock->index];
struct msm_timer_sync_data_t data;
uint32_t gpt_clk_val;
- u64 gpt_period = (1ULL << 32) * HZ / GPT_HZ;
+ u64 gpt_period = (1ULL << 32) * HZ;
u64 now = get_jiffies_64();
+ do_div(gpt_period, gpt_hz);
+
BUG_ON(clock == gpt_clk);
if (clock_state->in_sync &&
@@ -780,7 +743,7 @@
data.timeout = 0;
data.exit_sleep = exit_sleep;
- msm_timer_sync_update(&data, gpt_clk_val, GPT_HZ);
+ msm_timer_sync_update(&data, gpt_clk_val, gpt_hz);
clock_state->in_sync = 1;
clock_state->last_sync_gpt = gpt_clk_val;
@@ -937,12 +900,14 @@
if (period) {
tmp = 1LL << 32;
- tmp = tmp * NSEC_PER_SEC / SCLK_HZ;
+ tmp *= NSEC_PER_SEC;
+ do_div(tmp, sclk_hz);
*period = tmp;
}
tmp = (int64_t)clock_value;
- tmp = tmp * NSEC_PER_SEC / SCLK_HZ;
+ tmp *= NSEC_PER_SEC;
+ do_div(tmp, sclk_hz);
return tmp;
}
@@ -973,7 +938,7 @@
unsigned long long notrace sched_clock(void)
{
- struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
+ struct msm_clock *clock = &msm_clocks[msm_global_timer];
struct clocksource *cs = &clock->clocksource;
u32 cyc = cs->read(cs);
return cyc_to_sched_clock(&cd, cyc, ((u32)~0 >> clock->shift));
@@ -981,7 +946,7 @@
static void notrace msm_update_sched_clock(void)
{
- struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
+ struct msm_clock *clock = &msm_clocks[msm_global_timer];
struct clocksource *cs = &clock->clocksource;
u32 cyc = cs->read(cs);
update_sched_clock(&cd, cyc, ((u32)~0) >> clock->shift);
@@ -998,7 +963,7 @@
static void __init msm_sched_clock_init(void)
{
- struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
+ struct msm_clock *clock = &msm_clocks[msm_global_timer];
init_sched_clock(&cd, msm_update_sched_clock, 32 - clock->shift,
clock->freq);
@@ -1007,11 +972,47 @@
{
int i;
int res;
+ struct msm_clock *dgt = &msm_clocks[MSM_CLOCK_DGT];
+ struct msm_clock *gpt = &msm_clocks[MSM_CLOCK_GPT];
-#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) || \
- defined(CONFIG_ARCH_APQ8064) || defined(CONFIG_ARCH_MSM9615)
- __raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-#endif
+ if (cpu_is_msm7x01() || cpu_is_msm7x25() || cpu_is_msm7x27() ||
+ cpu_is_msm7x25a() || cpu_is_msm7x27a() || cpu_is_msm7x25aa() ||
+ cpu_is_msm7x27aa()) {
+ dgt->shift = MSM_DGT_SHIFT;
+ dgt->freq = 19200000 >> MSM_DGT_SHIFT;
+ dgt->clockevent.shift = 32 + MSM_DGT_SHIFT;
+ dgt->clocksource.mask = CLOCKSOURCE_MASK(32 - MSM_DGT_SHIFT);
+ dgt->clocksource.shift = 24 - MSM_DGT_SHIFT;
+ gpt->regbase = MSM_TMR_BASE;
+ dgt->regbase = MSM_TMR_BASE + 0x10;
+ } else if (cpu_is_qsd8x50()) {
+ dgt->freq = 4800000;
+ gpt->regbase = MSM_TMR_BASE;
+ dgt->regbase = MSM_TMR_BASE + 0x10;
+ } else if (cpu_is_fsm9xxx())
+ dgt->freq = 4800000;
+ else if (cpu_is_msm7x30() || cpu_is_msm8x55())
+ dgt->freq = 6144000;
+ else if (cpu_is_msm8x60()) {
+ dgt->freq = 6750000;
+ __raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+ } else if (cpu_is_msm8960() || cpu_is_apq8064() || cpu_is_msm8930()
+ || cpu_is_msm9615()) {
+ dgt->freq = 6750000;
+ __raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+ gpt->freq = 32765;
+ gpt_hz = 32765;
+ sclk_hz = 32765;
+ } else {
+ WARN_ON("Timer running on unknown hardware. Configure this! "
+ "Assuming default configuration.\n");
+ dgt->freq = 6750000;
+ }
+
+ if (msm_clocks[MSM_CLOCK_GPT].clocksource.rating > DG_TIMER_RATING)
+ msm_global_timer = MSM_CLOCK_GPT;
+ else
+ msm_global_timer = MSM_CLOCK_DGT;
for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
struct msm_clock *clock = &msm_clocks[i];
@@ -1022,14 +1023,14 @@
__raw_writel(0, clock->regbase + TIMER_COUNT_VAL);
__raw_writel(~0, clock->regbase + TIMER_MATCH_VAL);
- if ((clock->freq << clock->shift) == GPT_HZ) {
+ if ((clock->freq << clock->shift) == gpt_hz) {
clock->rollover_offset = 0;
} else {
uint64_t temp;
temp = clock->freq << clock->shift;
temp <<= 32;
- temp /= GPT_HZ;
+ do_div(temp, gpt_hz);
clock->rollover_offset = (uint32_t) temp;
}
@@ -1072,7 +1073,7 @@
{
unsigned long flags;
static DEFINE_PER_CPU(bool, first_boot) = true;
- struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
+ struct msm_clock *clock = &msm_clocks[msm_global_timer];
/* Use existing clock_event for cpu 0 */
if (!smp_processor_id())
diff --git a/arch/arm/mach-msm/wcnss-ssr-8960.c b/arch/arm/mach-msm/wcnss-ssr-8960.c
index 954b925..2ef5c61 100644
--- a/arch/arm/mach-msm/wcnss-ssr-8960.c
+++ b/arch/arm/mach-msm/wcnss-ssr-8960.c
@@ -38,8 +38,7 @@
static void riva_smsm_cb_fn(struct work_struct *work)
{
- pr_err("%s: Initiating subsytem restart\n", MODULE_NAME);
- subsystem_restart("riva");
+ panic(MODULE_NAME ": SMSM reset request received from Riva");
}
static void smsm_state_cb_hdlr(void *data, uint32_t old_state,
@@ -59,9 +58,8 @@
static void riva_fatal_fn(struct work_struct *work)
{
- pr_err("%s: Watchdog bite received from Riva\n", MODULE_NAME);
if (!ss_restart_inprogress)
- subsystem_restart("riva");
+ panic(MODULE_NAME ": Watchdog bite received from Riva");
}
/* SMSM reset Riva */
diff --git a/drivers/gpu/ion/ion.c b/drivers/gpu/ion/ion.c
index a9dfc60..930ba83 100644
--- a/drivers/gpu/ion/ion.c
+++ b/drivers/gpu/ion/ion.c
@@ -630,7 +630,7 @@
buffer = handle->buffer;
mutex_lock(&buffer->lock);
- if (ION_IS_CACHED(buffer->flags)) {
+ if (!ION_IS_CACHED(buffer->flags)) {
ret = 0;
goto out;
}
@@ -688,29 +688,25 @@
{
struct ion_client *client = s->private;
struct rb_node *n;
- size_t sizes[ION_NUM_HEAPS] = {0};
- const char *names[ION_NUM_HEAPS] = {0};
- int i;
+ seq_printf(s, "%16.16s: %16.16s : %16.16s : %16.16s\n", "heap_name",
+ "size_in_bytes", "handle refcount", "buffer");
mutex_lock(&client->lock);
for (n = rb_first(&client->handles); n; n = rb_next(n)) {
struct ion_handle *handle = rb_entry(n, struct ion_handle,
node);
- enum ion_heap_type type = handle->buffer->heap->type;
- if (!names[type])
- names[type] = handle->buffer->heap->name;
- sizes[type] += handle->buffer->size;
+ seq_printf(s, "%16.16s: %16u : %16d : %16p\n",
+ handle->buffer->heap->name,
+ handle->buffer->size,
+ atomic_read(&handle->ref.refcount),
+ handle->buffer);
}
+
+ seq_printf(s, "%16.16s %d\n", "client refcount:",
+ atomic_read(&client->ref.refcount));
mutex_unlock(&client->lock);
- seq_printf(s, "%16.16s: %16.16s\n", "heap_name", "size_in_bytes");
- for (i = 0; i < ION_NUM_HEAPS; i++) {
- if (!names[i])
- continue;
- seq_printf(s, "%16.16s: %16u %d\n", names[i], sizes[i],
- atomic_read(&client->ref.refcount));
- }
return 0;
}
@@ -1247,6 +1243,14 @@
seq_printf(s, "%16.s %16u %16u\n", client->name, client->pid,
size);
}
+ if (heap->ops->get_allocated) {
+ seq_printf(s, "total bytes currently allocated: %lx\n",
+ heap->ops->get_allocated(heap));
+ }
+ if (heap->ops->get_total) {
+ seq_printf(s, "total heap size: %lx\n",
+ heap->ops->get_total(heap));
+ }
return 0;
}
diff --git a/drivers/gpu/ion/ion_carveout_heap.c b/drivers/gpu/ion/ion_carveout_heap.c
index 86d4c8e..a572ca8 100644
--- a/drivers/gpu/ion/ion_carveout_heap.c
+++ b/drivers/gpu/ion/ion_carveout_heap.c
@@ -31,6 +31,8 @@
struct ion_heap heap;
struct gen_pool *pool;
ion_phys_addr_t base;
+ unsigned long allocated_bytes;
+ unsigned long total_size;
};
ion_phys_addr_t ion_carveout_allocate(struct ion_heap *heap,
@@ -45,6 +47,7 @@
if (!offset)
return ION_CARVEOUT_ALLOCATE_FAIL;
+ carveout_heap->allocated_bytes += size;
return offset;
}
@@ -57,6 +60,7 @@
if (addr == ION_CARVEOUT_ALLOCATE_FAIL)
return;
gen_pool_free(carveout_heap->pool, addr, size);
+ carveout_heap->allocated_bytes -= size;
}
static int ion_carveout_heap_phys(struct ion_heap *heap,
@@ -156,6 +160,22 @@
return 0;
}
+static unsigned long ion_carveout_get_allocated(struct ion_heap *heap)
+{
+ struct ion_carveout_heap *carveout_heap =
+ container_of(heap, struct ion_carveout_heap, heap);
+
+ return carveout_heap->allocated_bytes;
+}
+
+static unsigned long ion_carveout_get_total(struct ion_heap *heap)
+{
+ struct ion_carveout_heap *carveout_heap =
+ container_of(heap, struct ion_carveout_heap, heap);
+
+ return carveout_heap->total_size;
+}
+
static struct ion_heap_ops carveout_heap_ops = {
.allocate = ion_carveout_heap_allocate,
.free = ion_carveout_heap_free,
@@ -164,6 +184,8 @@
.map_kernel = ion_carveout_heap_map_kernel,
.unmap_kernel = ion_carveout_heap_unmap_kernel,
.cache_op = ion_carveout_cache_ops,
+ .get_allocated = ion_carveout_get_allocated,
+ .get_total = ion_carveout_get_total,
};
struct ion_heap *ion_carveout_heap_create(struct ion_platform_heap *heap_data)
@@ -189,6 +211,8 @@
}
carveout_heap->heap.ops = &carveout_heap_ops;
carveout_heap->heap.type = ION_HEAP_TYPE_CARVEOUT;
+ carveout_heap->allocated_bytes = 0;
+ carveout_heap->total_size = heap_data->size;
return &carveout_heap->heap;
}
diff --git a/drivers/gpu/ion/ion_priv.h b/drivers/gpu/ion/ion_priv.h
index fd5c125..10e2219 100644
--- a/drivers/gpu/ion/ion_priv.h
+++ b/drivers/gpu/ion/ion_priv.h
@@ -104,6 +104,8 @@
int (*cache_op)(struct ion_heap *heap, struct ion_buffer *buffer,
void *vaddr, unsigned int offset,
unsigned int length, unsigned int cmd);
+ unsigned long (*get_allocated)(struct ion_heap *heap);
+ unsigned long (*get_total)(struct ion_heap *heap);
};
/**
diff --git a/drivers/gpu/ion/ion_system_heap.c b/drivers/gpu/ion/ion_system_heap.c
index 5609b72..b26d48c 100644
--- a/drivers/gpu/ion/ion_system_heap.c
+++ b/drivers/gpu/ion/ion_system_heap.c
@@ -23,6 +23,9 @@
#include "ion_priv.h"
#include <mach/memory.h>
+static atomic_t system_heap_allocated;
+static atomic_t system_contig_heap_allocated;
+
static int ion_system_heap_allocate(struct ion_heap *heap,
struct ion_buffer *buffer,
unsigned long size, unsigned long align,
@@ -31,12 +34,15 @@
buffer->priv_virt = vmalloc_user(size);
if (!buffer->priv_virt)
return -ENOMEM;
+
+ atomic_add(size, &system_heap_allocated);
return 0;
}
void ion_system_heap_free(struct ion_buffer *buffer)
{
vfree(buffer->priv_virt);
+ atomic_sub(buffer->size, &system_heap_allocated);
}
struct scatterlist *ion_system_heap_map_dma(struct ion_heap *heap,
@@ -149,6 +155,11 @@
return 0;
}
+static unsigned long ion_system_heap_get_allocated(struct ion_heap *heap)
+{
+ return atomic_read(&system_heap_allocated);
+}
+
static struct ion_heap_ops vmalloc_ops = {
.allocate = ion_system_heap_allocate,
.free = ion_system_heap_free,
@@ -158,6 +169,7 @@
.unmap_kernel = ion_system_heap_unmap_kernel,
.map_user = ion_system_heap_map_user,
.cache_op = ion_system_heap_cache_ops,
+ .get_allocated = ion_system_heap_get_allocated,
};
struct ion_heap *ion_system_heap_create(struct ion_platform_heap *unused)
@@ -186,12 +198,14 @@
buffer->priv_virt = kzalloc(len, GFP_KERNEL);
if (!buffer->priv_virt)
return -ENOMEM;
+ atomic_add(len, &system_contig_heap_allocated);
return 0;
}
void ion_system_contig_heap_free(struct ion_buffer *buffer)
{
kfree(buffer->priv_virt);
+ atomic_sub(buffer->size, &system_contig_heap_allocated);
}
static int ion_system_contig_heap_phys(struct ion_heap *heap,
@@ -266,6 +280,11 @@
return 0;
}
+static unsigned long ion_system_contig_heap_get_allocated(struct ion_heap *heap)
+{
+ return atomic_read(&system_contig_heap_allocated);
+}
+
static struct ion_heap_ops kmalloc_ops = {
.allocate = ion_system_contig_heap_allocate,
.free = ion_system_contig_heap_free,
@@ -276,6 +295,7 @@
.unmap_kernel = ion_system_heap_unmap_kernel,
.map_user = ion_system_contig_heap_map_user,
.cache_op = ion_system_contig_heap_cache_ops,
+ .get_allocated = ion_system_contig_heap_get_allocated,
};
struct ion_heap *ion_system_contig_heap_create(struct ion_platform_heap *unused)
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 639f219..d59057c 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -61,7 +61,7 @@
adreno_regwrite(rb->device, REG_CP_RB_WPTR, rb->wptr);
}
-static int
+static void
adreno_ringbuffer_waitspace(struct adreno_ringbuffer *rb, unsigned int numcmds,
int wptr_ahead)
{
@@ -102,8 +102,6 @@
freecmds = rb->rptr - rb->wptr;
} while ((freecmds != 0) && (freecmds <= numcmds));
-
- return 0;
}
@@ -111,7 +109,6 @@
unsigned int numcmds)
{
unsigned int *ptr = NULL;
- int status = 0;
BUG_ON(numcmds >= rb->sizedwords);
@@ -122,22 +119,20 @@
/* reserve dwords for nop packet */
if ((rb->wptr + numcmds) > (rb->sizedwords -
GSL_RB_NOP_SIZEDWORDS))
- status = adreno_ringbuffer_waitspace(rb, numcmds, 1);
+ adreno_ringbuffer_waitspace(rb, numcmds, 1);
} else {
/* wptr behind rptr */
if ((rb->wptr + numcmds) >= rb->rptr)
- status = adreno_ringbuffer_waitspace(rb, numcmds, 0);
+ adreno_ringbuffer_waitspace(rb, numcmds, 0);
/* check for remaining space */
/* reserve dwords for nop packet */
if ((rb->wptr + numcmds) > (rb->sizedwords -
GSL_RB_NOP_SIZEDWORDS))
- status = adreno_ringbuffer_waitspace(rb, numcmds, 1);
+ adreno_ringbuffer_waitspace(rb, numcmds, 1);
}
- if (status == 0) {
- ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
- rb->wptr += numcmds;
- }
+ ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+ rb->wptr += numcmds;
return ptr;
}
@@ -391,7 +386,7 @@
return status;
}
-int adreno_ringbuffer_stop(struct adreno_ringbuffer *rb)
+void adreno_ringbuffer_stop(struct adreno_ringbuffer *rb)
{
if (rb->flags & KGSL_FLAGS_STARTED) {
/* ME_HALT */
@@ -399,8 +394,6 @@
rb->flags &= ~KGSL_FLAGS_STARTED;
}
-
- return 0;
}
int adreno_ringbuffer_init(struct kgsl_device *device)
@@ -443,7 +436,7 @@
return 0;
}
-int adreno_ringbuffer_close(struct adreno_ringbuffer *rb)
+void adreno_ringbuffer_close(struct adreno_ringbuffer *rb)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);
@@ -457,8 +450,6 @@
adreno_dev->pm4_fw = NULL;
memset(rb, 0, sizeof(struct adreno_ringbuffer));
-
- return 0;
}
static uint32_t
diff --git a/drivers/gpu/msm/adreno_ringbuffer.h b/drivers/gpu/msm/adreno_ringbuffer.h
index 487a748..a90b0cb 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.h
+++ b/drivers/gpu/msm/adreno_ringbuffer.h
@@ -117,9 +117,9 @@
int adreno_ringbuffer_start(struct adreno_ringbuffer *rb,
unsigned int init_ram);
-int adreno_ringbuffer_stop(struct adreno_ringbuffer *rb);
+void adreno_ringbuffer_stop(struct adreno_ringbuffer *rb);
-int adreno_ringbuffer_close(struct adreno_ringbuffer *rb);
+void adreno_ringbuffer_close(struct adreno_ringbuffer *rb);
void adreno_ringbuffer_issuecmds(struct kgsl_device *device,
unsigned int flags,
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index f43b96e..30365a3 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -226,8 +226,6 @@
{
int ret;
unsigned int range = memdesc->size;
- unsigned int iommu_map_addr;
- int map_order = get_order(SZ_4K);
struct iommu_domain *domain = (struct iommu_domain *)
mmu_specific_pt;
@@ -240,14 +238,11 @@
if (range == 0 || gpuaddr == 0)
return 0;
- for (iommu_map_addr = gpuaddr; iommu_map_addr < (gpuaddr + range);
- iommu_map_addr += SZ_4K) {
- ret = iommu_unmap(domain, iommu_map_addr, map_order);
- if (ret)
- KGSL_CORE_ERR("iommu_unmap(%p, %x, %d) failed "
- "with err: %d\n", domain, iommu_map_addr,
- map_order, ret);
- }
+ ret = iommu_unmap_range(domain, gpuaddr, range);
+ if (ret)
+ KGSL_CORE_ERR("iommu_unmap_range(%p, %x, %d) failed "
+ "with err: %d\n", domain, gpuaddr,
+ range, ret);
return 0;
}
@@ -257,34 +252,23 @@
struct kgsl_memdesc *memdesc,
unsigned int protflags)
{
- int ret, i;
- struct scatterlist *s;
+ int ret;
unsigned int iommu_virt_addr;
- int map_order;
struct iommu_domain *domain = mmu_specific_pt;
BUG_ON(NULL == domain);
- map_order = get_order(SZ_4K);
iommu_virt_addr = memdesc->gpuaddr;
- for_each_sg(memdesc->sg, s, memdesc->sglen, i) {
- unsigned int paddr = sg_phys(s), j;
- for (j = paddr; j < paddr + s->length; j += PAGE_SIZE) {
- ret = iommu_map(domain, iommu_virt_addr, j,
- map_order, MSM_IOMMU_ATTR_NONCACHED);
- if (ret) {
- KGSL_CORE_ERR("iommu_map(%p, %x, %x, %d, %d) "
- "failed with err: %d\n", domain,
- iommu_virt_addr, j, map_order,
- MSM_IOMMU_ATTR_NONCACHED, ret);
- kgsl_iommu_unmap(mmu_specific_pt, memdesc);
- return ret;
- }
-
- iommu_virt_addr += SZ_4K;
- }
+ ret = iommu_map_range(domain, iommu_virt_addr, memdesc->sg,
+ memdesc->size, MSM_IOMMU_ATTR_NONCACHED);
+ if (ret) {
+ KGSL_CORE_ERR("iommu_map_range(%p, %x, %p, %d, %d) "
+ "failed with err: %d\n", domain,
+ iommu_virt_addr, memdesc->sg, memdesc->size,
+ MSM_IOMMU_ATTR_NONCACHED, ret);
+ return ret;
}
return ret;
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 84f2b33..aee42a1 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -582,11 +582,11 @@
idle_check_ws);
mutex_lock(&device->mutex);
- if (device->ftbl->isidle(device) &&
- (device->requested_state != KGSL_STATE_SLEEP))
- kgsl_pwrscale_idle(device);
-
if (device->state & (KGSL_STATE_ACTIVE | KGSL_STATE_NAP)) {
+ if (device->ftbl->isidle(device) &&
+ (device->requested_state != KGSL_STATE_SLEEP))
+ kgsl_pwrscale_idle(device);
+
if (kgsl_pwrctrl_sleep(device) != 0) {
mod_timer(&device->idle_timer,
jiffies +
diff --git a/drivers/gpu/msm/kgsl_pwrscale.c b/drivers/gpu/msm/kgsl_pwrscale.c
index fa7203d..b5c6876 100644
--- a/drivers/gpu/msm/kgsl_pwrscale.c
+++ b/drivers/gpu/msm/kgsl_pwrscale.c
@@ -272,8 +272,11 @@
static void _kgsl_pwrscale_detach_policy(struct kgsl_device *device)
{
- if (device->pwrscale.policy != NULL)
+ if (device->pwrscale.policy != NULL) {
device->pwrscale.policy->close(device, &device->pwrscale);
+ kgsl_pwrctrl_pwrlevel_change(device,
+ device->pwrctrl.thermal_pwrlevel);
+ }
device->pwrscale.policy = NULL;
}
diff --git a/drivers/hwmon/pm8921-adc.c b/drivers/hwmon/pm8921-adc.c
index 5ab6296..33f4a3a 100644
--- a/drivers/hwmon/pm8921-adc.c
+++ b/drivers/hwmon/pm8921-adc.c
@@ -31,6 +31,7 @@
#include <linux/mfd/pm8xxx/pm8921-adc.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
+#include <linux/wakelock.h>
/* User Bank register set */
#define PM8921_ADC_ARB_USRP_CNTRL1 0x197
@@ -142,6 +143,8 @@
uint32_t mpp_base;
struct sensor_device_attribute *sens_attr;
struct device *hwmon;
+ struct wake_lock adc_wakelock;
+ int msm_suspend_check;
};
struct pm8921_adc_amux_properties {
@@ -188,14 +191,18 @@
static bool pm8921_adc_calib_first_adc;
static bool pm8921_adc_initialized, pm8921_adc_calib_device_init;
-static int32_t pm8921_adc_arb_cntrl(uint32_t arb_cntrl)
+static int32_t pm8921_adc_arb_cntrl(uint32_t arb_cntrl, uint32_t channel)
{
struct pm8921_adc *adc_pmic = pmic_adc;
int i, rc;
u8 data_arb_cntrl = 0;
- if (arb_cntrl)
+ if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("PM8921 ADC request being made after suspend "
+ "irq with channel id:%d\n", channel);
data_arb_cntrl |= PM8921_ADC_ARB_USRP_CNTRL1_EN_ARB;
+ }
/* Write twice to the CNTRL register for the arbiter settings
to take into effect */
@@ -212,6 +219,13 @@
data_arb_cntrl |= PM8921_ADC_ARB_USRP_CNTRL1_REQ;
rc = pm8xxx_writeb(adc_pmic->dev->parent,
PM8921_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ if (rc < 0) {
+ pr_err("PM8921 arb cntrl write failed with %d\n", rc);
+ return rc;
+ }
+ wake_lock(&adc_pmic->adc_wakelock);
+ } else {
+ wake_unlock(&adc_pmic->adc_wakelock);
}
return 0;
@@ -369,7 +383,7 @@
if (!pm8921_adc_calib_first_adc)
enable_irq(adc_pmic->adc_irq);
- rc = pm8921_adc_arb_cntrl(1);
+ rc = pm8921_adc_arb_cntrl(1, chan_prop->amux_mpp_channel);
if (rc < 0) {
pr_err("Configuring ADC Arbiter"
"enable failed with %d\n", rc);
@@ -409,7 +423,7 @@
/* Default value for switching off the arbiter after reading
the ADC value. Bit 0 set to 0. */
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -558,7 +572,7 @@
(calib_read_1 - calib_read_2);
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dx
= PM8921_CHANNEL_ADC_625_MV;
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -638,7 +652,7 @@
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dx =
adc_pmic->adc_prop->adc_vdd_reference;
calib_fail:
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -1122,11 +1136,43 @@
return rc;
}
+#ifdef CONFIG_PM
+static int pm8921_adc_suspend_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pm8921_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8921_adc_resume_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pm8921_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8921_adc_dev_pm_ops = {
+ .suspend_noirq = pm8921_adc_suspend_noirq,
+ .resume_noirq = pm8921_adc_resume_noirq,
+};
+
+#define PM8921_ADC_DEV_PM_OPS (&pm8921_adc_dev_pm_ops)
+#else
+#define PM8921_ADC_DEV_PM_OPS NULL
+#endif
+
static int __devexit pm8921_adc_teardown(struct platform_device *pdev)
{
struct pm8921_adc *adc_pmic = pmic_adc;
int i;
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
free_irq(adc_pmic->adc_irq, adc_pmic);
free_irq(adc_pmic->btm_warm_irq, adc_pmic);
free_irq(adc_pmic->btm_cool_irq, adc_pmic);
@@ -1262,6 +1308,8 @@
INIT_WORK(&adc_pmic->warm_work, pm8921_adc_btm_warm_scheduler_fn);
INIT_WORK(&adc_pmic->cool_work, pm8921_adc_btm_cool_scheduler_fn);
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pm8921_adc_wakelock");
create_debugfs_entries();
pm8921_adc_calib_first_adc = false;
pm8921_adc_calib_device_init = false;
@@ -1286,6 +1334,7 @@
.driver = {
.name = PM8921_ADC_DEV_NAME,
.owner = THIS_MODULE,
+ .pm = PM8921_ADC_DEV_PM_OPS,
},
};
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 00c7633..7a3df4d1 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -601,9 +601,18 @@
{
int total_len = 0;
int ret = 0;
- if (dev->msg->len >= (dev->out_fifo_sz - 1)) {
- total_len = dev->msg->len + 1 +
- (dev->msg->len/(dev->out_blk_sz-1));
+ int len = dev->msg->len;
+ struct i2c_msg *next = NULL;
+ if (rem > 1)
+ next = dev->msg + 1;
+ while (rem > 1 && next->flags == 0) {
+ len += next->len + 1;
+ next = next + 1;
+ rem--;
+ }
+ if (len >= (dev->out_fifo_sz - 1)) {
+ total_len = len + 1 + (len/(dev->out_blk_sz-1));
+
writel_relaxed(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN,
dev->base + QUP_IO_MODE);
dev->wr_sz = dev->out_blk_sz;
@@ -612,7 +621,6 @@
dev->base + QUP_IO_MODE);
if (rem > 1) {
- struct i2c_msg *next = dev->msg + 1;
if (next->addr == dev->msg->addr &&
next->flags == I2C_M_RD) {
qup_set_read_mode(dev, next->len);
diff --git a/drivers/leds/leds-pm8xxx.c b/drivers/leds/leds-pm8xxx.c
index 94af3ce..025b756 100644
--- a/drivers/leds/leds-pm8xxx.c
+++ b/drivers/leds/leds-pm8xxx.c
@@ -18,8 +18,10 @@
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/workqueue.h>
+#include <linux/err.h>
#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/pwm.h>
#include <linux/leds-pm8xxx.h>
#define SSBI_REG_ADDR_DRV_KEYPAD 0x48
@@ -54,6 +56,8 @@
#define PM8XXX_LED_OFFSET(id) ((id) - PM8XXX_ID_LED_0)
+#define PM8XXX_LED_PWM_FLAGS (PM_PWM_LUT_LOOP | PM_PWM_LUT_RAMP_UP)
+
/**
* struct pm8xxx_led_data - internal led data structure
* @led_classdev - led class device
@@ -61,6 +65,10 @@
* @work - workqueue for led
* @lock - to protect the transactions
* @reg - cached value of led register
+ * @pwm_dev - pointer to PWM device if LED is driven using PWM
+ * @pwm_channel - PWM channel ID
+ * @pwm_period_us - PWM period in micro seconds
+ * @pwm_duty_cycles - struct that describes PWM duty cycles info
*/
struct pm8xxx_led_data {
struct led_classdev cdev;
@@ -69,6 +77,10 @@
struct device *dev;
struct work_struct work;
struct mutex lock;
+ struct pwm_device *pwm_dev;
+ int pwm_channel;
+ u32 pwm_period_us;
+ struct pm8xxx_pwm_duty_cycles *pwm_duty_cycles;
};
static void led_kp_set(struct pm8xxx_led_data *led, enum led_brightness value)
@@ -133,6 +145,26 @@
led->id, rc);
}
+static int pm8xxx_led_pwm_work(struct pm8xxx_led_data *led)
+{
+ int duty_us;
+ int rc = 0;
+
+ if (led->pwm_duty_cycles == NULL) {
+ duty_us = (led->pwm_period_us * led->cdev.brightness) /
+ LED_FULL;
+ rc = pwm_config(led->pwm_dev, duty_us, led->pwm_period_us);
+ if (led->cdev.brightness)
+ rc = pwm_enable(led->pwm_dev);
+ else
+ pwm_disable(led->pwm_dev);
+ } else {
+ rc = pm8xxx_pwm_lut_enable(led->pwm_dev, led->cdev.brightness);
+ }
+
+ return rc;
+}
+
static void __pm8xxx_led_work(struct pm8xxx_led_data *led,
enum led_brightness level)
{
@@ -158,11 +190,19 @@
static void pm8xxx_led_work(struct work_struct *work)
{
+ int rc;
+
struct pm8xxx_led_data *led = container_of(work,
struct pm8xxx_led_data, work);
- int level = led->cdev.brightness;
- __pm8xxx_led_work(led, level);
+ if (led->pwm_dev == NULL) {
+ __pm8xxx_led_work(led, led->cdev.brightness);
+ } else {
+ rc = pm8xxx_led_pwm_work(led);
+ if (rc)
+ pr_err("could not configure PWM mode for LED:%d\n",
+ led->id);
+ }
}
static void pm8xxx_led_set(struct led_classdev *led_cdev,
@@ -270,6 +310,47 @@
return rc;
}
+static int pm8xxx_led_pwm_configure(struct pm8xxx_led_data *led)
+{
+ int start_idx, idx_len, duty_us, rc;
+
+ led->pwm_dev = pwm_request(led->pwm_channel,
+ led->cdev.name);
+
+ if (IS_ERR_OR_NULL(led->pwm_dev)) {
+ pr_err("could not acquire PWM Channel %d, "
+ "error %ld\n", led->pwm_channel,
+ PTR_ERR(led->pwm_dev));
+ led->pwm_dev = NULL;
+ return -ENODEV;
+ }
+
+ if (led->pwm_duty_cycles != NULL) {
+ start_idx = led->pwm_duty_cycles->start_idx;
+ idx_len = led->pwm_duty_cycles->num_duty_pcts;
+
+ if (idx_len >= PM_PWM_LUT_SIZE && start_idx) {
+ pr_err("Wrong LUT size or index\n");
+ return -EINVAL;
+ }
+ if ((start_idx + idx_len) > PM_PWM_LUT_SIZE) {
+ pr_err("Exceed LUT limit\n");
+ return -EINVAL;
+ }
+
+ rc = pm8xxx_pwm_lut_config(led->pwm_dev, led->pwm_period_us,
+ led->pwm_duty_cycles->duty_pcts,
+ led->pwm_duty_cycles->duty_ms,
+ start_idx, idx_len, 0, 0,
+ PM8XXX_LED_PWM_FLAGS);
+ } else {
+ duty_us = led->pwm_period_us;
+ rc = pwm_config(led->pwm_dev, duty_us, led->pwm_period_us);
+ }
+
+ return rc;
+}
+
static int __devinit pm8xxx_led_probe(struct platform_device *pdev)
{
const struct pm8xxx_led_platform_data *pdata = pdev->dev.platform_data;
@@ -304,6 +385,9 @@
led_cfg = &pdata->configs[i];
led_dat->id = led_cfg->id;
+ led_dat->pwm_channel = led_cfg->pwm_channel;
+ led_dat->pwm_period_us = led_cfg->pwm_period_us;
+ led_dat->pwm_duty_cycles = led_cfg->pwm_duty_cycles;
if (!((led_dat->id >= PM8XXX_ID_LED_KB_LIGHT) &&
(led_dat->id <= PM8XXX_ID_FLASH_LED_1))) {
@@ -340,11 +424,22 @@
goto fail_id_check;
}
- if (led_cfg->mode != PM8XXX_LED_MODE_MANUAL)
+ if (led_cfg->mode != PM8XXX_LED_MODE_MANUAL) {
__pm8xxx_led_work(led_dat,
led_dat->cdev.max_brightness);
- else
+
+ if (led_dat->pwm_channel != -1) {
+ led_dat->cdev.max_brightness = LED_FULL;
+ rc = pm8xxx_led_pwm_configure(led_dat);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to "
+ "configure LED, error: %d\n", rc);
+ goto fail_id_check;
+ }
+ }
+ } else {
__pm8xxx_led_work(led_dat, LED_OFF);
+ }
}
platform_set_drvdata(pdev, led);
@@ -356,6 +451,8 @@
for (i = i - 1; i >= 0; i--) {
mutex_destroy(&led[i].lock);
led_classdev_unregister(&led[i].cdev);
+ if (led[i].pwm_dev != NULL)
+ pwm_free(led[i].pwm_dev);
}
}
kfree(led);
@@ -373,6 +470,8 @@
cancel_work_sync(&led[i].work);
mutex_destroy(&led[i].lock);
led_classdev_unregister(&led[i].cdev);
+ if (led[i].pwm_dev != NULL)
+ pwm_free(led[i].pwm_dev);
}
kfree(led);
diff --git a/drivers/media/video/msm/actuators/imx074_act.c b/drivers/media/video/msm/actuators/imx074_act.c
index 2af21d6..f267f80 100644
--- a/drivers/media/video/msm/actuators/imx074_act.c
+++ b/drivers/media/video/msm/actuators/imx074_act.c
@@ -15,7 +15,7 @@
#include "msm_logging.h"
#include "msm_camera_i2c.h"
-#define IMX074_TOTAL_STEPS_NEAR_TO_FAR 52
+#define IMX074_TOTAL_STEPS_NEAR_TO_FAR 41
DEFINE_MUTEX(imx074_act_mutex);
static struct msm_actuator_ctrl_t imx074_act_t;
@@ -39,7 +39,7 @@
/* MOVE_NEAR Dir */
/* Scene 1 => Damping params */
{
- .damping_step = 2,
+ .damping_step = 0xFF,
.damping_delay = 0,
},
};
@@ -91,6 +91,23 @@
return rc;
}
+static int32_t imx074_set_default_focus(
+ struct msm_actuator_ctrl_t *a_ctrl)
+{
+ int32_t rc = 0;
+
+ if (!a_ctrl->step_position_table)
+ a_ctrl->func_tbl.actuator_init_table(a_ctrl);
+
+ if (a_ctrl->curr_step_pos != 0) {
+ rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, 0x7F, NULL);
+ rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, 0x7F, NULL);
+ a_ctrl->curr_step_pos = 0;
+ } else if (a_ctrl->func_tbl.actuator_init_focus)
+ rc = a_ctrl->func_tbl.actuator_init_focus(a_ctrl);
+ return rc;
+}
+
static int32_t imx074_act_init_focus(struct msm_actuator_ctrl_t *a_ctrl)
{
int32_t rc;
@@ -207,7 +224,7 @@
.actuator_init_table = msm_actuator_init_table,
.actuator_move_focus = msm_actuator_move_focus,
.actuator_write_focus = imx074_act_write_focus,
- .actuator_set_default_focus = msm_actuator_set_default_focus,
+ .actuator_set_default_focus = imx074_set_default_focus,
.actuator_init_focus = imx074_act_init_focus,
.actuator_i2c_write = imx074_wrapper_i2c_write,
},
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 74534af..5d9112e 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -2356,24 +2356,39 @@
void *act_client = NULL;
struct msm_actuator_ctrl *a_ext_ctrl = NULL;
- if (!actuator_info) {
- actctrl->a_init_table = NULL;
- actctrl->a_power_down = NULL;
- actctrl->a_config = NULL;
- actctrl->a_create_subdevice = NULL;
- return rc;
- }
+ D("%s called\n", __func__);
+
+ if (!actuator_info)
+ goto probe_fail;
adapter = i2c_get_adapter(actuator_info->bus_id);
+ if (!adapter)
+ goto probe_fail;
act_client = i2c_new_device(adapter, actuator_info->board_info);
+ if (!act_client)
+ goto device_fail;
a_ext_ctrl = (struct msm_actuator_ctrl *)i2c_get_clientdata(act_client);
+ if (!a_ext_ctrl)
+ goto client_fail;
*actctrl = *a_ext_ctrl;
a_ext_ctrl->a_create_subdevice((void *)actuator_info->board_info,
(void *)act_sdev);
return rc;
+
+client_fail:
+ i2c_unregister_device(act_client);
+device_fail:
+ i2c_put_adapter(adapter);
+ adapter = NULL;
+probe_fail:
+ actctrl->a_init_table = NULL;
+ actctrl->a_power_down = NULL;
+ actctrl->a_config = NULL;
+ actctrl->a_create_subdevice = NULL;
+ return rc;
}
static int msm_sync_init(struct msm_sync *sync,
@@ -2544,6 +2559,7 @@
implemenation of mutex_init is not consuming resources */
msm_sync_destroy(&pcam->mctl.sync);
pcam->pdev = NULL;
+ kfree(act_sdev);
kfree(sdev);
kzfree(pcam);
return rc;
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 219e504..51b7a90 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -678,7 +678,7 @@
msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
- msm_io_dump(vfe32_ctrl->vfebase, 0x7B4);
+ msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total * 4);
/* Ensure the write order while writing
to the command register using the barrier */
@@ -986,7 +986,6 @@
int i;
uint32_t value, value1, value2;
vfe32_program_dmi_cfg(channel_sel);
- /* for loop for extracting init table. */
for (i = 0 ; i < (VFE32_GAMMA_NUM_ENTRIES/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
@@ -997,6 +996,20 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
+static void vfe32_read_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
+ uint32_t *tbl)
+{
+ int i;
+ vfe32_program_dmi_cfg(channel_sel);
+ CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
+ for (i = 0 ; i < VFE32_GAMMA_NUM_ENTRIES ; i++) {
+ *tbl = msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *tbl);
+ tbl++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+}
+
static void vfe32_write_la_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
{
@@ -1004,7 +1017,6 @@
uint32_t value, value1, value2;
vfe32_program_dmi_cfg(channel_sel);
- /* for loop for extracting init table. */
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
@@ -1196,23 +1208,6 @@
}
rc = vfe32_capture(snapshot_cnt);
break;
- case VFE_CMD_GET_HW_VERSION:
- if (cmd->length != V32_GET_HW_VERSION_LEN) {
- rc = -EINVAL;
- goto proc_general_done;
- }
- cmdp = kmalloc(V32_GET_HW_VERSION_LEN, GFP_ATOMIC);
- if (!cmdp) {
- rc = -ENOMEM;
- goto proc_general_done;
- }
- *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
- if (copy_to_user((void __user *)(cmd->value), cmdp,
- V32_GET_HW_VERSION_LEN)) {
- rc = -EFAULT;
- goto proc_general_done;
- }
- break;
case VFE_CMD_START_RECORDING:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
@@ -1342,12 +1337,6 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= RS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- */
msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
@@ -1365,12 +1354,6 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= CS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- */
msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
@@ -1453,6 +1436,44 @@
}
break;
+ case VFE_CMD_GET_MESH_ROLLOFF_TABLE:
+ temp1 = sizeof(uint32_t) * ((V32_MESH_ROLL_OFF_INIT_TABLE_SIZE *
+ 2) + (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2));
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ CDBG("%s: Mesh Rolloff init Table\n", __func__);
+ for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
+ for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ CDBG("done reading delta table\n");
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_LA_CFG:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
@@ -1500,6 +1521,36 @@
vfe32_ctrl->update_la = true;
break;
+ case VFE_CMD_GET_LA_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_LA_TABLE_LENGTH / 2;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
+ else
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
+ for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH / 2) ; i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_io_r(vfe32_ctrl->vfebase +
+ VFE_DMI_DATA_LO)) << 16;
+ cmdp_local++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_SK_ENHAN_CFG:
case VFE_CMD_SK_ENHAN_UPDATE:{
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
@@ -1542,7 +1593,7 @@
cmdp_local = cmdp + 17;
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
- break;
+ break;
case VFE_CMD_LINEARIZATION_UPDATE:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
@@ -1572,8 +1623,38 @@
else
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK1, cmdp_local);
vfe32_ctrl->update_linear = true;
- break;
+ break;
+ case VFE_CMD_GET_LINEARIZATON_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_LINEARIZATON_TABLE_LENGTH;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1);
+ else
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0);
+ CDBG("%s: Linearization Table\n", __func__);
+ for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_DEMOSAICV3:
if (cmd->length !=
V32_DEMOSAICV3_0_LEN+V32_DEMOSAICV3_1_LEN) {
@@ -1755,6 +1836,34 @@
cmdp -= 1;
break;
+ case VFE_CMD_GET_RGB_G_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_GAMMA_NUM_ENTRIES * 3;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+
+ old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
+ RGBLUT_RAM_CH0_BANK0;
+ for (i = 0; i < 3; i++) {
+ vfe32_read_gamma_cfg(temp2,
+ cmdp_local + (VFE32_GAMMA_NUM_ENTRIES * i));
+ temp2 += 2;
+ }
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+
case VFE_CMD_STATS_AWB_STOP: {
old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
@@ -1947,9 +2056,9 @@
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
- else
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
@@ -1963,9 +2072,9 @@
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- else
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
@@ -1978,7 +2087,88 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
vfe32_ctrl->update_rolloff = true;
break;
+ case VFE_CMD_GET_PCA_ROLLOFF_TABLE:
+ temp1 = sizeof(uint64_t) * V33_PCA_ROLL_OFF_TABLE_SIZE * 2;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ old_val = msm_io_r(vfe32_ctrl->vfebase +
+ V33_PCA_ROLL_OFF_CFG_OFF1) &
+ V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
+ if (old_val)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+
+ CDBG("%s: PCA Rolloff Ram0\n", __func__);
+ for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE * 2; i++) {
+ temp2 = (i == (V33_PCA_ROLL_OFF_TABLE_SIZE - 1));
+ if (old_val && temp2)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ else if (!old_val && temp2)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
+
+ *(cmdp_local + 1) =
+ msm_io_r(vfe32_ctrl->vfebase +
+ VFE33_DMI_DATA_HI);
+ *cmdp_local = msm_io_r(vfe32_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
+ CDBG("%s: %08x%08x\n", __func__,
+ *(cmdp_local + 1), *cmdp_local);
+ cmdp_local += 2;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+ case VFE_CMD_GET_HW_VERSION:
+ if (cmd->length != V32_GET_HW_VERSION_LEN) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(V32_GET_HW_VERSION_LEN, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ V32_GET_HW_VERSION_LEN)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+ case VFE_CMD_GET_REG_DUMP:
+ temp1 = sizeof(uint32_t) * vfe32_ctrl->register_total;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(temp1, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
+ CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
+ vfe32_ctrl->vfebase, temp1);
+ memcpy_fromio((void *)cmdp, vfe32_ctrl->vfebase, temp1);
+ if (copy_to_user((void __user *)(cmd->value), cmdp, temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
default:
if (cmd->length != vfe32_cmd[cmd->id].length)
return -EINVAL;
@@ -3371,6 +3561,12 @@
msm_camio_set_perf_lvl(S_INIT);
msm_camio_set_perf_lvl(S_PREVIEW);
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ VFE32_HW_NUMBER)
+ vfe32_ctrl->register_total = VFE32_REGISTER_TOTAL;
+ else
+ vfe32_ctrl->register_total = VFE33_REGISTER_TOTAL;
+
/* TO DO: Need to release the VFE resources */
rc = request_irq(vfe32_ctrl->vfeirq, vfe32_parse_irq,
IRQF_TRIGGER_RISING, "vfe", 0);
diff --git a/drivers/media/video/msm/msm_vfe32.h b/drivers/media/video/msm/msm_vfe32.h
index d763c2e..30b77d7 100644
--- a/drivers/media/video/msm/msm_vfe32.h
+++ b/drivers/media/video/msm/msm_vfe32.h
@@ -16,6 +16,15 @@
#define TRUE 1
#define FALSE 0
+#define VFE32_HW_NUMBER 0x3030B
+#define VFE33_HW_NUMBER 0x30408
+
+/* This defines total number registers in VFE.
+ * Each register is 4 bytes so to get the range,
+ * multiply this number with 4. */
+#define VFE32_REGISTER_TOTAL 0x000001CD
+#define VFE33_REGISTER_TOTAL 0x000001EE
+
/* at start of camif, bit 1:0 = 0x01:enable
* image data capture at frame boundary. */
#define CAMIF_COMMAND_START 0x00000005
@@ -903,6 +912,7 @@
int vfeirq;
void __iomem *vfebase;
void *syncdata;
+ uint32_t register_total;
struct resource *vfemem;
struct resource *vfeio;
diff --git a/drivers/misc/pmic8058-xoadc.c b/drivers/misc/pmic8058-xoadc.c
index f21668a..b63800c 100644
--- a/drivers/misc/pmic8058-xoadc.c
+++ b/drivers/misc/pmic8058-xoadc.c
@@ -223,7 +223,7 @@
data_arb_rsv = 0x20;
slot->chan_properties.gain_numerator = 1;
slot->chan_properties.gain_denominator = 1;
- slot->chan_properties.adc_graph = &adc_pmic->adc_graph[0];
+ slot->chan_properties.adc_graph = &adc_pmic->adc_graph[1];
break;
case CHAN_PATH_TYPE7:
diff --git a/drivers/mmc/core/sdio_cis.c b/drivers/mmc/core/sdio_cis.c
index dc94222..ebd4132 100644
--- a/drivers/mmc/core/sdio_cis.c
+++ b/drivers/mmc/core/sdio_cis.c
@@ -55,7 +55,7 @@
for (i = 0; i < nr_strings; i++) {
buffer[i] = string;
- strcpy(string, buf);
+ strlcpy(string, buf, sizeof(string));
string += strlen(string) + 1;
buf += strlen(buf) + 1;
}
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index b5a08d2..c1df55e 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -1634,7 +1634,7 @@
}
}
- if (mrq->sbc) {
+ if (mrq->data && mrq->sbc) {
mrq->sbc->mrq = mrq;
mrq->sbc->data = mrq->data;
if (mrq->data->flags & MMC_DATA_WRITE) {
@@ -3000,6 +3000,12 @@
&sps_config->desc.phys_base,
GFP_KERNEL);
+ if (!sps_config->desc.base) {
+ rc = -ENOMEM;
+ pr_err("%s: dma_alloc_coherent() failed!!! Can't allocate buffer\n"
+ , mmc_hostname(host->mmc));
+ goto get_config_err;
+ }
memset(sps_config->desc.base, 0x00, sps_config->desc.size);
/* Establish connection between peripheral and memory endpoint */
@@ -3482,7 +3488,7 @@
struct resource *bam_memres = NULL;
struct resource *dmares = NULL;
struct resource *dma_crci_res = NULL;
- int ret;
+ int ret = 0;
int i;
/* must have platform data */
diff --git a/drivers/net/msm_rmnet_bam.c b/drivers/net/msm_rmnet_bam.c
index 5397cbf..8a3e427 100644
--- a/drivers/net/msm_rmnet_bam.c
+++ b/drivers/net/msm_rmnet_bam.c
@@ -81,8 +81,11 @@
struct tasklet_struct tsklt;
u32 operation_mode; /* IOCTL specified mode (protocol, QoS header) */
uint8_t device_up;
+ uint8_t waiting_for_ul;
};
+static uint8_t ul_is_connected;
+
#ifdef CONFIG_MSM_RMNET_DEBUG
static unsigned long timeout_us;
@@ -337,6 +340,8 @@
static void bam_notify(void *dev, int event, unsigned long data)
{
+ struct rmnet_private *p = netdev_priv(dev);
+
switch (event) {
case BAM_DMUX_RECEIVE:
bam_recv_notify(dev, (struct sk_buff *)(data));
@@ -344,6 +349,16 @@
case BAM_DMUX_WRITE_DONE:
bam_write_done(dev, (struct sk_buff *)(data));
break;
+ case BAM_DMUX_UL_CONNECTED:
+ ul_is_connected = 1;
+ if (p->waiting_for_ul) {
+ netif_wake_queue(dev);
+ p->waiting_for_ul = 0;
+ }
+ break;
+ case BAM_DMUX_UL_DISCONNECTED:
+ ul_is_connected = 0;
+ break;
}
}
@@ -419,6 +434,8 @@
static int rmnet_xmit(struct sk_buff *skb, struct net_device *dev)
{
+ struct rmnet_private *p = netdev_priv(dev);
+
if (netif_queue_stopped(dev)) {
pr_err("[%s]fatal: rmnet_xmit called when "
"netif_queue is stopped", dev->name);
@@ -426,6 +443,11 @@
}
netif_stop_queue(dev);
+ if (!ul_is_connected) {
+ p->waiting_for_ul = 1;
+ msm_bam_dmux_kickoff_ul_wakeup();
+ return NETDEV_TX_BUSY;
+ }
_rmnet_xmit(skb, dev);
return 0;
@@ -626,6 +648,7 @@
/* Initial config uses Ethernet */
p->operation_mode = RMNET_MODE_LLP_ETH;
p->ch_id = n;
+ p->waiting_for_ul = 0;
spin_lock_init(&p->lock);
#ifdef CONFIG_MSM_RMNET_DEBUG
p->timeout_us = timeout_us;
diff --git a/drivers/net/wireless/libra/qcomwlan_pwrif.c b/drivers/net/wireless/libra/qcomwlan_pwrif.c
index de8b918..6dd603c 100644
--- a/drivers/net/wireless/libra/qcomwlan_pwrif.c
+++ b/drivers/net/wireless/libra/qcomwlan_pwrif.c
@@ -14,7 +14,7 @@
#include <linux/qcomwlan_pwrif.h>
#define GPIO_WLAN_DEEP_SLEEP_N 230
-#define GPIO_WLAN_DEEP_SLEEP_N_DRAGON 108
+#define GPIO_WLAN_DEEP_SLEEP_N_DRAGON 82
#define WLAN_RESET_OUT 1
#define WLAN_RESET 0
@@ -212,7 +212,7 @@
}
}
if (on) {
- gpio_set_value_cansleep(GPIO_WLAN_DEEP_SLEEP_N, WLAN_RESET_OUT);
+ gpio_set_value_cansleep(wlan_gpio_deep_sleep, WLAN_RESET_OUT);
wlan_on = true;
}
else
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 3e61ad2..82582c4 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -202,6 +202,9 @@
struct power_supply batt_psy;
struct dentry *dent;
struct bms_notify bms_notify;
+ struct ext_chg_pm8921 *ext;
+ bool ext_charging;
+ bool ext_charge_done;
DECLARE_BITMAP(enabled_irqs, PM_CHG_MAX_INTS);
struct work_struct battery_id_valid_work;
int64_t batt_id_min;
@@ -757,8 +760,33 @@
return pm_chg_get_rt_status(chip, DCIN_VALID_IRQ);
}
+static bool is_ext_charging(struct pm8921_chg_chip *chip)
+{
+ if (chip->ext == NULL)
+ return false;
+
+ if (chip->ext_charging)
+ return true;
+
+ return false;
+}
+
+static bool is_ext_trickle_charging(struct pm8921_chg_chip *chip)
+{
+ if (chip->ext == NULL)
+ return false;
+
+ if (chip->ext->is_trickle(chip->ext->ctx))
+ return true;
+
+ return false;
+}
+
static int is_battery_charging(int fsm_state)
{
+ if (is_ext_charging(the_chip))
+ return 1;
+
switch (fsm_state) {
case FSM_STATE_ATC_2A:
case FSM_STATE_ATC_2B:
@@ -918,6 +946,15 @@
{
int temp;
+ if (!get_prop_batt_present(chip))
+ return POWER_SUPPLY_CHARGE_TYPE_NONE;
+
+ if (is_ext_trickle_charging(chip))
+ return POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
+
+ if (is_ext_charging(chip))
+ return POWER_SUPPLY_CHARGE_TYPE_FAST;
+
temp = pm_chg_get_rt_status(chip, TRKLCHG_IRQ);
if (temp)
return POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
@@ -933,6 +970,17 @@
{
int temp = 0;
+ if (!get_prop_batt_present(chip))
+ return POWER_SUPPLY_STATUS_UNKNOWN;
+
+ if (chip->ext) {
+ if (chip->ext_charge_done)
+ return POWER_SUPPLY_STATUS_FULL;
+
+ if (chip->ext_charging)
+ return POWER_SUPPLY_STATUS_CHARGING;
+ }
+
/* TODO reading the FSM state is more reliable */
temp = pm_chg_get_rt_status(chip, TRKLCHG_IRQ);
@@ -1259,6 +1307,77 @@
bms_notify_check(chip);
}
+static void handle_stop_ext_chg(struct pm8921_chg_chip *chip)
+{
+ if (chip->ext == NULL) {
+ pr_debug("external charger not registered.\n");
+ return;
+ }
+
+ if (!chip->ext_charging) {
+ pr_debug("already not charging.\n");
+ return;
+ }
+
+ chip->ext->stop_charging(chip->ext->ctx);
+ chip->ext_charging = false;
+}
+
+static void handle_start_ext_chg(struct pm8921_chg_chip *chip)
+{
+ int dc_present;
+ int batt_present;
+ int batt_temp_ok;
+ int vbat_ov;
+ int batfet;
+ unsigned long delay =
+ round_jiffies_relative(msecs_to_jiffies(EOC_CHECK_PERIOD_MS));
+
+ if (chip->ext == NULL) {
+ pr_debug("external charger not registered.\n");
+ return;
+ }
+
+ if (chip->ext_charging) {
+ pr_debug("already charging.\n");
+ return;
+ }
+
+ dc_present = is_dc_chg_plugged_in(chip);
+ batt_present = pm_chg_get_rt_status(chip, BATT_INSERTED_IRQ);
+ batt_temp_ok = pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ);
+ vbat_ov = pm_chg_get_rt_status(chip, VBAT_OV_IRQ);
+ batfet = pm_chg_get_rt_status(chip, BATFET_IRQ);
+
+ if (!dc_present) {
+ pr_warn("%s. dc not present.\n", __func__);
+ return;
+ }
+ if (!batt_present) {
+ pr_warn("%s. battery not present.\n", __func__);
+ return;
+ }
+ if (!batt_temp_ok) {
+ pr_warn("%s. battery temperature not ok.\n", __func__);
+ return;
+ }
+ if (vbat_ov) {
+ pr_warn("%s. battery over voltage.\n", __func__);
+ return;
+ }
+ if (!batfet) {
+ pr_warn("%s. battery FET not closed.\n", __func__);
+ return;
+ }
+
+ chip->ext->start_charging(chip->ext->ctx);
+ chip->ext_charging = true;
+ chip->ext_charge_done = false;
+ /* Start BMS */
+ schedule_delayed_work(&chip->eoc_work, delay);
+ wake_lock(&chip->eoc_wake_lock);
+}
+
static void handle_dc_removal_insertion(struct pm8921_chg_chip *chip)
{
int dc_present;
@@ -1290,11 +1409,21 @@
status = pm_chg_get_rt_status(chip, BATT_INSERTED_IRQ);
schedule_work(&chip->battery_id_valid_work);
+ handle_start_ext_chg(chip);
pr_debug("battery present=%d", status);
power_supply_changed(&chip->batt_psy);
return IRQ_HANDLED;
}
-/* this interrupt used to restart charging a battery */
+
+/*
+ * this interrupt used to restart charging a battery.
+ *
+ * Note: When DC-inserted the VBAT can't go low.
+ * VPH_PWR is provided by the ext-charger.
+ * After End-Of-Charging from DC, charging can be resumed only
+ * if DC is removed and then inserted after the battery was in use.
+ * Therefore the handle_start_ext_chg() is not called.
+ */
static irqreturn_t vbatdet_low_irq_handler(int irq, void *data)
{
struct pm8921_chg_chip *chip = data;
@@ -1355,6 +1484,9 @@
struct pm8921_chg_chip *chip = data;
pr_debug("state_changed_to=%d\n", pm_chg_get_fsm_state(data));
+
+ handle_stop_ext_chg(chip);
+
power_supply_changed(&chip->batt_psy);
power_supply_changed(&chip->usb_psy);
power_supply_changed(&chip->dc_psy);
@@ -1432,6 +1564,7 @@
status = pm_chg_get_rt_status(chip, BATT_REMOVED_IRQ);
pr_debug("battery present=%d state=%d", !status,
pm_chg_get_fsm_state(data));
+ handle_stop_ext_chg(chip);
power_supply_changed(&chip->batt_psy);
return IRQ_HANDLED;
}
@@ -1440,6 +1573,7 @@
{
struct pm8921_chg_chip *chip = data;
+ handle_stop_ext_chg(chip);
power_supply_changed(&chip->batt_psy);
return IRQ_HANDLED;
}
@@ -1460,6 +1594,8 @@
struct pm8921_chg_chip *chip = data;
pr_debug("Batt cold fsm_state=%d\n", pm_chg_get_fsm_state(data));
+ handle_stop_ext_chg(chip);
+
power_supply_changed(&chip->batt_psy);
power_supply_changed(&chip->usb_psy);
power_supply_changed(&chip->dc_psy);
@@ -1482,6 +1618,8 @@
struct pm8921_chg_chip *chip = data;
pr_debug("batt temp ok fsm_state=%d\n", pm_chg_get_fsm_state(data));
+ handle_start_ext_chg(chip);
+
power_supply_changed(&chip->batt_psy);
power_supply_changed(&chip->usb_psy);
power_supply_changed(&chip->dc_psy);
@@ -1524,17 +1662,33 @@
static irqreturn_t dcin_valid_irq_handler(int irq, void *data)
{
- handle_dc_removal_insertion(data);
+ struct pm8921_chg_chip *chip = data;
+
+ pm8921_disable_source_current(true); /* Force BATFET=ON */
+
+ handle_dc_removal_insertion(chip);
+ handle_start_ext_chg(chip);
return IRQ_HANDLED;
}
static irqreturn_t dcin_ov_irq_handler(int irq, void *data)
{
+ struct pm8921_chg_chip *chip = data;
+
+ pm8921_disable_source_current(false); /* release BATFET */
+
+ handle_dc_removal_insertion(chip);
+ handle_stop_ext_chg(chip);
return IRQ_HANDLED;
}
static irqreturn_t dcin_uv_irq_handler(int irq, void *data)
{
+ struct pm8921_chg_chip *chip = data;
+
+ pm8921_disable_source_current(false); /* release BATFET */
+ handle_stop_ext_chg(chip);
+
return IRQ_HANDLED;
}
@@ -1556,7 +1710,7 @@
}
/**
- * eoc_work - internal function to check if battery EOC
+ * eoc_worker - internal function to check if battery EOC
* has happened
*
* If all conditions favouring, if the charge current is
@@ -1569,7 +1723,7 @@
#define CONSECUTIVE_COUNT 3
#define VBAT_TOLERANCE_MV 70
#define CHG_DISABLE_MSLEEP 100
-static void eoc_work(struct work_struct *work)
+static void eoc_worker(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct pm8921_chg_chip *chip = container_of(dwork,
@@ -1580,41 +1734,44 @@
int rc;
static int count;
- /* return if the battery is not being fastcharged */
- fast_chg = pm_chg_get_rt_status(chip, FASTCHG_IRQ);
- pr_debug("fast_chg = %d\n", fast_chg);
- if (fast_chg == 0) {
- /* enable fastchg irq */
- pm8921_chg_enable_irq(chip, FASTCHG_IRQ);
- count = 0;
- wake_unlock(&chip->eoc_wake_lock);
- return;
- }
+ if (!is_ext_charging(chip)) {
+ /* return if the battery is not being fastcharged */
+ fast_chg = pm_chg_get_rt_status(chip, FASTCHG_IRQ);
+ pr_debug("fast_chg = %d\n", fast_chg);
+ if (fast_chg == 0) {
+ /* enable fastchg irq */
+ pm8921_chg_enable_irq(chip, FASTCHG_IRQ);
+ count = 0;
+ wake_unlock(&chip->eoc_wake_lock);
+ return;
+ }
- vcp = pm_chg_get_rt_status(chip, VCP_IRQ);
- pr_debug("vcp = %d\n", vcp);
- if (vcp == 1)
- goto reset_and_reschedule;
+ vcp = pm_chg_get_rt_status(chip, VCP_IRQ);
+ pr_debug("vcp = %d\n", vcp);
+ if (vcp == 1)
+ goto reset_and_reschedule;
- /* reset count if battery is hot/cold */
- rc = pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ);
- pr_debug("batt_temp_ok = %d\n", rc);
- if (rc == 0)
- goto reset_and_reschedule;
+ /* reset count if battery is hot/cold */
+ rc = pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ);
+ pr_debug("batt_temp_ok = %d\n", rc);
+ if (rc == 0)
+ goto reset_and_reschedule;
- /* reset count if battery voltage is less than vddmax */
- vbat_meas = get_prop_battery_mvolts(chip);
- if (vbat_meas < 0)
- goto reset_and_reschedule;
+ /* reset count if battery voltage is less than vddmax */
+ vbat_meas = get_prop_battery_mvolts(chip);
+ if (vbat_meas < 0)
+ goto reset_and_reschedule;
- rc = pm_chg_vddmax_get(chip, &vbat_programmed);
- if (rc) {
- pr_err("couldnt read vddmax rc = %d\n", rc);
- goto reset_and_reschedule;
- }
- pr_debug("vddmax = %d vbat_meas=%d\n", vbat_programmed, vbat_meas);
- if (vbat_meas < vbat_programmed - VBAT_TOLERANCE_MV)
- goto reset_and_reschedule;
+ rc = pm_chg_vddmax_get(chip, &vbat_programmed);
+ if (rc) {
+ pr_err("couldnt read vddmax rc = %d\n", rc);
+ goto reset_and_reschedule;
+ }
+ pr_debug("vddmax = %d vbat_meas=%d\n",
+ vbat_programmed, vbat_meas);
+ if (vbat_meas < vbat_programmed - VBAT_TOLERANCE_MV)
+ goto reset_and_reschedule;
+ } /* !is_ext_charging */
/* reset count if battery chg current is more than iterm */
rc = pm_chg_iterm_get(chip, &iterm_programmed);
@@ -1636,20 +1793,22 @@
if (ichg_meas * -1 > iterm_programmed)
goto reset_and_reschedule;
- /*
- * TODO if charging from an external charger check SOC instead of
- * regulation loop
- */
- regulation_loop = pm_chg_get_regulation_loop(chip);
- if (regulation_loop < 0) {
- pr_err("couldnt read the regulation loop err=%d\n",
- regulation_loop);
- goto reset_and_reschedule;
- }
- pr_debug("regulation_loop=%d\n", regulation_loop);
+ if (!is_ext_charging(chip)) {
+ /*
+ * TODO if charging from an external charger
+ * check SOC instead of regulation loop
+ */
+ regulation_loop = pm_chg_get_regulation_loop(chip);
+ if (regulation_loop < 0) {
+ pr_err("couldnt read the regulation loop err=%d\n",
+ regulation_loop);
+ goto reset_and_reschedule;
+ }
+ pr_debug("regulation_loop=%d\n", regulation_loop);
- if (regulation_loop != 0 && regulation_loop != VDD_LOOP)
- goto reset_and_reschedule;
+ if (regulation_loop != 0 && regulation_loop != VDD_LOOP)
+ goto reset_and_reschedule;
+ } /* !is_ext_charging */
count++;
if (count == CONSECUTIVE_COUNT) {
@@ -1658,6 +1817,9 @@
pm_chg_auto_enable(chip, 0);
+ if (is_ext_charging(chip))
+ chip->ext_charge_done = true;
+
/* declare end of charging by invoking chgdone interrupt */
chgdone_irq_handler(chip->pmic_chg_irq[CHGDONE_IRQ], chip);
wake_unlock(&chip->eoc_wake_lock);
@@ -1738,6 +1900,36 @@
return rc;
}
+int register_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ if (the_chip == NULL) {
+ pr_err("called too early\n");
+ return -EINVAL;
+ }
+ /* TODO check function pointers */
+ the_chip->ext = ext;
+ the_chip->ext_charging = false;
+
+ if (is_dc_chg_plugged_in(the_chip))
+ pm8921_disable_source_current(true); /* Force BATFET=ON */
+
+ handle_start_ext_chg(the_chip);
+
+ return 0;
+}
+EXPORT_SYMBOL(register_external_dc_charger);
+
+void unregister_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ if (the_chip == NULL) {
+ pr_err("called too early\n");
+ return;
+ }
+ handle_stop_ext_chg(the_chip);
+ the_chip->ext = NULL;
+}
+EXPORT_SYMBOL(unregister_external_dc_charger);
+
/**
* set_disable_status_param -
*
@@ -2397,7 +2589,7 @@
the_chip = chip;
wake_lock_init(&chip->eoc_wake_lock, WAKE_LOCK_SUSPEND, "pm8921_eoc");
- INIT_DELAYED_WORK(&chip->eoc_work, eoc_work);
+ INIT_DELAYED_WORK(&chip->eoc_work, eoc_worker);
rc = request_irqs(chip, pdev);
if (rc) {
diff --git a/drivers/slimbus/slim-msm-ctrl.c b/drivers/slimbus/slim-msm-ctrl.c
index 1e4302b..937bfe7 100644
--- a/drivers/slimbus/slim-msm-ctrl.c
+++ b/drivers/slimbus/slim-msm-ctrl.c
@@ -21,6 +21,7 @@
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/clk.h>
+#include <linux/pm_runtime.h>
#include <mach/sps.h>
/* Per spec.max 40 bytes per received message */
@@ -44,6 +45,7 @@
#define MSM_SLIM_PERF_SUMM_THRESHOLD 0x8000
#define MSM_SLIM_NCHANS 32
#define MSM_SLIM_NPORTS 24
+#define MSM_SLIM_AUTOSUSPEND MSEC_PER_SEC
/*
* Need enough descriptors to receive present messages from slaves
@@ -184,6 +186,12 @@
REF_CLK_GEAR = 15,
};
+enum msm_ctrl_state {
+ MSM_CTRL_AWAKE,
+ MSM_CTRL_SLEEPING,
+ MSM_CTRL_ASLEEP,
+};
+
struct msm_slim_sps_bam {
u32 hdl;
void __iomem *base;
@@ -226,10 +234,11 @@
struct mutex tx_lock;
u8 pgdla;
bool use_rx_msgqs;
- int suspended;
int pipe_b;
struct completion reconf;
bool reconf_busy;
+ bool chan_active;
+ enum msm_ctrl_state state;
};
struct msm_slim_sat {
@@ -450,6 +459,11 @@
* before exiting ISR
*/
mb();
+ if (dev->ctrl.sched.usedslots == 0 &&
+ dev->state != MSM_CTRL_SLEEPING) {
+ dev->chan_active = false;
+ pm_runtime_put(dev->dev);
+ }
complete(&dev->reconf);
}
pstat = readl_relaxed(dev->base + PGD_PORT_INT_ST_EEn + (16 * dev->ee));
@@ -649,17 +663,36 @@
u8 *puc;
int timeout;
u8 la = txn->la;
+ /*
+ * Voting for runtime PM: Slimbus has 2 possible use cases:
+ * 1. messaging
+ * 2. Data channels
+ * Messaging case goes through messaging slots and data channels
+ * use their own slots
+ * This "get" votes for messaging bandwidth
+ */
+ if (dev->state != MSM_CTRL_SLEEPING)
+ pm_runtime_get_sync(dev->dev);
mutex_lock(&dev->tx_lock);
+ if (dev->state == MSM_CTRL_ASLEEP) {
+ dev_err(dev->dev, "runtime or system PM suspended state");
+ mutex_unlock(&dev->tx_lock);
+ pm_runtime_put(dev->dev);
+ return -EBUSY;
+ }
if (txn->mt == SLIM_MSG_MT_CORE &&
- txn->mc == SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
- dev->reconf_busy) {
+ txn->mc == SLIM_MSG_MC_BEGIN_RECONFIGURATION) {
+ if (dev->reconf_busy) {
wait_for_completion(&dev->reconf);
dev->reconf_busy = false;
- }
- if (dev->suspended) {
- dev_err(dev->dev, "No transaction in suspended state");
- mutex_unlock(&dev->tx_lock);
- return -EBUSY;
+ }
+ /* This "get" votes for data channels */
+ if (dev->ctrl.sched.usedslots != 0 &&
+ !dev->chan_active) {
+ dev->chan_active = true;
+ if (dev->state != MSM_CTRL_SLEEPING)
+ pm_runtime_get(dev->dev);
+ }
}
txn->rl--;
pbuf = msm_get_msg_buf(ctrl, txn->rl);
@@ -668,6 +701,8 @@
if (txn->dt == SLIM_MSG_DEST_ENUMADDR) {
mutex_unlock(&dev->tx_lock);
+ if (dev->state != MSM_CTRL_SLEEPING)
+ pm_runtime_put(dev->dev);
return -EPROTONOSUPPORT;
}
if (txn->mt == SLIM_MSG_MT_CORE && txn->la == 0xFF &&
@@ -715,11 +750,15 @@
*/
dev->pipes[*puc].connected = false;
mutex_unlock(&dev->tx_lock);
+ if (dev->state != MSM_CTRL_SLEEPING)
+ pm_runtime_put(dev->dev);
return 0;
}
if (dev->err) {
dev_err(dev->dev, "pipe-port connect err:%d", dev->err);
mutex_unlock(&dev->tx_lock);
+ if (dev->state != MSM_CTRL_SLEEPING)
+ pm_runtime_put(dev->dev);
return dev->err;
}
*(puc) = *(puc) + dev->pipe_b;
@@ -730,10 +769,22 @@
dev->wr_comp = &done;
msm_send_msg_buf(ctrl, pbuf, txn->rl);
timeout = wait_for_completion_timeout(&done, HZ);
+
+ if (dev->state == MSM_CTRL_SLEEPING &&
+ txn->mc == SLIM_MSG_MC_RECONFIGURE_NOW &&
+ txn->mt == SLIM_MSG_MT_CORE && timeout) {
+ timeout = wait_for_completion_timeout(&dev->reconf, HZ);
+ if (timeout)
+ dev->reconf_busy = false;
+ }
+ mutex_unlock(&dev->tx_lock);
+ if (!txn->rbuf && dev->state != MSM_CTRL_SLEEPING)
+ pm_runtime_put(dev->dev);
+
if (!timeout)
dev_err(dev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
txn->mt);
- mutex_unlock(&dev->tx_lock);
+
return timeout ? dev->err : -ETIMEDOUT;
}
@@ -763,6 +814,7 @@
static int msm_clk_pause_wakeup(struct slim_controller *ctrl)
{
struct msm_slim_ctrl *dev = slim_get_ctrldata(ctrl);
+ enable_irq(dev->irq);
clk_enable(dev->rclk);
writel_relaxed(1, dev->base + FRM_WAKEUP);
/* Make sure framer wakeup write goes through before exiting function */
@@ -913,6 +965,7 @@
u8 e_addr[6];
for (i = 0; i < 6; i++)
e_addr[i] = buf[7-i];
+ pm_runtime_get_sync(dev->dev);
ret = slim_assign_laddr(&dev->ctrl, e_addr, 6, &laddr);
/* Is this Qualcomm ported generic device? */
@@ -921,6 +974,7 @@
e_addr[1] == QC_DEVID_PGD &&
e_addr[2] != QC_CHIPID_SL)
dev->pgdla = laddr;
+ pm_runtime_put(dev->dev);
} else if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
mc == SLIM_MSG_MC_REPLY_VALUE) {
@@ -928,6 +982,7 @@
dev_dbg(dev->dev, "tid:%d, len:%d\n", tid, len - 4);
slim_msg_response(&dev->ctrl, &buf[4], tid,
len - 4);
+ pm_runtime_put(dev->dev);
} else if (mc == SLIM_MSG_MC_REPORT_INFORMATION) {
u8 l_addr = buf[2];
u16 ele = (u16)buf[4] << 4;
@@ -980,11 +1035,19 @@
for (i = 0; i < 6; i++)
e_addr[i] = buf[7-i];
+ pm_runtime_get_sync(dev->dev);
slim_assign_laddr(&dev->ctrl, e_addr, 6, &laddr);
sat->satcl.laddr = laddr;
- }
+ } else if (mt != SLIM_MSG_MT_CORE &&
+ mc != SLIM_MSG_MC_REPORT_PRESENT)
+ pm_runtime_get_sync(dev->dev);
switch (mc) {
case SLIM_MSG_MC_REPORT_PRESENT:
+ /* Remove runtime_pm vote once satellite acks */
+ if (mt != SLIM_MSG_MT_CORE) {
+ pm_runtime_put(dev->dev);
+ continue;
+ }
/* send a Manager capability msg */
if (sat->sent_capability)
continue;
@@ -1085,8 +1148,11 @@
default:
break;
}
- if (!gen_ack)
+ if (!gen_ack) {
+ if (mc != SLIM_MSG_MC_REPORT_PRESENT)
+ pm_runtime_put(dev->dev);
continue;
+ }
wbuf[0] = tid;
if (!ret)
wbuf[1] = MSM_SAT_SUCCSS;
@@ -1099,6 +1165,7 @@
txn.wbuf = wbuf;
txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
msm_xfer_msg(&dev->ctrl, &txn);
+ pm_runtime_put(dev->dev);
}
}
@@ -1702,6 +1769,10 @@
* function
*/
mb();
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_autosuspend_delay(&pdev->dev, MSM_SLIM_AUTOSUSPEND);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
dev_dbg(dev->dev, "MSM SB controller is up!\n");
return 0;
@@ -1735,12 +1806,13 @@
struct resource *slew_mem = dev->slew_mem;
struct msm_slim_sat *sat = dev->satd;
slim_remove_device(&sat->satcl);
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
kfree(sat->satch);
destroy_workqueue(sat->wq);
kfree(sat);
free_irq(dev->irq, dev);
slim_del_controller(&dev->ctrl);
- clk_disable(dev->rclk);
clk_put(dev->rclk);
msm_slim_sps_exit(dev);
kthread_stop(dev->rx_msgq_thread);
@@ -1760,79 +1832,91 @@
return 0;
}
-#ifdef CONFIG_PM
-static int msm_slim_suspend(struct device *device)
+#ifdef CONFIG_PM_RUNTIME
+static int msm_slim_runtime_idle(struct device *device)
{
struct platform_device *pdev = to_platform_device(device);
struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
- int ret = slim_ctrl_clk_pause(&dev->ctrl, false, SLIM_CLK_UNSPECIFIED);
+ dev_dbg(device, "pm_runtime: idle...\n");
+ pm_runtime_mark_last_busy(dev->dev);
+ pm_request_autosuspend(device);
+ return -EAGAIN;
+}
+#endif
+
+/*
+ * If PM_RUNTIME is not defined, these 2 functions become helper
+ * functions to be called from system suspend/resume. So they are not
+ * inside ifdef CONFIG_PM_RUNTIME
+ */
+static int msm_slim_runtime_suspend(struct device *device)
+{
+ struct platform_device *pdev = to_platform_device(device);
+ struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
+ int ret;
+ dev_dbg(device, "pm_runtime: suspending...\n");
+ dev->state = MSM_CTRL_SLEEPING;
+ ret = slim_ctrl_clk_pause(&dev->ctrl, false, SLIM_CLK_UNSPECIFIED);
/* Make sure clock pause goes through */
- mutex_lock(&dev->tx_lock);
- if (!ret && dev->reconf_busy) {
- wait_for_completion(&dev->reconf);
- dev->reconf_busy = false;
- }
- mutex_unlock(&dev->tx_lock);
if (!ret) {
clk_disable(dev->rclk);
disable_irq(dev->irq);
- dev->suspended = 1;
- } else if (ret == -EBUSY) {
+ dev->state = MSM_CTRL_ASLEEP;
+ } else
+ dev->state = MSM_CTRL_AWAKE;
+ return ret;
+}
+
+static int msm_slim_runtime_resume(struct device *device)
+{
+ struct platform_device *pdev = to_platform_device(device);
+ struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
+ int ret = 0;
+ dev_dbg(device, "pm_runtime: resuming...\n");
+ mutex_lock(&dev->tx_lock);
+ if (dev->state == MSM_CTRL_ASLEEP) {
+ mutex_unlock(&dev->tx_lock);
+ ret = slim_ctrl_clk_pause(&dev->ctrl, true, 0);
+ if (!ret)
+ dev->state = MSM_CTRL_AWAKE;
+ return ret;
+ }
+ mutex_unlock(&dev->tx_lock);
+ return ret;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int msm_slim_suspend(struct device *dev)
+{
+ int ret = 0;
+ if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
+ dev_dbg(dev, "system suspend");
+ ret = msm_slim_runtime_suspend(dev);
+ }
+ if (ret == -EBUSY) {
/*
- * If the clock pause failed due to active channels, there is
- * a possibility that some audio stream is active during suspend
- * We dont want to return suspend failure in that case so that
- * display and relevant components can still go to suspend.
- * If there is some other error, then it should be passed-on
- * to system level suspend
- */
+ * If the clock pause failed due to active channels, there is
+ * a possibility that some audio stream is active during suspend
+ * We dont want to return suspend failure in that case so that
+ * display and relevant components can still go to suspend.
+ * If there is some other error, then it should be passed-on
+ * to system level suspend
+ */
ret = 0;
}
return ret;
}
-static int msm_slim_resume(struct device *device)
+static int msm_slim_resume(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(device);
- struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
- mutex_lock(&dev->tx_lock);
- if (dev->suspended) {
- dev->suspended = 0;
- mutex_unlock(&dev->tx_lock);
- enable_irq(dev->irq);
- return slim_ctrl_clk_pause(&dev->ctrl, true, 0);
+ /* If runtime_pm is enabled, this resume shouldn't do anything */
+ if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
+ dev_dbg(dev, "system resume");
+ return msm_slim_runtime_resume(dev);
}
- mutex_unlock(&dev->tx_lock);
return 0;
}
-#else
-#define msm_slim_suspend NULL
-#define msm_slim_resume NULL
-#endif /* CONFIG_PM */
-
-#ifdef CONFIG_PM_RUNTIME
-static int msm_slim_runtime_idle(struct device *dev)
-{
- dev_dbg(dev, "pm_runtime: idle...\n");
- return 0;
-}
-
-static int msm_slim_runtime_suspend(struct device *dev)
-{
- dev_dbg(dev, "pm_runtime: suspending...\n");
- return 0;
-}
-
-static int msm_slim_runtime_resume(struct device *dev)
-{
- dev_dbg(dev, "pm_runtime: resuming...\n");
- return 0;
-}
-#else
-#define msm_slim_runtime_idle NULL
-#define msm_slim_runtime_suspend NULL
-#define msm_slim_runtime_resume NULL
-#endif
+#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops msm_slim_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(
diff --git a/drivers/thermal/msm_tsens.c b/drivers/thermal/msm_tsens.c
index f4e094e..d9a6efc 100644
--- a/drivers/thermal/msm_tsens.c
+++ b/drivers/thermal/msm_tsens.c
@@ -24,6 +24,7 @@
#include <linux/io.h>
#include <mach/msm_iomap.h>
+#include <linux/pm.h>
/* Trips: from very hot to very cold */
enum tsens_trip_type {
@@ -88,6 +89,7 @@
bool prev_reading_avail;
int offset;
struct work_struct work;
+ uint32_t pm_tsens_thr_data;
};
struct tsens_tm_device *tmdev;
@@ -471,9 +473,6 @@
if (lower_th_x)
mask |= TSENS_LOWER_STATUS_CLR;
if (upper_th_x || lower_th_x) {
- thermal_zone_device_update(
- tm->sensor[i].tz_dev);
-
/* Notify user space */
schedule_work(&tm->work);
adc_code = readl(TSENS_S0_STATUS_ADDR
@@ -490,6 +489,53 @@
return IRQ_HANDLED;
}
+#ifdef CONFIG_PM
+static int tsens_suspend(struct device *dev)
+{
+ unsigned int reg;
+
+ tmdev->pm_tsens_thr_data = readl_relaxed(TSENS_THRESHOLD_ADDR);
+ reg = readl_relaxed(TSENS_CNTL_ADDR);
+ writel_relaxed(reg & ~(TSENS_SLP_CLK_ENA | TSENS_EN), TSENS_CNTL_ADDR);
+ tmdev->prev_reading_avail = 0;
+
+ disable_irq_nosync(TSENS_UPPER_LOWER_INT);
+ mb();
+ return 0;
+}
+
+static int tsens_resume(struct device *dev)
+{
+ unsigned int reg;
+
+ reg = readl_relaxed(TSENS_CNTL_ADDR);
+ writel_relaxed(reg | TSENS_SW_RST, TSENS_CNTL_ADDR);
+ reg |= TSENS_SLP_CLK_ENA | TSENS_EN | (TSENS_MEASURE_PERIOD << 16) |
+ TSENS_LOWER_STATUS_CLR | TSENS_UPPER_STATUS_CLR |
+ TSENS_MIN_STATUS_MASK | TSENS_MAX_STATUS_MASK |
+ (((1 << TSENS_NUM_SENSORS) - 1) << 3);
+
+ reg = (reg & ~TSENS_CONFIG_MASK) | (TSENS_CONFIG << TSENS_CONFIG_SHIFT);
+ writel_relaxed(reg, TSENS_CNTL_ADDR);
+
+ if (tmdev->sensor->mode == THERMAL_DEVICE_DISABLED) {
+ writel_relaxed(reg & ~((((1 << TSENS_NUM_SENSORS) - 1) << 3)
+ | TSENS_SLP_CLK_ENA | TSENS_EN), TSENS_CNTL_ADDR);
+ }
+
+ writel_relaxed(tmdev->pm_tsens_thr_data, TSENS_THRESHOLD_ADDR);
+
+ enable_irq(TSENS_UPPER_LOWER_INT);
+ mb();
+ return 0;
+}
+
+static const struct dev_pm_ops tsens_pm_ops = {
+ .suspend = tsens_suspend,
+ .resume = tsens_resume,
+};
+#endif
+
static int __devinit tsens_tm_probe(struct platform_device *pdev)
{
unsigned int reg, i, calib_data, calib_data_backup;
@@ -555,7 +601,6 @@
return -ENODEV;
}
tmdev->sensor[i].sensor_num = i;
- thermal_zone_device_update(tmdev->sensor[i].tz_dev);
tmdev->sensor[i].mode = THERMAL_DEVICE_DISABLED;
}
@@ -596,6 +641,9 @@
.driver = {
.name = "tsens-tm",
.owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &tsens_pm_ops,
+#endif
},
};
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 9d268d1..7dc7377 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1405,8 +1405,15 @@
mEp = &udc->ci13xxx_ep[ep_num];
n = hw_ep_bit(mEp->num, mEp->dir);
+ pr_info("%s: prime:%08x stat:%08x ep#%d dir:%s"
+ "dTD_update_fail_count: %lu"
+ "mEp->dTD_update_fail_count: %lu\n", __func__,
+ hw_cread(CAP_ENDPTPRIME, ~0),
+ hw_cread(CAP_ENDPTSTAT, ~0),
+ mEp->num, mEp->dir ? "IN" : "OUT",
+ udc->dTD_update_fail_count,
+ mEp->dTD_update_fail_count);
- pr_info("ep#%d dir:%s\n", mEp->num, mEp->dir ? "IN" : "OUT");
pr_info("QH: cap:%08x cur:%08x next:%08x token:%08x\n",
mEp->qh.ptr->cap, mEp->qh.ptr->curr,
mEp->qh.ptr->td.next, mEp->qh.ptr->td.token);
@@ -2017,17 +2024,35 @@
struct ci13xxx_req *mReq, *mReqTemp;
struct ci13xxx_ep *mEpTemp = mEp;
int uninitialized_var(retval);
+ int req_dequeue = 1;
+ struct ci13xxx *udc = _udc;
trace("%p", mEp);
if (list_empty(&mEp->qh.queue))
- return -EINVAL;
+ return 0;
list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
queue) {
+dequeue:
retval = _hardware_dequeue(mEp, mReq);
- if (retval < 0)
+ if (retval < 0) {
+ /*
+ * FIXME: don't know exact delay
+ * required for HW to update dTD status
+ * bits. This is a temporary workaround till
+ * HW designers come back on this.
+ */
+ if (retval == -EBUSY && req_dequeue && mEp->dir == 0) {
+ req_dequeue = 0;
+ udc->dTD_update_fail_count++;
+ mEp->dTD_update_fail_count++;
+ udelay(10);
+ goto dequeue;
+ }
break;
+ }
+ req_dequeue = 0;
list_del_init(&mReq->queue);
dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
if (mReq->req.complete != NULL) {
diff --git a/drivers/usb/gadget/ci13xxx_udc.h b/drivers/usb/gadget/ci13xxx_udc.h
index c37a717..b917fe9 100644
--- a/drivers/usb/gadget/ci13xxx_udc.h
+++ b/drivers/usb/gadget/ci13xxx_udc.h
@@ -98,6 +98,7 @@
spinlock_t *lock;
struct device *device;
struct dma_pool *td_pool;
+ unsigned long dTD_update_fail_count;
};
struct ci13xxx;
@@ -139,6 +140,7 @@
int vbus_active; /* is VBUS active */
int softconnect; /* is pull-up enable allowed */
struct otg_transceiver *transceiver; /* Transceiver struct */
+ unsigned long dTD_update_fail_count;
};
/******************************************************************************
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 936b5d4..ca3c079 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -1442,6 +1442,10 @@
}
#endif
+ if (mdp_rev >= MDP_REV_40)
+ mfd->cursor_update = mdp_hw_cursor_sync_update;
+ else
+ mfd->cursor_update = mdp_hw_cursor_update;
break;
case MIPI_CMD_PANEL:
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index d2a2cf8..590fd13 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -680,7 +680,16 @@
#endif
int mdp_hw_cursor_update(struct fb_info *info, struct fb_cursor *cursor);
+#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDP40)
int mdp_hw_cursor_sync_update(struct fb_info *info, struct fb_cursor *cursor);
+#else
+static inline int mdp_hw_cursor_sync_update(struct fb_info *info,
+ struct fb_cursor *cursor)
+{
+ return 0;
+}
+#endif
+
void mdp_enable_irq(uint32 term);
void mdp_disable_irq(uint32 term);
void mdp_disable_irq_nosync(uint32 term);
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index ef3092b..f60cb78 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -427,6 +427,10 @@
int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req);
int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req);
int mdp4_overlay_unset(struct fb_info *info, int ndx);
+void mdp4_overlay_dtv_wait_for_ov(struct msm_fb_data_type *mfd,
+ struct mdp4_overlay_pipe *pipe);
+int mdp4_overlay_play_wait(struct fb_info *info,
+ struct msmfb_overlay_data *req);
int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req,
struct file **pp_src_file, struct file **pp_src_plane1_file,
struct file **pp_src_plane2_file);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index 1b2dec4..f865edf 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -2262,6 +2262,29 @@
return ((row_num_w * row_num_h * tile_w * tile_h) + 8191) & ~8191;
}
+int mdp4_overlay_play_wait(struct fb_info *info, struct msmfb_overlay_data *req)
+{
+ struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
+ struct mdp4_overlay_pipe *pipe;
+
+ if (mfd == NULL)
+ return -ENODEV;
+
+ if (!mfd->panel_power_on) /* suspended */
+ return -EPERM;
+
+ pipe = mdp4_overlay_ndx2pipe(req->id);
+
+ if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
+ return -EINTR;
+
+ mdp4_overlay_dtv_wait_for_ov(mfd, pipe);
+
+ mutex_unlock(&mfd->dma->ov_mutex);
+
+ return 0;
+}
+
int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req,
struct file **pp_src_file, struct file **pp_src_plane1_file,
struct file **pp_src_plane2_file)
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index a8ace6b..a9b32ab 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -334,7 +334,7 @@
mdp4_set_perf_level();
}
-static void mdp4_overlay_dtv_wait4_ov_done(struct msm_fb_data_type *mfd)
+static void mdp4_overlay_dtv_ov_start(struct msm_fb_data_type *mfd)
{
unsigned long flag;
@@ -347,6 +347,18 @@
mdp_intr_mask |= INTR_OVERLAY1_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
+ mfd->ov_start = true;
+}
+
+static void mdp4_overlay_dtv_wait4_ov_done(struct msm_fb_data_type *mfd,
+ struct mdp4_overlay_pipe *pipe)
+{
+ u32 data = inpdw(MDP_BASE + DTV_BASE);
+
+ mfd->ov_start = false;
+
+ if (!(data & 0x1) || (pipe == NULL))
+ return;
wait_for_completion_killable(&dtv_pipe->comp);
mdp_disable_irq(MDP_OVERLAY1_TERM);
}
@@ -356,15 +368,28 @@
{
mdp4_overlay_reg_flush(pipe, 1);
+ mdp4_overlay_dtv_ov_start(mfd);
+
if (pipe->flags & MDP_OV_PLAY_NOWAIT)
return;
- mdp4_overlay_dtv_wait4_ov_done(mfd);
+ mdp4_overlay_dtv_wait4_ov_done(mfd, pipe);
/* change mdp clk while mdp is idle` */
mdp4_set_perf_level();
}
+void mdp4_overlay_dtv_wait_for_ov(struct msm_fb_data_type *mfd,
+ struct mdp4_overlay_pipe *pipe)
+{
+ if (mfd->ov_end) {
+ mfd->ov_end = false;
+ return;
+ }
+ mdp4_overlay_dtv_wait4_ov_done(mfd, pipe);
+ mdp4_set_perf_level();
+}
+
void mdp4_external_vsync_dtv()
{
complete(&dtv_pipe->comp);
@@ -413,7 +438,6 @@
struct fb_info *fbi = mfd->fbi;
uint8 *buf;
int bpp;
- unsigned long flag;
struct mdp4_overlay_pipe *pipe;
if (!mfd->panel_power_on)
@@ -430,19 +454,12 @@
pipe = dtv_pipe;
pipe->srcp0_addr = (uint32) buf;
mdp4_overlay_rgb_setup(pipe);
- mdp4_overlay_reg_flush(pipe, 1); /* rgb2 and mixer1 */
- /* enable irq */
- spin_lock_irqsave(&mdp_spin_lock, flag);
- mdp_enable_irq(MDP_OVERLAY1_TERM);
- INIT_COMPLETION(dtv_pipe->comp);
- mfd->dma->waiting = TRUE;
- outp32(MDP_INTR_CLEAR, INTR_OVERLAY1_DONE);
- mdp_intr_mask |= INTR_OVERLAY1_DONE;
- outp32(MDP_INTR_ENABLE, mdp_intr_mask);
- spin_unlock_irqrestore(&mdp_spin_lock, flag);
- wait_for_completion_killable(&dtv_pipe->comp);
- mdp_disable_irq(MDP_OVERLAY1_TERM);
+ if (mfd->ov_start) {
+ mdp4_overlay_dtv_wait4_ov_done(mfd, pipe);
+ mfd->ov_end = true;
+ }
+ mdp4_overlay_dtv_ov_done_push(mfd, pipe);
mdp4_stat.kickoff_dtv++;
mutex_unlock(&mfd->dma->ov_mutex);
diff --git a/drivers/video/msm/mipi_dsi_host.c b/drivers/video/msm/mipi_dsi_host.c
index 9caa154..600aac5 100644
--- a/drivers/video/msm/mipi_dsi_host.c
+++ b/drivers/video/msm/mipi_dsi_host.c
@@ -1159,7 +1159,7 @@
struct dsi_buf *tp, struct dsi_buf *rp,
struct dsi_cmd_desc *cmds, int rlen)
{
- int cnt, len, diff, pkt_size;
+ int i , cnt, len, diff, pkt_size;
unsigned long flag;
char cmd;
@@ -1172,8 +1172,7 @@
len = mfd->panel_info.mipi.fixed_packet_size;
pkt_size = len; /* Avoid command to the device */
cnt = (len + 6 + 3) & ~0x03; /* Add padding for align */
- }
- else {
+ } else {
if (len > MIPI_DSI_LEN)
len = MIPI_DSI_LEN; /* 8 bytes at most */
@@ -1204,12 +1203,14 @@
dsi_mdp_busy = TRUE;
spin_unlock_irqrestore(&dsi_mdp_lock, flag);
- /* packet size need to be set at every read */
- pkt_size = len;
- max_pktsize[0] = pkt_size;
- mipi_dsi_buf_init(tp);
- mipi_dsi_cmd_dma_add(tp, pkt_size_cmd);
- mipi_dsi_cmd_dma_tx(tp);
+ if (!mfd->panel_info.mipi.fixed_packet_size) {
+ /* packet size need to be set at every read */
+ pkt_size = len;
+ max_pktsize[0] = pkt_size;
+ mipi_dsi_buf_init(tp);
+ mipi_dsi_cmd_dma_add(tp, pkt_size_cmd);
+ mipi_dsi_cmd_dma_tx(tp);
+ }
mipi_dsi_buf_init(tp);
mipi_dsi_cmd_dma_add(tp, cmds);
@@ -1224,12 +1225,22 @@
mipi_dsi_buf_init(rp);
mipi_dsi_cmd_dma_rx(rp, cnt);
+ for (i = 0; i < cnt ; i++)
+ pr_debug("%s.rp->data[%d]=0x%x.\n", __func__, i, rp->data[i]);
+
spin_lock_irqsave(&dsi_mdp_lock, flag);
dsi_mdp_busy = FALSE;
mipi_dsi_disable_irq();
complete(&dsi_mdp_comp);
spin_unlock_irqrestore(&dsi_mdp_lock, flag);
+ /* Remove leading padding zeros if exist */
+ for (i = 0; i < cnt ; i++)
+ if (rp->data[0] == 0)
+ rp->data++;
+ else
+ break;
+
cmd = rp->data[0];
switch (cmd) {
case DTYPE_ACK_ERR_RESP:
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index 94c38ff..b3d5573 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -2501,6 +2501,26 @@
return mdp4_overlay_unset(info, ndx);
}
+static int msmfb_overlay_play_wait(struct fb_info *info, unsigned long *argp)
+{
+ int ret;
+ struct msmfb_overlay_data req;
+ struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
+
+ if (mfd->overlay_play_enable == 0) /* nothing to do */
+ return 0;
+
+ ret = copy_from_user(&req, argp, sizeof(req));
+ if (ret) {
+ pr_err("%s:msmfb_overlay_wait ioctl failed", __func__);
+ return ret;
+ }
+
+ ret = mdp4_overlay_play_wait(info, &req);
+
+ return ret;
+}
+
static int msmfb_overlay_play(struct fb_info *info, unsigned long *argp)
{
int ret;
@@ -2764,6 +2784,11 @@
ret = msmfb_overlay_play_enable(info, argp);
up(&msm_fb_ioctl_ppp_sem);
break;
+ case MSMFB_OVERLAY_PLAY_WAIT:
+ down(&msm_fb_ioctl_ppp_sem);
+ ret = msmfb_overlay_play_wait(info, argp);
+ up(&msm_fb_ioctl_ppp_sem);
+ break;
case MSMFB_OVERLAY_BLT:
down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_blt(info, argp);
diff --git a/drivers/video/msm/msm_fb.h b/drivers/video/msm/msm_fb.h
index bdf32eb..43802a2 100644
--- a/drivers/video/msm/msm_fb.h
+++ b/drivers/video/msm/msm_fb.h
@@ -150,6 +150,7 @@
struct timer_list msmfb_no_update_notify_timer;
struct completion msmfb_update_notify;
struct completion msmfb_no_update_notify;
+ u32 ov_start, ov_end;
};
struct dentry *msm_fb_get_debugfs_root(void);
diff --git a/include/linux/leds-pm8xxx.h b/include/linux/leds-pm8xxx.h
index edd3c28..3f31498 100644
--- a/include/linux/leds-pm8xxx.h
+++ b/include/linux/leds-pm8xxx.h
@@ -14,6 +14,7 @@
#define __LEDS_PM8XXX_H__
#include <linux/kernel.h>
+#include <linux/mfd/pm8xxx/pwm.h>
#define PM8XXX_LEDS_DEV_NAME "pm8xxx-led"
@@ -51,24 +52,30 @@
/**
* pm8xxx_led_config - led configuration parameters
- * id - LED id
- * mode - LED mode
- * max_current - maximum current that LED can sustain
+ * @id - LED id
+ * @mode - LED mode
+ * @max_current - maximum current that LED can sustain
+ * @pwm_channel - PWM channel ID the LED is driven to
+ * @pwm_period_us - PWM period value in micro seconds
+ * @pwm_duty_cycles - PWM duty cycle information
*/
struct pm8xxx_led_config {
u8 id;
u8 mode;
u16 max_current;
+ int pwm_channel;
+ u32 pwm_period_us;
+ struct pm8xxx_pwm_duty_cycles *pwm_duty_cycles;
};
/**
* pm8xxx_led_platform_data - platform data for LED
- * led_core - array of LEDs. Each datum in array contains
+ * @led_core - array of LEDs. Each datum in array contains
* core data for the LED
- * configs - array of platform configuration parameters
+ * @configs - array of platform configuration parameters
* for each LED. It maps one-to-one with
* array of LEDs
- * num_configs - count of members of configs array
+ * @num_configs - count of members of configs array
*/
struct pm8xxx_led_platform_data {
struct led_platform_data *led_core;
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index 9f98656..aeb88b2 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -119,6 +119,26 @@
PM8921_CHG_SRC_DC,
};
+/**
+ * struct ext_chg_pm8921 -
+ * @name: name of the external charger
+ * @ctx: client context.
+ * @start_charging: callback to start charging. Can be called from an
+ * interrupt context
+ * @stop_charging: callback to stop charging. Can be called from an
+ * interrupt context
+ * @is_trickle: callback to check if trickle charging.
+ * Can be called from an interrupt context
+ *
+ */
+struct ext_chg_pm8921 {
+ const char *name;
+ void *ctx;
+ int (*start_charging) (void *ctx);
+ int (*stop_charging) (void *ctx);
+ bool (*is_trickle) (void *ctx);
+};
+
#if defined(CONFIG_PM8921_CHARGER) || defined(CONFIG_PM8921_CHARGER_MODULE)
void pm8921_charger_vbus_draw(unsigned int mA);
int pm8921_charger_register_vbus_sn(void (*callback)(int));
@@ -190,6 +210,28 @@
*
*/
int pm8921_batt_temperature(void);
+/**
+ * register_external_dc_charger -
+ * @ext: The structure representing an external charger
+ *
+ * RETURNS: Negative error code is there was a problem. Zero for sucess
+ *
+ * The charger callbacks might be called even before this function
+ * completes. The external charger driver should be ready to handle
+ * it.
+ */
+int register_external_dc_charger(struct ext_chg_pm8921 *ext);
+
+/**
+ * unregister_external_dc_charger -
+ * @ext: The structure representing an external charger
+ *
+ * The charger callbacks might be called even before this function
+ * completes. The external charger driver should be ready to handle
+ * it.
+ */
+void unregister_external_dc_charger(struct ext_chg_pm8921 *ext);
+
#else
static inline void pm8921_charger_vbus_draw(unsigned int mA)
{
@@ -238,6 +280,15 @@
{
return -ENXIO;
}
+static inline int register_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ pr_err("%s.not implemented.\n", __func__);
+ return -ENODEV;
+}
+static inline void unregister_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ pr_err("%s.not implemented.\n", __func__);
+}
#endif
#endif
diff --git a/include/linux/mfd/pm8xxx/pwm.h b/include/linux/mfd/pm8xxx/pwm.h
index b15645d..be3ec65 100644
--- a/include/linux/mfd/pm8xxx/pwm.h
+++ b/include/linux/mfd/pm8xxx/pwm.h
@@ -78,6 +78,20 @@
};
/**
+ * struct pm8xxx_pwm_duty_cycles - PWM duty cycle info
+ * duty_pcts - pointer to an array of duty percentage for a pwm period
+ * num_duty_pcts - total entries in duty_pcts array
+ * duty_ms - duty cycle time in ms
+ * start_idx - index in the LUT
+ */
+struct pm8xxx_pwm_duty_cycles {
+ int *duty_pcts;
+ int num_duty_pcts;
+ int duty_ms;
+ int start_idx;
+};
+
+/**
* pm8xxx_pwm_config_period - change PWM period
*
* @pwm: the PWM device
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index a739761..ac18939 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -52,7 +52,8 @@
#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
struct msmfb_mixer_info_req)
-
+#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
+ struct msmfb_overlay_data)
#define FB_TYPE_3D_PANEL 0x10101010
#define MDP_IMGTYPE2_START 0x10000
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index e64f4c6..3cd86ea 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -68,18 +68,18 @@
#define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3])
-enum {
- TCP_FLAG_CWR = __cpu_to_be32(0x00800000),
- TCP_FLAG_ECE = __cpu_to_be32(0x00400000),
- TCP_FLAG_URG = __cpu_to_be32(0x00200000),
- TCP_FLAG_ACK = __cpu_to_be32(0x00100000),
- TCP_FLAG_PSH = __cpu_to_be32(0x00080000),
- TCP_FLAG_RST = __cpu_to_be32(0x00040000),
- TCP_FLAG_SYN = __cpu_to_be32(0x00020000),
- TCP_FLAG_FIN = __cpu_to_be32(0x00010000),
- TCP_RESERVED_BITS = __cpu_to_be32(0x0F000000),
- TCP_DATA_OFFSET = __cpu_to_be32(0xF0000000)
-};
+enum {
+ TCP_FLAG_CWR = __constant_htonl(0x00800000),
+ TCP_FLAG_ECE = __constant_htonl(0x00400000),
+ TCP_FLAG_URG = __constant_htonl(0x00200000),
+ TCP_FLAG_ACK = __constant_htonl(0x00100000),
+ TCP_FLAG_PSH = __constant_htonl(0x00080000),
+ TCP_FLAG_RST = __constant_htonl(0x00040000),
+ TCP_FLAG_SYN = __constant_htonl(0x00020000),
+ TCP_FLAG_FIN = __constant_htonl(0x00010000),
+ TCP_RESERVED_BITS = __constant_htonl(0x0F000000),
+ TCP_DATA_OFFSET = __constant_htonl(0xF0000000)
+};
/*
* TCP general constants
@@ -134,6 +134,7 @@
__u8 tcpi_backoff;
__u8 tcpi_options;
__u8 tcpi_snd_wscale : 4, tcpi_rcv_wscale : 4;
+ __u8 tcpi_count;
__u32 tcpi_rto;
__u32 tcpi_ato;
diff --git a/include/media/msm_isp.h b/include/media/msm_isp.h
index b7fd30f..d4fe4ca 100644
--- a/include/media/msm_isp.h
+++ b/include/media/msm_isp.h
@@ -165,6 +165,12 @@
#define VFE_CMD_CLF_CHROMA_UPDATE 119
#define VFE_CMD_PCA_ROLL_OFF_CFG 120
#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
+#define VFE_CMD_GET_REG_DUMP 122
+#define VFE_CMD_GET_LINEARIZATON_TABLE 123
+#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
+#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
+#define VFE_CMD_GET_RGB_G_TABLE 126
+#define VFE_CMD_GET_LA_TABLE 127
struct msm_isp_cmd {
int32_t id;
diff --git a/include/net/bluetooth/amp.h b/include/net/bluetooth/amp.h
index 4b08079..53fea37 100644
--- a/include/net/bluetooth/amp.h
+++ b/include/net/bluetooth/amp.h
@@ -16,7 +16,7 @@
/* AMP defaults */
-#define A2MP_RSP_TIMEOUT (20000) /* 20 seconds */
+#define A2MP_RSP_TIMEOUT (8000) /* 8 seconds */
/* A2MP Protocol */
diff --git a/include/sound/apr_audio.h b/include/sound/apr_audio.h
index 0c109ae..d2a7dba 100644
--- a/include/sound/apr_audio.h
+++ b/include/sound/apr_audio.h
@@ -847,7 +847,7 @@
#define ADPCM 0x00010BE7
#define YADPCM 0x00010BE8
#define MP3 0x00010BE9
-#define MPEG4_AAC 0x00010D86
+#define MPEG4_AAC 0x00010BEA
#define AMRNB_FS 0x00010BEB
#define V13K_FS 0x00010BED
#define EVRC_FS 0x00010BEE
@@ -862,6 +862,7 @@
#define G711_ALAW_FS 0x00010BF7
#define G711_MLAW_FS 0x00010BF8
#define G711_PCM_FS 0x00010BF9
+#define MPEG4_MULTI_AAC 0x00010D86
#define ASM_ENCDEC_SBCRATE 0x00010C13
#define ASM_ENCDEC_IMMDIATE_DECODE 0x00010C14
diff --git a/include/sound/q6asm.h b/include/sound/q6asm.h
index bad9be7..fc7e521 100644
--- a/include/sound/q6asm.h
+++ b/include/sound/q6asm.h
@@ -38,6 +38,7 @@
#define FORMAT_WMA_V10PRO 0x000e
#define FORMAT_WMA_V9 0x000f
#define FORMAT_AMR_WB_PLUS 0x0010
+#define FORMAT_MPEG4_MULTI_AAC 0x0011
#define ENCDEC_SBCBITRATE 0x0001
#define ENCDEC_IMMEDIATE_DECODE 0x0002
@@ -241,6 +242,9 @@
int q6asm_media_format_block_aac(struct audio_client *ac,
struct asm_aac_cfg *cfg);
+int q6asm_media_format_block_multi_aac(struct audio_client *ac,
+ struct asm_aac_cfg *cfg);
+
int q6asm_media_format_block_wma(struct audio_client *ac,
void *cfg);
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index c21eb88..7ca920e 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -738,8 +738,10 @@
if (l2cap_check_security(sk) && __l2cap_no_conn_pending(sk)) {
l2cap_pi(sk)->conf_state |= L2CAP_CONF_CONNECT_PEND;
- if (l2cap_pi(sk)->amp_pref == BT_AMP_POLICY_PREFER_AMP)
- amp_create_physical(l2cap_pi(sk)->conn, sk);
+ if (l2cap_pi(sk)->amp_pref ==
+ BT_AMP_POLICY_PREFER_AMP &&
+ conn->fc_mask & L2CAP_FC_A2MP)
+ amp_create_physical(conn, sk);
else
l2cap_send_conn_req(sk);
}
@@ -843,8 +845,10 @@
l2cap_pi(sk)->conf_state |= L2CAP_CONF_CONNECT_PEND;
- if (l2cap_pi(sk)->amp_pref == BT_AMP_POLICY_PREFER_AMP)
- amp_create_physical(l2cap_pi(sk)->conn, sk);
+ if (l2cap_pi(sk)->amp_pref ==
+ BT_AMP_POLICY_PREFER_AMP &&
+ conn->fc_mask & L2CAP_FC_A2MP)
+ amp_create_physical(conn, sk);
else
l2cap_send_conn_req(sk);
diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c
index 7694764..361c984 100644
--- a/net/bluetooth/l2cap_sock.c
+++ b/net/bluetooth/l2cap_sock.c
@@ -761,8 +761,7 @@
BT_DBG("BT_AMP_POLICY now %d", opt);
if ((sk->sk_state == BT_CONNECTED) &&
- (l2cap_pi(sk)->amp_move_role == L2CAP_AMP_MOVE_NONE) &&
- (l2cap_pi(sk)->conn->fc_mask & L2CAP_FC_A2MP))
+ (l2cap_pi(sk)->amp_move_role == L2CAP_AMP_MOVE_NONE))
l2cap_amp_move_init(sk);
break;
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index f2d9813..e5f1113 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -2504,6 +2504,15 @@
info->tcpi_rcv_space = tp->rcvq_space.space;
info->tcpi_total_retrans = tp->total_retrans;
+
+ /*
+ * Expose reference count for socket.
+ */
+ if (NULL != sk->sk_socket) {
+ struct file *filep = sk->sk_socket->file;
+ if (NULL != filep)
+ info->tcpi_count = atomic_read(&filep->f_count);
+ }
}
EXPORT_SYMBOL_GPL(tcp_get_info);
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 649f219..620822c 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -1764,28 +1764,40 @@
{"RX1 MIX1 INP2", "IIR1", "IIR1"},
{"RX2 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX2 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX2 MIX1 INP1", "IIR1", "IIR1"},
{"RX2 MIX1 INP2", "RX1", "SLIM RX1"},
{"RX2 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX2 MIX1 INP2", "IIR1", "IIR1"},
{"RX3 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX3 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX3 MIX1 INP1", "IIR1", "IIR1"},
{"RX3 MIX1 INP2", "RX1", "SLIM RX1"},
{"RX3 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX3 MIX1 INP2", "IIR1", "IIR1"},
{"RX4 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX4 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX4 MIX1 INP1", "IIR1", "IIR1"},
{"RX4 MIX1 INP2", "RX1", "SLIM RX1"},
{"RX4 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX4 MIX1 INP2", "IIR1", "IIR1"},
{"RX5 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX5 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX5 MIX1 INP1", "IIR1", "IIR1"},
{"RX5 MIX1 INP2", "RX1", "SLIM RX1"},
{"RX5 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX5 MIX1 INP2", "IIR1", "IIR1"},
{"RX6 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX6 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX6 MIX1 INP1", "IIR1", "IIR1"},
{"RX6 MIX1 INP2", "RX1", "SLIM RX1"},
{"RX6 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX6 MIX1 INP2", "IIR1", "IIR1"},
{"RX7 MIX1 INP1", "RX1", "SLIM RX1"},
{"RX7 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX7 MIX1 INP1", "IIR1", "IIR1"},
{"RX7 MIX1 INP2", "RX1", "SLIM RX1"},
{"RX7 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX7 MIX1 INP2", "IIR1", "IIR1"},
/* Decimator Inputs */
{"DEC1 MUX", "DMIC1", "DMIC1"},
@@ -1825,7 +1837,16 @@
{"ADC6", NULL, "AMIC6"},
{"IIR1", NULL, "IIR1 INP1 MUX"},
+ {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
+ {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
+ {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"},
+ {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"},
+ {"IIR1 INP1 MUX", "DEC5", "DEC5 MUX"},
{"IIR1 INP1 MUX", "DEC6", "DEC6 MUX"},
+ {"IIR1 INP1 MUX", "DEC7", "DEC7 MUX"},
+ {"IIR1 INP1 MUX", "DEC8", "DEC8 MUX"},
+ {"IIR1 INP1 MUX", "DEC9", "DEC9 MUX"},
+ {"IIR1 INP1 MUX", "DEC10", "DEC10 MUX"},
{"MIC BIAS1 Internal1", NULL, "LDO_H"},
{"MIC BIAS1 Internal2", NULL, "LDO_H"},
diff --git a/sound/soc/msm/msm-dai-fe.c b/sound/soc/msm/msm-dai-fe.c
index 8970400..2ad7f3e 100644
--- a/sound/soc/msm/msm-dai-fe.c
+++ b/sound/soc/msm/msm-dai-fe.c
@@ -21,6 +21,31 @@
static struct snd_soc_dai_ops msm_fe_dai_ops = {};
+/* Conventional and unconventional sample rate supported */
+static unsigned int supported_sample_rates[] = {
+ 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
+};
+
+static struct snd_pcm_hw_constraint_list constraints_sample_rates = {
+ .count = ARRAY_SIZE(supported_sample_rates),
+ .list = supported_sample_rates,
+ .mask = 0,
+};
+
+static int multimedia_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &constraints_sample_rates);
+
+ return 0;
+}
+
+static struct snd_soc_dai_ops msm_fe_Multimedia_dai_ops = {
+ .startup = multimedia_startup,
+};
+
static struct snd_soc_dai_driver msm_fe_dais[] = {
{
.playback = {
@@ -113,14 +138,15 @@
{
.playback = {
.stream_name = "MultiMedia3 Playback",
- .rates = SNDRV_PCM_RATE_8000_48000,
+ .rates = (SNDRV_PCM_RATE_8000_48000 |
+ SNDRV_PCM_RATE_KNOT),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
- .ops = &msm_fe_dai_ops,
+ .ops = &msm_fe_Multimedia_dai_ops,
.name = "MultiMedia3",
},
/* FE DAIs created for hostless operation purpose */
diff --git a/sound/soc/msm/msm-pcm-lpa.c b/sound/soc/msm/msm-pcm-lpa.c
index 8a44a56..a3c311c 100644
--- a/sound/soc/msm/msm-pcm-lpa.c
+++ b/sound/soc/msm/msm-pcm-lpa.c
@@ -46,7 +46,7 @@
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
- .rates = SNDRV_PCM_RATE_8000_48000,
+ .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT,
.rate_min = 8000,
.rate_max = 48000,
.channels_min = 1,
diff --git a/sound/soc/msm/msm-pcm-routing.c b/sound/soc/msm/msm-pcm-routing.c
index 3eb9a42..3c92514 100644
--- a/sound/soc/msm/msm-pcm-routing.c
+++ b/sound/soc/msm/msm-pcm-routing.c
@@ -360,7 +360,8 @@
static int msm_routing_put_switch_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
- struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
pr_debug("%s: FM Switch enable %ld\n", __func__,
ucontrol->value.integer.value[0]);
@@ -710,7 +711,7 @@
SND_SOC_DAPM_AIF_OUT("AUX_PCM_RX", "AUX PCM Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("AUX_PCM_TX", "AUX PCM Capture", 0, 0, 0, 0),
/* Switch Definitions */
- SND_SOC_DAPM_SWITCH("SBUS_0_RX", SND_SOC_NOPM, 0, 0,
+ SND_SOC_DAPM_SWITCH("SLIMBUS_DL_HL", SND_SOC_NOPM, 0, 0,
&fm_switch_mixer_controls),
/* Mixer definitions */
SND_SOC_DAPM_MIXER("PRI_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
@@ -843,7 +844,8 @@
{"Voip_Tx Mixer", "AUX_PCM_TX_Voip", "AUX_PCM_TX"},
{"VOIP_UL", NULL, "Voip_Tx Mixer"},
- {"SLIMBUS_0_RX", "Switch", "SLIM0_DL_HL"},
+ {"SLIMBUS_DL_HL", "Switch", "SLIM0_DL_HL"},
+ {"SLIMBUS_0_RX", NULL, "SLIMBUS_DL_HL"},
{"SLIM0_UL_HL", NULL, "SLIMBUS_0_TX"},
{"INT_FM_RX", NULL, "INTFM_DL_HL"},
{"INTFM_UL_HL", NULL, "INT_FM_TX"},
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 5e81e0f..0f08682 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -25,7 +25,7 @@
#include <sound/jack.h>
#include <asm/mach-types.h>
#include "msm-pcm-routing.h"
-#include <../codecs/wcd9310.h>
+#include "../codecs/wcd9310.h"
/* 8960 machine driver */
diff --git a/sound/soc/msm/qdsp6/q6adm.c b/sound/soc/msm/qdsp6/q6adm.c
index 51be337..ee6116a 100644
--- a/sound/soc/msm/qdsp6/q6adm.c
+++ b/sound/soc/msm/qdsp6/q6adm.c
@@ -609,6 +609,8 @@
ret = -EINVAL;
goto fail_cmd;
}
+
+ rtac_remove_adm_device(port_id);
}
fail_cmd:
diff --git a/sound/soc/msm/qdsp6/q6asm.c b/sound/soc/msm/qdsp6/q6asm.c
index 052286b..9fcee70 100644
--- a/sound/soc/msm/qdsp6/q6asm.c
+++ b/sound/soc/msm/qdsp6/q6asm.c
@@ -205,6 +205,7 @@
static void q6asm_session_free(struct audio_client *ac)
{
pr_debug("%s: sessionid[%d]\n", __func__, ac->session);
+ rtac_remove_popp_from_adm_devices(ac->session);
mutex_lock(&session_lock);
session[ac->session] = 0;
mutex_unlock(&session_lock);
@@ -1133,6 +1134,9 @@
case FORMAT_MPEG4_AAC:
open.format = MPEG4_AAC;
break;
+ case FORMAT_MPEG4_MULTI_AAC:
+ open.format = MPEG4_MULTI_AAC;
+ break;
case FORMAT_WMA_V9:
open.format = WMA_V9;
break;
@@ -1192,6 +1196,9 @@
case FORMAT_MPEG4_AAC:
open.write_format = MPEG4_AAC;
break;
+ case FORMAT_MPEG4_MULTI_AAC:
+ open.write_format = MPEG4_MULTI_AAC;
+ break;
case FORMAT_WMA_V9:
open.write_format = WMA_V9;
break;
@@ -1675,6 +1682,56 @@
return -EINVAL;
}
+
+int q6asm_media_format_block_multi_aac(struct audio_client *ac,
+ struct asm_aac_cfg *cfg)
+{
+ struct asm_stream_media_format_update fmt;
+ int rc = 0;
+
+ pr_debug("%s:session[%d]rate[%d]ch[%d]\n", __func__, ac->session,
+ cfg->sample_rate, cfg->ch_cfg);
+
+ q6asm_add_hdr(ac, &fmt.hdr, sizeof(fmt), TRUE);
+
+ fmt.hdr.opcode = ASM_DATA_CMD_MEDIA_FORMAT_UPDATE;
+
+ fmt.format = MPEG4_MULTI_AAC;
+ fmt.cfg_size = sizeof(struct asm_aac_cfg);
+ fmt.write_cfg.aac_cfg.format = cfg->format;
+ fmt.write_cfg.aac_cfg.aot = cfg->aot;
+ fmt.write_cfg.aac_cfg.ep_config = cfg->ep_config;
+ fmt.write_cfg.aac_cfg.section_data_resilience =
+ cfg->section_data_resilience;
+ fmt.write_cfg.aac_cfg.scalefactor_data_resilience =
+ cfg->scalefactor_data_resilience;
+ fmt.write_cfg.aac_cfg.spectral_data_resilience =
+ cfg->spectral_data_resilience;
+ fmt.write_cfg.aac_cfg.ch_cfg = cfg->ch_cfg;
+ fmt.write_cfg.aac_cfg.sample_rate = cfg->sample_rate;
+ pr_info("%s:format=%x cfg_size=%d aac-cfg=%x aot=%d ch=%d sr=%d\n",
+ __func__, fmt.format, fmt.cfg_size,
+ fmt.write_cfg.aac_cfg.format,
+ fmt.write_cfg.aac_cfg.aot,
+ fmt.write_cfg.aac_cfg.ch_cfg,
+ fmt.write_cfg.aac_cfg.sample_rate);
+ rc = apr_send_pkt(ac->apr, (uint32_t *) &fmt);
+ if (rc < 0) {
+ pr_err("%s:Comamnd open failed\n", __func__);
+ goto fail_cmd;
+ }
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
+ if (!rc) {
+ pr_err("%s:timeout. waited for FORMAT_UPDATE\n", __func__);
+ goto fail_cmd;
+ }
+ return 0;
+fail_cmd:
+ return -EINVAL;
+}
+
+
int q6asm_media_format_block_wma(struct audio_client *ac,
void *cfg)
{
diff --git a/sound/soc/msm/qdsp6/q6voice.c b/sound/soc/msm/qdsp6/q6voice.c
index ecfef5b..965211d 100644
--- a/sound/soc/msm/qdsp6/q6voice.c
+++ b/sound/soc/msm/qdsp6/q6voice.c
@@ -287,8 +287,9 @@
mvm_session_cmd.hdr.token = 0;
mvm_session_cmd.hdr.opcode =
VSS_IMVM_CMD_CREATE_PASSIVE_CONTROL_SESSION;
- strncpy(mvm_session_cmd.mvm_session.name,
- "default modem voice", SESSION_NAME_LEN);
+ strlcpy(mvm_session_cmd.mvm_session.name,
+ "default modem voice",
+ sizeof(mvm_session_cmd.mvm_session.name));
v->mvm_state = CMD_STATUS_FAIL;
@@ -320,8 +321,9 @@
mvm_session_cmd.hdr.token = 0;
mvm_session_cmd.hdr.opcode =
VSS_IMVM_CMD_CREATE_FULL_CONTROL_SESSION;
- strncpy(mvm_session_cmd.mvm_session.name,
- "default voip", SESSION_NAME_LEN);
+ strlcpy(mvm_session_cmd.mvm_session.name,
+ "default voip",
+ sizeof(mvm_session_cmd.mvm_session.name));
v->mvm_state = CMD_STATUS_FAIL;
@@ -361,8 +363,9 @@
cvs_session_cmd.hdr.token = 0;
cvs_session_cmd.hdr.opcode =
VSS_ISTREAM_CMD_CREATE_PASSIVE_CONTROL_SESSION;
- strncpy(cvs_session_cmd.cvs_session.name,
- "default modem voice", SESSION_NAME_LEN);
+ strlcpy(cvs_session_cmd.cvs_session.name,
+ "default modem voice",
+ sizeof(cvs_session_cmd.cvs_session.name));
v->cvs_state = CMD_STATUS_FAIL;
@@ -407,8 +410,9 @@
common.mvs_info.media_type;
cvs_full_ctl_cmd.cvs_session.network_id =
common.mvs_info.network_type;
- strncpy(cvs_full_ctl_cmd.cvs_session.name,
- "default q6 voice", 16);
+ strlcpy(cvs_full_ctl_cmd.cvs_session.name,
+ "default q6 voice",
+ sizeof(cvs_full_ctl_cmd.cvs_session.name));
v->cvs_state = CMD_STATUS_FAIL;