Merge "msm: defconfig: enable smd on 8064" into msm-3.0
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 52a4d20..43ac10a 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -20,6 +20,7 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_PANIC_TIMEOUT=5
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_PERF_EVENTS is not set
@@ -41,6 +42,7 @@
CONFIG_MSM_SMD_PKG4=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_WATCHDOG=y
+CONFIG_MSM_DLOAD_MODE=y
CONFIG_SWP_EMULATE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -132,7 +134,7 @@
# CONFIG_MMC_MSM_SDC3_SUPPORT is not set
# CONFIG_MMC_MSM_SDC4_SUPPORT is not set
# CONFIG_MMC_MSM_SDC5_SUPPORT is not set
-# CONFIG_MMC_MSM_SPS_SUPPORT is not set
+CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_MSM_SSBI=y
CONFIG_SPS=y
CONFIG_SPS_SUPPORT_BAMDMA=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 5bd19e5..99655d0 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1598,7 +1598,7 @@
config MSM_DLOAD_MODE
bool "Enable download mode on crashes"
- depends on ARCH_MSM8X60 || ARCH_MSM8960
+ depends on ARCH_MSM8X60 || ARCH_MSM8960 || ARCH_MSM9615
default n
help
This makes the SoC enter download mode when it resets
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 4a34512..35b9646 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -39,15 +39,18 @@
&msm9615_device_tsens,
&msm_device_nand,
&msm_rpm_device,
+#ifdef CONFIG_HW_RANDOM_MSM
+ &msm_device_rng,
+#endif
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
- &qcrypto_device,
+ &msm9615_qcrypto_device,
#endif
#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
- &qcedev_device,
+ &msm9615_qcedev_device,
#endif
};
@@ -214,117 +217,6 @@
},
};
-#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
- defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
-
-#define QCE_SIZE 0x10000
-#define QCE_0_BASE 0x18500000
-
-#define QCE_HW_KEY_SUPPORT 0
-#define QCE_SHA_HMAC_SUPPORT 1
-#define QCE_SHARE_CE_RESOURCE 1
-#define QCE_CE_SHARED 0
-
-static struct resource qcrypto_resources[] = {
- [0] = {
- .start = QCE_0_BASE,
- .end = QCE_0_BASE + QCE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "crypto_channels",
- .start = DMOV_CE_IN_CHAN,
- .end = DMOV_CE_OUT_CHAN,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .name = "crypto_crci_in",
- .start = DMOV_CE_IN_CRCI,
- .end = DMOV_CE_IN_CRCI,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .name = "crypto_crci_out",
- .start = DMOV_CE_OUT_CRCI,
- .end = DMOV_CE_OUT_CRCI,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct resource qcedev_resources[] = {
- [0] = {
- .start = QCE_0_BASE,
- .end = QCE_0_BASE + QCE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "crypto_channels",
- .start = DMOV_CE_IN_CHAN,
- .end = DMOV_CE_OUT_CHAN,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .name = "crypto_crci_in",
- .start = DMOV_CE_IN_CRCI,
- .end = DMOV_CE_IN_CRCI,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .name = "crypto_crci_out",
- .start = DMOV_CE_OUT_CRCI,
- .end = DMOV_CE_OUT_CRCI,
- .flags = IORESOURCE_DMA,
- },
-};
-
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
- defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
-
-static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
- .ce_shared = QCE_CE_SHARED,
- .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
- .hw_key_support = QCE_HW_KEY_SUPPORT,
- .sha_hmac = QCE_SHA_HMAC_SUPPORT,
-};
-
-static struct platform_device qcrypto_device = {
- .name = "qcrypto",
- .id = 0,
- .num_resources = ARRAY_SIZE(qcrypto_resources),
- .resource = qcrypto_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &qcrypto_ce_hw_suppport,
- },
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
- defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
-
-static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
- .ce_shared = QCE_CE_SHARED,
- .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
- .hw_key_support = QCE_HW_KEY_SUPPORT,
- .sha_hmac = QCE_SHA_HMAC_SUPPORT,
-};
-
-static struct platform_device qcedev_device = {
- .name = "qce",
- .id = 0,
- .num_resources = ARRAY_SIZE(qcedev_resources),
- .resource = qcedev_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &qcedev_ce_hw_suppport,
- },
-};
-#endif
-
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
diff --git a/arch/arm/mach-msm/board-apq8064.c b/arch/arm/mach-msm/board-apq8064.c
index d37fb7b..4328b85 100644
--- a/arch/arm/mach-msm/board-apq8064.c
+++ b/arch/arm/mach-msm/board-apq8064.c
@@ -36,6 +36,18 @@
#include "board-apq8064.h"
+static struct platform_device android_usb_device = {
+ .name = "android_usb",
+ .id = -1,
+};
+
+static struct msm_otg_platform_data msm_otg_pdata = {
+ .mode = USB_PERIPHERAL,
+ .otg_control = OTG_PHY_CONTROL,
+ .phy_type = SNPS_28NM_INTEGRATED_PHY,
+ .pclk_src_name = "dfab_usb_hs_clk",
+};
+
/* APQ8064 have 4 SDCC controllers */
enum sdcc_controllers {
SDCC1,
@@ -310,6 +322,9 @@
&apq8064_device_ssbi_pmic1,
&apq8064_device_ssbi_pmic2,
&msm_device_smd_apq8064,
+ &apq8064_device_otg,
+ &apq8064_device_gadget_peripheral,
+ &android_usb_device,
};
static struct platform_device *sim_devices[] __initdata = {
@@ -326,13 +341,6 @@
.max_clock_speed = 26000000,
};
-static struct msm_otg_platform_data msm_otg_pdata = {
- .mode = USB_PERIPHERAL,
- .otg_control = OTG_PHY_CONTROL,
- .phy_type = SNPS_28NM_INTEGRATED_PHY,
- .pclk_src_name = "dfab_usb_hs_clk",
-};
-
#define KS8851_IRQ_GPIO 43
static struct spi_board_info spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 058bc47..1c277c8 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -233,7 +233,13 @@
.pull = GPIOMUX_PULL_DOWN,
};
-static struct gpiomux_setting gsbi3 = {
+static struct gpiomux_setting gsbi3_suspended_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_KEEPER,
+};
+
+static struct gpiomux_setting gsbi3_active_cfg = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
.pull = GPIOMUX_PULL_NONE,
@@ -347,13 +353,15 @@
{
.gpio = 16, /* GSBI3 I2C QUP SDA */
.settings = {
- [GPIOMUX_SUSPENDED] = &gsbi3,
+ [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
},
},
{
.gpio = 17, /* GSBI3 I2C QUP SCL */
.settings = {
- [GPIOMUX_SUSPENDED] = &gsbi3,
+ [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
},
},
{
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 4552f80..3d2d720 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -1513,7 +1513,7 @@
SND(FM_DIGITAL_STEREO_HEADSET, 26),
SND(FM_DIGITAL_SPEAKER_PHONE, 27),
SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
- SND(CURRENT, 34),
+ SND(CURRENT, 0x7FFFFFFE),
SND(FM_ANALOG_STEREO_HEADSET, 35),
SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
};
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index ea2d9d2..243b3d2 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -297,6 +297,11 @@
#define LCC_PCM_MD_REG REG_LPA(0x0058)
#define LCC_PCM_NS_REG REG_LPA(0x0054)
#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
+#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
+#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
+#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
+#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
+#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
@@ -308,6 +313,7 @@
#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
+#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
@@ -4939,7 +4945,7 @@
CLK_LOOKUP("cxo", cxo_clk.c, NULL),
CLK_LOOKUP("pll2", pll2_clk.c, NULL),
CLK_LOOKUP("pll8", pll8_clk.c, NULL),
- CLK_DUMMY("pll4", PLL4, NULL, 0),
+ CLK_LOOKUP("pll4", pll4_clk.c, NULL),
CLK_LOOKUP("measure", measure_clk.c, "debug"),
CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
@@ -4982,12 +4988,12 @@
CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
- CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
- CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
+ CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
+ CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
CLK_LOOKUP("sata_phy_ref_clk", sata_phy_ref_clk.c, NULL),
@@ -5001,8 +5007,8 @@
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
- CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
- CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
+ CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
@@ -5098,17 +5104,18 @@
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, NULL),
CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
- CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
+ CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
+ CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
+ CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
+ CLK_DUMMY("sps_slimbus_clk", SPS_SLIMBUS_CLK, NULL, OFF),
CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
@@ -5190,6 +5197,8 @@
CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
+ CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
+ CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
@@ -5445,13 +5454,19 @@
/* Deassert MM SW_RESET_ALL signal. */
writel_relaxed(0, SW_RESET_ALL_REG);
+ /*
+ * Some bits are only used on either 8960 or 8064 and are marked as
+ * reserved bits on the other SoC. Writing to these reserved bits
+ * should have no effect.
+ */
/* Initialize MM AHB registers: Enable the FPB clock and disable HW
* gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
* prevent its memory from being collapsed when the clock is halted.
* The sleep and wake-up delays are set to safe values. */
rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
writel_relaxed(0x000007F9, AHB_EN2_REG);
- rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
+ if (cpu_is_apq8064())
+ rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
/* Deassert all locally-owned MM AHB resets. */
rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
@@ -5465,7 +5480,8 @@
rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
- rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
+ if (cpu_is_apq8064())
+ rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
/* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
@@ -5477,22 +5493,26 @@
rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
- if (cpu_is_apq8064())
+ if (cpu_is_msm8960()) {
+ rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
+ }
+ if (cpu_is_apq8064()) {
+ rmwreg(0x00000000, TV_CC_REG, 0x00004010);
rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
+ }
/*
* Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
@@ -5500,8 +5520,10 @@
* and wake-up value to max.
*/
rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
- rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
- rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
+ if (cpu_is_apq8064()) {
+ rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
+ rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
+ }
/* De-assert MM AXI resets to all hardware blocks. */
writel_relaxed(0, SW_RESET_AXI_REG);
@@ -5527,7 +5549,8 @@
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
/* Source SLIMBus xo src from slimbus reference clock */
- writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
+ if (cpu_is_msm8960())
+ writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
/* Source the dsi_byte_clks from the DSI PHY PLLs */
rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
@@ -5671,6 +5694,33 @@
regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
regval |= BIT(12);
writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
+
+ /* Check if PLL4 is active */
+ is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
+ if (!is_pll_enabled) {
+ /* Ref clk = 24.5MHz and program pll4 to 393.2160MHz */
+ writel_relaxed(0x10, LCC_PLL0_L_VAL_REG);
+ writel_relaxed(0x130, LCC_PLL0_M_VAL_REG);
+ writel_relaxed(0x17ED, LCC_PLL0_N_VAL_REG);
+
+ regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
+
+ /* Enable the main output and the MN accumulator */
+ regval |= BIT(23) | BIT(22);
+
+ /* Set pre-divider and post-divider values to 1 and 1 */
+ regval &= ~BIT(19);
+ regval &= ~BM(21, 20);
+
+ /* Set VCO frequency */
+ regval &= ~BM(17, 16);
+ writel_relaxed(regval, LCC_PLL0_CONFIG_REG);
+
+ set_fsm_mode(LCC_PLL0_MODE_REG);
+ }
+
+ /* Enable PLL4 source on the LPASS Primary PLL Mux */
+ writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
}
}
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 9b9ac4a..84121ef 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1524,7 +1524,7 @@
CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
- CLK_LOOKUP("prng_clk", prng_clk.c, NULL),
+ CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 649aeab..2477221 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -190,7 +190,9 @@
cur_freq = acpuclk_get_rate(policy->cpu);
if (cpufreq_frequency_table_target(policy, table, cur_freq,
- CPUFREQ_RELATION_H, &index)) {
+ CPUFREQ_RELATION_H, &index) &&
+ cpufreq_frequency_table_target(policy, table, cur_freq,
+ CPUFREQ_RELATION_L, &index)) {
pr_info("cpufreq: cpu%d at invalid freq: %d\n",
policy->cpu, cur_freq);
return -EINVAL;
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index d542b96..62cc590 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -16,6 +16,8 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/msm_tsens.h>
+#include <linux/platform_data/qcom_crypto_device.h>
+#include <linux/dma-mapping.h>
#include <asm/hardware/gic.h>
#include <asm/mach/flash.h>
#include <mach/board.h>
@@ -257,6 +259,133 @@
.id = -1,
};
+#ifdef CONFIG_HW_RANDOM_MSM
+/* PRNG device */
+#define MSM_PRNG_PHYS 0x1A500000
+static struct resource rng_resources = {
+ .flags = IORESOURCE_MEM,
+ .start = MSM_PRNG_PHYS,
+ .end = MSM_PRNG_PHYS + SZ_512 - 1,
+};
+
+struct platform_device msm_device_rng = {
+ .name = "msm_rng",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &rng_resources,
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+#define QCE_SIZE 0x10000
+#define QCE_0_BASE 0x18500000
+
+#define QCE_HW_KEY_SUPPORT 0
+#define QCE_SHA_HMAC_SUPPORT 1
+#define QCE_SHARE_CE_RESOURCE 1
+#define QCE_CE_SHARED 0
+
+static struct resource qcrypto_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource qcedev_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+
+static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+struct platform_device msm9615_qcrypto_device = {
+ .name = "qcrypto",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcrypto_resources),
+ .resource = qcrypto_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcrypto_ce_hw_suppport,
+ },
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+struct platform_device msm9615_qcedev_device = {
+ .name = "qce",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcedev_resources),
+ .resource = qcedev_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcedev_ce_hw_suppport,
+ },
+};
+#endif
#define MSM_SDC1_BASE 0x12180000
#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 4a82b33..458b00d 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -192,4 +192,15 @@
extern struct platform_device ion_dev;
extern struct platform_device msm_rpm_device;
+extern struct platform_device msm_device_rng;
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+extern struct platform_device msm9615_qcrypto_device;
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+extern struct platform_device msm9615_qcedev_device;
+#endif
#endif
diff --git a/arch/arm/mach-msm/sdio_al.c b/arch/arm/mach-msm/sdio_al.c
index 8267fad..ace437b 100644
--- a/arch/arm/mach-msm/sdio_al.c
+++ b/arch/arm/mach-msm/sdio_al.c
@@ -108,6 +108,7 @@
* packet) rx data.
*/
#define DEFAULT_READ_THRESHOLD (1024)
+#define LOW_LATENCY_THRESHOLD (1)
/* Extra bytes to ensure getting the rx threshold interrupt on stream channels
when restoring the threshold after sleep */
@@ -119,7 +120,6 @@
#define THRESHOLD_DISABLE_VAL (0xFFFFFFFF)
-
/** Mailbox polling time for packet channels */
#define DEFAULT_POLL_DELAY_MSEC 10
/** Mailbox polling time for streaming channels */
@@ -986,7 +986,7 @@
continue;
}
if (ch->is_packet_mode == false) {
- ch->read_threshold = 1;
+ ch->read_threshold = LOW_LATENCY_THRESHOLD;
set_pipe_threshold(sdio_al_dev,
ch->rx_pipe_index,
ch->read_threshold);
@@ -1156,13 +1156,22 @@
sdio_al_dev->host->index);
}
ch->read_avail = read_avail;
- /* Restore default thresh for non packet channels */
+
+ /*
+ * Restore default thresh for non packet channels.
+ * in case it IS low latency channel then read_threshold
+ * and def_read_threshold are both
+ * LOW_LATENCY_THRESHOLD
+ */
if ((ch->read_threshold != ch->def_read_threshold) &&
(read_avail >= ch->threshold_change_cnt)) {
- ch->read_threshold = ch->def_read_threshold;
- set_pipe_threshold(sdio_al_dev,
- ch->rx_pipe_index,
- ch->read_threshold);
+ if (!ch->is_low_latency_ch) {
+ ch->read_threshold =
+ ch->def_read_threshold;
+ set_pipe_threshold(sdio_al_dev,
+ ch->rx_pipe_index,
+ ch->read_threshold);
+ }
}
}
@@ -1968,14 +1977,18 @@
goto exit_err;
}
- /* Aggregation up to 90% of the maximum size */
- ch->read_threshold = (ch_config->max_rx_threshold * 9) / 10;
+ ch->read_threshold = LOW_LATENCY_THRESHOLD;
+ ch->is_low_latency_ch = ch_config->is_low_latency_ch;
/* Threshold on 50% of the maximum size , sdioc uses double-buffer */
ch->write_threshold = (ch_config->max_tx_threshold * 5) / 10;
ch->threshold_change_cnt = ch->ch_config.max_rx_threshold -
ch->read_threshold + THRESHOLD_CHANGE_EXTRA_BYTES;
- ch->def_read_threshold = ch->read_threshold;
+ if (ch->is_low_latency_ch)
+ ch->def_read_threshold = LOW_LATENCY_THRESHOLD;
+ else /* Aggregation up to 90% of the maximum size */
+ ch->def_read_threshold = (ch_config->max_rx_threshold * 9) / 10;
+
ch->is_packet_mode = ch_config->is_packet_mode;
if (!ch->is_packet_mode) {
ch->poll_delay_msec = DEFAULT_POLL_DELAY_NOPACKET_MSEC;
diff --git a/arch/arm/mach-msm/sdio_al_private.h b/arch/arm/mach-msm/sdio_al_private.h
index f352499..36d9ec1 100644
--- a/arch/arm/mach-msm/sdio_al_private.h
+++ b/arch/arm/mach-msm/sdio_al_private.h
@@ -66,7 +66,8 @@
u32 is_host_ok_to_sleep;
u32 is_packet_mode;
u32 peer_operation;
- u32 reserved[24];
+ u32 is_low_latency_ch;
+ u32 reserved[23];
};
@@ -173,6 +174,7 @@
int min_write_avail;
int poll_delay_msec;
int is_packet_mode;
+ int is_low_latency_ch;
struct peer_sdioc_channel_config ch_config;
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 31634ff..66bab6b 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -302,6 +302,7 @@
break;
}
+ kfree_skb(skb);
wake_unlock(&hs.wake_lock_tx);
return ret;
}
diff --git a/drivers/char/hw_random/msm_rng.c b/drivers/char/hw_random/msm_rng.c
index 3a2cd9a..5937c78 100644
--- a/drivers/char/hw_random/msm_rng.c
+++ b/drivers/char/hw_random/msm_rng.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/types.h>
+#include <mach/socinfo.h>
#define DRIVER_NAME "msm_rng"
@@ -78,11 +79,11 @@
/* read random data from h/w */
do {
/* check status bit if data is available */
- if (!(readl(base + PRNG_STATUS_OFFSET) & 0x00000001))
+ if (!(readl_relaxed(base + PRNG_STATUS_OFFSET) & 0x00000001))
break; /* no data to read so just bail */
/* read FIFO */
- val = readl(base + PRNG_DATA_OUT_OFFSET);
+ val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET);
if (!val)
break; /* no data to read so just bail */
@@ -106,6 +107,45 @@
.read = msm_rng_read,
};
+static int __devinit msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev)
+{
+ unsigned long val = 0;
+ int ret = 0;
+ int error = 0;
+
+ ret = clk_enable(msm_rng_dev->prng_clk);
+ if (ret) {
+ dev_err(&(msm_rng_dev->pdev)->dev,
+ "failed to enable clock in probe\n");
+ error = -EPERM;
+ return error;
+ }
+
+ /* enable PRNG h/w*/
+ val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET) &
+ PRNG_LFSR_CFG_MASK;
+ val |= PRNG_LFSR_CFG_MASK;
+ writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
+
+ /* The PRNG CONFIG register should be read after writing to the
+ * PRNG_LFSR_CFG register.
+ */
+ mb();
+ val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
+ PRNG_CONFIG_MASK;
+ val |= PRNG_CONFIG_ENABLE;
+ writel_relaxed(val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
+
+ /* The PRNG clk should be disabled only after we have enabled the
+ * PRNG H/W by writting to the PRNG_CONFIG register.
+ */
+ mb();
+
+ clk_disable(msm_rng_dev->prng_clk);
+
+ return error;
+}
+
static int __devinit msm_rng_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -147,18 +187,25 @@
msm_rng_dev->pdev = pdev;
platform_set_drvdata(pdev, msm_rng_dev);
+ /* Enable rng h/w */
+ if (cpu_is_msm9615())
+ error = msm_rng_enable_hw(msm_rng_dev);
+
+ if (error)
+ goto rollback_clk;
+
/* register with hwrng framework */
msm_rng.priv = (unsigned long) msm_rng_dev;
error = hwrng_register(&msm_rng);
if (error) {
dev_err(&pdev->dev, "failed to register hwrng\n");
error = -EPERM;
- goto err_hw_register;
+ goto rollback_clk;
}
return 0;
-err_hw_register:
+rollback_clk:
clk_put(msm_rng_dev->prng_clk);
err_clk_get:
iounmap(msm_rng_dev->base);
diff --git a/drivers/gpu/msm/adreno_postmortem.c b/drivers/gpu/msm/adreno_postmortem.c
index 7c7f0dc..cc69360 100644
--- a/drivers/gpu/msm/adreno_postmortem.c
+++ b/drivers/gpu/msm/adreno_postmortem.c
@@ -25,6 +25,7 @@
#include "a2xx_reg.h"
#define INVALID_RB_CMD 0xaaaaaaaa
+#define NUM_DWORDS_OF_RINGBUFFER_HISTORY 100
struct pm_id_name {
uint32_t id;
@@ -536,7 +537,12 @@
kgsl_regread(device, REG_CP_RB_RPTR_ADDR, &r3);
KGSL_LOG_DUMP(device,
"CP_RB: BASE = %08X | CNTL = %08X | RPTR_ADDR = %08X"
- "\n", cp_rb_base, r2, r3);
+ " | rb_count = %08X\n", cp_rb_base, r2, r3, rb_count);
+ {
+ struct adreno_ringbuffer *rb = &adreno_dev->ringbuffer;
+ if (rb->sizedwords != rb_count)
+ rb_count = rb->sizedwords;
+ }
kgsl_regread(device, REG_CP_RB_RPTR, &cp_rb_rptr);
kgsl_regread(device, REG_CP_RB_WPTR, &cp_rb_wptr);
@@ -683,13 +689,13 @@
goto error_vfree;
}
- read_idx = (int)cp_rb_rptr - 64;
+ read_idx = (int)cp_rb_rptr - NUM_DWORDS_OF_RINGBUFFER_HISTORY;
if (read_idx < 0)
read_idx += rb_count;
write_idx = (int)cp_rb_wptr + 16;
if (write_idx > rb_count)
write_idx -= rb_count;
- num_item += 64+16;
+ num_item += NUM_DWORDS_OF_RINGBUFFER_HISTORY+16;
if (num_item > rb_count)
num_item = rb_count;
if (write_idx >= read_idx)
@@ -736,7 +742,7 @@
the process in whose context the GPU hung */
cur_pt_base = pt_base;
- read_idx = (int)cp_rb_rptr - 64;
+ read_idx = (int)cp_rb_rptr - NUM_DWORDS_OF_RINGBUFFER_HISTORY;
if (read_idx < 0)
read_idx += rb_count;
KGSL_LOG_DUMP(device,
@@ -745,13 +751,14 @@
adreno_dump_rb(device, rb_copy, num_item<<2, read_idx, rb_count);
if (adreno_ib_dump_enabled()) {
- for (read_idx = 64; read_idx >= 0; --read_idx) {
+ for (read_idx = NUM_DWORDS_OF_RINGBUFFER_HISTORY;
+ read_idx >= 0; --read_idx) {
uint32_t this_cmd = rb_copy[read_idx];
if (this_cmd == cp_type3_packet(
CP_INDIRECT_BUFFER_PFD, 2)) {
uint32_t ib_addr = rb_copy[read_idx+1];
uint32_t ib_size = rb_copy[read_idx+2];
- if (cp_ib1_bufsz && cp_ib1_base == ib_addr) {
+ if (ib_size && cp_ib1_base == ib_addr) {
KGSL_LOG_DUMP(device,
"IB1: base:%8.8X "
"count:%d\n", ib_addr, ib_size);
@@ -762,9 +769,9 @@
}
}
for (i = 0; i < ib_list.count; ++i) {
- if (cp_ib2_bufsz && cp_ib2_base == ib_list.bases[i]) {
- uint32_t ib_size = ib_list.sizes[i];
- uint32_t ib_offset = ib_list.offsets[i];
+ uint32_t ib_size = ib_list.sizes[i];
+ uint32_t ib_offset = ib_list.offsets[i];
+ if (ib_size && cp_ib2_base == ib_list.bases[i]) {
KGSL_LOG_DUMP(device,
"IB2: base:%8.8X count:%d\n",
cp_ib2_base, ib_size);
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index f9d671e..f3cd0ad 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -797,6 +797,15 @@
The driver supports reading the HKADC, XOADC and support to set and receive
temperature threshold notifications using the Battery temperature module.
+config SENSORS_PM8XXX_ADC
+ tristate "Support for Qualcomm PM8XXX ADC"
+ depends on MFD_PM8018_CORE
+ help
+ This is the ADC arbiter driver for Qualcomm PM8XXX Chip.
+
+ The driver supports reading the HKADC, XOADC and support to set and receive
+ temperature threshold notifications using the Battery temperature module.
+
config SENSORS_PC87360
tristate "National Semiconductor PC87360 family"
select HWMON_VID
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index c25ffcb..10d0699 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -121,6 +121,7 @@
obj-$(CONFIG_SENSORS_WPCE775X) += wpce775x.o
obj-$(CONFIG_SENSORS_MSM_ADC) += msm_adc.o m_adcproc.o
obj-$(CONFIG_SENSORS_PM8921_ADC) += pm8921-adc.o msmproc_adc.o
+obj-$(CONFIG_SENSORS_PM8XXX_ADC) += pm8xxx-adc.o pm8xxx-adc-scale.o
# PMBus drivers
obj-$(CONFIG_PMBUS) += pmbus_core.o
diff --git a/drivers/hwmon/pm8xxx-adc-scale.c b/drivers/hwmon/pm8xxx-adc-scale.c
new file mode 100644
index 0000000..40ade69
--- /dev/null
+++ b/drivers/hwmon/pm8xxx-adc-scale.c
@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+#define KELVINMIL_DEGMIL 273160
+
+static const struct pm8xxx_adc_map_pt adcmap_batttherm[] = {
+ {41001, -30},
+ {40017, -20},
+ {38721, -10},
+ {37186, 0},
+ {35554, 10},
+ {33980, 20},
+ {33253, 25},
+ {32580, 30},
+ {31412, 40},
+ {30481, 50},
+ {29759, 60},
+ {29209, 70},
+ {28794, 80}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_btm_threshold[] = {
+ {-30, 41001},
+ {-20, 40017},
+ {-10, 38721},
+ {0, 37186},
+ {10, 35554},
+ {11, 35392},
+ {12, 35230},
+ {13, 35070},
+ {14, 34910},
+ {15, 34751},
+ {16, 34594},
+ {17, 34438},
+ {18, 34284},
+ {19, 34131},
+ {20, 33980},
+ {21, 33830},
+ {22, 33683},
+ {23, 33538},
+ {24, 33394},
+ {25, 33253},
+ {26, 33114},
+ {27, 32977},
+ {28, 32842},
+ {29, 32710},
+ {30, 32580},
+ {31, 32452},
+ {32, 32327},
+ {33, 32204},
+ {34, 32084},
+ {35, 31966},
+ {36, 31850},
+ {37, 31737},
+ {38, 31627},
+ {39, 31518},
+ {40, 31412},
+ {41, 31309},
+ {42, 31208},
+ {43, 31109},
+ {44, 31013},
+ {45, 30918},
+ {46, 30827},
+ {47, 30737},
+ {48, 30649},
+ {49, 30564},
+ {50, 30481},
+ {51, 30400},
+ {52, 30321},
+ {53, 30244},
+ {54, 30169},
+ {55, 30096},
+ {56, 30025},
+ {57, 29956},
+ {58, 29889},
+ {59, 29823},
+ {60, 29759},
+ {61, 29697},
+ {62, 29637},
+ {63, 29578},
+ {64, 29521},
+ {65, 29465},
+ {66, 29411},
+ {67, 29359},
+ {68, 29308},
+ {69, 29258},
+ {70, 29209},
+ {71, 29162},
+ {72, 29117},
+ {73, 29072},
+ {74, 29029},
+ {75, 28987},
+ {76, 28946},
+ {77, 28906},
+ {78, 28868},
+ {79, 28830},
+ {80, 28794}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_pa_therm[] = {
+ {41350, -30},
+ {41282, -29},
+ {41211, -28},
+ {41137, -27},
+ {41060, -26},
+ {40980, -25},
+ {40897, -24},
+ {40811, -23},
+ {40721, -22},
+ {40629, -21},
+ {40533, -20},
+ {40434, -19},
+ {40331, -18},
+ {40226, -17},
+ {40116, -16},
+ {40004, -15},
+ {39888, -14},
+ {39769, -13},
+ {39647, -12},
+ {39521, -11},
+ {39392, -10},
+ {39260, -9},
+ {39124, -8},
+ {38986, -7},
+ {38845, -6},
+ {38700, -5},
+ {38553, -4},
+ {38403, -3},
+ {38250, -2},
+ {38094, -1},
+ {37936, 0},
+ {37776, 1},
+ {37613, 2},
+ {37448, 3},
+ {37281, 4},
+ {37112, 5},
+ {36942, 6},
+ {36770, 7},
+ {36596, 8},
+ {36421, 9},
+ {36245, 10},
+ {36068, 11},
+ {35890, 12},
+ {35712, 13},
+ {35532, 14},
+ {35353, 15},
+ {35173, 16},
+ {34993, 17},
+ {34813, 18},
+ {34634, 19},
+ {34455, 20},
+ {34276, 21},
+ {34098, 22},
+ {33921, 23},
+ {33745, 24},
+ {33569, 25},
+ {33395, 26},
+ {33223, 27},
+ {33051, 28},
+ {32881, 29},
+ {32713, 30},
+ {32547, 31},
+ {32382, 32},
+ {32219, 33},
+ {32058, 34},
+ {31899, 35},
+ {31743, 36},
+ {31588, 37},
+ {31436, 38},
+ {31285, 39},
+ {31138, 40},
+ {30992, 41},
+ {30849, 42},
+ {30708, 43},
+ {30570, 44},
+ {30434, 45},
+ {30300, 46},
+ {30169, 47},
+ {30041, 48},
+ {29915, 49},
+ {29791, 50},
+ {29670, 51},
+ {29551, 52},
+ {29435, 53},
+ {29321, 54},
+ {29210, 55},
+ {29101, 56},
+ {28994, 57},
+ {28890, 58},
+ {28788, 59},
+ {28688, 60},
+ {28590, 61},
+ {28495, 62},
+ {28402, 63},
+ {28311, 64},
+ {28222, 65},
+ {28136, 66},
+ {28051, 67},
+ {27968, 68},
+ {27888, 69},
+ {27809, 70},
+ {27732, 71},
+ {27658, 72},
+ {27584, 73},
+ {27513, 74},
+ {27444, 75},
+ {27376, 76},
+ {27310, 77},
+ {27245, 78},
+ {27183, 79},
+ {27121, 80},
+ {27062, 81},
+ {27004, 82},
+ {26947, 83},
+ {26892, 84},
+ {26838, 85},
+ {26785, 86},
+ {26734, 87},
+ {26684, 88},
+ {26636, 89},
+ {26588, 90}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_ntcg_104ef_104fb[] = {
+ {696483, -40960},
+ {649148, -39936},
+ {605368, -38912},
+ {564809, -37888},
+ {527215, -36864},
+ {492322, -35840},
+ {460007, -34816},
+ {429982, -33792},
+ {402099, -32768},
+ {376192, -31744},
+ {352075, -30720},
+ {329714, -29696},
+ {308876, -28672},
+ {289480, -27648},
+ {271417, -26624},
+ {254574, -25600},
+ {238903, -24576},
+ {224276, -23552},
+ {210631, -22528},
+ {197896, -21504},
+ {186007, -20480},
+ {174899, -19456},
+ {164521, -18432},
+ {154818, -17408},
+ {145744, -16384},
+ {137265, -15360},
+ {129307, -14336},
+ {121866, -13312},
+ {114896, -12288},
+ {108365, -11264},
+ {102252, -10240},
+ {96499, -9216},
+ {91111, -8192},
+ {86055, -7168},
+ {81308, -6144},
+ {76857, -5120},
+ {72660, -4096},
+ {68722, -3072},
+ {65020, -2048},
+ {61538, -1024},
+ {58261, 0},
+ {55177, 1024},
+ {52274, 2048},
+ {49538, 3072},
+ {46962, 4096},
+ {44531, 5120},
+ {42243, 6144},
+ {40083, 7168},
+ {38045, 8192},
+ {36122, 9216},
+ {34308, 10240},
+ {32592, 11264},
+ {30972, 12288},
+ {29442, 13312},
+ {27995, 14336},
+ {26624, 15360},
+ {25333, 16384},
+ {24109, 17408},
+ {22951, 18432},
+ {21854, 19456},
+ {20807, 20480},
+ {19831, 21504},
+ {18899, 22528},
+ {18016, 23552},
+ {17178, 24576},
+ {16384, 25600},
+ {15631, 26624},
+ {14916, 27648},
+ {14237, 28672},
+ {13593, 29696},
+ {12976, 30720},
+ {12400, 31744},
+ {11848, 32768},
+ {11324, 33792},
+ {10825, 34816},
+ {10354, 35840},
+ {9900, 36864},
+ {9471, 37888},
+ {9062, 38912},
+ {8674, 39936},
+ {8306, 40960},
+ {7951, 41984},
+ {7616, 43008},
+ {7296, 44032},
+ {6991, 45056},
+ {6701, 46080},
+ {6424, 47104},
+ {6160, 48128},
+ {5908, 49152},
+ {5667, 50176},
+ {5439, 51200},
+ {5219, 52224},
+ {5010, 53248},
+ {4810, 54272},
+ {4619, 55296},
+ {4440, 56320},
+ {4263, 57344},
+ {4097, 58368},
+ {3938, 59392},
+ {3785, 60416},
+ {3637, 61440},
+ {3501, 62464},
+ {3368, 63488},
+ {3240, 64512},
+ {3118, 65536},
+ {2998, 66560},
+ {2889, 67584},
+ {2782, 68608},
+ {2680, 69632},
+ {2581, 70656},
+ {2490, 71680},
+ {2397, 72704},
+ {2310, 73728},
+ {2227, 74752},
+ {2147, 75776},
+ {2064, 76800},
+ {1998, 77824},
+ {1927, 78848},
+ {1860, 79872},
+ {1795, 80896},
+ {1736, 81920},
+ {1673, 82944},
+ {1615, 83968},
+ {1560, 84992},
+ {1507, 86016},
+ {1456, 87040},
+ {1407, 88064},
+ {1360, 89088},
+ {1314, 90112},
+ {1271, 91136},
+ {1228, 92160},
+ {1189, 93184},
+ {1150, 94208},
+ {1112, 95232},
+ {1076, 96256},
+ {1042, 97280},
+ {1008, 98304},
+ {976, 99328},
+ {945, 100352},
+ {915, 101376},
+ {886, 102400},
+ {859, 103424},
+ {832, 104448},
+ {807, 105472},
+ {782, 106496},
+ {756, 107520},
+ {735, 108544},
+ {712, 109568},
+ {691, 110592},
+ {670, 111616},
+ {650, 112640},
+ {631, 113664},
+ {612, 114688},
+ {594, 115712},
+ {577, 116736},
+ {560, 117760},
+ {544, 118784},
+ {528, 119808},
+ {513, 120832},
+ {498, 121856},
+ {483, 122880},
+ {470, 123904},
+ {457, 124928},
+ {444, 125952},
+ {431, 126976},
+ {419, 128000}
+};
+
+static int32_t pm8xxx_adc_map_linear(const struct pm8xxx_adc_map_pt *pts,
+ uint32_t tablesize, int32_t input, int64_t *output)
+{
+ bool descending = 1;
+ uint32_t i = 0;
+
+ if ((pts == NULL) || (output == NULL))
+ return -EINVAL;
+
+ /* Check if table is descending or ascending */
+ if (tablesize > 1) {
+ if (pts[0].x < pts[1].x)
+ descending = 0;
+ }
+
+ while (i < tablesize) {
+ if ((descending == 1) && (pts[i].x < input)) {
+ /* table entry is less than measured
+ value and table is descending, stop */
+ break;
+ } else if ((descending == 0) &&
+ (pts[i].x > input)) {
+ /* table entry is greater than measured
+ value and table is ascending, stop */
+ break;
+ } else {
+ i++;
+ }
+ }
+
+ if (i == 0)
+ *output = pts[0].y;
+ else if (i == tablesize)
+ *output = pts[tablesize-1].y;
+ else {
+ /* result is between search_index and search_index-1 */
+ /* interpolate linearly */
+ *output = (((int32_t) ((pts[i].y - pts[i-1].y)*
+ (input - pts[i-1].x))/
+ (pts[i].x - pts[i-1].x))+
+ pts[i-1].y);
+ }
+
+ return 0;
+}
+
+int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ bool negative_rawfromoffset = 0;
+ int32_t rawfromoffset = 0;
+
+ if (!chan_properties || !chan_properties->offset_gain_numerator ||
+ !chan_properties->offset_gain_denominator || !adc_properties
+ || !adc_chan_result)
+ return -EINVAL;
+
+ rawfromoffset = adc_code -
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+
+ adc_chan_result->adc_code = adc_code;
+ if (rawfromoffset < 0) {
+ if (adc_properties->bipolar) {
+ rawfromoffset = -rawfromoffset;
+ negative_rawfromoffset = 1;
+ } else {
+ rawfromoffset = 0;
+ }
+ }
+
+ if (rawfromoffset >= 1 << adc_properties->bitresolution)
+ rawfromoffset = (1 << adc_properties->bitresolution) - 1;
+
+ adc_chan_result->measurement = (int64_t)rawfromoffset *
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dx *
+ chan_properties->offset_gain_denominator;
+
+ /* do_div only perform positive integer division! */
+ do_div(adc_chan_result->measurement,
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dy *
+ chan_properties->offset_gain_numerator);
+
+ if (negative_rawfromoffset)
+ adc_chan_result->measurement = -adc_chan_result->measurement;
+
+ /* Note: adc_chan_result->measurement is in the unit of
+ * adc_properties.adc_reference. For generic channel processing,
+ * channel measurement is a scale/ratio relative to the adc
+ * reference input */
+ adc_chan_result->physical = (int32_t) adc_chan_result->measurement;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_default);
+
+int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->measurement = adc_code;
+ /* convert mV ---> degC using the table */
+ return pm8xxx_adc_map_linear(
+ adcmap_batttherm,
+ ARRAY_SIZE(adcmap_batttherm),
+ adc_code,
+ &adc_chan_result->physical);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_batt_therm);
+
+int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->measurement = adc_code;
+ /* convert mV ---> degC using the table */
+ return pm8xxx_adc_map_linear(
+ adcmap_pa_therm,
+ ARRAY_SIZE(adcmap_pa_therm),
+ adc_code,
+ &adc_chan_result->physical);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_pa_therm);
+
+int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ int32_t rawfromoffset;
+
+ if (!chan_properties || !chan_properties->offset_gain_numerator ||
+ !chan_properties->offset_gain_denominator || !adc_properties
+ || !adc_chan_result)
+ return -EINVAL;
+
+ adc_chan_result->adc_code = adc_code;
+ rawfromoffset = adc_code -
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+ if (rawfromoffset > 0) {
+ if (rawfromoffset >= 1 << adc_properties->bitresolution)
+ rawfromoffset = (1 << adc_properties->bitresolution)
+ - 1;
+ /* 2mV/K */
+ adc_chan_result->measurement = (int64_t)rawfromoffset*
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dx *
+ chan_properties->offset_gain_denominator * 1000;
+
+ do_div(adc_chan_result->measurement,
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dy *
+ chan_properties->offset_gain_numerator*2);
+ } else {
+ adc_chan_result->measurement = 0;
+ }
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->physical = (int32_t)adc_chan_result->measurement;
+ /* Change to .001 deg C */
+ adc_chan_result->physical -= KELVINMIL_DEGMIL;
+ adc_chan_result->measurement <<= 1;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_pmic_therm);
+
+/* Scales the ADC code to 0.001 degrees C using the map
+ * table for the XO thermistor.
+ */
+int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ int32_t rt_r25;
+ int32_t offset = chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+
+ rt_r25 = adc_code - offset;
+
+ pm8xxx_adc_map_linear(adcmap_ntcg_104ef_104fb,
+ ARRAY_SIZE(adcmap_ntcg_104ef_104fb),
+ rt_r25, &adc_chan_result->physical);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_tdkntcg_therm);
+
+int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *btm_param)
+{
+ int rc;
+
+ rc = pm8xxx_adc_map_linear(
+ adcmap_btm_threshold,
+ ARRAY_SIZE(adcmap_btm_threshold),
+ btm_param->low_thr_temp,
+ &btm_param->low_thr_voltage);
+
+ if (!rc) {
+ rc = pm8xxx_adc_map_linear(
+ adcmap_btm_threshold,
+ ARRAY_SIZE(adcmap_btm_threshold),
+ btm_param->high_thr_temp,
+ &btm_param->high_thr_voltage);
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_batt_scaler);
diff --git a/drivers/hwmon/pm8xxx-adc.c b/drivers/hwmon/pm8xxx-adc.c
new file mode 100644
index 0000000..152eb40
--- /dev/null
+++ b/drivers/hwmon/pm8xxx-adc.c
@@ -0,0 +1,1286 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Qualcomm's PM8921/PM8018 ADC Arbiter driver
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/hwmon.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/wakelock.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+
+/* User Bank register set */
+#define PM8XXX_ADC_ARB_USRP_CNTRL1 0x197
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB BIT(0)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV2 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV3 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV4 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV5 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_EOC BIT(6)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_REQ BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL 0x198
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_PREMUX0 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_PREMUX1 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_ANA_PARAM 0x199
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM 0x19A
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_RSV 0x19B
+#define PM8XXX_ADC_ARB_USRP_RSV_RST BIT(0)
+#define PM8XXX_ADC_ARB_USRP_RSV_DTEST0 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_RSV_DTEST1 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_RSV_OP BIT(3)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_RSV_TRM BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_DATA0 0x19D
+#define PM8XXX_ADC_ARB_USRP_DATA1 0x19C
+
+#define PM8XXX_ADC_ARB_BTM_CNTRL1 0x17e
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_EOC BIT(6)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_REQ BIT(7)
+
+#define PM8XXX_ADC_ARB_BTM_CNTRL2 0x18c
+#define PM8XXX_ADC_ARB_BTM_AMUX_CNTRL 0x17f
+#define PM8XXX_ADC_ARB_BTM_ANA_PARAM 0x180
+#define PM8XXX_ADC_ARB_BTM_DIG_PARAM 0x181
+#define PM8XXX_ADC_ARB_BTM_RSV 0x182
+#define PM8XXX_ADC_ARB_BTM_DATA1 0x183
+#define PM8XXX_ADC_ARB_BTM_DATA0 0x184
+#define PM8XXX_ADC_ARB_BTM_BAT_COOL_THR1 0x185
+#define PM8XXX_ADC_ARB_BTM_BAT_COOL_THR0 0x186
+#define PM8XXX_ADC_ARB_BTM_BAT_WARM_THR1 0x187
+#define PM8XXX_ADC_ARB_BTM_BAT_WARM_THR0 0x188
+
+#define PM8XXX_ADC_ARB_ANA_DIG 0xa0
+#define PM8XXX_ADC_BTM_RSV 0x10
+#define PM8XXX_ADC_AMUX_MPP_SEL 2
+#define PM8XXX_ADC_AMUX_SEL 4
+#define PM8XXX_ADC_RSV_IP_SEL 4
+#define PM8XXX_ADC_BTM_CHANNEL_SEL 4
+#define PM8XXX_MAX_CHANNEL_PROPERTIES 2
+#define PM8XXX_ADC_IRQ_0 0
+#define PM8XXX_ADC_IRQ_1 1
+#define PM8XXX_ADC_IRQ_2 2
+#define PM8XXX_ADC_BTM_INTERVAL_SEL_MASK 0xF
+#define PM8XXX_ADC_BTM_INTERVAL_SEL_SHIFT 2
+#define PM8XXX_ADC_BTM_DECIMATION_SEL 5
+#define PM8XXX_ADC_MUL 10
+#define PM8XXX_ADC_CONV_TIME_MIN 2000
+#define PM8XXX_ADC_CONV_TIME_MAX 2100
+#define PM8XXX_ADC_MPP_SETTLE_TIME_MIN 200
+#define PM8XXX_ADC_MPP_SETTLE_TIME_MAX 200
+#define PM8XXX_ADC_PA_THERM_VREG_UV_MIN 1800000
+#define PM8XXX_ADC_PA_THERM_VREG_UV_MAX 1800000
+#define PM8XXX_ADC_PA_THERM_VREG_UA_LOAD 100000
+
+struct pm8xxx_adc {
+ struct device *dev;
+ struct pm8xxx_adc_properties *adc_prop;
+ int adc_irq;
+ struct mutex adc_lock;
+ struct mutex mpp_adc_lock;
+ spinlock_t btm_lock;
+ uint32_t adc_num_channel;
+ uint32_t adc_num_board_channel;
+ struct completion adc_rslt_completion;
+ struct pm8xxx_adc_amux *adc_channel;
+ int btm_warm_irq;
+ int btm_cool_irq;
+ struct dentry *dent;
+ struct work_struct warm_work;
+ struct work_struct cool_work;
+ uint32_t mpp_base;
+ struct device *hwmon;
+ struct wake_lock adc_wakelock;
+ int msm_suspend_check;
+ struct pm8xxx_adc_amux_properties *conv;
+ struct pm8xxx_adc_arb_btm_param batt[0];
+ struct sensor_device_attribute sens_attr[0];
+};
+
+struct pm8xxx_adc_amux_properties {
+ uint32_t amux_channel;
+ uint32_t decimation;
+ uint32_t amux_ip_rsv;
+ uint32_t amux_mpp_channel;
+ struct pm8xxx_adc_chan_properties chan_prop[0];
+};
+
+static const struct pm8xxx_adc_scaling_ratio pm8xxx_amux_scaling_ratio[] = {
+ {1, 1},
+ {1, 3},
+ {1, 4},
+ {1, 6}
+};
+
+static struct pm8xxx_adc *pmic_adc;
+
+static struct pm8xxx_adc_scale_fn adc_scale_fn[] = {
+ [ADC_SCALE_DEFAULT] = {pm8xxx_adc_scale_default},
+ [ADC_SCALE_BATT_THERM] = {pm8xxx_adc_scale_batt_therm},
+ [ADC_SCALE_PA_THERM] = {pm8xxx_adc_scale_pa_therm},
+ [ADC_SCALE_PMIC_THERM] = {pm8xxx_adc_scale_pmic_therm},
+ [ADC_SCALE_XOTHERM] = {pm8xxx_adc_tdkntcg_therm},
+};
+
+/* On PM8921 ADC the MPP needs to first be configured
+as an analog input to the AMUX pre-mux channel before
+issuing a read request. PM8921 MPP 8 is mapped to AMUX8
+and is common between remote processor's.
+On PM8018 ADC the MPP is directly connected to the AMUX
+pre-mux. Therefore clients of the PM8018 MPP do not need
+to configure the MPP as an analog input to the pre-mux.
+Clients can directly issue request on the pre-mux AMUX
+channel to read the ADC on the MPP */
+static struct pm8xxx_mpp_config_data pm8xxx_adc_mpp_config = {
+ .type = PM8XXX_MPP_TYPE_A_INPUT,
+ /* AMUX6 is dedicated to be used for apps processor */
+ .level = PM8XXX_MPP_AIN_AMUX_CH6,
+ .control = PM8XXX_MPP_AOUT_CTRL_DISABLE,
+};
+
+/* MPP Configuration for default settings */
+static struct pm8xxx_mpp_config_data pm8xxx_adc_mpp_unconfig = {
+ .type = PM8XXX_MPP_TYPE_SINK,
+ .level = PM8XXX_MPP_AIN_AMUX_CH5,
+ .control = PM8XXX_MPP_AOUT_CTRL_DISABLE,
+};
+
+static bool pm8xxx_adc_calib_first_adc;
+static bool pm8xxx_adc_initialized, pm8xxx_adc_calib_device_init;
+
+static int32_t pm8xxx_adc_arb_cntrl(uint32_t arb_cntrl,
+ uint32_t channel)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i, rc;
+ u8 data_arb_cntrl = 0;
+
+ if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("PM8xxx ADC request made after suspend_noirq "
+ "with channel: %d\n", channel);
+ data_arb_cntrl |= PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB;
+ wake_lock(&adc_pmic->adc_wakelock);
+ }
+
+ /* Write twice to the CNTRL register for the arbiter settings
+ to take into effect */
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_writeb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ if (rc < 0) {
+ pr_err("PM8xxx arb cntrl write failed with %d\n", rc);
+ return rc;
+ }
+ }
+
+ if (arb_cntrl) {
+ data_arb_cntrl |= PM8XXX_ADC_ARB_USRP_CNTRL1_REQ;
+ rc = pm8xxx_writeb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ } else
+ wake_unlock(&adc_pmic->adc_wakelock);
+
+ return 0;
+}
+
+static int32_t pm8xxx_adc_patherm_power(bool on)
+{
+ static struct regulator *pa_therm;
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0;
+ if (on) {
+ pa_therm = regulator_get(adc_pmic->dev,
+ "pa_therm");
+ if (IS_ERR(pa_therm)) {
+ rc = PTR_ERR(pa_therm);
+ pr_err("failed to request pa_therm vreg "
+ "with error %d\n", rc);
+ return rc;
+ }
+
+ rc = regulator_set_voltage(pa_therm,
+ PM8XXX_ADC_PA_THERM_VREG_UV_MIN,
+ PM8XXX_ADC_PA_THERM_VREG_UV_MAX);
+ if (rc < 0) {
+ pr_err("failed to set the voltage for "
+ "pa_therm with error %d\n", rc);
+ goto fail;
+ }
+
+ rc = regulator_set_optimum_mode(pa_therm,
+ PM8XXX_ADC_PA_THERM_VREG_UA_LOAD);
+ if (rc < 0) {
+ pr_err("failed to set optimum mode for "
+ "pa_therm with error %d\n", rc);
+ goto fail;
+ }
+
+ if (regulator_enable(pa_therm)) {
+ pr_err("failed to enable pa_therm vreg with "
+ "error %d\n", rc);
+ goto fail;
+ }
+ } else {
+ if (pa_therm != NULL) {
+ regulator_disable(pa_therm);
+ regulator_put(pa_therm);
+ }
+ }
+
+ return rc;
+fail:
+ regulator_put(pa_therm);
+ return rc;
+}
+
+static int32_t pm8xxx_adc_channel_power_enable(uint32_t channel,
+ bool power_cntrl)
+{
+ int rc = 0;
+
+ switch (channel)
+ case ADC_MPP_1_AMUX8:
+ pm8xxx_adc_patherm_power(power_cntrl);
+
+ return rc;
+}
+
+
+static uint32_t pm8xxx_adc_read_reg(uint32_t reg, u8 *data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc;
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent, reg, data);
+ if (rc < 0) {
+ pr_err("PM8xxx adc read reg %d failed with %d\n", reg, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static uint32_t pm8xxx_adc_write_reg(uint32_t reg, u8 data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc;
+
+ rc = pm8xxx_writeb(adc_pmic->dev->parent, reg, data);
+ if (rc < 0) {
+ pr_err("PM8xxx adc write reg %d failed with %d\n", reg, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int32_t pm8xxx_adc_configure(
+ struct pm8xxx_adc_amux_properties *chan_prop)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ u8 data_amux_chan = 0, data_arb_rsv = 0, data_dig_param = 0;
+ int rc;
+
+ data_amux_chan |= chan_prop->amux_channel << PM8XXX_ADC_AMUX_SEL;
+
+ if (chan_prop->amux_mpp_channel)
+ data_amux_chan |= chan_prop->amux_mpp_channel <<
+ PM8XXX_ADC_AMUX_MPP_SEL;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_AMUX_CNTRL,
+ data_amux_chan);
+ if (rc < 0)
+ return rc;
+
+ data_arb_rsv &= (PM8XXX_ADC_ARB_USRP_RSV_RST |
+ PM8XXX_ADC_ARB_USRP_RSV_DTEST0 |
+ PM8XXX_ADC_ARB_USRP_RSV_DTEST1 |
+ PM8XXX_ADC_ARB_USRP_RSV_OP |
+ PM8XXX_ADC_ARB_USRP_RSV_TRM);
+ data_arb_rsv |= chan_prop->amux_ip_rsv << PM8XXX_ADC_RSV_IP_SEL;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_RSV, data_arb_rsv);
+ if (rc < 0)
+ return rc;
+
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_DIG_PARAM,
+ &data_dig_param);
+ if (rc < 0)
+ return rc;
+
+ /* Default 2.4Mhz clock rate */
+ /* Client chooses the decimation */
+ switch (chan_prop->decimation) {
+ case ADC_DECIMATION_TYPE1:
+ data_dig_param |= PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0;
+ break;
+ case ADC_DECIMATION_TYPE2:
+ data_dig_param |= (PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0
+ | PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE1);
+ break;
+ default:
+ data_dig_param |= PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0;
+ break;
+ }
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_DIG_PARAM,
+ PM8XXX_ADC_ARB_ANA_DIG);
+ if (rc < 0)
+ return rc;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_ANA_PARAM,
+ PM8XXX_ADC_ARB_ANA_DIG);
+ if (rc < 0)
+ return rc;
+
+ if (!pm8xxx_adc_calib_first_adc)
+ enable_irq(adc_pmic->adc_irq);
+
+ rc = pm8xxx_adc_arb_cntrl(1, data_amux_chan);
+ if (rc < 0) {
+ pr_err("Configuring ADC Arbiter"
+ "enable failed with %d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static uint32_t pm8xxx_adc_read_adc_code(int32_t *data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ uint8_t rslt_lsb, rslt_msb;
+ int32_t rc, max_ideal_adc_code = 1 << adc_pmic->adc_prop->bitresolution;
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_DATA0, &rslt_lsb);
+ if (rc < 0) {
+ pr_err("PM8xxx adc result read failed with %d\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_DATA1, &rslt_msb);
+ if (rc < 0) {
+ pr_err("PM8xxx adc result read failed with %d\n", rc);
+ return rc;
+ }
+
+ *data = (rslt_msb << 8) | rslt_lsb;
+
+ /* Use the midpoint to determine underflow or overflow */
+ if (*data > max_ideal_adc_code + (max_ideal_adc_code >> 1))
+ *data |= ((1 << (8 * sizeof(*data) -
+ adc_pmic->adc_prop->bitresolution)) - 1) <<
+ adc_pmic->adc_prop->bitresolution;
+
+ /* Default value for switching off the arbiter after reading
+ the ADC value. Bit 0 set to 0. */
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void pm8xxx_adc_btm_warm_scheduler_fn(struct work_struct *work)
+{
+ struct pm8xxx_adc *adc_pmic = container_of(work, struct pm8xxx_adc,
+ warm_work);
+ unsigned long flags = 0;
+ bool warm_status;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ warm_status = irq_read_line(adc_pmic->btm_warm_irq);
+ if (adc_pmic->batt->btm_warm_fn != NULL)
+ adc_pmic->batt->btm_warm_fn(warm_status);
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+}
+
+static void pm8xxx_adc_btm_cool_scheduler_fn(struct work_struct *work)
+{
+ struct pm8xxx_adc *adc_pmic = container_of(work, struct pm8xxx_adc,
+ cool_work);
+ unsigned long flags = 0;
+ bool cool_status;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ cool_status = irq_read_line(adc_pmic->btm_cool_irq);
+ if (adc_pmic->batt->btm_cool_fn != NULL)
+ adc_pmic->batt->btm_cool_fn(cool_status);
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+}
+
+static irqreturn_t pm8xxx_adc_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *adc_8xxx = dev_id;
+
+ disable_irq_nosync(adc_8xxx->adc_irq);
+
+ if (pm8xxx_adc_calib_first_adc)
+ return IRQ_HANDLED;
+ /* TODO Handle spurius interrupt condition */
+ complete(&adc_8xxx->adc_rslt_completion);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pm8xxx_btm_warm_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *btm_8xxx = dev_id;
+
+ schedule_work(&btm_8xxx->warm_work);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pm8xxx_btm_cool_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *btm_8xxx = dev_id;
+
+ schedule_work(&btm_8xxx->cool_work);
+
+ return IRQ_HANDLED;
+}
+
+static uint32_t pm8xxx_adc_calib_device(void)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ struct pm8xxx_adc_amux_properties conv;
+ int rc, offset_adc, slope_adc, calib_read_1, calib_read_2;
+ u8 data_arb_usrp_cntrl1 = 0;
+
+ conv.amux_channel = CHANNEL_125V;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV1;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_1);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ conv.amux_channel = CHANNEL_625MV;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV1;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_2);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ slope_adc = (((calib_read_1 - calib_read_2) << PM8XXX_ADC_MUL)/
+ PM8XXX_CHANNEL_ADC_625_MV);
+ offset_adc = calib_read_2 -
+ ((slope_adc * PM8XXX_CHANNEL_ADC_625_MV) >>
+ PM8XXX_ADC_MUL);
+
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].offset
+ = offset_adc;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dy =
+ (calib_read_1 - calib_read_2);
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dx
+ = PM8XXX_CHANNEL_ADC_625_MV;
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ return rc;
+ }
+ /* Ratiometric Calibration */
+ conv.amux_channel = CHANNEL_MUXOFF;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV5;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_1);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ conv.amux_channel = CHANNEL_MUXOFF;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV4;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_2);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ slope_adc = (((calib_read_1 - calib_read_2) << PM8XXX_ADC_MUL)/
+ adc_pmic->adc_prop->adc_vdd_reference);
+ offset_adc = calib_read_2 -
+ ((slope_adc * adc_pmic->adc_prop->adc_vdd_reference)
+ >> PM8XXX_ADC_MUL);
+
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].offset
+ = offset_adc;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dy =
+ (calib_read_1 - calib_read_2);
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dx =
+ adc_pmic->adc_prop->adc_vdd_reference;
+calib_fail:
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ }
+
+ return rc;
+}
+
+uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i = 0, rc = 0, rc_fail, amux_prescaling, scale_type;
+ enum pm8xxx_adc_premux_mpp_scale_type mpp_scale;
+
+ if (!pm8xxx_adc_initialized)
+ return -ENODEV;
+
+ if (!pm8xxx_adc_calib_device_init) {
+ if (pm8xxx_adc_calib_device() == 0)
+ pm8xxx_adc_calib_device_init = true;
+ }
+
+ mutex_lock(&adc_pmic->adc_lock);
+
+ for (i = 0; i < adc_pmic->adc_num_channel; i++) {
+ if (channel == adc_pmic->adc_channel[i].channel_name)
+ break;
+ }
+
+ if (i == adc_pmic->adc_num_channel) {
+ rc = -EBADF;
+ goto fail_unlock;
+ }
+
+ if (channel < PM8XXX_CHANNEL_MPP_SCALE1_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_0;
+ adc_pmic->conv->amux_channel = channel;
+ } else if (channel >= PM8XXX_CHANNEL_MPP_SCALE1_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_1;
+ adc_pmic->conv->amux_channel = channel %
+ PM8XXX_CHANNEL_MPP_SCALE1_IDX;
+ } else if (channel >= PM8XXX_CHANNEL_MPP_SCALE3_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_1_DIV3;
+ adc_pmic->conv->amux_channel = channel %
+ PM8XXX_CHANNEL_MPP_SCALE3_IDX;
+ }
+
+ adc_pmic->conv->amux_mpp_channel = mpp_scale;
+ adc_pmic->conv->amux_ip_rsv = adc_pmic->adc_channel[i].adc_rsv;
+ adc_pmic->conv->decimation = adc_pmic->adc_channel[i].adc_decimation;
+ amux_prescaling = adc_pmic->adc_channel[i].chan_path_prescaling;
+
+ adc_pmic->conv->chan_prop->offset_gain_numerator =
+ pm8xxx_amux_scaling_ratio[amux_prescaling].num;
+ adc_pmic->conv->chan_prop->offset_gain_denominator =
+ pm8xxx_amux_scaling_ratio[amux_prescaling].den;
+
+ rc = pm8xxx_adc_channel_power_enable(channel, true);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+
+ rc = pm8xxx_adc_configure(adc_pmic->conv);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ wait_for_completion(&adc_pmic->adc_rslt_completion);
+
+ rc = pm8xxx_adc_read_adc_code(&result->adc_code);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ scale_type = adc_pmic->adc_channel[i].adc_scale_fn;
+ if (scale_type >= ADC_SCALE_NONE) {
+ rc = -EBADF;
+ goto fail;
+ }
+
+ adc_scale_fn[scale_type].chan(result->adc_code,
+ adc_pmic->adc_prop, adc_pmic->conv->chan_prop, result);
+
+ rc = pm8xxx_adc_channel_power_enable(channel, false);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+
+ mutex_unlock(&adc_pmic->adc_lock);
+
+ return 0;
+fail:
+ rc_fail = pm8xxx_adc_channel_power_enable(channel, false);
+ if (rc_fail)
+ pr_err("pm8xxx adc power disable failed\n");
+fail_unlock:
+ mutex_unlock(&adc_pmic->adc_lock);
+ pr_err("pm8xxx adc error with %d\n", rc);
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_read);
+
+uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0;
+
+ if (!adc_pmic->mpp_base) {
+ rc = -EINVAL;
+ pr_info("PM8xxx MPP base invalid with error %d\n", rc);
+ return rc;
+ }
+
+ if (mpp_num == PM8XXX_AMUX_MPP_8) {
+ rc = -EINVAL;
+ pr_info("PM8xxx MPP8 is already configured "
+ "to AMUX8. Use pm8xxx_adc_read() instead.\n");
+ return rc;
+ }
+
+ mutex_lock(&adc_pmic->mpp_adc_lock);
+
+ rc = pm8xxx_mpp_config(((mpp_num - 1) + adc_pmic->mpp_base),
+ &pm8xxx_adc_mpp_config);
+ if (rc < 0) {
+ pr_err("pm8xxx adc mpp config error with %d\n", rc);
+ goto fail;
+ }
+
+ usleep_range(PM8XXX_ADC_MPP_SETTLE_TIME_MIN,
+ PM8XXX_ADC_MPP_SETTLE_TIME_MAX);
+
+ rc = pm8xxx_adc_read(channel, result);
+ if (rc < 0)
+ pr_err("pm8xxx adc read error with %d\n", rc);
+
+ rc = pm8xxx_mpp_config(((mpp_num - 1) + adc_pmic->mpp_base),
+ &pm8xxx_adc_mpp_unconfig);
+ if (rc < 0)
+ pr_err("pm8xxx adc mpp config error with %d\n", rc);
+fail:
+ mutex_unlock(&adc_pmic->mpp_adc_lock);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_mpp_config_read);
+
+uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *btm_param)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ u8 data_btm_cool_thr0, data_btm_cool_thr1;
+ u8 data_btm_warm_thr0, data_btm_warm_thr1;
+ u8 arb_btm_cntrl1;
+ unsigned long flags = 0;
+ int rc;
+
+ if (adc_pmic == NULL) {
+ pr_err("PMIC ADC not valid\n");
+ return -EINVAL;
+ }
+
+ if ((btm_param->btm_cool_fn == NULL) &&
+ (btm_param->btm_warm_fn == NULL)) {
+ pr_err("No BTM warm/cool notification??\n");
+ return -EINVAL;
+ }
+
+ rc = pm8xxx_adc_batt_scaler(btm_param);
+ if (rc < 0) {
+ pr_err("Failed to lookup the BTM thresholds\n");
+ return rc;
+ }
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+
+ data_btm_cool_thr0 = ((btm_param->low_thr_voltage << 24) >> 24);
+ data_btm_cool_thr1 = ((btm_param->low_thr_voltage << 16) >> 24);
+ data_btm_warm_thr0 = ((btm_param->high_thr_voltage << 24) >> 24);
+ data_btm_warm_thr1 = ((btm_param->high_thr_voltage << 16) >> 24);
+
+ if (btm_param->btm_cool_fn != NULL) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_COOL_THR0,
+ data_btm_cool_thr0);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_COOL_THR1,
+ data_btm_cool_thr1);
+ if (rc < 0)
+ goto write_err;
+
+ adc_pmic->batt->btm_cool_fn = btm_param->btm_cool_fn;
+ }
+
+ if (btm_param->btm_warm_fn != NULL) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_WARM_THR0,
+ data_btm_warm_thr0);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_WARM_THR1,
+ data_btm_warm_thr1);
+ if (rc < 0)
+ goto write_err;
+
+ adc_pmic->batt->btm_warm_fn = btm_param->btm_warm_fn;
+ }
+
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_BTM_CNTRL1, &arb_btm_cntrl1);
+ if (rc < 0)
+ goto bail_out;
+
+ btm_param->interval &= PM8XXX_ADC_BTM_INTERVAL_SEL_MASK;
+ arb_btm_cntrl1 |=
+ btm_param->interval << PM8XXX_ADC_BTM_INTERVAL_SEL_SHIFT;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1, arb_btm_cntrl1);
+ if (rc < 0)
+ goto write_err;
+
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+
+ return rc;
+bail_out:
+write_err:
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ pr_debug("%s: with error code %d\n", __func__, rc);
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_configure);
+
+static uint32_t pm8xxx_adc_btm_read(uint32_t channel)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc, i;
+ u8 arb_btm_dig_param, arb_btm_ana_param, arb_btm_rsv;
+ u8 arb_btm_amux_cntrl, data_arb_btm_cntrl = 0;
+ unsigned long flags;
+
+ arb_btm_amux_cntrl = channel << PM8XXX_ADC_BTM_CHANNEL_SEL;
+ arb_btm_rsv = adc_pmic->adc_channel[channel].adc_rsv;
+ arb_btm_dig_param = arb_btm_ana_param = PM8XXX_ADC_ARB_ANA_DIG;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_AMUX_CNTRL,
+ arb_btm_amux_cntrl);
+ if (rc < 0)
+ goto write_err;
+
+ arb_btm_rsv = PM8XXX_ADC_BTM_RSV;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_RSV, arb_btm_rsv);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_DIG_PARAM,
+ arb_btm_dig_param);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_ANA_PARAM,
+ arb_btm_ana_param);
+ if (rc < 0)
+ goto write_err;
+
+ data_arb_btm_cntrl |= PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM;
+
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0)
+ goto write_err;
+ }
+
+ data_arb_btm_cntrl |= PM8XXX_ADC_ARB_BTM_CNTRL1_REQ
+ | PM8XXX_ADC_ARB_BTM_CNTRL1_SEL_OP_MODE;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0)
+ goto write_err;
+
+ if (pmic_adc->batt->btm_warm_fn != NULL)
+ enable_irq(adc_pmic->btm_warm_irq);
+
+ if (pmic_adc->batt->btm_cool_fn != NULL)
+ enable_irq(adc_pmic->btm_cool_irq);
+
+write_err:
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+}
+
+uint32_t pm8xxx_adc_btm_start(void)
+{
+ return pm8xxx_adc_btm_read(CHANNEL_BATT_THERM);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_start);
+
+uint32_t pm8xxx_adc_btm_end(void)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i, rc;
+ u8 data_arb_btm_cntrl;
+ unsigned long flags;
+
+ disable_irq_nosync(adc_pmic->btm_warm_irq);
+ disable_irq_nosync(adc_pmic->btm_cool_irq);
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ /* Set BTM registers to Disable mode */
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ &data_arb_btm_cntrl);
+ if (rc < 0) {
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+ }
+
+ data_arb_btm_cntrl |= ~PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM;
+ /* Write twice to the CNTRL register for the arbiter settings
+ to take into effect */
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0) {
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+ }
+ }
+
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_end);
+
+static ssize_t pm8xxx_adc_show(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ struct pm8xxx_adc_chan_result result;
+ int rc = -1;
+
+ if (attr->index < adc_pmic->adc_num_channel)
+ rc = pm8xxx_adc_read(attr->index, &result);
+
+ if (rc)
+ return 0;
+
+ return snprintf(buf, sizeof(struct pm8xxx_adc_chan_result),
+ "Result:%lld Raw:%d\n",
+ result.physical, result.adc_code);
+}
+
+static int get_adc(void *data, u64 *val)
+{
+ struct pm8xxx_adc_chan_result result;
+ int i = (int)data;
+ int rc;
+
+ rc = pm8xxx_adc_read(i, &result);
+ if (!rc)
+ pr_info("ADC value raw:%x physical:%lld\n",
+ result.adc_code, result.physical);
+ *val = result.physical;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reg_fops, get_adc, NULL, "%llu\n");
+
+static int get_mpp_adc(void *data, u64 *val)
+{
+ struct pm8xxx_adc_chan_result result;
+ int i = (int)data;
+ int rc;
+
+ rc = pm8xxx_adc_mpp_config_read(i,
+ ADC_MPP_1_AMUX6, &result);
+ if (!rc)
+ pr_info("ADC MPP value raw:%x physical:%lld\n",
+ result.adc_code, result.physical);
+ *val = result.physical;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reg_mpp_fops, get_mpp_adc, NULL, "%llu\n");
+
+#ifdef CONFIG_DEBUG_FS
+static void create_debugfs_entries(void)
+{
+ int i = 0;
+ pmic_adc->dent = debugfs_create_dir("pm8xxx_adc", NULL);
+
+ if (IS_ERR(pmic_adc->dent)) {
+ pr_err("pmic adc debugfs dir not created\n");
+ return;
+ }
+
+ for (i = 0; i < pmic_adc->adc_num_board_channel; i++)
+ debugfs_create_file(pmic_adc->adc_channel[i].name,
+ 0644, pmic_adc->dent,
+ (void *)pmic_adc->adc_channel[i].channel_name,
+ ®_fops);
+}
+#else
+static inline void create_debugfs_entries(void)
+{
+}
+#endif
+static struct sensor_device_attribute pm8xxx_adc_attr =
+ SENSOR_ATTR(NULL, S_IRUGO, pm8xxx_adc_show, NULL, 0);
+
+static int32_t pm8xxx_adc_init_hwmon(struct platform_device *pdev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0, i;
+
+ for (i = 0; i < pmic_adc->adc_num_board_channel; i++) {
+ pm8xxx_adc_attr.index = adc_pmic->adc_channel[i].channel_name;
+ pm8xxx_adc_attr.dev_attr.attr.name =
+ adc_pmic->adc_channel[i].name;
+ memcpy(&adc_pmic->sens_attr[i], &pm8xxx_adc_attr,
+ sizeof(pm8xxx_adc_attr));
+ rc = device_create_file(&pdev->dev,
+ &adc_pmic->sens_attr[i].dev_attr);
+ if (rc) {
+ dev_err(&pdev->dev, "device_create_file failed for "
+ "dev %s\n",
+ adc_pmic->adc_channel[i].name);
+ goto hwmon_err_sens;
+ }
+ }
+
+ return 0;
+hwmon_err_sens:
+ pr_info("Init HWMON failed for pm8xxx_adc with %d\n", rc);
+ return rc;
+}
+
+#ifdef CONFIG_PM
+static int pm8xxx_adc_suspend_noirq(struct device *dev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8xxx_adc_resume_noirq(struct device *dev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8xxx_adc_dev_pm_ops = {
+ .suspend_noirq = pm8xxx_adc_suspend_noirq,
+ .resume_noirq = pm8xxx_adc_resume_noirq,
+};
+
+#define PM8XXX_ADC_DEV_PM_OPS (&pm8xxx_adc_dev_pm_ops)
+#else
+#define PM8XXX_ADC_DEV_PM_OPS NULL
+#endif
+
+static int __devexit pm8xxx_adc_teardown(struct platform_device *pdev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i;
+
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
+ platform_set_drvdata(pdev, NULL);
+ pmic_adc = NULL;
+ for (i = 0; i < adc_pmic->adc_num_board_channel; i++)
+ device_remove_file(adc_pmic->dev,
+ &adc_pmic->sens_attr[i].dev_attr);
+ pm8xxx_adc_initialized = false;
+
+ return 0;
+}
+
+static int __devinit pm8xxx_adc_probe(struct platform_device *pdev)
+{
+ const struct pm8xxx_adc_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8xxx_adc *adc_pmic;
+ struct pm8xxx_adc_amux_properties *adc_amux_prop;
+ int rc = 0;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data?\n");
+ return -EINVAL;
+ }
+
+ adc_pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8xxx_adc) +
+ sizeof(struct pm8xxx_adc_arb_btm_param) +
+ (sizeof(struct sensor_device_attribute) *
+ pdata->adc_num_board_channel), GFP_KERNEL);
+ if (!adc_pmic) {
+ dev_err(&pdev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ adc_amux_prop = devm_kzalloc(&pdev->dev,
+ sizeof(struct pm8xxx_adc_amux_properties) +
+ sizeof(struct pm8xxx_adc_chan_properties)
+ , GFP_KERNEL);
+ if (!adc_amux_prop) {
+ dev_err(&pdev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ adc_pmic->dev = &pdev->dev;
+ adc_pmic->adc_prop = pdata->adc_prop;
+ adc_pmic->conv = adc_amux_prop;
+ init_completion(&adc_pmic->adc_rslt_completion);
+ adc_pmic->adc_channel = pdata->adc_channel;
+ adc_pmic->adc_num_board_channel = pdata->adc_num_board_channel;
+ adc_pmic->adc_num_channel = ADC_MPP_2_CHANNEL_NONE;
+ adc_pmic->mpp_base = pdata->adc_mpp_base;
+
+ mutex_init(&adc_pmic->adc_lock);
+ mutex_init(&adc_pmic->mpp_adc_lock);
+ spin_lock_init(&adc_pmic->btm_lock);
+
+ adc_pmic->adc_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_0);
+ if (adc_pmic->adc_irq < 0)
+ return adc_pmic->adc_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->adc_irq,
+ pm8xxx_adc_isr,
+ IRQF_TRIGGER_RISING, "pm8xxx_adc_interrupt", adc_pmic);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to request adc irq "
+ "with error %d\n", rc);
+ }
+
+ disable_irq_nosync(adc_pmic->adc_irq);
+
+ adc_pmic->btm_warm_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_1);
+ if (adc_pmic->btm_warm_irq < 0)
+ return adc_pmic->btm_warm_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->btm_warm_irq,
+ pm8xxx_btm_warm_isr,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "pm8xxx_btm_warm_interrupt", adc_pmic);
+ if (rc) {
+ pr_err("btm warm irq failed %d with interrupt number %d\n",
+ rc, adc_pmic->btm_warm_irq);
+ dev_err(&pdev->dev, "failed to request btm irq\n");
+ }
+
+ disable_irq_nosync(adc_pmic->btm_warm_irq);
+
+ adc_pmic->btm_cool_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_2);
+ if (adc_pmic->btm_cool_irq < 0)
+ return adc_pmic->btm_cool_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->btm_cool_irq,
+ pm8xxx_btm_cool_isr,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "pm8xxx_btm_cool_interrupt", adc_pmic);
+ if (rc) {
+ pr_err("btm cool irq failed with return %d and number %d\n",
+ rc, adc_pmic->btm_cool_irq);
+ dev_err(&pdev->dev, "failed to request btm irq\n");
+ }
+
+ disable_irq_nosync(adc_pmic->btm_cool_irq);
+ platform_set_drvdata(pdev, adc_pmic);
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pm8xxx_adc_wakelock");
+ adc_pmic->msm_suspend_check = 0;
+ pmic_adc = adc_pmic;
+
+ INIT_WORK(&adc_pmic->warm_work, pm8xxx_adc_btm_warm_scheduler_fn);
+ INIT_WORK(&adc_pmic->cool_work, pm8xxx_adc_btm_cool_scheduler_fn);
+ create_debugfs_entries();
+ pm8xxx_adc_calib_first_adc = false;
+ pm8xxx_adc_calib_device_init = false;
+ pm8xxx_adc_initialized = true;
+
+ rc = pm8xxx_adc_init_hwmon(pdev);
+ if (rc) {
+ pr_err("pm8xxx adc init hwmon failed with %d\n", rc);
+ dev_err(&pdev->dev, "failed to initialize pm8xxx hwmon adc\n");
+ }
+ adc_pmic->hwmon = hwmon_device_register(adc_pmic->dev);
+ return 0;
+}
+
+static struct platform_driver pm8xxx_adc_driver = {
+ .probe = pm8xxx_adc_probe,
+ .remove = __devexit_p(pm8xxx_adc_teardown),
+ .driver = {
+ .name = PM8XXX_ADC_DEV_NAME,
+ .owner = THIS_MODULE,
+ .pm = PM8XXX_ADC_DEV_PM_OPS,
+ },
+};
+
+static int __init pm8xxx_adc_init(void)
+{
+ return platform_driver_register(&pm8xxx_adc_driver);
+}
+module_init(pm8xxx_adc_init);
+
+static void __exit pm8xxx_adc_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_adc_driver);
+}
+module_exit(pm8xxx_adc_exit);
+
+MODULE_ALIAS("platform:" PM8XXX_ADC_DEV_NAME);
+MODULE_DESCRIPTION("PMIC8921/8018 ADC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index e5bd99b..c9a5ba2 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -17,7 +17,7 @@
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/input/mt.h>
+#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
@@ -539,21 +539,19 @@
if (!finger[id].status)
continue;
- input_mt_slot(input_dev, id);
- input_mt_report_slot_state(input_dev, MT_TOOL_FINGER,
- finger[id].status != MXT_RELEASE);
+ input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
+ finger[id].status != MXT_RELEASE ?
+ finger[id].area : 0);
+ input_report_abs(input_dev, ABS_MT_POSITION_X,
+ finger[id].x);
+ input_report_abs(input_dev, ABS_MT_POSITION_Y,
+ finger[id].y);
+ input_mt_sync(input_dev);
- if (finger[id].status != MXT_RELEASE) {
- finger_num++;
- input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
- finger[id].area);
- input_report_abs(input_dev, ABS_MT_POSITION_X,
- finger[id].x);
- input_report_abs(input_dev, ABS_MT_POSITION_Y,
- finger[id].y);
- } else {
+ if (finger[id].status == MXT_RELEASE)
finger[id].status = 0;
- }
+ else
+ finger_num++;
}
input_report_key(input_dev, BTN_TOUCH, finger_num > 0);
@@ -1429,7 +1427,6 @@
0, data->max_y, 0, 0);
/* For multi touch */
- input_mt_init_slots(input_dev, MXT_MAX_FINGER);
input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
0, MXT_MAX_AREA, 0, 0);
input_set_abs_params(input_dev, ABS_MT_POSITION_X,
diff --git a/drivers/mfd/pm8018-core.c b/drivers/mfd/pm8018-core.c
index 4dfc4cf..e60b97b 100644
--- a/drivers/mfd/pm8018-core.c
+++ b/drivers/mfd/pm8018-core.c
@@ -39,6 +39,9 @@
#define PM8018_VERSION_VALUE 0x08F0
#define PM8018_REVISION_MASK 0x000F
+#define REG_PM8018_PON_CNTRL_3 0x01D
+#define PM8018_RESTART_REASON_MASK 0x07
+
#define SINGLE_IRQ_RESOURCE(_name, _irq) \
{ \
.name = _name, \
@@ -325,6 +328,17 @@
return ret;
}
+static const char * const pm8018_restart_reason[] = {
+ [0] = "Unknown",
+ [1] = "Triggered from CBL (external charger)",
+ [2] = "Triggered from KPD (power key press)",
+ [3] = "Triggered from CHG (usb charger insertion)",
+ [4] = "Triggered from SMPL (sudden momentary power loss)",
+ [5] = "Triggered from RTC (real time clock)",
+ [6] = "Triggered by Hard Reset",
+ [7] = "Triggered by General Purpose Trigger",
+};
+
static const char * const pm8018_rev_names[] = {
[PM8XXX_REVISION_8018_TEST] = "test",
[PM8XXX_REVISION_8018_1p0] = "1.0",
@@ -386,6 +400,14 @@
} else {
WARN_ON(version != PM8XXX_VERSION_8018);
}
+ /* Log human readable restart reason */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_PM8018_PON_CNTRL_3, &val, 1);
+ if (rc) {
+ pr_err("Cannot read restart reason rc=%d\n", rc);
+ goto err_read_rev;
+ }
+ val &= PM8018_RESTART_REASON_MASK;
+ pr_info("PMIC Restart Reason: %s\n", pm8018_restart_reason[val]);
rc = pm8018_add_subdevices(pdata, pmic);
if (rc) {
diff --git a/drivers/mfd/pm8xxx-misc.c b/drivers/mfd/pm8xxx-misc.c
index cd5624f..00ac2ab 100644
--- a/drivers/mfd/pm8xxx-misc.c
+++ b/drivers/mfd/pm8xxx-misc.c
@@ -23,6 +23,7 @@
/* PON CTRL 1 register */
#define REG_PM8058_PON_CTRL_1 0x01C
#define REG_PM8921_PON_CTRL_1 0x01C
+#define REG_PM8018_PON_CTRL_1 0x01C
#define PON_CTRL_1_PULL_UP_MASK 0xE0
#define PON_CTRL_1_USB_PWR_EN 0x10
@@ -37,6 +38,7 @@
/* SLEEP CTRL register */
#define REG_PM8058_SLEEP_CTRL 0x02B
#define REG_PM8921_SLEEP_CTRL 0x10A
+#define REG_PM8018_SLEEP_CTRL 0x10A
#define SLEEP_CTRL_SMPL_EN_MASK 0x04
#define SLEEP_CTRL_SMPL_EN_RESET 0x04
@@ -81,6 +83,35 @@
return rc;
}
+static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset)
+{
+ int rc;
+
+ /* Enable SMPL if resetting is desired. */
+ rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL,
+ SLEEP_CTRL_SMPL_EN_MASK,
+ (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF));
+ if (rc) {
+ pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ /*
+ * Select action to perform (reset or shutdown) when PS_HOLD goes low.
+ * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that
+ * USB charging is enabled.
+ */
+ rc = pm8xxx_misc_masked_write(chip, REG_PM8018_PON_CTRL_1,
+ PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN
+ | PON_CTRL_1_WD_EN_MASK,
+ PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN
+ | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF));
+ if (rc)
+ pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset)
{
int rc;
@@ -201,6 +232,9 @@
/* Loop over all attached PMICs and call specific functions for them. */
list_for_each_entry(chip, &pm8xxx_misc_chips, link) {
switch (chip->version) {
+ case PM8XXX_VERSION_8018:
+ rc = __pm8018_reset_pwr_off(chip, reset);
+ break;
case PM8XXX_VERSION_8058:
rc = __pm8058_reset_pwr_off(chip, reset);
break;
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index d0c1392..e666bfc 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -87,6 +87,7 @@
unsigned int batt_id_channel;
unsigned int pmic_bms_irq[PM_BMS_MAX_INTS];
DECLARE_BITMAP(enabled_irqs, PM_BMS_MAX_INTS);
+ spinlock_t bms_output_lock;
};
static struct pm8921_bms_chip *the_chip;
@@ -156,6 +157,32 @@
return 0;
}
+#define HOLD_OREG_DATA BIT(1)
+static int pm_bms_lock_output_data(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ rc = pm_bms_masked_write(chip, BMS_CONTROL, HOLD_OREG_DATA,
+ HOLD_OREG_DATA);
+ if (rc) {
+ pr_err("couldnt lock bms output rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int pm_bms_unlock_output_data(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ rc = pm_bms_masked_write(chip, BMS_CONTROL, HOLD_OREG_DATA, 0);
+ if (rc) {
+ pr_err("fail to unlock BMS_CONTROL rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
#define SELECT_OUTPUT_DATA 0x1C
#define SELECT_OUTPUT_TYPE_SHIFT 2
#define OCV_FOR_RBATT 0x0
@@ -182,6 +209,18 @@
pr_err("invalid type %d asked to read\n", type);
return -EINVAL;
}
+
+ /* make sure the bms registers are locked */
+ rc = pm8xxx_readb(chip->dev->parent, BMS_CONTROL, ®);
+ if (rc) {
+ pr_err("fail to read BMS_OUTPUT0 for type %d rc = %d\n",
+ type, rc);
+ return rc;
+ }
+
+ /* Output register data must be held (locked) while reading output */
+ WARN_ON(!(reg && HOLD_OREG_DATA));
+
rc = pm_bms_masked_write(chip, BMS_CONTROL, SELECT_OUTPUT_DATA,
type << SELECT_OUTPUT_TYPE_SHIFT);
if (rc) {
@@ -779,11 +818,16 @@
int64_t *cc_mah)
{
int coulumb_counter;
+ unsigned long flags;
*fcc = calculate_fcc(chip, batt_temp, chargecycles);
pr_debug("FCC = %umAh batt_temp = %d, cycles = %d",
*fcc, batt_temp, chargecycles);
+ /* fcc doesnt need to be read from hardware, lock the bms now */
+ spin_lock_irqsave(&chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(chip);
+
*unusable_charge = calculate_unusable_charge_mah(chip, *fcc,
batt_temp, chargecycles);
@@ -796,6 +840,9 @@
/* calculate cc milli_volt_hour */
calculate_cc_mah(chip, cc_mah, &coulumb_counter);
+
+ pm_bms_unlock_output_data(chip);
+ spin_unlock_irqrestore(&chip->bms_output_lock, flags);
pr_debug("cc_mah = %lldmAh cc = %d\n", *cc_mah, coulumb_counter);
}
@@ -862,8 +909,7 @@
* shutdown for low battery
*/
soc = BATTERY_POWER_SUPPLY_SOC;
- pr_debug("Adjusting SOC to %d\n",
- BATTERY_POWER_SUPPLY_SOC);
+ pr_debug("Adjusting SOC to %d\n", soc);
}
}
@@ -947,16 +993,26 @@
int pm8921_bms_get_vsense_avg(int *result)
{
- if (the_chip)
- return read_vsense_avg(the_chip, result);
+ int rc = -EINVAL;
+ unsigned long flags;
+
+ if (the_chip) {
+ spin_lock_irqsave(&the_chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(the_chip);
+ rc = read_vsense_avg(the_chip, result);
+ pm_bms_unlock_output_data(the_chip);
+ spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
+ }
pr_err("called before initialization\n");
- return -EINVAL;
+ return rc;
}
EXPORT_SYMBOL(pm8921_bms_get_vsense_avg);
int pm8921_bms_get_battery_current(int *result)
{
+ unsigned long flags;
+
if (!the_chip) {
pr_err("called before initialization\n");
return -EINVAL;
@@ -966,7 +1022,11 @@
return -EINVAL;
}
+ spin_lock_irqsave(&the_chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(the_chip);
read_vsense_avg(the_chip, result);
+ pm_bms_unlock_output_data(the_chip);
+ spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
pr_debug("vsense=%d\n", *result);
/* cast for signed division */
*result = *result / (int)the_chip->r_sense;
@@ -1528,7 +1588,7 @@
pr_err("Cannot allocate pm_bms_chip\n");
return -ENOMEM;
}
-
+ spin_lock_init(&chip->bms_output_lock);
chip->dev = &pdev->dev;
chip->r_sense = pdata->r_sense;
chip->i_test = pdata->i_test;
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index 5e38238..a86e049 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -346,7 +346,7 @@
char *name;
char buf[32], *b;
int once = 0, err = -1;
- int (*notify)(uint32_t, const char *);
+ int (*notify)(uint32_t, const char *) = NULL;
strncpy(buf, diag_clients, sizeof(buf));
b = strim(buf);
@@ -354,10 +354,8 @@
while (b) {
name = strsep(&b, ",");
/* Allow only first diag channel to update pid and serial no */
- if (!once++)
+ if (_android_dev->pdata && !once++)
notify = _android_dev->pdata->update_pid_and_serial_num;
- else
- notify = NULL;
if (name) {
err = diag_function_add(c, name, notify);
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 9017706..9d268d1 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1699,6 +1699,9 @@
if (mReq->req.status != -EALREADY)
return -EINVAL;
+ /* clean speculative fetches on req->ptr->token */
+ mb();
+
if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
return -EBUSY;
@@ -2074,7 +2077,6 @@
continue; /* not configured */
if (hw_test_and_clear_complete(i)) {
- udelay(200);
err = isr_tr_complete_low(mEp);
if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
if (err > 0) /* needs status phase */
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index f8cadbb..1b2dec4 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -461,6 +461,7 @@
switch (pipe->src_format) {
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
*luma_off = pipe->src_x;
*chroma_off = pipe->src_x/2;
@@ -521,6 +522,11 @@
dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
ptype = mdp4_overlay_format2type(pipe->src_format);
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ frame_size = ((pipe->src_height << 16) |
+ ALIGN(pipe->src_width, 16));
+ src_size = ((pipe->src_h << 16) | ALIGN(pipe->src_w, 16));
+ }
format = mdp4_overlay_format(pipe);
pattern = mdp4_overlay_unpack_pattern(pipe);
@@ -618,6 +624,7 @@
case MDP_Y_CBCR_H2V2_TILE:
case MDP_Y_CRCB_H2V2_TILE:
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CRCB_H1V1:
case MDP_Y_CBCR_H1V1:
@@ -866,6 +873,7 @@
pipe->bpp = 2; /* 2 bpp */
break;
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
pipe->fetch_plane = OVERLAY_PLANE_PLANAR;
@@ -961,6 +969,7 @@
b_num = 8;
break;
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CRCB_H2V2:
case MDP_Y_CRCB_H2V1:
case MDP_Y_CRCB_H1V1:
@@ -2361,18 +2370,35 @@
pipe->srcp2_addr = start + img->offset;
*pp_src_plane2_file = p_src_plane2_file;
} else {
- addr += (pipe->src_width * pipe->src_height);
- pipe->srcp1_addr = addr;
- addr += ((pipe->src_width / 2) *
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ addr += (ALIGN(pipe->src_width, 16) *
+ pipe->src_height);
+ pipe->srcp1_addr = addr;
+ addr += ((ALIGN((pipe->src_width / 2), 16)) *
(pipe->src_height / 2));
- pipe->srcp2_addr = addr;
+ pipe->srcp2_addr = addr;
+ } else {
+ addr += (pipe->src_width * pipe->src_height);
+ pipe->srcp1_addr = addr;
+ addr += ((pipe->src_width / 2) *
+ (pipe->src_height / 2));
+ pipe->srcp2_addr = addr;
+ }
}
/* mdp planar format expects Cb in srcp1 and Cr in p2 */
- if (pipe->src_format == MDP_Y_CR_CB_H2V2)
+ if ((pipe->src_format == MDP_Y_CR_CB_H2V2) ||
+ (pipe->src_format == MDP_Y_CR_CB_GH2V2))
swap(pipe->srcp1_addr, pipe->srcp2_addr);
- pipe->srcp0_ystride = pipe->src_width;
- pipe->srcp1_ystride = pipe->src_width / 2;
- pipe->srcp2_ystride = pipe->src_width / 2;
+
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ pipe->srcp0_ystride = ALIGN(pipe->src_width, 16);
+ pipe->srcp1_ystride = ALIGN(pipe->src_width / 2, 16);
+ pipe->srcp2_ystride = ALIGN(pipe->src_width / 2, 16);
+ } else {
+ pipe->srcp0_ystride = pipe->src_width;
+ pipe->srcp1_ystride = pipe->src_width / 2;
+ pipe->srcp2_ystride = pipe->src_width / 2;
+ }
}
if (pipe->pipe_num >= OVERLAY_PIPE_VG1)
diff --git a/include/linux/mfd/pm8xxx/pm8xxx-adc.h b/include/linux/mfd/pm8xxx/pm8xxx-adc.h
new file mode 100644
index 0000000..aa642cc
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8xxx-adc.h
@@ -0,0 +1,574 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921/8018 ADC driver header file
+ *
+ */
+
+#ifndef __PM8XXX_ADC_H
+#define __PM8XXX_ADC_H
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+
+/**
+ * enum pm8xxx_adc_channels - PM8XXX AMUX arbiter channels
+ * %CHANNEL_VCOIN: Backup voltage for certain register set
+ * %CHANNEL_VBAT: Battery voltage
+ * %CHANNEL_DCIN: Charger input voltage without internal OVP
+ * %CHANNEL_ICHG: Charge-current monitor
+ * %CHANNEL_VPH_PWR: Main system power
+ * %CHANNEL_IBAT: Battery charge current
+ * %CHANNEL_MPP_1: 16:1 pre-mux unity scale MPP input
+ * %CHANNEL_MPP_2: 16:1 pre-mux 1/3 scale MPP input
+ * %CHANNEL_BATT_THERM: Battery temperature
+ * %CHANNEL_BATT_ID: Battery detection
+ * %CHANNEL_USBIN: Charger input voltage with internal OVP
+ * %CHANNEL_DIE_TEMP: Pmic_die temperature
+ * %CHANNEL_625MV: 625mv reference channel
+ * %CHANNEL_125V: 1.25v reference channel
+ * %CHANNEL_CHG_TEMP: Charger temperature
+ * %CHANNEL_MUXOFF: Channel to reduce input load on the mux
+ * %CHANNEL_NONE: Do not use this channel
+ */
+enum pm8xxx_adc_channels {
+ CHANNEL_VCOIN = 0,
+ CHANNEL_VBAT,
+ CHANNEL_DCIN,
+ CHANNEL_ICHG,
+ CHANNEL_VPH_PWR,
+ CHANNEL_IBAT,
+ CHANNEL_MPP_1,
+ CHANNEL_MPP_2,
+ CHANNEL_BATT_THERM,
+ CHANNEL_BATT_ID,
+ CHANNEL_USBIN,
+ CHANNEL_DIE_TEMP,
+ CHANNEL_625MV,
+ CHANNEL_125V,
+ CHANNEL_CHG_TEMP,
+ CHANNEL_MUXOFF,
+ CHANNEL_NONE,
+ ADC_MPP_1_ATEST_8 = 20,
+ ADC_MPP_1_USB_SNS_DIV20,
+ ADC_MPP_1_DCIN_SNS_DIV20,
+ ADC_MPP_1_AMUX3,
+ ADC_MPP_1_AMUX4,
+ ADC_MPP_1_AMUX5,
+ ADC_MPP_1_AMUX6,
+ ADC_MPP_1_AMUX7,
+ ADC_MPP_1_AMUX8,
+ ADC_MPP_1_ATEST_1,
+ ADC_MPP_1_ATEST_2,
+ ADC_MPP_1_ATEST_3,
+ ADC_MPP_1_ATEST_4,
+ ADC_MPP_1_ATEST_5,
+ ADC_MPP_1_ATEST_6,
+ ADC_MPP_1_ATEST_7,
+ ADC_MPP_1_CHANNEL_NONE,
+ ADC_MPP_2_ATEST_8 = 40,
+ ADC_MPP_2_USB_SNS_DIV20,
+ ADC_MPP_2_DCIN_SNS_DIV20,
+ ADC_MPP_2_AMUX3,
+ ADC_MPP_2_AMUX4,
+ ADC_MPP_2_AMUX5,
+ ADC_MPP_2_AMUX6,
+ ADC_MPP_2_AMUX7,
+ ADC_MPP_2_AMUX8,
+ ADC_MPP_2_ATEST_1,
+ ADC_MPP_2_ATEST_2,
+ ADC_MPP_2_ATEST_3,
+ ADC_MPP_2_ATEST_4,
+ ADC_MPP_2_ATEST_5,
+ ADC_MPP_2_ATEST_6,
+ ADC_MPP_2_ATEST_7,
+ ADC_MPP_2_CHANNEL_NONE,
+};
+
+#define PM8XXX_ADC_PMIC_0 0x0
+
+#define PM8XXX_CHANNEL_ADC_625_MV 625
+#define PM8XXX_CHANNEL_MPP_SCALE1_IDX 20
+#define PM8XXX_CHANNEL_MPP_SCALE3_IDX 40
+
+#define PM8XXX_AMUX_MPP_3 0x3
+#define PM8XXX_AMUX_MPP_4 0x4
+#define PM8XXX_AMUX_MPP_5 0x5
+#define PM8XXX_AMUX_MPP_6 0x6
+#define PM8XXX_AMUX_MPP_7 0x7
+#define PM8XXX_AMUX_MPP_8 0x8
+
+#define PM8XXX_ADC_DEV_NAME "pm8xxx-adc"
+
+/**
+ * enum pm8xxx_adc_decimation_type - Sampling rate supported
+ * %ADC_DECIMATION_TYPE1: 512
+ * %ADC_DECIMATION_TYPE2: 1K
+ * %ADC_DECIMATION_TYPE3: 2K
+ * %ADC_DECIMATION_TYPE4: 4k
+ * %ADC_DECIMATION_NONE: Do not use this Sampling type
+ *
+ * The Sampling rate is specific to each channel of the PM8XXX ADC arbiter.
+ */
+enum pm8xxx_adc_decimation_type {
+ ADC_DECIMATION_TYPE1 = 0,
+ ADC_DECIMATION_TYPE2,
+ ADC_DECIMATION_TYPE3,
+ ADC_DECIMATION_TYPE4,
+ ADC_DECIMATION_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_calib_type - PM8XXX ADC Calibration type
+ * %ADC_CALIB_ABSOLUTE: Use 625mV and 1.25V reference channels
+ * %ADC_CALIB_RATIOMETRIC: Use reference Voltage/GND
+ * %ADC_CALIB_CONFIG_NONE: Do not use this calibration type
+ *
+ * Use the input reference voltage depending on the calibration type
+ * to calcluate the offset and gain parameters. The calibration is
+ * specific to each channel of the PM8XXX ADC.
+ */
+enum pm8xxx_adc_calib_type {
+ ADC_CALIB_ABSOLUTE = 0,
+ ADC_CALIB_RATIOMETRIC,
+ ADC_CALIB_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_channel_scaling_param - pre-scaling AMUX ratio
+ * %CHAN_PATH_SCALING1: ratio of {1, 1}
+ * %CHAN_PATH_SCALING2: ratio of {1, 3}
+ * %CHAN_PATH_SCALING3: ratio of {1, 4}
+ * %CHAN_PATH_SCALING4: ratio of {1, 6}
+ * %CHAN_PATH_NONE: Do not use this pre-scaling ratio type
+ *
+ * The pre-scaling is applied for signals to be within the voltage range
+ * of the ADC.
+ */
+enum pm8xxx_adc_channel_scaling_param {
+ CHAN_PATH_SCALING1 = 0,
+ CHAN_PATH_SCALING2,
+ CHAN_PATH_SCALING3,
+ CHAN_PATH_SCALING4,
+ CHAN_PATH_SCALING_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_amux_input_rsv - HK/XOADC reference voltage
+ * %AMUX_RSV0: XO_IN/XOADC_GND
+ * %AMUX_RSV1: PMIC_IN/XOADC_GND
+ * %AMUX_RSV2: PMIC_IN/BMS_CSP
+ * %AMUX_RSV3: not used
+ * %AMUX_RSV4: XOADC_GND/XOADC_GND
+ * %AMUX_RSV5: XOADC_VREF/XOADC_GND
+ * %AMUX_NONE: Do not use this input reference voltage selection
+ */
+enum pm8xxx_adc_amux_input_rsv {
+ AMUX_RSV0 = 0,
+ AMUX_RSV1,
+ AMUX_RSV2,
+ AMUX_RSV3,
+ AMUX_RSV4,
+ AMUX_RSV5,
+ AMUX_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_premux_mpp_scale_type - 16:1 pre-mux scale ratio
+ * %PREMUX_MPP_SCALE_0: No scaling to the input signal
+ * %PREMUX_MPP_SCALE_1: Unity scaling selected by the user for MPP input
+ * %PREMUX_MPP_SCALE_1_DIV3: 1/3 pre-scale to the input MPP signal
+ * %PREMUX_MPP_NONE: Do not use this pre-scale mpp type
+ */
+enum pm8xxx_adc_premux_mpp_scale_type {
+ PREMUX_MPP_SCALE_0 = 0,
+ PREMUX_MPP_SCALE_1,
+ PREMUX_MPP_SCALE_1_DIV3,
+ PREMUX_MPP_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_scale_fn_type - Scaling function for pm8921 pre calibrated
+ * digital data relative to ADC reference
+ * %ADC_SCALE_DEFAULT: Default scaling to convert raw adc code to voltage
+ * %ADC_SCALE_BATT_THERM: Conversion to temperature based on btm parameters
+ * %ADC_SCALE_PMIC_THERM: Returns result in milli degree's Centigrade
+ * %ADC_SCALE_XTERN_CHGR_CUR: Returns current across 0.1 ohm resistor
+ * %ADC_SCALE_XOTHERM: Returns XO thermistor voltage in degree's Centigrade
+ * %ADC_SCALE_NONE: Do not use this scaling type
+ */
+enum pm8xxx_adc_scale_fn_type {
+ ADC_SCALE_DEFAULT = 0,
+ ADC_SCALE_BATT_THERM,
+ ADC_SCALE_PA_THERM,
+ ADC_SCALE_PMIC_THERM,
+ ADC_SCALE_XOTHERM,
+ ADC_SCALE_NONE,
+};
+
+/**
+ * struct pm8xxx_adc_linear_graph - Represent ADC characteristics
+ * @offset: Offset with respect to the actual curve
+ * @dy: Numerator slope to calculate the gain
+ * @dx: Denominator slope to calculate the gain
+ *
+ * Each ADC device has different offset and gain parameters which are computed
+ * to calibrate the device.
+ */
+struct pm8xxx_adc_linear_graph {
+ int32_t offset;
+ int32_t dy;
+ int32_t dx;
+};
+
+/**
+ * struct pm8xxx_adc_map_pt - Map the graph representation for ADC channel
+ * @x: Represent the ADC digitized code
+ * @y: Represent the physical data which can be temperature, voltage,
+ * resistance
+ */
+struct pm8xxx_adc_map_pt {
+ int32_t x;
+ int32_t y;
+};
+
+/**
+ * struct pm8xxx_adc_scaling_ratio - Represent scaling ratio for adc input
+ * @num: Numerator scaling parameter
+ * @den: Denominator scaling parameter
+ */
+struct pm8xxx_adc_scaling_ratio {
+ int32_t num;
+ int32_t den;
+};
+
+/**
+ * struct pm8xxx_adc_properties - Represent the ADC properties
+ * @adc_reference: Reference voltage for PM8XXX ADC
+ * @bitresolution: ADC bit resolution for PM8XXX ADC
+ * @biploar: Polarity for PM8XXX ADC
+ */
+struct pm8xxx_adc_properties {
+ uint32_t adc_vdd_reference;
+ uint32_t bitresolution;
+ bool bipolar;
+};
+
+/**
+ * struct pm8xxx_adc_chan_properties - Represent channel properties of the ADC
+ * @offset_gain_numerator: The inverse numerator of the gain applied to the
+ * input channel
+ * @offset_gain_denominator: The inverse denominator of the gain applied to the
+ * input channel
+ * @adc_graph: ADC graph for the channel of struct type pm8xxx_adc_linear_graph
+ */
+struct pm8xxx_adc_chan_properties {
+ uint32_t offset_gain_numerator;
+ uint32_t offset_gain_denominator;
+ struct pm8xxx_adc_linear_graph adc_graph[2];
+};
+
+/**
+ * struct pm8xxx_adc_chan_result - Represent the result of the PM8XXX ADC
+ * @chan: The channel number of the requested conversion
+ * @adc_code: The pre-calibrated digital output of a given ADC relative to the
+ * the ADC reference
+ * @measurement: In units specific for a given ADC; most ADC uses reference
+ * voltage but some ADC uses reference current. This measurement
+ * here is a number relative to a reference of a given ADC
+ * @physical: The data meaningful for each individual channel whether it is
+ * voltage, current, temperature, etc.
+ */
+struct pm8xxx_adc_chan_result {
+ uint32_t chan;
+ int32_t adc_code;
+ int64_t measurement;
+ int64_t physical;
+};
+
+#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
+ || defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
+/**
+ * pm8xxx_adc_scale_default() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: Physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_tdkntcg_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature of the xo therm in mili
+ degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_batt_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature in degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_pa_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature in degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_pmic_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Performs the AMUX out as 2mv/K and returns
+ * the temperature in mili degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+#else
+static inline int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+#endif
+
+/**
+ * struct pm8xxx_adc_scale_fn - Scaling function prototype
+ * @chan: Function pointer to one of the scaling functions
+ * which takes the adc properties, channel properties,
+ * and returns the physical result
+ */
+struct pm8xxx_adc_scale_fn {
+ int32_t (*chan) (int32_t,
+ const struct pm8xxx_adc_properties *,
+ const struct pm8xxx_adc_chan_properties *,
+ struct pm8xxx_adc_chan_result *);
+};
+
+/**
+ * struct pm8xxx_adc_amux - AMUX properties for individual channel
+ * @name: Channel name
+ * @channel_name: Channel in integer used from pm8xxx_adc_channels
+ * @chan_path_prescaling: Channel scaling performed on the input signal
+ * @adc_rsv: Input reference Voltage/GND selection to the ADC
+ * @adc_decimation: Sampling rate desired for the channel
+ * adc_scale_fn: Scaling function to convert to the data meaningful for
+ * each individual channel whether it is voltage, current,
+ * temperature, etc and compensates the channel properties
+ */
+struct pm8xxx_adc_amux {
+ char *name;
+ enum pm8xxx_adc_channels channel_name;
+ enum pm8xxx_adc_channel_scaling_param chan_path_prescaling;
+ enum pm8xxx_adc_amux_input_rsv adc_rsv;
+ enum pm8xxx_adc_decimation_type adc_decimation;
+ enum pm8xxx_adc_scale_fn_type adc_scale_fn;
+};
+
+/**
+ * struct pm8xxx_adc_arb_btm_param - PM8XXX ADC BTM parameters to set threshold
+ * temperature for client notification
+ * @low_thr_temp: low temperature threshold request for notification
+ * @high_thr_temp: high temperature threshold request for notification
+ * @low_thr_voltage: low temperature converted to voltage by arbiter driver
+ * @high_thr_voltage: high temperature converted to voltage by arbiter driver
+ * @interval: Interval period to check for temperature notification
+ * @btm_warm_fn: Remote function call for warm threshold.
+ * @btm_cool_fn: Remote function call for cold threshold.
+ *
+ * BTM client passes the parameters to be set for the
+ * temperature threshold notifications. The client is
+ * responsible for setting the new threshold
+ * levels once the thresholds are reached
+ */
+struct pm8xxx_adc_arb_btm_param {
+ uint32_t low_thr_temp;
+ uint32_t high_thr_temp;
+ uint64_t low_thr_voltage;
+ uint64_t high_thr_voltage;
+ int32_t interval;
+ void (*btm_warm_fn) (bool);
+ void (*btm_cool_fn) (bool);
+};
+
+int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *);
+
+/**
+ * struct pm8xxx_adc_platform_data - PM8XXX ADC platform data
+ * @adc_prop: ADC specific parameters, voltage and channel setup
+ * @adc_channel: Channel properties of the ADC arbiter
+ * @adc_num_board_channel: Number of channels added in the board file
+ * @adc_mpp_base: PM8XXX MPP0 base passed from board file. This is used
+ * to offset the PM8XXX MPP passed to configure the
+ * the MPP to AMUX mapping.
+ */
+struct pm8xxx_adc_platform_data {
+ struct pm8xxx_adc_properties *adc_prop;
+ struct pm8xxx_adc_amux *adc_channel;
+ uint32_t adc_num_board_channel;
+ uint32_t adc_mpp_base;
+};
+
+/* Public API */
+#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
+ || defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
+/**
+ * pm8xxx_adc_read() - Performs ADC read on the channel.
+ * @channel: Input channel to perform the ADC read.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result);
+/**
+ * pm8xxx_adc_mpp_config_read() - Configure's the PM8XXX MPP
+ * to AMUX6 and performs an ADC read.
+ *
+ * On PM8921 ADC the MPP needs to first be configured
+ * as an analog input to the AMUX pre-mux channel before
+ * issuing a read request. PM8921 MPP 8 is mapped to AMUX8
+ * and is common between remote processor's.
+ *
+ * On PM8018 ADC the MPP is directly connected to the AMUX
+ * pre-mux. Therefore clients of the PM8018 MPP do not need
+ * to configure the MPP as an analog input to the pre-mux.
+ * Clients can directly issue request on the pre-mux AMUX
+ * channel to read the ADC on the MPP. Clients can directly
+ * call the pm8xxx_adc_read().
+ * @mpp_num PM8XXX MPP number to configure to AMUX6.
+ * @channel: Input channel to perform the ADC read.
+ * a) 'ADC_MPP_1_AMUX6' if the input voltage is less than 1.8V
+ * b) 'ADC_MPP_2_AMUX6' if the input voltage is greater then 1.8V
+ * the input voltage is pre-divided by 3 and passed to the ADC.
+ * The appropriate scaling function needs to be selected to let
+ * the driver know a post scaling is required before returning
+ * the result.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result);
+/**
+ * pm8xxx_adc_btm_start() - Configure the BTM registers and start
+ monitoring the BATT_THERM channel for
+ threshold warm/cold temperature set
+ by the Battery client. The btm_start
+ api is to be used after calling the
+ pm8xxx_btm_configure() api which sets
+ the temperature thresholds, interval
+ and functions to call when warm/cold
+ events are triggered.
+ * @param: none.
+ */
+uint32_t pm8xxx_adc_btm_start(void);
+
+/**
+ * pm8xxx_adc_btm_end() - Configures the BTM registers to stop
+ * monitoring the BATT_THERM channel for
+ * warm/cold events and disables the
+ * interval timer.
+ * @param: none.
+ */
+uint32_t pm8xxx_adc_btm_end(void);
+
+/**
+ * pm8xxx_adc_btm_configure() - Configures the BATT_THERM channel
+ * parameters for warm/cold thresholds.
+ * Sets the interval timer for perfoming
+ * reading the temperature done by the HW.
+ * @btm_param: Structure pointer of type adc_arb_btm_param *
+ * which client provides for threshold warm/cold,
+ * interval and functions to call when warm/cold
+ * events are triggered.
+ */
+uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *);
+#else
+static inline uint32_t pm8xxx_adc_read(uint32_t channel,
+ struct pm8xxx_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_start(void)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_end(void)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_configure(
+ struct pm8xxx_adc_arb_btm_param *param)
+{ return -ENXIO; }
+#endif
+
+#endif /* PM8XXX_ADC_H */
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index aa6aeb9..b67803a 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -708,6 +708,12 @@
__le16 sco_max_pkt;
} __packed;
+#define HCI_OP_WRITE_CURRENT_IAC_LAP 0x0c3a
+struct hci_cp_write_current_iac_lap {
+ __u8 num_current_iac;
+ __u8 lap[6];
+} __packed;
+
#define HCI_OP_WRITE_INQUIRY_MODE 0x0c45
#define HCI_MAX_EIR_LENGTH 240
diff --git a/include/net/bluetooth/mgmt.h b/include/net/bluetooth/mgmt.h
index 5e855dbf..208c157 100644
--- a/include/net/bluetooth/mgmt.h
+++ b/include/net/bluetooth/mgmt.h
@@ -90,6 +90,8 @@
__u8 major;
__u8 minor;
} __packed;
+#define MGMT_MAJOR_CLASS_MASK 0x1F
+#define MGMT_MAJOR_CLASS_LIMITED 0x20
#define MGMT_OP_SET_SERVICE_CACHE 0x000C
struct mgmt_cp_set_service_cache {
@@ -214,6 +216,8 @@
bdaddr_t bdaddr;
} __packed;
+#define MGMT_OP_SET_LIMIT_DISCOVERABLE 0x001F
+
#define MGMT_EV_CMD_COMPLETE 0x0001
struct mgmt_ev_cmd_complete {
__le16 opcode;
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index a328db9..ea72708 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -409,6 +409,124 @@
return err;
}
+static u8 get_service_classes(struct hci_dev *hdev)
+{
+ struct list_head *p;
+ u8 val = 0;
+
+ list_for_each(p, &hdev->uuids) {
+ struct bt_uuid *uuid = list_entry(p, struct bt_uuid, list);
+
+ val |= uuid->svc_hint;
+ }
+
+ return val;
+}
+
+static int update_class(struct hci_dev *hdev)
+{
+ u8 cod[3];
+
+ BT_DBG("%s", hdev->name);
+
+ if (test_bit(HCI_SERVICE_CACHE, &hdev->flags))
+ return 0;
+
+ cod[0] = hdev->minor_class;
+ cod[1] = hdev->major_class;
+ cod[2] = get_service_classes(hdev);
+
+ if (memcmp(cod, hdev->dev_class, 3) == 0)
+ return 0;
+
+ return hci_send_cmd(hdev, HCI_OP_WRITE_CLASS_OF_DEV, sizeof(cod), cod);
+}
+
+static int set_limited_discoverable(struct sock *sk, u16 index,
+ unsigned char *data, u16 len)
+{
+ struct mgmt_mode *cp;
+ struct hci_dev *hdev;
+ struct pending_cmd *cmd;
+ struct hci_cp_write_current_iac_lap dcp;
+ int update_cod;
+ int err = 0;
+ /* General Inquiry LAP: 0x9E8B33, Limited Inquiry LAP: 0x9E8B00 */
+ u8 lap[] = { 0x33, 0x8b, 0x9e, 0x00, 0x8b, 0x9e };
+
+ cp = (void *) data;
+
+ BT_DBG("hci%u discoverable: %d", index, cp->val);
+
+ if (!cp || len != sizeof(*cp))
+ return cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EINVAL);
+
+ hdev = hci_dev_get(index);
+ if (!hdev)
+ return cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ ENODEV);
+
+ hci_dev_lock(hdev);
+
+ if (!test_bit(HCI_UP, &hdev->flags)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ ENETDOWN);
+ goto failed;
+ }
+
+ if (mgmt_pending_find(MGMT_OP_SET_LIMIT_DISCOVERABLE, index)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EBUSY);
+ goto failed;
+ }
+
+ if (cp->val == test_bit(HCI_ISCAN, &hdev->flags) &&
+ test_bit(HCI_PSCAN, &hdev->flags)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EALREADY);
+ goto failed;
+ }
+
+ cmd = mgmt_pending_add(sk, MGMT_OP_SET_LIMIT_DISCOVERABLE, index, data,
+ len);
+ if (!cmd) {
+ err = -ENOMEM;
+ goto failed;
+ }
+
+ memset(&dcp, 0, sizeof(dcp));
+ dcp.num_current_iac = cp->val ? 2 : 1;
+ memcpy(&dcp.lap, lap, dcp.num_current_iac * 3);
+ update_cod = 1;
+
+ if (cp->val) {
+ if (hdev->major_class & MGMT_MAJOR_CLASS_LIMITED)
+ update_cod = 0;
+ hdev->major_class |= MGMT_MAJOR_CLASS_LIMITED;
+ } else {
+ if (!(hdev->major_class & MGMT_MAJOR_CLASS_LIMITED))
+ update_cod = 0;
+ hdev->major_class &= ~MGMT_MAJOR_CLASS_LIMITED;
+ }
+
+ if (update_cod)
+ err = update_class(hdev);
+
+ if (err >= 0)
+ err = hci_send_cmd(hdev, HCI_OP_WRITE_CURRENT_IAC_LAP,
+ sizeof(dcp), &dcp);
+
+ if (err < 0)
+ mgmt_pending_remove(cmd);
+
+failed:
+ hci_dev_unlock(hdev);
+ hci_dev_put(hdev);
+
+ return err;
+}
+
static int set_discoverable(struct sock *sk, u16 index, unsigned char *data,
u16 len)
{
@@ -751,39 +869,6 @@
return hci_send_cmd(hdev, HCI_OP_WRITE_EIR, sizeof(cp), &cp);
}
-static u8 get_service_classes(struct hci_dev *hdev)
-{
- struct list_head *p;
- u8 val = 0;
-
- list_for_each(p, &hdev->uuids) {
- struct bt_uuid *uuid = list_entry(p, struct bt_uuid, list);
-
- val |= uuid->svc_hint;
- }
-
- return val;
-}
-
-static int update_class(struct hci_dev *hdev)
-{
- u8 cod[3];
-
- BT_DBG("%s", hdev->name);
-
- if (test_bit(HCI_SERVICE_CACHE, &hdev->flags))
- return 0;
-
- cod[0] = hdev->minor_class;
- cod[1] = hdev->major_class;
- cod[2] = get_service_classes(hdev);
-
- if (memcmp(cod, hdev->dev_class, 3) == 0)
- return 0;
-
- return hci_send_cmd(hdev, HCI_OP_WRITE_CLASS_OF_DEV, sizeof(cod), cod);
-}
-
static int add_uuid(struct sock *sk, u16 index, unsigned char *data, u16 len)
{
struct mgmt_cp_add_uuid *cp;
@@ -912,7 +997,8 @@
hci_dev_lock(hdev);
- hdev->major_class = cp->major;
+ hdev->major_class &= ~MGMT_MAJOR_CLASS_MASK;
+ hdev->major_class |= cp->major & MGMT_MAJOR_CLASS_MASK;
hdev->minor_class = cp->minor;
err = update_class(hdev);
@@ -2111,6 +2197,10 @@
case MGMT_OP_SET_DISCOVERABLE:
err = set_discoverable(sk, index, buf + sizeof(*hdr), len);
break;
+ case MGMT_OP_SET_LIMIT_DISCOVERABLE:
+ err = set_limited_discoverable(sk, index, buf + sizeof(*hdr),
+ len);
+ break;
case MGMT_OP_SET_CONNECTABLE:
err = set_connectable(sk, index, buf + sizeof(*hdr), len);
break;
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 548b834..bbb0789 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -447,11 +447,8 @@
{"DMIC5", NULL, "MIC BIAS4 External"},
{"MIC BIAS4 External", NULL, "Digital Mic5"},
-};
-
-static const struct snd_soc_dapm_route cdp_audio_map[] = {
- /** Digital Mic GM4 on CDP mainboard.
- * Connected to DMIC6 input on Tabla codec.
+ /* Tabla digital Mic6 - back bottom digital Mic on Liquid and
+ * bottom mic on CDP. FLUID/MTP do not have dmic6 installed.
*/
{"DMIC6", NULL, "MIC BIAS4 External"},
{"MIC BIAS4 External", NULL, "Digital Mic6"},
@@ -584,16 +581,6 @@
snd_soc_dapm_add_routes(dapm, common_audio_map,
ARRAY_SIZE(common_audio_map));
- if (machine_is_msm8960_cdp())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
- else if (machine_is_msm8960_mtp())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
- else if (machine_is_msm8960_fluid())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
-
snd_soc_dapm_enable_pin(dapm, "Ext Spk");
snd_soc_dapm_sync(dapm);