| commit | 9553426372eef71c849499fb1d232f4b0577c0f9 | [log] [tgz] |
|---|---|---|
| author | Li Peng <peng.li@linux.intel.com> | Tue May 18 18:58:44 2010 +0800 |
| committer | Eric Anholt <eric@anholt.net> | Wed May 26 14:22:51 2010 -0700 |
| tree | 8df1e5e08fd759c2c7279c232ef7e6732a3e65db | |
| parent | d8201ab6514f8dc1a0ccfac52c688d80976a425a [diff] |
drm/i915: Add CxSR support on Pineview DDR3 Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>