Merge "msm: board-8960: Bump SPI GPIO drive strength to 12mA" into msm-3.0
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 3bc7456..4322baf 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -221,6 +221,8 @@
CONFIG_VIDEO_DEV=y
# CONFIG_MT9T013 is not set
# CONFIG_MT9D112 is not set
+CONFIG_OV5640=y
+CONFIG_WEBCAM_OV7692_QRD=y
CONFIG_WEBCAM_OV9726=y
# CONFIG_MT9P012 is not set
# CONFIG_MT9P012_KM is not set
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index 10d1fc5..be8ade5 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -219,6 +219,8 @@
CONFIG_VIDEO_DEV=y
# CONFIG_MT9T013 is not set
# CONFIG_MT9D112 is not set
+CONFIG_OV5640=y
+CONFIG_WEBCAM_OV7692_QRD=y
CONFIG_WEBCAM_OV9726=y
# CONFIG_MT9P012 is not set
# CONFIG_MT9P012_KM is not set
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index 5b52404..fb0f106 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -71,7 +71,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm7630_defconfig b/arch/arm/configs/msm7630_defconfig
index 9ad0b5a..cde4048 100644
--- a/arch/arm/configs/msm7630_defconfig
+++ b/arch/arm/configs/msm7630_defconfig
@@ -70,7 +70,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 0f41c0a..c9082f0 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -104,7 +104,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index e900062..2569f82 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -95,7 +95,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index 73d0756..12f946c 100755
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -97,7 +97,7 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 7ef47c8..953f088 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -113,6 +113,7 @@
CONFIG_USB_G_ANDROID=y
CONFIG_SWITCH=y
CONFIG_NET=y
+CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
@@ -205,3 +206,21 @@
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
+
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_NETDEVICES=y
+CONFIG_WLAN=y
+CONFIG_MSM_RMNET=y
+CONFIG_HOSTAP=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index cfc7dd0..47da48e 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -509,7 +509,6 @@
/* Move CPU to HFPLL source. */
set_pri_clk_src(sc, tgt_s->pri_src_sel);
} else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
- /* TODO: Enable source. */
/*
* If responding to CPU_DEAD we must be running on another
* CPU. Therefore, we can't access the downed CPU's CP15
@@ -533,12 +532,9 @@
*/
if (reason != SETRATE_HOTPLUG || sc == &scalable[L2])
set_pri_clk_src(sc, tgt_s->pri_src_sel);
- /* TODO: Disable source. */
} else {
- /* TODO: Enable source. */
if (reason != SETRATE_HOTPLUG || sc == &scalable[L2])
set_sec_clk_src(sc, tgt_s->sec_src_sel);
- /* TODO: Disable source. */
}
sc->current_speed = tgt_s;
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 44939e7..cd590c3 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -1847,7 +1847,7 @@
if (!strncmp(name, "lcdc_toshiba_fwvga_pt", 21) ||
!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
ret = 0;
- } else if (machine_is_msm7x27a_ffa()) {
+ } else if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa()) {
if (!strncmp(name, "mipi_cmd_renesas_fwvga", 22))
ret = 0;
}
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 1470026..5c11af3 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -1411,7 +1411,7 @@
return rc;
}
-#define GPIO_SDC1_HW_DET 85
+#define GPIO_SDC1_HW_DET 42
#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) \
&& defined(CONFIG_MMC_MSM_CARD_HW_DETECTION)
@@ -1432,7 +1432,7 @@
} else {
status = gpio_direction_input(GPIO_SDC1_HW_DET);
if (!status)
- status = gpio_get_value(GPIO_SDC1_HW_DET);
+ status = !gpio_get_value(GPIO_SDC1_HW_DET);
gpio_free(GPIO_SDC1_HW_DET);
}
return status;
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 50be14b..73020dc 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -137,36 +137,71 @@
/*
* Clock frequency definitions and macros
*/
-#define F_BASIC(f, s, div, v) \
+#define F_BASIC(f, s, div) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = SDIV(SRC_SEL_##s, div), \
- .sys_vdd = v, \
}
-#define F_MND16(f, s, div, m, n, v) \
+#define F_MND16(f, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-#define F_MND8(f, nmsb, nlsb, s, div, m, n, v) \
+#define F_MND8(f, nmsb, nlsb, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(m, n), \
.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_ops clk_ops_rcg_7x30;
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ int rc, target_mv;
+
+ static const int mv[] = {
+ [VDD_DIG_NONE] = 1000,
+ [VDD_DIG_LOW] = 1000,
+ [VDD_DIG_NOMINAL] = 1100,
+ [VDD_DIG_HIGH] = 1200
+ };
+
+ target_mv = mv[level];
+ rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
+ if (rc)
+ return rc;
+ if (target_mv)
+ rc = -EINVAL;
+
+ return rc;
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+
#define PCOM_XO_DISABLE 0
#define PCOM_XO_ENABLE 1
#define PCOM_XO_TCXO 0
@@ -290,7 +325,7 @@
static struct clk_ops clk_ops_branch;
static struct clk_freq_tbl clk_tbl_axi[] = {
- F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -308,6 +343,7 @@
.c = {
.dbg_name = "glbl_root_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1),
CLK_INIT(glbl_root_clk.c),
},
};
@@ -948,10 +984,10 @@
};
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(153600000, 24, 17, pll1, 2, 2, 5, NOMINAL),
- F_MND8(192000000, 24, 17, pll1, 4, 0, 0, NOMINAL),
- F_MND8(384000000, 24, 17, pll1, 2, 0, 0, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(153600000, 24, 17, pll1, 2, 2, 5),
+ F_MND8(192000000, 24, 17, pll1, 4, 0, 0),
+ F_MND8(384000000, 24, 17, pll1, 2, 0, 0),
F_END,
};
@@ -973,12 +1009,13 @@
.c = {
.dbg_name = "csi0_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 384000000),
CLK_INIT(csi0_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_tcxo[] = {
- F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -997,6 +1034,7 @@
.c = {
.dbg_name = "i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_clk.c),
},
};
@@ -1016,6 +1054,7 @@
.c = {
.dbg_name = "i2c_2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_2_clk.c),
},
};
@@ -1035,6 +1074,7 @@
.c = {
.dbg_name = "qup_i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(qup_i2c_clk.c),
},
};
@@ -1054,6 +1094,7 @@
.c = {
.dbg_name = "uart1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart1_clk.c),
},
};
@@ -1073,23 +1114,24 @@
.c = {
.dbg_name = "uart2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart2_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_uartdm[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 3686400, pll3, 3, 3, 200, NOMINAL),
- F_MND16( 7372800, pll3, 3, 3, 100, NOMINAL),
- F_MND16(14745600, pll3, 3, 3, 50, NOMINAL),
- F_MND16(32000000, pll3, 3, 25, 192, NOMINAL),
- F_MND16(40000000, pll3, 3, 125, 768, NOMINAL),
- F_MND16(46400000, pll3, 3, 145, 768, NOMINAL),
- F_MND16(48000000, pll3, 3, 25, 128, NOMINAL),
- F_MND16(51200000, pll3, 3, 5, 24, NOMINAL),
- F_MND16(56000000, pll3, 3, 175, 768, NOMINAL),
- F_MND16(58982400, pll3, 3, 6, 25, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 3686400, pll3, 3, 3, 200),
+ F_MND16( 7372800, pll3, 3, 3, 100),
+ F_MND16(14745600, pll3, 3, 3, 50),
+ F_MND16(32000000, pll3, 3, 25, 192),
+ F_MND16(40000000, pll3, 3, 125, 768),
+ F_MND16(46400000, pll3, 3, 145, 768),
+ F_MND16(48000000, pll3, 3, 25, 128),
+ F_MND16(51200000, pll3, 3, 5, 24),
+ F_MND16(56000000, pll3, 3, 175, 768),
+ F_MND16(58982400, pll3, 3, 6, 25),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -1111,6 +1153,7 @@
.c = {
.dbg_name = "uart1dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart1dm_clk.c),
},
};
@@ -1133,20 +1176,21 @@
.c = {
.dbg_name = "uart2dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart2dm_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdh[] = {
- F_BASIC( 0, gnd, 1, NONE),
- F_BASIC( 49150000, pll3, 15, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, NOMINAL),
- F_BASIC(368640000, pll3, 2, NOMINAL),
- F_BASIC(384000000, pll1, 2, NOMINAL),
- F_BASIC(445500000, pll4, 2, NOMINAL),
+ F_BASIC( 0, gnd, 1),
+ F_BASIC( 49150000, pll3, 15),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(245760000, pll3, 3),
+ F_BASIC(368640000, pll3, 2),
+ F_BASIC(384000000, pll1, 2),
+ F_BASIC(445500000, pll4, 2),
F_END,
};
@@ -1166,6 +1210,7 @@
.dbg_name = "emdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(emdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1187,30 +1232,31 @@
.dbg_name = "pmdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(pmdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_grp[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52662875, pll3, 14, NOMINAL),
- F_BASIC( 56713846, pll3, 13, NOMINAL),
- F_BASIC( 61440000, pll3, 12, NOMINAL),
- F_BASIC( 67025454, pll3, 11, NOMINAL),
- F_BASIC( 73728000, pll3, 10, NOMINAL),
- F_BASIC( 81920000, pll3, 9, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(105325714, pll3, 7, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(192000000, pll1, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52662875, pll3, 14),
+ F_BASIC( 56713846, pll3, 13),
+ F_BASIC( 61440000, pll3, 12),
+ F_BASIC( 67025454, pll3, 11),
+ F_BASIC( 73728000, pll3, 10),
+ F_BASIC( 81920000, pll3, 9),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(105325714, pll3, 7),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(192000000, pll1, 4),
+ F_BASIC(245760000, pll3, 3),
/* Sync to AXI. Hence this "rate" is not fixed. */
- F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NULL),
F_END,
};
@@ -1231,6 +1277,7 @@
.c = {
.dbg_name = "grp_2d_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_2d_clk.c),
.depends = &axi_grp_2d_clk.c,
},
@@ -1250,6 +1297,7 @@
.c = {
.dbg_name = "grp_3d_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_3d_src_clk.c),
.depends = &axi_li_grp_clk.c,
},
@@ -1288,14 +1336,14 @@
};
static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 19, 12, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 19, 12, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 19, 12, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 19, 12, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 19, 12, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 19, 12, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 19, 12, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 19, 12, lpxo, 1, 1, 171),
+ F_MND8( 400000, 19, 12, lpxo, 1, 2, 123),
+ F_MND8(16027000, 19, 12, pll3, 3, 14, 215),
+ F_MND8(17000000, 19, 12, pll3, 4, 19, 206),
+ F_MND8(20480000, 19, 12, pll3, 4, 23, 212),
+ F_MND8(24576000, 19, 12, lpxo, 1, 0, 0),
+ F_MND8(49152000, 19, 12, pll3, 3, 1, 5),
F_END,
};
@@ -1317,6 +1365,7 @@
.c = {
.dbg_name = "sdc1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc1_clk.c),
},
};
@@ -1339,19 +1388,20 @@
.c = {
.dbg_name = "sdc3_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc3_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 20, 13, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 20, 13, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 20, 13, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 20, 13, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 20, 13, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 20, 13, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 20, 13, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 20, 13, lpxo, 1, 1, 171),
+ F_MND8( 400000, 20, 13, lpxo, 1, 2, 123),
+ F_MND8(16027000, 20, 13, pll3, 3, 14, 215),
+ F_MND8(17000000, 20, 13, pll3, 4, 19, 206),
+ F_MND8(20480000, 20, 13, pll3, 4, 23, 212),
+ F_MND8(24576000, 20, 13, lpxo, 1, 0, 0),
+ F_MND8(49152000, 20, 13, pll3, 3, 1, 5),
F_END,
};
@@ -1373,6 +1423,7 @@
.c = {
.dbg_name = "sdc2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc2_clk.c),
},
};
@@ -1395,20 +1446,21 @@
.c = {
.dbg_name = "sdc4_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc4_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdp_core[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52663000, pll3, 14, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(153600000, pll1, 5, NOMINAL),
- F_BASIC(192000000, pll1, 4, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52663000, pll3, 14),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(153600000, pll1, 5),
+ F_BASIC(192000000, pll1, 4),
F_END,
};
@@ -1429,18 +1481,19 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(mdp_clk.c),
.depends = &axi_mdp_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16(30720000, pll3, 4, 1, 6, NOMINAL),
- F_MND16(32768000, pll3, 3, 2, 15, NOMINAL),
- F_MND16(40960000, pll3, 2, 1, 9, NOMINAL),
- F_MND16(73728000, pll3, 2, 1, 5, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(24576000, lpxo, 1, 0, 0),
+ F_MND16(30720000, pll3, 4, 1, 6),
+ F_MND16(32768000, pll3, 3, 2, 15),
+ F_MND16(40960000, pll3, 2, 1, 9),
+ F_MND16(73728000, pll3, 2, 1, 5),
F_END,
};
@@ -1462,6 +1515,7 @@
.c = {
.dbg_name = "mdp_lcdc_pclk_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 73728000),
CLK_INIT(mdp_lcdc_pclk_clk.c),
},
};
@@ -1483,8 +1537,8 @@
};
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NONE, NULL),
- F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NOMINAL, NULL),
+ F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NULL),
+ F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NULL),
F_END,
};
@@ -1504,14 +1558,15 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 24576000),
CLK_INIT(mdp_vsync_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 2048000, lpxo, 4, 1, 3, NOMINAL),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 2048000, lpxo, 4, 1, 3),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1533,6 +1588,7 @@
.c = {
.dbg_name = "mi2s_codec_rx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_rx_m_clk.c),
},
};
@@ -1571,6 +1627,7 @@
.c = {
.dbg_name = "mi2s_codec_tx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_tx_m_clk.c),
},
};
@@ -1592,8 +1649,8 @@
};
static struct clk_freq_tbl clk_tbl_mi2s[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1615,6 +1672,7 @@
.c = {
.dbg_name = "mi2s_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_m_clk.c),
},
};
@@ -1636,8 +1694,8 @@
};
static struct clk_freq_tbl clk_tbl_midi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(98304000, 19, 12, pll3, 3, 2, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(98304000, 19, 12, pll3, 3, 2, 5),
F_END,
};
@@ -1658,30 +1716,30 @@
.c = {
.dbg_name = "midi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 98304000),
CLK_INIT(midi_clk.c),
},
};
-#define F_SDAC(f, s, div, m, n, v) \
+#define F_SDAC(f, s, div, m, n) \
{ \
.freq_hz = f, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_SDAC_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
.src_clk = &s##_clk.c, \
}
static struct clk_freq_tbl clk_tbl_sdac[] = {
- F_SDAC( 256000, lpxo, 4, 1, 24, NOMINAL),
- F_SDAC( 352800, lpxo, 1, 147, 10240, NOMINAL),
- F_SDAC( 384000, lpxo, 4, 1, 16, NOMINAL),
- F_SDAC( 512000, lpxo, 4, 1, 12, NOMINAL),
- F_SDAC( 705600, lpxo, 1, 147, 5120, NOMINAL),
- F_SDAC( 768000, lpxo, 4, 1, 8, NOMINAL),
- F_SDAC(1024000, lpxo, 4, 1, 6, NOMINAL),
- F_SDAC(1411200, lpxo, 1, 147, 2560, NOMINAL),
- F_SDAC(1536000, lpxo, 4, 1, 4, NOMINAL),
+ F_SDAC( 256000, lpxo, 4, 1, 24),
+ F_SDAC( 352800, lpxo, 1, 147, 10240),
+ F_SDAC( 384000, lpxo, 4, 1, 16),
+ F_SDAC( 512000, lpxo, 4, 1, 12),
+ F_SDAC( 705600, lpxo, 1, 147, 5120),
+ F_SDAC( 768000, lpxo, 4, 1, 8),
+ F_SDAC(1024000, lpxo, 4, 1, 6),
+ F_SDAC(1411200, lpxo, 1, 147, 2560),
+ F_SDAC(1536000, lpxo, 4, 1, 4),
F_END,
};
@@ -1703,6 +1761,7 @@
.c = {
.dbg_name = "sdac_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1536000),
CLK_INIT(sdac_clk.c),
},
};
@@ -1724,9 +1783,9 @@
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(27000000, 23, 16, pll4, 2, 2, 33, NOMINAL),
- F_MND8(74250000, 23, 16, pll4, 2, 1, 6, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(27000000, 23, 16, pll4, 2, 2, 33),
+ F_MND8(74250000, 23, 16, pll4, 2, 1, 6),
F_END,
};
@@ -1745,6 +1804,7 @@
.c = {
.dbg_name = "tv_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 74250000),
CLK_INIT(tv_clk.c),
},
};
@@ -1815,8 +1875,8 @@
};
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(60000000, 23, 16, pll1, 2, 5, 32, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(60000000, 23, 16, pll1, 2, 5, 32),
F_END,
};
@@ -1835,6 +1895,7 @@
.c = {
.dbg_name = "usb_hs_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs_src_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1936,19 +1997,19 @@
};
static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
- F_MND16( 24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16( 36864000, pll3, 4, 1, 5, NOMINAL),
- F_MND16( 46080000, pll3, 4, 1, 4, NOMINAL),
- F_MND16( 61440000, pll3, 4, 1, 3, NOMINAL),
- F_MND16( 73728000, pll3, 2, 1, 5, NOMINAL),
- F_MND16( 81920000, pll3, 3, 1, 3, NOMINAL),
- F_MND16( 92160000, pll3, 4, 1, 2, NOMINAL),
- F_MND16( 98304000, pll3, 3, 2, 5, NOMINAL),
- F_MND16(105326000, pll3, 2, 2, 7, NOMINAL),
- F_MND16(122880000, pll3, 2, 1, 3, NOMINAL),
- F_MND16(147456000, pll3, 2, 2, 5, NOMINAL),
- F_MND16(153600000, pll1, 2, 2, 5, NOMINAL),
- F_MND16(192000000, pll1, 4, 0, 0, HIGH),
+ F_MND16( 24576000, lpxo, 1, 0, 0),
+ F_MND16( 36864000, pll3, 4, 1, 5),
+ F_MND16( 46080000, pll3, 4, 1, 4),
+ F_MND16( 61440000, pll3, 4, 1, 3),
+ F_MND16( 73728000, pll3, 2, 1, 5),
+ F_MND16( 81920000, pll3, 3, 1, 3),
+ F_MND16( 92160000, pll3, 4, 1, 2),
+ F_MND16( 98304000, pll3, 3, 2, 5),
+ F_MND16(105326000, pll3, 2, 2, 7),
+ F_MND16(122880000, pll3, 2, 1, 3),
+ F_MND16(147456000, pll3, 2, 2, 5),
+ F_MND16(153600000, pll1, 2, 2, 5),
+ F_MND16(192000000, pll1, 4, 0, 0),
F_END,
};
@@ -1970,6 +2031,7 @@
.c = {
.dbg_name = "jpeg_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(jpeg_clk.c),
.depends = &axi_li_jpeg_clk.c,
},
@@ -1993,6 +2055,7 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(vfe_clk.c),
.depends = &axi_li_vfe_clk.c,
},
@@ -2047,16 +2110,16 @@
};
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 6000000, pll1, 4, 1, 32, NOMINAL),
- F_MND16( 8000000, pll1, 4, 1, 24, NOMINAL),
- F_MND16(12000000, pll1, 4, 1, 16, NOMINAL),
- F_MND16(16000000, pll1, 4, 1, 12, NOMINAL),
- F_MND16(19200000, pll1, 4, 1, 10, NOMINAL),
- F_MND16(24000000, pll1, 4, 1, 8, NOMINAL),
- F_MND16(32000000, pll1, 4, 1, 6, NOMINAL),
- F_MND16(48000000, pll1, 4, 1, 4, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 6000000, pll1, 4, 1, 32),
+ F_MND16( 8000000, pll1, 4, 1, 24),
+ F_MND16(12000000, pll1, 4, 1, 16),
+ F_MND16(16000000, pll1, 4, 1, 12),
+ F_MND16(19200000, pll1, 4, 1, 10),
+ F_MND16(24000000, pll1, 4, 1, 8),
+ F_MND16(32000000, pll1, 4, 1, 6),
+ F_MND16(48000000, pll1, 4, 1, 4),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -2076,18 +2139,19 @@
.c = {
.dbg_name = "cam_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(cam_m_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 22, 15, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 22, 15, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 22, 15, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 22, 15, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 22, 15, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 22, 15, pll1, 1, 1, 5, NOMINAL),
+ F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 22, 15, pll3, 4, 1, 6),
+ F_MND8( 61440000, 22, 15, pll3, 4, 1, 3),
+ F_MND8( 81920000, 22, 15, pll3, 3, 1, 3),
+ F_MND8(122880000, 22, 15, pll3, 3, 1, 2),
+ F_MND8(147456000, 22, 15, pll3, 1, 1, 5),
+ F_MND8(153600000, 22, 15, pll1, 1, 1, 5),
F_END,
};
@@ -2109,21 +2173,21 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 153600000),
CLK_INIT(vpe_clk.c),
.depends = &axi_vpe_clk.c,
},
};
-
static struct clk_freq_tbl clk_tbl_mfc[] = {
- F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 24, 17, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 24, 17, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 24, 17, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 24, 17, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 24, 17, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 24, 17, pll1, 1, 1, 5, NOMINAL),
- F_MND8(170667000, 24, 17, pll1, 1, 2, 9, NOMINAL),
+ F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 24, 17, pll3, 4, 1, 6),
+ F_MND8( 61440000, 24, 17, pll3, 4, 1, 3),
+ F_MND8( 81920000, 24, 17, pll3, 3, 1, 3),
+ F_MND8(122880000, 24, 17, pll3, 3, 1, 2),
+ F_MND8(147456000, 24, 17, pll3, 1, 1, 5),
+ F_MND8(153600000, 24, 17, pll1, 1, 1, 5),
+ F_MND8(170667000, 24, 17, pll1, 1, 2, 9),
F_END,
};
@@ -2145,6 +2209,7 @@
.c = {
.dbg_name = "mfc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 170667000),
CLK_INIT(mfc_clk.c),
.depends = &axi_mfc_clk.c,
},
@@ -2167,9 +2232,9 @@
};
static struct clk_freq_tbl clk_tbl_spi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 9963243, 19, 12, pll3, 4, 2, 37, NOMINAL),
- F_MND8(26331429, 19, 12, pll3, 4, 1, 7, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 9963243, 19, 12, pll3, 4, 2, 37),
+ F_MND8(26331429, 19, 12, pll3, 4, 1, 7),
F_END,
};
@@ -2191,15 +2256,16 @@
.c = {
.dbg_name = "spi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 26331429),
CLK_INIT(spi_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL), /* src MI2S_CODEC_RX */
- F_RAW(2, NULL, 0, 1, 0, 0, LOW, NULL), /* src ECODEC_CIF */
- F_RAW(3, NULL, 0, 2, 0, 0, LOW, NULL), /* src MI2S */
- F_RAW(4, NULL, 0, 3, 0, 0, LOW, NULL), /* src SDAC */
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL), /* src MI2S_CODEC_RX */
+ F_RAW(2, NULL, 0, 1, 0, 0, NULL), /* src ECODEC_CIF */
+ F_RAW(3, NULL, 0, 2, 0, 0, NULL), /* src MI2S */
+ F_RAW(4, NULL, 0, 3, 0, 0, NULL), /* src SDAC */
F_END,
};
@@ -2219,12 +2285,13 @@
.c = {
.dbg_name = "lpa_codec_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 4),
CLK_INIT(lpa_codec_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdc[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL),
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL),
F_END
};
@@ -2244,6 +2311,7 @@
.c = {
.dbg_name = "mdc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 1),
CLK_INIT(mdc_clk.c),
},
};
@@ -2368,32 +2436,6 @@
static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_fixed_clk.c);
static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_fixed_clk.c);
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm7x30_update_sys_vdd(enum sys_vdd_level level)
-{
- int rc, target_mv;
- static const int mv[NUM_SYS_VDD_LEVELS] = {
- [NONE...LOW] = 1000,
- [NOMINAL] = 1100,
- [HIGH] = 1200,
- };
-
- target_mv = mv[level];
- rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
- if (rc)
- goto out;
- if (target_mv) {
- rc = -EINVAL;
- goto out;
- }
-out:
- return rc;
-}
-
#ifdef CONFIG_DEBUG_FS
#define CLK_TEST_2(s) (s)
@@ -2739,7 +2781,7 @@
{ CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL) },
{ CLK_LOOKUP("ebi1_fixed_clk", ebi1_fixed_clk.c, NULL) },
{ CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL) },
- { CLK_LOOKUP("gp_clk", gp_clk.c, NULL) },
+ { CLK_LOOKUP("core_clk", gp_clk.c, NULL) },
{ CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2") },
{ CLK_LOOKUP("usb_phy_clk", usb_phy_clk.c, NULL) },
@@ -2947,8 +2989,6 @@
print_ownership();
set_clock_ownership();
- soc_update_sys_vdd = msm7x30_update_sys_vdd;
-
/* When we have no local clock control, the rest of the code in this
* function is a NOP since writes to shadow regions that we don't own
* are ignored. */
@@ -2990,7 +3030,7 @@
static struct clk_ops clk_ops_rcg_7x30 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
.get_rate = rcg_clk_get_rate,
@@ -3006,7 +3046,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = soc_branch_clk_reset,
.set_flags = soc_clk_set_flags,
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 4ce0cf6..615a6b5 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -426,6 +426,41 @@
};
#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 0,
+ [VDD_DIG_LOW] = 945000,
+ [VDD_DIG_NOMINAL] = 1050000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
+ vdd_uv[level], 1150000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
/*
* Clock Descriptions
*/
@@ -556,24 +591,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8960_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 0,
- [LOW] = 945000,
- [NOMINAL] = 1050000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -582,7 +599,7 @@
static struct clk_ops clk_ops_rcg_8960 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
@@ -598,7 +615,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -1187,34 +1204,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1251,29 +1268,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1290,17 +1307,16 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_QDSS(f, s, d, v) \
+#define F_QDSS(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_qdss[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(128000000, pll8, 3, LOW),
- F_QDSS(300000000, pll3, 4, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(128000000, pll8, 3),
+ F_QDSS(300000000, pll3, 4),
F_END
};
@@ -1416,7 +1432,7 @@
const struct qdss_bank *bank = clk->bank_info;
u32 reg, bank_sel_mask = bank->bank_sel_mask;
- rcg_clk_auto_off(c);
+ rcg_clk_disable(c);
/* Switch to bank 0 */
reg = readl_relaxed(clk->ns_reg);
reg &= ~bank_sel_mask;
@@ -1460,6 +1476,7 @@
.c = {
.dbg_name = "qdss_at_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_at_clk.c),
},
};
@@ -1506,14 +1523,15 @@
.c = {
.dbg_name = "qdss_traceclkin_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_traceclkin_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(200000000, pll3, 6, LOW),
- F_QDSS(400000000, pll3, 3, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(200000000, pll3, 6),
+ F_QDSS(400000000, pll3, 3),
F_END
};
@@ -1541,6 +1559,7 @@
.c = {
.dbg_name = "qdss_tsctr_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 200000000, NOMINAL, 400000000),
CLK_INIT(qdss_tsctr_clk.c),
},
};
@@ -1562,16 +1581,15 @@
},
};
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1593,6 +1611,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1611,14 +1630,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1636,11 +1654,12 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
-#define CLK_SDC(name, n, h_b, f_table) \
+#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
struct rcg_clk name = { \
.b = { \
.ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
@@ -1655,85 +1674,54 @@
.root_en_mask = BIT(11), \
.ns_mask = (BM(23, 16) | BM(6, 0)), \
.set_rate = set_rate_mnd, \
- .freq_tbl = f_table, \
+ .freq_tbl = clk_tbl_sdc, \
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
+static struct clk_freq_tbl clk_tbl_sdc[] = {
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
+ F_SDC( 64000000, pll8, 3, 1, 2),
+ F_SDC( 96000000, pll8, 4, 0, 0),
F_END
};
-static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
-static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
+static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
+static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
+static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
+static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
+static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
-static struct clk_freq_tbl clk_tbl_sdc3[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, LOW),
- F_SDC( 96000000, pll8, 4, 0, 0, LOW),
- F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
-
-static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
-static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
-
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1754,20 +1742,20 @@
.c = {
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
CLK_INIT(tsif_ref_clk.c),
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1786,6 +1774,7 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
@@ -1810,22 +1799,22 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1834,8 +1823,8 @@
CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, LOW),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1856,6 +1845,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 60000000),
CLK_INIT(usb_hsic_xcvr_fs_clk.c),
},
};
@@ -1877,14 +1867,13 @@
},
};
-#define F_USB_HSIC(f, s, v) \
+#define F_USB_HSIC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
- F_USB_HSIC(480000000, pll14, LOW),
+ F_USB_HSIC(480000000, pll14),
F_END
};
@@ -1900,6 +1889,7 @@
.c = {
.dbg_name = "usb_hsic_hsic_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 480000000),
CLK_INIT(usb_hsic_hsic_src_clk.c),
},
};
@@ -1919,14 +1909,13 @@
},
};
-#define F_USB_HSIO_CAL(f, s, v) \
+#define F_USB_HSIO_CAL(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
- F_USB_HSIO_CAL(9000000, pxo, LOW),
+ F_USB_HSIO_CAL(9000000, pxo),
F_END
};
@@ -1943,6 +1932,7 @@
.c = {
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 10000000),
CLK_INIT(usb_hsic_hsio_cal_clk.c),
},
};
@@ -1959,7 +1949,7 @@
},
};
-#define CLK_USB_FS(i, n) \
+#define CLK_USB_FS(i, n, fmax_nom) \
struct rcg_clk i##_clk = { \
.ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
.b = { \
@@ -1975,11 +1965,12 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
CLK_INIT(i##_clk.c), \
}, \
}
-static CLK_USB_FS(usb_fs1_src, 1);
+static CLK_USB_FS(usb_fs1_src, 1, 64000000);
static struct branch_clk usb_fs1_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
@@ -2014,7 +2005,7 @@
},
};
-static CLK_USB_FS(usb_fs2_src, 2);
+static CLK_USB_FS(usb_fs2_src, 2, 60000000);
static struct branch_clk usb_fs2_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
@@ -2078,18 +2069,17 @@
},
};
-#define F_CE3(f, s, d, v) \
+#define F_CE3(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ce3[] = {
- F_CE3( 0, gnd, 1, NONE),
- F_CE3( 48000000, pll8, 8, LOW),
- F_CE3(100000000, pll3, 12, NOMINAL),
+ F_CE3( 0, gnd, 1),
+ F_CE3( 48000000, pll8, 8),
+ F_CE3(100000000, pll3, 12),
F_END
};
@@ -2107,6 +2097,7 @@
.c = {
.dbg_name = "ce3_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
CLK_INIT(ce3_src_clk.c),
},
};
@@ -2681,10 +2672,11 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2692,21 +2684,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2714,7 +2705,7 @@
static CLK_CAM(cam1_clk, 1, 16);
static CLK_CAM(cam2_clk, 2, 31);
-#define F_CSI(f, s, d, m, n, v) \
+#define F_CSI(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2722,12 +2713,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, 0, 0, NONE),
- F_CSI( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI( 0, gnd, 1, 0, 0),
+ F_CSI( 85330000, pll8, 1, 2, 9),
+ F_CSI(177780000, pll2, 1, 2, 9),
F_END
};
@@ -2747,6 +2737,7 @@
.c = {
.dbg_name = "csi0_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi0_src_clk.c),
},
};
@@ -2801,6 +2792,7 @@
.c = {
.dbg_name = "csi1_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi1_src_clk.c),
},
};
@@ -2855,6 +2847,7 @@
.c = {
.dbg_name = "csi2_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi2_src_clk.c),
},
};
@@ -3076,7 +3069,7 @@
},
};
-#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
+#define F_CSI_PHYTIMER(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3084,12 +3077,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
- F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
- F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
+ F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
+ F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
F_END
};
@@ -3109,6 +3101,7 @@
.c = {
.dbg_name = "csiphy_timer_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csiphy_timer_src_clk.c),
},
};
@@ -3261,7 +3254,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3269,22 +3262,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -3324,6 +3316,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -3364,11 +3358,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3376,69 +3372,80 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(300000000, pll3, 1, 4),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 300000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
/* TODO: need to add 325MHz back once it is fixed in the simulation model */
static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 325000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -3475,12 +3482,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_VCAP(f, s, m, n, v) \
+#define F_VCAP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3488,18 +3497,17 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcap[] = {
- F_VCAP( 0, gnd, 0, 0, NONE),
- F_VCAP( 27000000, pxo, 0, 0, LOW),
- F_VCAP( 54860000, pll8, 1, 7, LOW),
- F_VCAP( 64000000, pll8, 1, 6, LOW),
- F_VCAP( 76800000, pll8, 1, 5, LOW),
- F_VCAP(128000000, pll8, 1, 3, NOMINAL),
- F_VCAP(160000000, pll2, 1, 5, NOMINAL),
- F_VCAP(200000000, pll2, 1, 4, NOMINAL),
+ F_VCAP( 0, gnd, 0, 0),
+ F_VCAP( 27000000, pxo, 0, 0),
+ F_VCAP( 54860000, pll8, 1, 7),
+ F_VCAP( 64000000, pll8, 1, 6),
+ F_VCAP( 76800000, pll8, 1, 5),
+ F_VCAP(128000000, pll8, 1, 3),
+ F_VCAP(160000000, pll2, 1, 5),
+ F_VCAP(200000000, pll2, 1, 4),
F_END
};
@@ -3538,6 +3546,7 @@
.dbg_name = "vcap_clk",
.ops = &clk_ops_rcg_8960,
.depends = &vcap_axi_clk.c,
+ VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
CLK_INIT(vcap_clk.c),
},
};
@@ -3557,7 +3566,7 @@
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3565,37 +3574,34 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_ijpeg_8960[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_ijpeg[] = {
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
+ F_IJPEG(266667000, pll2, 1, 1, 3),
+ F_IJPEG(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_ijpeg_8064[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, LOW),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk ijpeg_clk = {
@@ -3613,30 +3619,30 @@
.ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_ijpeg_8960,
+ .freq_tbl = clk_tbl_ijpeg,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -3658,12 +3664,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3671,44 +3678,30 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_mdp_8960[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+static struct clk_freq_tbl clk_tbl_mdp[] = {
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
+ F_MDP(266667000, pll2, 1, 3),
F_END
};
-static struct clk_freq_tbl clk_tbl_mdp_8064[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, LOW),
- F_MDP(128000000, pll8, 1, 3, LOW),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
- F_MDP(266000000, pll2, 1, 3, NOMINAL),
- F_END
+static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000
};
static struct bank_masks bmnd_info_mdp = {
@@ -3741,12 +3734,13 @@
.ns_reg = MDP_NS_REG,
.root_en_mask = BIT(2),
.set_rate = set_rate_mnd_banked,
- .freq_tbl = clk_tbl_mdp_8960,
+ .freq_tbl = clk_tbl_mdp,
.bank_info = &bmnd_info_mdp,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
@@ -3767,15 +3761,14 @@
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -3796,34 +3789,34 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, LOW),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
- F_ROT(200000000, pll2, 4, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
+ F_ROT(200000000, pll2, 4),
F_END
};
@@ -3855,6 +3848,7 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
@@ -3902,7 +3896,7 @@
CLK_INIT(hdmi_pll_clk),
};
-#define F_TV_GND(f, s, p_r, d, m, n, v) \
+#define F_TV_GND(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3910,9 +3904,8 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk, \
@@ -3920,20 +3913,24 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = (void *)p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
- F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
- F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
- F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
- F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
- F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
+ F_TV_GND( 0, gnd, 0, 1, 0, 0),
+ F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
+ F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
+ F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
+ F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
+ F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
F_END
};
+static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 74250000,
+ [VDD_DIG_NOMINAL] = 149000000
+};
+
/*
* Unlike other clocks, the TV rate is adjusted through PLL
* re-programming. It is also routed through an MND divider.
@@ -3962,6 +3959,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -4065,7 +4063,7 @@
.mode_mask = BM(12, 11),
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4073,18 +4071,17 @@
.ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
.ctl_val = CC_BANKED(6, 11, n), \
.mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -4106,28 +4103,29 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
F_END
};
@@ -4149,12 +4147,13 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4162,50 +4161,40 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_vfe_8960[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_vfe[] = {
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
+ F_VFE(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_vfe_8064[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, LOW),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk vfe_clk = {
@@ -4223,11 +4212,12 @@
.ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_vfe_8960,
+ .freq_tbl = clk_tbl_vfe,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -4253,28 +4243,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4299,6 +4288,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4323,6 +4313,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4421,28 +4412,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4466,6 +4456,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -4490,6 +4481,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -4979,25 +4971,25 @@
CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
- CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
- CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
+ CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
+ CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
- CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
- CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
- CLK_LOOKUP("sata_phy_ref_clk", sata_phy_ref_clk.c, NULL),
- CLK_LOOKUP("sata_phy_cfg_clk", sata_phy_cfg_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
+ CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
+ CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, NULL),
CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
@@ -5006,7 +4998,7 @@
CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
- CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
@@ -5021,11 +5013,11 @@
CLK_LOOKUP("iface_clk", ce3_p_clk.c, NULL),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
- CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", amp_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
@@ -5066,7 +5058,7 @@
CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, NULL),
CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
- CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
+ CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
@@ -5081,7 +5073,6 @@
CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
- CLK_LOOKUP("rot_axi_clk", rot_axi_clk.c, NULL),
CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, NULL),
CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, NULL),
CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, NULL),
@@ -5096,8 +5087,8 @@
CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
- CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
- CLK_LOOKUP("imem_pclk", imem_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
+ CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
@@ -5198,9 +5189,7 @@
CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
- CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
- CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
@@ -5210,7 +5199,7 @@
CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
- CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
+ CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
@@ -5247,11 +5236,11 @@
CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
- CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", amp_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
@@ -5288,10 +5277,10 @@
CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("imem_axi_clk", imem_axi_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
+ CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
@@ -5340,7 +5329,7 @@
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
@@ -5743,6 +5732,14 @@
sizeof(msm_clocks_8960_v1));
if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
+ sizeof(vfe_clk.c.fmax));
+
memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
num_lookups = ARRAY_SIZE(msm_clocks_8960);
@@ -5751,20 +5748,27 @@
}
/*
- * Change the freq tables for gfx3d_clk, ijpeg_clk, mdp_clk,
- * tv_src_clk and vfe_clk at runtime and chain gmem_axi_clk
- * with gfx3d_axi_clk for 8064.
+ * Change the freq tables for and voltage requirements for
+ * clocks which differ between 8960 and 8064.
*/
if (cpu_is_apq8064()) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
- ijpeg_clk.freq_tbl = clk_tbl_ijpeg_8064;
- mdp_clk.freq_tbl = clk_tbl_mdp_8064;
- vfe_clk.freq_tbl = clk_tbl_vfe_8064;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
+ sizeof(tv_src_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
+ sizeof(vfe_clk.c.fmax));
+
gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
}
- soc_update_sys_vdd = msm8960_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -5840,7 +5844,8 @@
rc = clk_enable(cfpb_a_clk);
if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
return rc;
- return local_unvote_sys_vdd(HIGH);
+
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8960_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 343cb88..f6dd39e 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -313,6 +313,41 @@
| BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
* !!(n))
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 500000,
+ [VDD_DIG_LOW] = 1000000,
+ [VDD_DIG_NOMINAL] = 1100000,
+ [VDD_DIG_HIGH] = 1200000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], 1200000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
static struct msm_xo_voter *xo_pxo, *xo_cxo;
static bool xo_clk_is_local(struct clk *clk)
@@ -498,24 +533,6 @@
writel_relaxed(pll_mode, MM_PLL2_MODE_REG);
}
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8660_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 500000,
- [LOW] = 1000000,
- [NOMINAL] = 1100000,
- [HIGH] = 1200000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -524,7 +541,7 @@
static struct clk_ops clk_ops_rcg_8x60 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
@@ -540,7 +557,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -1053,34 +1070,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1117,29 +1134,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1156,16 +1173,15 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1187,6 +1203,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1205,14 +1222,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1230,6 +1246,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -1254,27 +1271,27 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC(16000000, pll8, 4, 1, 6, LOW),
- F_SDC(17070000, pll8, 1, 2, 45, LOW),
- F_SDC(20210000, pll8, 1, 1, 19, LOW),
- F_SDC(24000000, pll8, 4, 1, 4, LOW),
- F_SDC(48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC(16000000, pll8, 4, 1, 6),
+ F_SDC(17070000, pll8, 1, 2, 45),
+ F_SDC(20210000, pll8, 1, 1, 19),
+ F_SDC(24000000, pll8, 4, 1, 4),
+ F_SDC(48000000, pll8, 4, 1, 2),
F_END
};
@@ -1284,18 +1301,17 @@
static CLK_SDC(sdc4, 4, CLK_HALT_DFAB_STATE_REG, 3);
static CLK_SDC(sdc5, 5, CLK_HALT_DFAB_STATE_REG, 2);
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1320,16 +1336,15 @@
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1348,22 +1363,22 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1386,6 +1401,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -1418,6 +1434,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -2014,7 +2031,7 @@
},
};
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2022,21 +2039,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2057,21 +2073,21 @@
.c = {
.dbg_name = "cam_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000),
CLK_INIT(cam_clk.c),
},
};
-#define F_CSI(f, s, d, v) \
+#define F_CSI(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, NONE),
- F_CSI(192000000, pll8, 2, LOW),
- F_CSI(384000000, pll8, 1, NOMINAL),
+ F_CSI( 0, gnd, 1),
+ F_CSI(192000000, pll8, 2),
+ F_CSI(384000000, pll8, 1),
F_END
};
@@ -2089,6 +2105,7 @@
.c = {
.dbg_name = "csi_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 192000000, NOMINAL, 384000000),
CLK_INIT(csi_src_clk.c),
},
};
@@ -2178,7 +2195,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2186,22 +2203,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -2241,6 +2257,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -2281,11 +2299,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2293,24 +2313,23 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, HIGH),
- F_GFX3D(266667000, pll2, 1, 3, HIGH),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
@@ -2350,12 +2369,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 96000000, NOMINAL, 200000000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2363,19 +2384,18 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!n, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ijpeg[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
F_END
};
@@ -2399,25 +2419,25 @@
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 228571000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -2439,12 +2459,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2452,24 +2473,23 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
F_END
};
@@ -2509,20 +2529,21 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 85330000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -2543,11 +2564,12 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_PIXEL_MDP(f, s, d, m, n, v) \
+#define F_PIXEL_MDP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2555,21 +2577,20 @@
.ns_val = NS_MM(31, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pixel_mdp[] = {
- F_PIXEL_MDP( 0, gnd, 1, 0, 0, NONE),
- F_PIXEL_MDP( 25600000, pll8, 3, 1, 5, LOW),
- F_PIXEL_MDP( 42667000, pll8, 1, 1, 9, LOW),
- F_PIXEL_MDP( 43192000, pll8, 1, 64, 569, LOW),
- F_PIXEL_MDP( 48000000, pll8, 4, 1, 2, LOW),
- F_PIXEL_MDP( 53990000, pll8, 2, 169, 601, LOW),
- F_PIXEL_MDP( 64000000, pll8, 2, 1, 3, LOW),
- F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280, LOW),
- F_PIXEL_MDP( 76800000, pll8, 1, 1, 5, LOW),
- F_PIXEL_MDP( 85333000, pll8, 1, 2, 9, LOW),
- F_PIXEL_MDP(106500000, pll8, 1, 71, 256, NOMINAL),
- F_PIXEL_MDP(109714000, pll8, 1, 2, 7, NOMINAL),
+ F_PIXEL_MDP( 0, gnd, 1, 0, 0),
+ F_PIXEL_MDP( 25600000, pll8, 3, 1, 5),
+ F_PIXEL_MDP( 42667000, pll8, 1, 1, 9),
+ F_PIXEL_MDP( 43192000, pll8, 1, 64, 569),
+ F_PIXEL_MDP( 48000000, pll8, 4, 1, 2),
+ F_PIXEL_MDP( 53990000, pll8, 2, 169, 601),
+ F_PIXEL_MDP( 64000000, pll8, 2, 1, 3),
+ F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280),
+ F_PIXEL_MDP( 76800000, pll8, 1, 1, 5),
+ F_PIXEL_MDP( 85333000, pll8, 1, 2, 9),
+ F_PIXEL_MDP(106500000, pll8, 1, 71, 256),
+ F_PIXEL_MDP(109714000, pll8, 1, 2, 7),
F_END
};
@@ -2593,6 +2614,7 @@
.c = {
.dbg_name = "pixel_mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 85333000, NOMINAL, 170000000),
CLK_INIT(pixel_mdp_clk.c),
},
};
@@ -2612,29 +2634,28 @@
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, NOMINAL),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
F_END
};
@@ -2666,12 +2687,13 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
};
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2679,7 +2701,6 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
@@ -2691,12 +2712,12 @@
[4] = PLL_RATE(44, 0, 0, 2, 4, 0x6248F), /* 297000000 Hz */
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0, NONE),
- F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0, LOW),
- F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0, LOW),
- F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0, LOW),
- F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0, NOMINAL),
- F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0, NOMINAL),
+ F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0),
+ F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0),
+ F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0),
+ F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0),
+ F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0),
+ F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0),
F_END
};
@@ -2716,6 +2737,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -2802,7 +2824,7 @@
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2810,18 +2832,17 @@
.ns_val = NS_MM(18, 11, n, m, 0, 0, 1, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -2845,29 +2866,30 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
- F_VPE(200000000, pll2, 4, HIGH),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
+ F_VPE(200000000, pll2, 4),
F_END
};
@@ -2889,12 +2911,14 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 76800000, NOMINAL, 160000000,
+ HIGH, 200000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2902,26 +2926,25 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vfe[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, HIGH),
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
F_END
};
@@ -2945,6 +2968,8 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 228570000,
+ HIGH, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -2987,27 +3012,26 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 768000, pll4, 4, 1, 176, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 132, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 88, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 66, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 44, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 33, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 22, LOW),
- F_AIF_OSR( 8192000, pll4, 2, 1, 33, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 11, LOW),
- F_AIF_OSR(24576000, pll4, 2, 1, 11, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 768000, pll4, 4, 1, 176),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 132),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 88),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 66),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 44),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 33),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 22),
+ F_AIF_OSR( 8192000, pll4, 2, 1, 33),
+ F_AIF_OSR(12288000, pll4, 4, 1, 11),
+ F_AIF_OSR(24576000, pll4, 2, 1, 11),
F_END
};
@@ -3032,6 +3056,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -3094,28 +3119,27 @@
static CLK_AIF_BIT(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 264, LOW),
- F_PCM( 768000, pll4, 4, 1, 176, LOW),
- F_PCM( 1024000, pll4, 4, 1, 132, LOW),
- F_PCM( 1536000, pll4, 4, 1, 88, LOW),
- F_PCM( 2048000, pll4, 4, 1, 66, LOW),
- F_PCM( 3072000, pll4, 4, 1, 44, LOW),
- F_PCM( 4096000, pll4, 4, 1, 33, LOW),
- F_PCM( 6144000, pll4, 4, 1, 22, LOW),
- F_PCM( 8192000, pll4, 2, 1, 33, LOW),
- F_PCM(12288000, pll4, 4, 1, 11, LOW),
- F_PCM(24580000, pll4, 2, 1, 11, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 264),
+ F_PCM( 768000, pll4, 4, 1, 176),
+ F_PCM( 1024000, pll4, 4, 1, 132),
+ F_PCM( 1536000, pll4, 4, 1, 88),
+ F_PCM( 2048000, pll4, 4, 1, 66),
+ F_PCM( 3072000, pll4, 4, 1, 44),
+ F_PCM( 4096000, pll4, 4, 1, 33),
+ F_PCM( 6144000, pll4, 4, 1, 22),
+ F_PCM( 8192000, pll4, 2, 1, 33),
+ F_PCM(12288000, pll4, 4, 1, 11),
+ F_PCM(24580000, pll4, 2, 1, 11),
F_END
};
@@ -3139,6 +3163,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 24580000),
CLK_INIT(pcm_clk.c),
},
};
@@ -3567,7 +3592,7 @@
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("gsbi_qup_clk", gsbi12_qup_clk.c, "msm_dsps"),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.5"),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_dsps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
@@ -3577,7 +3602,7 @@
CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.1"),
- CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
+ CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
@@ -3623,11 +3648,11 @@
CLK_LOOKUP("iface_clk", adm1_p_clk.c, "msm_dmov.1"),
CLK_LOOKUP("modem_ahb1_pclk", modem_ahb1_p_clk.c, NULL),
CLK_LOOKUP("modem_ahb2_pclk", modem_ahb2_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
- CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", amp_clk.c, NULL),
CLK_LOOKUP("cam_clk", cam_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov7692.0"),
@@ -3643,7 +3668,7 @@
CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
+ CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
@@ -3689,7 +3714,7 @@
CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
- CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
@@ -3843,7 +3868,6 @@
/* Local clock driver initialization. */
static void __init msm8660_clock_init(void)
{
- soc_update_sys_vdd = msm8660_update_sys_vdd;
xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8x60");
if (IS_ERR(xo_pxo)) {
pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
@@ -3855,7 +3879,7 @@
BUG();
}
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
/* Initialize clock registers. */
reg_init();
@@ -3893,11 +3917,7 @@
if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
return rc;
- /* Remove temporary vote for HIGH vdd_dig. */
- rc = local_unvote_sys_vdd(HIGH);
- WARN(rc, "local_unvote_sys_vdd(HIGH) failed (%d)\n", rc);
-
- return rc;
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8x60_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 63d3f72..dca8268 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -185,6 +185,36 @@
#define NS_SRC_SEL(s_msb, s_lsb, s) \
BVAL(s_msb, s_lsb, s)
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ /* TODO: Update these voltages when info becomes available. */
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 1150000,
+ [VDD_DIG_LOW] = 1150000,
+ [VDD_DIG_NOMINAL] = 1150000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], vdd_uv[VDD_DIG_HIGH], 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
/*
* Clock Descriptions
@@ -283,24 +313,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* TODO: Update these voltages when info becomes available. */
-/* Update the sys_vdd voltage given a level. */
-static int msm9615_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE...LOW] = 1150000,
- [NOMINAL] = 1150000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -309,7 +321,7 @@
static struct clk_ops clk_ops_rcg_9615 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
- .auto_off = rcg_clk_auto_off,
+ .auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.set_min_rate = rcg_clk_set_min_rate,
.get_rate = rcg_clk_get_rate,
@@ -324,7 +336,7 @@
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
- .auto_off = branch_clk_auto_off,
+ .auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.is_local = local_clk_is_local,
@@ -355,33 +367,33 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -411,28 +423,28 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 960000, cxo, 4, 1, 5, LOW),
- F_GSBI_QUP( 4800000, cxo, 4, 0, 1, LOW),
- F_GSBI_QUP( 9600000, cxo, 2, 0, 1, LOW),
- F_GSBI_QUP(15058800, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 960000, cxo, 4, 1, 5),
+ F_GSBI_QUP( 4800000, cxo, 4, 0, 1),
+ F_GSBI_QUP( 9600000, cxo, 2, 0, 1),
+ F_GSBI_QUP(15058800, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -442,16 +454,15 @@
static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(19200000, cxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(19200000, cxo, 1),
F_END
};
@@ -473,6 +484,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 19200000),
CLK_INIT(pdm_clk.c),
},
};
@@ -491,14 +503,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(32000000, pll8, LOW),
+ F_PRNG(32000000, pll8),
F_END
};
@@ -516,6 +527,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -540,45 +552,44 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144300, cxo, 1, 1, 133, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144300, cxo, 1, 1, 133),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
F_END
};
static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -601,6 +612,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -624,6 +636,7 @@
.c = {
.dbg_name = "usb_hs1_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_sys_clk.c),
},
};
@@ -647,6 +660,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_xcvr_clk.c),
},
};
@@ -670,13 +684,14 @@
.c = {
.dbg_name = "usb_hsic_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_sys_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(480000000, pll14, 1, 0, 1, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(480000000, pll14, 1, 0, 1),
F_END
};
@@ -699,6 +714,7 @@
.c = {
.dbg_name = "usb_hsic_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 480000000),
CLK_INIT(usb_hsic_clk.c),
},
};
@@ -980,28 +996,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1148,28 +1163,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1193,6 +1207,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -1217,6 +1232,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -1520,13 +1536,13 @@
CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.0"),
- CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
- CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
- CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
@@ -1547,10 +1563,10 @@
CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
- CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
- CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
- CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
@@ -1717,8 +1733,7 @@
BUG();
}
- soc_update_sys_vdd = msm9615_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -1744,7 +1759,7 @@
static int __init msm9615_clock_late_init(void)
{
- return local_unvote_sys_vdd(HIGH);
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm9615_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index c0af9b5..4e0d3e9 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -170,10 +170,25 @@
static int list_rates_show(struct seq_file *m, void *unused)
{
struct clk *clock = m->private;
- int rate, i = 0;
+ int rate, level, fmax = 0, i = 0;
- while ((rate = clock->ops->list_rate(clock, i++)) >= 0)
- seq_printf(m, "%d\n", rate);
+ /* Find max frequency supported within voltage constraints. */
+ if (!clock->vdd_class) {
+ fmax = ULONG_MAX;
+ } else {
+ for (level = 0; level < ARRAY_SIZE(clock->fmax); level++)
+ if (clock->fmax[level])
+ fmax = clock->fmax[level];
+ }
+
+ /*
+ * List supported frequencies <= fmax. Higher frequencies may appear in
+ * the frequency table, but are not valid and should not be listed.
+ */
+ while ((rate = clock->ops->list_rate(clock, i++)) >= 0) {
+ if (rate <= fmax)
+ seq_printf(m, "%u\n", rate);
+ }
return 0;
}
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index ea76512..473b439 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -48,9 +48,6 @@
DEFINE_SPINLOCK(local_clock_reg_lock);
struct clk_freq_tbl rcg_dummy_freq = F_END;
-unsigned local_sys_vdd_votes[NUM_SYS_VDD_LEVELS];
-static DEFINE_SPINLOCK(sys_vdd_vote_lock);
-
/*
* Common Set-Rate Functions
*/
@@ -264,81 +261,6 @@
clk->ns_mask = new_bank_masks->ns_mask;
}
-int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
- * SYS_VDD voting functions
- */
-
-/* Update system voltage level given the current votes. */
-static int local_update_sys_vdd(void)
-{
- static int cur_level = NUM_SYS_VDD_LEVELS;
- int level, rc = 0;
-
- if (local_sys_vdd_votes[HIGH])
- level = HIGH;
- else if (local_sys_vdd_votes[NOMINAL])
- level = NOMINAL;
- else if (local_sys_vdd_votes[LOW])
- level = LOW;
- else
- level = NONE;
-
- if (level == cur_level)
- return rc;
-
- rc = soc_update_sys_vdd(level);
- if (!rc)
- cur_level = level;
-
- return rc;
-}
-
-/* Vote for a system voltage level. */
-int local_vote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
- local_sys_vdd_votes[level]++;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]--;
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
-
- return rc;
-}
-
-/* Remove vote for a system voltage level. */
-int local_unvote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
-
- if (WARN(!local_sys_vdd_votes[level],
- "Reference counts are incorrect for level %d!\n", level))
- goto out;
-
- local_sys_vdd_votes[level]--;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]++;
-out:
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
- return rc;
-}
/*
* Clock enable/disable functions
*/
@@ -486,19 +408,25 @@
}
}
-static void _rcg_clk_enable(struct rcg_clk *clk)
+/* Enable a rate-settable clock. */
+int rcg_clk_enable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_enable_reg(clk);
clk->enabled = true;
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+ return 0;
}
-static void _rcg_clk_disable(struct rcg_clk *clk)
+/* Disable a rate-settable clock. */
+void rcg_clk_disable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_disable_reg(clk);
@@ -506,34 +434,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-/* Enable a clock and any related power rail. */
-int rcg_clk_enable(struct clk *c)
-{
- int rc;
- struct rcg_clk *clk = to_rcg_clk(c);
-
- rc = local_vote_sys_vdd(clk->current_freq->sys_vdd);
- if (rc)
- return rc;
- _rcg_clk_enable(clk);
- return rc;
-}
-
-/* Disable a clock and any related power rail. */
-void rcg_clk_disable(struct clk *c)
-{
- struct rcg_clk *clk = to_rcg_clk(c);
-
- _rcg_clk_disable(clk);
- local_unvote_sys_vdd(clk->current_freq->sys_vdd);
-}
-
-/* Turn off a clock at boot, without checking refcounts. */
-void rcg_clk_auto_off(struct clk *c)
-{
- _rcg_clk_disable(to_rcg_clk(c));
-}
-
/*
* Frequency-related functions
*/
@@ -544,25 +444,17 @@
struct clk_freq_tbl *cf;
int rc = 0;
struct clk *chld;
- unsigned long flags;
-
- spin_lock_irqsave(&clk->c.lock, flags);
/* Check if frequency is actually changed. */
cf = clk->current_freq;
if (nf == cf)
- goto unlock;
+ return 0;
if (clk->enabled) {
- /* Vote for voltage and source for new freq. */
- rc = local_vote_sys_vdd(nf->sys_vdd);
- if (rc)
- goto unlock;
+ /* Enable source clock dependency for the new freq. */
rc = clk_enable(nf->src_clk);
- if (rc) {
- local_unvote_sys_vdd(nf->sys_vdd);
- goto unlock;
- }
+ if (rc)
+ return rc;
}
spin_lock(&local_clock_reg_lock);
@@ -608,13 +500,9 @@
spin_unlock(&local_clock_reg_lock);
- /* Release requirements of the old freq. */
- if (clk->enabled) {
+ /* Release source requirements of the old freq. */
+ if (clk->enabled)
clk_disable(cf->src_clk);
- local_unvote_sys_vdd(cf->sys_vdd);
- }
-unlock:
- spin_unlock_irqrestore(&clk->c.lock, flags);
return rc;
}
@@ -985,16 +873,6 @@
return branch->enabled;
}
-void branch_clk_auto_off(struct clk *clk)
-{
- struct branch_clk *branch = to_branch_clk(clk);
- unsigned long flags;
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- __branch_clk_disable_reg(&branch->b, branch->c.dbg_name);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
int branch_reset(struct branch *clk, enum clk_reset_action action)
{
int ret = 0;
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index f62e753..ec2462a 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -74,22 +74,17 @@
const struct bank_mask_info bank1_mask;
};
-#define F_RAW(f, sc, m_v, n_v, c_v, m_m, v, e) { \
+#define F_RAW(f, sc, m_v, n_v, c_v, m_m, e) { \
.freq_hz = f, \
.src_clk = sc, \
.md_val = m_v, \
.ns_val = n_v, \
.ctl_val = c_v, \
.mnd_en_mask = m_m, \
- .sys_vdd = v, \
.extra_freq_data = e, \
}
#define FREQ_END (UINT_MAX-1)
-#define F_END \
- { \
- .freq_hz = FREQ_END, \
- .sys_vdd = LOW, \
- }
+#define F_END { .freq_hz = FREQ_END }
/**
* struct branch - branch on/off
@@ -146,7 +141,6 @@
int rcg_clk_enable(struct clk *clk);
void rcg_clk_disable(struct clk *clk);
-void rcg_clk_auto_off(struct clk *clk);
int rcg_clk_set_rate(struct clk *clk, unsigned rate);
int rcg_clk_set_min_rate(struct clk *clk, unsigned rate);
unsigned rcg_clk_get_rate(struct clk *clk);
@@ -156,17 +150,6 @@
struct clk *rcg_clk_get_parent(struct clk *c);
int rcg_clk_handoff(struct clk *c);
-/*
- * SYS_VDD voltage levels
- */
-enum sys_vdd_level {
- NONE,
- LOW,
- NOMINAL,
- HIGH,
- NUM_SYS_VDD_LEVELS
-};
-
/**
* struct fixed_clk - fixed rate clock (used for crystal oscillators)
* @rate: output rate
@@ -268,7 +251,6 @@
struct clk *branch_clk_get_parent(struct clk *clk);
int branch_clk_set_parent(struct clk *clk, struct clk *parent);
int branch_clk_is_enabled(struct clk *clk);
-void branch_clk_auto_off(struct clk *clk);
int branch_clk_reset(struct clk *c, enum clk_reset_action action);
/**
@@ -301,16 +283,9 @@
/*
* Local-clock APIs
*/
-int local_vote_sys_vdd(enum sys_vdd_level level);
-int local_unvote_sys_vdd(enum sys_vdd_level level);
bool local_clk_is_local(struct clk *clk);
/*
- * Required SoC-specific functions, implemented for every supported SoC
- */
-extern int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 9a5e644..b176301 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -149,7 +149,7 @@
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
CLK_LOOKUP("emdh_clk", emdh_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
@@ -197,7 +197,7 @@
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "footswitch-pcom.2"),
CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
@@ -274,7 +274,7 @@
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "footswitch-pcom.2"),
CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
@@ -341,7 +341,7 @@
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
CLK_LOOKUP("emdh_clk", emdh_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
diff --git a/arch/arm/mach-msm/clock-rpm.c b/arch/arm/mach-msm/clock-rpm.c
index 286b3d0..2ccebb4 100644
--- a/arch/arm/mach-msm/clock-rpm.c
+++ b/arch/arm/mach-msm/clock-rpm.c
@@ -104,11 +104,6 @@
return;
}
-static void rpm_clk_auto_off(struct clk *clk)
-{
- /* Not supported */
-}
-
static int rpm_clk_set_min_rate(struct clk *clk, unsigned rate)
{
unsigned long flags;
@@ -194,7 +189,6 @@
struct clk_ops clk_ops_rpm = {
.enable = rpm_clk_enable,
.disable = rpm_clk_disable,
- .auto_off = rpm_clk_auto_off,
.set_min_rate = rpm_clk_set_min_rate,
.get_rate = rpm_clk_get_rate,
.is_enabled = rpm_clk_is_enabled,
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 58a64a3..de89382 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -24,13 +24,116 @@
#include "clock.h"
+/* Find the voltage level required for a given rate. */
+static int find_vdd_level(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ for (level = 0; level < ARRAY_SIZE(clk->fmax); level++)
+ if (rate <= clk->fmax[level])
+ break;
+
+ if (level == ARRAY_SIZE(clk->fmax)) {
+ pr_err("Rate %lu for %s is greater than highest Fmax\n", rate,
+ clk->dbg_name);
+ return -EINVAL;
+ }
+
+ return level;
+}
+
+/* Update voltage level given the current votes. */
+static int update_vdd(struct clk_vdd_class *vdd_class)
+{
+ int level, rc;
+
+ for (level = ARRAY_SIZE(vdd_class->level_votes)-1; level > 0; level--)
+ if (vdd_class->level_votes[level])
+ break;
+
+ if (level == vdd_class->cur_level)
+ return 0;
+
+ rc = vdd_class->set_vdd(vdd_class, level);
+ if (!rc)
+ vdd_class->cur_level = level;
+
+ return rc;
+}
+
+/* Vote for a voltage level. */
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ vdd_class->level_votes[level]++;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]--;
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+
+ return rc;
+}
+
+/* Remove vote for a voltage level. */
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ if (WARN(!vdd_class->level_votes[level],
+ "Reference counts are incorrect for %s level %d\n",
+ vdd_class->class_name, level))
+ goto out;
+ vdd_class->level_votes[level]--;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]++;
+out:
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+ return rc;
+}
+
+/* Vote for a voltage level corresponding to a clock's rate. */
+static int vote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return 0;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return level;
+
+ return vote_vdd_level(clk->vdd_class, level);
+}
+
+/* Remove vote for a voltage level corresponding to a clock's rate. */
+static void unvote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return;
+
+ unvote_vdd_level(clk->vdd_class, level);
+}
+
/*
* Standard clock functions defined in include/linux/clk.h
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
- unsigned long flags;
+ unsigned long flags, rate;
struct clk *parent;
if (!clk)
@@ -39,22 +142,22 @@
spin_lock_irqsave(&clk->lock, flags);
if (clk->count == 0) {
parent = clk_get_parent(clk);
+ rate = clk_get_rate(clk);
+
ret = clk_enable(parent);
if (ret)
- goto out;
+ goto err_enable_parent;
ret = clk_enable(clk->depends);
- if (ret) {
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_depends;
+ ret = vote_rate_vdd(clk, rate);
+ if (ret)
+ goto err_vote_vdd;
if (clk->ops->enable)
ret = clk->ops->enable(clk);
- if (ret) {
- clk_disable(clk->depends);
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_clock;
} else if (clk->flags & CLKFLAG_HANDOFF_RATE) {
/*
* The clock was already enabled by handoff code so there is no
@@ -69,6 +172,16 @@
out:
spin_unlock_irqrestore(&clk->lock, flags);
+ return 0;
+
+err_enable_clock:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ clk_disable(clk->depends);
+err_enable_depends:
+ clk_disable(parent);
+err_enable_parent:
+ spin_unlock_irqrestore(&clk->lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -76,7 +189,6 @@
void clk_disable(struct clk *clk)
{
unsigned long flags;
- struct clk *parent;
if (!clk)
return;
@@ -85,10 +197,13 @@
if (WARN(clk->count == 0, "%s is unbalanced", clk->dbg_name))
goto out;
if (clk->count == 1) {
+ struct clk *parent = clk_get_parent(clk);
+ unsigned long rate = clk_get_rate(clk);
+
if (clk->ops->disable)
clk->ops->disable(clk);
+ unvote_rate_vdd(clk, rate);
clk_disable(clk->depends);
- parent = clk_get_parent(clk);
clk_disable(parent);
}
clk->count--;
@@ -117,10 +232,35 @@
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned long start_rate, flags;
+ int rc;
+
if (!clk->ops->set_rate)
return -ENOSYS;
- return clk->ops->set_rate(clk, rate);
+ spin_lock_irqsave(&clk->lock, flags);
+ if (clk->count) {
+ start_rate = clk_get_rate(clk);
+ /* Enforce vdd requirements for target frequency. */
+ rc = vote_rate_vdd(clk, rate);
+ if (rc)
+ goto err_vote_vdd;
+ rc = clk->ops->set_rate(clk, rate);
+ if (rc)
+ goto err_set_rate;
+ /* Release vdd requirements for starting frequency. */
+ unvote_rate_vdd(clk, start_rate);
+ } else {
+ rc = clk->ops->set_rate(clk, rate);
+ }
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
+
+err_set_rate:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
}
EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index f4a7363..ed5c9c6 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -33,6 +33,32 @@
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
+#define MAX_VDD_LEVELS 4
+
+/**
+ * struct clk_vdd_class - Voltage scaling class
+ * @class_name: name of the class
+ * @set_vdd: function to call when applying a new voltage setting
+ * @level_votes: array of votes for each level
+ * @cur_level: the currently set voltage level
+ * @lock: lock to protect this struct
+ */
+struct clk_vdd_class {
+ const char *class_name;
+ int (*set_vdd)(struct clk_vdd_class *v_class, int level);
+ int level_votes[MAX_VDD_LEVELS];
+ unsigned cur_level;
+ spinlock_t lock;
+};
+
+#define DEFINE_VDD_CLASS(_name, _set_vdd) \
+ struct clk_vdd_class _name = { \
+ .class_name = #_name, \
+ .set_vdd = _set_vdd, \
+ .cur_level = ARRAY_SIZE(_name.level_votes), \
+ .lock = __SPIN_LOCK_UNLOCKED(lock) \
+ }
+
struct clk_ops {
int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
@@ -57,12 +83,16 @@
* @count: enable refcount
* @lock: protects clk_enable()/clk_disable() path and @count
* @depends: non-direct parent of clock to enable when this clock is enabled
+ * @vdd_class: voltage scaling requirement class
+ * @fmax: maximum frequency in Hz supported at each voltage level
*/
struct clk {
uint32_t flags;
struct clk_ops *ops;
const char *dbg_name;
struct clk *depends;
+ struct clk_vdd_class *vdd_class;
+ unsigned long fmax[MAX_VDD_LEVELS];
struct list_head children;
struct list_head siblings;
@@ -104,6 +134,8 @@
extern struct clock_init_data qds8x50_clock_init_data;
void msm_clock_init(struct clock_init_data *data);
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level);
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level);
#ifdef CONFIG_DEBUG_FS
int clock_debug_init(struct clock_init_data *data);
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index b567da3..694a70d 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -608,7 +608,7 @@
CLK_DUMMY("core_clk", GSBI5_QUP_CLK, "spi_qsd.0", OFF),
CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF),
CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF),
- CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
@@ -616,7 +616,7 @@
CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
CLK_DUMMY("ref_clk", TSIF_REF_CLK, NULL, OFF),
- CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS3_XCVR_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS4_XCVR_CLK, NULL, OFF),
@@ -632,7 +632,7 @@
CLK_DUMMY("pcie_alt_ref_clk", PCIE_ALT_REF_CLK, NULL, OFF),
CLK_DUMMY("sata_rxoob_clk", SATA_RXOOB_CLK, NULL, OFF),
CLK_DUMMY("sata_pmalive_clk", SATA_PMALIVE_CLK, NULL, OFF),
- CLK_DUMMY("sata_phy_ref_clk", SATA_PHY_REF_CLK, NULL, OFF),
+ CLK_DUMMY("ref_clk", SATA_PHY_REF_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", GSBI1_P_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", GSBI2_P_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", GSBI3_P_CLK, "msm_serial_hsl.0", OFF),
@@ -651,11 +651,11 @@
CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF),
CLK_DUMMY("core_clk", ADM0_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", ADM0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
- CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
- CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
+ CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
@@ -676,13 +676,13 @@
CLK_DUMMY("core_clk", GFX3D_CLK, NULL, OFF),
CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
- CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index f92c54a..7512414 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -1585,7 +1585,7 @@
CLK_DUMMY("core_clk", GSBI10_QUP_CLK, NULL, OFF),
CLK_DUMMY("core_clk", GSBI11_QUP_CLK, NULL, OFF),
CLK_DUMMY("core_clk", GSBI12_QUP_CLK, NULL, OFF),
- CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
@@ -1594,7 +1594,7 @@
CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
CLK_DUMMY("core_clk", SDC5_CLK, NULL, OFF),
CLK_DUMMY("core_clk", TSIF_REF_CLK, NULL, OFF),
- CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
@@ -1630,11 +1630,11 @@
CLK_DUMMY("iface_clk", SDC5_P_CLK, NULL, OFF),
CLK_DUMMY("core_clk", ADM0_CLK, NULL, OFF),
CLK_DUMMY("iface_clk", ADM0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
- CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
- CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
- CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
+ CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
+ CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
@@ -1655,7 +1655,7 @@
CLK_DUMMY("core_clk", GFX3D_CLK, NULL, OFF),
CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
- CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
@@ -1663,7 +1663,7 @@
CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
- CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
+ CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-msm7x25.c b/arch/arm/mach-msm/devices-msm7x25.c
index c166c8d..d918315 100644
--- a/arch/arm/mach-msm/devices-msm7x25.c
+++ b/arch/arm/mach-msm/devices-msm7x25.c
@@ -942,7 +942,7 @@
CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
- CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp_clk.c, NULL),
CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
diff --git a/arch/arm/mach-msm/footswitch-8x60.c b/arch/arm/mach-msm/footswitch-8x60.c
index 6ece538..98447fa 100644
--- a/arch/arm/mach-msm/footswitch-8x60.c
+++ b/arch/arm/mach-msm/footswitch-8x60.c
@@ -42,6 +42,7 @@
#define VED_GFS_CTL_REG REG(0x0194)
#define VFE_GFS_CTL_REG REG(0x0198)
#define VPE_GFS_CTL_REG REG(0x019C)
+#define VCAP_GFS_CTL_REG REG(0x0254)
#define CLAMP_BIT BIT(5)
#define ENABLE_BIT BIT(8)
@@ -469,6 +470,9 @@
FOOTSWITCH(FS_VPE, "fs_vpe", &standard_fs_ops,
VPE_GFS_CTL_REG, 31, true, 0,
MSM_BUS_MASTER_VPE, 0),
+ FOOTSWITCH(FS_VCAP, "fs_vcap", &standard_fs_ops,
+ VCAP_GFS_CTL_REG, 31, true, 0,
+ MSM_BUS_MASTER_VIDEO_CAP, 0),
};
static int footswitch_probe(struct platform_device *pdev)
diff --git a/arch/arm/mach-msm/footswitch.h b/arch/arm/mach-msm/footswitch.h
index 06b7c79..4882ff0 100644
--- a/arch/arm/mach-msm/footswitch.h
+++ b/arch/arm/mach-msm/footswitch.h
@@ -27,7 +27,8 @@
#define FS_VED 7
#define FS_VFE 8
#define FS_VPE 9
-#define MAX_FS 10
+#define FS_VCAP 10
+#define MAX_FS 11
#define FS_GENERIC(_drv_name, _id, _name) (&(struct platform_device){ \
.name = (_drv_name), \
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index c8867bd..dbde068 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -210,7 +210,11 @@
static inline int cpu_is_msm8930(void)
{
+#ifdef CONFIG_ARCH_MSM8930
return read_msm_cpu_type() == MSM_CPU_8930;
+#else
+ return 0;
+#endif
}
static inline int cpu_is_fsm9xxx(void)
diff --git a/arch/arm/mach-msm/msm_xo.c b/arch/arm/mach-msm/msm_xo.c
index a82d4d5..1e9c05f 100644
--- a/arch/arm/mach-msm/msm_xo.c
+++ b/arch/arm/mach-msm/msm_xo.c
@@ -190,11 +190,11 @@
{
int ret;
unsigned long flags;
- /* TODO: Remove or fix this function for 8064 once xo is in */
- if (cpu_is_apq8064())
+
+ if (!xo_voter)
return 0;
- if (mode >= NUM_MSM_XO_MODES)
+ if (mode >= NUM_MSM_XO_MODES || IS_ERR(xo_voter))
return -EINVAL;
spin_lock_irqsave(&msm_xo_lock, flags);
@@ -221,7 +221,10 @@
unsigned long flags;
struct msm_xo_voter *xo_voter;
- /* TODO: Remove or fix this function for 8064 once xo is in */
+ /*
+ * TODO: Remove early return for 8064 once RPM XO voting support
+ * is available.
+ */
if (cpu_is_apq8064())
return NULL;
@@ -271,6 +274,9 @@
{
unsigned long flags;
+ if (!xo_voter || IS_ERR(xo_voter))
+ return;
+
spin_lock_irqsave(&msm_xo_lock, flags);
__msm_xo_mode_vote(xo_voter, MSM_XO_MODE_OFF);
xo_voter->xo->votes[MSM_XO_MODE_OFF]--;
diff --git a/arch/arm/mach-msm/sdio_al.c b/arch/arm/mach-msm/sdio_al.c
index ace437b..8fff2461 100644
--- a/arch/arm/mach-msm/sdio_al.c
+++ b/arch/arm/mach-msm/sdio_al.c
@@ -15,7 +15,7 @@
*
* To be used with Qualcomm's SDIO-Client connected to this host.
*/
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/module.h>
#include <linux/scatterlist.h>
diff --git a/arch/arm/mach-msm/sdio_al_dloader.c b/arch/arm/mach-msm/sdio_al_dloader.c
index a172d2b..77a06a3 100644
--- a/arch/arm/mach-msm/sdio_al_dloader.c
+++ b/arch/arm/mach-msm/sdio_al_dloader.c
@@ -25,7 +25,7 @@
#include <linux/dma-mapping.h>
#include <mach/dma.h>
#include <linux/mmc/sdio_func.h>
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/kthread.h>
diff --git a/arch/arm/mach-msm/sdio_al_test.c b/arch/arm/mach-msm/sdio_al_test.c
index bc48821..8b9abcf 100644
--- a/arch/arm/mach-msm/sdio_al_test.c
+++ b/arch/arm/mach-msm/sdio_al_test.c
@@ -30,7 +30,7 @@
#include <linux/wakelock.h>
#include <linux/uaccess.h>
-#include <sdio_al_private.h>
+#include "sdio_al_private.h"
#include <linux/debugfs.h>
#include <linux/kthread.h>
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index d83bcb0..532a2f7 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -2548,6 +2548,8 @@
smd_initialized = 1;
smd_alloc_loopback_channel();
+ smsm_irq_handler(0, 0);
+ tasklet_schedule(&smd_fake_irq_tasklet);
return 0;
}
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 45653a2..9df1a68 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -210,9 +210,12 @@
[104] = MSM_CPU_9615,
[105] = MSM_CPU_9615,
- /* 8064 IDs*/
+ /* 8064 IDs */
[109] = MSM_CPU_8064,
+ /* 8930 IDs */
+ [116] = MSM_CPU_8930,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
considered as unknown CPU. */
@@ -700,9 +703,12 @@
const int read_msm_cpu_type(void)
{
- if (machine_is_msm8960_sim())
+ if (machine_is_msm8960_sim() || machine_is_msm8960_rumi3())
return MSM_CPU_8960;
+ if (socinfo_get_msm_cpu() != MSM_CPU_UNKNOWN)
+ return socinfo_get_msm_cpu();
+
switch (read_cpuid_id()) {
case 0x510F02D0:
case 0x510F02D2:
@@ -712,13 +718,12 @@
case 0x510F04D0:
case 0x510F04D1:
case 0x510F04D2:
+ case 0x511F04D0:
+ case 0x512F04D0:
return MSM_CPU_8960;
- case 0x511F04D0:
- if (get_core_count() == 2)
- return MSM_CPU_8960;
- else
- return MSM_CPU_8930;
+ case 0x51404D11: /* We can't get here unless we are in bringup */
+ return MSM_CPU_8930;
case 0x510F06F0:
return MSM_CPU_8064;
diff --git a/drivers/gpu/ion/ion.c b/drivers/gpu/ion/ion.c
index c37d952..930ba83 100644
--- a/drivers/gpu/ion/ion.c
+++ b/drivers/gpu/ion/ion.c
@@ -688,29 +688,25 @@
{
struct ion_client *client = s->private;
struct rb_node *n;
- size_t sizes[ION_NUM_HEAPS] = {0};
- const char *names[ION_NUM_HEAPS] = {0};
- int i;
+ seq_printf(s, "%16.16s: %16.16s : %16.16s : %16.16s\n", "heap_name",
+ "size_in_bytes", "handle refcount", "buffer");
mutex_lock(&client->lock);
for (n = rb_first(&client->handles); n; n = rb_next(n)) {
struct ion_handle *handle = rb_entry(n, struct ion_handle,
node);
- enum ion_heap_type type = handle->buffer->heap->type;
- if (!names[type])
- names[type] = handle->buffer->heap->name;
- sizes[type] += handle->buffer->size;
+ seq_printf(s, "%16.16s: %16u : %16d : %16p\n",
+ handle->buffer->heap->name,
+ handle->buffer->size,
+ atomic_read(&handle->ref.refcount),
+ handle->buffer);
}
+
+ seq_printf(s, "%16.16s %d\n", "client refcount:",
+ atomic_read(&client->ref.refcount));
mutex_unlock(&client->lock);
- seq_printf(s, "%16.16s: %16.16s\n", "heap_name", "size_in_bytes");
- for (i = 0; i < ION_NUM_HEAPS; i++) {
- if (!names[i])
- continue;
- seq_printf(s, "%16.16s: %16u %d\n", names[i], sizes[i],
- atomic_read(&client->ref.refcount));
- }
return 0;
}
@@ -1247,6 +1243,14 @@
seq_printf(s, "%16.s %16u %16u\n", client->name, client->pid,
size);
}
+ if (heap->ops->get_allocated) {
+ seq_printf(s, "total bytes currently allocated: %lx\n",
+ heap->ops->get_allocated(heap));
+ }
+ if (heap->ops->get_total) {
+ seq_printf(s, "total heap size: %lx\n",
+ heap->ops->get_total(heap));
+ }
return 0;
}
diff --git a/drivers/gpu/ion/ion_carveout_heap.c b/drivers/gpu/ion/ion_carveout_heap.c
index 86d4c8e..a572ca8 100644
--- a/drivers/gpu/ion/ion_carveout_heap.c
+++ b/drivers/gpu/ion/ion_carveout_heap.c
@@ -31,6 +31,8 @@
struct ion_heap heap;
struct gen_pool *pool;
ion_phys_addr_t base;
+ unsigned long allocated_bytes;
+ unsigned long total_size;
};
ion_phys_addr_t ion_carveout_allocate(struct ion_heap *heap,
@@ -45,6 +47,7 @@
if (!offset)
return ION_CARVEOUT_ALLOCATE_FAIL;
+ carveout_heap->allocated_bytes += size;
return offset;
}
@@ -57,6 +60,7 @@
if (addr == ION_CARVEOUT_ALLOCATE_FAIL)
return;
gen_pool_free(carveout_heap->pool, addr, size);
+ carveout_heap->allocated_bytes -= size;
}
static int ion_carveout_heap_phys(struct ion_heap *heap,
@@ -156,6 +160,22 @@
return 0;
}
+static unsigned long ion_carveout_get_allocated(struct ion_heap *heap)
+{
+ struct ion_carveout_heap *carveout_heap =
+ container_of(heap, struct ion_carveout_heap, heap);
+
+ return carveout_heap->allocated_bytes;
+}
+
+static unsigned long ion_carveout_get_total(struct ion_heap *heap)
+{
+ struct ion_carveout_heap *carveout_heap =
+ container_of(heap, struct ion_carveout_heap, heap);
+
+ return carveout_heap->total_size;
+}
+
static struct ion_heap_ops carveout_heap_ops = {
.allocate = ion_carveout_heap_allocate,
.free = ion_carveout_heap_free,
@@ -164,6 +184,8 @@
.map_kernel = ion_carveout_heap_map_kernel,
.unmap_kernel = ion_carveout_heap_unmap_kernel,
.cache_op = ion_carveout_cache_ops,
+ .get_allocated = ion_carveout_get_allocated,
+ .get_total = ion_carveout_get_total,
};
struct ion_heap *ion_carveout_heap_create(struct ion_platform_heap *heap_data)
@@ -189,6 +211,8 @@
}
carveout_heap->heap.ops = &carveout_heap_ops;
carveout_heap->heap.type = ION_HEAP_TYPE_CARVEOUT;
+ carveout_heap->allocated_bytes = 0;
+ carveout_heap->total_size = heap_data->size;
return &carveout_heap->heap;
}
diff --git a/drivers/gpu/ion/ion_priv.h b/drivers/gpu/ion/ion_priv.h
index fd5c125..10e2219 100644
--- a/drivers/gpu/ion/ion_priv.h
+++ b/drivers/gpu/ion/ion_priv.h
@@ -104,6 +104,8 @@
int (*cache_op)(struct ion_heap *heap, struct ion_buffer *buffer,
void *vaddr, unsigned int offset,
unsigned int length, unsigned int cmd);
+ unsigned long (*get_allocated)(struct ion_heap *heap);
+ unsigned long (*get_total)(struct ion_heap *heap);
};
/**
diff --git a/drivers/gpu/ion/ion_system_heap.c b/drivers/gpu/ion/ion_system_heap.c
index 5609b72..b26d48c 100644
--- a/drivers/gpu/ion/ion_system_heap.c
+++ b/drivers/gpu/ion/ion_system_heap.c
@@ -23,6 +23,9 @@
#include "ion_priv.h"
#include <mach/memory.h>
+static atomic_t system_heap_allocated;
+static atomic_t system_contig_heap_allocated;
+
static int ion_system_heap_allocate(struct ion_heap *heap,
struct ion_buffer *buffer,
unsigned long size, unsigned long align,
@@ -31,12 +34,15 @@
buffer->priv_virt = vmalloc_user(size);
if (!buffer->priv_virt)
return -ENOMEM;
+
+ atomic_add(size, &system_heap_allocated);
return 0;
}
void ion_system_heap_free(struct ion_buffer *buffer)
{
vfree(buffer->priv_virt);
+ atomic_sub(buffer->size, &system_heap_allocated);
}
struct scatterlist *ion_system_heap_map_dma(struct ion_heap *heap,
@@ -149,6 +155,11 @@
return 0;
}
+static unsigned long ion_system_heap_get_allocated(struct ion_heap *heap)
+{
+ return atomic_read(&system_heap_allocated);
+}
+
static struct ion_heap_ops vmalloc_ops = {
.allocate = ion_system_heap_allocate,
.free = ion_system_heap_free,
@@ -158,6 +169,7 @@
.unmap_kernel = ion_system_heap_unmap_kernel,
.map_user = ion_system_heap_map_user,
.cache_op = ion_system_heap_cache_ops,
+ .get_allocated = ion_system_heap_get_allocated,
};
struct ion_heap *ion_system_heap_create(struct ion_platform_heap *unused)
@@ -186,12 +198,14 @@
buffer->priv_virt = kzalloc(len, GFP_KERNEL);
if (!buffer->priv_virt)
return -ENOMEM;
+ atomic_add(len, &system_contig_heap_allocated);
return 0;
}
void ion_system_contig_heap_free(struct ion_buffer *buffer)
{
kfree(buffer->priv_virt);
+ atomic_sub(buffer->size, &system_contig_heap_allocated);
}
static int ion_system_contig_heap_phys(struct ion_heap *heap,
@@ -266,6 +280,11 @@
return 0;
}
+static unsigned long ion_system_contig_heap_get_allocated(struct ion_heap *heap)
+{
+ return atomic_read(&system_contig_heap_allocated);
+}
+
static struct ion_heap_ops kmalloc_ops = {
.allocate = ion_system_contig_heap_allocate,
.free = ion_system_contig_heap_free,
@@ -276,6 +295,7 @@
.unmap_kernel = ion_system_heap_unmap_kernel,
.map_user = ion_system_contig_heap_map_user,
.cache_op = ion_system_contig_heap_cache_ops,
+ .get_allocated = ion_system_contig_heap_get_allocated,
};
struct ion_heap *ion_system_contig_heap_create(struct ion_platform_heap *unused)
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 639f219..d59057c 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -61,7 +61,7 @@
adreno_regwrite(rb->device, REG_CP_RB_WPTR, rb->wptr);
}
-static int
+static void
adreno_ringbuffer_waitspace(struct adreno_ringbuffer *rb, unsigned int numcmds,
int wptr_ahead)
{
@@ -102,8 +102,6 @@
freecmds = rb->rptr - rb->wptr;
} while ((freecmds != 0) && (freecmds <= numcmds));
-
- return 0;
}
@@ -111,7 +109,6 @@
unsigned int numcmds)
{
unsigned int *ptr = NULL;
- int status = 0;
BUG_ON(numcmds >= rb->sizedwords);
@@ -122,22 +119,20 @@
/* reserve dwords for nop packet */
if ((rb->wptr + numcmds) > (rb->sizedwords -
GSL_RB_NOP_SIZEDWORDS))
- status = adreno_ringbuffer_waitspace(rb, numcmds, 1);
+ adreno_ringbuffer_waitspace(rb, numcmds, 1);
} else {
/* wptr behind rptr */
if ((rb->wptr + numcmds) >= rb->rptr)
- status = adreno_ringbuffer_waitspace(rb, numcmds, 0);
+ adreno_ringbuffer_waitspace(rb, numcmds, 0);
/* check for remaining space */
/* reserve dwords for nop packet */
if ((rb->wptr + numcmds) > (rb->sizedwords -
GSL_RB_NOP_SIZEDWORDS))
- status = adreno_ringbuffer_waitspace(rb, numcmds, 1);
+ adreno_ringbuffer_waitspace(rb, numcmds, 1);
}
- if (status == 0) {
- ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
- rb->wptr += numcmds;
- }
+ ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+ rb->wptr += numcmds;
return ptr;
}
@@ -391,7 +386,7 @@
return status;
}
-int adreno_ringbuffer_stop(struct adreno_ringbuffer *rb)
+void adreno_ringbuffer_stop(struct adreno_ringbuffer *rb)
{
if (rb->flags & KGSL_FLAGS_STARTED) {
/* ME_HALT */
@@ -399,8 +394,6 @@
rb->flags &= ~KGSL_FLAGS_STARTED;
}
-
- return 0;
}
int adreno_ringbuffer_init(struct kgsl_device *device)
@@ -443,7 +436,7 @@
return 0;
}
-int adreno_ringbuffer_close(struct adreno_ringbuffer *rb)
+void adreno_ringbuffer_close(struct adreno_ringbuffer *rb)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);
@@ -457,8 +450,6 @@
adreno_dev->pm4_fw = NULL;
memset(rb, 0, sizeof(struct adreno_ringbuffer));
-
- return 0;
}
static uint32_t
diff --git a/drivers/gpu/msm/adreno_ringbuffer.h b/drivers/gpu/msm/adreno_ringbuffer.h
index 487a748..a90b0cb 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.h
+++ b/drivers/gpu/msm/adreno_ringbuffer.h
@@ -117,9 +117,9 @@
int adreno_ringbuffer_start(struct adreno_ringbuffer *rb,
unsigned int init_ram);
-int adreno_ringbuffer_stop(struct adreno_ringbuffer *rb);
+void adreno_ringbuffer_stop(struct adreno_ringbuffer *rb);
-int adreno_ringbuffer_close(struct adreno_ringbuffer *rb);
+void adreno_ringbuffer_close(struct adreno_ringbuffer *rb);
void adreno_ringbuffer_issuecmds(struct kgsl_device *device,
unsigned int flags,
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index f43b96e..30365a3 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -226,8 +226,6 @@
{
int ret;
unsigned int range = memdesc->size;
- unsigned int iommu_map_addr;
- int map_order = get_order(SZ_4K);
struct iommu_domain *domain = (struct iommu_domain *)
mmu_specific_pt;
@@ -240,14 +238,11 @@
if (range == 0 || gpuaddr == 0)
return 0;
- for (iommu_map_addr = gpuaddr; iommu_map_addr < (gpuaddr + range);
- iommu_map_addr += SZ_4K) {
- ret = iommu_unmap(domain, iommu_map_addr, map_order);
- if (ret)
- KGSL_CORE_ERR("iommu_unmap(%p, %x, %d) failed "
- "with err: %d\n", domain, iommu_map_addr,
- map_order, ret);
- }
+ ret = iommu_unmap_range(domain, gpuaddr, range);
+ if (ret)
+ KGSL_CORE_ERR("iommu_unmap_range(%p, %x, %d) failed "
+ "with err: %d\n", domain, gpuaddr,
+ range, ret);
return 0;
}
@@ -257,34 +252,23 @@
struct kgsl_memdesc *memdesc,
unsigned int protflags)
{
- int ret, i;
- struct scatterlist *s;
+ int ret;
unsigned int iommu_virt_addr;
- int map_order;
struct iommu_domain *domain = mmu_specific_pt;
BUG_ON(NULL == domain);
- map_order = get_order(SZ_4K);
iommu_virt_addr = memdesc->gpuaddr;
- for_each_sg(memdesc->sg, s, memdesc->sglen, i) {
- unsigned int paddr = sg_phys(s), j;
- for (j = paddr; j < paddr + s->length; j += PAGE_SIZE) {
- ret = iommu_map(domain, iommu_virt_addr, j,
- map_order, MSM_IOMMU_ATTR_NONCACHED);
- if (ret) {
- KGSL_CORE_ERR("iommu_map(%p, %x, %x, %d, %d) "
- "failed with err: %d\n", domain,
- iommu_virt_addr, j, map_order,
- MSM_IOMMU_ATTR_NONCACHED, ret);
- kgsl_iommu_unmap(mmu_specific_pt, memdesc);
- return ret;
- }
-
- iommu_virt_addr += SZ_4K;
- }
+ ret = iommu_map_range(domain, iommu_virt_addr, memdesc->sg,
+ memdesc->size, MSM_IOMMU_ATTR_NONCACHED);
+ if (ret) {
+ KGSL_CORE_ERR("iommu_map_range(%p, %x, %p, %d, %d) "
+ "failed with err: %d\n", domain,
+ iommu_virt_addr, memdesc->sg, memdesc->size,
+ MSM_IOMMU_ATTR_NONCACHED, ret);
+ return ret;
}
return ret;
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 84f2b33..aee42a1 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -582,11 +582,11 @@
idle_check_ws);
mutex_lock(&device->mutex);
- if (device->ftbl->isidle(device) &&
- (device->requested_state != KGSL_STATE_SLEEP))
- kgsl_pwrscale_idle(device);
-
if (device->state & (KGSL_STATE_ACTIVE | KGSL_STATE_NAP)) {
+ if (device->ftbl->isidle(device) &&
+ (device->requested_state != KGSL_STATE_SLEEP))
+ kgsl_pwrscale_idle(device);
+
if (kgsl_pwrctrl_sleep(device) != 0) {
mod_timer(&device->idle_timer,
jiffies +
diff --git a/drivers/gpu/msm/kgsl_pwrscale.c b/drivers/gpu/msm/kgsl_pwrscale.c
index fa7203d..b5c6876 100644
--- a/drivers/gpu/msm/kgsl_pwrscale.c
+++ b/drivers/gpu/msm/kgsl_pwrscale.c
@@ -272,8 +272,11 @@
static void _kgsl_pwrscale_detach_policy(struct kgsl_device *device)
{
- if (device->pwrscale.policy != NULL)
+ if (device->pwrscale.policy != NULL) {
device->pwrscale.policy->close(device, &device->pwrscale);
+ kgsl_pwrctrl_pwrlevel_change(device,
+ device->pwrctrl.thermal_pwrlevel);
+ }
device->pwrscale.policy = NULL;
}
diff --git a/drivers/hwmon/pm8921-adc.c b/drivers/hwmon/pm8921-adc.c
index 5ab6296..33f4a3a 100644
--- a/drivers/hwmon/pm8921-adc.c
+++ b/drivers/hwmon/pm8921-adc.c
@@ -31,6 +31,7 @@
#include <linux/mfd/pm8xxx/pm8921-adc.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
+#include <linux/wakelock.h>
/* User Bank register set */
#define PM8921_ADC_ARB_USRP_CNTRL1 0x197
@@ -142,6 +143,8 @@
uint32_t mpp_base;
struct sensor_device_attribute *sens_attr;
struct device *hwmon;
+ struct wake_lock adc_wakelock;
+ int msm_suspend_check;
};
struct pm8921_adc_amux_properties {
@@ -188,14 +191,18 @@
static bool pm8921_adc_calib_first_adc;
static bool pm8921_adc_initialized, pm8921_adc_calib_device_init;
-static int32_t pm8921_adc_arb_cntrl(uint32_t arb_cntrl)
+static int32_t pm8921_adc_arb_cntrl(uint32_t arb_cntrl, uint32_t channel)
{
struct pm8921_adc *adc_pmic = pmic_adc;
int i, rc;
u8 data_arb_cntrl = 0;
- if (arb_cntrl)
+ if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("PM8921 ADC request being made after suspend "
+ "irq with channel id:%d\n", channel);
data_arb_cntrl |= PM8921_ADC_ARB_USRP_CNTRL1_EN_ARB;
+ }
/* Write twice to the CNTRL register for the arbiter settings
to take into effect */
@@ -212,6 +219,13 @@
data_arb_cntrl |= PM8921_ADC_ARB_USRP_CNTRL1_REQ;
rc = pm8xxx_writeb(adc_pmic->dev->parent,
PM8921_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ if (rc < 0) {
+ pr_err("PM8921 arb cntrl write failed with %d\n", rc);
+ return rc;
+ }
+ wake_lock(&adc_pmic->adc_wakelock);
+ } else {
+ wake_unlock(&adc_pmic->adc_wakelock);
}
return 0;
@@ -369,7 +383,7 @@
if (!pm8921_adc_calib_first_adc)
enable_irq(adc_pmic->adc_irq);
- rc = pm8921_adc_arb_cntrl(1);
+ rc = pm8921_adc_arb_cntrl(1, chan_prop->amux_mpp_channel);
if (rc < 0) {
pr_err("Configuring ADC Arbiter"
"enable failed with %d\n", rc);
@@ -409,7 +423,7 @@
/* Default value for switching off the arbiter after reading
the ADC value. Bit 0 set to 0. */
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -558,7 +572,7 @@
(calib_read_1 - calib_read_2);
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dx
= PM8921_CHANNEL_ADC_625_MV;
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -638,7 +652,7 @@
adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dx =
adc_pmic->adc_prop->adc_vdd_reference;
calib_fail:
- rc = pm8921_adc_arb_cntrl(0);
+ rc = pm8921_adc_arb_cntrl(0, CHANNEL_MUXOFF);
if (rc < 0) {
pr_err("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -1122,11 +1136,43 @@
return rc;
}
+#ifdef CONFIG_PM
+static int pm8921_adc_suspend_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pm8921_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8921_adc_resume_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pm8921_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8921_adc_dev_pm_ops = {
+ .suspend_noirq = pm8921_adc_suspend_noirq,
+ .resume_noirq = pm8921_adc_resume_noirq,
+};
+
+#define PM8921_ADC_DEV_PM_OPS (&pm8921_adc_dev_pm_ops)
+#else
+#define PM8921_ADC_DEV_PM_OPS NULL
+#endif
+
static int __devexit pm8921_adc_teardown(struct platform_device *pdev)
{
struct pm8921_adc *adc_pmic = pmic_adc;
int i;
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
free_irq(adc_pmic->adc_irq, adc_pmic);
free_irq(adc_pmic->btm_warm_irq, adc_pmic);
free_irq(adc_pmic->btm_cool_irq, adc_pmic);
@@ -1262,6 +1308,8 @@
INIT_WORK(&adc_pmic->warm_work, pm8921_adc_btm_warm_scheduler_fn);
INIT_WORK(&adc_pmic->cool_work, pm8921_adc_btm_cool_scheduler_fn);
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pm8921_adc_wakelock");
create_debugfs_entries();
pm8921_adc_calib_first_adc = false;
pm8921_adc_calib_device_init = false;
@@ -1286,6 +1334,7 @@
.driver = {
.name = PM8921_ADC_DEV_NAME,
.owner = THIS_MODULE,
+ .pm = PM8921_ADC_DEV_PM_OPS,
},
};
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 00c7633..7a3df4d1 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -601,9 +601,18 @@
{
int total_len = 0;
int ret = 0;
- if (dev->msg->len >= (dev->out_fifo_sz - 1)) {
- total_len = dev->msg->len + 1 +
- (dev->msg->len/(dev->out_blk_sz-1));
+ int len = dev->msg->len;
+ struct i2c_msg *next = NULL;
+ if (rem > 1)
+ next = dev->msg + 1;
+ while (rem > 1 && next->flags == 0) {
+ len += next->len + 1;
+ next = next + 1;
+ rem--;
+ }
+ if (len >= (dev->out_fifo_sz - 1)) {
+ total_len = len + 1 + (len/(dev->out_blk_sz-1));
+
writel_relaxed(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN,
dev->base + QUP_IO_MODE);
dev->wr_sz = dev->out_blk_sz;
@@ -612,7 +621,6 @@
dev->base + QUP_IO_MODE);
if (rem > 1) {
- struct i2c_msg *next = dev->msg + 1;
if (next->addr == dev->msg->addr &&
next->flags == I2C_M_RD) {
qup_set_read_mode(dev, next->len);
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 74534af..5d9112e 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -2356,24 +2356,39 @@
void *act_client = NULL;
struct msm_actuator_ctrl *a_ext_ctrl = NULL;
- if (!actuator_info) {
- actctrl->a_init_table = NULL;
- actctrl->a_power_down = NULL;
- actctrl->a_config = NULL;
- actctrl->a_create_subdevice = NULL;
- return rc;
- }
+ D("%s called\n", __func__);
+
+ if (!actuator_info)
+ goto probe_fail;
adapter = i2c_get_adapter(actuator_info->bus_id);
+ if (!adapter)
+ goto probe_fail;
act_client = i2c_new_device(adapter, actuator_info->board_info);
+ if (!act_client)
+ goto device_fail;
a_ext_ctrl = (struct msm_actuator_ctrl *)i2c_get_clientdata(act_client);
+ if (!a_ext_ctrl)
+ goto client_fail;
*actctrl = *a_ext_ctrl;
a_ext_ctrl->a_create_subdevice((void *)actuator_info->board_info,
(void *)act_sdev);
return rc;
+
+client_fail:
+ i2c_unregister_device(act_client);
+device_fail:
+ i2c_put_adapter(adapter);
+ adapter = NULL;
+probe_fail:
+ actctrl->a_init_table = NULL;
+ actctrl->a_power_down = NULL;
+ actctrl->a_config = NULL;
+ actctrl->a_create_subdevice = NULL;
+ return rc;
}
static int msm_sync_init(struct msm_sync *sync,
@@ -2544,6 +2559,7 @@
implemenation of mutex_init is not consuming resources */
msm_sync_destroy(&pcam->mctl.sync);
pcam->pdev = NULL;
+ kfree(act_sdev);
kfree(sdev);
kzfree(pcam);
return rc;
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 219e504..51b7a90 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -678,7 +678,7 @@
msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
- msm_io_dump(vfe32_ctrl->vfebase, 0x7B4);
+ msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total * 4);
/* Ensure the write order while writing
to the command register using the barrier */
@@ -986,7 +986,6 @@
int i;
uint32_t value, value1, value2;
vfe32_program_dmi_cfg(channel_sel);
- /* for loop for extracting init table. */
for (i = 0 ; i < (VFE32_GAMMA_NUM_ENTRIES/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
@@ -997,6 +996,20 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
+static void vfe32_read_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
+ uint32_t *tbl)
+{
+ int i;
+ vfe32_program_dmi_cfg(channel_sel);
+ CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
+ for (i = 0 ; i < VFE32_GAMMA_NUM_ENTRIES ; i++) {
+ *tbl = msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *tbl);
+ tbl++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+}
+
static void vfe32_write_la_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
{
@@ -1004,7 +1017,6 @@
uint32_t value, value1, value2;
vfe32_program_dmi_cfg(channel_sel);
- /* for loop for extracting init table. */
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH/2) ; i++) {
value = *tbl++;
value1 = value & 0x0000FFFF;
@@ -1196,23 +1208,6 @@
}
rc = vfe32_capture(snapshot_cnt);
break;
- case VFE_CMD_GET_HW_VERSION:
- if (cmd->length != V32_GET_HW_VERSION_LEN) {
- rc = -EINVAL;
- goto proc_general_done;
- }
- cmdp = kmalloc(V32_GET_HW_VERSION_LEN, GFP_ATOMIC);
- if (!cmdp) {
- rc = -ENOMEM;
- goto proc_general_done;
- }
- *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
- if (copy_to_user((void __user *)(cmd->value), cmdp,
- V32_GET_HW_VERSION_LEN)) {
- rc = -EFAULT;
- goto proc_general_done;
- }
- break;
case VFE_CMD_START_RECORDING:
pr_info("vfe32_proc_general: cmdID = %s\n",
vfe32_general_cmd[cmd->id]);
@@ -1342,12 +1337,6 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= RS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- */
msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
@@ -1365,12 +1354,6 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= CS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- */
msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
@@ -1453,6 +1436,44 @@
}
break;
+ case VFE_CMD_GET_MESH_ROLLOFF_TABLE:
+ temp1 = sizeof(uint32_t) * ((V32_MESH_ROLL_OFF_INIT_TABLE_SIZE *
+ 2) + (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2));
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+ CDBG("%s: Mesh Rolloff init Table\n", __func__);
+ for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
+ for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ CDBG("done reading delta table\n");
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_LA_CFG:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
@@ -1500,6 +1521,36 @@
vfe32_ctrl->update_la = true;
break;
+ case VFE_CMD_GET_LA_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_LA_TABLE_LENGTH / 2;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
+ else
+ vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
+ for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH / 2) ; i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_io_r(vfe32_ctrl->vfebase +
+ VFE_DMI_DATA_LO)) << 16;
+ cmdp_local++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_SK_ENHAN_CFG:
case VFE_CMD_SK_ENHAN_UPDATE:{
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
@@ -1542,7 +1593,7 @@
cmdp_local = cmdp + 17;
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
- break;
+ break;
case VFE_CMD_LINEARIZATION_UPDATE:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
@@ -1572,8 +1623,38 @@
else
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK1, cmdp_local);
vfe32_ctrl->update_linear = true;
- break;
+ break;
+ case VFE_CMD_GET_LINEARIZATON_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_LINEARIZATON_TABLE_LENGTH;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1);
+ else
+ vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0);
+ CDBG("%s: Linearization Table\n", __func__);
+ for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
+ *cmdp_local =
+ msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ CDBG("%s: %08x\n", __func__, *cmdp_local);
+ cmdp_local++;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
case VFE_CMD_DEMOSAICV3:
if (cmd->length !=
V32_DEMOSAICV3_0_LEN+V32_DEMOSAICV3_1_LEN) {
@@ -1755,6 +1836,34 @@
cmdp -= 1;
break;
+ case VFE_CMD_GET_RGB_G_TABLE:
+ temp1 = sizeof(uint32_t) * VFE32_GAMMA_NUM_ENTRIES * 3;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+
+ old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
+ RGBLUT_RAM_CH0_BANK0;
+ for (i = 0; i < 3; i++) {
+ vfe32_read_gamma_cfg(temp2,
+ cmdp_local + (VFE32_GAMMA_NUM_ENTRIES * i));
+ temp2 += 2;
+ }
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+
case VFE_CMD_STATS_AWB_STOP: {
old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
@@ -1947,9 +2056,9 @@
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
- else
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
@@ -1963,9 +2072,9 @@
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
if (temp2)
- vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- else
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
@@ -1978,7 +2087,88 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
vfe32_ctrl->update_rolloff = true;
break;
+ case VFE_CMD_GET_PCA_ROLLOFF_TABLE:
+ temp1 = sizeof(uint64_t) * V33_PCA_ROLL_OFF_TABLE_SIZE * 2;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kzalloc(temp1, GFP_KERNEL);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ cmdp_local = cmdp;
+ old_val = msm_io_r(vfe32_ctrl->vfebase +
+ V33_PCA_ROLL_OFF_CFG_OFF1) &
+ V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
+ if (old_val)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
+ else
+ vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
+
+ CDBG("%s: PCA Rolloff Ram0\n", __func__);
+ for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE * 2; i++) {
+ temp2 = (i == (V33_PCA_ROLL_OFF_TABLE_SIZE - 1));
+ if (old_val && temp2)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
+ else if (!old_val && temp2)
+ vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
+
+ *(cmdp_local + 1) =
+ msm_io_r(vfe32_ctrl->vfebase +
+ VFE33_DMI_DATA_HI);
+ *cmdp_local = msm_io_r(vfe32_ctrl->vfebase +
+ VFE33_DMI_DATA_LO);
+ CDBG("%s: %08x%08x\n", __func__,
+ *(cmdp_local + 1), *cmdp_local);
+ cmdp_local += 2;
+ }
+ vfe32_program_dmi_cfg(NO_MEM_SELECTED);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+ case VFE_CMD_GET_HW_VERSION:
+ if (cmd->length != V32_GET_HW_VERSION_LEN) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(V32_GET_HW_VERSION_LEN, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
+ if (copy_to_user((void __user *)(cmd->value), cmdp,
+ V32_GET_HW_VERSION_LEN)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
+ case VFE_CMD_GET_REG_DUMP:
+ temp1 = sizeof(uint32_t) * vfe32_ctrl->register_total;
+ if (cmd->length != temp1) {
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ cmdp = kmalloc(temp1, GFP_ATOMIC);
+ if (!cmdp) {
+ rc = -ENOMEM;
+ goto proc_general_done;
+ }
+ msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
+ CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
+ vfe32_ctrl->vfebase, temp1);
+ memcpy_fromio((void *)cmdp, vfe32_ctrl->vfebase, temp1);
+ if (copy_to_user((void __user *)(cmd->value), cmdp, temp1)) {
+ rc = -EFAULT;
+ goto proc_general_done;
+ }
+ break;
default:
if (cmd->length != vfe32_cmd[cmd->id].length)
return -EINVAL;
@@ -3371,6 +3561,12 @@
msm_camio_set_perf_lvl(S_INIT);
msm_camio_set_perf_lvl(S_PREVIEW);
+ if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ VFE32_HW_NUMBER)
+ vfe32_ctrl->register_total = VFE32_REGISTER_TOTAL;
+ else
+ vfe32_ctrl->register_total = VFE33_REGISTER_TOTAL;
+
/* TO DO: Need to release the VFE resources */
rc = request_irq(vfe32_ctrl->vfeirq, vfe32_parse_irq,
IRQF_TRIGGER_RISING, "vfe", 0);
diff --git a/drivers/media/video/msm/msm_vfe32.h b/drivers/media/video/msm/msm_vfe32.h
index d763c2e..30b77d7 100644
--- a/drivers/media/video/msm/msm_vfe32.h
+++ b/drivers/media/video/msm/msm_vfe32.h
@@ -16,6 +16,15 @@
#define TRUE 1
#define FALSE 0
+#define VFE32_HW_NUMBER 0x3030B
+#define VFE33_HW_NUMBER 0x30408
+
+/* This defines total number registers in VFE.
+ * Each register is 4 bytes so to get the range,
+ * multiply this number with 4. */
+#define VFE32_REGISTER_TOTAL 0x000001CD
+#define VFE33_REGISTER_TOTAL 0x000001EE
+
/* at start of camif, bit 1:0 = 0x01:enable
* image data capture at frame boundary. */
#define CAMIF_COMMAND_START 0x00000005
@@ -903,6 +912,7 @@
int vfeirq;
void __iomem *vfebase;
void *syncdata;
+ uint32_t register_total;
struct resource *vfemem;
struct resource *vfeio;
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 3e61ad2..82582c4 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -202,6 +202,9 @@
struct power_supply batt_psy;
struct dentry *dent;
struct bms_notify bms_notify;
+ struct ext_chg_pm8921 *ext;
+ bool ext_charging;
+ bool ext_charge_done;
DECLARE_BITMAP(enabled_irqs, PM_CHG_MAX_INTS);
struct work_struct battery_id_valid_work;
int64_t batt_id_min;
@@ -757,8 +760,33 @@
return pm_chg_get_rt_status(chip, DCIN_VALID_IRQ);
}
+static bool is_ext_charging(struct pm8921_chg_chip *chip)
+{
+ if (chip->ext == NULL)
+ return false;
+
+ if (chip->ext_charging)
+ return true;
+
+ return false;
+}
+
+static bool is_ext_trickle_charging(struct pm8921_chg_chip *chip)
+{
+ if (chip->ext == NULL)
+ return false;
+
+ if (chip->ext->is_trickle(chip->ext->ctx))
+ return true;
+
+ return false;
+}
+
static int is_battery_charging(int fsm_state)
{
+ if (is_ext_charging(the_chip))
+ return 1;
+
switch (fsm_state) {
case FSM_STATE_ATC_2A:
case FSM_STATE_ATC_2B:
@@ -918,6 +946,15 @@
{
int temp;
+ if (!get_prop_batt_present(chip))
+ return POWER_SUPPLY_CHARGE_TYPE_NONE;
+
+ if (is_ext_trickle_charging(chip))
+ return POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
+
+ if (is_ext_charging(chip))
+ return POWER_SUPPLY_CHARGE_TYPE_FAST;
+
temp = pm_chg_get_rt_status(chip, TRKLCHG_IRQ);
if (temp)
return POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
@@ -933,6 +970,17 @@
{
int temp = 0;
+ if (!get_prop_batt_present(chip))
+ return POWER_SUPPLY_STATUS_UNKNOWN;
+
+ if (chip->ext) {
+ if (chip->ext_charge_done)
+ return POWER_SUPPLY_STATUS_FULL;
+
+ if (chip->ext_charging)
+ return POWER_SUPPLY_STATUS_CHARGING;
+ }
+
/* TODO reading the FSM state is more reliable */
temp = pm_chg_get_rt_status(chip, TRKLCHG_IRQ);
@@ -1259,6 +1307,77 @@
bms_notify_check(chip);
}
+static void handle_stop_ext_chg(struct pm8921_chg_chip *chip)
+{
+ if (chip->ext == NULL) {
+ pr_debug("external charger not registered.\n");
+ return;
+ }
+
+ if (!chip->ext_charging) {
+ pr_debug("already not charging.\n");
+ return;
+ }
+
+ chip->ext->stop_charging(chip->ext->ctx);
+ chip->ext_charging = false;
+}
+
+static void handle_start_ext_chg(struct pm8921_chg_chip *chip)
+{
+ int dc_present;
+ int batt_present;
+ int batt_temp_ok;
+ int vbat_ov;
+ int batfet;
+ unsigned long delay =
+ round_jiffies_relative(msecs_to_jiffies(EOC_CHECK_PERIOD_MS));
+
+ if (chip->ext == NULL) {
+ pr_debug("external charger not registered.\n");
+ return;
+ }
+
+ if (chip->ext_charging) {
+ pr_debug("already charging.\n");
+ return;
+ }
+
+ dc_present = is_dc_chg_plugged_in(chip);
+ batt_present = pm_chg_get_rt_status(chip, BATT_INSERTED_IRQ);
+ batt_temp_ok = pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ);
+ vbat_ov = pm_chg_get_rt_status(chip, VBAT_OV_IRQ);
+ batfet = pm_chg_get_rt_status(chip, BATFET_IRQ);
+
+ if (!dc_present) {
+ pr_warn("%s. dc not present.\n", __func__);
+ return;
+ }
+ if (!batt_present) {
+ pr_warn("%s. battery not present.\n", __func__);
+ return;
+ }
+ if (!batt_temp_ok) {
+ pr_warn("%s. battery temperature not ok.\n", __func__);
+ return;
+ }
+ if (vbat_ov) {
+ pr_warn("%s. battery over voltage.\n", __func__);
+ return;
+ }
+ if (!batfet) {
+ pr_warn("%s. battery FET not closed.\n", __func__);
+ return;
+ }
+
+ chip->ext->start_charging(chip->ext->ctx);
+ chip->ext_charging = true;
+ chip->ext_charge_done = false;
+ /* Start BMS */
+ schedule_delayed_work(&chip->eoc_work, delay);
+ wake_lock(&chip->eoc_wake_lock);
+}
+
static void handle_dc_removal_insertion(struct pm8921_chg_chip *chip)
{
int dc_present;
@@ -1290,11 +1409,21 @@
status = pm_chg_get_rt_status(chip, BATT_INSERTED_IRQ);
schedule_work(&chip->battery_id_valid_work);
+ handle_start_ext_chg(chip);
pr_debug("battery present=%d", status);
power_supply_changed(&chip->batt_psy);
return IRQ_HANDLED;
}
-/* this interrupt used to restart charging a battery */
+
+/*
+ * this interrupt used to restart charging a battery.
+ *
+ * Note: When DC-inserted the VBAT can't go low.
+ * VPH_PWR is provided by the ext-charger.
+ * After End-Of-Charging from DC, charging can be resumed only
+ * if DC is removed and then inserted after the battery was in use.
+ * Therefore the handle_start_ext_chg() is not called.
+ */
static irqreturn_t vbatdet_low_irq_handler(int irq, void *data)
{
struct pm8921_chg_chip *chip = data;
@@ -1355,6 +1484,9 @@
struct pm8921_chg_chip *chip = data;
pr_debug("state_changed_to=%d\n", pm_chg_get_fsm_state(data));
+
+ handle_stop_ext_chg(chip);
+
power_supply_changed(&chip->batt_psy);
power_supply_changed(&chip->usb_psy);
power_supply_changed(&chip->dc_psy);
@@ -1432,6 +1564,7 @@
status = pm_chg_get_rt_status(chip, BATT_REMOVED_IRQ);
pr_debug("battery present=%d state=%d", !status,
pm_chg_get_fsm_state(data));
+ handle_stop_ext_chg(chip);
power_supply_changed(&chip->batt_psy);
return IRQ_HANDLED;
}
@@ -1440,6 +1573,7 @@
{
struct pm8921_chg_chip *chip = data;
+ handle_stop_ext_chg(chip);
power_supply_changed(&chip->batt_psy);
return IRQ_HANDLED;
}
@@ -1460,6 +1594,8 @@
struct pm8921_chg_chip *chip = data;
pr_debug("Batt cold fsm_state=%d\n", pm_chg_get_fsm_state(data));
+ handle_stop_ext_chg(chip);
+
power_supply_changed(&chip->batt_psy);
power_supply_changed(&chip->usb_psy);
power_supply_changed(&chip->dc_psy);
@@ -1482,6 +1618,8 @@
struct pm8921_chg_chip *chip = data;
pr_debug("batt temp ok fsm_state=%d\n", pm_chg_get_fsm_state(data));
+ handle_start_ext_chg(chip);
+
power_supply_changed(&chip->batt_psy);
power_supply_changed(&chip->usb_psy);
power_supply_changed(&chip->dc_psy);
@@ -1524,17 +1662,33 @@
static irqreturn_t dcin_valid_irq_handler(int irq, void *data)
{
- handle_dc_removal_insertion(data);
+ struct pm8921_chg_chip *chip = data;
+
+ pm8921_disable_source_current(true); /* Force BATFET=ON */
+
+ handle_dc_removal_insertion(chip);
+ handle_start_ext_chg(chip);
return IRQ_HANDLED;
}
static irqreturn_t dcin_ov_irq_handler(int irq, void *data)
{
+ struct pm8921_chg_chip *chip = data;
+
+ pm8921_disable_source_current(false); /* release BATFET */
+
+ handle_dc_removal_insertion(chip);
+ handle_stop_ext_chg(chip);
return IRQ_HANDLED;
}
static irqreturn_t dcin_uv_irq_handler(int irq, void *data)
{
+ struct pm8921_chg_chip *chip = data;
+
+ pm8921_disable_source_current(false); /* release BATFET */
+ handle_stop_ext_chg(chip);
+
return IRQ_HANDLED;
}
@@ -1556,7 +1710,7 @@
}
/**
- * eoc_work - internal function to check if battery EOC
+ * eoc_worker - internal function to check if battery EOC
* has happened
*
* If all conditions favouring, if the charge current is
@@ -1569,7 +1723,7 @@
#define CONSECUTIVE_COUNT 3
#define VBAT_TOLERANCE_MV 70
#define CHG_DISABLE_MSLEEP 100
-static void eoc_work(struct work_struct *work)
+static void eoc_worker(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct pm8921_chg_chip *chip = container_of(dwork,
@@ -1580,41 +1734,44 @@
int rc;
static int count;
- /* return if the battery is not being fastcharged */
- fast_chg = pm_chg_get_rt_status(chip, FASTCHG_IRQ);
- pr_debug("fast_chg = %d\n", fast_chg);
- if (fast_chg == 0) {
- /* enable fastchg irq */
- pm8921_chg_enable_irq(chip, FASTCHG_IRQ);
- count = 0;
- wake_unlock(&chip->eoc_wake_lock);
- return;
- }
+ if (!is_ext_charging(chip)) {
+ /* return if the battery is not being fastcharged */
+ fast_chg = pm_chg_get_rt_status(chip, FASTCHG_IRQ);
+ pr_debug("fast_chg = %d\n", fast_chg);
+ if (fast_chg == 0) {
+ /* enable fastchg irq */
+ pm8921_chg_enable_irq(chip, FASTCHG_IRQ);
+ count = 0;
+ wake_unlock(&chip->eoc_wake_lock);
+ return;
+ }
- vcp = pm_chg_get_rt_status(chip, VCP_IRQ);
- pr_debug("vcp = %d\n", vcp);
- if (vcp == 1)
- goto reset_and_reschedule;
+ vcp = pm_chg_get_rt_status(chip, VCP_IRQ);
+ pr_debug("vcp = %d\n", vcp);
+ if (vcp == 1)
+ goto reset_and_reschedule;
- /* reset count if battery is hot/cold */
- rc = pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ);
- pr_debug("batt_temp_ok = %d\n", rc);
- if (rc == 0)
- goto reset_and_reschedule;
+ /* reset count if battery is hot/cold */
+ rc = pm_chg_get_rt_status(chip, BAT_TEMP_OK_IRQ);
+ pr_debug("batt_temp_ok = %d\n", rc);
+ if (rc == 0)
+ goto reset_and_reschedule;
- /* reset count if battery voltage is less than vddmax */
- vbat_meas = get_prop_battery_mvolts(chip);
- if (vbat_meas < 0)
- goto reset_and_reschedule;
+ /* reset count if battery voltage is less than vddmax */
+ vbat_meas = get_prop_battery_mvolts(chip);
+ if (vbat_meas < 0)
+ goto reset_and_reschedule;
- rc = pm_chg_vddmax_get(chip, &vbat_programmed);
- if (rc) {
- pr_err("couldnt read vddmax rc = %d\n", rc);
- goto reset_and_reschedule;
- }
- pr_debug("vddmax = %d vbat_meas=%d\n", vbat_programmed, vbat_meas);
- if (vbat_meas < vbat_programmed - VBAT_TOLERANCE_MV)
- goto reset_and_reschedule;
+ rc = pm_chg_vddmax_get(chip, &vbat_programmed);
+ if (rc) {
+ pr_err("couldnt read vddmax rc = %d\n", rc);
+ goto reset_and_reschedule;
+ }
+ pr_debug("vddmax = %d vbat_meas=%d\n",
+ vbat_programmed, vbat_meas);
+ if (vbat_meas < vbat_programmed - VBAT_TOLERANCE_MV)
+ goto reset_and_reschedule;
+ } /* !is_ext_charging */
/* reset count if battery chg current is more than iterm */
rc = pm_chg_iterm_get(chip, &iterm_programmed);
@@ -1636,20 +1793,22 @@
if (ichg_meas * -1 > iterm_programmed)
goto reset_and_reschedule;
- /*
- * TODO if charging from an external charger check SOC instead of
- * regulation loop
- */
- regulation_loop = pm_chg_get_regulation_loop(chip);
- if (regulation_loop < 0) {
- pr_err("couldnt read the regulation loop err=%d\n",
- regulation_loop);
- goto reset_and_reschedule;
- }
- pr_debug("regulation_loop=%d\n", regulation_loop);
+ if (!is_ext_charging(chip)) {
+ /*
+ * TODO if charging from an external charger
+ * check SOC instead of regulation loop
+ */
+ regulation_loop = pm_chg_get_regulation_loop(chip);
+ if (regulation_loop < 0) {
+ pr_err("couldnt read the regulation loop err=%d\n",
+ regulation_loop);
+ goto reset_and_reschedule;
+ }
+ pr_debug("regulation_loop=%d\n", regulation_loop);
- if (regulation_loop != 0 && regulation_loop != VDD_LOOP)
- goto reset_and_reschedule;
+ if (regulation_loop != 0 && regulation_loop != VDD_LOOP)
+ goto reset_and_reschedule;
+ } /* !is_ext_charging */
count++;
if (count == CONSECUTIVE_COUNT) {
@@ -1658,6 +1817,9 @@
pm_chg_auto_enable(chip, 0);
+ if (is_ext_charging(chip))
+ chip->ext_charge_done = true;
+
/* declare end of charging by invoking chgdone interrupt */
chgdone_irq_handler(chip->pmic_chg_irq[CHGDONE_IRQ], chip);
wake_unlock(&chip->eoc_wake_lock);
@@ -1738,6 +1900,36 @@
return rc;
}
+int register_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ if (the_chip == NULL) {
+ pr_err("called too early\n");
+ return -EINVAL;
+ }
+ /* TODO check function pointers */
+ the_chip->ext = ext;
+ the_chip->ext_charging = false;
+
+ if (is_dc_chg_plugged_in(the_chip))
+ pm8921_disable_source_current(true); /* Force BATFET=ON */
+
+ handle_start_ext_chg(the_chip);
+
+ return 0;
+}
+EXPORT_SYMBOL(register_external_dc_charger);
+
+void unregister_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ if (the_chip == NULL) {
+ pr_err("called too early\n");
+ return;
+ }
+ handle_stop_ext_chg(the_chip);
+ the_chip->ext = NULL;
+}
+EXPORT_SYMBOL(unregister_external_dc_charger);
+
/**
* set_disable_status_param -
*
@@ -2397,7 +2589,7 @@
the_chip = chip;
wake_lock_init(&chip->eoc_wake_lock, WAKE_LOCK_SUSPEND, "pm8921_eoc");
- INIT_DELAYED_WORK(&chip->eoc_work, eoc_work);
+ INIT_DELAYED_WORK(&chip->eoc_work, eoc_worker);
rc = request_irqs(chip, pdev);
if (rc) {
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 936b5d4..ca3c079 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -1442,6 +1442,10 @@
}
#endif
+ if (mdp_rev >= MDP_REV_40)
+ mfd->cursor_update = mdp_hw_cursor_sync_update;
+ else
+ mfd->cursor_update = mdp_hw_cursor_update;
break;
case MIPI_CMD_PANEL:
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index d2a2cf8..590fd13 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -680,7 +680,16 @@
#endif
int mdp_hw_cursor_update(struct fb_info *info, struct fb_cursor *cursor);
+#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDP40)
int mdp_hw_cursor_sync_update(struct fb_info *info, struct fb_cursor *cursor);
+#else
+static inline int mdp_hw_cursor_sync_update(struct fb_info *info,
+ struct fb_cursor *cursor)
+{
+ return 0;
+}
+#endif
+
void mdp_enable_irq(uint32 term);
void mdp_disable_irq(uint32 term);
void mdp_disable_irq_nosync(uint32 term);
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index 9f98656..aeb88b2 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -119,6 +119,26 @@
PM8921_CHG_SRC_DC,
};
+/**
+ * struct ext_chg_pm8921 -
+ * @name: name of the external charger
+ * @ctx: client context.
+ * @start_charging: callback to start charging. Can be called from an
+ * interrupt context
+ * @stop_charging: callback to stop charging. Can be called from an
+ * interrupt context
+ * @is_trickle: callback to check if trickle charging.
+ * Can be called from an interrupt context
+ *
+ */
+struct ext_chg_pm8921 {
+ const char *name;
+ void *ctx;
+ int (*start_charging) (void *ctx);
+ int (*stop_charging) (void *ctx);
+ bool (*is_trickle) (void *ctx);
+};
+
#if defined(CONFIG_PM8921_CHARGER) || defined(CONFIG_PM8921_CHARGER_MODULE)
void pm8921_charger_vbus_draw(unsigned int mA);
int pm8921_charger_register_vbus_sn(void (*callback)(int));
@@ -190,6 +210,28 @@
*
*/
int pm8921_batt_temperature(void);
+/**
+ * register_external_dc_charger -
+ * @ext: The structure representing an external charger
+ *
+ * RETURNS: Negative error code is there was a problem. Zero for sucess
+ *
+ * The charger callbacks might be called even before this function
+ * completes. The external charger driver should be ready to handle
+ * it.
+ */
+int register_external_dc_charger(struct ext_chg_pm8921 *ext);
+
+/**
+ * unregister_external_dc_charger -
+ * @ext: The structure representing an external charger
+ *
+ * The charger callbacks might be called even before this function
+ * completes. The external charger driver should be ready to handle
+ * it.
+ */
+void unregister_external_dc_charger(struct ext_chg_pm8921 *ext);
+
#else
static inline void pm8921_charger_vbus_draw(unsigned int mA)
{
@@ -238,6 +280,15 @@
{
return -ENXIO;
}
+static inline int register_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ pr_err("%s.not implemented.\n", __func__);
+ return -ENODEV;
+}
+static inline void unregister_external_dc_charger(struct ext_chg_pm8921 *ext)
+{
+ pr_err("%s.not implemented.\n", __func__);
+}
#endif
#endif
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index e64f4c6..3cd86ea 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -68,18 +68,18 @@
#define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3])
-enum {
- TCP_FLAG_CWR = __cpu_to_be32(0x00800000),
- TCP_FLAG_ECE = __cpu_to_be32(0x00400000),
- TCP_FLAG_URG = __cpu_to_be32(0x00200000),
- TCP_FLAG_ACK = __cpu_to_be32(0x00100000),
- TCP_FLAG_PSH = __cpu_to_be32(0x00080000),
- TCP_FLAG_RST = __cpu_to_be32(0x00040000),
- TCP_FLAG_SYN = __cpu_to_be32(0x00020000),
- TCP_FLAG_FIN = __cpu_to_be32(0x00010000),
- TCP_RESERVED_BITS = __cpu_to_be32(0x0F000000),
- TCP_DATA_OFFSET = __cpu_to_be32(0xF0000000)
-};
+enum {
+ TCP_FLAG_CWR = __constant_htonl(0x00800000),
+ TCP_FLAG_ECE = __constant_htonl(0x00400000),
+ TCP_FLAG_URG = __constant_htonl(0x00200000),
+ TCP_FLAG_ACK = __constant_htonl(0x00100000),
+ TCP_FLAG_PSH = __constant_htonl(0x00080000),
+ TCP_FLAG_RST = __constant_htonl(0x00040000),
+ TCP_FLAG_SYN = __constant_htonl(0x00020000),
+ TCP_FLAG_FIN = __constant_htonl(0x00010000),
+ TCP_RESERVED_BITS = __constant_htonl(0x0F000000),
+ TCP_DATA_OFFSET = __constant_htonl(0xF0000000)
+};
/*
* TCP general constants
@@ -134,6 +134,7 @@
__u8 tcpi_backoff;
__u8 tcpi_options;
__u8 tcpi_snd_wscale : 4, tcpi_rcv_wscale : 4;
+ __u8 tcpi_count;
__u32 tcpi_rto;
__u32 tcpi_ato;
diff --git a/include/media/msm_isp.h b/include/media/msm_isp.h
index b7fd30f..d4fe4ca 100644
--- a/include/media/msm_isp.h
+++ b/include/media/msm_isp.h
@@ -165,6 +165,12 @@
#define VFE_CMD_CLF_CHROMA_UPDATE 119
#define VFE_CMD_PCA_ROLL_OFF_CFG 120
#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
+#define VFE_CMD_GET_REG_DUMP 122
+#define VFE_CMD_GET_LINEARIZATON_TABLE 123
+#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
+#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
+#define VFE_CMD_GET_RGB_G_TABLE 126
+#define VFE_CMD_GET_LA_TABLE 127
struct msm_isp_cmd {
int32_t id;
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index f2d9813..e5f1113 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -2504,6 +2504,15 @@
info->tcpi_rcv_space = tp->rcvq_space.space;
info->tcpi_total_retrans = tp->total_retrans;
+
+ /*
+ * Expose reference count for socket.
+ */
+ if (NULL != sk->sk_socket) {
+ struct file *filep = sk->sk_socket->file;
+ if (NULL != filep)
+ info->tcpi_count = atomic_read(&filep->f_count);
+ }
}
EXPORT_SYMBOL_GPL(tcp_get_info);