msm: Allow conditional L2 flush during power collapse
On existing targets, L2 is flushed every time any of the core executes a
power collapse. This adds latency into the enter path for idle power
collapse. This commit provides a API that would vote for a L2 flush
during power collapse.
Remove invalidating the L1/L2 cache during warmboot. On
Krait/Scorpion processors, the boot loaders code takes care of
invalidating the L1/L2 cache. On A5 processor, L1 is invalidated at reset.
And the L2 cache is invalidated later in the boot process using the L2
cache controller.
Change-Id: Ib63cfefafcc3aa887faa902a9856fbc5eb137075
Signed-off-by: Maheshkumar Sivasubramanian <msivasub@codeaurora.org>
diff --git a/arch/arm/mach-msm/rpm_resources.c b/arch/arm/mach-msm/rpm_resources.c
index e6b91ee..0cc2272 100644
--- a/arch/arm/mach-msm/rpm_resources.c
+++ b/arch/arm/mach-msm/rpm_resources.c
@@ -28,6 +28,7 @@
#include "mpm.h"
#include "rpm_resources.h"
#include "spm.h"
+#include "idle.h"
/******************************************************************************
* Debug Definitions
@@ -513,6 +514,7 @@
BUG_ON(!msm_rpmrs_l2_counter_addr);
writel_relaxed(++msm_rpmrs_l2_reset_count,
msm_rpmrs_l2_counter_addr);
+ msm_pm_set_l2_flush_flag(1);
break;
case MSM_RPMRS_L2_CACHE_GDHS:
lpm = MSM_SPM_L2_MODE_GDHS;
@@ -537,6 +539,7 @@
bool notify_rpm, bool collapsed)
{
msm_spm_l2_set_low_power_mode(MSM_SPM_MODE_DISABLED, notify_rpm);
+ msm_pm_set_l2_flush_flag(0);
if (!collapsed && (limits->l2_cache == MSM_RPMRS_L2_CACHE_HSFS_OPEN))
writel_relaxed(--msm_rpmrs_l2_reset_count,
msm_rpmrs_l2_counter_addr);
@@ -769,6 +772,7 @@
goto resource_sysfs_add_exit;
}
+ rc = 0;
resource_sysfs_add_exit:
if (rc) {
if (low_power_kobj)
@@ -1063,6 +1067,8 @@
msm_rpmrs_l2_counter_addr);
mb();
+ msm_pm_set_l2_flush_flag(0);
+
msm_rpmrs_l2_cache.beyond_limits =
msm_spm_l2_cache_beyond_limits;
msm_rpmrs_l2_cache.aggregate = NULL;