msm: 8064: Enable SDC2 and SDC4 slots
Add support for SDC2/4 primarily for SDIO cards. On
reference platform, card-detect and write-protect
GPIOS cannot be monitored, so polling must be
enabled.
Change-Id: I6c42c208faccd50a0448d3abf18c9a9e97f87783
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8064-gpiomux.c b/arch/arm/mach-msm/board-8064-gpiomux.c
index b018a20..6ef1335a 100644
--- a/arch/arm/mach-msm/board-8064-gpiomux.c
+++ b/arch/arm/mach-msm/board-8064-gpiomux.c
@@ -1023,6 +1023,151 @@
},
};
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+static struct gpiomux_setting sdc2_clk_active_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting sdc2_cmd_data_0_3_active_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct gpiomux_setting sdc2_suspended_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting sdc2_data_1_suspended_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct msm_gpiomux_config apq8064_sdc2_configs[] __initdata = {
+ {
+ .gpio = 59,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc2_clk_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc2_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 57,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc2_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc2_suspended_cfg,
+ },
+
+ },
+ {
+ .gpio = 62,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc2_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc2_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 61,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc2_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc2_data_1_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 60,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc2_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc2_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 58,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc2_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc2_suspended_cfg,
+ },
+ },
+};
+#endif
+
+
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+static struct gpiomux_setting sdc4_clk_active_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting sdc4_cmd_data_0_3_active_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct gpiomux_setting sdc4_suspended_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting sdc4_data_1_suspended_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct msm_gpiomux_config apq8064_sdc4_configs[] __initdata = {
+ {
+ .gpio = 68,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc4_clk_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc4_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 67,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc4_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc4_suspended_cfg,
+ },
+
+ },
+ {
+ .gpio = 66,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc4_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc4_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 65,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc4_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc4_data_1_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 64,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc4_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc4_suspended_cfg,
+ },
+ },
+ {
+ .gpio = 63,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdc4_cmd_data_0_3_active_cfg,
+ [GPIOMUX_SUSPENDED] = &sdc4_suspended_cfg,
+ },
+ },
+};
+#endif
+
void __init apq8064_init_gpiomux(void)
{
int rc;
@@ -1104,4 +1249,14 @@
if (machine_is_mpq8064_cdp())
msm_gpiomux_install(mpq8064_ir_configs,
ARRAY_SIZE(mpq8064_ir_configs));
+
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+ msm_gpiomux_install(apq8064_sdc2_configs,
+ ARRAY_SIZE(apq8064_sdc2_configs));
+#endif
+
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+ msm_gpiomux_install(apq8064_sdc4_configs,
+ ARRAY_SIZE(apq8064_sdc4_configs));
+#endif
}
diff --git a/arch/arm/mach-msm/board-8064-storage.c b/arch/arm/mach-msm/board-8064-storage.c
index 72126c8..96e54b6 100644
--- a/arch/arm/mach-msm/board-8064-storage.c
+++ b/arch/arm/mach-msm/board-8064-storage.c
@@ -188,13 +188,50 @@
},
};
+static struct msm_mmc_gpio sdc2_gpio[] = {
+ {59, "sdc2_clk"},
+ {57, "sdc2_cmd"},
+ {62, "sdc2_dat_0"},
+ {61, "sdc2_dat_1"},
+ {60, "sdc2_dat_2"},
+ {58, "sdc2_dat_3"},
+};
+
+static struct msm_mmc_gpio sdc4_gpio[] = {
+ {68, "sdc4_clk"},
+ {67, "sdc4_cmd"},
+ {66, "sdc4_dat_0"},
+ {65, "sdc4_dat_1"},
+ {64, "sdc4_dat_2"},
+ {63, "sdc4_dat_3"},
+};
+
+static struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = {
+ [SDCC2] = {
+ .gpio = sdc2_gpio,
+ .size = ARRAY_SIZE(sdc2_gpio),
+ },
+ [SDCC4] = {
+ .gpio = sdc4_gpio,
+ .size = ARRAY_SIZE(sdc4_gpio),
+ }
+};
+
static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
[SDCC1] = {
.pad_data = &mmc_pad_data[SDCC1],
},
+ [SDCC2] = {
+ .is_gpio = 1,
+ .gpio_data = &mmc_gpio_data[SDCC2],
+ },
[SDCC3] = {
.pad_data = &mmc_pad_data[SDCC3],
},
+ [SDCC4] = {
+ .is_gpio = 1,
+ .gpio_data = &mmc_gpio_data[SDCC4],
+ },
};
#define MSM_MPM_PIN_SDC1_DAT1 17
@@ -227,6 +264,26 @@
static struct mmc_platform_data *apq8064_sdc1_pdata;
#endif
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+static unsigned int sdc2_sup_clk_rates[] = {
+ 400000, 24000000, 48000000
+};
+
+static struct mmc_platform_data sdc2_data = {
+ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
+ .mmc_bus_width = MMC_CAP_4_BIT_DATA,
+ .sup_clk_table = sdc2_sup_clk_rates,
+ .sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
+ .pclk_src_dfab = 1,
+ .pin_data = &mmc_slot_pin_data[SDCC2],
+ .sdiowakeup_irq = MSM_GPIO_TO_INT(61),
+ .msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
+};
+static struct mmc_platform_data *apq8064_sdc2_pdata = &sdc2_data;
+#else
+static struct mmc_platform_data *apq8064_sdc2_pdata;
+#endif
+
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
static unsigned int sdc3_sup_clk_rates[] = {
400000, 24000000, 48000000, 96000000, 192000000
@@ -258,6 +315,27 @@
static struct mmc_platform_data *apq8064_sdc3_pdata;
#endif
+
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+static unsigned int sdc4_sup_clk_rates[] = {
+ 400000, 24000000, 48000000
+};
+
+static struct mmc_platform_data sdc4_data = {
+ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
+ .mmc_bus_width = MMC_CAP_4_BIT_DATA,
+ .sup_clk_table = sdc4_sup_clk_rates,
+ .sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
+ .pclk_src_dfab = 1,
+ .pin_data = &mmc_slot_pin_data[SDCC4],
+ .sdiowakeup_irq = MSM_GPIO_TO_INT(65),
+ .msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
+};
+static struct mmc_platform_data *apq8064_sdc4_pdata = &sdc4_data;
+#else
+static struct mmc_platform_data *apq8064_sdc4_pdata;
+#endif
+
void __init apq8064_init_mmc(void)
{
if ((machine_is_apq8064_rumi3()) || machine_is_apq8064_sim()) {
@@ -278,6 +356,9 @@
if (apq8064_sdc1_pdata)
apq8064_add_sdcc(1, apq8064_sdc1_pdata);
+ if (apq8064_sdc2_pdata)
+ apq8064_add_sdcc(2, apq8064_sdc2_pdata);
+
if (apq8064_sdc3_pdata) {
if (!machine_is_apq8064_cdp()) {
apq8064_sdc3_pdata->wpswitch_gpio = 0;
@@ -292,4 +373,7 @@
}
apq8064_add_sdcc(3, apq8064_sdc3_pdata);
}
+
+ if (apq8064_sdc4_pdata)
+ apq8064_add_sdcc(4, apq8064_sdc4_pdata);
}