tree d7fbdeea3ea85fd65ce20a5132e4264cb866c9c9
parent 75154f402ef18e459ff97ddece25656b6c2b329c
author Haavard Skinnemoen <hskinnemoen@atmel.com> 1182168498 +0200
committer Haavard Skinnemoen <hskinnemoen@atmel.com> 1182603172 +0200

[AVR32] Fix bug in invalidate_dcache_region()

If (start + size) is not cacheline aligned and (start & mask) > (end &
mask), the last but one cacheline won't be invalidated as it should.
Fix this by rounding `end' down to the nearest cacheline boundary if
it gets adjusted due to misalignment.

Also flush the write buffer unconditionally -- if the dcache wrote
back a line just before we invalidated it, the dirty data may be
sitting in the write buffer waiting to corrupt our buffer later.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>