msm: clock: Rename measure_clk_ops and clk_pll_ops
All other clock types follow the "clk_ops_<type>" naming convention.
Update the ops for measure_clk and pll_clk types to match this.
Change-Id: Ieebce91430c88ba8b6b79121ec7d60f017318e92
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index d842d45..f71d6d5 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -39,7 +39,7 @@
.id = PLL_0,
.mode_reg = PLLn_MODE(0),
.c = {
- .ops = &clk_pll_ops,
+ .ops = &clk_ops_pll,
.dbg_name = "pll0_clk",
CLK_INIT(pll0_clk.c),
},
@@ -49,7 +49,7 @@
.id = PLL_1,
.mode_reg = PLLn_MODE(1),
.c = {
- .ops = &clk_pll_ops,
+ .ops = &clk_ops_pll,
.dbg_name = "pll1_clk",
CLK_INIT(pll1_clk.c),
},
@@ -59,7 +59,7 @@
.id = PLL_2,
.mode_reg = PLLn_MODE(2),
.c = {
- .ops = &clk_pll_ops,
+ .ops = &clk_ops_pll,
.dbg_name = "pll2_clk",
CLK_INIT(pll2_clk.c),
},
@@ -69,7 +69,7 @@
.id = PLL_4,
.mode_reg = PLL4_MODE,
.c = {
- .ops = &clk_pll_ops,
+ .ops = &clk_ops_pll,
.dbg_name = "pll4_clk",
CLK_INIT(pll4_clk.c),
},