tree 387755844593ae99cdc38b4556d775a100cde7da
parent e653034e66ec406f37427f588115badc6fc6af64
author Kevin Hilman <khilman@deeprootsystems.com> 1237595341 -0700
committer Kevin Hilman <khilman@deeprootsystems.com> 1240504260 -0700

davinci: major rework of clock, PLL, PSC infrastructure

This is a significant rework of the low-level clock, PLL and Power
Sleep Controller (PSC) implementation for the DaVinci family.  The
primary goal is to have better modeling if the hardware clocks and
features with the aim of DVFS functionality.

Highlights:
- model PLLs and all PLL-derived clocks
- model parent/child relationships of PLLs and clocks
- convert to new clkdev layer
- view clock frequency and refcount via /proc/davinci_clocks

Special thanks to significant contributions and testing by David
Brownell.

Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>