Merge "coresight: fix whitespace in coresight drivers" into msm-3.4
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index a1bc937..ee0a264 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -350,6 +350,72 @@
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
};
+
+ chan@2 {
+ label = "vchg_sns";
+ qcom,channel-num = <2>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <6>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@5 {
+ label = "vcoin";
+ qcom,channel-num = <5>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <3>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@6 {
+ label = "vbat_sns";
+ qcom,channel-num = <6>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <3>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ qcom,channel-num = <7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <3>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ qcom,channel-num = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@10 {
+ label = "ref_1125v";
+ qcom,channel-num = <10>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
};
iadc@3600 {
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 36ff8c3..0b7d2c5 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -685,16 +685,18 @@
compatible = "qcom,qcedev";
reg = <0xfd440000 0x20000>,
<0xfd444000 0x8000>;
+ reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 235 0>;
- qcom,bam-pipes = <0>;
+ qcom,bam-pipe-pair = <0>;
};
qcom,qcrypto@fd444000 {
compatible = "qcom,qcrypto";
reg = <0xfd440000 0x20000>,
<0xfd444000 0x8000>;
+ reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 235 0>;
- qcom,bam-pipes = <1>;
+ qcom,bam-pipe-pair = <1>;
};
qcom,usbbam@f9304000 {
@@ -732,6 +734,15 @@
qcom,descriptor-fifo-size = <0x1400>;
};
};
+
+ qcom,msm-thermal {
+ compatible = "qcom,msm-thermal";
+ qcom,sensor-id = <0>;
+ qcom,poll-ms = <250>;
+ qcom,limit-temp = <60>;
+ qcom,temp-hysteresis = <10>;
+ qcom,freq-step = <2>;
+ };
};
/include/ "msm-pm8x41-rpm-regulator.dtsi"
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index 0949213..c73c62e 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -52,6 +52,8 @@
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_OCMEM=y
CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
+CONFIG_MSM_OCMEM_DEBUG=y
+CONFIG_MSM_OCMEM_POWER_DISABLE=y
CONFIG_MSM_MEMORY_DUMP=y
CONFIG_MSM_CACHE_ERP=y
CONFIG_MSM_L1_ERR_PANIC=y
@@ -256,4 +258,3 @@
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
-CONFIG_MSM_BUS_SCALING=y
diff --git a/arch/arm/mach-msm/board-8930-gpiomux.c b/arch/arm/mach-msm/board-8930-gpiomux.c
index e0f012a..ff0a61f 100644
--- a/arch/arm/mach-msm/board-8930-gpiomux.c
+++ b/arch/arm/mach-msm/board-8930-gpiomux.c
@@ -688,6 +688,22 @@
},
};
+static struct gpiomux_setting gyro_int_line = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct msm_gpiomux_config msm8930_gyro_int_config[] __initdata = {
+ {
+ .gpio = 69, /* Gyro Interrupt Line */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gyro_int_line,
+ [GPIOMUX_ACTIVE] = &gyro_int_line,
+ },
+ },
+};
+
int __init msm8930_init_gpiomux(void)
{
int rc = msm_gpiomux_init(NR_GPIO_IRQS);
@@ -758,5 +774,9 @@
msm_gpiomux_install(msm8930_sd_det_config,
ARRAY_SIZE(msm8930_sd_det_config));
+ if (machine_is_msm8930_fluid() || machine_is_msm8930_mtp())
+ msm_gpiomux_install(msm8930_gyro_int_config,
+ ARRAY_SIZE(msm8930_gyro_int_config));
+
return 0;
}
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index b80d62d..4fce029 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -2431,6 +2431,7 @@
static struct i2c_board_info __initdata mpu3050_i2c_boardinfo[] = {
{
I2C_BOARD_INFO("mpu3050", 0x68),
+ .irq = MSM_GPIO_TO_INT(MPU3050_INT_GPIO),
.platform_data = &mpu3050_gyro,
},
};
diff --git a/arch/arm/mach-msm/board-8974.c b/arch/arm/mach-msm/board-8974.c
index ba8d7770..388307b 100644
--- a/arch/arm/mach-msm/board-8974.c
+++ b/arch/arm/mach-msm/board-8974.c
@@ -26,6 +26,7 @@
#endif
#include <linux/regulator/machine.h>
#include <linux/regulator/krait-regulator.h>
+#include <linux/msm_thermal.h>
#include <asm/mach/map.h>
#include <asm/hardware/gic.h>
#include <mach/board.h>
@@ -434,6 +435,7 @@
else
msm_clock_init(&msm8974_clock_init_data);
msm8974_init_buses();
+ msm_thermal_device_init();
}
static struct of_device_id irq_match[] __initdata = {
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 9c5e436..8ac1c88 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -104,6 +104,7 @@
#define CLOCK_FRQ_MEASURE_CTL_REG 0x1884
#define CLOCK_FRQ_MEASURE_STATUS_REG 0x1888
#define GCC_XO_DIV4_CBCR_REG 0x10C8
+#define GCC_PLLTEST_PAD_CFG_REG 0x188C
#define APCS_GPLL_ENA_VOTE_REG 0x1480
#define MMSS_PLL_VOTE_APCS_REG 0x0100
#define MMSS_DEBUG_CLK_CTL_REG 0x0900
@@ -488,13 +489,13 @@
#define OCMEMNOC_CBCR 0x50B4
#define LPASS_Q6SS_AHB_LFABIF_CBCR 0x22000
#define LPASS_Q6SS_XO_CBCR 0x26000
+#define LPASS_Q6_AXI_CBCR 0x11C0
#define Q6SS_AHBM_CBCR 0x22004
#define MSS_XO_Q6_CBCR 0x108C
#define MSS_BUS_Q6_CBCR 0x10A4
#define MSS_CFG_AHB_CBCR 0x0280
+#define MSS_Q6_BIMC_AXI_CBCR 0x0284
-#define GCC_USB_BOOT_CLOCK_CTL 0x1A00
-#define GCC_KPSS_BOOT_CLOCK_CTL 0x19C0
#define APCS_CLOCK_BRANCH_ENA_VOTE 0x1484
#define APCS_CLOCK_SLEEP_ENA_VOTE 0x1488
@@ -2291,6 +2292,17 @@
},
};
+static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
+ .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
+ .has_sibling = 1,
+ .base = &virt_bases[GCC_BASE],
+ .c = {
+ .dbg_name = "gcc_mss_q6_bimc_axi_clk",
+ .ops = &clk_ops_branch,
+ CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
+ },
+};
+
static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
F_MM( 19200000, cxo, 1, 0, 0),
F_MM(150000000, gpll0, 4, 0, 0),
@@ -3896,7 +3908,7 @@
};
static struct clk_freq_tbl ftbl_audio_core_slimbus_core_clock[] = {
- F_LPASS(28800000, lpapll0, 1, 15, 256),
+ F_LPASS(24576000, lpapll0, 4, 1, 5),
F_END
};
@@ -4322,6 +4334,17 @@
},
};
+static struct branch_clk gcc_lpass_q6_axi_clk = {
+ .cbcr_reg = LPASS_Q6_AXI_CBCR,
+ .has_sibling = 1,
+ .base = &virt_bases[GCC_BASE],
+ .c = {
+ .dbg_name = "gcc_lpass_q6_axi_clk",
+ .ops = &clk_ops_branch,
+ CLK_INIT(gcc_lpass_q6_axi_clk.c),
+ },
+};
+
static struct branch_clk q6ss_xo_clk = {
.cbcr_reg = LPASS_Q6SS_XO_CBCR,
.bcr_reg = LPASS_Q6SS_BCR,
@@ -4455,6 +4478,8 @@
{&gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071},
{&gcc_ocmem_noc_cfg_ahb_clk.c, GCC_BASE, 0x0029},
{&gcc_ce1_clk.c, GCC_BASE, 0x0138},
+ {&gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160},
+ {&gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031},
{&mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004},
{&ocmemnoc_clk.c, MMSS_BASE, 0x0007},
{&ocmemcx_ocmemnoc_clk.c, MMSS_BASE, 0x0009},
@@ -4706,6 +4731,7 @@
ret = (raw_count_full * clk->multiplier);
}
+ writel_relaxed(0x51A00, GCC_REG_BASE(GCC_PLLTEST_PAD_CFG_REG));
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
clk_disable_unprepare(&cxo_clk_src.c);
@@ -5020,13 +5046,16 @@
CLK_LOOKUP("core_oe_clk", audio_core_lpaif_pcmoe_clk.c,
"msm-dai-q6.4106"),
- CLK_LOOKUP("core_clk", mss_xo_q6_clk.c, "pil-q6v5-mss"),
- CLK_LOOKUP("bus_clk", mss_bus_q6_clk.c, "pil-q6v5-mss"),
- CLK_LOOKUP("bus_clk", gcc_mss_cfg_ahb_clk.c, ""),
- CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "pil-q6v5-mss"),
- CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "pil-q6v5-lpass"),
- CLK_LOOKUP("bus_clk", q6ss_ahb_lfabif_clk.c, "pil-q6v5-lpass"),
- CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("core_clk", mss_xo_q6_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("reg_clk", mss_bus_q6_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "pil-q6v5-mss"),
+
+ CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "pil-q6v5-lpass"),
CLK_LOOKUP("core_clk", gcc_prng_ahb_clk.c, "msm_rng"),
CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
@@ -5303,10 +5332,6 @@
*/
writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
- /* Clear a bit that forces-on certain USB HS and Krait clocks */
- writel_relaxed(0x0, GCC_REG_BASE(GCC_USB_BOOT_CLOCK_CTL));
- writel_relaxed(0x0, GCC_REG_BASE(GCC_KPSS_BOOT_CLOCK_CTL));
-
/*
* TODO: The following sequence enables the LPASS audio core GDSC.
* Remove when this becomes unnecessary.
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 90e0089..0d05df9 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -102,6 +102,15 @@
.bark_time = 11000,
.has_secure = true,
.needs_expired_enable = true,
+ .base = MSM_TMR0_BASE + WDT0_OFFSET,
+};
+
+static struct resource msm_watchdog_resources[] = {
+ {
+ .start = WDT0_ACCSCSSNBARK_INT,
+ .end = WDT0_ACCSCSSNBARK_INT,
+ .flags = IORESOURCE_IRQ,
+ },
};
struct platform_device msm8064_device_watchdog = {
@@ -110,6 +119,8 @@
.dev = {
.platform_data = &msm_watchdog_pdata,
},
+ .num_resources = ARRAY_SIZE(msm_watchdog_resources),
+ .resource = msm_watchdog_resources,
};
static struct resource msm_dmov_resource[] = {
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 680770e..8347580 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -1331,6 +1331,15 @@
.pet_time = 10000,
.bark_time = 11000,
.has_secure = true,
+ .base = MSM_TMR0_BASE + WDT0_OFFSET,
+};
+
+static struct resource msm_watchdog_resources[] = {
+ {
+ .start = WDT0_ACCSCSSNBARK_INT,
+ .end = WDT0_ACCSCSSNBARK_INT,
+ .flags = IORESOURCE_IRQ,
+ },
};
struct platform_device msm8960_device_watchdog = {
@@ -1339,6 +1348,8 @@
.dev = {
.platform_data = &msm_watchdog_pdata,
},
+ .num_resources = ARRAY_SIZE(msm_watchdog_resources),
+ .resource = msm_watchdog_resources,
};
static struct resource msm_dmov_resource[] = {
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index fff8e0d..c307714 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -70,6 +70,15 @@
.bark_time = 11000,
.has_secure = false,
.use_kernel_fiq = true,
+ .base = MSM_TMR_BASE + WDT0_OFFSET,
+};
+
+static struct resource msm_watchdog_resources[] = {
+ {
+ .start = WDT0_ACCSCSSNBARK_INT,
+ .end = WDT0_ACCSCSSNBARK_INT,
+ .flags = IORESOURCE_IRQ,
+ },
};
struct platform_device msm9615_device_watchdog = {
@@ -78,6 +87,8 @@
.dev = {
.platform_data = &msm_watchdog_pdata,
},
+ .num_resources = ARRAY_SIZE(msm_watchdog_resources),
+ .resource = msm_watchdog_resources,
};
static struct resource msm_dmov_resource[] = {
diff --git a/arch/arm/mach-msm/devices-fsm9xxx.c b/arch/arm/mach-msm/devices-fsm9xxx.c
index 5f4d940..639eeae 100644
--- a/arch/arm/mach-msm/devices-fsm9xxx.c
+++ b/arch/arm/mach-msm/devices-fsm9xxx.c
@@ -419,6 +419,15 @@
.bark_time = 11000,
.has_secure = false,
.has_vic = true,
+ .base = MSM_TMR_BASE + WDT1_OFFSET,
+};
+
+static struct resource msm_watchdog_resources[] = {
+ {
+ .start = INT_WDT1_ACCSCSSBARK,
+ .end = INT_WDT1_ACCSCSSBARK,
+ .flags = IORESOURCE_IRQ,
+ },
};
struct platform_device fsm9xxx_device_watchdog = {
@@ -427,5 +436,7 @@
.dev = {
.platform_data = &fsm_watchdog_pdata,
},
+ .num_resources = ARRAY_SIZE(msm_watchdog_resources),
+ .resource = msm_watchdog_resources,
};
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 5402251..9f31a18 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -1996,6 +1996,15 @@
.pet_time = 10000,
.bark_time = 11000,
.has_secure = true,
+ .base = MSM_TMR0_BASE + WDT0_OFFSET,
+};
+
+static struct resource msm_watchdog_resources[] = {
+ {
+ .start = WDT0_ACCSCSSNBARK_INT,
+ .end = WDT0_ACCSCSSNBARK_INT,
+ .flags = IORESOURCE_IRQ,
+ },
};
struct platform_device msm8660_device_watchdog = {
@@ -2004,6 +2013,8 @@
.dev = {
.platform_data = &msm_watchdog_pdata,
},
+ .num_resources = ARRAY_SIZE(msm_watchdog_resources),
+ .resource = msm_watchdog_resources,
};
static struct resource msm_dmov_resource_adm0[] = {
@@ -2304,10 +2315,14 @@
#ifdef CONFIG_MSM_BUS_SCALING
.vidc_bus_client_pdata = &vidc_bus_client_data,
#endif
+#ifdef CONFIG_MSM_VIDC_CONTENT_PROTECTION
+ .cp_enabled = 1,
+#else
+ .cp_enabled = 0,
+#endif
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
.memtype = ION_CP_MM_HEAP_ID,
.enable_ion = 1,
- .cp_enabled = 1,
.secure_wb_heap = 1,
#else
.memtype = MEMTYPE_SMI_KERNEL,
diff --git a/arch/arm/mach-msm/msm_watchdog.c b/arch/arm/mach-msm/msm_watchdog.c
index b471426..aca7667 100644
--- a/arch/arm/mach-msm/msm_watchdog.c
+++ b/arch/arm/mach-msm/msm_watchdog.c
@@ -37,22 +37,23 @@
#define TCSR_WDT_CFG 0x30
-#define WDT0_RST 0x38
-#define WDT0_EN 0x40
-#define WDT0_STS 0x44
-#define WDT0_BARK_TIME 0x4C
-#define WDT0_BITE_TIME 0x5C
+#define WDT_RST 0x0
+#define WDT_EN 0x8
+#define WDT_STS 0xC
+#define WDT_BARK_TIME 0x14
+#define WDT_BITE_TIME 0x24
#define WDT_HZ 32768
struct msm_watchdog_dump msm_dump_cpu_ctx;
-static void __iomem *msm_tmr0_base;
+static void __iomem *msm_wdt_base;
static unsigned long delay_time;
static unsigned long bark_time;
static unsigned long long last_pet;
static bool has_vic;
+static unsigned int msm_wdog_irq;
/*
* On the kernel command line specify
@@ -116,8 +117,8 @@
if (!enable)
return 0;
- __raw_writel(1, msm_tmr0_base + WDT0_RST);
- __raw_writel(0, msm_tmr0_base + WDT0_EN);
+ __raw_writel(1, msm_wdt_base + WDT_RST);
+ __raw_writel(0, msm_wdt_base + WDT_EN);
mb();
return 0;
}
@@ -127,8 +128,8 @@
if (!enable)
return 0;
- __raw_writel(1, msm_tmr0_base + WDT0_EN);
- __raw_writel(1, msm_tmr0_base + WDT0_RST);
+ __raw_writel(1, msm_wdt_base + WDT_EN);
+ __raw_writel(1, msm_wdt_base + WDT_RST);
mb();
return 0;
}
@@ -137,14 +138,14 @@
unsigned long event, void *ptr)
{
if (panic_timeout == 0) {
- __raw_writel(0, msm_tmr0_base + WDT0_EN);
+ __raw_writel(0, msm_wdt_base + WDT_EN);
mb();
} else {
__raw_writel(WDT_HZ * (panic_timeout + 4),
- msm_tmr0_base + WDT0_BARK_TIME);
+ msm_wdt_base + WDT_BARK_TIME);
__raw_writel(WDT_HZ * (panic_timeout + 4),
- msm_tmr0_base + WDT0_BITE_TIME);
- __raw_writel(1, msm_tmr0_base + WDT0_RST);
+ msm_wdt_base + WDT_BITE_TIME);
+ __raw_writel(1, msm_wdt_base + WDT_RST);
}
return NOTIFY_DONE;
}
@@ -162,14 +163,14 @@
{
struct wdog_disable_work_data *work_data =
container_of(work, struct wdog_disable_work_data, work);
- __raw_writel(0, msm_tmr0_base + WDT0_EN);
+ __raw_writel(0, msm_wdt_base + WDT_EN);
mb();
if (has_vic) {
- free_irq(WDT0_ACCSCSSNBARK_INT, 0);
+ free_irq(msm_wdog_irq, 0);
} else {
- disable_percpu_irq(WDT0_ACCSCSSNBARK_INT);
+ disable_percpu_irq(msm_wdog_irq);
if (!appsbark_fiq) {
- free_percpu_irq(WDT0_ACCSCSSNBARK_INT,
+ free_percpu_irq(msm_wdog_irq,
percpu_pdata);
free_percpu(percpu_pdata);
}
@@ -178,7 +179,7 @@
atomic_notifier_chain_unregister(&panic_notifier_list, &panic_blk);
cancel_delayed_work(&dogwork_struct);
/* may be suspended after the first write above */
- __raw_writel(0, msm_tmr0_base + WDT0_EN);
+ __raw_writel(0, msm_wdt_base + WDT_EN);
complete(&work_data->complete);
pr_info("MSM Watchdog deactivated.\n");
}
@@ -229,11 +230,11 @@
if (!enable)
return;
- slack = __raw_readl(msm_tmr0_base + WDT0_STS) >> 3;
+ slack = __raw_readl(msm_wdt_base + WDT_STS) >> 3;
slack = ((bark_time*WDT_HZ)/1000) - slack;
if (slack < min_slack_ticks)
min_slack_ticks = slack;
- __raw_writel(1, msm_tmr0_base + WDT0_RST);
+ __raw_writel(1, msm_wdt_base + WDT_RST);
time_ns = sched_clock();
slack_ns = (last_pet + bark_time_ns) - time_ns;
if (slack_ns < min_slack_ns)
@@ -329,7 +330,7 @@
int ret;
if (has_vic) {
- ret = request_irq(WDT0_ACCSCSSNBARK_INT, wdog_bark_handler, 0,
+ ret = request_irq(msm_wdog_irq, wdog_bark_handler, 0,
"apps_wdog_bark", NULL);
if (ret)
return;
@@ -344,7 +345,7 @@
}
msm_wdog_fiq_setup(stack);
- gic_set_irq_secure(WDT0_ACCSCSSNBARK_INT);
+ gic_set_irq_secure(msm_wdog_irq);
} else {
percpu_pdata = alloc_percpu(struct msm_watchdog_pdata *);
if (!percpu_pdata) {
@@ -354,7 +355,7 @@
}
/* Must request irq before sending scm command */
- ret = request_percpu_irq(WDT0_ACCSCSSNBARK_INT,
+ ret = request_percpu_irq(msm_wdog_irq,
wdog_bark_handler, "apps_wdog_bark", percpu_pdata);
if (ret) {
free_percpu(percpu_pdata);
@@ -364,20 +365,20 @@
configure_bark_dump();
- __raw_writel(timeout, msm_tmr0_base + WDT0_BARK_TIME);
- __raw_writel(timeout + 3*WDT_HZ, msm_tmr0_base + WDT0_BITE_TIME);
+ __raw_writel(timeout, msm_wdt_base + WDT_BARK_TIME);
+ __raw_writel(timeout + 3*WDT_HZ, msm_wdt_base + WDT_BITE_TIME);
schedule_delayed_work_on(0, &dogwork_struct, delay_time);
atomic_notifier_chain_register(&panic_notifier_list,
&panic_blk);
- __raw_writel(1, msm_tmr0_base + WDT0_EN);
- __raw_writel(1, msm_tmr0_base + WDT0_RST);
+ __raw_writel(1, msm_wdt_base + WDT_EN);
+ __raw_writel(1, msm_wdt_base + WDT_RST);
last_pet = sched_clock();
if (!has_vic)
- enable_percpu_irq(WDT0_ACCSCSSNBARK_INT, IRQ_TYPE_EDGE_RISING);
+ enable_percpu_irq(msm_wdog_irq, IRQ_TYPE_EDGE_RISING);
printk(KERN_INFO "MSM Watchdog Initialized\n");
@@ -400,7 +401,8 @@
appsbark_fiq = pdata->use_kernel_fiq;
}
- msm_tmr0_base = msm_timer_get_timer0_base();
+ msm_wdt_base = pdata->base;
+ msm_wdog_irq = platform_get_irq(pdev, 0);
/*
* This is only temporary till SBLs turn on the XPUs
diff --git a/arch/arm/mach-msm/msm_watchdog.h b/arch/arm/mach-msm/msm_watchdog.h
index 00ff0b6..5fb82ee 100644
--- a/arch/arm/mach-msm/msm_watchdog.h
+++ b/arch/arm/mach-msm/msm_watchdog.h
@@ -13,6 +13,10 @@
#ifndef __ARCH_ARM_MACH_MSM_MSM_WATCHDOG_H
#define __ARCH_ARM_MACH_MSM_MSM_WATCHDOG_H
+/* The base is just address of the WDT_RST register */
+#define WDT0_OFFSET 0x38
+#define WDT1_OFFSET 0x60
+
struct msm_watchdog_pdata {
/* pet interval period in ms */
unsigned int pet_time;
@@ -23,6 +27,7 @@
bool has_vic;
/* You have to be running in secure mode to use FIQ */
bool use_kernel_fiq;
+ void __iomem *base;
};
struct msm_watchdog_dump {
diff --git a/arch/arm/mach-msm/pil-q6v5-lpass.c b/arch/arm/mach-msm/pil-q6v5-lpass.c
index 99223f2..44d8bc6 100644
--- a/arch/arm/mach-msm/pil-q6v5-lpass.c
+++ b/arch/arm/mach-msm/pil-q6v5-lpass.c
@@ -18,13 +18,56 @@
#include <linux/err.h>
#include <linux/of.h>
#include <linux/clk.h>
-
+#include <mach/clk.h>
#include "peripheral-loader.h"
#include "pil-q6v5.h"
#define QDSP6SS_RST_EVB 0x010
#define PROXY_TIMEOUT_MS 10000
+static int pil_lpass_enable_clks(struct q6v5_data *drv)
+{
+ int ret;
+
+ ret = clk_reset(drv->core_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ goto err_reset;
+ ret = clk_prepare_enable(drv->core_clk);
+ if (ret)
+ goto err_core_clk;
+ ret = clk_prepare_enable(drv->ahb_clk);
+ if (ret)
+ goto err_ahb_clk;
+ ret = clk_prepare_enable(drv->axi_clk);
+ if (ret)
+ goto err_axi_clk;
+ ret = clk_prepare_enable(drv->reg_clk);
+ if (ret)
+ goto err_reg_clk;
+
+ return 0;
+
+err_reg_clk:
+ clk_disable_unprepare(drv->axi_clk);
+err_axi_clk:
+ clk_disable_unprepare(drv->ahb_clk);
+err_ahb_clk:
+ clk_disable_unprepare(drv->core_clk);
+err_core_clk:
+ clk_reset(drv->core_clk, CLK_RESET_ASSERT);
+err_reset:
+ return ret;
+}
+
+static void pil_lpass_disable_clks(struct q6v5_data *drv)
+{
+ clk_disable_unprepare(drv->reg_clk);
+ clk_disable_unprepare(drv->axi_clk);
+ clk_disable_unprepare(drv->ahb_clk);
+ clk_disable_unprepare(drv->core_clk);
+ clk_reset(drv->core_clk, CLK_RESET_ASSERT);
+}
+
static int pil_lpass_shutdown(struct pil_desc *pil)
{
struct q6v5_data *drv = dev_get_drvdata(pil->dev);
@@ -37,10 +80,10 @@
* performed during the shutdown succeed.
*/
if (drv->is_booted == false)
- pil_q6v5_enable_clks(pil);
+ pil_lpass_enable_clks(drv);
pil_q6v5_shutdown(pil);
- pil_q6v5_disable_clks(pil);
+ pil_lpass_disable_clks(drv);
drv->is_booted = false;
@@ -52,7 +95,7 @@
struct q6v5_data *drv = dev_get_drvdata(pil->dev);
int ret;
- ret = pil_q6v5_enable_clks(pil);
+ ret = pil_lpass_enable_clks(drv);
if (ret)
return ret;
@@ -62,7 +105,7 @@
ret = pil_q6v5_reset(pil);
if (ret) {
- pil_q6v5_disable_clks(pil);
+ pil_lpass_disable_clks(drv);
return ret;
}
@@ -96,9 +139,21 @@
desc->owner = THIS_MODULE;
desc->proxy_timeout = PROXY_TIMEOUT_MS;
- drv->ss_clk = devm_clk_get(&pdev->dev, "reg_clk");
- if (IS_ERR(drv->ss_clk))
- return PTR_ERR(drv->ss_clk);
+ drv->core_clk = devm_clk_get(&pdev->dev, "core_clk");
+ if (IS_ERR(drv->core_clk))
+ return PTR_ERR(drv->core_clk);
+
+ drv->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(drv->ahb_clk))
+ return PTR_ERR(drv->ahb_clk);
+
+ drv->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
+ if (IS_ERR(drv->axi_clk))
+ return PTR_ERR(drv->axi_clk);
+
+ drv->reg_clk = devm_clk_get(&pdev->dev, "reg_clk");
+ if (IS_ERR(drv->reg_clk))
+ return PTR_ERR(drv->reg_clk);
drv->pil = msm_pil_register(desc);
if (IS_ERR(drv->pil))
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index 56be717..6a30940 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -74,6 +74,55 @@
return regulator_disable(drv->vreg);
}
+static int pil_mss_enable_clks(struct q6v5_data *drv)
+{
+ int ret;
+
+ ret = clk_prepare_enable(drv->ahb_clk);
+ if (ret)
+ goto err_ahb_clk;
+ ret = clk_reset(drv->core_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ goto err_reset;
+ ret = clk_prepare_enable(drv->core_clk);
+ if (ret)
+ goto err_core_clk;
+ ret = clk_prepare_enable(drv->axi_clk);
+ if (ret)
+ goto err_axi_clk;
+ ret = clk_prepare_enable(drv->reg_clk);
+ if (ret)
+ goto err_reg_clk;
+ ret = clk_prepare_enable(drv->rom_clk);
+ if (ret)
+ goto err_rom_clk;
+
+ return 0;
+
+err_rom_clk:
+ clk_disable_unprepare(drv->reg_clk);
+err_reg_clk:
+ clk_disable_unprepare(drv->axi_clk);
+err_axi_clk:
+ clk_disable_unprepare(drv->core_clk);
+err_core_clk:
+ clk_reset(drv->core_clk, CLK_RESET_ASSERT);
+err_reset:
+ clk_disable_unprepare(drv->ahb_clk);
+err_ahb_clk:
+ return ret;
+}
+
+static void pil_mss_disable_clks(struct q6v5_data *drv)
+{
+ clk_disable_unprepare(drv->rom_clk);
+ clk_disable_unprepare(drv->reg_clk);
+ clk_disable_unprepare(drv->axi_clk);
+ clk_disable_unprepare(drv->core_clk);
+ clk_reset(drv->core_clk, CLK_RESET_ASSERT);
+ clk_disable_unprepare(drv->ahb_clk);
+}
+
static int wait_for_mba_ready(struct device *dev)
{
struct q6v5_data *drv = dev_get_drvdata(dev);
@@ -123,11 +172,11 @@
*/
if (drv->is_booted == false) {
pil_mss_power_up(pil->dev);
- pil_q6v5_enable_clks(pil);
+ pil_mss_enable_clks(drv);
}
pil_q6v5_shutdown(pil);
- pil_q6v5_disable_clks(pil);
+ pil_mss_disable_clks(drv);
pil_mss_power_down(pil->dev);
writel_relaxed(1, drv->restart_reg);
@@ -155,7 +204,7 @@
if (ret)
goto err_power;
- ret = pil_q6v5_enable_clks(pil);
+ ret = pil_mss_enable_clks(drv);
if (ret)
goto err_clks;
@@ -190,7 +239,7 @@
err_auth:
pil_q6v5_shutdown(pil);
err_q6v5_reset:
- pil_q6v5_disable_clks(pil);
+ pil_mss_disable_clks(drv);
err_clks:
pil_mss_power_down(pil->dev);
err_power:
@@ -259,9 +308,25 @@
return ret;
}
- drv->ss_clk = devm_clk_get(&pdev->dev, "mem_clk");
- if (IS_ERR(drv->ss_clk))
- return PTR_ERR(drv->ss_clk);
+ drv->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(drv->ahb_clk))
+ return PTR_ERR(drv->ahb_clk);
+
+ drv->core_clk = devm_clk_get(&pdev->dev, "core_clk");
+ if (IS_ERR(drv->core_clk))
+ return PTR_ERR(drv->core_clk);
+
+ drv->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
+ if (IS_ERR(drv->axi_clk))
+ return PTR_ERR(drv->axi_clk);
+
+ drv->reg_clk = devm_clk_get(&pdev->dev, "reg_clk");
+ if (IS_ERR(drv->reg_clk))
+ return PTR_ERR(drv->reg_clk);
+
+ drv->rom_clk = devm_clk_get(&pdev->dev, "mem_clk");
+ if (IS_ERR(drv->rom_clk))
+ return PTR_ERR(drv->rom_clk);
drv->pil = msm_pil_register(desc);
if (IS_ERR(drv->pil))
diff --git a/arch/arm/mach-msm/pil-q6v5.c b/arch/arm/mach-msm/pil-q6v5.c
index d8d23c0..772031b 100644
--- a/arch/arm/mach-msm/pil-q6v5.c
+++ b/arch/arm/mach-msm/pil-q6v5.c
@@ -20,9 +20,7 @@
#include <linux/err.h>
#include <linux/of.h>
#include <linux/clk.h>
-
#include <mach/clk.h>
-
#include "peripheral-loader.h"
#include "pil-q6v5.h"
@@ -112,50 +110,6 @@
}
EXPORT_SYMBOL(pil_q6v5_init_image);
-int pil_q6v5_enable_clks(struct pil_desc *pil)
-{
- struct q6v5_data *drv = dev_get_drvdata(pil->dev);
- int ret;
-
- ret = clk_prepare_enable(drv->bus_clk);
- if (ret)
- goto err_bus_clk;
- if (drv->ss_clk) {
- ret = clk_prepare_enable(drv->ss_clk);
- if (ret)
- goto err_ss_clk;
- }
- ret = clk_reset(drv->core_clk, CLK_RESET_DEASSERT);
- if (ret)
- goto err_reset;
- ret = clk_prepare_enable(drv->core_clk);
- if (ret)
- goto err_core_clk;
-
- return 0;
-
-err_core_clk:
- clk_reset(drv->core_clk, CLK_RESET_ASSERT);
-err_reset:
- clk_disable_unprepare(drv->ss_clk);
-err_ss_clk:
- clk_disable_unprepare(drv->bus_clk);
-err_bus_clk:
- return ret;
-}
-EXPORT_SYMBOL(pil_q6v5_enable_clks);
-
-void pil_q6v5_disable_clks(struct pil_desc *pil)
-{
- struct q6v5_data *drv = dev_get_drvdata(pil->dev);
-
- clk_disable_unprepare(drv->core_clk);
- clk_reset(drv->core_clk, CLK_RESET_ASSERT);
- clk_disable_unprepare(drv->ss_clk);
- clk_disable_unprepare(drv->bus_clk);
-}
-EXPORT_SYMBOL(pil_q6v5_disable_clks);
-
void pil_q6v5_shutdown(struct pil_desc *pil)
{
u32 val;
@@ -277,14 +231,6 @@
if (IS_ERR(drv->xo))
return ERR_CAST(drv->xo);
- drv->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
- if (IS_ERR(drv->bus_clk))
- return ERR_CAST(drv->bus_clk);
-
- drv->core_clk = devm_clk_get(&pdev->dev, "core_clk");
- if (IS_ERR(drv->core_clk))
- return ERR_CAST(drv->core_clk);
-
desc->dev = &pdev->dev;
return desc;
diff --git a/arch/arm/mach-msm/pil-q6v5.h b/arch/arm/mach-msm/pil-q6v5.h
index 6985360..03f93fa 100644
--- a/arch/arm/mach-msm/pil-q6v5.h
+++ b/arch/arm/mach-msm/pil-q6v5.h
@@ -21,10 +21,12 @@
struct q6v5_data {
void __iomem *reg_base;
- struct clk *xo;
- struct clk *bus_clk;
- struct clk *core_clk;
- struct clk *ss_clk;
+ struct clk *xo; /* XO clock source */
+ struct clk *ahb_clk; /* PIL access to registers */
+ struct clk *axi_clk; /* CPU access to memory */
+ struct clk *core_clk; /* CPU core */
+ struct clk *reg_clk; /* CPU access registers */
+ struct clk *rom_clk; /* Boot ROM */
void __iomem *axi_halt_base;
void __iomem *rmb_base;
void __iomem *restart_reg;
@@ -43,8 +45,6 @@
size_t size);
void pil_q6v5_shutdown(struct pil_desc *pil);
int pil_q6v5_reset(struct pil_desc *pil);
-int pil_q6v5_enable_clks(struct pil_desc *pil);
-void pil_q6v5_disable_clks(struct pil_desc *pil);
struct pil_desc *pil_q6v5_init(struct platform_device *pdev);
#endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 2749098..28b7748 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -120,6 +120,29 @@
return 0;
}
+static int __cpuinit krait_release_secondary_p3(unsigned long base, int cpu)
+{
+ void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
+ if (!base_ptr)
+ return -ENODEV;
+
+ writel_relaxed(0x021, base_ptr+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x020, base_ptr+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x000, base_ptr+0x04);
+ mb();
+
+ writel_relaxed(0x080, base_ptr+0x04);
+ mb();
+ iounmap(base_ptr);
+ return 0;
+}
+
static int __cpuinit release_secondary(unsigned int cpu)
{
BUG_ON(cpu >= get_core_count());
@@ -134,6 +157,9 @@
cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab())
return krait_release_secondary(0x02088000, cpu);
+ if (cpu_is_msm8974())
+ return krait_release_secondary_p3(0xf9088000, cpu);
+
WARN(1, "unknown CPU case in release_secondary\n");
return -EINVAL;
}
diff --git a/drivers/gpio/qpnp-pin.c b/drivers/gpio/qpnp-pin.c
index bbcba81..ccbbd67 100644
--- a/drivers/gpio/qpnp-pin.c
+++ b/drivers/gpio/qpnp-pin.c
@@ -46,10 +46,10 @@
/* mpp peripheral type and subtype values */
#define Q_MPP_TYPE 0x11
-#define Q_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x1
-#define Q_MPP_SUBTYPE_4CH_NO_SINK 0x2
-#define Q_MPP_SUBTYPE_4CH_FULL_FUNC 0x3
-#define Q_MPP_SUBTYPE_8CH_FULL_FUNC 0x7
+#define Q_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
+#define Q_MPP_SUBTYPE_4CH_NO_SINK 0x5
+#define Q_MPP_SUBTYPE_4CH_FULL_FUNC 0x2
+#define Q_MPP_SUBTYPE_8CH_FULL_FUNC 0x4
/* control register base address offsets */
#define Q_REG_MODE_CTL 0x40
diff --git a/drivers/input/misc/mpu3050.c b/drivers/input/misc/mpu3050.c
index 8b6e172..d3da652 100644
--- a/drivers/input/misc/mpu3050.c
+++ b/drivers/input/misc/mpu3050.c
@@ -40,6 +40,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
+#include <linux/gpio.h>
#include <linux/input/mpu3050.h>
#include <linux/regulator/consumer.h>
@@ -50,6 +51,8 @@
#define MPU3050_MIN_VALUE -32768
#define MPU3050_MAX_VALUE 32767
+#define MPU3050_MIN_POLL_INTERVAL 1
+#define MPU3050_MAX_POLL_INTERVAL 250
#define MPU3050_DEFAULT_POLL_INTERVAL 200
#define MPU3050_DEFAULT_FS_RANGE 3
@@ -90,8 +93,10 @@
#define MPU3050_DLPF_CFG_MASK 0x07
/* INT_CFG */
#define MPU3050_RAW_RDY_EN 0x01
-#define MPU3050_MPU_RDY_EN 0x02
-#define MPU3050_LATCH_INT_EN 0x04
+#define MPU3050_MPU_RDY_EN 0x04
+#define MPU3050_LATCH_INT_EN 0x20
+#define MPU3050_OPEN_DRAIN 0x40
+#define MPU3050_ACTIVE_LOW 0x80
/* PWR_MGM */
#define MPU3050_PWR_MGM_PLL_X 0x01
#define MPU3050_PWR_MGM_PLL_Y 0x02
@@ -117,6 +122,7 @@
struct mpu3050_gyro_platform_data *platform_data;
struct delayed_work input_work;
u32 use_poll;
+ u32 poll_interval;
};
struct sensor_regulator {
@@ -190,6 +196,78 @@
}
/**
+ * mpu3050_attr_get_polling_rate - get the sampling rate
+ */
+static ssize_t mpu3050_attr_get_polling_rate(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int val;
+ struct mpu3050_sensor *sensor = dev_get_drvdata(dev);
+ val = sensor ? sensor->poll_interval : 0;
+ return snprintf(buf, 8, "%d\n", val);
+}
+
+/**
+ * mpu3050_attr_set_polling_rate - set the sampling rate
+ */
+static ssize_t mpu3050_attr_set_polling_rate(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct mpu3050_sensor *sensor = dev_get_drvdata(dev);
+ unsigned long interval_ms;
+
+ if (kstrtoul(buf, 10, &interval_ms))
+ return -EINVAL;
+ if ((interval_ms < MPU3050_MIN_POLL_INTERVAL) ||
+ (interval_ms > MPU3050_MAX_POLL_INTERVAL))
+ return -EINVAL;
+
+ if (sensor)
+ sensor->poll_interval = interval_ms;
+
+ /* Output frequency divider. The poll interval */
+ i2c_smbus_write_byte_data(sensor->client, MPU3050_SMPLRT_DIV,
+ interval_ms - 1);
+
+ return size;
+}
+
+static struct device_attribute attributes[] = {
+
+ __ATTR(pollrate_ms, 0666,
+ mpu3050_attr_get_polling_rate,
+ mpu3050_attr_set_polling_rate),
+};
+
+static int create_sysfs_interfaces(struct device *dev)
+{
+ int i;
+ int err;
+ for (i = 0; i < ARRAY_SIZE(attributes); i++) {
+ err = device_create_file(dev, attributes + i);
+ if (err)
+ goto error;
+ }
+ return 0;
+
+error:
+ for ( ; i >= 0; i--)
+ device_remove_file(dev, attributes + i);
+ dev_err(dev, "%s:Unable to create interface\n", __func__);
+ return err;
+}
+
+static int remove_sysfs_interfaces(struct device *dev)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(attributes); i++)
+ device_remove_file(dev, attributes + i);
+ return 0;
+}
+
+/**
* mpu3050_xyz_read_reg - read the axes values
* @buffer: provide register addr and get register
* @length: length of register
@@ -284,20 +362,20 @@
struct mpu3050_sensor *sensor = input_get_drvdata(input);
int error;
- pm_runtime_get(sensor->dev);
+ pm_runtime_get_sync(sensor->dev);
/* Enable interrupts */
error = i2c_smbus_write_byte_data(sensor->client, MPU3050_INT_CFG,
- MPU3050_LATCH_INT_EN |
- MPU3050_RAW_RDY_EN |
- MPU3050_MPU_RDY_EN);
+ MPU3050_ACTIVE_LOW |
+ MPU3050_OPEN_DRAIN |
+ MPU3050_RAW_RDY_EN);
if (error < 0) {
pm_runtime_put(sensor->dev);
return error;
}
if (sensor->use_poll)
schedule_delayed_work(&sensor->input_work,
- msecs_to_jiffies(MPU3050_DEFAULT_POLL_INTERVAL));
+ msecs_to_jiffies(sensor->poll_interval));
return 0;
}
@@ -366,7 +444,7 @@
if (sensor->use_poll)
schedule_delayed_work(&sensor->input_work,
- msecs_to_jiffies(MPU3050_DEFAULT_POLL_INTERVAL));
+ msecs_to_jiffies(sensor->poll_interval));
}
/**
@@ -399,7 +477,7 @@
/* Output frequency divider. The poll interval */
ret = i2c_smbus_write_byte_data(client, MPU3050_SMPLRT_DIV,
- MPU3050_DEFAULT_POLL_INTERVAL - 1);
+ sensor->poll_interval - 1);
if (ret < 0)
return ret;
@@ -444,6 +522,18 @@
sensor->dev = &client->dev;
sensor->idev = idev;
sensor->platform_data = client->dev.platform_data;
+ i2c_set_clientdata(client, sensor);
+ if (sensor->platform_data) {
+ u32 interval = sensor->platform_data->poll_interval;
+
+ if ((interval < MPU3050_MIN_POLL_INTERVAL) ||
+ (interval > MPU3050_MAX_POLL_INTERVAL))
+ sensor->poll_interval = MPU3050_DEFAULT_POLL_INTERVAL;
+ else
+ sensor->poll_interval = interval;
+ } else {
+ sensor->poll_interval = MPU3050_DEFAULT_POLL_INTERVAL;
+ }
mpu3050_set_power_mode(client, 1);
msleep(10);
@@ -485,14 +575,34 @@
goto err_pm_set_suspended;
if (client->irq == 0) {
- INIT_DELAYED_WORK(&sensor->input_work, mpu3050_input_work_fn);
sensor->use_poll = 1;
+ INIT_DELAYED_WORK(&sensor->input_work, mpu3050_input_work_fn);
} else {
sensor->use_poll = 0;
+ if (gpio_is_valid(sensor->platform_data->gpio_int)) {
+ /* configure interrupt gpio */
+ ret = gpio_request(sensor->platform_data->gpio_int,
+ "gyro_gpio_int");
+ if (ret) {
+ pr_err("%s: unable to request interrupt gpio %d\n",
+ __func__,
+ sensor->platform_data->gpio_int);
+ goto err_pm_set_suspended;
+ }
+
+ ret = gpio_direction_input(
+ sensor->platform_data->gpio_int);
+ if (ret) {
+ pr_err("%s: unable to set direction for gpio %d\n",
+ __func__, sensor->platform_data->gpio_int);
+ goto err_free_gpio;
+ }
+ }
+
error = request_threaded_irq(client->irq,
NULL, mpu3050_interrupt_thread,
- IRQF_TRIGGER_RISING,
+ IRQF_TRIGGER_FALLING,
"mpu3050", sensor);
if (error) {
dev_err(&client->dev,
@@ -508,14 +618,26 @@
goto err_free_irq;
}
+ error = create_sysfs_interfaces(&client->dev);
+ if (error < 0) {
+ dev_err(&client->dev, "failed to create sysfs\n");
+ goto err_input_cleanup;
+ }
+
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, MPU3050_AUTO_DELAY);
return 0;
+err_input_cleanup:
+ input_unregister_device(idev);
err_free_irq:
if (client->irq > 0)
free_irq(client->irq, sensor);
+err_free_gpio:
+ if ((client->irq > 0) &&
+ (gpio_is_valid(sensor->platform_data->gpio_int)))
+ gpio_free(sensor->platform_data->gpio_int);
err_pm_set_suspended:
pm_runtime_set_suspended(&client->dev);
err_free_mem:
@@ -537,8 +659,12 @@
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
- free_irq(client->irq, sensor);
+ if (client->irq)
+ free_irq(client->irq, sensor);
+
+ remove_sysfs_interfaces(&client->dev);
input_unregister_device(sensor->idev);
+
kfree(sensor);
return 0;
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tsif.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tsif.c
index bd1ecfe..74a0dbe 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tsif.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tsif.c
@@ -26,8 +26,8 @@
#define DMX_TSIF_MAX_SECTION_FILTER_NUM 64
/* When TSIF driver notifies demux that new packets are received */
-#define DMX_TSIF_PACKETS_IN_CHUNK_DEF 16
-#define DMX_TSIF_CHUNKS_IN_BUF 8
+#define DMX_TSIF_PACKETS_IN_CHUNK_DEF 512
+#define DMX_TSIF_CHUNKS_IN_BUF 16
#define DMX_TSIF_TIME_LIMIT 10000
/* TSIF_DRIVER_MODE: 3 means manual control from debugfs. use 1 normally. */
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c
index fd94e80..372c612 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c
@@ -47,18 +47,20 @@
#define TSPP_RAW_TTS_SIZE 192
-/* Size of single descriptor.
- * Assuming 20MBit/sec stream, with 200 packets
- * per descriptor there would be about 68 descriptors.
- * Meanning about 68 interrupts per second.
+/* Size of single descriptor. Using max descriptor size (170 packets).
+ * Assuming 20MBit/sec stream, with 170 packets
+ * per descriptor there would be about 82 descriptors,
+ * Meanning about 82 notifications per second.
*/
-#define TSPP_BUFFER_SIZE (TSPP_RAW_TTS_SIZE * 200)
+#define MAX_BAM_DESCRIPTOR_SIZE (32*1024 - 1)
+#define TSPP_BUFFER_SIZE \
+ ((MAX_BAM_DESCRIPTOR_SIZE / TSPP_RAW_TTS_SIZE) * TSPP_RAW_TTS_SIZE)
/* Number of descriptors, total size: TSPP_BUFFER_SIZE*TSPP_BUFFER_COUNT */
-#define TSPP_BUFFER_COUNT (16)
+#define TSPP_BUFFER_COUNT (32)
/* When TSPP notifies demux that new packets are received */
-#define TSPP_NOTIFICATION_SIZE (TSPP_RAW_TTS_SIZE * 100)
+#define TSPP_NOTIFICATION_SIZE 1
/* Channel timeout in msec */
#define TSPP_CHANNEL_TIMEOUT 16
@@ -232,7 +234,7 @@
* @channel_id: Channel with new TS packets
* @user: user-data holding TSIF number
*/
-static void mpq_tspp_callback(u32 channel_id, void *user)
+static void mpq_tspp_callback(int channel_id, void *user)
{
int tsif = (int)user;
struct work_struct *work;
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index b2d2f74..d082273 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -75,7 +75,7 @@
config THERMAL_MONITOR
bool "Monitor thermal state and limit CPU Frequency"
- depends on THERMAL_TSENS8960
+ depends on THERMAL_TSENS8960 || THERMAL_TSENS8974
depends on CPU_FREQ_MSM
default n
help
diff --git a/drivers/usb/gadget/f_rmnet.c b/drivers/usb/gadget/f_rmnet.c
index 414a7b9..1d0b6d4 100644
--- a/drivers/usb/gadget/f_rmnet.c
+++ b/drivers/usb/gadget/f_rmnet.c
@@ -607,6 +607,7 @@
struct usb_cdc_notification *event;
unsigned long flags;
int ret;
+ struct rmnet_ctrl_pkt *cpkt;
pr_debug("%s:dev:%p portno#%d\n", __func__, dev, dev->port_num);
@@ -633,6 +634,14 @@
ret = usb_ep_queue(dev->notify, dev->notify_req, GFP_ATOMIC);
if (ret) {
atomic_dec(&dev->notify_count);
+ spin_lock_irqsave(&dev->lock, flags);
+ cpkt = list_first_entry(&dev->cpkt_resp_q,
+ struct rmnet_ctrl_pkt, list);
+ if (cpkt) {
+ list_del(&cpkt->list);
+ rmnet_free_ctrl_pkt(cpkt);
+ }
+ spin_unlock_irqrestore(&dev->lock, flags);
pr_debug("ep enqueue error %d\n", ret);
}
}
@@ -768,6 +777,8 @@
{
struct f_rmnet *dev = req->context;
int status = req->status;
+ unsigned long flags;
+ struct rmnet_ctrl_pkt *cpkt;
pr_debug("%s: dev:%p port#%d\n", __func__, dev, dev->port_num);
@@ -790,6 +801,14 @@
status = usb_ep_queue(dev->notify, req, GFP_ATOMIC);
if (status) {
atomic_dec(&dev->notify_count);
+ spin_lock_irqsave(&dev->lock, flags);
+ cpkt = list_first_entry(&dev->cpkt_resp_q,
+ struct rmnet_ctrl_pkt, list);
+ if (cpkt) {
+ list_del(&cpkt->list);
+ rmnet_free_ctrl_pkt(cpkt);
+ }
+ spin_unlock_irqrestore(&dev->lock, flags);
pr_debug("ep enqueue error %d\n", status);
}
break;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
index d45de2d..d83cde8 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
@@ -897,7 +897,7 @@
VIDC_SM_EXTENDED_PAR_HEIGHT_SHFT);
break;
default:
- DDL_MSG_ERROR("Incorrect Aspect Ratio.");
+ DDL_MSG_HIGH("Incorrect Aspect Ratio.");
aspect_ratio_info->par_width = 1;
aspect_ratio_info->par_height = 1;
break;
@@ -955,7 +955,7 @@
VIDC_SM_EXTENDED_PAR_HEIGHT_SHFT);
break;
default:
- DDL_MSG_ERROR("Incorrect Aspect Ratio.");
+ DDL_MSG_HIGH("Incorrect Aspect Ratio.");
aspect_ratio_info->par_width = 1;
aspect_ratio_info->par_height = 1;
break;
diff --git a/drivers/video/msm/vidc/Kconfig b/drivers/video/msm/vidc/Kconfig
index 9ffcb15..7820e53 100644
--- a/drivers/video/msm/vidc/Kconfig
+++ b/drivers/video/msm/vidc/Kconfig
@@ -37,3 +37,7 @@
help
This option enables support for Video decoder.
+config MSM_VIDC_CONTENT_PROTECTION
+ bool "Enable Content Protection"
+ help
+ Enable content protection feature for Video.
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 59cb45b..4758829 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -35,6 +35,10 @@
#include <linux/gpio.h>
#include "wcd9310.h"
+static int cfilt_adjust_ms = 10;
+module_param(cfilt_adjust_ms, int, 0644);
+MODULE_PARM_DESC(cfilt_adjust_ms, "delay after adjusting cfilt voltage in ms");
+
#define WCD9310_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
@@ -2240,26 +2244,26 @@
}
snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
- if (!tabla->no_mic_headset_override) {
- if (mbhc_state == MBHC_STATE_POTENTIAL) {
- pr_debug("%s recovering MBHC state macine\n", __func__);
- tabla->mbhc_state = MBHC_STATE_POTENTIAL_RECOVERY;
- /* set to max button press threshold */
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL,
- 0x7F);
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL,
- 0xFF);
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL,
- (TABLA_IS_1_X(tabla_core->version) ?
- 0x07 : 0x7F));
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL,
- 0xFF);
- /* set to max */
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL,
- 0x7F);
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL,
- 0xFF);
- }
+ if (tabla->no_mic_headset_override) {
+ pr_debug("%s setting button threshold to min", __func__);
+ /* set to min */
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL, 0x80);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0x00);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL, 0x80);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL, 0x00);
+ } else if (unlikely(mbhc_state == MBHC_STATE_POTENTIAL)) {
+ pr_debug("%s recovering MBHC state machine\n", __func__);
+ tabla->mbhc_state = MBHC_STATE_POTENTIAL_RECOVERY;
+ /* set to max button press threshold */
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL, 0x7F);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL, 0xFF);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL,
+ (TABLA_IS_1_X(tabla_core->version) ?
+ 0x07 : 0x7F));
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0xFF);
+ /* set to max */
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL, 0x7F);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL, 0xFF);
}
snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x1);
@@ -2479,11 +2483,11 @@
cfilt_k_val = tabla_find_k_value(
tabla->pdata->micbias.ldoh_v,
VDDIO_MICBIAS_MV);
- usleep_range(10000, 10000);
snd_soc_update_bits(codec,
tabla->mbhc_bias_regs.cfilt_val,
0xFC, (cfilt_k_val << 2));
- usleep_range(10000, 10000);
+ usleep_range(cfilt_adjust_ms * 1000,
+ cfilt_adjust_ms * 1000);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL,
tabla->mbhc_data.adj_v_ins_hu & 0xFF);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL,
@@ -2517,7 +2521,8 @@
snd_soc_update_bits(codec,
tabla->mbhc_bias_regs.cfilt_val,
0xFC, (cfilt_k_val << 2));
- usleep_range(10000, 10000);
+ usleep_range(cfilt_adjust_ms * 1000,
+ cfilt_adjust_ms * 1000);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL,
tabla->mbhc_data.v_ins_hu & 0xFF);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL,
@@ -7777,9 +7782,15 @@
lbuf[cnt] = '\0';
buf = (char *)lbuf;
- tabla->no_mic_headset_override = (*strsep(&buf, " ") == '0') ?
- false : true;
- return rc;
+ TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
+ tabla->no_mic_headset_override =
+ (*strsep(&buf, " ") == '0') ? false : true;
+ if (tabla->no_mic_headset_override && tabla->mbhc_polling_active) {
+ tabla_codec_pause_hs_polling(tabla->codec);
+ tabla_codec_start_hs_polling(tabla->codec);
+ }
+ TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
+ return cnt;
}
static ssize_t codec_mbhc_debug_read(struct file *file, char __user *buf,