mmc: require explicit support for high-speed
The new high-speed timings are similar to each other and the old
system, but not identical. And although things "just work" most of
the time, sometimes it does not. So we need to start marking which
hosts are known to fully comply with the new timings.
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 7522f76..c52b167 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -606,7 +606,6 @@
static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
int div;
- u8 ctrl;
u16 clk;
unsigned long timeout;
@@ -615,13 +614,6 @@
writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
- ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
- if (clock > 25000000)
- ctrl |= SDHCI_CTRL_HISPD;
- else
- ctrl &= ~SDHCI_CTRL_HISPD;
- writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
-
if (clock == 0)
goto out;
@@ -761,10 +753,17 @@
sdhci_set_power(host, ios->vdd);
ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
+
if (ios->bus_width == MMC_BUS_WIDTH_4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
+
+ if (ios->timing == MMC_TIMING_SD_HS)
+ ctrl |= SDHCI_CTRL_HISPD;
+ else
+ ctrl &= ~SDHCI_CTRL_HISPD;
+
writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
mmiowb();
@@ -1274,6 +1273,9 @@
mmc->f_max = host->max_clk;
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
+ if (caps & SDHCI_CAN_DO_HISPD)
+ mmc->caps |= MMC_CAP_SD_HIGHSPEED;
+
mmc->ocr_avail = 0;
if (caps & SDHCI_CAN_VDD_330)
mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
@@ -1282,13 +1284,6 @@
if (caps & SDHCI_CAN_VDD_180)
mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
- if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
- printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
- " but no high speed support.\n",
- host->slot_descr);
- mmc->f_max = 25000000;
- }
-
if (mmc->ocr_avail == 0) {
printk(KERN_ERR "%s: Hardware doesn't report any "
"support voltages.\n", host->slot_descr);