mmc: msm_sdcc: fix data timeout calculation for DDR bus speed mode
When card operates in DDR (Double Data Rate) bus speed mode,
most of the HW logic of SDCC controller needs to have clock
frequency that is twice the clock frequency going out to card.
For example, if a card operates at 50MHz clock in DDR mode then
internally SDCC controller logic will operate at a clock of 100MHz.
But SDCC controller's data timeout logic works on the clock rate
that actually goes to card. So this change calculates the data
timeout value based on the clock frequency that goes to card rather
than SDCC controller's clock frequency.
CRs-Fixed: 450675
Change-Id: I3ef48ae070678c203fded8a8bf13dc5d01518f1a
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
1 file changed