| commit | d0ba3922ae241a87d22a1c3ffad72b96fe993c9a | [log] [tgz] |
|---|---|---|
| author | Paul Walmsley <paul@pwsan.com> | Fri Jun 19 19:08:27 2009 -0600 |
| committer | paul <paul@twilight.(none)> | Fri Jun 19 19:09:31 2009 -0600 |
| tree | 3f23d60fbbf2ffceef44b01c8579db7be7d20025 | |
| parent | c9812d042a21eb492a36cfabf9f41107f5ecee3d [diff] |
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>