msm: acpuclock-8960: Apply alternate 8064 workaround for Krait errata
8064v1.x hardware has a known issue where the CPU's primary and secondary
clock source muxes reset to their default states when the L2 cache is
power-collapsed. To work around this, software sets these muxes to their
default positions (QSB selected) before L2 power-collapse so that software
state remains in sync with the hardware.
Replace this workaround with an improved one that incurs less of a latency
penalty in the hotplug path (since selecting the slow QSB source may slow
down hotplug). The improved workaround targets the root of the problem,
which is that the L2CPUVRF8 CP15 register becomes corrupt when L2CPMR or
L2CPUCPMR are written to. It is this corruption that results in the
change in L2 power-collapse behaviour and the muxes getting reset.
Implement the improved workaround, which saves and restores L2CPUVRF8's
value around L2CPMR and L2CPUCPMR writes. Although the register is still
corrupt for a short period of time before the register is restored, this
is of no consequence since L2 power-collapse cannot happen at that time.
Change-Id: I3ac13f286ac903d5f974bf735ebf287d9413216b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
2 files changed