commit d464ab17154599a8b8fc8921da4ab92a413c5a0b
author Taniya Das <tdas@codeaurora.org> Tue Apr 08 12:35:27 2014 +0530
committer Taniya Das <tdas@codeaurora.org> Wed Apr 16 14:39:26 2014 +0530
tree d5318eb793349fa6143912028ad4e996bb04e638
parent 9a286e0721f475ae41624e2bc132218089535ee3

ARM: dts: msm: Limit DDR to 200MHz for APSS freVquency

For APSS frequency of 787MHz, DDR frequency still required to be at SVS of
BIMC frequency.

CRs-Fixed: 644461
Change-Id: If129291f544adec30792ca20bfbfefb44141ef53
Signed-off-by: Taniya Das <tdas@codeaurora.org>

arch/arm/boot/dts/msm8226.dtsi

diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index 993da79..2599c46 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -1061,7 +1061,7 @@
 			<  300000 1525 >,
 			<  384000 1525 >,
 			<  600000 1525 >,
-			<  787200 3051 >,
+			<  787200 1525 >,
 			<  998400 4066 >,
 			< 1094400 4066 >,
 			< 1190400 4066 >,