Merge "ASoC: msm: Default format for the compressed driver as LPCM" into msm-3.4
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index f082a0f..0eb186e 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -202,3 +202,55 @@
qcom,msm-ocmem-audio-ib = <471859200>;
};
+* MSM8974 ASoC Machine driver
+
+Required properties:
+- compatible : "qcom,msm8974-audio-taiko"
+- qcom,model : The user-visible name of this sound card.
+- qcom,audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source.
+- qcom,cdc-mclk-gpios : GPIO on which mclk signal is comming.
+- taiko-mclk-clk : phandle to PMIC8941 clkdiv1 node.
+- qcom,taiko-mclk-clk-freq : Taiko mclk Freq in Hz. currently only 9600000Hz
+ is supported.
+
+Example:
+
+sound {
+ compatible = "qcom,msm8974-audio-taiko";
+ qcom,model = "msm8974-taiko-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "HEADPHONE", "LDO_H",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS3 Internal1",
+ "MIC BIAS3 Internal1", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS1 Internal2",
+ "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+
+ qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>;
+ taiko-mclk-clk = <&pm8941_clkdiv1>;
+ qcom,taiko-mclk-clk-freq = <9600000>;
+};
diff --git a/arch/arm/boot/dts/mpq8092-sim.dts b/arch/arm/boot/dts/mpq8092-sim.dts
new file mode 100644
index 0000000..f73abe7
--- /dev/null
+++ b/arch/arm/boot/dts/mpq8092-sim.dts
@@ -0,0 +1,49 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "Qualcomm MPQ8092 Simulator";
+ compatible = "qcom,mpq8092-sim", "qcom,mpq8092";
+ interrupt-parent = <&intc>;
+
+ intc: interrupt-controller@f9000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xf9000000 0x1000>,
+ <0xf9002000 0x1000>;
+ };
+
+ timer {
+ compatible = "qcom,msm-qtimer", "arm,armv7-timer";
+ interrupts = <1 2 0>, <1 3 0>;
+ clock-frequency = <19200000>;
+ };
+
+ serial@f991f000 {
+ compatible = "qcom,msm-lsuart-v14";
+ reg = <0xf991f000 0x1000>;
+ interrupts = <0 109 0>;
+ };
+
+ serial@f995e000 {
+ compatible = "qcom,msm-lsuart-v14";
+ reg = <0xf995e000 0x1000>;
+ interrupts = <0 114 0>;
+ };
+
+};
+
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index 030d0e3..6347b51 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -750,5 +750,66 @@
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
+
+ qcom,leds@d800 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd800 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@d900 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd900 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@da00 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xda00 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@db00 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xdb00 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@dc00 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xdc00 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@dd00 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xdd00 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@de00 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xde00 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@df00 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xdf00 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@e000 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xe000 0x100>;
+ qcom,label = "wled";
+ };
+
+ qcom,leds@e100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xe100 0x100>;
+ qcom,label = "wled";
+ };
+
};
};
diff --git a/arch/arm/boot/dts/msm8974-clock.dtsi b/arch/arm/boot/dts/msm8974-clock.dtsi
index bdc5d9b..043346f 100644
--- a/arch/arm/boot/dts/msm8974-clock.dtsi
+++ b/arch/arm/boot/dts/msm8974-clock.dtsi
@@ -15,6 +15,7 @@
qcom,pm8941@0 {
pm8941_clkdiv1: clkdiv@5b00 {
+ qcom,cxo-div = <2>;
};
pm8941_clkdiv2: clkdiv@5c00 {
diff --git a/arch/arm/boot/dts/msm8974-gpio.dtsi b/arch/arm/boot/dts/msm8974-gpio.dtsi
index b36859e..caea36c 100644
--- a/arch/arm/boot/dts/msm8974-gpio.dtsi
+++ b/arch/arm/boot/dts/msm8974-gpio.dtsi
@@ -86,6 +86,13 @@
gpio@ce00 {
status = "ok";
+ qcom,mode = <1>;
+ qcom,output-type = <0>;
+ qcom,pull = <5>;
+ qcom,vin-sel = <2>;
+ qcom,out-strength = <3>;
+ qcom,src-select = <2>;
+ qcom,master-en = <1>;
};
gpio@cf00 {
diff --git a/arch/arm/boot/dts/msm8974-mdss.dtsi b/arch/arm/boot/dts/msm8974-mdss.dtsi
index dbaa492..0382021 100644
--- a/arch/arm/boot/dts/msm8974-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8974-mdss.dtsi
@@ -29,6 +29,30 @@
vreg-supply = <&pm8941_l2>;
};
+ qcom,hdmi_tx@fd922100 {
+ cell-index = <0>;
+ compatible = "qcom,hdmi-tx";
+ reg = <0xfd922100 0x35C>,
+ <0xfd922500 0x7C>,
+ <0xfc4b8000 0x60F0>;
+ reg-names = "core_physical", "phy_physical", "qfprom_physical";
+
+ hpd-5v-supply = <&pm8941_mvs2>;
+ core-vdda-supply = <&pm8941_l12>;
+ core-vcc-supply = <&pm8941_s3>;
+ qcom,hdmi-tx-supply-names = "hpd-5v", "core-vdda", "core-vcc";
+ qcom,hdmi-tx-supply-type = <0 1 1>;
+ qcom,hdmi-tx-min-voltage-level = <0 1800000 1800000>;
+ qcom,hdmi-tx-max-voltage-level = <0 1800000 1800000>;
+ qcom,hdmi-tx-op-mode = <0 1800000 0>;
+
+ gpios = <&msmgpio 31 0>,
+ <&msmgpio 32 0>,
+ <&msmgpio 33 0>,
+ <&msmgpio 34 0>;
+ qcom,hdmi-tx-gpio-names = "cec-pin", "hpd-ddc-clk", "hpd-ddc-data", "hpd-pin";
+ };
+
qcom,mdss_wb_panel {
compatible = "qcom,mdss_wb";
qcom,mdss_pan_res = <640 480>;
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index d67c42f..fcc5070 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -55,11 +55,9 @@
vidc-cp-map = <0x1000000 0x40000000>;
vidc-ns-map = <0x40000000 0x40000000>;
load-freq-tbl = <979200 410000000>,
- <560145 266670000>,
- <421161 200000000>,
- <243000 133330000>,
- <108000 100000000>,
- <36000 50000000>;
+ <783360 410000000>,
+ <489000 266670000>,
+ <244800 133330000>;
};
serial@f991f000 {
@@ -281,6 +279,44 @@
};
};
+ sound {
+ compatible = "qcom,msm8974-audio-taiko";
+ qcom,model = "msm8974-taiko-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "HEADPHONE", "LDO_H",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS3 Internal1",
+ "MIC BIAS3 Internal1", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS1 Internal2",
+ "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+
+ qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>;
+ taiko-mclk-clk = <&pm8941_clkdiv1>;
+ qcom,taiko-mclk-clk-freq = <9600000>;
+ };
+
spmi_bus: qcom,spmi@fc4c0000 {
cell-index = <0>;
compatible = "qcom,spmi-pmic-arb";
@@ -427,6 +463,60 @@
<0x1e50008a>, /* LPG_CHAN10 */
<0x1e60008b>, /* LPG_CHAN11 */
<0x1e70008c>; /* LPG_CHAN12 */
+
+ qcom,pm8941@1 {
+ qcom,leds@d800 {
+ qcom,name = "wled:backlight";
+ linux,default-trigger = "bkl-trigger";
+ qcom,cs-out-en;
+ qcom,op-fdbck;
+ qcom,default-state = "on";
+ qcom,max-current = <25>;
+ qcom,ctrl-delay-us = <0>;
+ qcom,boost-curr-lim = <3>;
+ qcom,cp-sel = <0>;
+ qcom,switch-freq = <2>;
+ qcom,ovp-val = <2>;
+ qcom,num-strings = <1>;
+ status = "okay";
+ };
+
+ qcom,leds@d900 {
+ status = "disabled";
+ };
+
+ qcom,leds@da00 {
+ status = "disabled";
+ };
+
+ qcom,leds@db00 {
+ status = "disabled";
+ };
+
+ qcom,leds@dc00 {
+ status = "disabled";
+ };
+
+ qcom,leds@dd00 {
+ status = "disabled";
+ };
+
+ qcom,leds@de00 {
+ status = "disabled";
+ };
+
+ qcom,leds@df00 {
+ status = "disabled";
+ };
+
+ qcom,leds@e000 {
+ status = "disabled";
+ };
+
+ qcom,leds@e100 {
+ status = "disabled";
+ };
+ };
};
i2c@f9967000 {
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 8363b7f..1b792d9 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -53,6 +53,8 @@
CONFIG_PM8XXX_RPC_VIBRATOR=y
CONFIG_MSM_SPM_V2=y
CONFIG_MSM_MULTIMEDIA_USE_ION=y
+CONFIG_MSM_CPR=y
+CONFIG_MSM_VP_REGULATOR=y
CONFIG_ARM_THUMBEE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -81,9 +83,13 @@
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
+CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@@ -162,6 +168,12 @@
CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_FILTER=y
+CONFIG_ATM=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
@@ -200,6 +212,19 @@
CONFIG_TUN=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
CONFIG_LIBRA_SDIOIF=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index d7735f5..25d97af 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -53,6 +53,8 @@
CONFIG_PM8XXX_RPC_VIBRATOR=y
CONFIG_MSM_SPM_V2=y
CONFIG_MSM_MULTIMEDIA_USE_ION=y
+CONFIG_MSM_CPR=y
+CONFIG_MSM_VP_REGULATOR=y
CONFIG_ARM_THUMBEE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -81,9 +83,13 @@
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
+CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@@ -162,6 +168,12 @@
CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_FILTER=y
+CONFIG_ATM=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
@@ -200,6 +212,19 @@
CONFIG_TUN=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
CONFIG_LIBRA_SDIOIF=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index fd6442c..0a99036 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -48,6 +48,7 @@
CONFIG_MSM_PIL_MBA=y
CONFIG_MSM_PIL_VENUS=y
CONFIG_MSM_PIL_PRONTO=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_OCMEM=y
@@ -230,6 +231,12 @@
CONFIG_MMC_TEST=m
CONFIG_MMC_MSM=y
CONFIG_MMC_MSM_SPS_SUPPORT=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_QPNP=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_SWITCH=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 42dda69..6f0a7e7 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -263,6 +263,18 @@
select ARM_HAS_SG_CHAIN
select MSM_RUN_QUEUE_STATS
+config ARCH_MPQ8092
+ bool "MPQ8092"
+ select ARCH_MSM_KRAITMP
+ select GPIO_MSM_V3
+ select ARM_GIC
+ select MULTI_IRQ_HANDLER
+ select CPU_V7
+ select MSM_GPIOMUX
+ select MAY_HAVE_SPARSE_IRQ
+ select SPARSE_IRQ
+ select MSM_NOPM
+
config ARCH_FSM9XXX
bool "FSM9XXX"
select ARCH_MSM_SCORPION
@@ -307,6 +319,7 @@
select ARM_TICKET_LOCKS
select MSM_RUN_QUEUE_STATS
select MIGHT_HAVE_CACHE_L2X0
+ select ARM_HAS_SG_CHAIN
config ARCH_MSM9625
bool "MSM9625"
@@ -398,6 +411,7 @@
select ARM_GIC
select ARCH_MSM_CORTEXMP
select MIGHT_HAVE_CACHE_L2X0
+ select ARM_HAS_SG_CHAIN
config MSM_VIC
bool
@@ -887,6 +901,7 @@
default "0x80200000" if ARCH_MSM8960
default "0x80200000" if ARCH_MSM8930
default "0x00000000" if ARCH_MSM8974
+ default "0x00000000" if ARCH_MPQ8092
default "0x10000000" if ARCH_FSM9XXX
default "0x20200000" if ARCH_MSM9625
default "0x00200000" if !MSM_STACKED_MEMORY
@@ -1026,6 +1041,14 @@
help
Say Y here if you want the debug print routines to direct
their output to the serial port on MSM 8974 devices.
+
+ config DEBUG_MPQ8092_UART
+ bool "Kernel low-level debugging messages via MPQ8092 UART"
+ depends on ARCH_MPQ8092
+ select MSM_HAS_DEBUG_UART_HS_V14
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the serial port on MPQ8092 devices.
endchoice
choice
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index da3d3c4..524ec89 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -103,6 +103,7 @@
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
ifndef CONFIG_ARCH_MSM8974
+ifndef CONFIG_ARCH_MPQ8092
obj-$(CONFIG_MSM_SMD) += pmic.o
obj-$(CONFIG_MSM_ONCRPCROUTER) += rpc_hsusb.o rpc_pmapp.o rpc_fsusb.o
endif
@@ -110,17 +111,20 @@
endif
endif
endif
+endif
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
ifndef CONFIG_ARCH_APQ8064
ifndef CONFIG_ARCH_MSM8974
ifndef CONFIG_ARCH_MSM9625
+ifndef CONFIG_ARCH_MPQ8092
obj-y += nand_partitions.o
endif
endif
endif
endif
endif
+endif
obj-$(CONFIG_MSM_SDIO_TTY) += sdio_tty.o
obj-$(CONFIG_MSM_SMD_TTY) += smd_tty.o
obj-$(CONFIG_MSM_SMD_QMI) += smd_qmi.o
@@ -244,6 +248,7 @@
obj-$(CONFIG_MACH_MSM7X27_FFA) += board-msm7x27.o devices-msm7x27.o
obj-$(CONFIG_ARCH_MSM7X27A) += clock-pcom-lookup.o devices-msm7x27a.o
board-7627a-all-objs += board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o
+board-7627a-all-objs += audio-7627a-devices.o
board-7627a-all-objs += board-msm7627a-display.o board-msm7627a-wlan.o board-msm7627a-io.o
obj-$(CONFIG_MACH_MSM7X27A_RUMI3) += board-msm7x27a.o board-7627a-all.o
obj-$(CONFIG_MACH_MSM7X27A_SURF) += board-msm7x27a.o board-7627a-all.o
@@ -294,6 +299,7 @@
obj-$(CONFIG_ARCH_MSM8974) += krait-regulator.o
obj-$(CONFIG_ARCH_MSM9625) += board-9625.o board-9625-gpiomux.o
obj-$(CONFIG_ARCH_MSM8930) += acpuclock-8930.o acpuclock-8627.o acpuclock-8930aa.o
+obj-$(CONFIG_ARCH_MPQ8092) += board-8092.o board-8092-gpiomux.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o
@@ -348,7 +354,7 @@
obj-$(CONFIG_ARCH_MSM9615) += gpiomux-v2.o gpiomux.o
obj-$(CONFIG_ARCH_MSM8974) += gpiomux-v2.o gpiomux.o
obj-$(CONFIG_ARCH_MSM9625) += gpiomux-v2.o gpiomux.o
-
+obj-$(CONFIG_ARCH_MPQ8092) += gpiomux-v2.o gpiomux.o
obj-$(CONFIG_MSM_SLEEP_STATS_DEVICE) += idle_stats_device.o
obj-$(CONFIG_MSM_DCVS) += msm_dcvs_scm.o msm_dcvs.o msm_dcvs_idle.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index b57d4e1..437933e 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -58,3 +58,7 @@
zreladdr-$(CONFIG_ARCH_FSM9XXX) := 0x10008000
params_phys-$(CONFIG_ARCH_FSM9XXX) := 0x10000100
initrd_phys-$(CONFIG_ARCH_FSM9XXX) := 0x12000000
+
+# MPQ8092
+ zreladdr-$(CONFIG_ARCH_MPQ8092) := 0x00008000
+
diff --git a/arch/arm/mach-msm/audio-7627a-devices.c b/arch/arm/mach-msm/audio-7627a-devices.c
new file mode 100644
index 0000000..798c118
--- /dev/null
+++ b/arch/arm/mach-msm/audio-7627a-devices.c
@@ -0,0 +1,218 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/android_pmem.h>
+#include <mach/board.h>
+
+#include "board-msm7627a.h"
+
+#define SND(desc, num) { .name = #desc, .id = num }
+static struct snd_endpoint snd_endpoints_list[] = {
+ SND(HANDSET, 0),
+ SND(MONO_HEADSET, 2),
+ SND(HEADSET, 3),
+ SND(SPEAKER, 6),
+ SND(TTY_HEADSET, 8),
+ SND(TTY_VCO, 9),
+ SND(TTY_HCO, 10),
+ SND(BT, 12),
+ SND(IN_S_SADC_OUT_HANDSET, 16),
+ SND(IN_S_SADC_OUT_SPEAKER_PHONE, 25),
+ SND(FM_DIGITAL_STEREO_HEADSET, 26),
+ SND(FM_DIGITAL_SPEAKER_PHONE, 27),
+ SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
+ SND(STEREO_HEADSET_AND_SPEAKER, 31),
+ SND(CURRENT, 0x7FFFFFFE),
+ SND(FM_ANALOG_STEREO_HEADSET, 35),
+ SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
+};
+#undef SND
+
+static struct msm_snd_endpoints msm_device_snd_endpoints = {
+ .endpoints = snd_endpoints_list,
+ .num = sizeof(snd_endpoints_list) / sizeof(struct snd_endpoint)
+};
+
+struct platform_device msm_device_snd = {
+ .name = "msm_snd",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_device_snd_endpoints
+ },
+};
+
+#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
+ (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
+ (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
+ (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
+ (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
+ (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP)| \
+ (1<<MSM_ADSP_CODEC_AC3))
+#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
+ (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
+ (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
+ (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
+ (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
+ (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
+#define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
+ (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
+ (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
+ (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
+ (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
+ (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
+#define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
+ (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
+ (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
+ (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
+ (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
+ (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
+#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
+
+static unsigned int dec_concurrency_table[] = {
+ /* Audio LP */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DMA)), 0,
+ 0, 0, 0,
+
+ /* Concurrency 1 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC4_FORMAT),
+
+ /* Concurrency 2 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC4_FORMAT),
+
+ /* Concurrency 3 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC4_FORMAT),
+
+ /* Concurrency 4 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC4_FORMAT),
+
+ /* Concurrency 5 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC4_FORMAT),
+
+ /* Concurrency 6 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|
+ (1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ 0, 0, 0, 0,
+
+ /* Concurrency 7 */
+ (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
+ (DEC4_FORMAT),
+};
+
+#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
+ .module_queueid = queueid, .module_decid = decid, \
+ .nr_codec_support = nr_codec}
+
+static struct msm_adspdec_info dec_info_list[] = {
+ DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
+ DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
+ DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
+ DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
+ DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
+};
+
+static struct msm_adspdec_database msm_device_adspdec_database = {
+ .num_dec = ARRAY_SIZE(dec_info_list),
+ .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
+ ARRAY_SIZE(dec_info_list)),
+ .dec_concurrency_table = dec_concurrency_table,
+ .dec_info_list = dec_info_list,
+};
+
+struct platform_device msm_device_adspdec = {
+ .name = "msm_adspdec",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_device_adspdec_database
+ },
+};
+
+#define SNDDEV_CAP_NONE 0x0
+#define SNDDEV_CAP_RX 0x1 /* RX direction */
+#define SNDDEV_CAP_TX 0x2 /* TX direction */
+#define SNDDEV_CAP_VOICE 0x4 /* Support voice call */
+#define SNDDEV_CAP_FM 0x10 /* Support FM radio */
+#define SNDDEV_CAP_TTY 0x20 /* Support TTY */
+#define CAD(desc, num, cap) { .name = #desc, .id = num, .capability = cap, }
+static struct cad_endpoint cad_endpoints_list[] = {
+ CAD(NONE, 0, SNDDEV_CAP_NONE),
+ CAD(HANDSET_SPKR, 1, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
+ CAD(HANDSET_MIC, 2, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(HEADSET_MIC, 3, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(HEADSET_SPKR_MONO, 4, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
+ CAD(HEADSET_SPKR_STEREO, 5, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
+ CAD(SPEAKER_PHONE_MIC, 6, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(SPEAKER_PHONE_MONO, 7, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
+ CAD(SPEAKER_PHONE_STEREO, 8, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
+ CAD(BT_SCO_MIC, 9, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(BT_SCO_SPKR, 10, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(BT_A2DP_SPKR, 11, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
+ CAD(TTY_HEADSET_MIC, 12, (SNDDEV_CAP_TX | \
+ SNDDEV_CAP_VOICE | SNDDEV_CAP_TTY)),
+ CAD(TTY_HEADSET_SPKR, 13, (SNDDEV_CAP_RX | \
+ SNDDEV_CAP_VOICE | SNDDEV_CAP_TTY)),
+ CAD(HEADSET_STEREO_PLUS_SPKR_MONO_RX, 19, (SNDDEV_CAP_TX | \
+ SNDDEV_CAP_VOICE)),
+ CAD(LP_FM_HEADSET_SPKR_STEREO_RX, 25, (SNDDEV_CAP_TX | SNDDEV_CAP_FM)),
+ CAD(I2S_RX, 26, (SNDDEV_CAP_RX)),
+ CAD(SPEAKER_PHONE_MIC_ENDFIRE, 45, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(HANDSET_MIC_ENDFIRE, 46, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
+ CAD(I2S_TX, 48, (SNDDEV_CAP_TX)),
+ CAD(LP_FM_HEADSET_SPKR_STEREO_PLUS_HEADSET_SPKR_STEREO_RX, 57, \
+ (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
+ CAD(FM_DIGITAL_HEADSET_SPKR_STEREO, 65, \
+ (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
+ CAD(FM_DIGITAL_SPEAKER_PHONE_MONO, 67, \
+ (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
+ CAD(FM_DIGITAL_BT_A2DP_SPKR, 69, \
+ (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
+ CAD(MAX, 80, SNDDEV_CAP_NONE),
+};
+#undef CAD
+
+static struct msm_cad_endpoints msm_device_cad_endpoints = {
+ .endpoints = cad_endpoints_list,
+ .num = sizeof(cad_endpoints_list) / sizeof(struct cad_endpoint)
+};
+
+struct platform_device msm_device_cad = {
+ .name = "msm_cad",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_device_cad_endpoints
+ },
+};
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index fbc3e25..1a02fce 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -1711,6 +1711,20 @@
}
/*
+ * if this gets hit, that means restart_notifier_cb() has started
+ * but probably not finished, thus we know SSR has happened, but
+ * haven't been able to send that info to our clients yet.
+ * in that case, abort the ul_wakeup() so that we don't undo any
+ * work restart_notifier_cb() has done. The clients will be notified
+ * shortly. No cleanup necessary (reschedule the wakeup) as our and
+ * their SSR handling will cover it
+ */
+ if (unlikely(in_global_reset == 1)) {
+ mutex_unlock(&wakeup_lock);
+ return;
+ }
+
+ /*
* if someone is voting for UL before bam is inited (modem up first
* time), set flag for init to kickoff ul wakeup once bam is inited
*/
diff --git a/arch/arm/mach-msm/board-8064-gpiomux.c b/arch/arm/mach-msm/board-8064-gpiomux.c
index 9e43874..f4e9a8f 100644
--- a/arch/arm/mach-msm/board-8064-gpiomux.c
+++ b/arch/arm/mach-msm/board-8064-gpiomux.c
@@ -336,6 +336,13 @@
.pull = GPIOMUX_PULL_NONE,
};
+static struct gpiomux_setting gpio_i2c_2ma_config = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+
static struct gpiomux_setting gpio_i2c_config_sus = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_2MA,
@@ -714,12 +721,6 @@
},
},
{
- .gpio = 32, /* EPM CS */
- .settings = {
- [GPIOMUX_SUSPENDED] = &gpio_epm_spi_cs_config,
- },
- },
- {
.gpio = 53, /* NOR CS */
.settings = {
[GPIOMUX_SUSPENDED] = &gpio_spi_cs_config,
@@ -737,6 +738,35 @@
[GPIOMUX_SUSPENDED] = &gsbi7_func1_cfg,
},
},
+};
+
+static struct msm_gpiomux_config apq8064_non_mi2s_gsbi_configs[] __initdata = {
+ {
+ .gpio = 32, /* EPM CS */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_epm_spi_cs_config,
+ },
+ },
+};
+
+static struct msm_gpiomux_config apq8064_gsbi1_i2c_2ma_configs[] __initdata = {
+ {
+ .gpio = 21, /* GSBI1 QUP I2C_CLK */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_config_sus,
+ [GPIOMUX_ACTIVE] = &gpio_i2c_2ma_config,
+ },
+ },
+ {
+ .gpio = 20, /* GSBI1 QUP I2C_DATA */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_config_sus,
+ [GPIOMUX_ACTIVE] = &gpio_i2c_2ma_config,
+ },
+ },
+};
+
+static struct msm_gpiomux_config apq8064_gsbi1_i2c_8ma_configs[] __initdata = {
{
.gpio = 21, /* GSBI1 QUP I2C_CLK */
.settings = {
@@ -768,7 +798,7 @@
},
};
-static struct gpiomux_setting spkr_i2c = {
+static struct gpiomux_setting spkr_i2s = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
.pull = GPIOMUX_PULL_KEEPER,
@@ -778,25 +808,25 @@
{
.gpio = 47, /* spkr i2c sck */
.settings = {
- [GPIOMUX_SUSPENDED] = &spkr_i2c,
+ [GPIOMUX_SUSPENDED] = &spkr_i2s,
},
},
{
.gpio = 48, /* spkr_i2s_ws */
.settings = {
- [GPIOMUX_SUSPENDED] = &spkr_i2c,
+ [GPIOMUX_SUSPENDED] = &spkr_i2s,
},
},
{
.gpio = 49, /* spkr_i2s_dout */
.settings = {
- [GPIOMUX_SUSPENDED] = &spkr_i2c,
+ [GPIOMUX_SUSPENDED] = &spkr_i2s,
},
},
{
.gpio = 50, /* spkr_i2s_mclk */
.settings = {
- [GPIOMUX_SUSPENDED] = &spkr_i2c,
+ [GPIOMUX_SUSPENDED] = &spkr_i2s,
},
},
};
@@ -968,13 +998,19 @@
},
};
-static struct gpiomux_setting mi2s_act_cfg = {
+static struct gpiomux_setting i2s_act_cfg = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
.pull = GPIOMUX_PULL_NONE,
};
-static struct gpiomux_setting mi2s_sus_cfg = {
+static struct gpiomux_setting i2s_act_func_2_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting i2s_sus_cfg = {
.func = GPIOMUX_FUNC_GPIO,
.drv = GPIOMUX_DRV_2MA,
.pull = GPIOMUX_PULL_DOWN,
@@ -984,55 +1020,145 @@
{
.gpio = 27, /* mi2s ws */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
{
.gpio = 28, /* mi2s sclk */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
{
.gpio = 29, /* mi2s dout3 */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
{
.gpio = 30, /* mi2s dout2 */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
{
.gpio = 31, /* mi2s dout1 */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
{
.gpio = 32, /* mi2s dout0 */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
{
.gpio = 33, /* mi2s mclk */
.settings = {
- [GPIOMUX_ACTIVE] = &mi2s_act_cfg,
- [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg,
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
},
},
};
+
+static struct msm_gpiomux_config apq8064_mi2s_configs[] __initdata = {
+ {
+ .gpio = 27, /* mi2s ws */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 28, /* mi2s sclk */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 29, /* mi2s dout3 - TX*/
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 32, /* mi2s dout0 - RX */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+
+ {
+ .gpio = 33, /* mi2s mclk */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+};
+
+static struct msm_gpiomux_config apq8064_mic_i2s_configs[] __initdata = {
+ {
+ .gpio = 35, /* mic i2s sclk */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 36, /* mic i2s ws */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 37, /* mic i2s din0 */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+};
+
+
+static struct msm_gpiomux_config apq8064_spkr_i2s_configs[] __initdata = {
+ {
+ .gpio = 40, /* spkr i2s sclk */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_func_2_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 41, /* spkr i2s dout */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_func_2_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+ {
+ .gpio = 42, /* spkr i2s ws */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &i2s_act_cfg,
+ [GPIOMUX_SUSPENDED] = &i2s_sus_cfg,
+ },
+ },
+};
+
+
static struct msm_gpiomux_config apq8064_mxt_configs[] __initdata = {
{ /* TS INTERRUPT */
.gpio = 6,
@@ -1373,10 +1499,28 @@
msm_gpiomux_install(apq8064_gsbi_configs,
ARRAY_SIZE(apq8064_gsbi_configs));
- }
- msm_gpiomux_install(apq8064_slimbus_config,
- ARRAY_SIZE(apq8064_slimbus_config));
+ if (!(machine_is_apq8064_mtp() &&
+ (SOCINFO_VERSION_MINOR(platform_version) == 1)))
+ msm_gpiomux_install(apq8064_non_mi2s_gsbi_configs,
+ ARRAY_SIZE(apq8064_non_mi2s_gsbi_configs));
+ }
+ if (machine_is_apq8064_mtp() &&
+ (SOCINFO_VERSION_MINOR(platform_version) == 1)) {
+ msm_gpiomux_install(apq8064_mic_i2s_configs,
+ ARRAY_SIZE(apq8064_mic_i2s_configs));
+ msm_gpiomux_install(apq8064_spkr_i2s_configs,
+ ARRAY_SIZE(apq8064_spkr_i2s_configs));
+ msm_gpiomux_install(apq8064_mi2s_configs,
+ ARRAY_SIZE(apq8064_mi2s_configs));
+ msm_gpiomux_install(apq8064_gsbi1_i2c_2ma_configs,
+ ARRAY_SIZE(apq8064_gsbi1_i2c_2ma_configs));
+ } else {
+ msm_gpiomux_install(apq8064_slimbus_config,
+ ARRAY_SIZE(apq8064_slimbus_config));
+ msm_gpiomux_install(apq8064_gsbi1_i2c_8ma_configs,
+ ARRAY_SIZE(apq8064_gsbi1_i2c_8ma_configs));
+ }
msm_gpiomux_install(apq8064_audio_codec_configs,
ARRAY_SIZE(apq8064_audio_codec_configs));
diff --git a/arch/arm/mach-msm/board-8064-regulator.c b/arch/arm/mach-msm/board-8064-regulator.c
index 819f5d9..3c9ef65 100644
--- a/arch/arm/mach-msm/board-8064-regulator.c
+++ b/arch/arm/mach-msm/board-8064-regulator.c
@@ -128,6 +128,8 @@
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla-slim"),
REGULATOR_SUPPLY("VDDD_CDC_D", "tabla2x-slim"),
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla2x-slim"),
+ REGULATOR_SUPPLY("VDDD_CDC_D", "0-000d"),
+ REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "0-000d"),
};
VREG_CONSUMERS(L26) = {
REGULATOR_SUPPLY("8921_l26", NULL),
@@ -169,6 +171,10 @@
REGULATOR_SUPPLY("CDC_VDD_CP", "tabla2x-slim"),
REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla2x-slim"),
REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla2x-slim"),
+ REGULATOR_SUPPLY("VDDIO_CDC", "0-000d"),
+ REGULATOR_SUPPLY("CDC_VDD_CP", "0-000d"),
+ REGULATOR_SUPPLY("CDC_VDDA_TX", "0-000d"),
+ REGULATOR_SUPPLY("CDC_VDDA_RX", "0-000d"),
REGULATOR_SUPPLY("riva_vddpx", "wcnss_wlan.0"),
REGULATOR_SUPPLY("vcc_i2c", "3-005b"),
REGULATOR_SUPPLY("vcc_i2c", "3-0024"),
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index 97cb2aa..47a5a08 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -1148,6 +1148,84 @@
},
};
+static struct wcd9xxx_pdata apq8064_tabla_i2c_platform_data = {
+ .irq = MSM_GPIO_TO_INT(77),
+ .irq_base = TABLA_INTERRUPT_BASE,
+ .num_irqs = NR_WCD9XXX_IRQS,
+ .reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
+ .micbias = {
+ .ldoh_v = TABLA_LDOH_2P85_V,
+ .cfilt1_mv = 1800,
+ .cfilt2_mv = 1800,
+ .cfilt3_mv = 1800,
+ .bias1_cfilt_sel = TABLA_CFILT1_SEL,
+ .bias2_cfilt_sel = TABLA_CFILT2_SEL,
+ .bias3_cfilt_sel = TABLA_CFILT3_SEL,
+ .bias4_cfilt_sel = TABLA_CFILT3_SEL,
+ },
+ .regulator = {
+ {
+ .name = "CDC_VDD_CP",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
+ },
+ {
+ .name = "CDC_VDDA_RX",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX,
+ },
+ {
+ .name = "CDC_VDDA_TX",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX,
+ },
+ {
+ .name = "VDDIO_CDC",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX,
+ },
+ {
+ .name = "VDDD_CDC_D",
+ .min_uV = 1225000,
+ .max_uV = 1250000,
+ .optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX,
+ },
+ {
+ .name = "CDC_VDDA_A_1P2V",
+ .min_uV = 1225000,
+ .max_uV = 1250000,
+ .optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX,
+ },
+ },
+};
+
+static struct i2c_board_info apq8064_tabla_i2c_device_info[] __initdata = {
+ {
+ I2C_BOARD_INFO("tabla top level",
+ APQ_8064_TABLA_I2C_SLAVE_ADDR),
+ .platform_data = &apq8064_tabla_i2c_platform_data,
+ },
+ {
+ I2C_BOARD_INFO("tabla analog",
+ APQ_8064_TABLA_ANALOG_I2C_SLAVE_ADDR),
+ .platform_data = &apq8064_tabla_i2c_platform_data,
+ },
+ {
+ I2C_BOARD_INFO("tabla digital1",
+ APQ_8064_TABLA_DIGITAL1_I2C_SLAVE_ADDR),
+ .platform_data = &apq8064_tabla_i2c_platform_data,
+ },
+ {
+ I2C_BOARD_INFO("tabla digital2",
+ APQ_8064_TABLA_DIGITAL2_I2C_SLAVE_ADDR),
+ .platform_data = &apq8064_tabla_i2c_platform_data,
+ },
+};
+
/* enable the level shifter for cs8427 to make sure the I2C
* clock is running at 100KHz and voltage levels are at 3.3
* and 5 volts
@@ -1164,8 +1242,10 @@
return ret;
}
gpio_direction_output(SX150X_GPIO(1, 10), 1);
- } else
+ } else {
+ gpio_direction_output(SX150X_GPIO(1, 10), 0);
gpio_free(SX150X_GPIO(1, 10));
+ }
return ret;
}
@@ -1290,7 +1370,7 @@
/* T6 Object */
0, 0, 0, 0, 0, 0,
/* T38 Object */
- 14, 2, 0, 24, 5, 12, 0, 0, 0, 0,
+ 14, 3, 0, 5, 7, 12, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1298,12 +1378,12 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* T7 Object */
- 100, 10, 50,
+ 32, 10, 50,
/* T8 Object */
25, 0, 20, 20, 0, 0, 0, 0, 0, 0,
/* T9 Object */
139, 0, 0, 26, 42, 0, 32, 80, 2, 5,
- 0, 5, 5, 0, 10, 30, 10, 10, 255, 2,
+ 0, 5, 5, 79, 10, 30, 10, 10, 255, 2,
85, 5, 0, 5, 9, 5, 12, 35, 70, 40,
20, 5, 0, 0, 0,
/* T18 Object */
@@ -2247,6 +2327,17 @@
&apq8064_device_qup_i2c_gsbi4,
};
+static struct platform_device *common_mpq_devices[] __initdata = {
+ &mpq_cpudai_sec_i2s_rx,
+ &mpq_cpudai_mi2s_tx,
+};
+
+static struct platform_device *common_i2s_devices[] __initdata = {
+ &apq_cpudai_mi2s,
+ &apq_cpudai_i2s_rx,
+ &apq_cpudai_i2s_tx,
+};
+
static struct platform_device *early_common_devices[] __initdata = {
&apq8064_device_acpuclk,
&apq8064_device_dmov,
@@ -2318,8 +2409,6 @@
&apq_pcm_routing,
&apq_cpudai0,
&apq_cpudai1,
- &mpq_cpudai_sec_i2s_rx,
- &mpq_cpudai_mi2s_tx,
&apq_cpudai_hdmi_rx,
&apq_cpudai_bt_rx,
&apq_cpudai_bt_tx,
@@ -2933,6 +3022,14 @@
}
};
+static struct i2c_registry apq8064_tabla_i2c_devices[] __initdata = {
+ {
+ .bus = APQ_8064_GSBI1_QUP_I2C_BUS_ID,
+ .info = apq8064_tabla_i2c_device_info,
+ .len = ARRAY_SIZE(apq8064_tabla_i2c_device_info),
+ },
+};
+
#define SX150X_EXP1_INT_N PM8921_MPP_IRQ(PM8921_IRQ_BASE, 9)
#define SX150X_EXP2_INT_N MSM_GPIO_TO_INT(81)
@@ -3011,6 +3108,7 @@
{
u8 mach_mask = 0;
int i;
+ u32 version;
#ifdef CONFIG_MSM_CAMERA
struct i2c_registry apq8064_camera_i2c_devices = {
@@ -3053,6 +3151,18 @@
mpq8064_i2c_devices[i].info,
mpq8064_i2c_devices[i].len);
}
+
+ if (machine_is_apq8064_mtp()) {
+ version = socinfo_get_platform_version();
+ if (SOCINFO_VERSION_MINOR(version) == 1)
+ for (i = 0; i < ARRAY_SIZE(apq8064_tabla_i2c_devices);
+ ++i)
+ i2c_register_board_info(
+ apq8064_tabla_i2c_devices[i].bus,
+ apq8064_tabla_i2c_devices[i].info,
+ apq8064_tabla_i2c_devices[i].len);
+ }
+
}
static void enable_ddr3_regulator(void)
@@ -3091,7 +3201,7 @@
static void __init apq8064_common_init(void)
{
- u32 platform_version;
+ u32 platform_version = socinfo_get_platform_version();
if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
apq8064_pm8917_pdata_fixup();
@@ -3144,6 +3254,18 @@
machine_is_mpq8064_dtv()))
platform_add_devices(common_not_mpq_devices,
ARRAY_SIZE(common_not_mpq_devices));
+
+ if ((machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
+ machine_is_mpq8064_dtv()))
+ platform_add_devices(common_mpq_devices,
+ ARRAY_SIZE(common_mpq_devices));
+
+ if (machine_is_apq8064_mtp()) {
+ if (SOCINFO_VERSION_MINOR(platform_version) == 1)
+ platform_add_devices(common_i2s_devices,
+ ARRAY_SIZE(common_i2s_devices));
+ }
+
enable_ddr3_regulator();
if (machine_is_apq8064_mtp()) {
msm_hsic_pdata.log2_irq_thresh = 5,
@@ -3155,7 +3277,6 @@
if (machine_is_apq8064_mtp()) {
mdm_8064_device.dev.platform_data = &mdm_platform_data;
- platform_version = socinfo_get_platform_version();
if (SOCINFO_VERSION_MINOR(platform_version) == 1) {
i2s_mdm_8064_device.dev.platform_data =
&mdm_platform_data;
diff --git a/arch/arm/mach-msm/board-8064.h b/arch/arm/mach-msm/board-8064.h
index 1437b3b..740fa39 100644
--- a/arch/arm/mach-msm/board-8064.h
+++ b/arch/arm/mach-msm/board-8064.h
@@ -86,6 +86,13 @@
extern struct msm_camera_board_info apq8064_camera_board_info;
void apq8064_init_cam(void);
+
+/* Tabla slave address for I2C */
+#define APQ_8064_TABLA_I2C_SLAVE_ADDR 0x0d
+#define APQ_8064_TABLA_ANALOG_I2C_SLAVE_ADDR 0x77
+#define APQ_8064_TABLA_DIGITAL1_I2C_SLAVE_ADDR 0x66
+#define APQ_8064_TABLA_DIGITAL2_I2C_SLAVE_ADDR 0x55
+
#define APQ_8064_GSBI1_QUP_I2C_BUS_ID 0
#define APQ_8064_GSBI3_QUP_I2C_BUS_ID 3
#define APQ_8064_GSBI4_QUP_I2C_BUS_ID 4
diff --git a/arch/arm/mach-msm/board-8092-gpiomux.c b/arch/arm/mach-msm/board-8092-gpiomux.c
new file mode 100644
index 0000000..823ef70
--- /dev/null
+++ b/arch/arm/mach-msm/board-8092-gpiomux.c
@@ -0,0 +1,53 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/gpiomux.h>
+
+static struct gpiomux_setting gpio_uart_config = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_16MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_OUT_HIGH,
+};
+
+static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
+ {
+ .gpio = 45, /* BLSP8 UART TX */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_uart_config,
+ },
+ },
+ {
+ .gpio = 46, /* BLSP8 UART RX */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_uart_config,
+ },
+ },
+};
+
+void __init mpq8092_init_gpiomux(void)
+{
+ int rc;
+
+ rc = msm_gpiomux_init(NR_GPIO_IRQS);
+ if (rc) {
+ pr_err(KERN_ERR "mpq8092_init_gpiomux failed %d\n", rc);
+ return;
+ }
+
+ msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs));
+}
diff --git a/arch/arm/mach-msm/board-8092.c b/arch/arm/mach-msm/board-8092.c
new file mode 100644
index 0000000..0471ff4
--- /dev/null
+++ b/arch/arm/mach-msm/board-8092.c
@@ -0,0 +1,110 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <asm/hardware/gic.h>
+#include <asm/arch_timer.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/socinfo.h>
+#include <mach/board.h>
+
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+
+#include "clock.h"
+
+static struct of_device_id irq_match[] __initdata = {
+ { .compatible = "qcom,msm-qgic2", .data = gic_of_init, },
+ { .compatible = "qcom,msm-gpio", .data = msm_gpio_of_init, },
+ {}
+};
+
+static struct clk_lookup msm_clocks_dummy[] = {
+ CLK_DUMMY("core_clk", BLSP1_UART_CLK, "msm_serial_hsl.0", OFF),
+ CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "msm_serial_hsl.0", OFF),
+};
+
+struct clock_init_data mpq8092_clock_init_data __initdata = {
+ .table = msm_clocks_dummy,
+ .size = ARRAY_SIZE(msm_clocks_dummy),
+};
+
+void __init mpq8092_init_irq(void)
+{
+ of_irq_init(irq_match);
+}
+
+static void __init mpq8092_dt_timer_init(void)
+{
+ arch_timer_of_register();
+}
+
+static struct sys_timer mpq8092_dt_timer = {
+ .init = mpq8092_dt_timer_init
+};
+
+static void __init mpq8092_dt_init_irq(void)
+{
+ mpq8092_init_irq();
+}
+
+static void __init mpq8092_dt_map_io(void)
+{
+ msm_map_mpq8092_io();
+ if (socinfo_init() < 0)
+ pr_err("%s: socinfo_init() failed\n", __func__);
+
+}
+
+static struct of_dev_auxdata mpq8092_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("qcom,msm-lsuart-v14", 0xF991F000, \
+ "msm_serial_hsl.0", NULL),
+ {}
+};
+
+static void __init mpq8092_init(struct of_dev_auxdata **adata)
+{
+ mpq8092_init_gpiomux();
+ *adata = mpq8092_auxdata_lookup;
+ msm_clock_init(&mpq8092_clock_init_data);
+}
+
+static void __init mpq8092_dt_init(void)
+{
+ struct of_dev_auxdata *adata = NULL;
+
+ mpq8092_init(&adata);
+ of_platform_populate(NULL, of_default_bus_match_table, adata, NULL);
+}
+
+static const char *mpq8092_dt_match[] __initconst = {
+ "qcom,mpq8092-sim",
+ NULL
+};
+
+DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+ .map_io = mpq8092_dt_map_io,
+ .init_irq = mpq8092_dt_init_irq,
+ .init_machine = mpq8092_dt_init,
+ .handle_irq = gic_handle_irq,
+ .timer = &mpq8092_dt_timer,
+ .dt_compat = mpq8092_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index af7204e..a3de539 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -1447,6 +1447,14 @@
0x23, 0x83,/* set source impedance sdjusment */
-1};
+static int sglte_phy_init_seq[] = {
+ 0x44, 0x80, /* set VBUS valid threshold
+ and disconnect valid threshold */
+ 0x3A, 0x81, /* update DC voltage level */
+ 0x24, 0x82, /* set preemphasis and rise/fall time */
+ 0x13, 0x83, /* set source impedance adjusment */
+ -1};
+
#ifdef CONFIG_MSM_BUS_SCALING
/* Bandwidth requests (zero) if no vote placed */
static struct msm_bus_vectors usb_init_vectors[] = {
@@ -3137,7 +3145,14 @@
msm8960_device_otg.dev.platform_data = &msm_otg_pdata;
if (machine_is_msm8960_mtp() || machine_is_msm8960_fluid() ||
machine_is_msm8960_cdp()) {
- msm_otg_pdata.phy_init_seq = wr_phy_init_seq;
+ /* Due to availability of USB Switch in SGLTE Platform
+ * it requires different HSUSB PHY settings compare to
+ * 8960 MTP/CDP platform.
+ */
+ if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE)
+ msm_otg_pdata.phy_init_seq = sglte_phy_init_seq;
+ else
+ msm_otg_pdata.phy_init_seq = wr_phy_init_seq;
} else if (machine_is_msm8960_liquid()) {
msm_otg_pdata.phy_init_seq =
liquid_v1_phy_init_seq;
diff --git a/arch/arm/mach-msm/board-8974-gpiomux.c b/arch/arm/mach-msm/board-8974-gpiomux.c
index 74c503d..fd2329f 100644
--- a/arch/arm/mach-msm/board-8974-gpiomux.c
+++ b/arch/arm/mach-msm/board-8974-gpiomux.c
@@ -126,6 +126,56 @@
},
};
+
+static struct gpiomux_setting hdmi_suspend_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting hdmi_active_1_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct gpiomux_setting hdmi_active_2_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_16MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct msm_gpiomux_config msm_hdmi_configs[] __initdata = {
+ {
+ .gpio = 31,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hdmi_active_1_cfg,
+ [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
+ },
+ },
+ {
+ .gpio = 32,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hdmi_active_1_cfg,
+ [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
+ },
+ },
+ {
+ .gpio = 33,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hdmi_active_1_cfg,
+ [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
+ },
+ },
+ {
+ .gpio = 34,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hdmi_active_2_cfg,
+ [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
+ },
+ },
+};
+
static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
{
@@ -394,4 +444,6 @@
msm_gpiomux_install(msm_sensor_configs, ARRAY_SIZE(msm_sensor_configs));
msm_gpiomux_install(msm_taiko_config, ARRAY_SIZE(msm_taiko_config));
+
+ msm_gpiomux_install(msm_hdmi_configs, ARRAY_SIZE(msm_hdmi_configs));
}
diff --git a/arch/arm/mach-msm/board-msm7627a.h b/arch/arm/mach-msm/board-msm7627a.h
index 4357e01..cd7c1df 100644
--- a/arch/arm/mach-msm/board-msm7627a.h
+++ b/arch/arm/mach-msm/board-msm7627a.h
@@ -102,6 +102,10 @@
void __init msm7627a_bt_power_init(void);
#endif
+extern struct platform_device msm_device_snd;
+extern struct platform_device msm_device_adspdec;
+extern struct platform_device msm_device_cad;
+
void __init msm7627a_camera_init(void);
int lcd_camera_power_onoff(int on);
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index cda7c2a..8df1c9b 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -63,13 +63,6 @@
#define PMEM_KERNEL_EBI1_SIZE 0x3A000
#define MSM_PMEM_AUDIO_SIZE 0x1F4000
-#define SNDDEV_CAP_NONE 0x0
-#define SNDDEV_CAP_RX 0x1 /* RX direction */
-#define SNDDEV_CAP_TX 0x2 /* TX direction */
-#define SNDDEV_CAP_VOICE 0x4 /* Support voice call */
-#define SNDDEV_CAP_FM 0x10 /* Support FM radio */
-#define SNDDEV_CAP_TTY 0x20 /* Support TTY */
-
#if defined(CONFIG_GPIO_SX150X)
enum {
SX150X_CORE,
@@ -480,197 +473,6 @@
early_param("pmem_adsp_size", pmem_adsp_size_setup);
-#define SND(desc, num) { .name = #desc, .id = num }
-static struct snd_endpoint snd_endpoints_list[] = {
- SND(HANDSET, 0),
- SND(MONO_HEADSET, 2),
- SND(HEADSET, 3),
- SND(SPEAKER, 6),
- SND(TTY_HEADSET, 8),
- SND(TTY_VCO, 9),
- SND(TTY_HCO, 10),
- SND(BT, 12),
- SND(IN_S_SADC_OUT_HANDSET, 16),
- SND(IN_S_SADC_OUT_SPEAKER_PHONE, 25),
- SND(FM_DIGITAL_STEREO_HEADSET, 26),
- SND(FM_DIGITAL_SPEAKER_PHONE, 27),
- SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
- SND(STEREO_HEADSET_AND_SPEAKER, 31),
- SND(CURRENT, 0x7FFFFFFE),
- SND(FM_ANALOG_STEREO_HEADSET, 35),
- SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
-};
-#undef SND
-static struct msm_snd_endpoints msm_device_snd_endpoints = {
- .endpoints = snd_endpoints_list,
- .num = sizeof(snd_endpoints_list) / sizeof(struct snd_endpoint)
-};
-
-static struct platform_device msm_device_snd = {
- .name = "msm_snd",
- .id = -1,
- .dev = {
- .platform_data = &msm_device_snd_endpoints
- },
-};
-
-#define CAD(desc, num, cap) { .name = #desc, .id = num, .capability = cap, }
-static struct cad_endpoint cad_endpoints_list[] = {
- CAD(NONE, 0, SNDDEV_CAP_NONE),
- CAD(HANDSET_SPKR, 1, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(HANDSET_MIC, 2, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(HEADSET_MIC, 3, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(HEADSET_SPKR_MONO, 4, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(HEADSET_SPKR_STEREO, 5, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(SPEAKER_PHONE_MIC, 6, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(SPEAKER_PHONE_MONO, 7, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(SPEAKER_PHONE_STEREO, 8, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(BT_SCO_MIC, 9, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(BT_SCO_SPKR, 10, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(BT_A2DP_SPKR, 11, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(TTY_HEADSET_MIC, 12, (SNDDEV_CAP_TX | \
- SNDDEV_CAP_VOICE | SNDDEV_CAP_TTY)),
- CAD(TTY_HEADSET_SPKR, 13, (SNDDEV_CAP_RX | \
- SNDDEV_CAP_VOICE | SNDDEV_CAP_TTY)),
- CAD(HEADSET_STEREO_PLUS_SPKR_MONO_RX, 19, (SNDDEV_CAP_TX | \
- SNDDEV_CAP_VOICE)),
- CAD(LP_FM_HEADSET_SPKR_STEREO_RX, 25, (SNDDEV_CAP_TX | SNDDEV_CAP_FM)),
- CAD(I2S_RX, 26, (SNDDEV_CAP_RX)),
- CAD(SPEAKER_PHONE_MIC_ENDFIRE, 45, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(HANDSET_MIC_ENDFIRE, 46, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(I2S_TX, 48, (SNDDEV_CAP_TX)),
- CAD(LP_FM_HEADSET_SPKR_STEREO_PLUS_HEADSET_SPKR_STEREO_RX, 57, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(FM_DIGITAL_HEADSET_SPKR_STEREO, 65, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(FM_DIGITAL_SPEAKER_PHONE_MONO, 67, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(FM_DIGITAL_BT_A2DP_SPKR, 69, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(MAX, 80, SNDDEV_CAP_NONE),
-};
-#undef CAD
-static struct msm_cad_endpoints msm_device_cad_endpoints = {
- .endpoints = cad_endpoints_list,
- .num = sizeof(cad_endpoints_list) / sizeof(struct cad_endpoint)
-};
-
-static struct platform_device msm_device_cad = {
- .name = "msm_cad",
- .id = -1,
- .dev = {
- .platform_data = &msm_device_cad_endpoints
- },
-};
-
-#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))| \
- (1<<MSM_ADSP_CODEC_AC3)
-#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
-#define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
-#define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
-#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
-
-static unsigned int dec_concurrency_table[] = {
- /* Audio LP */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DMA)), 0,
- 0, 0, 0,
-
- /* Concurrency 1 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 2 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 3 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 4 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 5 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 6 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|
- (1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- 0, 0, 0, 0,
-
- /* Concurrency 7 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-};
-
-#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
- .module_queueid = queueid, .module_decid = decid, \
- .nr_codec_support = nr_codec}
-
-static struct msm_adspdec_info dec_info_list[] = {
- DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
-};
-
-static struct msm_adspdec_database msm_device_adspdec_database = {
- .num_dec = ARRAY_SIZE(dec_info_list),
- .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
- ARRAY_SIZE(dec_info_list)),
- .dec_concurrency_table = dec_concurrency_table,
- .dec_info_list = dec_info_list,
-};
-
-static struct platform_device msm_device_adspdec = {
- .name = "msm_adspdec",
- .id = -1,
- .dev = {
- .platform_data = &msm_device_adspdec_database
- },
-};
-
static struct android_pmem_platform_data android_pmem_audio_pdata = {
.name = "pmem_audio",
.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 0d17f47..58cb4ab 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -75,12 +75,6 @@
#define I2C_PIN_CTL 0x15
#define I2C_NORMAL 0x40
-#define SNDDEV_CAP_NONE 0x0
-#define SNDDEV_CAP_RX 0x1 /* RX direction */
-#define SNDDEV_CAP_TX 0x2 /* TX direction */
-#define SNDDEV_CAP_VOICE 0x4 /* Support voice call */
-#define SNDDEV_CAP_FM 0x10 /* Support FM radio */
-#define SNDDEV_CAP_TTY 0x20 /* Support TTY */
static struct platform_device msm_wlan_ar6000_pm_device = {
.name = "wlan_ar6000_pm_dev",
@@ -426,199 +420,6 @@
early_param("pmem_adsp_size", pmem_adsp_size_setup);
-#define SND(desc, num) { .name = #desc, .id = num }
-static struct snd_endpoint snd_endpoints_list[] = {
- SND(HANDSET, 0),
- SND(MONO_HEADSET, 2),
- SND(HEADSET, 3),
- SND(SPEAKER, 6),
- SND(TTY_HEADSET, 8),
- SND(TTY_VCO, 9),
- SND(TTY_HCO, 10),
- SND(BT, 12),
- SND(IN_S_SADC_OUT_HANDSET, 16),
- SND(IN_S_SADC_OUT_SPEAKER_PHONE, 25),
- SND(FM_DIGITAL_STEREO_HEADSET, 26),
- SND(FM_DIGITAL_SPEAKER_PHONE, 27),
- SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
- SND(STEREO_HEADSET_AND_SPEAKER, 31),
- SND(CURRENT, 0x7FFFFFFE),
- SND(FM_ANALOG_STEREO_HEADSET, 35),
- SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
-};
-#undef SND
-
-static struct msm_snd_endpoints msm_device_snd_endpoints = {
- .endpoints = snd_endpoints_list,
- .num = sizeof(snd_endpoints_list) / sizeof(struct snd_endpoint)
-};
-
-static struct platform_device msm_device_snd = {
- .name = "msm_snd",
- .id = -1,
- .dev = {
- .platform_data = &msm_device_snd_endpoints
- },
-};
-
-#define CAD(desc, num, cap) { .name = #desc, .id = num, .capability = cap, }
-static struct cad_endpoint cad_endpoints_list[] = {
- CAD(NONE, 0, SNDDEV_CAP_NONE),
- CAD(HANDSET_SPKR, 1, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(HANDSET_MIC, 2, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(HEADSET_MIC, 3, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(HEADSET_SPKR_MONO, 4, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(HEADSET_SPKR_STEREO, 5, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(SPEAKER_PHONE_MIC, 6, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(SPEAKER_PHONE_MONO, 7, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(SPEAKER_PHONE_STEREO, 8, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(BT_SCO_MIC, 9, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(BT_SCO_SPKR, 10, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(BT_A2DP_SPKR, 11, (SNDDEV_CAP_RX | SNDDEV_CAP_VOICE)),
- CAD(TTY_HEADSET_MIC, 12, (SNDDEV_CAP_TX | \
- SNDDEV_CAP_VOICE | SNDDEV_CAP_TTY)),
- CAD(TTY_HEADSET_SPKR, 13, (SNDDEV_CAP_RX | \
- SNDDEV_CAP_VOICE | SNDDEV_CAP_TTY)),
- CAD(HEADSET_STEREO_PLUS_SPKR_MONO_RX, 19, (SNDDEV_CAP_TX | \
- SNDDEV_CAP_VOICE)),
- CAD(LP_FM_HEADSET_SPKR_STEREO_RX, 25, (SNDDEV_CAP_TX | SNDDEV_CAP_FM)),
- CAD(I2S_RX, 26, (SNDDEV_CAP_RX)),
- CAD(SPEAKER_PHONE_MIC_ENDFIRE, 45, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(HANDSET_MIC_ENDFIRE, 46, (SNDDEV_CAP_TX | SNDDEV_CAP_VOICE)),
- CAD(I2S_TX, 48, (SNDDEV_CAP_TX)),
- CAD(LP_FM_HEADSET_SPKR_STEREO_PLUS_HEADSET_SPKR_STEREO_RX, 57, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(FM_DIGITAL_HEADSET_SPKR_STEREO, 65, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(FM_DIGITAL_SPEAKER_PHONE_MONO, 67, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(FM_DIGITAL_BT_A2DP_SPKR, 69, \
- (SNDDEV_CAP_FM | SNDDEV_CAP_RX)),
- CAD(MAX, 80, SNDDEV_CAP_NONE),
-};
-#undef CAD
-
-static struct msm_cad_endpoints msm_device_cad_endpoints = {
- .endpoints = cad_endpoints_list,
- .num = sizeof(cad_endpoints_list) / sizeof(struct cad_endpoint)
-};
-
-static struct platform_device msm_device_cad = {
- .name = "msm_cad",
- .id = -1,
- .dev = {
- .platform_data = &msm_device_cad_endpoints
- },
-};
-
-#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))| \
- (1<<MSM_ADSP_CODEC_AC3)
-#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
-#define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
-#define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
- (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
- (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
- (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
- (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
- (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
-#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
-
-static unsigned int dec_concurrency_table[] = {
- /* Audio LP */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DMA)), 0,
- 0, 0, 0,
-
- /* Concurrency 1 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 2 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 3 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 4 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 5 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-
- /* Concurrency 6 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|
- (1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- 0, 0, 0, 0,
-
- /* Concurrency 7 */
- (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
- (DEC4_FORMAT),
-};
-
-#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
- .module_queueid = queueid, .module_decid = decid, \
- .nr_codec_support = nr_codec}
-
-static struct msm_adspdec_info dec_info_list[] = {
- DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
- DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
-};
-
-static struct msm_adspdec_database msm_device_adspdec_database = {
- .num_dec = ARRAY_SIZE(dec_info_list),
- .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
- ARRAY_SIZE(dec_info_list)),
- .dec_concurrency_table = dec_concurrency_table,
- .dec_info_list = dec_info_list,
-};
-
-static struct platform_device msm_device_adspdec = {
- .name = "msm_adspdec",
- .id = -1,
- .dev = {
- .platform_data = &msm_device_adspdec_database
- },
-};
-
static struct android_pmem_platform_data android_pmem_audio_pdata = {
.name = "pmem_audio",
.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index da98f34..5fc4806 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -746,6 +746,29 @@
},
};
+struct msm_mi2s_pdata apq_mi2s_data = {
+ .rx_sd_lines = MSM_MI2S_SD0,
+ .tx_sd_lines = MSM_MI2S_SD3,
+};
+
+struct platform_device apq_cpudai_mi2s = {
+ .name = "msm-dai-q6-mi2s",
+ .id = -1,
+ .dev = {
+ .platform_data = &apq_mi2s_data,
+ },
+};
+
+struct platform_device apq_cpudai_i2s_rx = {
+ .name = "msm-dai-q6",
+ .id = PRIMARY_I2S_RX,
+};
+
+struct platform_device apq_cpudai_i2s_tx = {
+ .name = "msm-dai-q6",
+ .id = PRIMARY_I2S_TX,
+};
+
struct platform_device apq_cpu_fe = {
.name = "msm-dai-fe",
.id = -1,
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 951177c..4a6271c 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -1688,8 +1688,8 @@
.ring_osc = 0,
.step_quot = ~0,
.tgt_volt_offset = 0,
- .Vmax = 1200000,
- .Vmin = 1000000,
+ .nom_Vmax = 1350000,
+ .nom_Vmin = 1250000,
.calibrated_uV = 1100000,
},
[TURBO_MODE] = {
@@ -1706,8 +1706,10 @@
.ring_osc = 0,
.step_quot = ~0,
.tgt_volt_offset = 0,
- .Vmax = 1350000,
- .Vmin = 1150000,
+ .turbo_Vmax = 1350000,
+ .turbo_Vmin = 950000,
+ .nom_Vmax = 1350000,
+ .nom_Vmin = 950000,
.calibrated_uV = 1300000,
},
};
@@ -1725,7 +1727,7 @@
uint32_t quot;
/* This formula is as per chip characterization data */
- quot = max_quot - ((max_freq / 10 - new_freq / 10) * 9) + 20;
+ quot = max_quot - ((max_freq / 10 - new_freq / 10) * 5);
return quot;
}
@@ -1814,7 +1816,7 @@
* This formula is used since available fuse bits in the chip are not
* enough to represent the value of maximum quot
*/
- msm_cpr_pdata.max_quot = cpr_info->turbo_quot * 10 + 610;
+ msm_cpr_pdata.max_quot = cpr_info->turbo_quot * 10 + 600;
/**
* Bits 4:0 of pvs_fuse provide mapping to the safe boot up voltage.
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 4d338b1..e66bf27 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -444,3 +444,8 @@
extern struct platform_device msm9615_device_acpuclk;
extern struct platform_device msm_gpio_device;
+
+extern struct platform_device apq_cpudai_mi2s;
+extern struct platform_device apq_cpudai_i2s_rx;
+extern struct platform_device apq_cpudai_i2s_tx;
+
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index aa33a0b..a7dc730 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -578,6 +578,8 @@
void msm_8974_very_early(void);
void msm_8974_init_gpiomux(void);
void msm9625_init_gpiomux(void);
+void msm_map_mpq8092_io(void);
+void mpq8092_init_gpiomux(void);
struct mmc_platform_data;
int msm_add_sdcc(unsigned int controller,
diff --git a/arch/arm/mach-msm/include/mach/irqs-8092.h b/arch/arm/mach-msm/include/mach/irqs-8092.h
new file mode 100644
index 0000000..ae9634e
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8092.h
@@ -0,0 +1,45 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8092_H
+#define __ASM_ARCH_MSM_IRQS_8092_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/*
+ * 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define AVS_SVICINT (GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
+#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
+/* PPI 15 is unused */
+
+#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
+#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
+#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
+
+#define NR_MSM_IRQS 1020 /* Should be 256 - but higher due to bug in sim */
+#define NR_GPIO_IRQS 146
+#define NR_QPNP_IRQS 32768 /* SPARSE_IRQ is required to support this */
+#define NR_BOARD_IRQS NR_QPNP_IRQS
+#define NR_TLMM_MSM_DIR_CONN_IRQ 8
+#define NR_MSM_GPIOS NR_GPIO_IRQS
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 143159e..cc1fb69 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -60,6 +60,8 @@
#if defined(CONFIG_ARCH_MSM8974)
#include "irqs-8974.h"
+#elif defined(CONFIG_ARCH_MPQ8092)
+#include "irqs-8092.h"
#elif defined(CONFIG_ARCH_MSM9615)
#include "irqs-9615.h"
#elif defined(CONFIG_ARCH_MSM9625)
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 6b7ad9a..acfbe4a 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -79,6 +79,7 @@
int platform_physical_active_pages(u64, u64);
int platform_physical_low_power_pages(u64, u64);
int msm_get_memory_type_from_name(const char *memtype_name);
+unsigned long get_ddr_size(void);
extern int (*change_memory_power)(u64, u64, int);
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8092.h b/arch/arm/mach-msm/include/mach/msm_iomap-8092.h
new file mode 100644
index 0000000..dec8a58
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8092.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8092_H
+#define __ASM_ARCH_MSM_IOMAP_8092_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * io desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MPQ8092_SHARED_RAM_PHYS 0x0FA00000
+
+#define MPQ8092_QGIC_DIST_PHYS 0xF9000000
+#define MPQ8092_QGIC_DIST_SIZE SZ_4K
+
+#define MPQ8092_QGIC_CPU_PHYS 0xF9002000
+#define MPQ8092_QGIC_CPU_SIZE SZ_4K
+
+#define MPQ8092_APCS_GCC_PHYS 0xF9011000
+#define MPQ8092_APCS_GCC_SIZE SZ_4K
+
+#define MPQ8092_TLMM_PHYS 0xFD510000
+#define MPQ8092_TLMM_SIZE SZ_16K
+
+#ifdef CONFIG_DEBUG_MPQ8092_UART
+#define MSM_DEBUG_UART_BASE IOMEM(0xFA71E000)
+#define MSM_DEBUG_UART_PHYS 0xF991E000
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 4c849d4..e961dfc 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -53,7 +53,7 @@
defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM7X27) || \
defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X01A) || \
defined(CONFIG_ARCH_MSM8625) || defined(CONFIG_ARCH_MSM7X30) || \
- defined(CONFIG_ARCH_MSM9625)
+ defined(CONFIG_ARCH_MSM9625) || defined(CONFIG_ARCH_MPQ8092)
/* Unified iomap */
@@ -118,6 +118,7 @@
#include "msm_iomap-9615.h"
#include "msm_iomap-8974.h"
#include "msm_iomap-9625.h"
+#include "msm_iomap-8092.h"
#else
/* Legacy single-target iomap */
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index a9598b1..7570fef 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -44,6 +44,11 @@
of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm9625")
#define machine_is_msm9625() \
of_machine_is_compatible("qcom,msm9625")
+#define early_machine_is_mpq8092() \
+ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,mpq8092")
+#define machine_is_mpq8092_sim() \
+ of_machine_is_compatible("qcom,mpq8092-sim")
+
#else
#define early_machine_is_msm8974() 0
#define machine_is_msm8974() 0
@@ -51,6 +56,8 @@
#define machine_is_msm8974_rumi() 0
#define early_machine_is_msm9625() 0
#define machine_is_msm9625() 0
+#define early_machine_is_mpq8092() 0
+#define machine_is_mpq8092_sim() 0
#endif
#define PLATFORM_SUBTYPE_SGLTE 6
@@ -80,7 +87,8 @@
MSM_CPU_8974,
MSM_CPU_8627,
MSM_CPU_8625,
- MSM_CPU_9625
+ MSM_CPU_9625,
+ MSM_CPU_8092
};
enum pmic_model {
@@ -362,4 +370,16 @@
#endif
}
+static inline int cpu_is_mpq8092(void)
+{
+#ifdef CONFIG_ARCH_MPQ8092
+ enum msm_cpu cpu = socinfo_get_msm_cpu();
+
+ BUG_ON(cpu == MSM_CPU_UNKNOWN);
+ return cpu == MSM_CPU_8092;
+#else
+ return 0;
+#endif
+
+}
#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 2035d3f..a2e46ca 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -477,3 +477,26 @@
msm_map_io(msm9625_io_desc, ARRAY_SIZE(msm9625_io_desc));
}
#endif /* CONFIG_ARCH_MSM9625 */
+
+#ifdef CONFIG_ARCH_MPQ8092
+static struct map_desc mpq8092_io_desc[] __initdata = {
+ MSM_CHIP_DEVICE(QGIC_DIST, MPQ8092),
+ MSM_CHIP_DEVICE(QGIC_CPU, MPQ8092),
+ MSM_CHIP_DEVICE(APCS_GCC, MPQ8092),
+ MSM_CHIP_DEVICE(TLMM, MPQ8092),
+ {
+ .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
+ .length = MSM_SHARED_RAM_SIZE,
+ .type = MT_DEVICE,
+ },
+#ifdef CONFIG_DEBUG_MPQ8092_UART
+ MSM_DEVICE(DEBUG_UART),
+#endif
+};
+
+void __init msm_map_mpq8092_io(void)
+{
+ msm_shared_ram_phys = MSM8974_MSM_SHARED_RAM_PHYS;
+ msm_map_io(mpq8092_io_desc, ARRAY_SIZE(mpq8092_io_desc));
+}
+#endif /* CONFIG_ARCH_MPQ8092 */
diff --git a/arch/arm/mach-msm/lpm_resources.c b/arch/arm/mach-msm/lpm_resources.c
index 7d432f4..48d31f3 100644
--- a/arch/arm/mach-msm/lpm_resources.c
+++ b/arch/arm/mach-msm/lpm_resources.c
@@ -698,7 +698,7 @@
case CPU_DEAD_FROZEN:
case CPU_DEAD:
if (num_online_cpus() == 1)
- rs->rs_data.value = MSM_LPM_L2_CACHE_GDHS;
+ rs->rs_data.value = MSM_LPM_L2_CACHE_HSFS_OPEN;
break;
}
return NOTIFY_OK;
diff --git a/arch/arm/mach-msm/memory.c b/arch/arm/mach-msm/memory.c
index 4a2fd7c..74c1c4a 100644
--- a/arch/arm/mach-msm/memory.c
+++ b/arch/arm/mach-msm/memory.c
@@ -505,3 +505,14 @@
out:
return 0;
}
+
+unsigned long get_ddr_size(void)
+{
+ unsigned int i;
+ unsigned long ret = 0;
+
+ for (i = 0; i < meminfo.nr_banks; i++)
+ ret += meminfo.bank[i].size;
+
+ return ret;
+}
diff --git a/arch/arm/mach-msm/msm_cpr.c b/arch/arm/mach-msm/msm_cpr.c
index b6c05f4..a61bd20 100644
--- a/arch/arm/mach-msm/msm_cpr.c
+++ b/arch/arm/mach-msm/msm_cpr.c
@@ -56,6 +56,8 @@
bool max_volt_set;
void __iomem *base;
unsigned int irq;
+ uint32_t cur_Vmin;
+ uint32_t cur_Vmax;
struct mutex cpr_mutex;
struct regulator *vreg_cx;
const struct msm_cpr_config *config;
@@ -189,7 +191,7 @@
* voltage, offset is always subtracted from it.
*
*/
- level_uV = chip_data->Vmax -
+ level_uV = chip_data->turbo_Vmax -
(chip_data->tgt_volt_offset * cpr->vp->step_size);
pr_debug("tgt_volt_uV = %d\n", level_uV);
@@ -319,8 +321,8 @@
* freq switch handler and CPR interrupt handler here
*/
/* Set New PMIC voltage */
- set_volt_uV = (new_volt < chip_data->Vmax ? new_volt
- : chip_data->Vmax);
+ set_volt_uV = (new_volt < cpr->cur_Vmax ? new_volt
+ : cpr->cur_Vmax);
rc = regulator_set_voltage(cpr->vreg_cx, set_volt_uV,
set_volt_uV);
if (rc) {
@@ -331,13 +333,7 @@
}
pr_info("(railway_voltage: %d uV)\n", set_volt_uV);
- cpr->max_volt_set = (set_volt_uV == chip_data->Vmax) ? 1 : 0;
-
- /**
- * Save the new calibrated voltage to be re-used
- * whenever we return to same mode after a mode switch.
- */
- chip_data->calibrated_uV = set_volt_uV;
+ cpr->max_volt_set = (set_volt_uV == cpr->cur_Vmax) ? 1 : 0;
/* Clear all the interrupts */
cpr_write_reg(cpr, RBIF_IRQ_CLEAR, ALL_CPR_IRQ);
@@ -367,8 +363,8 @@
* freq switch handler and CPR interrupt handler here
*/
/* Set New PMIC volt */
- set_volt_uV = (new_volt > chip_data->Vmin ? new_volt
- : chip_data->Vmin);
+ set_volt_uV = (new_volt > cpr->cur_Vmin ? new_volt
+ : cpr->cur_Vmin);
rc = regulator_set_voltage(cpr->vreg_cx, set_volt_uV,
set_volt_uV);
if (rc) {
@@ -381,16 +377,10 @@
cpr->max_volt_set = 0;
- /**
- * Save the new calibrated voltage to be re-used
- * whenever we return to same mode after a mode switch.
- */
- chip_data->calibrated_uV = set_volt_uV;
-
/* Clear all the interrupts */
cpr_write_reg(cpr, RBIF_IRQ_CLEAR, ALL_CPR_IRQ);
- if (new_volt <= chip_data->Vmin) {
+ if (new_volt <= cpr->cur_Vmin) {
/*
* Disable down interrupt to App after we hit Vmin
* It shall be enabled after we service an up interrupt
@@ -422,7 +412,8 @@
chip_data = &cpr->config->cpr_mode_data[cpr->cpr_mode];
error_step = cpr_read_reg(cpr, RBCPR_RESULT_0) >> 2;
error_step &= 0xF;
- curr_volt = chip_data->calibrated_uV;
+
+ curr_volt = regulator_get_voltage(cpr->vreg_cx);
if (action == UP) {
/* Clear IRQ, ACK and return if Vdd already at Vmax */
@@ -580,7 +571,7 @@
{
struct msm_cpr *cpr = container_of(nb, struct msm_cpr, freq_transition);
struct cpufreq_freqs *freqs = data;
- uint32_t quot, new_freq;
+ uint32_t quot, new_freq, ctl_reg;
switch (val) {
case CPUFREQ_PRECHANGE:
@@ -604,13 +595,20 @@
case CPUFREQ_POSTCHANGE:
pr_debug("post freq change notification to cpr\n");
+ ctl_reg = cpr_read_reg(cpr, RBCPR_CTL);
/**
* As per chip characterization data, use max nominal freq
* to calculate quot for all lower frequencies too
*/
- new_freq = (freqs->new > cpr->config->max_nom_freq)
- ? freqs->new
- : cpr->config->max_nom_freq;
+ if (freqs->new > cpr->config->max_nom_freq) {
+ new_freq = freqs->new;
+ cpr->cur_Vmin = cpr->config->cpr_mode_data[1].turbo_Vmin;
+ cpr->cur_Vmax = cpr->config->cpr_mode_data[1].turbo_Vmax;
+ } else {
+ new_freq = cpr->config->max_nom_freq;
+ cpr->cur_Vmin = cpr->config->cpr_mode_data[1].nom_Vmin;
+ cpr->cur_Vmax = cpr->config->cpr_mode_data[1].nom_Vmax;
+ }
/* Configure CPR for the new frequency */
quot = cpr->config->get_quot(cpr->config->max_quot,
@@ -630,6 +628,14 @@
* state if vdd had hit Vmax / Vmin earlier
*/
cpr_irq_set(cpr, INT_MASK & ~MID_INT, 1);
+
+ /**
+ * Clear the auto NACK down bit if enabled in the freq.
+ * transition phase.
+ */
+ if (ctl_reg & SW_AUTO_CONT_NACK_DN_EN)
+ cpr_modify_reg(cpr, RBCPR_CTL,
+ SW_AUTO_CONT_NACK_DN_EN_M, 0);
pr_debug("RBIF_IRQ_EN(0): 0x%x\n",
cpr_read_reg(cpr, RBIF_IRQ_EN(cpr->config->irq_line)));
pr_debug("RBCPR_CTL: 0x%x\n",
@@ -753,6 +759,10 @@
/* Initialize platform_data */
cpr->config = pdata;
+ /* Set initial Vmin,Vmax equal to turbo */
+ cpr->cur_Vmin = cpr->config->cpr_mode_data[1].turbo_Vmin;
+ cpr->cur_Vmax = cpr->config->cpr_mode_data[1].turbo_Vmax;
+
cpr_pdev = pdev;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/arch/arm/mach-msm/msm_cpr.h b/arch/arm/mach-msm/msm_cpr.h
index cb665b7..e690c63 100644
--- a/arch/arm/mach-msm/msm_cpr.h
+++ b/arch/arm/mach-msm/msm_cpr.h
@@ -154,8 +154,10 @@
int ring_osc;
int32_t tgt_volt_offset;
uint32_t step_quot;
- uint32_t Vmax;
- uint32_t Vmin;
+ uint32_t turbo_Vmax;
+ uint32_t turbo_Vmin;
+ uint32_t nom_Vmax;
+ uint32_t nom_Vmin;
uint32_t calibrated_uV;
};
diff --git a/arch/arm/mach-msm/msm_rq_stats.c b/arch/arm/mach-msm/msm_rq_stats.c
index 2ea7ed3..ea08f4b 100644
--- a/arch/arm/mach-msm/msm_rq_stats.c
+++ b/arch/arm/mach-msm/msm_rq_stats.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -11,7 +11,7 @@
*
*/
/*
- * Qualcomm MSM Runqueue Stats Interface for Userspace
+ * Qualcomm MSM Runqueue Stats and cpu utilization Interface for Userspace
*/
#include <linux/kernel.h>
#include <linux/init.h>
@@ -26,12 +26,183 @@
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/rq_stats.h>
+#include <linux/cpufreq.h>
+#include <linux/kernel_stat.h>
+#include <linux/tick.h>
#include <asm/smp_plat.h>
#define MAX_LONG_SIZE 24
#define DEFAULT_RQ_POLL_JIFFIES 1
#define DEFAULT_DEF_TIMER_JIFFIES 5
+struct notifier_block freq_transition;
+struct notifier_block cpu_hotplug;
+
+struct cpu_load_data {
+ cputime64_t prev_cpu_idle;
+ cputime64_t prev_cpu_wall;
+ cputime64_t prev_cpu_iowait;
+ unsigned int avg_load_maxfreq;
+ unsigned int samples;
+ unsigned int window_size;
+ unsigned int cur_freq;
+ unsigned int policy_max;
+ cpumask_var_t related_cpus;
+ struct mutex cpu_load_mutex;
+};
+
+static DEFINE_PER_CPU(struct cpu_load_data, cpuload);
+
+static inline u64 get_cpu_idle_time_jiffy(unsigned int cpu, u64 *wall)
+{
+ u64 idle_time;
+ u64 cur_wall_time;
+ u64 busy_time;
+
+ cur_wall_time = jiffies64_to_cputime64(get_jiffies_64());
+
+ busy_time = kcpustat_cpu(cpu).cpustat[CPUTIME_USER];
+ busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_SYSTEM];
+ busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_IRQ];
+ busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_SOFTIRQ];
+ busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_STEAL];
+ busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_NICE];
+
+ idle_time = cur_wall_time - busy_time;
+ if (wall)
+ *wall = jiffies_to_usecs(cur_wall_time);
+
+ return jiffies_to_usecs(idle_time);
+}
+
+static inline cputime64_t get_cpu_idle_time(unsigned int cpu, cputime64_t *wall)
+{
+ u64 idle_time = get_cpu_idle_time_us(cpu, NULL);
+
+ if (idle_time == -1ULL)
+ return get_cpu_idle_time_jiffy(cpu, wall);
+ else
+ idle_time += get_cpu_iowait_time_us(cpu, wall);
+
+ return idle_time;
+}
+
+static inline cputime64_t get_cpu_iowait_time(unsigned int cpu,
+ cputime64_t *wall)
+{
+ u64 iowait_time = get_cpu_iowait_time_us(cpu, wall);
+
+ if (iowait_time == -1ULL)
+ return 0;
+
+ return iowait_time;
+}
+
+static int update_average_load(unsigned int freq, unsigned int cpu)
+{
+
+ struct cpu_load_data *pcpu = &per_cpu(cpuload, cpu);
+ cputime64_t cur_wall_time, cur_idle_time, cur_iowait_time;
+ unsigned int idle_time, wall_time, iowait_time;
+ unsigned int cur_load, load_at_max_freq;
+
+ cur_idle_time = get_cpu_idle_time(cpu, &cur_wall_time);
+ cur_iowait_time = get_cpu_iowait_time(cpu, &cur_wall_time);
+
+ wall_time = (unsigned int) (cur_wall_time - pcpu->prev_cpu_wall);
+ pcpu->prev_cpu_wall = cur_wall_time;
+
+ idle_time = (unsigned int) (cur_idle_time - pcpu->prev_cpu_idle);
+ pcpu->prev_cpu_idle = cur_idle_time;
+
+ iowait_time = (unsigned int) (cur_iowait_time - pcpu->prev_cpu_iowait);
+ pcpu->prev_cpu_iowait = cur_iowait_time;
+
+ if (idle_time >= iowait_time)
+ idle_time -= iowait_time;
+
+ if (unlikely(!wall_time || wall_time < idle_time))
+ return 0;
+
+ cur_load = 100 * (wall_time - idle_time) / wall_time;
+
+ /* Calculate the scaled load across CPU */
+ load_at_max_freq = (cur_load * freq) / pcpu->policy_max;
+
+ if (!pcpu->avg_load_maxfreq) {
+ /* This is the first sample in this window*/
+ pcpu->avg_load_maxfreq = load_at_max_freq;
+ pcpu->window_size = wall_time;
+ } else {
+ /*
+ * The is already a sample available in this window.
+ * Compute weighted average with prev entry, so that we get
+ * the precise weighted load.
+ */
+ pcpu->avg_load_maxfreq =
+ ((pcpu->avg_load_maxfreq * pcpu->window_size) +
+ (load_at_max_freq * wall_time)) /
+ (wall_time + pcpu->window_size);
+
+ pcpu->window_size += wall_time;
+ }
+
+ return 0;
+}
+
+static unsigned int report_load_at_max_freq(void)
+{
+ int cpu;
+ struct cpu_load_data *pcpu;
+ unsigned int total_load = 0;
+
+ for_each_online_cpu(cpu) {
+ pcpu = &per_cpu(cpuload, cpu);
+ mutex_lock(&pcpu->cpu_load_mutex);
+ update_average_load(pcpu->cur_freq, cpu);
+ total_load += pcpu->avg_load_maxfreq;
+ pcpu->avg_load_maxfreq = 0;
+ mutex_unlock(&pcpu->cpu_load_mutex);
+ }
+ return total_load;
+}
+
+static int cpufreq_transition_handler(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ struct cpufreq_freqs *freqs = data;
+ struct cpu_load_data *this_cpu = &per_cpu(cpuload, freqs->cpu);
+ int j;
+
+ switch (val) {
+ case CPUFREQ_POSTCHANGE:
+ for_each_cpu(j, this_cpu->related_cpus) {
+ struct cpu_load_data *pcpu = &per_cpu(cpuload, j);
+ mutex_lock(&pcpu->cpu_load_mutex);
+ update_average_load(freqs->old, freqs->cpu);
+ pcpu->cur_freq = freqs->new;
+ mutex_unlock(&pcpu->cpu_load_mutex);
+ }
+ break;
+ }
+ return 0;
+}
+
+static int cpu_hotplug_handler(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ unsigned int cpu = (unsigned long)data;
+ struct cpu_load_data *this_cpu = &per_cpu(cpuload, cpu);
+
+ switch (val) {
+ case CPU_ONLINE:
+ case CPU_ONLINE_FROZEN:
+ this_cpu->avg_load_maxfreq = 0;
+ }
+
+ return NOTIFY_OK;
+}
+
static void def_work_fn(struct work_struct *work)
{
int64_t diff;
@@ -121,7 +292,18 @@
__ATTR(def_timer_ms, S_IWUSR | S_IRUSR, show_def_timer_ms,
store_def_timer_ms);
+static ssize_t show_cpu_normalized_load(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return snprintf(buf, MAX_LONG_SIZE, "%u\n", report_load_at_max_freq());
+}
+
+static struct kobj_attribute cpu_normalized_load_attr =
+ __ATTR(cpu_normalized_load, S_IWUSR | S_IRUSR, show_cpu_normalized_load,
+ NULL);
+
static struct attribute *rq_attrs[] = {
+ &cpu_normalized_load_attr.attr,
&def_timer_ms_attr.attr,
&run_queue_avg_attr.attr,
&run_queue_poll_ms_attr.attr,
@@ -157,7 +339,8 @@
static int __init msm_rq_stats_init(void)
{
int ret;
-
+ int i;
+ struct cpufreq_policy cpu_policy;
/* Bail out if this is not an SMP Target */
if (!is_smp()) {
rq_info.init = 0;
@@ -175,6 +358,20 @@
ret = init_rq_attribs();
rq_info.init = 1;
+
+ for_each_possible_cpu(i) {
+ struct cpu_load_data *pcpu = &per_cpu(cpuload, i);
+ mutex_init(&pcpu->cpu_load_mutex);
+ cpufreq_get_policy(&cpu_policy, i);
+ pcpu->policy_max = cpu_policy.cpuinfo.max_freq;
+ cpumask_copy(pcpu->related_cpus, cpu_policy.cpus);
+ }
+ freq_transition.notifier_call = cpufreq_transition_handler;
+ cpu_hotplug.notifier_call = cpu_hotplug_handler;
+ cpufreq_register_notifier(&freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ register_hotcpu_notifier(&cpu_hotplug);
+
return ret;
}
late_initcall(msm_rq_stats_init);
diff --git a/arch/arm/mach-msm/msm_vp.c b/arch/arm/mach-msm/msm_vp.c
index 2569474..4404f0a 100644
--- a/arch/arm/mach-msm/msm_vp.c
+++ b/arch/arm/mach-msm/msm_vp.c
@@ -53,8 +53,11 @@
* 750mV is minimum voltage of MSMC2 smps.
*/
#define VOLT_TO_BIT(x) (((x-750)/(12500/1000)) + 0x20)
-#define VREG_VREF_SEL (1 << 5)
-#define VREG_PD_EN (1 << 6)
+#define VREG_VREF_SEL (1 << 5)
+#define VREG_VREF_SEL_SHIFT (0x5)
+#define VREG_PD_EN (1 << 6)
+#define VREG_PD_EN_SHIFT (0x6)
+#define VREG_LVL_M (0x1F)
/**
* struct msm_vp - Structure for VP
@@ -85,8 +88,8 @@
* in corresponding PLEVEL register.
*/
cur_plevel = readl_relaxed(VDD_APC_PLEVEL(perf_level));
- /* clear lower 6 bits */
- cur_plevel &= ~0x3F;
+ /* clear lower 7 bits */
+ cur_plevel &= ~(0x7F);
cur_plevel |= (plevel | VREG_VREF_SEL);
if (fine_step_volt >= 12500)
cur_plevel |= VREG_PD_EN;
@@ -113,9 +116,21 @@
static int vp_reg_get_voltage(struct regulator_dev *rdev)
{
- struct msm_vp *vp = rdev_get_drvdata(rdev);
+ uint32_t reg_val, perf_level, vlevel, cur_plevel;
+ uint32_t vref_sel, pd_en;
+ uint32_t cur_voltage;
- return MV_TO_UV(vp->current_voltage);
+ reg_val = readl_relaxed(VDD_SVS_PLEVEL_ADDR);
+ perf_level = reg_val & 0x07;
+
+ cur_plevel = readl_relaxed(VDD_APC_PLEVEL(perf_level));
+ vref_sel = (cur_plevel >> VREG_VREF_SEL_SHIFT) & 0x1;
+ pd_en = (cur_plevel >> VREG_PD_EN_SHIFT) & 0x1;
+ vlevel = cur_plevel & VREG_LVL_M;
+
+ cur_voltage = (750000 + (pd_en * 12500) +
+ (vlevel * 25000)) * (2 - vref_sel);
+ return cur_voltage;
}
static int vp_reg_enable(struct regulator_dev *rdev)
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index f6b44c6..b2681b7 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -84,7 +84,7 @@
if (!base_ptr)
return -ENODEV;
- if (machine_is_msm8974_sim()) {
+ if (machine_is_msm8974_sim() || machine_is_mpq8092_sim()) {
writel_relaxed(0x800, base_ptr+0x04);
writel_relaxed(0x3FFF, base_ptr+0x14);
}
@@ -159,7 +159,7 @@
if (cpu_is_msm8x60())
return scorpion_release_secondary();
- if (machine_is_msm8974_sim())
+ if (machine_is_msm8974_sim() || machine_is_mpq8092_sim())
return krait_release_secondary_sim(0xf9088000, cpu);
if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_lpa.c b/arch/arm/mach-msm/qdsp6v2/audio_lpa.c
index cbfee70..f89eb18 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_lpa.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_lpa.c
@@ -707,6 +707,15 @@
case RESET_EVENTS:
reset_device();
break;
+ case APR_BASIC_RSP_RESULT:
+ switch (payload[0]) {
+ case ASM_STREAM_CMD_CLOSE:
+ audlpa_unmap_ion_region(audio);
+ break;
+ default:
+ break;
+ }
+ break;
default:
break;
}
@@ -1126,7 +1135,6 @@
if (audio->out_enabled)
audlpa_async_flush(audio);
audio->wflush = 0;
- audlpa_unmap_ion_region(audio);
audio_disable(audio);
msm_clear_session_id(audio->ac->session);
auddev_unregister_evt_listner(AUDDEV_CLNT_DEC, audio->ac->session);
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
index e9f5c0a..1937aafc 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
@@ -436,7 +436,7 @@
return;
}
-static void audio_aio_unmap_ion_region(struct q6audio_aio *audio)
+void audio_aio_unmap_ion_region(struct q6audio_aio *audio)
{
struct audio_aio_ion_region *region;
struct list_head *ptr, *next;
@@ -468,7 +468,6 @@
audio->wflush = 0;
audio->drv_ops.out_flush(audio);
audio->drv_ops.in_flush(audio);
- audio_aio_unmap_ion_region(audio);
audio_aio_disable(audio);
audio_aio_reset_ion_region(audio);
ion_client_destroy(audio->client);
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
index 811baf0..4401f6f 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
@@ -210,6 +210,7 @@
int audio_aio_fsync(struct file *file, loff_t start, loff_t end, int datasync);
void audio_aio_async_out_flush(struct q6audio_aio *audio);
void audio_aio_async_in_flush(struct q6audio_aio *audio);
+void audio_aio_unmap_ion_region(struct q6audio_aio *audio);
#ifdef CONFIG_DEBUG_FS
ssize_t audio_aio_debug_open(struct inode *inode, struct file *file);
ssize_t audio_aio_debug_read(struct file *file, char __user *buf,
diff --git a/arch/arm/mach-msm/qdsp6v2/q6audio_v1_aio.c b/arch/arm/mach-msm/qdsp6v2/q6audio_v1_aio.c
index 078eea8..8304cb8 100644
--- a/arch/arm/mach-msm/qdsp6v2/q6audio_v1_aio.c
+++ b/arch/arm/mach-msm/qdsp6v2/q6audio_v1_aio.c
@@ -37,6 +37,7 @@
case ASM_STREAM_CMD_SET_ENCDEC_PARAM:
case ASM_DATA_EVENT_SR_CM_CHANGE_NOTIFY:
case ASM_DATA_EVENT_ENC_SR_CM_NOTIFY:
+ case APR_BASIC_RSP_RESULT:
audio_aio_cb(opcode, token, payload, audio);
break;
default:
@@ -106,6 +107,15 @@
e_payload.stream_info.sample_rate = audio->pcm_cfg.sample_rate;
audio_aio_post_event(audio, AUDIO_EVENT_STREAM_INFO, e_payload);
break;
+ case APR_BASIC_RSP_RESULT:
+ switch (payload[0]) {
+ case ASM_STREAM_CMD_CLOSE:
+ audio_aio_unmap_ion_region(audio);
+ break;
+ default:
+ break;
+ }
+ break;
default:
break;
}
diff --git a/arch/arm/mach-msm/qdsp6v2/rtac.c b/arch/arm/mach-msm/qdsp6v2/rtac.c
index 8808375..82aa14c 100644
--- a/arch/arm/mach-msm/qdsp6v2/rtac.c
+++ b/arch/arm/mach-msm/qdsp6v2/rtac.c
@@ -768,7 +768,8 @@
goto done;
}
- if (copy_from_user(&payload_size, buf + sizeof(u32), sizeof(u32))) {
+ if (copy_from_user(&payload_size, buf + sizeof(payload_size),
+ sizeof(payload_size))) {
pr_err("%s: Could not copy payload size from user buffer\n",
__func__);
goto done;
@@ -780,7 +781,8 @@
goto done;
}
- if (copy_from_user(&dest_port, buf + 2 * sizeof(u32), sizeof(u32))) {
+ if (copy_from_user(&dest_port, buf + 2 * sizeof(dest_port),
+ sizeof(dest_port))) {
pr_err("%s: Could not copy port id from user buffer\n",
__func__);
goto done;
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index ea0b7a3..c614086 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -280,6 +280,9 @@
[143] = MSM_CPU_8930AA,
[144] = MSM_CPU_8930AA,
+ /* 8092 IDs */
+ [146] = MSM_CPU_8092,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
considered as unknown CPU. */
@@ -715,6 +718,11 @@
sizeof(dummy_socinfo.build_id));
} else if (machine_is_msm8625_rumi3())
dummy_socinfo.id = 127;
+ else if (early_machine_is_mpq8092()) {
+ dummy_socinfo.id = 146;
+ strlcpy(dummy_socinfo.build_id, "mpq8092 - ",
+ sizeof(dummy_socinfo.build_id));
+ }
strlcat(dummy_socinfo.build_id, "Dummy socinfo",
sizeof(dummy_socinfo.build_id));
return (void *) &dummy_socinfo;
diff --git a/arch/arm/mach-msm/subsystem_restart.c b/arch/arm/mach-msm/subsystem_restart.c
index fdde328..7818c49 100644
--- a/arch/arm/mach-msm/subsystem_restart.c
+++ b/arch/arm/mach-msm/subsystem_restart.c
@@ -572,7 +572,6 @@
if (restart_orders == NULL || n_restart_orders < 1) {
WARN_ON(1);
- return -EINVAL;
}
return 0;
diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c
index 989bd00..f834ea8 100644
--- a/drivers/cpufreq/cpufreq_interactive.c
+++ b/drivers/cpufreq/cpufreq_interactive.c
@@ -845,6 +845,9 @@
pcpu->hispeed_validate_time =
pcpu->target_set_time;
pcpu->governor_enabled = 1;
+ pcpu->idle_exit_time = pcpu->target_set_time;
+ mod_timer(&pcpu->cpu_timer,
+ jiffies + usecs_to_jiffies(timer_rate));
smp_wmb();
}
diff --git a/drivers/gpu/msm/a3xx_reg.h b/drivers/gpu/msm/a3xx_reg.h
index 6fe316a..05c7967 100644
--- a/drivers/gpu/msm/a3xx_reg.h
+++ b/drivers/gpu/msm/a3xx_reg.h
@@ -77,6 +77,9 @@
#define A3XX_CP_PFP_UCODE_DATA 0x1CA
#define A3XX_CP_ROQ_ADDR 0x1CC
#define A3XX_CP_ROQ_DATA 0x1CD
+#define A3XX_CP_MERCIU_ADDR 0x1D1
+#define A3XX_CP_MERCIU_DATA 0x1D2
+#define A3XX_CP_MERCIU_DATA2 0x1D3
#define A3XX_CP_MEQ_ADDR 0x1DA
#define A3XX_CP_MEQ_DATA 0x1DB
#define A3XX_CP_HW_FAULT 0x45C
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index d99d398..7317702 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -1094,7 +1094,7 @@
static int
adreno_ocmem_gmem_malloc(struct adreno_device *adreno_dev)
{
- if (adreno_dev->gpurev != ADRENO_REV_A330)
+ if (!adreno_is_a330(adreno_dev))
return 0;
/* OCMEM is only needed once, do not support consective allocation */
@@ -1115,7 +1115,7 @@
static void
adreno_ocmem_gmem_free(struct adreno_device *adreno_dev)
{
- if (adreno_dev->gpurev != ADRENO_REV_A330)
+ if (!adreno_is_a330(adreno_dev))
return;
if (adreno_dev->ocmem_hdl == NULL)
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index d151255..66402fe 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -165,6 +165,9 @@
extern const unsigned int a3xx_registers[];
extern const unsigned int a3xx_registers_count;
+extern const unsigned int a330_registers[];
+extern const unsigned int a330_registers_count;
+
extern unsigned int hang_detect_regs[];
extern const unsigned int hang_detect_regs_count;
@@ -252,6 +255,11 @@
return (adreno_dev->gpurev == ADRENO_REV_A320);
}
+static inline int adreno_is_a330(struct adreno_device *adreno_dev)
+{
+ return (adreno_dev->gpurev == ADRENO_REV_A330);
+}
+
static inline int adreno_rb_ctxtswitch(unsigned int *cmd)
{
return (cmd[0] == cp_nop_packet(1) &&
diff --git a/drivers/gpu/msm/adreno_a2xx_snapshot.c b/drivers/gpu/msm/adreno_a2xx_snapshot.c
index 2368264..282440c 100644
--- a/drivers/gpu/msm/adreno_a2xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a2xx_snapshot.c
@@ -232,6 +232,7 @@
int *remain, int hang)
{
struct kgsl_device *device = &adreno_dev->dev;
+ struct kgsl_snapshot_registers_list list;
struct kgsl_snapshot_registers regs;
unsigned int pmoverride;
@@ -248,10 +249,13 @@
regs.count = a225_registers_count;
}
+ list.registers = ®s;
+ list.count = 1;
+
/* Master set of (non debug) registers */
snapshot = kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain,
- kgsl_snapshot_dump_regs, ®s);
+ kgsl_snapshot_dump_regs, &list);
/* CP_STATE_DEBUG indexed registers */
snapshot = kgsl_snapshot_indexed_registers(device, snapshot,
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index 4b3263d..4ae2fa8 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -69,6 +69,14 @@
const unsigned int a3xx_registers_count = ARRAY_SIZE(a3xx_registers) / 2;
+/* The set of additional registers to be dumped for A330 */
+
+const unsigned int a330_registers[] = {
+ 0x1d0, 0x1d0, 0x1d4, 0x1d4, 0x453, 0x453,
+};
+
+const unsigned int a330_registers_count = ARRAY_SIZE(a330_registers) / 2;
+
/* Simple macro to facilitate bit setting in the gmem2sys and sys2gmem
* functions.
*/
@@ -2698,7 +2706,7 @@
struct kgsl_device *device = &adreno_dev->dev;
/* Set up 16 deep read/write request queues */
- if (adreno_dev->gpurev == ADRENO_REV_A330) {
+ if (adreno_is_a330(adreno_dev)) {
adreno_regwrite(device, A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
adreno_regwrite(device, A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
adreno_regwrite(device, A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);
@@ -2781,7 +2789,7 @@
A3XX_RBBM_CLOCK_CTL_DEFAULT);
/* Set the OCMEM base address for A330 */
- if (adreno_dev->gpurev == ADRENO_REV_A330) {
+ if (adreno_is_a330(adreno_dev)) {
adreno_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
(unsigned int)(adreno_dev->ocmem_base >> 14));
}
diff --git a/drivers/gpu/msm/adreno_a3xx_snapshot.c b/drivers/gpu/msm/adreno_a3xx_snapshot.c
index a3bee4d..d49fc23 100644
--- a/drivers/gpu/msm/adreno_a3xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a3xx_snapshot.c
@@ -156,28 +156,68 @@
return DEBUG_SECTION_SZ(size);
}
-#define CP_ROQ_SIZE 128
+/* This is the ROQ buffer size on both the A305 and A320 */
+#define A320_CP_ROQ_SIZE 128
+/* This is the ROQ buffer size on the A330 */
+#define A330_CP_ROQ_SIZE 512
static int a3xx_snapshot_cp_roq(struct kgsl_device *device, void *snapshot,
int remain, void *priv)
{
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct kgsl_snapshot_debug *header = snapshot;
unsigned int *data = snapshot + sizeof(*header);
- int i;
+ int i, size;
- if (remain < DEBUG_SECTION_SZ(CP_ROQ_SIZE)) {
+ /* The size of the ROQ buffer is core dependent */
+ size = adreno_is_a330(adreno_dev) ?
+ A330_CP_ROQ_SIZE : A320_CP_ROQ_SIZE;
+
+ if (remain < DEBUG_SECTION_SZ(size)) {
SNAPSHOT_ERR_NOMEM(device, "CP ROQ DEBUG");
return 0;
}
header->type = SNAPSHOT_DEBUG_CP_ROQ;
- header->size = CP_ROQ_SIZE;
+ header->size = size;
adreno_regwrite(device, A3XX_CP_ROQ_ADDR, 0x0);
- for (i = 0; i < CP_ROQ_SIZE; i++)
+ for (i = 0; i < size; i++)
adreno_regread(device, A3XX_CP_ROQ_DATA, &data[i]);
- return DEBUG_SECTION_SZ(CP_ROQ_SIZE);
+ return DEBUG_SECTION_SZ(size);
+}
+
+#define A330_CP_MERCIU_QUEUE_SIZE 32
+
+static int a330_snapshot_cp_merciu(struct kgsl_device *device, void *snapshot,
+ int remain, void *priv)
+{
+ struct kgsl_snapshot_debug *header = snapshot;
+ unsigned int *data = snapshot + sizeof(*header);
+ int i, size;
+
+ /* The MERCIU data is two dwords per entry */
+ size = A330_CP_MERCIU_QUEUE_SIZE << 1;
+
+ if (remain < DEBUG_SECTION_SZ(size)) {
+ SNAPSHOT_ERR_NOMEM(device, "CP MERCIU DEBUG");
+ return 0;
+ }
+
+ header->type = SNAPSHOT_DEBUG_CP_MERCIU;
+ header->size = size;
+
+ adreno_regwrite(device, A3XX_CP_MERCIU_ADDR, 0x0);
+
+ for (i = 0; i < A330_CP_MERCIU_QUEUE_SIZE; i++) {
+ adreno_regread(device, A3XX_CP_MERCIU_DATA,
+ &data[(i * 2)]);
+ adreno_regread(device, A3XX_CP_MERCIU_DATA2,
+ &data[(i * 2) + 1]);
+ }
+
+ return DEBUG_SECTION_SZ(size);
}
#define DEBUGFS_BLOCK_SIZE 0x40
@@ -265,15 +305,26 @@
int *remain, int hang)
{
struct kgsl_device *device = &adreno_dev->dev;
- struct kgsl_snapshot_registers regs;
+ struct kgsl_snapshot_registers_list list;
+ struct kgsl_snapshot_registers regs[2];
- regs.regs = (unsigned int *) a3xx_registers;
- regs.count = a3xx_registers_count;
+ regs[0].regs = (unsigned int *) a3xx_registers;
+ regs[0].count = a3xx_registers_count;
+
+ list.registers = regs;
+ list.count = 1;
+
+ /* For A330, append the additional list of new registers to grab */
+ if (adreno_is_a330(adreno_dev)) {
+ regs[1].regs = (unsigned int *) a330_registers;
+ regs[1].count = a330_registers_count;
+ list.count++;
+ }
/* Master set of (non debug) registers */
snapshot = kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain,
- kgsl_snapshot_dump_regs, ®s);
+ kgsl_snapshot_dump_regs, &list);
/* CP_STATE_DEBUG indexed registers */
snapshot = kgsl_snapshot_indexed_registers(device, snapshot,
@@ -322,6 +373,12 @@
KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain,
a3xx_snapshot_cp_roq, NULL);
+ if (adreno_is_a330(adreno_dev)) {
+ snapshot = kgsl_snapshot_add_section(device,
+ KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain,
+ a330_snapshot_cp_merciu, NULL);
+ }
+
snapshot = a3xx_snapshot_debugbus(device, snapshot, remain);
/* Enable Clock gating */
diff --git a/drivers/gpu/msm/adreno_postmortem.c b/drivers/gpu/msm/adreno_postmortem.c
index 261e518..620b82c 100644
--- a/drivers/gpu/msm/adreno_postmortem.c
+++ b/drivers/gpu/msm/adreno_postmortem.c
@@ -869,9 +869,14 @@
else if (adreno_is_a225(adreno_dev))
adreno_dump_regs(device, a225_registers,
a225_registers_count);
- else if (adreno_is_a3xx(adreno_dev))
+ else if (adreno_is_a3xx(adreno_dev)) {
adreno_dump_regs(device, a3xx_registers,
a3xx_registers_count);
+
+ if (adreno_is_a330(adreno_dev))
+ adreno_dump_regs(device, a330_registers,
+ a330_registers_count);
+ }
}
error_vfree:
diff --git a/drivers/gpu/msm/kgsl_pwrscale_msm.c b/drivers/gpu/msm/kgsl_pwrscale_msm.c
index c6f8b1b..879b381 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_msm.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_msm.c
@@ -127,6 +127,28 @@
return;
}
+static void msm_remove_io_fraction(struct kgsl_device *device)
+{
+ int i;
+ struct kgsl_pwrctrl *pwr = &device->pwrctrl;
+
+ for (i = 0; i < pwr->num_pwrlevels; i++)
+ pwr->pwrlevels[i].io_fraction = 100;
+
+}
+
+static void msm_restore_io_fraction(struct kgsl_device *device)
+{
+ int i;
+ struct kgsl_device_platform_data *pdata =
+ kgsl_device_get_drvdata(device);
+ struct kgsl_pwrctrl *pwr = &device->pwrctrl;
+
+ for (i = 0; i < pdata->num_levels; i++)
+ pwr->pwrlevels[i].io_fraction =
+ pdata->pwrlevel[i].io_fraction;
+}
+
static int msm_init(struct kgsl_device *device,
struct kgsl_pwrscale *pwrscale)
{
@@ -177,6 +199,7 @@
} else {
priv->gpu_busy = 1;
}
+ msm_remove_io_fraction(device);
return 0;
}
@@ -201,6 +224,7 @@
msm_dcvs_freq_sink_unregister(&priv->freq_sink);
kfree(pwrscale->priv);
pwrscale->priv = NULL;
+ msm_restore_io_fraction(device);
}
struct kgsl_pwrscale_policy kgsl_pwrscale_policy_msm = {
diff --git a/drivers/gpu/msm/kgsl_snapshot.c b/drivers/gpu/msm/kgsl_snapshot.c
index abaa8ce..a2ab5b1 100644
--- a/drivers/gpu/msm/kgsl_snapshot.c
+++ b/drivers/gpu/msm/kgsl_snapshot.c
@@ -414,18 +414,24 @@
int kgsl_snapshot_dump_regs(struct kgsl_device *device, void *snapshot,
int remain, void *priv)
{
+ struct kgsl_snapshot_registers_list *list = priv;
+
struct kgsl_snapshot_regs *header = snapshot;
- struct kgsl_snapshot_registers *regs = priv;
+ struct kgsl_snapshot_registers *regs;
unsigned int *data = snapshot + sizeof(*header);
- int count = 0, i, j;
+ int count = 0, i, j, k;
/* Figure out how many registers we are going to dump */
- for (i = 0; i < regs->count; i++) {
- int start = regs->regs[i * 2];
- int end = regs->regs[i * 2 + 1];
+ for (i = 0; i < list->count; i++) {
+ regs = &(list->registers[i]);
- count += (end - start + 1);
+ for (j = 0; j < regs->count; j++) {
+ int start = regs->regs[j * 2];
+ int end = regs->regs[j * 2 + 1];
+
+ count += (end - start + 1);
+ }
}
if (remain < (count * 8) + sizeof(*header)) {
@@ -433,16 +439,20 @@
return 0;
}
- for (i = 0; i < regs->count; i++) {
- unsigned int start = regs->regs[i * 2];
- unsigned int end = regs->regs[i * 2 + 1];
- for (j = start; j <= end; j++) {
- unsigned int val;
+ for (i = 0; i < list->count; i++) {
+ regs = &(list->registers[i]);
+ for (j = 0; j < regs->count; j++) {
+ unsigned int start = regs->regs[j * 2];
+ unsigned int end = regs->regs[j * 2 + 1];
- kgsl_regread(device, j, &val);
- *data++ = j;
- *data++ = val;
+ for (k = start; k <= end; k++) {
+ unsigned int val;
+
+ kgsl_regread(device, k, &val);
+ *data++ = k;
+ *data++ = val;
+ }
}
}
diff --git a/drivers/gpu/msm/kgsl_snapshot.h b/drivers/gpu/msm/kgsl_snapshot.h
index d54afcf..6d81bcf 100644
--- a/drivers/gpu/msm/kgsl_snapshot.h
+++ b/drivers/gpu/msm/kgsl_snapshot.h
@@ -144,6 +144,7 @@
#define SNAPSHOT_DEBUG_CP_PFP_RAM 9
#define SNAPSHOT_DEBUG_CP_ROQ 10
#define SNAPSHOT_DEBUG_SHADER_MEMORY 11
+#define SNAPSHOT_DEBUG_CP_MERCIU 12
struct kgsl_snapshot_debug {
int type; /* Type identifier for the attached tata */
@@ -240,12 +241,22 @@
/* A common helper function to dump a range of registers. This will be used in
* the GPU specific devices like this:
*
- * struct kgsl_snapshot_registers priv;
- * priv.regs = registers_array;;
- * priv.count = num_registers;
+ * struct kgsl_snapshot_registers_list list;
+ * struct kgsl_snapshot_registers priv[2];
+ *
+ * priv[0].regs = registers_array;;
+ * priv[o].count = num_registers;
+ * priv[1].regs = registers_array_new;;
+ * priv[1].count = num_registers_new;
+ *
+ * list.registers = priv;
+ * list.count = 2;
*
* kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot,
- * remain, kgsl_snapshot_dump_regs, &priv).
+ * remain, kgsl_snapshot_dump_regs, &list).
+ *
+ * Pass in a struct pointing to a list of register definitions as described
+ * below:
*
* Pass in an array of register range pairs in the form of:
* start reg, stop reg
@@ -257,6 +268,13 @@
int count; /* Number of entries in the array */
};
+struct kgsl_snapshot_registers_list {
+ /* Pointer to an array of register lists */
+ struct kgsl_snapshot_registers *registers;
+ /* Number of registers lists in the array */
+ int count;
+};
+
int kgsl_snapshot_dump_regs(struct kgsl_device *device, void *snapshot,
int remain, void *priv);
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index 1894465..d596782 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -2653,7 +2653,7 @@
tx_ps.pi = radio->pi;
tx_ps.pty = radio->pty;
tx_ps.ps_repeatcount = radio->ps_repeatcount;
- tx_ps.ps_len = bytes_to_copy;
+ tx_ps.ps_num = (bytes_to_copy / PS_STRING_LEN);
retval = radio_hci_request(radio->fm_hdev, hci_trans_ps_req,
(unsigned long)&tx_ps, RADIO_HCI_TIMEOUT);
@@ -2672,7 +2672,7 @@
tx_rt.rt_control = 0x01;
tx_rt.pi = radio->pi;
tx_rt.pty = radio->pty;
- tx_rt.ps_len = bytes_to_copy;
+ tx_rt.rt_len = bytes_to_copy;
retval = radio_hci_request(radio->fm_hdev, hci_trans_rt_req,
(unsigned long)&tx_rt, RADIO_HCI_TIMEOUT);
diff --git a/drivers/media/video/msm/sensors/imx091.h b/drivers/media/video/msm/sensors/imx091.h
index 862b43a..3618b4c 100644
--- a/drivers/media/video/msm/sensors/imx091.h
+++ b/drivers/media/video/msm/sensors/imx091.h
@@ -42,7 +42,8 @@
{REQUEST_VREG, 0},
{ENABLE_VREG, 0},
{ENABLE_GPIO, 0},
- {CONFIG_CLK, 0},
+ {CONFIG_CLK, 1},
+ {CONFIG_I2C_MUX, 0},
};
static const struct i2c_device_id imx091_i2c_id[] = {
diff --git a/drivers/media/video/msm_vidc/msm_vidc_common.c b/drivers/media/video/msm_vidc/msm_vidc_common.c
index c9e8ff4..3f7e333 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_common.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_common.c
@@ -1384,13 +1384,21 @@
frame_data.filled_len = vb->v4l2_planes[0].bytesused;
frame_data.device_addr = vb->v4l2_planes[0].m.userptr;
frame_data.timestamp = time_usec;
+ frame_data.flags = 0;
frame_data.clnt_data = (u32)vb;
if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
frame_data.buffer_type = HAL_BUFFER_INPUT;
if (vb->v4l2_buf.flags & V4L2_BUF_FLAG_EOS) {
- frame_data.flags = HAL_BUFFERFLAG_EOS;
+ frame_data.flags |= HAL_BUFFERFLAG_EOS;
pr_debug("Received EOS on output capability\n");
}
+
+ if (vb->v4l2_buf.flags &
+ V4L2_QCOM_BUF_FLAG_CODECCONFIG) {
+ frame_data.flags |= HAL_BUFFERFLAG_CODECCONFIG;
+ pr_debug("Received CODECCONFIG on output capability\n");
+ }
+
pr_debug("Sending etb to hal: Alloc: %d :filled: %d\n",
frame_data.alloc_len, frame_data.filled_len);
rc = vidc_hal_session_etb((void *) inst->session,
diff --git a/drivers/mfd/pm8xxx-spk.c b/drivers/mfd/pm8xxx-spk.c
index 2de70f4..7ce6b50 100644
--- a/drivers/mfd/pm8xxx-spk.c
+++ b/drivers/mfd/pm8xxx-spk.c
@@ -136,7 +136,7 @@
val = pm8xxx_spk_read(PM8XXX_SPK_CTL1_REG_OFF);
if (val < 0)
return val;
- val |= (gain << 4);
+ val = (gain << 4) | (val & 0xF);
ret = pm8xxx_spk_write(PM8XXX_SPK_CTL1_REG_OFF, val);
if (!ret) {
pm8xxx_spk_bank_write(the_spk_chip->base
diff --git a/drivers/net/ppp/pppolac.c b/drivers/net/ppp/pppolac.c
index c94b850..a5d3d63 100644
--- a/drivers/net/ppp/pppolac.c
+++ b/drivers/net/ppp/pppolac.c
@@ -310,7 +310,7 @@
po->chan.hdrlen = 12;
po->chan.private = sk_udp;
po->chan.ops = &pppolac_channel_ops;
- po->chan.mtu = PPP_MTU - 80;
+ po->chan.mtu = PPP_MRU - 80;
po->proto.lac.local = unaligned(&addr->local)->u32;
po->proto.lac.remote = unaligned(&addr->remote)->u32;
atomic_set(&po->proto.lac.sequencing, 1);
diff --git a/drivers/net/ppp/pppopns.c b/drivers/net/ppp/pppopns.c
index fb81984..6016d29 100644
--- a/drivers/net/ppp/pppopns.c
+++ b/drivers/net/ppp/pppopns.c
@@ -290,7 +290,7 @@
po->chan.hdrlen = 14;
po->chan.private = sk_raw;
po->chan.ops = &pppopns_channel_ops;
- po->chan.mtu = PPP_MTU - 80;
+ po->chan.mtu = PPP_MRU - 80;
po->proto.pns.local = addr->local;
po->proto.pns.remote = addr->remote;
po->proto.pns.data_ready = sk_raw->sk_data_ready;
diff --git a/drivers/net/pppolac.c b/drivers/net/pppolac.c
index c94b850..a5d3d63 100644
--- a/drivers/net/pppolac.c
+++ b/drivers/net/pppolac.c
@@ -310,7 +310,7 @@
po->chan.hdrlen = 12;
po->chan.private = sk_udp;
po->chan.ops = &pppolac_channel_ops;
- po->chan.mtu = PPP_MTU - 80;
+ po->chan.mtu = PPP_MRU - 80;
po->proto.lac.local = unaligned(&addr->local)->u32;
po->proto.lac.remote = unaligned(&addr->remote)->u32;
atomic_set(&po->proto.lac.sequencing, 1);
diff --git a/drivers/net/pppopns.c b/drivers/net/pppopns.c
index fb81984..6016d29 100644
--- a/drivers/net/pppopns.c
+++ b/drivers/net/pppopns.c
@@ -290,7 +290,7 @@
po->chan.hdrlen = 14;
po->chan.private = sk_raw;
po->chan.ops = &pppopns_channel_ops;
- po->chan.mtu = PPP_MTU - 80;
+ po->chan.mtu = PPP_MRU - 80;
po->proto.pns.local = addr->local;
po->proto.pns.remote = addr->remote;
po->proto.pns.data_ready = sk_raw->sk_data_ready;
diff --git a/drivers/usb/gadget/u_serial.c b/drivers/usb/gadget/u_serial.c
index de93049..909744f 100644
--- a/drivers/usb/gadget/u_serial.c
+++ b/drivers/usb/gadget/u_serial.c
@@ -849,13 +849,6 @@
port->open_count = 1;
port->openclose = false;
- /* low_latency means ldiscs work is carried in the same context
- * of tty_flip_buffer_push. The same can be called from IRQ with
- * low_latency = 0. But better to use a dedicated worker thread
- * to push the data.
- */
- tty->low_latency = 1;
-
/* if connected, start the I/O stream */
if (port->port_usb) {
struct gserial *gser = port->port_usb;
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index 2126ff0..86b2d45 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -35,6 +35,7 @@
#include <linux/usb/msm_hsusb.h>
#include <linux/gpio.h>
#include <linux/spinlock.h>
+#include <linux/irq.h>
#include <mach/msm_bus.h>
#include <mach/clk.h>
@@ -1365,12 +1366,16 @@
/* configure wakeup irq */
if (mehci->wakeup_irq) {
+ /* In case if wakeup gpio is pulled high at this point
+ * remote wakeup interrupt fires right after request_irq.
+ * Remote wake up interrupt only needs to be enabled when
+ * HSIC bus goes to suspend.
+ */
+ irq_set_status_flags(mehci->wakeup_irq, IRQ_NOAUTOEN);
ret = request_irq(mehci->wakeup_irq, msm_hsic_wakeup_irq,
IRQF_TRIGGER_HIGH,
"msm_hsic_wakeup", mehci);
- if (!ret) {
- disable_irq_nosync(mehci->wakeup_irq);
- } else {
+ if (ret) {
dev_err(&pdev->dev, "request_irq(%d) failed: %d\n",
mehci->wakeup_irq, ret);
mehci->wakeup_irq = 0;
diff --git a/drivers/usb/host/ehci-msm72k.c b/drivers/usb/host/ehci-msm72k.c
index 816e408..3e53c14 100644
--- a/drivers/usb/host/ehci-msm72k.c
+++ b/drivers/usb/host/ehci-msm72k.c
@@ -399,7 +399,7 @@
ehci_writel(ehci, ehci->command, &ehci->regs->command);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
- hcd->state = HC_STATE_RUNNING;
+ ehci->rh_state = EHCI_RH_RUNNING;
/*Enable appropriate Interrupts*/
ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index bcbb253..054741f 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -568,6 +568,7 @@
void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe);
void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all);
void mdp4_mixer_blend_setup(int mixer);
+void mdp4_mixer_blend_cfg(int);
struct mdp4_overlay_pipe *mdp4_overlay_stage_pipe(int mixer, int stage);
void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe);
void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index b12ec94..c07b3a7 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -1889,6 +1889,32 @@
mdp4_overlay_reg_flush(pipe, 0);
}
+void mdp4_mixer_blend_cfg(int mixer)
+{
+ int i, off;
+ unsigned char *overlay_base;
+ struct blend_cfg *blend;
+
+ if (mixer == MDP4_MIXER2)
+ overlay_base = MDP_BASE + MDP4_OVERLAYPROC2_BASE;
+ else if (mixer == MDP4_MIXER1)
+ overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;
+ else
+ overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;
+
+ blend = &ctrl->blend[mixer][MDP4_MIXER_STAGE_BASE];
+ blend++; /* stage0 */
+
+ for (i = MDP4_MIXER_STAGE0; i < MDP4_MIXER_STAGE_MAX; i++) {
+ off = 20 * i;
+ off = 0x20 * (i - MDP4_MIXER_STAGE0);
+ if (i == MDP4_MIXER_STAGE3)
+ off -= 4;
+ outpdw(overlay_base + off + 0x104, blend->op);
+ blend++;
+ }
+}
+
/*
* D(i+1) = Ks * S + Kd * D(i)
*/
@@ -2032,7 +2058,10 @@
outpdw(overlay_base + off + 0x108, blend->fg_alpha);
outpdw(overlay_base + off + 0x10c, blend->bg_alpha);
- outpdw(overlay_base + off + 0x104, blend->op);
+
+ if (mdp_rev >= MDP_REV_42)
+ outpdw(overlay_base + off + 0x104, blend->op);
+
outpdw(overlay_base + (off << 5) + 0x1004, blend->co3_sel);
outpdw(overlay_base + off + 0x110, blend->transp_low0);/* low */
outpdw(overlay_base + off + 0x114, blend->transp_low1);/* low */
diff --git a/drivers/video/msm/mdp4_overlay_dsi_cmd.c b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
index 6f78305..c788c33 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_cmd.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
@@ -293,7 +293,7 @@
/* Blt */
if (vctrl->blt_wait)
need_dmap_wait = 1;
- else if (vctrl->ov_koff != vctrl->ov_done) {
+ if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index 00f44d4..e131369 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -840,8 +840,12 @@
vctrl->blt_change = 0;
}
+ if (mdp_rev <= MDP_REV_41)
+ mdp4_mixer_blend_cfg(MDP4_MIXER1);
+
complete_all(&vctrl->dmae_comp);
mdp4_overlay_dma_commit(MDP4_MIXER1);
+
vsync_irq_disable(INTR_DMA_E_DONE, MDP_DMA_E_TERM);
spin_unlock(&vctrl->spin_lock);
}
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index 08c3815..a2fabca 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -780,6 +780,10 @@
}
complete_all(&vctrl->dmap_comp);
+
+ if (mdp_rev <= MDP_REV_41)
+ mdp4_mixer_blend_cfg(MDP4_MIXER0);
+
mdp4_overlay_dma_commit(cndx);
spin_unlock(&vctrl->spin_lock);
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c
index a2327d5..3620f1a 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c
@@ -766,6 +766,6 @@
break;
}
if (string)
- DDL_MSG_ERROR("Recoverable Error code = 0x%x : %s",
+ DDL_MSG_LOW("Recoverable Error code = 0x%x : %s",
error_code, string);
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
index dfbee84..00addbe 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
@@ -471,7 +471,7 @@
ddl = ddl_context->current_ddl[1];
else {
DDL_MSG_LOW("STATE-CRITICAL-FRMRUN");
- DDL_MSG_ERROR("Unexpected channel ID = %d", channel_id);
+ DDL_MSG_LOW("Unexpected channel ID = %d", channel_id);
ddl = NULL;
}
return ddl;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
index 416b497..07b2fe2 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
@@ -947,7 +947,7 @@
VIDC_SM_EXTENDED_PAR_HEIGHT_SHFT);
break;
default:
- DDL_MSG_HIGH("Incorrect Aspect Ratio.");
+ DDL_MSG_LOW("Incorrect Aspect Ratio.");
aspect_ratio_info->par_width = 1;
aspect_ratio_info->par_height = 1;
break;
@@ -1005,7 +1005,7 @@
VIDC_SM_EXTENDED_PAR_HEIGHT_SHFT);
break;
default:
- DDL_MSG_HIGH("Incorrect Aspect Ratio.");
+ DDL_MSG_LOW("Incorrect Aspect Ratio.");
aspect_ratio_info->par_width = 1;
aspect_ratio_info->par_height = 1;
break;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
index 90114f7..5897a33 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
@@ -427,7 +427,7 @@
time_data->ddl_t1 = act_time;
DDL_MSG_LOW("\n%s(): Start Time (%u)", func_name, act_time);
} else if (vidc_msg_timing) {
- DDL_MSG_TIME("\n%s(): Timer already started! St(%u) Act(%u)",
+ DDL_MSG_LOW("\n%s(): Timer already started! St(%u) Act(%u)",
func_name, time_data->ddl_t1, act_time);
}
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
index 04bb160..978d1de 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
@@ -260,6 +260,12 @@
vidc_sm_set_mpeg4_profile_override(
&ddl->shared_mem[ddl->command_channel],
VIDC_SM_PROFILE_INFO_ASP);
+ if (VCD_CODEC_MPEG2 == decoder->codec.codec)
+ vidc_sm_set_mp2datadumpbuffer(
+ &ddl->shared_mem[ddl->command_channel],
+ DDL_ADDR_OFFSET(ddl_context->dram_base_a,
+ ddl->codec_data.decoder.hw_bufs.extnuserdata),
+ DDL_KILO_BYTE(2));
if (VCD_CODEC_H264 == decoder->codec.codec)
vidc_sm_set_decoder_sei_enable(
&ddl->shared_mem[ddl->command_channel],
diff --git a/include/media/radio-iris.h b/include/media/radio-iris.h
index 988de6a..ba705bd 100644
--- a/include/media/radio-iris.h
+++ b/include/media/radio-iris.h
@@ -210,8 +210,9 @@
#define HCI_FM_GET_DET_CH_TH_CMD 16
/* Defines for FM TX*/
-#define TX_PS_DATA_LENGTH 96
+#define TX_PS_DATA_LENGTH 108
#define TX_RT_DATA_LENGTH 64
+#define PS_STRING_LEN 9
/* ----- HCI Command request ----- */
struct hci_fm_recv_conf_req {
@@ -238,7 +239,7 @@
__u16 pi;
__u8 pty;
__u8 ps_repeatcount;
- __u8 ps_len;
+ __u8 ps_num;
__u8 ps_data[TX_PS_DATA_LENGTH];
} __packed;
@@ -246,7 +247,7 @@
__u8 rt_control;
__u16 pi;
__u8 pty;
- __u8 ps_len;
+ __u8 rt_len;
__u8 rt_data[TX_RT_DATA_LENGTH];
} __packed;
@@ -745,7 +746,7 @@
/* constants */
#define RDS_BLOCKS_NUM (4)
#define BYTES_PER_BLOCK (3)
-#define MAX_PS_LENGTH (96)
+#define MAX_PS_LENGTH (108)
#define MAX_RT_LENGTH (64)
#define RDS_GRP_CNTR_LEN (36)
#define RX_RT_DATA_LENGTH (63)
diff --git a/lib/genalloc.c b/lib/genalloc.c
index 188df2c..9cf1b8b 100644
--- a/lib/genalloc.c
+++ b/lib/genalloc.c
@@ -34,6 +34,7 @@
#include <linux/rculist.h>
#include <linux/interrupt.h>
#include <linux/genalloc.h>
+#include <linux/vmalloc.h>
static int set_bits_ll(unsigned long *addr, unsigned long mask_to_set)
{
@@ -178,9 +179,14 @@
int nbytes = sizeof(struct gen_pool_chunk) +
(nbits + BITS_PER_BYTE - 1) / BITS_PER_BYTE;
- chunk = kmalloc_node(nbytes, GFP_KERNEL | __GFP_ZERO, nid);
+ if (nbytes <= PAGE_SIZE)
+ chunk = kmalloc_node(nbytes, __GFP_ZERO, nid);
+ else
+ chunk = vmalloc(nbytes);
if (unlikely(chunk == NULL))
return -ENOMEM;
+ if (nbytes > PAGE_SIZE)
+ memset(chunk, 0, nbytes);
chunk->phys_addr = phys;
chunk->start_addr = virt;
@@ -235,14 +241,20 @@
int bit, end_bit;
list_for_each_safe(_chunk, _next_chunk, &pool->chunks) {
+ int nbytes;
chunk = list_entry(_chunk, struct gen_pool_chunk, next_chunk);
list_del(&chunk->next_chunk);
end_bit = (chunk->end_addr - chunk->start_addr) >> order;
+ nbytes = sizeof(struct gen_pool_chunk) +
+ (end_bit + BITS_PER_BYTE - 1) / BITS_PER_BYTE;
bit = find_next_bit(chunk->bits, end_bit, 0);
BUG_ON(bit < end_bit);
- kfree(chunk);
+ if (nbytes <= PAGE_SIZE)
+ kfree(chunk);
+ else
+ vfree(chunk);
}
kfree(pool);
return;
diff --git a/sound/soc/codecs/cs8427.c b/sound/soc/codecs/cs8427.c
index dc7f23b..23870a4 100644
--- a/sound/soc/codecs/cs8427.c
+++ b/sound/soc/codecs/cs8427.c
@@ -103,8 +103,37 @@
static int cs8427_i2c_write(struct cs8427 *chip, unsigned short reg,
int bytes, void *src)
{
- return cs8427_i2c_write_device(chip, reg, src, bytes);
+ int ret = 0, err = 0;
+ struct cs8427_platform_data *pdata = chip->client->dev.platform_data;
+ /*
+ * enable the 100KHz level shifter to communicate
+ * with CS8427 chip
+ */
+ if (pdata->enable) {
+ err = pdata->enable(1);
+ if (err < 0) {
+ dev_err(&chip->client->dev,
+ "failed to enable the level shifter\n");
+ return err;
+ }
+ }
+ ret = cs8427_i2c_write_device(chip, reg, src, bytes);
+
+ /*
+ * Disable the 100KHz level shifter to communicate
+ * with CS8427 chip
+ */
+ if (pdata->enable) {
+ err = pdata->enable(0);
+ if (err < 0) {
+ dev_err(&chip->client->dev,
+ "failed to disable the level shifter\n");
+ return err;
+ }
+ }
+ return ret;
}
+
static int cs8427_i2c_read_device(struct cs8427 *cs8427_i2c,
unsigned short reg,
int bytes, unsigned char *dest)
@@ -156,16 +185,45 @@
unsigned short reg,
int bytes, void *dest)
{
- return cs8427_i2c_read_device(chip, reg,
+ u32 err = 0, ret = 0;
+ struct cs8427_platform_data *pdata = chip->client->dev.platform_data;
+ /*
+ * enable the 100KHz level shifter to communicate
+ * with CS8427 chip
+ */
+ if (pdata->enable) {
+ err = pdata->enable(1);
+ if (err < 0) {
+ dev_err(&chip->client->dev,
+ "failed to enable the level shifter\n");
+ return err;
+ }
+ }
+ ret = cs8427_i2c_read_device(chip, reg,
bytes, dest);
+
+ /*
+ * Disable the 100KHz level shifter to communicate
+ * with CS8427 chip
+ */
+ if (pdata->enable) {
+ err = pdata->enable(0);
+ if (err < 0) {
+ dev_err(&chip->client->dev,
+ "failed to disable the level shifter\n");
+ return err;
+ }
+ }
+ return ret;
}
static int cs8427_i2c_sendbytes(struct cs8427 *chip,
char *reg_addr, char *data,
int bytes)
{
- u32 ret = 0;
+ u32 ret = 0, err = 0;
u8 i = 0;
+ struct cs8427_platform_data *pdata = chip->client->dev.platform_data;
if (!chip) {
pr_err("%s, invalid device info\n", __func__);
@@ -176,6 +234,18 @@
"invalid data pointer\n", __func__);
return -EINVAL;
}
+ /*
+ * enable the 100KHz level shifter to communicate
+ * with CS8427 chip
+ */
+ if (pdata->enable) {
+ err = pdata->enable(1);
+ if (err < 0) {
+ dev_err(&chip->client->dev,
+ "failed to enable the level shifter\n");
+ return err;
+ }
+ }
for (i = 0; i < bytes; i++) {
ret = cs8427_i2c_write_device(chip, (*reg_addr + i),
&data[i], 1);
@@ -186,6 +256,19 @@
break;
}
}
+
+ /*
+ * Disable the 100KHz level shifter to communicate
+ * with CS8427 chip
+ */
+ if (pdata->enable) {
+ err = pdata->enable(0);
+ if (err < 0) {
+ dev_err(&chip->client->dev,
+ "failed to disable the level shifter\n");
+ return err;
+ }
+ }
return i;
}
@@ -651,16 +734,6 @@
struct cs8427_platform_data *pdata = chip->client->dev.platform_data;
int ret = 0;
- /*enable the 100KHz level shifter*/
- if (pdata->enable) {
- ret = pdata->enable(1);
- if (ret < 0) {
- dev_err(&chip->client->dev,
- "failed to enable the level shifter\n");
- return ret;
- }
- }
-
ret = gpio_request(pdata->reset_gpio, "cs8427 reset");
if (ret < 0) {
dev_err(&chip->client->dev,
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 09cb605..374269d 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -103,7 +103,7 @@
#define TABLA_MBHC_STATUS_REL_DETECTION 0x0C
-#define TABLA_MBHC_GPIO_REL_DEBOUNCE_TIME_MS 200
+#define TABLA_MBHC_GPIO_REL_DEBOUNCE_TIME_MS 50
#define TABLA_MBHC_FAKE_INS_DELTA_MV 200
#define TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV 300
diff --git a/sound/soc/codecs/wcd9320.c b/sound/soc/codecs/wcd9320.c
index 01820eb..136024c 100644
--- a/sound/soc/codecs/wcd9320.c
+++ b/sound/soc/codecs/wcd9320.c
@@ -390,35 +390,60 @@
TAIKO_A_CDC_TX10_VOL_CTL_GAIN,
};
-static int taiko_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
+static int taiko_codec_enable_class_h_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
- pr_debug("%s %d\n", __func__, event);
+ pr_debug("%s %s %d\n", __func__, w->name, event);
- /* FIX . need to use CLASS-H controller */
switch (event) {
- case SND_SOC_DAPM_POST_PMU:
- snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_OTHR_CTL, 0x01,
- 0x01);
- usleep_range(200, 200);
- snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x10, 0x00);
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, TAIKO_A_CDC_CLSH_B1_CTL, 0x01, 0x01);
break;
case SND_SOC_DAPM_PRE_PMD:
- snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL,
- 0x01, 0x01);
- usleep_range(20, 20);
- snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x08, 0x08);
- snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x10, 0x10);
- snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_OTHR_CTL, 0x01,
- 0x00);
- snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x08, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_1, 0x80, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_CDC_CLSH_B1_CTL, 0x01, 0x00);
break;
}
return 0;
}
+static int taiko_codec_enable_class_h(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ pr_debug("%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_5, 0x02, 0x02);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_4, 0xFF, 0xFF);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_1, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_3, 0x04, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_3, 0x08, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_1, 0x80, 0x80);
+ usleep_range(1000, 1000);
+ break;
+ }
+ return 0;
+}
+
+static int taiko_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ pr_debug("%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(1000, 1000);
+ break;
+ }
+ return 0;
+}
+
+
static int taiko_get_anc_slot(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -2766,7 +2791,7 @@
struct snd_soc_codec *codec = w->codec;
struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
u8 mbhc_micb_ctl_val;
- pr_debug("%s: event = %d\n", __func__, event);
+ pr_debug("%s: %s event = %d\n", __func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
@@ -2780,6 +2805,19 @@
}
break;
+ case SND_SOC_DAPM_POST_PMU:
+
+ usleep_range(10000, 10000);
+
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_5, 0x02, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x20, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_3, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_3, 0x08, 0x00);
+
+ usleep_range(10, 10);
+
+ break;
+
case SND_SOC_DAPM_POST_PMD:
/* schedule work is required because at the time HPH PA DAPM
* event callback is called by DAPM framework, CODEC dapm mutex
@@ -3012,6 +3050,8 @@
{"EAR PA", NULL, "EAR_PA_MIXER"},
{"EAR_PA_MIXER", NULL, "DAC1"},
{"DAC1", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_EAR"},
+ {"CLASS_H_EAR", NULL, "CLASS_H_CLK"},
{"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX2"},
{"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX2"},
@@ -3028,7 +3068,12 @@
{"HPHR_PA_MIXER", NULL, "HPHR DAC"},
{"HPHL DAC", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_HPH_L"},
+ {"CLASS_H_HPH_L", NULL, "CLASS_H_CLK"},
+
{"HPHR DAC", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_HPH_R"},
+ {"CLASS_H_HPH_R", NULL, "CLASS_H_CLK"},
{"ANC", NULL, "ANC1 MUX"},
{"ANC", NULL, "ANC2 MUX"},
@@ -3082,7 +3127,7 @@
{"RX1 CHAIN", NULL, "ANC"},
{"RX2 CHAIN", NULL, "ANC"},
- {"CP", NULL, "RX_BIAS"},
+ {"CLASS_H_CLK", NULL, "RX_BIAS"},
{"LINEOUT1 DAC", NULL, "RX_BIAS"},
{"LINEOUT2 DAC", NULL, "RX_BIAS"},
{"LINEOUT3 DAC", NULL, "RX_BIAS"},
@@ -3094,7 +3139,6 @@
{"RX3 MIX1", NULL, "COMP2_CLK"},
{"RX5 MIX1", NULL, "COMP2_CLK"},
-
{"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
{"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
{"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
@@ -3295,38 +3339,16 @@
{"ADC6", NULL, "AMIC6"},
/* AUX PGA Connections */
- {"HPHL_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"HPHL_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"HPHL_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"HPHL_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
- {"HPHR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"HPHR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"HPHR_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"HPHR_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
- {"LINEOUT1_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"LINEOUT1_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"LINEOUT1_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"LINEOUT1_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
- {"LINEOUT2_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"LINEOUT2_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"LINEOUT2_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"LINEOUT2_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
- {"LINEOUT3_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"LINEOUT3_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"LINEOUT3_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"LINEOUT3_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
- {"LINEOUT4_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"LINEOUT4_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"LINEOUT4_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"LINEOUT4_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
{"EAR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
- {"EAR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
- {"EAR_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
- {"EAR_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
+ {"HPHL_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"HPHR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"LINEOUT1_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"LINEOUT2_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"LINEOUT3_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"LINEOUT4_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
{"AUX_PGA_Left", NULL, "AMIC5"},
{"AUX_PGA_Right", NULL, "AMIC6"},
-
{"IIR1", NULL, "IIR1 INP1 MUX"},
{"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
{"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
@@ -4153,6 +4175,28 @@
return ret;
}
+static int taiko_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ pr_debug("%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_5, 0x02, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x20, 0x00);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_3, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAIKO_A_BUCK_MODE_3, 0x08, 0x00);
+
+ usleep_range(5000, 5000);
+ break;
+ }
+ return 0;
+}
+
/* Todo: Have seperate dapm widgets for I2S and Slimbus.
* Might Need to have callbacks registered only for slimbus
*/
@@ -4160,7 +4204,8 @@
/*RX stuff */
SND_SOC_DAPM_OUTPUT("EAR"),
- SND_SOC_DAPM_PGA("EAR PA", TAIKO_A_RX_EAR_EN, 4, 0, NULL, 0),
+ SND_SOC_DAPM_PGA_E("EAR PA", TAIKO_A_RX_EAR_EN, 4, 0, NULL, 0,
+ taiko_codec_enable_ear_pa, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER("DAC1", TAIKO_A_RX_EAR_EN, 6, 0, dac1_switch,
ARRAY_SIZE(dac1_switch)),
@@ -4193,13 +4238,13 @@
SND_SOC_DAPM_OUTPUT("HEADPHONE"),
SND_SOC_DAPM_PGA_E("HPHL", TAIKO_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
taiko_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
- SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HPHL DAC", TAIKO_A_RX_HPH_L_DAC_CTL, 7, 0,
hphl_switch, ARRAY_SIZE(hphl_switch)),
SND_SOC_DAPM_PGA_E("HPHR", TAIKO_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
taiko_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
- SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("HPHR DAC", NULL, TAIKO_A_RX_HPH_R_DAC_CTL, 7, 0,
taiko_hphr_dac_event,
@@ -4329,10 +4374,23 @@
SND_SOC_DAPM_MUX("RX7 MIX2 INP2", SND_SOC_NOPM, 0, 0,
&rx7_mix2_inp2_mux),
- SND_SOC_DAPM_SUPPLY("CP", TAIKO_A_NCP_EN, 0, 0,
- taiko_codec_enable_charge_pump, SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_SUPPLY("CLASS_H_CLK", TAIKO_A_CDC_CLK_OTHR_CTL, 0, 0,
+ taiko_codec_enable_class_h_clk, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD),
+ SND_SOC_DAPM_SUPPLY("CLASS_H_EAR", TAIKO_A_CDC_CLSH_B1_CTL, 4, 0,
+ taiko_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_HPH_R", TAIKO_A_CDC_CLSH_B1_CTL, 3, 0,
+ taiko_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_HPH_L", TAIKO_A_CDC_CLSH_B1_CTL, 2, 0,
+ taiko_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CP", TAIKO_A_NCP_EN, 0, 0,
+ taiko_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
taiko_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
@@ -6812,6 +6870,85 @@
return IRQ_HANDLED;
}
+static const struct taiko_reg_mask_val taiko_1_0_class_h_ear[] = {
+
+ /* CLASS-H EAR IDLE_THRESHOLD Table */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_IDLE_EAR_THSD, 0x26),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD, 0x2C),
+
+ /* CLASS-H EAR I_PA_FACT Table. */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L, 0xA9),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U, 0x07),
+
+ /* CLASS-H EAR Voltage Headroom , Voltage Min. */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_V_PA_HD_EAR, 0x0D),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_V_PA_MIN_EAR, 0x3A),
+
+ /* CLASS-H EAR K values --chnages from load. */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_ADDR, 0x08),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x1B),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x2D),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x36),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x37),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+ /** end of Ear PA load 32 */
+};
+
+
+static const struct taiko_reg_mask_val taiko_1_0_class_h_hph[] = {
+
+ /* CLASS-H HPH IDLE_THRESHOLD Table */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_IDLE_HPH_THSD, 0x13),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD, 0x19),
+
+ /* CLASS-H HPH I_PA_FACT Table */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L, 0x9A),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U, 0x06),
+
+ /* CLASS-H HPH Voltage Headroom , Voltage Min */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_V_PA_HD_HPH, 0x0D),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_V_PA_MIN_HPH, 0x1D),
+
+ /* CLASS-H HPH K values --chnages from load .*/
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_ADDR, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0xAE),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x01),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x1C),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x25),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x27),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_K_DATA, 0x00),
+};
+
+static int taiko_config_ear_class_h(struct snd_soc_codec *codec, u32 ear_load)
+{
+ u32 i;
+
+ if (ear_load != 32)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(taiko_1_0_class_h_ear); i++)
+ snd_soc_write(codec, taiko_1_0_class_h_ear[i].reg,
+ taiko_1_0_class_h_ear[i].val);
+ return 0;
+}
+
+static int taiko_config_hph_class_h(struct snd_soc_codec *codec, u32 hph_load)
+{
+ u32 i;
+ if (hph_load != 16)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(taiko_1_0_class_h_hph); i++)
+ snd_soc_write(codec, taiko_1_0_class_h_hph[i].reg,
+ taiko_1_0_class_h_hph[i].val);
+ return 0;
+}
+
static int taiko_handle_pdata(struct taiko_priv *taiko)
{
struct snd_soc_codec *codec = taiko->codec;
@@ -6943,28 +7080,48 @@
break;
}
}
+
+ taiko_config_ear_class_h(codec, 32);
+ taiko_config_hph_class_h(codec, 16);
+
done:
return rc;
}
static const struct taiko_reg_mask_val taiko_1_0_reg_defaults[] = {
- /* Taiko 1.1 MICBIAS changes */
- TAIKO_REG_VAL(TAIKO_A_MICB_1_INT_RBIAS, 0x24),
- TAIKO_REG_VAL(TAIKO_A_MICB_2_INT_RBIAS, 0x24),
- TAIKO_REG_VAL(TAIKO_A_MICB_3_INT_RBIAS, 0x24),
+ /* set MCLk to 9.6 */
+ TAIKO_REG_VAL(TAIKO_A_CHIP_CTL, 0x0A),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLK_POWER_CTL, 0x03),
- /* Taiko 1.1 HPH changes */
- TAIKO_REG_VAL(TAIKO_A_RX_HPH_BIAS_PA, 0x57),
- TAIKO_REG_VAL(TAIKO_A_RX_HPH_BIAS_LDO, 0x56),
+ /* EAR PA deafults */
+ TAIKO_REG_VAL(TAIKO_A_RX_EAR_CMBUFF, 0x05),
+ /* HPH PA */
+ TAIKO_REG_VAL(TAIKO_A_RX_HPH_BIAS_PA, 0x7A),
- /* Taiko 1.1 EAR PA changes */
- TAIKO_REG_VAL(TAIKO_A_RX_EAR_BIAS_PA, 0xA6),
- TAIKO_REG_VAL(TAIKO_A_RX_EAR_GAIN, 0x02),
- TAIKO_REG_VAL(TAIKO_A_RX_EAR_VCM, 0x03),
+ /** BUCK and NCP defaults for EAR and HS */
+ TAIKO_REG_VAL(TAIKO_A_BUCK_CTRL_CCL_4, 0x50),
+ TAIKO_REG_VAL(TAIKO_A_BUCK_CTRL_VCL_1, 0x08),
+ TAIKO_REG_VAL(TAIKO_A_BUCK_CTRL_CCL_1, 0x5B),
+ TAIKO_REG_VAL(TAIKO_A_NCP_CLK, 0xFC),
+
+ /* CLASS-H defaults for EAR and HS */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_BUCK_NCP_VARS, 0x00),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_BUCK_NCP_VARS, 0x04),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_B2_CTL, 0x01),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_B2_CTL, 0x05),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_B2_CTL, 0x35),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_B3_CTL, 0x30),
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_B3_CTL, 0x3B),
+
+ /*
+ * For CLASS-H, Enable ANC delay buffer,
+ * set HPHL and EAR PA ref gain to 0 DB.
+ */
+ TAIKO_REG_VAL(TAIKO_A_CDC_CLSH_B1_CTL, 0x26),
- /* Taiko 1.1 RX Changes */
+ /* RX deafults */
TAIKO_REG_VAL(TAIKO_A_CDC_RX1_B5_CTL, 0x78),
TAIKO_REG_VAL(TAIKO_A_CDC_RX2_B5_CTL, 0x78),
TAIKO_REG_VAL(TAIKO_A_CDC_RX3_B5_CTL, 0x78),
@@ -6973,17 +7130,16 @@
TAIKO_REG_VAL(TAIKO_A_CDC_RX6_B5_CTL, 0x78),
TAIKO_REG_VAL(TAIKO_A_CDC_RX7_B5_CTL, 0x78),
- /* Taiko 1.1 RX1 and RX2 Changes */
+ /* RX1 and RX2 defaults */
TAIKO_REG_VAL(TAIKO_A_CDC_RX1_B6_CTL, 0xA0),
TAIKO_REG_VAL(TAIKO_A_CDC_RX2_B6_CTL, 0xA0),
- /* Taiko 1.1 RX3 to RX7 Changes */
+ /* RX3 to RX7 defaults */
TAIKO_REG_VAL(TAIKO_A_CDC_RX3_B6_CTL, 0x80),
TAIKO_REG_VAL(TAIKO_A_CDC_RX4_B6_CTL, 0x80),
TAIKO_REG_VAL(TAIKO_A_CDC_RX5_B6_CTL, 0x80),
TAIKO_REG_VAL(TAIKO_A_CDC_RX6_B6_CTL, 0x80),
TAIKO_REG_VAL(TAIKO_A_CDC_RX7_B6_CTL, 0x80),
-
};
static void taiko_update_reg_defaults(struct snd_soc_codec *codec)
@@ -7002,21 +7158,16 @@
{TAIKO_A_RX_HPH_OCP_CTL, 0xE0, 0x60},
{TAIKO_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
- {TAIKO_A_QFUSE_CTL, 0xFF, 0x03},
-
/* Initialize gain registers to use register gain */
- {TAIKO_A_RX_HPH_L_GAIN, 0x10, 0x10},
- {TAIKO_A_RX_HPH_R_GAIN, 0x10, 0x10},
- {TAIKO_A_RX_LINE_1_GAIN, 0x10, 0x10},
- {TAIKO_A_RX_LINE_2_GAIN, 0x10, 0x10},
- {TAIKO_A_RX_LINE_3_GAIN, 0x10, 0x10},
- {TAIKO_A_RX_LINE_4_GAIN, 0x10, 0x10},
+ {TAIKO_A_RX_HPH_L_GAIN, 0x20, 0x20},
+ {TAIKO_A_RX_HPH_R_GAIN, 0x20, 0x20},
+ {TAIKO_A_RX_LINE_1_GAIN, 0x20, 0x20},
+ {TAIKO_A_RX_LINE_2_GAIN, 0x20, 0x20},
+ {TAIKO_A_RX_LINE_3_GAIN, 0x20, 0x20},
+ {TAIKO_A_RX_LINE_4_GAIN, 0x20, 0x20},
- /* Initialize mic biases to differential mode */
- {TAIKO_A_MICB_1_INT_RBIAS, 0x24, 0x24},
- {TAIKO_A_MICB_2_INT_RBIAS, 0x24, 0x24},
- {TAIKO_A_MICB_3_INT_RBIAS, 0x24, 0x24},
-
+ /* CLASS H config */
+ {TAIKO_A_CDC_CONN_CLSH_CTL, 0x3C, 0x14},
/* Use 16 bit sample size for TX1 to TX6 */
{TAIKO_A_CDC_CONN_TX_SB_B1_CTL, 0x30, 0x20},
@@ -7048,21 +7199,22 @@
{TAIKO_A_CDC_TX9_MUX_CTL, 0x8, 0x0},
{TAIKO_A_CDC_TX10_MUX_CTL, 0x8, 0x0},
- /* config Decimator for DMIC CLK_MODE_1(4.8Mhz@9.6Mhz mclk) */
- {TAIKO_A_CDC_TX1_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX2_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX3_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX4_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX5_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX6_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX7_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX8_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX9_DMIC_CTL, 0x7, 0x0},
- {TAIKO_A_CDC_TX10_DMIC_CTL, 0x7, 0x0},
+ /* config Decimator for DMIC CLK_MODE_1(3.2Mhz@9.6Mhz mclk) */
+ {TAIKO_A_CDC_TX1_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX2_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX3_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX4_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX5_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX6_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX7_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX8_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX9_DMIC_CTL, 0x7, 0x1},
+ {TAIKO_A_CDC_TX10_DMIC_CTL, 0x7, 0x1},
- /* config DMIC clk to CLK_MODE_1 (4.8Mhz@9.6Mhz mclk) */
- {TAIKO_A_CDC_CLK_DMIC_B1_CTL, 0xEE, 0x0},
- {TAIKO_A_CDC_CLK_DMIC_B2_CTL, 0xEE, 0x0},
+ /* config DMIC clk to CLK_MODE_1 (3.2Mhz@9.6Mhz mclk) */
+ {TAIKO_A_CDC_CLK_DMIC_B1_CTL, 0xEE, 0x22},
+ {TAIKO_A_CDC_CLK_DMIC_B2_CTL, 0x0E, 0x02},
+
};
static void taiko_codec_init_reg(struct snd_soc_codec *codec)
@@ -7297,10 +7449,11 @@
int i;
int ch_cnt;
-
codec->control_data = dev_get_drvdata(codec->dev->parent);
control = codec->control_data;
+ dev_info(codec->dev, "%s()\n", __func__);
+
taiko = kzalloc(sizeof(struct taiko_priv), GFP_KERNEL);
if (!taiko) {
dev_err(codec->dev, "Failed to allocate private data\n");
diff --git a/sound/soc/msm/msm-multi-ch-pcm-q6.c b/sound/soc/msm/msm-multi-ch-pcm-q6.c
index 6945a4f..a33a01f 100644
--- a/sound/soc/msm/msm-multi-ch-pcm-q6.c
+++ b/sound/soc/msm/msm-multi-ch-pcm-q6.c
@@ -195,28 +195,45 @@
atomic_set(&prtd->start, 1);
break;
}
- pr_debug("%s:writing %d bytes"\
- " of buffer[%d] to dsp\n",
- __func__, prtd->pcm_count, prtd->out_head);
- buf = prtd->audio_client->port[IN].buf;
- pr_debug("%s:writing buffer[%d] from 0x%08x\n",
- __func__, prtd->out_head,
- ((unsigned int)buf[0].phys
- + (prtd->out_head * prtd->pcm_count)));
- param.paddr = (unsigned long)buf[prtd->out_head].phys;
- param.len = prtd->pcm_count;
- param.msw_ts = 0;
- param.lsw_ts = 0;
- param.flags = NO_TIMESTAMP;
- param.uid = (unsigned long)buf[prtd->out_head].phys;
- if (q6asm_async_write(prtd->audio_client,
- ¶m) < 0)
- pr_err("%s:q6asm_async_write failed\n",
- __func__);
- else
- prtd->out_head =
- (prtd->out_head + 1)
- & (runtime->periods - 1);
+ if (prtd->mmap_flag) {
+ pr_debug("%s:writing %d bytes"\
+ " of buffer[%d] to dsp\n",
+ __func__, prtd->pcm_count,
+ prtd->out_head);
+ buf = prtd->audio_client->port[IN].buf;
+ pr_debug("%s:writing buffer[%d] from 0x%08x\n",
+ __func__, prtd->out_head,
+ ((unsigned int)buf[0].phys
+ + (prtd->out_head * prtd->pcm_count)));
+ param.paddr = (unsigned long)
+ buf[prtd->out_head].phys;
+ param.len = prtd->pcm_count;
+ param.msw_ts = 0;
+ param.lsw_ts = 0;
+ param.flags = NO_TIMESTAMP;
+ param.uid = (unsigned long)
+ buf[prtd->out_head].phys;
+ if (q6asm_async_write(prtd->audio_client,
+ ¶m) < 0)
+ pr_err("%s:q6asm_async_write failed\n",
+ __func__);
+ else
+ prtd->out_head =
+ (prtd->out_head + 1)
+ & (runtime->periods - 1);
+ } else {
+ while (atomic_read(&prtd->out_needed)) {
+ pr_debug("%s:writing %d bytesi" \
+ " of buffer to dsp\n", \
+ __func__, \
+ prtd->pcm_count);
+ q6asm_write_nolock(prtd->audio_client,
+ prtd->pcm_count,
+ 0, 0, NO_TIMESTAMP);
+ atomic_dec(&prtd->out_needed);
+ wake_up(&the_locks.write_wait);
+ };
+ }
atomic_set(&prtd->start, 1);
break;
default:
@@ -237,6 +254,13 @@
int ret;
pr_debug("%s\n", __func__);
+ if (prtd->mmap_flag) {
+ ret = q6asm_set_io_mode(prtd->audio_client, ASYNC_IO_MODE);
+ if (ret < 0) {
+ pr_err("%s: Set IO mode failed\n", __func__);
+ return -ENOMEM;
+ }
+ }
prtd->pcm_size = snd_pcm_lib_buffer_bytes(substream);
prtd->pcm_count = snd_pcm_lib_period_bytes(substream);
prtd->pcm_irq_pos = 0;
@@ -731,12 +755,6 @@
else
dir = OUT;
- ret = q6asm_set_io_mode(prtd->audio_client, ASYNC_IO_MODE);
- if (ret < 0) {
- pr_err("%s: Set IO mode failed\n", __func__);
- return -ENOMEM;
- }
-
ret = q6asm_audio_client_buf_alloc_contiguous(dir,
prtd->audio_client,
(params_buffer_bytes(params) / params_periods(params)),
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index 45b69ea..c7820dd 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -13,11 +13,11 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
-#include <linux/mfd/pm8xxx/pm8921.h>
+#include <linux/of_gpio.h>
#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/mfd/pm8xxx/pm8921.h>
#include <linux/slab.h>
+#include <linux/mfd/pm8xxx/pm8921.h>
+#include <linux/qpnp/clkdiv.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
@@ -28,7 +28,7 @@
#include <qdsp6v2/msm-pcm-routing-v2.h>
#include "../codecs/wcd9320.h"
-/* 8974 machine driver */
+#define DRV_NAME "msm8974-asoc-taiko"
#define PM8921_GPIO_BASE NR_GPIO_IRQS
#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE)
@@ -57,6 +57,11 @@
#define TABLA_MBHC_DEF_BUTTONS 8
#define TABLA_MBHC_DEF_RLOADS 5
+struct msm8974_asoc_mach_data {
+ int mclk_gpio;
+ u32 mclk_freq;
+};
+
/* Shared channel numbers for Slimbus ports that connect APQ to MDM. */
enum {
SLIM_1_RX_1 = 145, /* BT-SCO and USB TX */
@@ -76,12 +81,13 @@
static int msm_slim_0_tx_ch = 1;
static int msm_btsco_rate = BTSCO_RATE_8KHZ;
-static int msm_headset_gpios_configured;
static struct snd_soc_jack hs_jack;
static struct snd_soc_jack button_jack;
static struct mutex cdc_mclk_mutex;
+static struct q_clkdiv *codec_clk;
+static int clk_users;
static void msm_enable_ext_spk_amp_gpio(u32 spk_amp_gpio)
{
@@ -309,16 +315,67 @@
return 0;
}
-static int msm_mclk_event(struct snd_soc_dapm_widget *w,
+static int msm8974_enable_codec_ext_clk(struct snd_soc_codec *codec, int enable,
+ bool dapm)
+{
+ int ret = 0;
+ pr_debug("%s: enable = %d clk_users = %d\n",
+ __func__, enable, clk_users);
+
+ mutex_lock(&cdc_mclk_mutex);
+ if (enable) {
+ if (!codec_clk) {
+ dev_err(codec->dev, "%s: did not get Taiko MCLK\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ clk_users++;
+ if (clk_users != 1)
+ return ret;
+
+ ret = qpnp_clkdiv_enable(codec_clk);
+ if (ret) {
+ dev_err(codec->dev, "%s: Error enabling taiko MCLK\n",
+ __func__);
+ return -ENODEV;
+ }
+ taiko_mclk_enable(codec, 1, dapm);
+ } else {
+ if (clk_users > 0) {
+ clk_users--;
+ if (clk_users == 0) {
+ taiko_mclk_enable(codec, 0, dapm);
+ qpnp_clkdiv_disable(codec_clk);
+ }
+ } else {
+ pr_err("%s: Error releasing Tabla MCLK\n", __func__);
+ ret = -EINVAL;
+ }
+ }
+ mutex_unlock(&cdc_mclk_mutex);
+ return ret;
+}
+
+static int msm8974_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
+ pr_debug("%s: event = %d\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ return msm8974_enable_codec_ext_clk(w->codec, 1, true);
+ case SND_SOC_DAPM_POST_PMD:
+ return msm8974_enable_codec_ext_clk(w->codec, 0, true);
+ }
+
return 0;
}
-static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
+static const struct snd_soc_dapm_widget msm8974_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
- msm_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ msm8974_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SPK("Ext Spk Bottom Pos", msm_spkramp_event),
SND_SOC_DAPM_SPK("Ext Spk Bottom Neg", msm_spkramp_event),
@@ -328,7 +385,6 @@
SND_SOC_DAPM_MIC("Handset Mic", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
- SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL),
SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL),
@@ -338,92 +394,6 @@
SND_SOC_DAPM_MIC("Digital Mic4", NULL),
SND_SOC_DAPM_MIC("Digital Mic5", NULL),
SND_SOC_DAPM_MIC("Digital Mic6", NULL),
-
-};
-
-static const struct snd_soc_dapm_route common_audio_map[] = {
-
- {"RX_BIAS", NULL, "MCLK"},
- {"LDO_H", NULL, "MCLK"},
-
- /* Speaker path */
- {"Ext Spk Bottom Pos", NULL, "LINEOUT1"},
- {"Ext Spk Bottom Neg", NULL, "LINEOUT3"},
-
- {"Ext Spk Top Pos", NULL, "LINEOUT2"},
- {"Ext Spk Top Neg", NULL, "LINEOUT4"},
-
- /* Microphone path */
- {"AMIC1", NULL, "MIC BIAS1 Internal1"},
- {"MIC BIAS1 Internal1", NULL, "Handset Mic"},
-
- {"AMIC2", NULL, "MIC BIAS2 External"},
- {"MIC BIAS2 External", NULL, "Headset Mic"},
-
- /**
- * AMIC3 and AMIC4 inputs are connected to ANC microphones
- * These mics are biased differently on CDP and FLUID
- * routing entries below are based on bias arrangement
- * on FLUID.
- */
- {"AMIC3", NULL, "MIC BIAS3 Internal1"},
- {"MIC BIAS3 Internal1", NULL, "ANCRight Headset Mic"},
-
- {"AMIC4", NULL, "MIC BIAS1 Internal2"},
- {"MIC BIAS1 Internal2", NULL, "ANCLeft Headset Mic"},
-
- {"HEADPHONE", NULL, "LDO_H"},
-
- /**
- * The digital Mic routes are setup considering
- * fluid as default device.
- */
-
- /**
- * Digital Mic1. Front Bottom left Digital Mic on Fluid and MTP.
- * Digital Mic GM5 on CDP mainboard.
- * Conncted to DMIC2 Input on Tabla codec.
- */
- {"DMIC2", NULL, "MIC BIAS1 External"},
- {"MIC BIAS1 External", NULL, "Digital Mic1"},
-
- /**
- * Digital Mic2. Front Bottom right Digital Mic on Fluid and MTP.
- * Digital Mic GM6 on CDP mainboard.
- * Conncted to DMIC1 Input on Tabla codec.
- */
- {"DMIC1", NULL, "MIC BIAS1 External"},
- {"MIC BIAS1 External", NULL, "Digital Mic2"},
-
- /**
- * Digital Mic3. Back Bottom Digital Mic on Fluid.
- * Digital Mic GM1 on CDP mainboard.
- * Conncted to DMIC4 Input on Tabla codec.
- */
- {"DMIC4", NULL, "MIC BIAS3 External"},
- {"MIC BIAS3 External", NULL, "Digital Mic3"},
-
- /**
- * Digital Mic4. Back top Digital Mic on Fluid.
- * Digital Mic GM2 on CDP mainboard.
- * Conncted to DMIC3 Input on Tabla codec.
- */
- {"DMIC3", NULL, "MIC BIAS3 External"},
- {"MIC BIAS3 External", NULL, "Digital Mic4"},
-
- /**
- * Digital Mic5. Front top Digital Mic on Fluid.
- * Digital Mic GM3 on CDP mainboard.
- * Conncted to DMIC5 Input on Tabla codec.
- */
- {"DMIC5", NULL, "MIC BIAS4 External"},
- {"MIC BIAS4 External", NULL, "Digital Mic5"},
-
- /* Tabla digital Mic6 - back bottom digital Mic on Liquid and
- * bottom mic on CDP. FLUID/MTP do not have dmic6 installed.
- */
- {"DMIC6", NULL, "MIC BIAS4 External"},
- {"MIC BIAS4 External", NULL, "Digital Mic6"},
};
static const char *const spk_function[] = {"Off", "On"};
@@ -671,11 +641,8 @@
if (err < 0)
return err;
- snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
- ARRAY_SIZE(msm_dapm_widgets));
-
- snd_soc_dapm_add_routes(dapm, common_audio_map,
- ARRAY_SIZE(common_audio_map));
+ snd_soc_dapm_new_controls(dapm, msm8974_dapm_widgets,
+ ARRAY_SIZE(msm8974_dapm_widgets));
snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
@@ -790,7 +757,7 @@
};
/* Digital audio interface glue - connects codec <---> CPU */
-static struct snd_soc_dai_link msm_dai[] = {
+static struct snd_soc_dai_link msm8974_dai[] = {
/* FrontEnd DAI Links */
{
.name = "MSM8974 Media1",
@@ -954,58 +921,148 @@
},
};
-static struct snd_soc_card snd_soc_card_msm = {
+struct snd_soc_card snd_soc_card_msm8974 = {
.name = "msm8974-taiko-snd-card",
- .dai_link = msm_dai,
- .num_links = ARRAY_SIZE(msm_dai),
+ .dai_link = msm8974_dai,
+ .num_links = ARRAY_SIZE(msm8974_dai),
};
-static struct platform_device *msm_snd_device;
-
-static void msm_free_headset_mic_gpios(void)
+static int msm8974_prepare_codec_mclk(struct snd_soc_card *card)
{
- if (msm_headset_gpios_configured) {
- gpio_free(PM8921_GPIO_PM_TO_SYS(23));
- gpio_free(PM8921_GPIO_PM_TO_SYS(35));
- }
-}
-
-static int __init msm_audio_init(void)
-{
- int ret = 0;
-
- mutex_init(&cdc_mclk_mutex);
- if (!machine_is_msm8974_sim()) {
- pr_info("%s: Not msm8974 machine type\n", __func__);
- return -ENODEV;
- }
- msm_snd_device = platform_device_alloc("soc-audio", 0);
- if (!msm_snd_device) {
- pr_err("Platform device allocation failed\n");
- return -ENOMEM;
+ struct msm8974_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ int ret;
+ if (pdata->mclk_gpio) {
+ ret = gpio_request(pdata->mclk_gpio, "TAIKO_CODEC_PMIC_MCLK");
+ if (ret) {
+ dev_err(card->dev,
+ "%s: Failed to request taiko mclk gpio %d\n",
+ __func__, pdata->mclk_gpio);
+ return ret;
+ }
}
- platform_set_drvdata(msm_snd_device, &snd_soc_card_msm);
- ret = platform_device_add(msm_snd_device);
+ codec_clk = qpnp_clkdiv_get(card->dev, "taiko-mclk");
+ if (IS_ERR(codec_clk)) {
+ dev_err(card->dev,
+ "%s: Failed to request taiko mclk from pmic %ld\n",
+ __func__, PTR_ERR(codec_clk));
+ return -ENODEV ;
+ }
+
+ ret = qpnp_clkdiv_config(codec_clk, Q_CLKDIV_XO_DIV_2);
if (ret) {
- platform_device_put(msm_snd_device);
- return ret;
+ dev_err(card->dev, "%s: Failed to set taiko mclk to %u\n",
+ __func__, pdata->mclk_gpio);
+ return ret;
}
- return ret;
-
+ return 0;
}
-module_init(msm_audio_init);
-static void __exit msm_audio_exit(void)
+static __devinit int msm8974_asoc_machine_probe(struct platform_device *pdev)
{
- if (!machine_is_msm8974_sim()) {
- pr_err("%s: Not the right machine type\n", __func__);
- return ;
+ struct snd_soc_card *card = &snd_soc_card_msm8974;
+ struct msm8974_asoc_mach_data *pdata;
+ int ret;
+
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "No platform supplied from device tree\n");
+ return -EINVAL;
}
- msm_free_headset_mic_gpios();
- platform_device_unregister(msm_snd_device);
+
+ pdata = devm_kzalloc(&pdev->dev,
+ sizeof(struct msm8974_asoc_mach_data), GFP_KERNEL);
+ if (!pdata) {
+ dev_err(&pdev->dev, "Can't allocate msm8974_asoc_mach_data\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ card->dev = &pdev->dev;
+ platform_set_drvdata(pdev, card);
+ snd_soc_card_set_drvdata(card, pdata);
+
+ ret = snd_soc_of_parse_card_name(card, "qcom,model");
+ if (ret)
+ goto err;
+
+ ret = snd_soc_of_parse_audio_routing(card,
+ "qcom,audio-routing");
+ if (ret)
+ goto err;
+
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "qcom,taiko-mclk-clk-freq", &pdata->mclk_freq);
+ if (ret) {
+ dev_err(&pdev->dev, "Looking up %s property in node %s failed",
+ "qcom,taiko-mclk-clk-freq",
+ pdev->dev.of_node->full_name);
+ goto err;
+ }
+
+ if (pdata->mclk_freq != 9600000) {
+ dev_err(&pdev->dev, "unsupported taiko mclk freq %u\n",
+ pdata->mclk_freq);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ pdata->mclk_gpio = of_get_named_gpio(pdev->dev.of_node,
+ "qcom,cdc-mclk-gpios", 0);
+ if (pdata->mclk_gpio < 0) {
+ dev_err(&pdev->dev,
+ "Looking up %s property in node %s failed %d\n",
+ "qcom, cdc-mclk-gpios", pdev->dev.of_node->full_name,
+ pdata->mclk_gpio);
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = msm8974_prepare_codec_mclk(card);
+ if (ret)
+ goto err;
+
+ ret = snd_soc_register_card(card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+ ret);
+ goto err;
+ }
+ mutex_init(&cdc_mclk_mutex);
+ return 0;
+err:
+ devm_kfree(&pdev->dev, pdata);
+ return ret;
}
-module_exit(msm_audio_exit);
+
+static int __devexit msm8974_asoc_machine_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct msm8974_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+
+ gpio_free(pdata->mclk_gpio);
+ snd_soc_unregister_card(card);
+
+ return 0;
+}
+
+static const struct of_device_id msm8974_asoc_machine_of_match[] = {
+ { .compatible = "qcom,msm8974-audio-taiko", },
+ {},
+};
+
+static struct platform_driver msm8974_asoc_machine_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
+ .of_match_table = msm8974_asoc_machine_of_match,
+ },
+ .probe = msm8974_asoc_machine_probe,
+ .remove = __devexit_p(msm8974_asoc_machine_remove),
+};
+module_platform_driver(msm8974_asoc_machine_driver);
MODULE_DESCRIPTION("ALSA SoC msm");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
+MODULE_DEVICE_TABLE(of, msm8974_asoc_machine_of_match);
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 65cee5d..f989b17 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -2046,6 +2046,8 @@
be_disconnect(fe, SNDRV_PCM_STREAM_PLAYBACK);
}
+ fe_path_put(&list);
+
capture:
/* skip if FE doesn't have capture capability */
if (!fe->cpu_dai->driver->capture.channels_min)