Merge "ARM: dts: msm: Add CX regulator Phandle to MDP node"
diff --git a/Documentation/devicetree/bindings/arm/msm/msm_tspp.txt b/Documentation/devicetree/bindings/arm/msm/msm_tspp.txt
index 5692ad2..4a1fb59 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm_tspp.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm_tspp.txt
@@ -38,7 +38,6 @@
the below optional properties:
- qcom,msm-bus,name
- qcom,msm-bus,num-cases
- - qcom,msm-bus,active-only
- qcom,msm-bus,num-paths
- qcom,msm-bus,vectors-KBps
@@ -85,7 +84,6 @@
qcom,msm-bus,name = "tsif";
qcom,msm-bus,num-cases = <2>;
- qcom,msm-bus,active-only = <0>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<82 512 0 0>, /* No vote */
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
index 7187908..cda437a 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
@@ -46,12 +46,6 @@
- qcom,platform-te-gpio: Specifies the gpio used for TE.
- qcom,platform-mode-gpio: Select video/command mode of panel through gpio when it supports
both modes.
-- qcom,platform-reset-sequence: An array that lists the
- sequence of reset gpio values and sleeps
- Each command will have the format defined
- as below:
- --> Reset GPIO value
- --> Sleep value (in ms)
Example:
mdss_dsi0: qcom,mdss_dsi@fd922800 {
@@ -77,7 +71,6 @@
qcom,platform-te-gpio = <&msmgpio 24 0>;
qcom,platform-enable-gpio = <&msmgpio 58 1>;
qcom,platform-mode-gpio = <&msmgpio 7 0>;
- qcom,platform-reset-sequence = <1 25 0 20 1 10>;
qcom,platform-supply-entry1 {
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <2800000>;
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index 20ef421..1a44f5a 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -242,6 +242,14 @@
in dsi controller.
"high" = Set GPIO to HIGH
"low" = Set GPIO to LOW
+- qcom,partial-update-enabled: Boolean used to enable partial
+ panel update for command mode panels.
+- qcom,mdss-dsi-reset-sequence: An array that lists the
+ sequence of reset gpio values and sleeps
+ Each command will have the format defined
+ as below:
+ --> Reset GPIO value
+ --> Sleep value (in ms)
Note, if a given optional qcom,* binding is not present, then the driver will configure
@@ -333,5 +341,7 @@
qcom,mdss-pan-physical-width-dimension = <60>;
qcom,mdss-pan-physical-height-dimension = <140>;
qcom,mdss-dsi-panel-mode-gpio-state = "low";
+ qcom,partial-update-enabled;
+ qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>;
};
};
diff --git a/Documentation/devicetree/bindings/input/touchscreen/ft5x06-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/ft5x06-ts.txt
index c563067e..398e253 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/ft5x06-ts.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/ft5x06-ts.txt
@@ -46,6 +46,7 @@
- focaltech,fw-delay-era-flsh-ms : specify the erase flash delay in ms for firmware upgrade
- focaltech,fw-auto-cal : specify whether calibration is needed after firmware upgrade
- focaltech,fw-vkey-support : specify if virtual keys are supported through firmware
+ - focaltech,ignore-id-check : specify ignore family-id check
Example:
i2c@f9923000{
diff --git a/Documentation/devicetree/bindings/media/video/msm-cci.txt b/Documentation/devicetree/bindings/media/video/msm-cci.txt
index c60441f..317c078 100644
--- a/Documentation/devicetree/bindings/media/video/msm-cci.txt
+++ b/Documentation/devicetree/bindings/media/video/msm-cci.txt
@@ -49,6 +49,7 @@
Required properties:
- compatible : should be manufacturer name followed by sensor name
- "qcom,s5k3l1yx"
+ - "sne,imx134"
- "qcom,imx135"
- "shinetech,gc0339"
- "shinetech,hi256"
diff --git a/Documentation/devicetree/bindings/nfc/nfc-nci.txt b/Documentation/devicetree/bindings/nfc/nfc-nci.txt
index f70d90f..cdd1e68 100644
--- a/Documentation/devicetree/bindings/nfc/nfc-nci.txt
+++ b/Documentation/devicetree/bindings/nfc/nfc-nci.txt
@@ -8,6 +8,8 @@
- reg: NCI i2c slave address.
- qcom,dis-gpio: specific gpio for hardware reset.
- qcom,irq-gpio: specific gpio for read interrupt.
+- qcom,clk-src: nfc clock source ("BBCLK2", "RFCLK3", "GPCLK", ...)
+- qcom,clk-en-gpio: msm gpio clock,used ony if clock source is msm gpio
- interrupt-parent: Should be phandle for the interrupt controller
that services interrupts for this device.
- interrupts: should contain the NFC interrupt. NFC has one read interrupt.
@@ -21,6 +23,8 @@
reg = <0x0e>;
qcom,irq-gpio = <&msmgpio 21 0x00>;
qcom,dis-gpio = <&msmgpio 20 0x00>;
+ qcom,clk-src = "BBCLK2";
+ qcom,clk-en-gpio = <&msmgpio 0 0x00>;
interrupt-parent = <&msmgpio>;
interrupts = <21 0>;
qcom,clk-gpio = <&pm8226_gpios 3 0>;
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1eec990..35e7324 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -45,6 +45,7 @@
samsung Samsung Semiconductor
sbs Smart Battery System
schindler Schindler
+sne Sony
stk Sensortek Technology Corporation.(formerly Sitronix Technology Co., Ltd.)
shinetech Shine Tech Corporation, Ltd.
sil Silicon Image
diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt
index a419f5e..8a20b47 100644
--- a/Documentation/sysctl/kernel.txt
+++ b/Documentation/sysctl/kernel.txt
@@ -26,6 +26,7 @@
- boot_reason [ ARM only ]
- callhome [ S390 only ]
- cap_last_cap
+- cold_boot [ ARM only ]
- core_pattern
- core_pipe_limit
- core_uses_pid
@@ -176,6 +177,16 @@
Highest valid capability of the running kernel. Exports
CAP_LAST_CAP from the kernel.
+===============================================================
+
+cold_boot
+
+ARM -- indicator for system cold boot
+
+A single bit will be set in the unsigned integer value to identify
+whether the device was booted from a cold or warm state. Zero
+indicating a warm boot and one indicating a cold boot.
+
==============================================================
core_pattern:
diff --git a/arch/arm/boot/dts/apq8074-v1-ion.dtsi b/arch/arm/boot/dts/apq8074-v1-ion.dtsi
new file mode 100644
index 0000000..49d7ee1
--- /dev/null
+++ b/arch/arm/boot/dts/apq8074-v1-ion.dtsi
@@ -0,0 +1,22 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ qcom,ion {
+ qcom,ion-heap@23 { /* OTHER PIL HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <23>;
+ qcom,heap-align = <0x1000>;
+ qcom,memory-fixed = <0x0dc00000 0x1e00000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/apq8074-v1.dtsi b/arch/arm/boot/dts/apq8074-v1.dtsi
index c4e7b7c..59e7f7f 100644
--- a/arch/arm/boot/dts/apq8074-v1.dtsi
+++ b/arch/arm/boot/dts/apq8074-v1.dtsi
@@ -17,6 +17,7 @@
*/
/include/ "msm8974-v1.dtsi"
+/include/ "apq8074-v1-ion.dtsi"
&soc {
qcom,qseecom@a700000 {
diff --git a/arch/arm/boot/dts/apq8074-v2.0-1-ion.dtsi b/arch/arm/boot/dts/apq8074-v2.0-1-ion.dtsi
new file mode 100644
index 0000000..49d7ee1
--- /dev/null
+++ b/arch/arm/boot/dts/apq8074-v2.0-1-ion.dtsi
@@ -0,0 +1,22 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ qcom,ion {
+ qcom,ion-heap@23 { /* OTHER PIL HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <23>;
+ qcom,heap-align = <0x1000>;
+ qcom,memory-fixed = <0x0dc00000 0x1e00000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/apq8074-v2.0-1.dtsi b/arch/arm/boot/dts/apq8074-v2.0-1.dtsi
index 2b75fa2..3575c92 100644
--- a/arch/arm/boot/dts/apq8074-v2.0-1.dtsi
+++ b/arch/arm/boot/dts/apq8074-v2.0-1.dtsi
@@ -17,6 +17,7 @@
*/
/include/ "msm8974-v2.0-1.dtsi"
+/include/ "apq8074-v2.0-1-ion.dtsi"
&soc {
qcom,qseecom@a700000 {
diff --git a/arch/arm/boot/dts/apq8074-v2.2-ion.dtsi b/arch/arm/boot/dts/apq8074-v2.2-ion.dtsi
new file mode 100644
index 0000000..49d7ee1
--- /dev/null
+++ b/arch/arm/boot/dts/apq8074-v2.2-ion.dtsi
@@ -0,0 +1,22 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ qcom,ion {
+ qcom,ion-heap@23 { /* OTHER PIL HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <23>;
+ qcom,heap-align = <0x1000>;
+ qcom,memory-fixed = <0x0dc00000 0x1e00000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/apq8074-v2.2.dtsi b/arch/arm/boot/dts/apq8074-v2.2.dtsi
index ddf7ec8..18f00c5 100644
--- a/arch/arm/boot/dts/apq8074-v2.2.dtsi
+++ b/arch/arm/boot/dts/apq8074-v2.2.dtsi
@@ -17,6 +17,7 @@
*/
/include/ "msm8974-v2.2.dtsi"
+/include/ "apq8074-v2.2-ion.dtsi"
&soc {
qcom,qseecom@a700000 {
diff --git a/arch/arm/boot/dts/batterydata-mtp-3000mah.dtsi b/arch/arm/boot/dts/batterydata-mtp-3000mah.dtsi
new file mode 100644
index 0000000..8dc6f71
--- /dev/null
+++ b/arch/arm/boot/dts/batterydata-mtp-3000mah.dtsi
@@ -0,0 +1,108 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,mtp-3000mah {
+ qcom,fcc-mah = <3000>;
+ qcom,default-rbatt-mohm = <113>;
+ qcom,max-voltage-uv = <4200000>;
+ qcom,rbatt-capacitive-mohm = <50>;
+ qcom,v-cutoff-uv = <3400000>;
+ qcom,chg-term-ua = <200000>;
+ qcom,batt-id-kohm = <300>;
+
+ qcom,fcc-temp-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-data = <3030 3033 3037 3035 3031>;
+ };
+
+ qcom,pc-temp-ocv-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 16 13 11>,
+ <10 9 8 7 6>,
+ <5 4 3 2 1>,
+ <0>;
+ qcom,lut-data = <4191 4188 4183 4179 4174>,
+ <4106 4125 4127 4125 4121>,
+ <4046 4082 4082 4080 4077>,
+ <3966 4038 4044 4040 4035>,
+ <3922 3983 3994 3998 3997>,
+ <3886 3949 3966 3966 3962>,
+ <3856 3908 3937 3935 3931>,
+ <3832 3875 3908 3907 3903>,
+ <3814 3847 3874 3878 3875>,
+ <3799 3826 3831 3832 3830>,
+ <3787 3807 3811 3811 3809>,
+ <3775 3793 3795 3795 3793>,
+ <3764 3782 3783 3783 3781>,
+ <3752 3775 3773 3772 3769>,
+ <3739 3768 3766 3762 3755>,
+ <3725 3756 3756 3747 3733>,
+ <3710 3732 3734 3725 3711>,
+ <3696 3707 3705 3697 3684>,
+ <3681 3695 3686 3678 3667>,
+ <3667 3690 3684 3676 3665>,
+ <3658 3688 3683 3675 3664>,
+ <3646 3685 3681 3674 3663>,
+ <3631 3682 3679 3673 3660>,
+ <3612 3677 3676 3669 3655>,
+ <3589 3667 3666 3660 3639>,
+ <3560 3643 3636 3630 3599>,
+ <3523 3600 3586 3581 3546>,
+ <3474 3537 3518 3516 3477>,
+ <3394 3446 3425 3427 3379>,
+ <3257 3306 3273 3283 3213>,
+ <3000 3000 3000 3000 3000>;
+ };
+
+ qcom,rbatt-sf-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 16 13 11>,
+ <10 9 8 7 6>,
+ <5 4 3 2 1>;
+ qcom,lut-data = <1025 208 100 85 80>,
+ <1025 208 100 85 80>,
+ <1032 225 103 87 81>,
+ <959 249 107 91 82>,
+ <954 249 109 92 84>,
+ <953 255 117 94 84>,
+ <957 230 123 98 87>,
+ <968 216 134 102 91>,
+ <983 212 138 112 95>,
+ <1002 213 103 89 82>,
+ <1030 215 100 86 81>,
+ <1066 219 101 89 83>,
+ <1115 224 104 92 85>,
+ <1182 234 106 94 86>,
+ <1263 246 108 92 84>,
+ <1357 257 107 87 81>,
+ <1464 261 102 85 80>,
+ <1564 256 101 84 80>,
+ <1637 268 100 84 80>,
+ <1580 276 102 87 81>,
+ <1617 285 104 87 82>,
+ <1670 298 107 91 82>,
+ <1725 315 108 92 83>,
+ <1785 338 112 92 83>,
+ <1850 361 111 91 82>,
+ <1921 378 108 89 84>,
+ <2000 394 112 92 87>,
+ <2119 430 121 99 94>,
+ <2795 497 144 114 104>,
+ <8769 1035 672 322 234>;
+ };
+};
diff --git a/arch/arm/boot/dts/batterydata-palladium.dtsi b/arch/arm/boot/dts/batterydata-palladium.dtsi
new file mode 100644
index 0000000..95c4ff1
--- /dev/null
+++ b/arch/arm/boot/dts/batterydata-palladium.dtsi
@@ -0,0 +1,111 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,palladium-batterydata {
+ qcom,fcc-mah = <1500>;
+ qcom,default-rbatt-mohm = <210>;
+ qcom,rbatt-capacitive-mohm = <50>;
+ qcom,flat-ocv-threshold-uv = <3800000>;
+ qcom,max-voltage-uv = <4200000>;
+ qcom,v-cutoff-uv = <3400000>;
+ qcom,chg-term-ua = <100000>;
+ qcom,batt-id-kohm = <75>;
+
+ qcom,fcc-temp-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-data = <1467 1470 1473 1473 1470>;
+ };
+
+ qcom,pc-temp-ocv-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 16 13 11>,
+ <10 9 8 7 6>,
+ <5 4 3 2 1>,
+ <0>;
+ qcom,lut-data = <4175 4173 4167 4162 4157>,
+ <4097 4111 4112 4110 4107>,
+ <4039 4075 4072 4068 4064>,
+ <3963 4017 4025 4026 4025>,
+ <3920 3969 3984 3989 3988>,
+ <3887 3932 3957 3958 3955>,
+ <3856 3898 3929 3928 3925>,
+ <3830 3868 3900 3901 3898>,
+ <3808 3843 3858 3863 3862>,
+ <3793 3821 3827 3827 3827>,
+ <3779 3803 3807 3808 3807>,
+ <3768 3788 3792 3793 3792>,
+ <3757 3779 3780 3780 3779>,
+ <3746 3771 3772 3768 3768>,
+ <3734 3762 3765 3759 3749>,
+ <3722 3747 3753 3744 3730>,
+ <3707 3721 3731 3722 3709>,
+ <3693 3705 3704 3696 3683>,
+ <3678 3698 3687 3678 3667>,
+ <3664 3693 3683 3676 3665>,
+ <3656 3690 3682 3675 3664>,
+ <3646 3687 3681 3674 3662>,
+ <3634 3683 3680 3672 3661>,
+ <3618 3677 3676 3668 3656>,
+ <3599 3667 3667 3655 3639>,
+ <3573 3645 3638 3623 3603>,
+ <3541 3607 3591 3575 3554>,
+ <3496 3550 3528 3511 3490>,
+ <3428 3469 3445 3423 3400>,
+ <3312 3342 3308 3280 3250>,
+ <3000 3000 3000 3000 3000>;
+ };
+
+ qcom,rbatt-sf-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 16 13 11>,
+ <10 9 8 7 6>,
+ <5 4 3 2 1>,
+ <0>;
+ qcom,lut-data = <909 216 100 85 84>,
+ <859 238 106 88 86>,
+ <860 237 105 88 86>,
+ <808 239 107 90 88>,
+ <801 234 111 94 90>,
+ <801 230 118 97 92>,
+ <801 224 123 100 95>,
+ <807 221 128 106 99>,
+ <818 221 111 101 97>,
+ <841 225 101 88 87>,
+ <870 229 101 88 87>,
+ <906 235 103 91 90>,
+ <950 243 106 93 93>,
+ <998 253 110 93 96>,
+ <1051 263 113 94 90>,
+ <1116 272 113 91 88>,
+ <1200 275 111 91 88>,
+ <1312 298 108 90 87>,
+ <1430 329 104 88 87>,
+ <1484 351 107 91 89>,
+ <1446 345 110 93 90>,
+ <1398 344 112 94 90>,
+ <1466 358 115 96 91>,
+ <1490 357 117 96 90>,
+ <1589 365 117 94 89>,
+ <1828 379 111 91 88>,
+ <2151 399 111 93 91>,
+ <2621 436 117 98 95>,
+ <3404 496 130 106 100>,
+ <8212 616 150 1906 134>,
+ <135251 124940 59087 49820 29672>;
+ };
+};
diff --git a/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
index 23091f0..2963d15 100644
--- a/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
@@ -76,5 +76,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
index 4230018..23b65f3 100644
--- a/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
@@ -118,6 +118,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
index c9d887b..83351ca 100644
--- a/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
@@ -78,6 +78,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
index 829197a..9bb11da 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
@@ -268,6 +268,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
index 0918cf4..a24cb58 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
@@ -531,6 +531,9 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
index 6d68a3e..79618b9 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
@@ -527,6 +527,9 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
index 49aef24..2312b37 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
@@ -582,6 +582,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
index 89a5063..9477c56 100644
--- a/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
@@ -261,6 +261,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi b/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
index c627e7a..285d8fc 100644
--- a/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
@@ -67,6 +67,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <4>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-sim-video.dtsi b/arch/arm/boot/dts/dsi-panel-sim-video.dtsi
index ccbb659..501fdde 100644
--- a/arch/arm/boot/dts/dsi-panel-sim-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-sim-video.dtsi
@@ -39,5 +39,6 @@
qcom,on-cmds-dsi-state = "DSI_LP_MODE";
qcom,panel-off-cmds = [22 01 00 00 00 00 02 00 00];
qcom,off-cmds-dsi-state = "DSI_LP_MODE";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
index 7bb414a..bb8389f 100644
--- a/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
@@ -115,5 +115,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
index 021ddef..f7de416 100644
--- a/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
@@ -92,5 +92,6 @@
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
index f6e6df8..d170833 100644
--- a/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
@@ -166,5 +166,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <2>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
index fae4834..546a90f 100644
--- a/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
@@ -164,5 +164,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/msm8226-mdss.dtsi b/arch/arm/boot/dts/msm8226-mdss.dtsi
index a82b0af..3e2507ff 100644
--- a/arch/arm/boot/dts/msm8226-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8226-mdss.dtsi
@@ -79,7 +79,6 @@
00 00 00 00 0a 00 00 01 97
00 00 00 00 0f 00 00 01 97
00 c0 00 00 00 00 00 01 bb];
- qcom,platform-reset-sequence = <1 20 0 1 1 20>;
qcom,platform-supply-entry1 {
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <2800000>;
diff --git a/arch/arm/boot/dts/msm8226-mtp.dtsi b/arch/arm/boot/dts/msm8226-mtp.dtsi
index 318d4fc..dbd2031 100644
--- a/arch/arm/boot/dts/msm8226-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8226-mtp.dtsi
@@ -40,6 +40,8 @@
reg = <0x0e>;
qcom,irq-gpio = <&msmgpio 21 0x00>;
qcom,dis-gpio = <&msmgpio 20 0x00>;
+ qcom,clk-src = "BBCLK2";
+ qcom,clk-en-gpio = <&msmgpio 0 0x00>;
interrupt-parent = <&msmgpio>;
interrupts = <21 0>;
qcom,clk-gpio = <&pm8226_gpios 3 0>;
@@ -462,6 +464,16 @@
};
};
+/ {
+ mtp_batterydata: qcom,battery-data {
+ qcom,rpull-up-kohm = <100>;
+ qcom,vref-batt-therm = <1800000>;
+
+ /include/ "batterydata-palladium.dtsi"
+ /include/ "batterydata-mtp-3000mah.dtsi"
+ };
+};
+
&pm8226_bms {
status = "ok";
qcom,enable-fcc-learning;
@@ -469,10 +481,12 @@
qcom,min-fcc-ocv-pc = <30>;
qcom,min-fcc-learning-samples = <5>;
qcom,fcc-resolution = <10>;
+ qcom,battery-data = <&mtp_batterydata>;
};
&pm8226_chg {
qcom,charging-disabled;
+ qcom,battery-data = <&mtp_batterydata>;
};
&slim_msm {
diff --git a/arch/arm/boot/dts/msm8226-v1-pm.dtsi b/arch/arm/boot/dts/msm8226-v1-pm.dtsi
index dcf46e6..1530074 100644
--- a/arch/arm/boot/dts/msm8226-v1-pm.dtsi
+++ b/arch/arm/boot/dts/msm8226-v1-pm.dtsi
@@ -266,6 +266,7 @@
<38 108>,
<39 109>,
<40 110>,
+ <41 115>,
<54 111>,
<55 113>;
};
diff --git a/arch/arm/boot/dts/msm8226-v2-cdp.dts b/arch/arm/boot/dts/msm8226-v2-cdp.dts
index 3d40180..3302d26 100644
--- a/arch/arm/boot/dts/msm8226-v2-cdp.dts
+++ b/arch/arm/boot/dts/msm8226-v2-cdp.dts
@@ -20,3 +20,7 @@
compatible = "qcom,msm8226-cdp", "qcom,msm8226", "qcom,cdp";
qcom,board-id = <1 0>;
};
+
+&hsic_host {
+ status = "ok";
+};
diff --git a/arch/arm/boot/dts/msm8226-v2-pm.dtsi b/arch/arm/boot/dts/msm8226-v2-pm.dtsi
index 9ee47e2..9104cba 100644
--- a/arch/arm/boot/dts/msm8226-v2-pm.dtsi
+++ b/arch/arm/boot/dts/msm8226-v2-pm.dtsi
@@ -268,6 +268,7 @@
<38 108>,
<39 109>,
<40 110>,
+ <41 115>,
<54 111>,
<55 113>;
};
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index cfb6bed..8958984 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -299,6 +299,37 @@
qcom,android-usb-swfi-latency = <1>;
};
+ hsic_host: hsic@f9a00000 {
+ status = "disabled";
+ compatible = "qcom,hsic-host";
+ reg = <0xf9a00000 0x400>;
+ #address-cells = <0>;
+ interrupt-parent = <&hsic_host>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 136 0
+ 1 &intc 0 148 0
+ 2 &msmgpio 115 0x8>;
+ interrupt-names = "core_irq", "async_irq", "wakeup";
+ hsic_vdd_dig-supply = <&pm8226_s1_corner>;
+ HSIC_GDSC-supply = <&gdsc_usb_hsic>;
+ hsic,strobe-gpio = <&msmgpio 115 0x00>;
+ hsic,data-gpio = <&msmgpio 116 0x00>;
+ hsic,ignore-cal-pad-config;
+ hsic,strobe-pad-offset = <0x2050>;
+ hsic,data-pad-offset = <0x2054>;
+ qcom,phy-susp-sof-workaround;
+ hsic,vdd-voltage-level = <1 5 7>;
+
+ qcom,msm-bus,name = "hsic";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <85 512 0 0>,
+ <85 512 40000 160000>;
+ };
+
wcd9xxx_intc: wcd9xxx-irq {
compatible = "qcom,wcd9xxx-irq";
interrupt-controller;
@@ -1088,6 +1119,10 @@
qcom,core-limit-temp = <80>;
qcom,core-temp-hysteresis = <10>;
qcom,core-control-mask = <0xe>;
+ qcom,hotplug-temp = <110>;
+ qcom,hotplug-temp-hysteresis = <20>;
+ qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor5",
+ "tsens_tz_sensor2", "tsens_tz_sensor2";
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply = <&pm8226_s1_floor_corner>;
diff --git a/arch/arm/boot/dts/msm8610-camera-sensor-cdp-mtp.dtsi b/arch/arm/boot/dts/msm8610-camera-sensor-cdp-mtp.dtsi
index e133117..bdcab77 100644
--- a/arch/arm/boot/dts/msm8610-camera-sensor-cdp-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8610-camera-sensor-cdp-mtp.dtsi
@@ -149,6 +149,44 @@
qcom,cci-master = <0>;
};
+ qcom,camera@34 {
+ compatible = "sne,imx134";
+ reg = <0x34>;
+ qcom,slave-id = <0x34 0x0016 0x0134>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,actuator-src = <&actuator0>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,mount-angle = <90>;
+ qcom,sensor-name = "imx134";
+ cam_vdig-supply = <&pm8110_l2>;
+ cam_vana-supply = <&pm8110_l19>;
+ cam_vio-supply = <&pm8110_l14>;
+ cam_vaf-supply = <&pm8110_l16>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-type = <0 0 0 0>;
+ qcom,cam-vreg-min-voltage = <1200000 1800000 2850000 3000000>;
+ qcom,cam-vreg-max-voltage = <1200000 1800000 2850000 3000000>;
+ qcom,cam-vreg-op-mode = <200000 8000 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ gpios = <&msmgpio 13 0>,
+ <&msmgpio 21 0>,
+ <&msmgpio 20 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK",
+ "CAM_RESET1",
+ "CAM_STANDBY";
+ qcom,csi-lane-assign = <0xe4>;
+ qcom,csi-lane-mask = <0x3>;
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <1>;
+ qcom,cci-master = <0>;
+ };
+
qcom,camera@6d {
compatible = "qcom,ov9724";
reg = <0x6d>;
diff --git a/arch/arm/boot/dts/msm8610-mdss.dtsi b/arch/arm/boot/dts/msm8610-mdss.dtsi
index de74e52..929659e 100644
--- a/arch/arm/boot/dts/msm8610-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8610-mdss.dtsi
@@ -38,9 +38,6 @@
qcom,platform-reset-gpio = <&msmgpio 41 0>;
qcom,platform-te-gpio = <&msmgpio 12 0>;
qcom,platform-mode-gpio = <&msmgpio 7 0>;
-
- qcom,platform-reset-sequence = <1 20 0 2 1 20 2>;
-
qcom,platform-strength-ctrl = [ff 06];
qcom,platform-bist-ctrl = [03 03 00 00 0f 00];
qcom,platform-regulator-settings = [02 08 05 00 20 03];
diff --git a/arch/arm/boot/dts/msm8610-mtp.dtsi b/arch/arm/boot/dts/msm8610-mtp.dtsi
index 1cc3e61..e597353 100644
--- a/arch/arm/boot/dts/msm8610-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8610-mtp.dtsi
@@ -408,8 +408,23 @@
};
};
+/ {
+ mtp_batterydata: qcom,battery-data {
+ qcom,rpull-up-kohm = <100>;
+ qcom,vref-batt-therm = <1800000>;
+
+ /include/ "batterydata-palladium.dtsi"
+ /include/ "batterydata-mtp-3000mah.dtsi"
+ };
+};
+
&pm8110_bms {
status = "ok";
+ qcom,battery-data = <&mtp_batterydata>;
+};
+
+&pm8110_chg {
+ qcom,battery-data = <&mtp_batterydata>;
};
&mdss_mdp {
diff --git a/arch/arm/boot/dts/msm8610.dtsi b/arch/arm/boot/dts/msm8610.dtsi
index 7dcb985..b0f9d62 100644
--- a/arch/arm/boot/dts/msm8610.dtsi
+++ b/arch/arm/boot/dts/msm8610.dtsi
@@ -795,6 +795,10 @@
qcom,core-limit-temp = <80>;
qcom,core-temp-hysteresis = <10>;
qcom,core-control-mask = <0xe>;
+ qcom,hotplug-temp = <110>;
+ qcom,hotplug-temp-hysteresis = <20>;
+ qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor5",
+ "tsens_tz_sensor5", "tsens_tz_sensor5";
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply = <&pm8110_s1_floor_corner>;
diff --git a/arch/arm/boot/dts/msm8926-cdp.dts b/arch/arm/boot/dts/msm8926-cdp.dts
index 7d8d6cf..d6e70e6 100644
--- a/arch/arm/boot/dts/msm8926-cdp.dts
+++ b/arch/arm/boot/dts/msm8926-cdp.dts
@@ -32,3 +32,7 @@
};
};
+
+&hsic_host {
+ status = "ok";
+};
diff --git a/arch/arm/boot/dts/msm8926-qrd-skug.dts b/arch/arm/boot/dts/msm8926-qrd-skug.dts
index a366205..6d907ef 100644
--- a/arch/arm/boot/dts/msm8926-qrd-skug.dts
+++ b/arch/arm/boot/dts/msm8926-qrd-skug.dts
@@ -66,6 +66,7 @@
focaltech,fw-delay-readid-ms = <10>;
focaltech,fw-delay-era-flsh-ms = <2000>;
focaltech,fw-auto-cal;
+ focaltech,ignore-id-check;
};
};
@@ -79,6 +80,23 @@
qcom,key-codes = <139 172 158>;
qcom,y-offset = <0>;
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ keypad-backlight {
+ gpios = <&msmgpio 34 0>;
+ label = "button-backlight";
+ linux,default-trigger = "none";
+ };
+ };
+};
+
+&spmi_bus {
+ qcom,pm8226@0 {
+ qcom,leds@a100 {
+ status = "disable";
+ };
+ };
};
&mdss_dsi0 {
diff --git a/arch/arm/boot/dts/msm8926.dtsi b/arch/arm/boot/dts/msm8926.dtsi
index 2ab272a..e9b7b0b 100644
--- a/arch/arm/boot/dts/msm8926.dtsi
+++ b/arch/arm/boot/dts/msm8926.dtsi
@@ -44,6 +44,11 @@
<0xfc4b80b0 0x8>;
reg-names = "rcg_base", "pte_efuse";
};
+
+ qcom,msm-thermal {
+ qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor5",
+ "tsens_tz_sensor1", "tsens_tz_sensor1";
+ };
};
&pm8226_l3 {
@@ -89,10 +94,18 @@
};
&msmgpio {
- ngpio = <120>;
+ ngpio = <121>;
};
&memory_hole {
qcom,memblock-remove = <0x08000000 0x7500000
0x0fa00000 0x500000>; /* Address and size of the hole */
};
+
+&hsic_host {
+ interrupt-map = <0 &intc 0 136 0
+ 1 &intc 0 148 0
+ 2 &msmgpio 119 0x8>;
+ hsic,strobe-gpio = <&msmgpio 119 0x00>;
+ hsic,data-gpio = <&msmgpio 120 0x00>;
+};
diff --git a/arch/arm/boot/dts/msm8974-mdss.dtsi b/arch/arm/boot/dts/msm8974-mdss.dtsi
index 7181db2..6d5000f 100644
--- a/arch/arm/boot/dts/msm8974-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8974-mdss.dtsi
@@ -90,7 +90,6 @@
qcom,mdss-mdp = <&mdss_mdp>;
qcom,platform-reset-gpio = <&pm8941_gpios 19 0>;
qcom,platform-enable-gpio = <&msmgpio 58 0>;
- qcom,platform-reset-sequence = <1 20 0 200 1 20 2>;
qcom,platform-te-gpio = <&msmgpio 12 0>;
qcom,platform-strength-ctrl = [ff 06];
qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
diff --git a/arch/arm/boot/dts/msm8974-mtp.dtsi b/arch/arm/boot/dts/msm8974-mtp.dtsi
index 7a81e64..b88fbdc 100644
--- a/arch/arm/boot/dts/msm8974-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8974-mtp.dtsi
@@ -374,6 +374,16 @@
qcom,otg-capability;
};
+/ {
+ mtp_batterydata: qcom,battery-data {
+ qcom,rpull-up-kohm = <100>;
+ qcom,vref-batt-therm = <1800000>;
+
+ /include/ "batterydata-palladium.dtsi"
+ /include/ "batterydata-mtp-3000mah.dtsi"
+ };
+};
+
&pm8941_bms {
qcom,enable-fcc-learning;
qcom,min-fcc-learning-soc = <20>;
@@ -381,11 +391,13 @@
qcom,min-fcc-learning-samples = <5>;
qcom,fcc-resolution = <10>;
status = "ok";
+ qcom,battery-data = <&mtp_batterydata>;
};
&pm8941_chg {
status = "ok";
qcom,charging-disabled;
+ qcom,battery-data = <&mtp_batterydata>;
qcom,chgr@1000 {
status = "ok";
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index cc00ce2..3057e6e 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -659,7 +659,6 @@
qcom,msm-bus,name = "tsif";
qcom,msm-bus,num-cases = <2>;
- qcom,msm-bus,active-only = <0>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<82 512 0 0>, /* No vote */
diff --git a/arch/arm/boot/dts/msm8974pro-ab-mtp.dts b/arch/arm/boot/dts/msm8974pro-ab-mtp.dts
index 002baf7..f61b4a6 100644
--- a/arch/arm/boot/dts/msm8974pro-ab-mtp.dts
+++ b/arch/arm/boot/dts/msm8974pro-ab-mtp.dts
@@ -26,3 +26,7 @@
<217 8 0x10000>,
<218 8 0x10000>;
};
+
+&sdhc_1 {
+ qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
+};
diff --git a/arch/arm/boot/dts/msm8974pro-ab.dtsi b/arch/arm/boot/dts/msm8974pro-ab.dtsi
index 5809069..0f37584 100644
--- a/arch/arm/boot/dts/msm8974pro-ab.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-ab.dtsi
@@ -36,6 +36,22 @@
qcom,use-phase-switching;
};
+&krait0_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
+&krait1_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
+&krait2_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
+&krait3_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
&tspp {
vdd_cx-supply = <&pm8841_s2_corner>;
};
diff --git a/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi b/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi
index e0473b7..c38c9e1 100644
--- a/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi
@@ -488,7 +488,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -504,7 +504,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -520,7 +520,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -536,7 +536,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
diff --git a/arch/arm/configs/apq8084_defconfig b/arch/arm/configs/apq8084_defconfig
index 66d66fc..7c1af1a 100644
--- a/arch/arm/configs/apq8084_defconfig
+++ b/arch/arm/configs/apq8084_defconfig
@@ -268,6 +268,7 @@
CONFIG_GPIO_QPNP_PIN_DEBUG=y
CONFIG_POWER_SUPPLY=y
CONFIG_SMB350_CHARGER=y
+CONFIG_SMB349_USB_CHARGER=y
CONFIG_BATTERY_BQ28400=y
CONFIG_QPNP_CHARGER=y
CONFIG_BATTERY_BCL=y
diff --git a/arch/arm/configs/msm8226-perf_defconfig b/arch/arm/configs/msm8226-perf_defconfig
index f8369a9..b822288 100644
--- a/arch/arm/configs/msm8226-perf_defconfig
+++ b/arch/arm/configs/msm8226-perf_defconfig
@@ -387,6 +387,7 @@
CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_LEDS_QPNP=y
CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_GPIO=y
CONFIG_SWITCH=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
diff --git a/arch/arm/configs/msm8226_defconfig b/arch/arm/configs/msm8226_defconfig
index 816b020..546b6b9 100644
--- a/arch/arm/configs/msm8226_defconfig
+++ b/arch/arm/configs/msm8226_defconfig
@@ -413,6 +413,7 @@
CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_LEDS_QPNP=y
CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_GPIO=y
CONFIG_SWITCH=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
diff --git a/arch/arm/configs/msm8610-perf_defconfig b/arch/arm/configs/msm8610-perf_defconfig
index 1a197a3..b91ce3c 100644
--- a/arch/arm/configs/msm8610-perf_defconfig
+++ b/arch/arm/configs/msm8610-perf_defconfig
@@ -284,6 +284,7 @@
CONFIG_HI256=y
CONFIG_OV12830=y
CONFIG_OV5648=y
+CONFIG_IMX134=y
CONFIG_MSM_CAMERA_SENSOR=y
# CONFIG_MSM_CPP is not set
CONFIG_MSM_EEPROM=y
diff --git a/arch/arm/configs/msm8610_defconfig b/arch/arm/configs/msm8610_defconfig
index 8238414..93e8f0f 100644
--- a/arch/arm/configs/msm8610_defconfig
+++ b/arch/arm/configs/msm8610_defconfig
@@ -285,6 +285,7 @@
CONFIG_s5k4e1=y
CONFIG_HI256=y
CONFIG_OV12830=y
+CONFIG_IMX134=y
CONFIG_MSM_CAMERA_SENSOR=y
CONFIG_MSM_EEPROM=y
CONFIG_MSM_CCI=y
diff --git a/arch/arm/configs/msm8974-perf_defconfig b/arch/arm/configs/msm8974-perf_defconfig
index 3224889..329fcec 100644
--- a/arch/arm/configs/msm8974-perf_defconfig
+++ b/arch/arm/configs/msm8974-perf_defconfig
@@ -169,6 +169,7 @@
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index cd0e638..812faf6 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -175,6 +175,7 @@
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
@@ -321,6 +322,7 @@
CONFIG_GPIO_QPNP_PIN_DEBUG=y
CONFIG_POWER_SUPPLY=y
CONFIG_SMB350_CHARGER=y
+CONFIG_SMB349_USB_CHARGER=y
CONFIG_BATTERY_BQ28400=y
CONFIG_QPNP_CHARGER=y
CONFIG_BATTERY_BCL=y
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 07209d7..3a2cd22 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -30,6 +30,7 @@
#endif
extern unsigned int boot_reason;
+extern unsigned int cold_boot;
struct debug_info {
#ifdef CONFIG_HAVE_HW_BREAKPOINT
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 28b114f..7298f9a 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -107,6 +107,9 @@
unsigned int boot_reason;
EXPORT_SYMBOL(boot_reason);
+unsigned int cold_boot;
+EXPORT_SYMBOL(cold_boot);
+
#ifdef MULTI_CPU
struct processor processor __read_mostly;
#endif
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 8410019..3e488e3 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -899,7 +899,7 @@
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs0[] __initdata = {
+static struct acpu_level pro_rev0_2p3g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
@@ -930,38 +930,38 @@
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs2[] __initdata = {
+static struct acpu_level pro_rev0_2p3g_pvs2[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
@@ -992,449 +992,1525 @@
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 845000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1100000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs0[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 845000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1100000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1035000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1075000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1035000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1075000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1050000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1050000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 985000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1025000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 985000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1025000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 840000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1000000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 840000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1000000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 830000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 870000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 885000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 900000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 930000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 945000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 960000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 975000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 830000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 870000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 885000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 900000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 930000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 945000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 960000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 975000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 725000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 725000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 725000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 725000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 735000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 745000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 755000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 765000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 775000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 785000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 795000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 805000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 825000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 835000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 845000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 865000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 875000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 890000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 905000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 920000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 935000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 950000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 725000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 725000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 725000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 725000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 735000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 745000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 755000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 765000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 775000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 785000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 795000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 805000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 825000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 835000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 845000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 865000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 875000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 890000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 905000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 920000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 935000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 950000, 800 },
{ 0, { 0 } }
};
-static struct pvs_table pvs_v1[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct acpu_level pro_rev1_2p5g_pvs0[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 810000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 820000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 830000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 840000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 850000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 860000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 870000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 930000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 940000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 950000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 965000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 980000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 995000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1010000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1040000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1055000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1070000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1085000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1100000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1115000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1120000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 870000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 880000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 890000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 900000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1090000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1105000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1110000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 930000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 945000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 990000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1050000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1065000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1080000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1095000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1100000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1010000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1025000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1040000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1055000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1070000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1085000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1090000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 880000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 890000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 900000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 925000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 940000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 955000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 970000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 985000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1000000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1015000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1030000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1045000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1075000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1080000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 880000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 890000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 960000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 990000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1005000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1035000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1050000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1065000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1070000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 890000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 905000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 935000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 950000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 965000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1040000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1060000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs7[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 895000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 955000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 970000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1000000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1030000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1045000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1050000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs8[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 850000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 990000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1005000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1020000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1035000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1040000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs9[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 790000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 800000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 810000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 820000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 830000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 840000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 850000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 860000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 875000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 890000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 920000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 935000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 950000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 965000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 980000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 995000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1025000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1030000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs10[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 985000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1000000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1015000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1020000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs11[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 855000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 870000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 900000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 930000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 945000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 990000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1010000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs12[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 845000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 875000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 890000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 935000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 950000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 965000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 980000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 995000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1000000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs13[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 775000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 835000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 990000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs14[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 760000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 770000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 780000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 790000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 800000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 810000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 825000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 855000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 870000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 885000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 900000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 915000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 930000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 945000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 960000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 975000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 980000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs15[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 750000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 760000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 770000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 780000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 790000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 800000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 830000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 845000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 875000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 890000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 920000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 935000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 950000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 965000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 970000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs0[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 810000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 820000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 830000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 840000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 850000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 860000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 870000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 880000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 890000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 900000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 910000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 920000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 930000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 955000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 970000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 985000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1000000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1015000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1030000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1045000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1060000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1075000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1090000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1105000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1120000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 810000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 820000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 830000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 840000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 850000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 860000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 870000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 880000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 910000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 920000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 930000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 945000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 960000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 975000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 990000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1005000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1020000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1035000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1065000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1080000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1095000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1110000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 810000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 820000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 830000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 840000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 850000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 860000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 870000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 935000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 965000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 980000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 995000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1010000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1025000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1040000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1055000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 870000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 880000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 890000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 900000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 925000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 940000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 955000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 970000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 985000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1000000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1015000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1030000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1045000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1060000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1075000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1090000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 945000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 960000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 975000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 990000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1005000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1035000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1050000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1065000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1080000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 905000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 935000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 950000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 965000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 980000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 995000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1010000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1025000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1040000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1055000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1070000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 880000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 940000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 955000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 970000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 985000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1015000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1030000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1045000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1060000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs7[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 900000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 915000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 930000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 945000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 960000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 975000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 990000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs8[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 890000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 980000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1025000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs9[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 865000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 895000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 910000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 925000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 940000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1015000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1030000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs10[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 975000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 990000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1005000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1020000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs11[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 790000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 800000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 810000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 820000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 830000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 875000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 890000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 905000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 920000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 965000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 980000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1010000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs12[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 850000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 865000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 880000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 910000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 925000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 940000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 955000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs13[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 870000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 900000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 945000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 960000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 975000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs14[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 815000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 860000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 890000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 905000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 920000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 980000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs15[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 805000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 835000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 738 },
+ { 0, { 0 } }
+};
+
+static struct pvs_table pvs_v1[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 8974v1 1.7GHz Parts */
- [0][0] = { acpu_freq_tbl_v1_pvs0, sizeof(acpu_freq_tbl_v1_pvs0) },
- [0][1] = { acpu_freq_tbl_v1_pvs1, sizeof(acpu_freq_tbl_v1_pvs1) },
- [0][2] = { acpu_freq_tbl_v1_pvs2, sizeof(acpu_freq_tbl_v1_pvs2) },
- [0][3] = { acpu_freq_tbl_v1_pvs3, sizeof(acpu_freq_tbl_v1_pvs3) },
- [0][4] = { acpu_freq_tbl_v1_pvs4, sizeof(acpu_freq_tbl_v1_pvs4) },
+ [0][0][0] = { acpu_freq_tbl_v1_pvs0, sizeof(acpu_freq_tbl_v1_pvs0) },
+ [0][0][1] = { acpu_freq_tbl_v1_pvs1, sizeof(acpu_freq_tbl_v1_pvs1) },
+ [0][0][2] = { acpu_freq_tbl_v1_pvs2, sizeof(acpu_freq_tbl_v1_pvs2) },
+ [0][0][3] = { acpu_freq_tbl_v1_pvs3, sizeof(acpu_freq_tbl_v1_pvs3) },
+ [0][0][4] = { acpu_freq_tbl_v1_pvs4, sizeof(acpu_freq_tbl_v1_pvs4) },
};
-static struct pvs_table pvs_v2[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct pvs_table pvs_v2[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 8974v2 2.0GHz Parts */
- [0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
- [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
- [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
- [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
- [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
- [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
- [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
+ [0][0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
+ [0][0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
+ [0][0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
+ [0][0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
+ [0][0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
+ [0][0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
/* 8974v2 2.3GHz Parts */
- [1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
- [1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
- [1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
- [1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
- [1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
- [1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
- [1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
+ [0][1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
+ [0][1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
+ [0][1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
+ [0][1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
+ [0][1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
+ [0][1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
+ [0][1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
+ [0][1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
/* 8974v2 2.2GHz Parts */
- [2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
- [2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
- [2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
- [2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
- [2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
- [2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
- [2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
- [2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
+ [0][2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
+ [0][2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
+ [0][2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
+ [0][2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
+ [0][2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
+ [0][2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
};
-static struct pvs_table pvs_pro[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct pvs_table pvs_pro[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 2.0 GHz is not used on 8974Pro */
- [0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
- [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
- [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
- [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
- [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
- [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
- [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
+ [0][0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
+ [0][0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
+ [0][0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
+ [0][0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
+ [0][0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
+ [0][0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
/* 8974Pro AB 2.3GHz */
- [1][0] = { acpu_ftbl_pro_2p3g_pvs0, sizeof(acpu_ftbl_pro_2p3g_pvs0) },
- [1][1] = { acpu_ftbl_pro_2p3g_pvs1, sizeof(acpu_ftbl_pro_2p3g_pvs1) },
- [1][2] = { acpu_ftbl_pro_2p3g_pvs2, sizeof(acpu_ftbl_pro_2p3g_pvs2) },
- [1][3] = { acpu_ftbl_pro_2p3g_pvs3, sizeof(acpu_ftbl_pro_2p3g_pvs3) },
- [1][4] = { acpu_ftbl_pro_2p3g_pvs4, sizeof(acpu_ftbl_pro_2p3g_pvs4) },
- [1][5] = { acpu_ftbl_pro_2p3g_pvs5, sizeof(acpu_ftbl_pro_2p3g_pvs5) },
- [1][6] = { acpu_ftbl_pro_2p3g_pvs6, sizeof(acpu_ftbl_pro_2p3g_pvs6) },
- [1][7] = { acpu_ftbl_pro_2p3g_pvs6, sizeof(acpu_ftbl_pro_2p3g_pvs6) },
+ [0][1][0] = { pro_rev0_2p3g_pvs0, sizeof(pro_rev0_2p3g_pvs0) },
+ [0][1][1] = { pro_rev0_2p3g_pvs1, sizeof(pro_rev0_2p3g_pvs1) },
+ [0][1][2] = { pro_rev0_2p3g_pvs2, sizeof(pro_rev0_2p3g_pvs2) },
+ [0][1][3] = { pro_rev0_2p3g_pvs3, sizeof(pro_rev0_2p3g_pvs3) },
+ [0][1][4] = { pro_rev0_2p3g_pvs4, sizeof(pro_rev0_2p3g_pvs4) },
+ [0][1][5] = { pro_rev0_2p3g_pvs5, sizeof(pro_rev0_2p3g_pvs5) },
+ [0][1][6] = { pro_rev0_2p3g_pvs6, sizeof(pro_rev0_2p3g_pvs6) },
+ [0][1][7] = { pro_rev0_2p3g_pvs6, sizeof(pro_rev0_2p3g_pvs6) },
/* 2.2GHz is not used on 8974Pro */
- [2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
- [2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
- [2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
- [2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
- [2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
- [2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
- [2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
- [2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
+ [0][2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
+ [0][2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
+ [0][2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
+ [0][2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
+ [0][2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
+ [0][2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
/* 8974Pro AC 2.5GHz */
- [3][0] = { acpu_ftbl_pro_2p5g_pvs0, sizeof(acpu_ftbl_pro_2p5g_pvs0) },
- [3][1] = { acpu_ftbl_pro_2p5g_pvs1, sizeof(acpu_ftbl_pro_2p5g_pvs1) },
- [3][2] = { acpu_ftbl_pro_2p5g_pvs2, sizeof(acpu_ftbl_pro_2p5g_pvs2) },
- [3][3] = { acpu_ftbl_pro_2p5g_pvs3, sizeof(acpu_ftbl_pro_2p5g_pvs3) },
- [3][4] = { acpu_ftbl_pro_2p5g_pvs4, sizeof(acpu_ftbl_pro_2p5g_pvs4) },
- [3][5] = { acpu_ftbl_pro_2p5g_pvs5, sizeof(acpu_ftbl_pro_2p5g_pvs5) },
- [3][6] = { acpu_ftbl_pro_2p5g_pvs6, sizeof(acpu_ftbl_pro_2p5g_pvs6) },
- [3][7] = { acpu_ftbl_pro_2p5g_pvs6, sizeof(acpu_ftbl_pro_2p5g_pvs6) },
+ [0][3][0] = { pro_rev0_2p5g_pvs0, sizeof(pro_rev0_2p5g_pvs0) },
+ [0][3][1] = { pro_rev0_2p5g_pvs1, sizeof(pro_rev0_2p5g_pvs1) },
+ [0][3][2] = { pro_rev0_2p5g_pvs2, sizeof(pro_rev0_2p5g_pvs2) },
+ [0][3][3] = { pro_rev0_2p5g_pvs3, sizeof(pro_rev0_2p5g_pvs3) },
+ [0][3][4] = { pro_rev0_2p5g_pvs4, sizeof(pro_rev0_2p5g_pvs4) },
+ [0][3][5] = { pro_rev0_2p5g_pvs5, sizeof(pro_rev0_2p5g_pvs5) },
+ [0][3][6] = { pro_rev0_2p5g_pvs6, sizeof(pro_rev0_2p5g_pvs6) },
+ [0][3][7] = { pro_rev0_2p5g_pvs6, sizeof(pro_rev0_2p5g_pvs6) },
+
+ /* 8974Pro AB 2.3GHz */
+ [1][1][0] = { pro_rev1_2p3g_pvs0, sizeof(pro_rev1_2p3g_pvs0) },
+ [1][1][1] = { pro_rev1_2p3g_pvs1, sizeof(pro_rev1_2p3g_pvs1) },
+ [1][1][2] = { pro_rev1_2p3g_pvs2, sizeof(pro_rev1_2p3g_pvs2) },
+ [1][1][3] = { pro_rev1_2p3g_pvs3, sizeof(pro_rev1_2p3g_pvs3) },
+ [1][1][4] = { pro_rev1_2p3g_pvs4, sizeof(pro_rev1_2p3g_pvs4) },
+ [1][1][5] = { pro_rev1_2p3g_pvs5, sizeof(pro_rev1_2p3g_pvs5) },
+ [1][1][6] = { pro_rev1_2p3g_pvs6, sizeof(pro_rev1_2p3g_pvs6) },
+ [1][1][7] = { pro_rev1_2p3g_pvs7, sizeof(pro_rev1_2p3g_pvs7) },
+ [1][1][8] = { pro_rev1_2p3g_pvs8, sizeof(pro_rev1_2p3g_pvs8) },
+ [1][1][9] = { pro_rev1_2p3g_pvs9, sizeof(pro_rev1_2p3g_pvs9) },
+ [1][1][10] = { pro_rev1_2p3g_pvs10, sizeof(pro_rev1_2p3g_pvs10) },
+ [1][1][11] = { pro_rev1_2p3g_pvs11, sizeof(pro_rev1_2p3g_pvs11) },
+ [1][1][12] = { pro_rev1_2p3g_pvs12, sizeof(pro_rev1_2p3g_pvs12) },
+ [1][1][13] = { pro_rev1_2p3g_pvs13, sizeof(pro_rev1_2p3g_pvs13) },
+ [1][1][14] = { pro_rev1_2p3g_pvs14, sizeof(pro_rev1_2p3g_pvs14) },
+ [1][1][15] = { pro_rev1_2p3g_pvs15, sizeof(pro_rev1_2p3g_pvs15) },
+
+ /* 8974Pro AC 2.5GHz */
+ [1][3][0] = { pro_rev1_2p5g_pvs0, sizeof(pro_rev1_2p5g_pvs0) },
+ [1][3][1] = { pro_rev1_2p5g_pvs1, sizeof(pro_rev1_2p5g_pvs1) },
+ [1][3][2] = { pro_rev1_2p5g_pvs2, sizeof(pro_rev1_2p5g_pvs2) },
+ [1][3][3] = { pro_rev1_2p5g_pvs3, sizeof(pro_rev1_2p5g_pvs3) },
+ [1][3][4] = { pro_rev1_2p5g_pvs4, sizeof(pro_rev1_2p5g_pvs4) },
+ [1][3][5] = { pro_rev1_2p5g_pvs5, sizeof(pro_rev1_2p5g_pvs5) },
+ [1][3][6] = { pro_rev1_2p5g_pvs6, sizeof(pro_rev1_2p5g_pvs6) },
+ [1][3][7] = { pro_rev1_2p5g_pvs7, sizeof(pro_rev1_2p5g_pvs7) },
+ [1][3][8] = { pro_rev1_2p5g_pvs8, sizeof(pro_rev1_2p5g_pvs8) },
+ [1][3][9] = { pro_rev1_2p5g_pvs9, sizeof(pro_rev1_2p5g_pvs9) },
+ [1][3][10] = { pro_rev1_2p5g_pvs10, sizeof(pro_rev1_2p5g_pvs10) },
+ [1][3][11] = { pro_rev1_2p5g_pvs11, sizeof(pro_rev1_2p5g_pvs11) },
+ [1][3][12] = { pro_rev1_2p5g_pvs12, sizeof(pro_rev1_2p5g_pvs12) },
+ [1][3][13] = { pro_rev1_2p5g_pvs13, sizeof(pro_rev1_2p5g_pvs13) },
+ [1][3][14] = { pro_rev1_2p5g_pvs14, sizeof(pro_rev1_2p5g_pvs14) },
+ [1][3][15] = { pro_rev1_2p5g_pvs15, sizeof(pro_rev1_2p5g_pvs15) },
};
static struct msm_bus_scale_pdata bus_scale_data __initdata = {
@@ -1470,12 +2546,15 @@
{ }
};
struct acpu_level *l;
- int s, p;
+ int s, p, r;
- for (s = 0; s < NUM_SPEED_BINS; s++)
- for (p = 0; p < NUM_PVS; p++)
- for (l = pvs_v1[s][p].table; l && l->speed.khz; l++)
- l->l2_level = l->l2_level > 5 ? 1 : 0;
+ for (r = 0; r < NUM_PVS_REVS; r++)
+ for (s = 0; s < NUM_SPEED_BINS; s++)
+ for (p = 0; p < NUM_PVS; p++) {
+ l = pvs_v1[r][s][p].table;
+ for (; l && l->speed.khz; l++)
+ l->l2_level = l->l2_level > 5 ? 1 : 0;
+ }
acpuclk_8974_params.l2_freq_tbl = resticted_l2_tbl;
acpuclk_8974_params.l2_freq_tbl_size = sizeof(resticted_l2_tbl);
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 0479844..cf3fac0 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -1092,15 +1092,17 @@
pte_efuse = readl_relaxed(base);
redundant_sel = (pte_efuse >> 24) & 0x7;
+ bin->pvs_rev = (pte_efuse >> 4) & 0x3;
bin->speed = pte_efuse & 0x7;
- bin->pvs = (pte_efuse >> 6) & 0x7;
+ /* PVS number is in bits 31, 8, 7, 6 */
+ bin->pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
switch (redundant_sel) {
case 1:
- bin->speed = (pte_efuse >> 27) & 0x7;
+ bin->speed = (pte_efuse >> 27) & 0xF;
break;
case 2:
- bin->pvs = (pte_efuse >> 27) & 0x7;
+ bin->pvs = (pte_efuse >> 27) & 0xF;
break;
}
bin->speed_valid = true;
@@ -1136,13 +1138,15 @@
if (bin.pvs_valid) {
drv.pvs_bin = bin.pvs;
dev_info(drv.dev, "ACPU PVS: %d\n", drv.pvs_bin);
+ drv.pvs_rev = bin.pvs_rev;
+ dev_info(drv.dev, "ACPU PVS REVISION: %d\n", drv.pvs_rev);
} else {
drv.pvs_bin = 0;
dev_warn(drv.dev, "ACPU PVS: Defaulting to %d\n",
drv.pvs_bin);
}
- return ¶ms->pvs_tables[drv.speed_bin][drv.pvs_bin];
+ return ¶ms->pvs_tables[drv.pvs_rev][drv.speed_bin][drv.pvs_bin];
}
static void __init drv_data_init(struct device *dev,
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
index f02af98..4eff45d 100644
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ b/arch/arm/mach-msm/acpuclock-krait.h
@@ -50,10 +50,15 @@
PVS_NOMINAL = 1,
PVS_FAST = 3,
PVS_FASTER = 4,
- NUM_PVS = 8
+ NUM_PVS = 16
};
/**
+ * The maximum number of PVS revisions.
+ */
+#define NUM_PVS_REVS (4)
+
+/**
* The maximum number of speed bins.
*/
#define NUM_SPEED_BINS (16)
@@ -236,12 +241,14 @@
* @pvs_valid: @pvs field is valid
* @speed: Speed bin ID
* @pvs: PVS bin ID
+ * @pvs_rev: PVS revision ID
*/
struct bin_info {
bool speed_valid;
bool pvs_valid;
int speed;
int pvs;
+ int pvs_rev;
};
/**
@@ -273,7 +280,7 @@
struct scalable *scalable;
size_t scalable_size;
struct hfpll_data *hfpll_data;
- struct pvs_table (*pvs_tables)[NUM_PVS];
+ struct pvs_table (*pvs_tables)[NUM_SPEED_BINS][NUM_PVS];
struct l2_level *l2_freq_tbl;
size_t l2_freq_tbl_size;
phys_addr_t pte_efuse_phys;
@@ -293,6 +300,7 @@
* @boost_uv: Voltage boost amount
* @speed_bin: Speed bin ID.
* @pvs_bin: PVS bin ID.
+ * @pvs_bin: PVS revision ID.
* @dev: Device.
*/
struct drv_data {
@@ -305,6 +313,7 @@
int boost_uv;
int speed_bin;
int pvs_bin;
+ int pvs_rev;
struct device *dev;
};
diff --git a/arch/arm/mach-msm/board-8226-gpiomux.c b/arch/arm/mach-msm/board-8226-gpiomux.c
index 5dd9bab..4dcbc3a 100644
--- a/arch/arm/mach-msm/board-8226-gpiomux.c
+++ b/arch/arm/mach-msm/board-8226-gpiomux.c
@@ -18,6 +18,38 @@
#include <mach/gpiomux.h>
#include <mach/socinfo.h>
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+static struct gpiomux_setting hsic_sus_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ .dir = GPIOMUX_OUT_LOW,
+};
+
+static struct gpiomux_setting hsic_act_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_16MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct msm_gpiomux_config msm_hsic_configs[] = {
+ {
+ .gpio = 115, /* HSIC_STROBE */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+ {
+ .gpio = 116, /* HSIC_DATA */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+};
+#endif
+
#define KS8851_IRQ_GPIO 115
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
@@ -824,4 +856,17 @@
ARRAY_SIZE(usb_otg_sw_configs));
msm_gpiomux_sdc3_install();
+
+ /*
+ * HSIC STROBE gpio is also used by the ethernet. Install HSIC
+ * gpio mux config only when HSIC is enabled. HSIC config will
+ * be disabled when ethernet config is enabled.
+ */
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ if (machine_is_msm8926()) {
+ msm_hsic_configs[0].gpio = 119; /* STROBE */
+ msm_hsic_configs[1].gpio = 120; /* DATA */
+ }
+ msm_gpiomux_install(msm_hsic_configs, ARRAY_SIZE(msm_hsic_configs));
+#endif
}
diff --git a/arch/arm/mach-msm/clock-8610.c b/arch/arm/mach-msm/clock-8610.c
index 33dcd9f..95d2f70 100644
--- a/arch/arm/mach-msm/clock-8610.c
+++ b/arch/arm/mach-msm/clock-8610.c
@@ -3022,12 +3022,14 @@
/* MM sensor clocks */
CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6-006f"),
+ CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6-0034"),
CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6-007d"),
CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6-006d"),
CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "6-0078"),
CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6-0020"),
CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6-006a"),
CLK_LOOKUP("cam_clk", mclk0_clk.c, "6-006f"),
+ CLK_LOOKUP("cam_clk", mclk0_clk.c, "6-0034"),
CLK_LOOKUP("cam_clk", mclk0_clk.c, "6-007d"),
CLK_LOOKUP("cam_clk", mclk0_clk.c, "6-006d"),
CLK_LOOKUP("cam_clk", mclk1_clk.c, "6-0078"),
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 0e3310c..9ae3340 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -5208,26 +5208,56 @@
/* ISPIF clocks */
CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
- CLK_LOOKUP("vfe0_clk_src", vfe0_clk_src.c, "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("vfe0_clk_src", vfe0_clk_src.c,
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("camss_vfe_vfe0_clk", camss_vfe_vfe0_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("camss_csi_vfe0_clk", camss_csi_vfe0_clk.c,
- "fda0a000.qcom,ispif"),
- CLK_LOOKUP("vfe1_clk_src", vfe1_clk_src.c, "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("vfe1_clk_src", vfe1_clk_src.c,
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("camss_vfe_vfe1_clk", camss_vfe_vfe1_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("camss_csi_vfe1_clk", camss_csi_vfe1_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
+
CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("csi0_clk", camss_csi0_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
+
+ CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_clk", camss_csi1_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c,
+ "fda0a000.qcom,ispif"),
+
+ CLK_LOOKUP("csi2_src_clk", csi2_clk_src.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi2_clk", camss_csi2_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi2_pix_clk", camss_csi2pix_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi2_rdi_clk", camss_csi2rdi_clk.c,
+ "fda0a000.qcom,ispif"),
+
+ CLK_LOOKUP("csi3_src_clk", csi3_clk_src.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi3_clk", camss_csi3_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi3_pix_clk", camss_csi3pix_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi3_rdi_clk", camss_csi3rdi_clk.c,
+ "fda0a000.qcom,ispif"),
/*VFE clocks*/
CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
diff --git a/arch/arm/mach-msm/include/mach/gpiomux.h b/arch/arm/mach-msm/include/mach/gpiomux.h
index bd1a4a2..122ffaa 100644
--- a/arch/arm/mach-msm/include/mach/gpiomux.h
+++ b/arch/arm/mach-msm/include/mach/gpiomux.h
@@ -114,6 +114,8 @@
TLMM_ETM_MODE_REG = 0x2014,
TLMM_SDC2_HDRV_PULL_CTL = 0x2048,
TLMM_SPARE_REG = 0x2024,
+ TLMM_CDC_HDRV_CTL = 0x2054,
+ TLMM_CDC_HDRV_PULL_CTL = 0x2058,
};
void msm_tlmm_misc_reg_write(enum msm_tlmm_misc_reg misc_reg, int val);
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8084.h b/arch/arm/mach-msm/include/mach/msm_iomap-8084.h
index 43f1de0..fe68524 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8084.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8084.h
@@ -31,6 +31,9 @@
#define APQ8084_TLMM_PHYS 0xFD510000
#define APQ8084_TLMM_SIZE SZ_16K
+#define APQ8084_QGIC_CPU_PHYS 0xF9002000
+#define APQ8084_QGIC_CPU_SIZE SZ_4K
+
#ifdef CONFIG_DEBUG_APQ8084_UART
#define MSM_DEBUG_UART_BASE IOMEM(0xFA71E000)
#define MSM_DEBUG_UART_PHYS 0xF991E000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8092.h b/arch/arm/mach-msm/include/mach/msm_iomap-8092.h
index f460a4e..2ae36a5 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8092.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8092.h
@@ -28,6 +28,9 @@
#define MPQ8092_QGIC_DIST_PHYS 0xF9000000
#define MPQ8092_QGIC_DIST_SIZE SZ_4K
+#define MPQ8092_QGIC_CPU_PHYS 0xF9002000
+#define MPQ8092_QGIC_CPU_SIZE SZ_4K
+
#define MPQ8092_TLMM_PHYS 0xFD510000
#define MPQ8092_TLMM_SIZE SZ_16K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8226.h b/arch/arm/mach-msm/include/mach/msm_iomap-8226.h
index 327c1ea..adf66ff 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8226.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8226.h
@@ -28,6 +28,9 @@
#define MSM8226_QGIC_DIST_PHYS 0xF9000000
#define MSM8226_QGIC_DIST_SIZE SZ_4K
+#define MSM8226_QGIC_CPU_PHYS 0xF9002000
+#define MSM8226_QGIC_CPU_SIZE SZ_4K
+
#define MSM8226_APCS_GCC_PHYS 0xF9011000
#define MSM8226_APCS_GCC_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8610.h b/arch/arm/mach-msm/include/mach/msm_iomap-8610.h
index 18e448d..4431d71 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8610.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8610.h
@@ -27,6 +27,9 @@
#define MSM8610_QGIC_DIST_PHYS 0xF9000000
#define MSM8610_QGIC_DIST_SIZE SZ_4K
+#define MSM8610_QGIC_CPU_PHYS 0xF9002000
+#define MSM8610_QGIC_CPU_SIZE SZ_4K
+
#define MSM8610_APCS_GCC_PHYS 0xF9011000
#define MSM8610_APCS_GCC_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8974.h b/arch/arm/mach-msm/include/mach/msm_iomap-8974.h
index ec3c210..4072f2d 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8974.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8974.h
@@ -28,6 +28,9 @@
#define MSM8974_QGIC_DIST_PHYS 0xF9000000
#define MSM8974_QGIC_DIST_SIZE SZ_4K
+#define MSM8974_QGIC_CPU_PHYS 0xF9002000
+#define MSM8974_QGIC_CPU_SIZE SZ_4K
+
#define MSM8974_TLMM_PHYS 0xFD510000
#define MSM8974_TLMM_SIZE SZ_16K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-9625.h b/arch/arm/mach-msm/include/mach/msm_iomap-9625.h
index 31b19b3..ee5a413 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-9625.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-9625.h
@@ -28,6 +28,9 @@
#define MSM9625_QGIC_DIST_PHYS 0xF9000000
#define MSM9625_QGIC_DIST_SIZE SZ_4K
+#define MSM9625_QGIC_CPU_PHYS 0xF9002000
+#define MSM9625_QGIC_CPU_SIZE SZ_4K
+
#define MSM9625_TMR_PHYS 0xF9021000
#define MSM9625_TMR_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index b06189f..6b3d590 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -50,6 +50,7 @@
#define machine_is_msm8610() of_machine_is_compatible("qcom,msm8610")
#define machine_is_msm8226() of_machine_is_compatible("qcom,msm8226")
#define machine_is_apq8074() of_machine_is_compatible("qcom,apq8074")
+#define machine_is_msm8926() of_machine_is_compatible("qcom,msm8926")
#define early_machine_is_msm8610() \
of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8610")
@@ -80,6 +81,7 @@
#define machine_is_msm8610() 0
#define machine_is_msm8226() 0
#define machine_is_apq8074() 0
+#define machine_is_msm8926() 0
#define early_machine_is_msm8610() 0
#define early_machine_is_mpq8092() 0
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index f736b30..d1c8500 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -299,6 +299,7 @@
#ifdef CONFIG_ARCH_MSM8974
static struct map_desc msm_8974_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, MSM8974),
+ MSM_CHIP_DEVICE(QGIC_CPU, MSM8974),
MSM_CHIP_DEVICE(TLMM, MSM8974),
MSM_CHIP_DEVICE(MPM2_PSHOLD, MSM8974),
{
@@ -322,6 +323,7 @@
#ifdef CONFIG_ARCH_APQ8084
static struct map_desc msm_8084_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, APQ8084),
+ MSM_CHIP_DEVICE(QGIC_CPU, APQ8084),
MSM_CHIP_DEVICE(TLMM, APQ8084),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
@@ -504,6 +506,7 @@
#ifdef CONFIG_ARCH_MSM9625
static struct map_desc msm9625_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, MSM9625),
+ MSM_CHIP_DEVICE(QGIC_CPU, MSM9625),
MSM_CHIP_DEVICE(TLMM, MSM9625),
MSM_CHIP_DEVICE(MPM2_PSHOLD, MSM9625),
MSM_CHIP_DEVICE(TMR, MSM9625),
@@ -547,6 +550,7 @@
#ifdef CONFIG_ARCH_MPQ8092
static struct map_desc mpq8092_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, MPQ8092),
+ MSM_CHIP_DEVICE(QGIC_CPU, MPQ8092),
MSM_CHIP_DEVICE(TLMM, MPQ8092),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
@@ -569,6 +573,7 @@
#ifdef CONFIG_ARCH_MSM8226
static struct map_desc msm_8226_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, MSM8226),
+ MSM_CHIP_DEVICE(QGIC_CPU, MSM8226),
MSM_CHIP_DEVICE(APCS_GCC, MSM8226),
MSM_CHIP_DEVICE(TLMM, MSM8226),
MSM_CHIP_DEVICE(MPM2_PSHOLD, MSM8226),
@@ -594,6 +599,7 @@
#ifdef CONFIG_ARCH_MSM8610
static struct map_desc msm8610_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, MSM8610),
+ MSM_CHIP_DEVICE(QGIC_CPU, MSM8610),
MSM_CHIP_DEVICE(APCS_GCC, MSM8610),
MSM_CHIP_DEVICE(TLMM, MSM8610),
MSM_CHIP_DEVICE(MPM2_PSHOLD, MSM8610),
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index da5e67a..00b0b3b 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -481,6 +481,10 @@
bool collapsed = 0;
int ret;
bool save_cpu_regs = !cpu || from_idle;
+ unsigned int saved_gic_cpu_ctrl;
+
+ saved_gic_cpu_ctrl = readl_relaxed(MSM_QGIC_CPU_BASE + GIC_CPU_CTRL);
+ mb();
if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
pr_info("CPU%u: %s: notify_rpm %d\n",
@@ -503,6 +507,9 @@
if (from_idle && msm_pm_pc_reset_timer)
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
+#ifdef CONFIG_VFP
+ vfp_pm_suspend();
+#endif
collapsed = save_cpu_regs ? msm_pm_collapse() : msm_pm_pc_hotplug();
if (from_idle && msm_pm_pc_reset_timer)
@@ -511,7 +518,14 @@
msm_pm_boot_config_after_pc(cpu);
if (collapsed) {
+#ifdef CONFIG_VFP
+ vfp_pm_resume();
+#endif
cpu_init();
+ writel(0xF0, MSM_QGIC_CPU_BASE + GIC_CPU_PRIMASK);
+ writel_relaxed(saved_gic_cpu_ctrl,
+ MSM_QGIC_CPU_BASE + GIC_CPU_CTRL);
+ mb();
local_fiq_enable();
}
diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c
index c726694..7409ccb 100644
--- a/drivers/crypto/msm/qcedev.c
+++ b/drivers/crypto/msm/qcedev.c
@@ -79,6 +79,7 @@
uint8_t first_blk;
uint8_t last_blk;
uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
+ bool init_done;
};
struct qcedev_async_req {
@@ -744,6 +745,7 @@
sha_ctxt->diglen = SHA256_DIGEST_SIZE;
}
}
+ sha_ctxt->init_done = true;
return 0;
}
@@ -878,6 +880,11 @@
int num_entries = 0;
uint32_t total = 0;
+ if (handle->sha_ctxt.init_done == false) {
+ pr_err("%s Init was not called\n", __func__);
+ return -EINVAL;
+ }
+
/* verify address src(s) */
for (i = 0; i < qcedev_areq->sha_op_req.entries; i++)
if (!access_ok(VERIFY_READ,
@@ -985,10 +992,19 @@
int err = 0;
struct scatterlist sg_src;
uint32_t total;
-
uint8_t *k_buf_src = NULL;
uint8_t *k_align_src = NULL;
+ if (handle->sha_ctxt.init_done == false) {
+ pr_err("%s Init was not called\n", __func__);
+ return -EINVAL;
+ }
+
+ if (handle->sha_ctxt.trailing_buf_len == 0) {
+ pr_err("%s Incorrect trailng buffer %d\n", __func__,
+ handle->sha_ctxt.trailing_buf_len);
+ return -EINVAL;
+ }
handle->sha_ctxt.last_blk = 1;
total = handle->sha_ctxt.trailing_buf_len;
@@ -1019,6 +1035,7 @@
handle->sha_ctxt.auth_data[0] = 0;
handle->sha_ctxt.auth_data[1] = 0;
handle->sha_ctxt.trailing_buf_len = 0;
+ handle->sha_ctxt.init_done = false;
memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
kfree(k_buf_src);
@@ -1413,12 +1430,37 @@
return -EFAULT;
/* Verify Destination Address's */
- if (areq->cipher_op_req.in_place_op != 1)
- for (i = 0; i < areq->cipher_op_req.entries; i++)
- if (!access_ok(VERIFY_READ,
- (void __user *)areq->cipher_op_req.vbuf.dst[i].vaddr,
- areq->cipher_op_req.vbuf.dst[i].len))
- return -EFAULT;
+ if (creq->in_place_op != 1) {
+ for (i = 0, total = 0; i < QCEDEV_MAX_BUFFERS; i++) {
+ if ((areq->cipher_op_req.vbuf.dst[i].vaddr != 0) &&
+ (total < creq->data_len)) {
+ if (!access_ok(VERIFY_WRITE,
+ (void __user *)creq->vbuf.dst[i].vaddr,
+ creq->vbuf.dst[i].len)) {
+ pr_err("%s:DST WR_VERIFY err %d=0x%x\n",
+ __func__, i,
+ (u32)creq->vbuf.dst[i].vaddr);
+ return -EFAULT;
+ }
+ total += creq->vbuf.dst[i].len;
+ }
+ }
+ } else {
+ for (i = 0, total = 0; i < creq->entries; i++) {
+ if (total < creq->data_len) {
+ if (!access_ok(VERIFY_WRITE,
+ (void __user *)creq->vbuf.src[i].vaddr,
+ creq->vbuf.src[i].len)) {
+ pr_err("%s:SRC WR_VERIFY err %d=0x%x\n",
+ __func__, i,
+ (u32)creq->vbuf.src[i].vaddr);
+ return -EFAULT;
+ }
+ total += creq->vbuf.src[i].len;
+ }
+ }
+ }
+ total = 0;
if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
byteoffset = areq->cipher_op_req.byteoffset;
@@ -1680,6 +1722,9 @@
static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
struct qcedev_control *podev)
{
+ uint32_t total = 0;
+ uint32_t i;
+
if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
(!podev->ce_support.cmac)) {
pr_err("%s: CMAC not supported\n", __func__);
@@ -1717,6 +1762,14 @@
}
}
+ /* Check for sum of all src length is equal to data_len */
+ for (i = 0, total = 0; i < req->entries; i++)
+ total += req->data[i].len;
+ if (total != req->data_len) {
+ pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
+ __func__, total, req->data_len);
+ goto sha_error;
+ }
return 0;
sha_error:
return -EINVAL;
@@ -1805,6 +1858,7 @@
sizeof(struct qcedev_sha_op_req)))
return -EFAULT;
}
+ handle->sha_ctxt.init_done = true;
break;
case QCEDEV_IOCTL_GET_CMAC_REQ:
if (!podev->ce_support.cmac)
@@ -1829,6 +1883,10 @@
if (err)
return err;
} else {
+ if (handle->sha_ctxt.init_done == false) {
+ pr_err("%s Init was not called\n", __func__);
+ return -EINVAL;
+ }
err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
if (err)
return err;
@@ -1845,6 +1903,10 @@
case QCEDEV_IOCTL_SHA_FINAL_REQ:
+ if (handle->sha_ctxt.init_done == false) {
+ pr_err("%s Init was not called\n", __func__);
+ return -EINVAL;
+ }
if (!access_ok(VERIFY_WRITE, (void __user *)arg,
sizeof(struct qcedev_sha_op_req)))
return -EFAULT;
@@ -1866,6 +1928,7 @@
if (__copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
sizeof(struct qcedev_sha_op_req)))
return -EFAULT;
+ handle->sha_ctxt.init_done = false;
break;
case QCEDEV_IOCTL_GET_SHA_REQ:
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index cdf711c..b393b21 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -632,11 +632,11 @@
kgsl_mmu_unmap(pagetable, &device->memstore);
- kgsl_mmu_unmap(pagetable, &adreno_dev->profile.shared_buffer);
-
kgsl_mmu_unmap(pagetable, &adreno_dev->pwron_fixup);
kgsl_mmu_unmap(pagetable, &device->mmu.setstate_memory);
+
+ kgsl_mmu_unmap(pagetable, &adreno_dev->profile.shared_buffer);
}
static int adreno_setup_pt(struct kgsl_device *device,
@@ -648,6 +648,12 @@
result = kgsl_mmu_map_global(pagetable, &rb->buffer_desc);
+ /*
+ * ALERT: Order of these mapping is important to
+ * Keep the most used entries like memptrs, memstore
+ * and mmu setstate memory by TLB prefetcher.
+ */
+
if (!result)
result = kgsl_mmu_map_global(pagetable, &rb->memptrs_desc);
@@ -656,17 +662,16 @@
if (!result)
result = kgsl_mmu_map_global(pagetable,
- &adreno_dev->profile.shared_buffer);
-
- if (!result)
- result = kgsl_mmu_map_global(pagetable,
&adreno_dev->pwron_fixup);
-
if (!result)
result = kgsl_mmu_map_global(pagetable,
&device->mmu.setstate_memory);
+ if (!result)
+ result = kgsl_mmu_map_global(pagetable,
+ &adreno_dev->profile.shared_buffer);
+
if (result) {
/* On error clean up what we have wrought */
adreno_cleanup_pt(device, pagetable);
@@ -678,8 +683,8 @@
* For the IOMMU, this will be used to restrict access to the
* mapped registers.
*/
- device->mh.mpu_range = device->mmu.setstate_memory.gpuaddr +
- device->mmu.setstate_memory.size;
+ device->mh.mpu_range = adreno_dev->profile.shared_buffer.gpuaddr +
+ adreno_dev->profile.shared_buffer.size;
return 0;
}
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 6507852..a837574 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -63,7 +63,6 @@
#define ADRENO_DEFAULT_PWRSCALE_POLICY NULL
#endif
-void adreno_debugfs_init(struct kgsl_device *device);
#define ADRENO_ISTORE_START 0x5000 /* Istore offset */
@@ -749,4 +748,11 @@
return ADRENO_REG_REGISTER_MAX;
return adreno_dev->gpudev->reg_offsets->offsets[offset_name];
}
+
+#ifdef CONFIG_DEBUG_FS
+void adreno_debugfs_init(struct kgsl_device *device);
+#else
+static inline void adreno_debugfs_init(struct kgsl_device *device) { }
+#endif
+
#endif /*__ADRENO_H */
diff --git a/drivers/gpu/msm/adreno_debugfs.c b/drivers/gpu/msm/adreno_debugfs.c
index fc98d86..a7d1b7f 100644
--- a/drivers/gpu/msm/adreno_debugfs.c
+++ b/drivers/gpu/msm/adreno_debugfs.c
@@ -23,8 +23,6 @@
#include "a2xx_reg.h"
-unsigned int kgsl_cff_dump_enable;
-
DEFINE_SIMPLE_ATTRIBUTE(kgsl_cff_dump_enable_fops, kgsl_cff_dump_enable_get,
kgsl_cff_dump_enable_set, "%llu\n");
diff --git a/drivers/gpu/msm/adreno_profile.h b/drivers/gpu/msm/adreno_profile.h
index d91b09b..7e1ccb2 100644
--- a/drivers/gpu/msm/adreno_profile.h
+++ b/drivers/gpu/msm/adreno_profile.h
@@ -61,6 +61,7 @@
#define ADRENO_PROFILE_LOG_BUF_SIZE_DWORDS (ADRENO_PROFILE_LOG_BUF_SIZE / \
sizeof(unsigned int))
+#ifdef CONFIG_DEBUG_FS
void adreno_profile_init(struct kgsl_device *device);
void adreno_profile_close(struct kgsl_device *device);
int adreno_profile_process_results(struct kgsl_device *device);
@@ -70,6 +71,22 @@
void adreno_profile_postib_processing(struct kgsl_device *device,
unsigned int *cmd_flags, unsigned int **rbptr,
unsigned int *cmds_gpu);
+#else
+static inline void adreno_profile_init(struct kgsl_device *device) { }
+static inline void adreno_profile_close(struct kgsl_device *device) { }
+static inline int adreno_profile_process_results(struct kgsl_device *device)
+{
+ return 0;
+}
+
+static inline void adreno_profile_preib_processing(struct kgsl_device *device,
+ unsigned int context_id, unsigned int *cmd_flags,
+ unsigned int **rbptr, unsigned int *cmds_gpu) { }
+
+static inline void adreno_profile_postib_processing(struct kgsl_device *device,
+ unsigned int *cmd_flags, unsigned int **rbptr,
+ unsigned int *cmds_gpu) { }
+#endif
static inline bool adreno_profile_enabled(struct adreno_profile *profile)
{
diff --git a/drivers/gpu/msm/kgsl_log.h b/drivers/gpu/msm/kgsl_log.h
index a7832e4..94649bd 100644
--- a/drivers/gpu/msm/kgsl_log.h
+++ b/drivers/gpu/msm/kgsl_log.h
@@ -13,8 +13,6 @@
#ifndef __KGSL_LOG_H
#define __KGSL_LOG_H
-extern unsigned int kgsl_cff_dump_enable;
-
#define KGSL_LOG_INFO(dev, lvl, fmt, args...) \
do { \
if ((lvl) >= 6) \
diff --git a/drivers/input/touchscreen/ft5x06_ts.c b/drivers/input/touchscreen/ft5x06_ts.c
index 2f9ea10..367a987 100644
--- a/drivers/input/touchscreen/ft5x06_ts.c
+++ b/drivers/input/touchscreen/ft5x06_ts.c
@@ -1247,6 +1247,9 @@
pdata->fw_vkey_support = of_property_read_bool(np,
"focaltech,fw-vkey-support");
+ pdata->ignore_id_check = of_property_read_bool(np,
+ "focaltech,ignore-id-check");
+
rc = of_property_read_u32(np, "focaltech,family-id", &temp_val);
if (!rc)
pdata->family_id = temp_val;
@@ -1447,7 +1450,7 @@
dev_info(&client->dev, "Device ID = 0x%x\n", reg_value);
- if (pdata->family_id != reg_value) {
+ if ((pdata->family_id != reg_value) && (!pdata->ignore_id_check)) {
dev_err(&client->dev, "%s:Unsupported controller\n", __func__);
goto free_reset_gpio;
}
diff --git a/drivers/media/platform/msm/camera_v2/Kconfig b/drivers/media/platform/msm/camera_v2/Kconfig
index bc7d135..262fb38 100644
--- a/drivers/media/platform/msm/camera_v2/Kconfig
+++ b/drivers/media/platform/msm/camera_v2/Kconfig
@@ -119,6 +119,15 @@
snapshot config = 4208 x 3120 at 24 fps,
Video HDR support.
+config IMX134
+ bool "Sensor IMX134 (BAYER 8M)"
+ depends on MSMB_CAMERA
+ ---help---
+ Sony 8 MP Bayer Sensor with auto focus, uses
+ 4 mipi lanes full resolution @30fps and
+ HFR @60fps and @120fps
+ Video HDR support.
+
config OV2720
bool "Sensor OV2720 (BAYER 2M)"
depends on MSMB_CAMERA
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
index a6972e4..a8da26d 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
@@ -24,7 +24,8 @@
#define VFE32_BURST_LEN 2
#define VFE32_UB_SIZE 1024
-#define VFE32_EQUAL_SLICE_UB 198
+#define VFE32_EQUAL_SLICE_UB 194
+#define VFE32_AXI_SLICE_UB 792
#define VFE32_WM_BASE(idx) (0x4C + 0x18 * idx)
#define VFE32_RDI_BASE(idx) (idx ? 0x734 + 0x4 * (idx - 1) : 0x06FC)
#define VFE32_XBAR_BASE(idx) (0x40 + 0x4 * (idx / 4))
@@ -319,6 +320,7 @@
uint32_t irq_status0, uint32_t irq_status1,
struct msm_isp_timestamp *ts)
{
+ uint32_t rdi_status;
if (!(irq_status0 & 0x20) && !(irq_status1 & 0x1C000000))
return;
@@ -331,6 +333,18 @@
if (irq_status1 & BIT(28))
msm_isp_sof_notify(vfe_dev, VFE_RAW_2, ts);
+ if (vfe_dev->axi_data.stream_update) {
+ rdi_status = msm_camera_io_r(vfe_dev->vfe_base +
+ VFE32_XBAR_BASE(0));
+ rdi_status |= msm_camera_io_r(vfe_dev->vfe_base +
+ VFE32_XBAR_BASE(4));
+
+ if (((rdi_status & BIT(7)) || (rdi_status & BIT(7)) ||
+ (rdi_status & BIT(7)) || (rdi_status & BIT(7))) &&
+ (!(irq_status0 & 0x20)))
+ return;
+ }
+
if (vfe_dev->axi_data.stream_update)
msm_isp_axi_stream_update(vfe_dev);
if (atomic_read(&vfe_dev->stats_data.stats_update))
@@ -759,11 +773,21 @@
{
int i;
uint32_t ub_offset = 0;
+ uint32_t final_ub_slice_size;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
- msm_camera_io_w(ub_offset << 16 | (VFE32_EQUAL_SLICE_UB - 1),
- vfe_dev->vfe_base + VFE32_WM_BASE(i) + 0xC);
- ub_offset += VFE32_EQUAL_SLICE_UB;
+ if (ub_offset + VFE32_EQUAL_SLICE_UB > VFE32_AXI_SLICE_UB) {
+ final_ub_slice_size = VFE32_AXI_SLICE_UB - ub_offset;
+ msm_camera_io_w(ub_offset << 16 |
+ (final_ub_slice_size - 1), vfe_dev->vfe_base +
+ VFE32_WM_BASE(i) + 0xC);
+ ub_offset += final_ub_slice_size;
+ } else {
+ msm_camera_io_w(ub_offset << 16 |
+ (VFE32_EQUAL_SLICE_UB - 1), vfe_dev->vfe_base +
+ VFE32_WM_BASE(i) + 0xC);
+ ub_offset += VFE32_EQUAL_SLICE_UB;
+ }
}
}
@@ -1023,7 +1047,7 @@
}
struct msm_vfe_axi_hardware_info msm_vfe32_axi_hw_info = {
- .num_wm = 4,
+ .num_wm = 5,
.num_comp_mask = 3,
.num_rdi = 3,
.num_rdi_master = 3,
diff --git a/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c b/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c
index 2b963a4..89016ec 100644
--- a/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c
+++ b/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c
@@ -72,6 +72,18 @@
{"csi0_clk", NO_SET_RATE},
{"csi0_pix_clk", NO_SET_RATE},
{"csi0_rdi_clk", NO_SET_RATE},
+ {"csi1_src_clk", INIT_RATE},
+ {"csi1_clk", NO_SET_RATE},
+ {"csi1_pix_clk", NO_SET_RATE},
+ {"csi1_rdi_clk", NO_SET_RATE},
+ {"csi2_src_clk", INIT_RATE},
+ {"csi2_clk", NO_SET_RATE},
+ {"csi2_pix_clk", NO_SET_RATE},
+ {"csi2_rdi_clk", NO_SET_RATE},
+ {"csi3_src_clk", INIT_RATE},
+ {"csi3_clk", NO_SET_RATE},
+ {"csi3_pix_clk", NO_SET_RATE},
+ {"csi3_rdi_clk", NO_SET_RATE},
{"vfe0_clk_src", INIT_RATE},
{"camss_vfe_vfe0_clk", NO_SET_RATE},
{"camss_csi_vfe0_clk", NO_SET_RATE},
@@ -110,6 +122,9 @@
CDBG("%s: VFE0 done\n", __func__);
if (timeout <= 0) {
pr_err("%s: VFE0 reset wait timeout\n", __func__);
+ msm_cam_clk_enable(&ispif->pdev->dev,
+ ispif_8974_reset_clk_info, reset_clk,
+ ARRAY_SIZE(ispif_8974_reset_clk_info), 0);
return -ETIMEDOUT;
}
@@ -120,6 +135,9 @@
CDBG("%s: VFE1 done\n", __func__);
if (timeout <= 0) {
pr_err("%s: VFE1 reset wait timeout\n", __func__);
+ msm_cam_clk_enable(&ispif->pdev->dev,
+ ispif_8974_reset_clk_info, reset_clk,
+ ARRAY_SIZE(ispif_8974_reset_clk_info), 0);
return -ETIMEDOUT;
}
}
diff --git a/drivers/media/platform/msm/camera_v2/sensor/Makefile b/drivers/media/platform/msm/camera_v2/sensor/Makefile
index bbfbbdf..e011793 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/Makefile
+++ b/drivers/media/platform/msm/camera_v2/sensor/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_MSM_CAMERA_SENSOR) += msm_sensor.o
obj-$(CONFIG_S5K3L1YX) += s5k3l1yx.o
obj-$(CONFIG_IMX135) += imx135.o
+obj-$(CONFIG_IMX134) += imx134.o
obj-$(CONFIG_OV8825) += ov8825.o
obj-$(CONFIG_s5k4e1) += s5k4e1.o
obj-$(CONFIG_OV12830) += ov12830.o
diff --git a/drivers/media/platform/msm/camera_v2/sensor/imx134.c b/drivers/media/platform/msm/camera_v2/sensor/imx134.c
new file mode 100644
index 0000000..17a5088
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v2/sensor/imx134.c
@@ -0,0 +1,174 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include "msm_sensor.h"
+#define IMX134_SENSOR_NAME "imx134"
+DEFINE_MSM_MUTEX(imx134_mut);
+
+static struct msm_sensor_ctrl_t imx134_s_ctrl;
+
+static struct msm_sensor_power_setting imx134_power_setting[] = {
+ {
+ .seq_type = SENSOR_VREG,
+ .seq_val = CAM_VDIG,
+ .config_val = 0,
+ .delay = 0,
+ },
+ {
+ .seq_type = SENSOR_VREG,
+ .seq_val = CAM_VANA,
+ .config_val = 0,
+ .delay = 0,
+ },
+ {
+ .seq_type = SENSOR_VREG,
+ .seq_val = CAM_VIO,
+ .config_val = 0,
+ .delay = 0,
+ },
+ {
+ .seq_type = SENSOR_VREG,
+ .seq_val = CAM_VAF,
+ .config_val = 0,
+ .delay = 0,
+ },
+ {
+ .seq_type = SENSOR_GPIO,
+ .seq_val = SENSOR_GPIO_RESET,
+ .config_val = GPIO_OUT_LOW,
+ .delay = 1,
+ },
+ {
+ .seq_type = SENSOR_GPIO,
+ .seq_val = SENSOR_GPIO_RESET,
+ .config_val = GPIO_OUT_HIGH,
+ .delay = 30,
+ },
+ {
+ .seq_type = SENSOR_GPIO,
+ .seq_val = SENSOR_GPIO_STANDBY,
+ .config_val = GPIO_OUT_LOW,
+ .delay = 1,
+ },
+ {
+ .seq_type = SENSOR_GPIO,
+ .seq_val = SENSOR_GPIO_STANDBY,
+ .config_val = GPIO_OUT_HIGH,
+ .delay = 30,
+ },
+ {
+ .seq_type = SENSOR_CLK,
+ .seq_val = SENSOR_CAM_MCLK,
+ .config_val = 0,
+ .delay = 1,
+ },
+ {
+ .seq_type = SENSOR_I2C_MUX,
+ .seq_val = 0,
+ .config_val = 0,
+ .delay = 0,
+ },
+};
+
+static struct v4l2_subdev_info imx134_subdev_info[] = {
+ {
+ .code = V4L2_MBUS_FMT_SBGGR10_1X10,
+ .colorspace = V4L2_COLORSPACE_JPEG,
+ .fmt = 1,
+ .order = 0,
+ },
+};
+
+static const struct i2c_device_id imx134_i2c_id[] = {
+ {IMX134_SENSOR_NAME, (kernel_ulong_t)&imx134_s_ctrl},
+ { }
+};
+
+static int32_t msm_imx134_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ return msm_sensor_i2c_probe(client, id, &imx134_s_ctrl);
+}
+
+static struct i2c_driver imx134_i2c_driver = {
+ .id_table = imx134_i2c_id,
+ .probe = msm_imx134_i2c_probe,
+ .driver = {
+ .name = IMX134_SENSOR_NAME,
+ },
+};
+
+static struct msm_camera_i2c_client imx134_sensor_i2c_client = {
+ .addr_type = MSM_CAMERA_I2C_WORD_ADDR,
+};
+
+static const struct of_device_id imx134_dt_match[] = {
+ {.compatible = "sne,imx134", .data = &imx134_s_ctrl},
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, imx134_dt_match);
+
+static struct platform_driver imx134_platform_driver = {
+ .driver = {
+ .name = "sne,imx134",
+ .owner = THIS_MODULE,
+ .of_match_table = imx134_dt_match,
+ },
+};
+
+static int32_t imx134_platform_probe(struct platform_device *pdev)
+{
+ int32_t rc = 0;
+ const struct of_device_id *match;
+ match = of_match_device(imx134_dt_match, &pdev->dev);
+ rc = msm_sensor_platform_probe(pdev, match->data);
+ return rc;
+}
+
+static int __init imx134_init_module(void)
+{
+ int32_t rc = 0;
+ pr_debug("%s:%d\n", __func__, __LINE__);
+ rc = platform_driver_probe(&imx134_platform_driver,
+ imx134_platform_probe);
+ if (!rc)
+ return rc;
+ pr_debug("%s:%d rc %d\n", __func__, __LINE__, rc);
+ return i2c_add_driver(&imx134_i2c_driver);
+}
+
+static void __exit imx134_exit_module(void)
+{
+ pr_debug("%s:%d\n", __func__, __LINE__);
+ if (imx134_s_ctrl.pdev) {
+ msm_sensor_free_sensor_data(&imx134_s_ctrl);
+ platform_driver_unregister(&imx134_platform_driver);
+ } else {
+ i2c_del_driver(&imx134_i2c_driver);
+ }
+ return;
+}
+
+static struct msm_sensor_ctrl_t imx134_s_ctrl = {
+ .sensor_i2c_client = &imx134_sensor_i2c_client,
+ .power_setting_array.power_setting = imx134_power_setting,
+ .power_setting_array.size = ARRAY_SIZE(imx134_power_setting),
+ .msm_sensor_mutex = &imx134_mut,
+ .sensor_v4l2_subdev_info = imx134_subdev_info,
+ .sensor_v4l2_subdev_info_size = ARRAY_SIZE(imx134_subdev_info),
+};
+
+module_init(imx134_init_module);
+module_exit(imx134_exit_module);
+MODULE_DESCRIPTION("imx134");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/msm/vidc/msm_vdec.c b/drivers/media/platform/msm/vidc/msm_vdec.c
index a3d88c5..08881aa 100644
--- a/drivers/media/platform/msm/vidc/msm_vdec.c
+++ b/drivers/media/platform/msm/vidc/msm_vdec.c
@@ -1037,15 +1037,13 @@
mutex_unlock(&inst->lock);
break;
}
- if (*num_buffers && *num_buffers >=
- bufreq->buffer_count_actual) {
+ *num_buffers = max(*num_buffers, bufreq->buffer_count_min);
+ if (*num_buffers != bufreq->buffer_count_actual) {
property_id = HAL_PARAM_BUFFER_COUNT_ACTUAL;
new_buf_count.buffer_type = HAL_BUFFER_OUTPUT;
new_buf_count.buffer_count_actual = *num_buffers;
rc = call_hfi_op(hdev, session_set_property,
inst->session, property_id, &new_buf_count);
- } else {
- *num_buffers = bufreq->buffer_count_min;
}
mutex_unlock(&inst->lock);
dprintk(VIDC_DBG, "count = %d, size = %d, alignment = %d\n",
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 58703cf..1452908 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -961,6 +961,11 @@
return -EINVAL;
}
+ if (req->cmd_req_len > UINT_MAX - req->resp_len) {
+ pr_err("Integer overflow detected in req_len & rsp_len, exiting now\n");
+ return -EINVAL;
+ }
+
reqd_len_sb_in = req->cmd_req_len + req->resp_len;
if (reqd_len_sb_in > data->client.sb_length) {
pr_debug("Not enough memory to fit cmd_buf and "
@@ -980,7 +985,7 @@
msm_ion_do_cache_op(qseecom.ion_clnt, data->client.ihandle,
data->client.sb_virt,
- (req->cmd_req_len + req->resp_len),
+ reqd_len_sb_in,
ION_IOC_CLEAN_INV_CACHES);
ret = scm_call(SCM_SVC_TZSCHEDULER, 1, (const void *) &send_data_req,
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index a7ce6ae..2c8598b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2687,6 +2687,9 @@
goto vreg_deinit;
}
+ /* Unset HC_MODE_EN bit in HC_MODE register */
+ writel_relaxed(0, (msm_host->core_mem + CORE_HC_MODE));
+
/* Set SW_RST bit in POWER register (Offset 0x0) */
writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
CORE_SW_RST, msm_host->core_mem + CORE_POWER);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f9f3802..0cb0491 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -110,7 +110,7 @@
sdhci_readl(host, SDHCI_INT_ENABLE),
sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
pr_info(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
- sdhci_readw(host, SDHCI_ACMD12_ERR),
+ sdhci_readw(host, SDHCI_AUTO_CMD_ERR),
sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
pr_info(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
sdhci_readl(host, SDHCI_CAPABILITIES),
@@ -118,6 +118,12 @@
pr_info(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
sdhci_readw(host, SDHCI_COMMAND),
sdhci_readl(host, SDHCI_MAX_CURRENT));
+ pr_info(DRIVER_NAME ": Resp 1: 0x%08x | Resp 0: 0x%08x\n",
+ sdhci_readl(host, SDHCI_RESPONSE + 0x4),
+ sdhci_readl(host, SDHCI_RESPONSE));
+ pr_info(DRIVER_NAME ": Resp 3: 0x%08x | Resp 2: 0x%08x\n",
+ sdhci_readl(host, SDHCI_RESPONSE + 0xC),
+ sdhci_readl(host, SDHCI_RESPONSE + 0x8));
pr_info(DRIVER_NAME ": Host ctl2: 0x%08x\n",
sdhci_readw(host, SDHCI_HOST_CONTROL2));
@@ -278,7 +284,8 @@
SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
- SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
+ SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
+ SDHCI_INT_AUTO_CMD_ERR);
if (soft) {
/* force clock reconfiguration */
@@ -2440,6 +2447,7 @@
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
{
+ u16 auto_cmd_status;
BUG_ON(intmask == 0);
if (!host->cmd) {
@@ -2456,6 +2464,18 @@
SDHCI_INT_INDEX))
host->cmd->error = -EILSEQ;
+ if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
+ auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_ERR);
+ if (auto_cmd_status & (SDHCI_AUTO_CMD12_NOT_EXEC |
+ SDHCI_AUTO_CMD_INDEX_ERR |
+ SDHCI_AUTO_CMD_ENDBIT_ERR))
+ host->cmd->error = -EIO;
+ else if (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT_ERR)
+ host->cmd->error = -ETIMEDOUT;
+ else if (auto_cmd_status & SDHCI_AUTO_CMD_CRC_ERR)
+ host->cmd->error = -EILSEQ;
+ }
+
if (host->quirks2 & SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING) {
if ((host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS400) ||
(host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index a3d8442..3db99c4 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -135,21 +135,29 @@
#define SDHCI_INT_DATA_CRC 0x00200000
#define SDHCI_INT_DATA_END_BIT 0x00400000
#define SDHCI_INT_BUS_POWER 0x00800000
-#define SDHCI_INT_ACMD12ERR 0x01000000
+#define SDHCI_INT_AUTO_CMD_ERR 0x01000000
#define SDHCI_INT_ADMA_ERROR 0x02000000
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
- SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
+ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
+ SDHCI_INT_AUTO_CMD_ERR)
+
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
-#define SDHCI_ACMD12_ERR 0x3C
+#define SDHCI_AUTO_CMD_ERR 0x3C
+#define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001
+#define SDHCI_AUTO_CMD_TIMEOUT_ERR 0x0002
+#define SDHCI_AUTO_CMD_CRC_ERR 0x0004
+#define SDHCI_AUTO_CMD_ENDBIT_ERR 0x0008
+#define SDHCI_AUTO_CMD_INDEX_ERR 0x0010
+#define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080
#define SDHCI_HOST_CONTROL2 0x3E
#define SDHCI_CTRL_UHS_MASK 0x0007
diff --git a/drivers/nfc/nfc-nci.c b/drivers/nfc/nfc-nci.c
index 87c7c30..67b057c 100644
--- a/drivers/nfc/nfc-nci.c
+++ b/drivers/nfc/nfc-nci.c
@@ -26,12 +26,15 @@
#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#include "nfc-nci.h"
+#include <mach/gpiomux.h>
struct qca199x_platform_data {
unsigned int irq_gpio;
unsigned int dis_gpio;
unsigned int ven_gpio;
unsigned int reg;
+ const char *clk_src;
+ unsigned int clk_src_gpio;
};
static struct of_device_id msm_match_table[] = {
@@ -397,7 +400,9 @@
gpio_set_value(qca199x_dev->dis_gpio, 1);
usleep(1000);
} else if (arg == 2) {
+ mutex_lock(&qca199x_dev->read_mutex);
r = nfcc_initialise(qca199x_dev->client, 0xE);
+ mutex_unlock(&qca199x_dev->read_mutex);
if (r) {
dev_err(&qca199x_dev->client->dev,
"nfc-nci probe: request nfcc initialise failed\n");
@@ -419,7 +424,6 @@
return r;
}
-
/*
* Inside nfc_ioctl_nfcc_mode
*
@@ -477,6 +481,64 @@
}
/*
+ * Inside nfc_ioctl_nfcc_version
+ *
+ * @brief nfc_ioctl_nfcc_version
+ *
+ *
+ */
+int nfc_ioctl_nfcc_version(struct file *filp, unsigned int cmd,
+ unsigned long arg)
+{
+ int r = 0;
+ unsigned short slave_addr = 0xE;
+ unsigned short curr_addr;
+
+ unsigned char raw_chip_version_addr = 0x00;
+ unsigned char raw_chip_rev_id_addr = 0x9C;
+ unsigned char raw_chip_version = 0xFF;
+
+ struct qca199x_dev *qca199x_dev = filp->private_data;
+ struct qca199x_platform_data *platform_data;
+
+ platform_data = qca199x_dev->client->dev.platform_data;
+
+ if (arg == 0) {
+ curr_addr = qca199x_dev->client->addr;
+ qca199x_dev->client->addr = slave_addr;
+ r = nfc_i2c_write(qca199x_dev->client,
+ &raw_chip_version_addr, 1);
+ if (r < 0)
+ goto invalid_wr;
+ usleep(10);
+ r = i2c_master_recv(qca199x_dev->client, &raw_chip_version, 1);
+ /* Restore original NFCC slave I2C address */
+ qca199x_dev->client->addr = curr_addr;
+ }
+ if (arg == 1) {
+ curr_addr = qca199x_dev->client->addr;
+ qca199x_dev->client->addr = slave_addr;
+ r = nfc_i2c_write(qca199x_dev->client,
+ &raw_chip_rev_id_addr, 1);
+ if (r < 0)
+ goto invalid_wr;
+ usleep(10);
+ r = i2c_master_recv(qca199x_dev->client, &raw_chip_version, 1);
+ /* Restore original NFCC slave I2C address */
+ qca199x_dev->client->addr = curr_addr;
+ }
+
+ return raw_chip_version;
+invalid_wr:
+ raw_chip_version = 0xFF;
+ dev_err(&qca199x_dev->client->dev,
+ "\nNFCC_INVALID_CHIP_VERSION = %d\n", raw_chip_version);
+ return raw_chip_version;
+}
+
+
+
+/*
* Inside nfc_ioctl_kernel_logging
*
* @brief nfc_ioctl_kernel_logging
@@ -522,6 +584,9 @@
case NFCC_MODE:
nfc_ioctl_nfcc_mode(pfile, cmd, arg);
break;
+ case NFCC_VERSION:
+ r = nfc_ioctl_nfcc_version(pfile, cmd, arg);
+ break;
case NFC_KERNEL_LOGGING_MODE:
nfc_ioctl_kernel_logging(arg, pfile);
break;
@@ -690,6 +755,14 @@
if ((!gpio_is_valid(pdata->irq_gpio)))
return -EINVAL;
+ r = of_property_read_string(np, "qcom,clk-src", &pdata->clk_src);
+
+ if (!strcmp(pdata->clk_src, "GPCLK"))
+ pdata->clk_src_gpio = of_get_named_gpio(np,
+ "qcom,clk-en-gpio", 0);
+
+ if (r)
+ return -EINVAL;
return r;
}
@@ -698,7 +771,7 @@
{
int r = 0;
int irqn = 0;
- struct clk *nfc_clk;
+ struct clk *nfc_clk = NULL;
struct device_node *node = client->dev.of_node;
struct qca199x_platform_data *platform_data;
struct qca199x_dev *qca199x_dev;
@@ -769,7 +842,7 @@
dev_err(&client->dev,
"NFC: unable to request gpio [%d]\n",
platform_data->dis_gpio);
- goto err_dis_gpio;
+ goto err_free_dev;
}
r = gpio_direction_output(platform_data->dis_gpio, 1);
if (r) {
@@ -785,15 +858,28 @@
gpio_set_value(platform_data->dis_gpio, 1);/* HPD */
msleep(20);
gpio_set_value(platform_data->dis_gpio, 0);/* ULPM */
-
- nfc_clk = clk_get(&client->dev, "ref_clk");
-
- if (nfc_clk == NULL)
- goto err_dis_gpio;
-
+ if (!strcmp(platform_data->clk_src, "BBCLK2")) {
+ nfc_clk = clk_get(&client->dev, "ref_clk");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else if (!strcmp(platform_data->clk_src, "RFCLK3")) {
+ nfc_clk = clk_get(&client->dev, "ref_clk_rf");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else if (!strcmp(platform_data->clk_src, "GPCLK")) {
+ if (gpio_is_valid(platform_data->clk_src_gpio)) {
+ nfc_clk = clk_get(&client->dev, "core_clk");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else {
+ goto err_dis_gpio;
+ }
+ } else {
+ nfc_clk = NULL;
+ }
r = clk_prepare_enable(nfc_clk);
if (r)
- goto err_dis_gpio;
+ goto err_clk;
platform_data->ven_gpio = of_get_named_gpio(node,
"qcom,clk-gpio", 0);
@@ -813,11 +899,9 @@
platform_data->ven_gpio);
goto err_ven_gpio;
}
-
} else {
-
dev_err(&client->dev, "ven gpio not provided\n");
- goto err_dis_gpio;
+ goto err_clk;
}
qca199x_dev->dis_gpio = platform_data->dis_gpio;
qca199x_dev->irq_gpio = platform_data->irq_gpio;
@@ -871,7 +955,18 @@
mutex_destroy(&qca199x_dev->read_mutex);
err_ven_gpio:
gpio_free(platform_data->ven_gpio);
+err_clk:
+ clk_disable_unprepare(nfc_clk);
err_dis_gpio:
+ r = gpio_direction_input(platform_data->dis_gpio);
+ if (r)
+ dev_err(&client->dev, "nfc-nci probe: Unable to set direction\n");
+ if (!strcmp(platform_data->clk_src, "GPCLK")) {
+ r = gpio_direction_input(platform_data->clk_src_gpio);
+ if (r)
+ dev_err(&client->dev, "nfc-nci probe: Unable to set direction\n");
+ gpio_free(platform_data->clk_src_gpio);
+ }
gpio_free(platform_data->dis_gpio);
err_irq:
gpio_free(platform_data->irq_gpio);
diff --git a/drivers/nfc/nfc-nci.h b/drivers/nfc/nfc-nci.h
index c3cabc2..81f2521 100644
--- a/drivers/nfc/nfc-nci.h
+++ b/drivers/nfc/nfc-nci.h
@@ -49,26 +49,27 @@
enum ehandler_mode handle_flavour;
} tdevicemode;
-#define NFC_DRIVER_NAME "nfc-nci"
+#define NFC_DRIVER_NAME "nfc-nci"
#define NFC_I2C_DRIVER_NAME "NCI NFC I2C Interface",
-#define NCI_I2C_SLAVE (0x2C)
-#define NFC_I2C_BUS 3 /* 6, 10, 4, 5 */
-#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int)
-#define NFCC_MODE _IOW(0xE9, 0x02, unsigned int)
+#define NCI_I2C_SLAVE (0x2C)
+#define NFC_I2C_BUS 3 /* 6, 10, 4, 5 */
+#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int)
+#define NFCC_MODE _IOW(0xE9, 0x02, unsigned int)
#define NFC_KERNEL_LOGGING_MODE _IOW(0xE9, 0x03, unsigned int)
-#define SET_RX_BLOCK _IOW(0xE9, 0x04, unsigned int)
+#define SET_RX_BLOCK _IOW(0xE9, 0x04, unsigned int)
#define SET_EMULATOR_TEST_POINT _IOW(0xE9, 0x05, unsigned int)
+#define NFCC_VERSION _IOW(0xE9, 0x08, unsigned int)
-#define NFC_MAX_I2C_TRANSFER (0x0400)
-#define NFC_MSG_MAX_SIZE (0x21)
+#define NFC_MAX_I2C_TRANSFER (0x0400)
+#define NFC_MSG_MAX_SIZE (0x21)
#define NFC_RX_BUFFER_CNT_START (0x0)
-#define NFC_RX_BUFFER_BLOCK_SIZE (0x120) /* Bytes per Block */
+#define NFC_RX_BUFFER_BLOCK_SIZE (0x120) /* Bytes per Block */
#define NFC_RX_BUFFER_PAGE_SIZE (0x1000) /* Page size Bytes */
#define NFC_RX_BUFFER_PAGES (0x8)
-#define NFC_RX_ORDER_FREE_PAGES (0x3) /* Free 8 Pages */
+#define NFC_RX_ORDER_FREE_PAGES (0x3) /* Free 8 Pages */
/* The total no. of Blocks */
#define NFC_RX_BUFFER_CNT_LIMIT (unsigned short)( \
@@ -86,10 +87,10 @@
/** Power Management Related **/
-#define NFCC_WAKE (0x01)
-#define NFCC_SLEEP (0x00)
+#define NFCC_WAKE (0x01)
+#define NFCC_SLEEP (0x00)
-#define XTAL_CLOCK (0X00)
+#define XTAL_CLOCK (0X00)
#define REFERENCE_CLOCK (0X01)
/* LDO Trim Settings */
@@ -122,8 +123,8 @@
#define LOCALBIASXTAL (0x20)
#define BIAS2X_FORCE (0x10)
#define BIAS2X (0x08)
-#define LBIAS2X (0x04)
-#define SMALLRF (0x02)
+#define LBIAS2X (0x04)
+#define SMALLRF (0x02)
#define SMALLRBIAS (0x01)
/* Select as appropriate */
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index b4edce8..c0371a5 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -1031,8 +1031,11 @@
index = ffs(pon_sts);
if ((index > PON_REASON_MAX) || (index < 0))
index = 0;
- pr_info("PMIC@SID%d Power-on reason: %s\n", pon->spmi->sid,
- index ? qpnp_pon_reason[index - 1] : "Unknown");
+
+ cold_boot = !qpnp_pon_is_warm_reset();
+ pr_info("PMIC@SID%d Power-on reason: %s and '%s' boot\n",
+ pon->spmi->sid, index ? qpnp_pon_reason[index - 1] :
+ "Unknown", cold_boot ? "cold" : "warm");
rc = of_property_read_u32(pon->spmi->dev.of_node,
"qcom,pon-dbc-delay", &delay);
diff --git a/drivers/usb/dwc3/dwc3_otg.c b/drivers/usb/dwc3/dwc3_otg.c
index 5348eb5..9599936 100644
--- a/drivers/usb/dwc3/dwc3_otg.c
+++ b/drivers/usb/dwc3/dwc3_otg.c
@@ -24,7 +24,7 @@
#include "io.h"
#include "xhci.h"
-#define VBUS_REG_CHECK_DELAY (jiffies + msecs_to_jiffies(1000))
+#define VBUS_REG_CHECK_DELAY (msecs_to_jiffies(1000))
#define MAX_INVALID_CHRGR_RETRY 3
static int max_chgr_retry_count = MAX_INVALID_CHRGR_RETRY;
module_param(max_chgr_retry_count, int, S_IRUGO | S_IWUSR);
@@ -678,7 +678,7 @@
struct dwc3_charger *charger = dotg->charger;
bool work = 0;
int ret = 0;
- int delay = 0;
+ unsigned long delay = 0;
pm_runtime_resume(phy->dev);
dev_dbg(phy->dev, "%s state\n", otg_state_string(phy->state));
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 8fa4774..8588ffb 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2617,10 +2617,13 @@
}
}
+ /*
+ * Notify suspend only to gadget driver, but not resume. Resume is
+ * notified as part of wakeup event in dwc3_gadget_wakeup_interrupt().
+ */
if (next == DWC3_LINK_STATE_U0) {
if (dwc->link_state == DWC3_LINK_STATE_U3) {
dbg_event(0xFF, "RESUME", 0);
- dwc->gadget_driver->resume(&dwc->gadget);
}
} else if (next == DWC3_LINK_STATE_U3) {
dbg_event(0xFF, "SUSPEND", 0);
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index bbb206d..6765078 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -1478,7 +1478,11 @@
rndis->ethaddr[0], rndis->ethaddr[1], rndis->ethaddr[2],
rndis->ethaddr[3], rndis->ethaddr[4], rndis->ethaddr[5]);
- ret = gether_setup_name(c->cdev->gadget, rndis->ethaddr, "rndis");
+ if (rndis->ethaddr[0])
+ ret = gether_setup_name(c->cdev->gadget, NULL, "rndis");
+ else
+ ret = gether_setup_name(c->cdev->gadget, rndis->ethaddr,
+ "rndis");
if (ret) {
pr_err("%s: gether_setup failed\n", __func__);
return ret;
diff --git a/drivers/video/msm/mdss/dsi_v2.c b/drivers/video/msm/mdss/dsi_v2.c
index 531c814..65cca0e 100644
--- a/drivers/video/msm/mdss/dsi_v2.c
+++ b/drivers/video/msm/mdss/dsi_v2.c
@@ -141,8 +141,6 @@
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
struct device_node *np = pdev->dev.of_node;
- int rc = 0, i = 0;
- u32 tmp[9];
ctrl_pdata->disp_en_gpio = of_get_named_gpio(np,
"qcom,platform-enable-gpio", 0);
@@ -160,15 +158,6 @@
__func__, __LINE__);
}
- rc = of_property_read_u32_array(np,
- "qcom,platform-reset-sequence", tmp, MDSS_DSI_RST_SEQ_LEN);
- if (rc)
- pr_err("%s:%d, unable to read gpio reset sequence\n",
- __func__, __LINE__);
- else
- for (i = 0; i < MDSS_DSI_RST_SEQ_LEN; ++i)
- ctrl_pdata->rst_seq[i] = tmp[i];
-
ctrl_pdata->rst_gpio = of_get_named_gpio(np,
"qcom,platform-reset-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->rst_gpio))
diff --git a/drivers/video/msm/mdss/mdp3.c b/drivers/video/msm/mdss/mdp3.c
index eff60a3..55037e3 100644
--- a/drivers/video/msm/mdss/mdp3.c
+++ b/drivers/video/msm/mdss/mdp3.c
@@ -1841,6 +1841,14 @@
return rc;
}
+static int mdp3_debug_dump_stats(void *data, char *buf, int len)
+{
+ int total = 0;
+ total = scnprintf(buf, len,"underrun: %08u\n",
+ mdp3_res->underrun_cnt);
+ return total;
+}
+
static void mdp3_debug_enable_clock(int on)
{
if (on)
@@ -1860,7 +1868,7 @@
mdss_res = mdata;
- mdata->debug_inf.debug_dump_stats = NULL;
+ mdata->debug_inf.debug_dump_stats = mdp3_debug_dump_stats;
mdata->debug_inf.debug_enable_clock = mdp3_debug_enable_clock;
rc = mdss_debugfs_init(mdata);
@@ -1882,6 +1890,14 @@
}
}
+static void mdp3_dma_underrun_intr_handler(int type, void *arg)
+{
+ mdp3_res->underrun_cnt++;
+ pr_debug("display underrun detected count=%d\n",
+ mdp3_res->underrun_cnt);
+}
+
+
static int mdp3_probe(struct platform_device *pdev)
{
int rc;
@@ -1892,6 +1908,11 @@
.fb_stride = mdp3_fb_stride,
};
+ struct mdp3_intr_cb underrun_cb = {
+ .cb = mdp3_dma_underrun_intr_handler,
+ .data = NULL,
+ };
+
if (!pdev->dev.of_node) {
pr_err("MDP driver only supports device tree probe\n");
return -ENOTSUPP;
@@ -1939,6 +1960,11 @@
if (rc)
pr_err("unable to register mdp instance\n");
+ rc = mdp3_set_intr_callback(MDP3_INTR_LCDC_UNDERFLOW,
+ &underrun_cb);
+ if (rc)
+ pr_err("unable to configure interrupt callback\n");
+
probe_done:
if (IS_ERR_VALUE(rc)) {
mdp3_res_deinit();
diff --git a/drivers/video/msm/mdss/mdp3.h b/drivers/video/msm/mdss/mdp3.h
index caee34f..4480c20 100644
--- a/drivers/video/msm/mdss/mdp3.h
+++ b/drivers/video/msm/mdss/mdp3.h
@@ -144,6 +144,7 @@
u32 irq_ref_count[MDP3_MAX_INTR];
u32 irq_mask;
struct mdp3_intr_cb callbacks[MDP3_MAX_INTR];
+ u32 underrun_cnt;
int irq_registered;
diff --git a/drivers/video/msm/mdss/mdp3_ctrl.c b/drivers/video/msm/mdss/mdp3_ctrl.c
index a888541..08bff9a 100644
--- a/drivers/video/msm/mdss/mdp3_ctrl.c
+++ b/drivers/video/msm/mdss/mdp3_ctrl.c
@@ -742,7 +742,8 @@
return rc;
}
-static int mdp3_ctrl_display_commit_kickoff(struct msm_fb_data_type *mfd)
+static int mdp3_ctrl_display_commit_kickoff(struct msm_fb_data_type *mfd,
+ struct mdp_display_commit *cmt_data)
{
struct mdp3_session_data *mdp3_session;
struct mdp3_img_data *data;
diff --git a/drivers/video/msm/mdss/mdp3_dma.c b/drivers/video/msm/mdss/mdp3_dma.c
index 5874286..89f3e27 100644
--- a/drivers/video/msm/mdss/mdp3_dma.c
+++ b/drivers/video/msm/mdss/mdp3_dma.c
@@ -159,6 +159,7 @@
.data = dma,
};
+
struct mdp3_intr_cb hist_cb = {
.cb = mdp3_hist_done_intr_handler,
.data = dma,
@@ -298,6 +299,7 @@
dma->output_config = *output_config;
mdp3_dma_sync_config(dma, source_config);
+ mdp3_irq_enable(MDP3_INTR_LCDC_UNDERFLOW);
mdp3_dma_callback_setup(dma);
return 0;
}
@@ -824,6 +826,7 @@
mdp3_dma_callback_disable(dma, MDP3_DMA_CALLBACK_TYPE_VSYNC |
MDP3_DMA_CALLBACK_TYPE_DMA_DONE);
+ mdp3_irq_disable(MDP3_INTR_LCDC_UNDERFLOW);
init_completion(&dma->dma_comp);
dma->vsync_client.handler = NULL;
diff --git a/drivers/video/msm/mdss/mdp3_ppp.c b/drivers/video/msm/mdss/mdp3_ppp.c
index 6e62cc7..1b1ddf1 100644
--- a/drivers/video/msm/mdss/mdp3_ppp.c
+++ b/drivers/video/msm/mdss/mdp3_ppp.c
@@ -495,6 +495,9 @@
{
int dst_h, src_w, i;
uint32_t mdp_op = blit_op->mdp_op;
+ void *src_p0 = blit_op->src.p0;
+ void *src_p1 = blit_op->src.p1;
+ void *dst_p0 = blit_op->dst.p0;
src_w = req->src_rect.w;
dst_h = blit_op->dst.roi.height;
@@ -527,8 +530,11 @@
/* this is for a remainder update */
dst_h -= 16;
src_w -= blit_op->src.roi.width;
- /* restore mdp_op since MDPOP_ASCALE have been cleared */
+ /* restore parameters that may have been overwritten */
blit_op->mdp_op = mdp_op;
+ blit_op->src.p0 = src_p0;
+ blit_op->src.p1 = src_p1;
+ blit_op->dst.p0 = dst_p0;
}
if ((dst_h < 0) || (src_w < 0))
diff --git a/drivers/video/msm/mdss/mdp3_ppp_data.c b/drivers/video/msm/mdss/mdp3_ppp_data.c
index e1c0f27..ba2a369 100644
--- a/drivers/video/msm/mdss/mdp3_ppp_data.c
+++ b/drivers/video/msm/mdss/mdp3_ppp_data.c
@@ -16,6 +16,8 @@
#include "mdss_fb.h"
#include "mdp3_ppp.h"
+#define MDP_IS_IMGTYPE_BAD(x) ((x) >= MDP_IMGTYPE_LIMIT)
+
/* bg_config_lut not needed since it is same as src */
const uint32_t src_cfg_lut[MDP_IMGTYPE_LIMIT] = {
[MDP_RGB_565] = MDP_RGB_565_SRC_REG,
@@ -1504,56 +1506,56 @@
uint32_t ppp_bpp(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return bytes_per_pixel[type];
}
uint32_t ppp_src_config(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return src_cfg_lut[type];
}
uint32_t ppp_out_config(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return out_cfg_lut[type];
}
uint32_t ppp_pack_pattern(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return pack_patt_lut[type];
}
uint32_t ppp_dst_op_reg(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return dst_op_reg[type];
}
uint32_t ppp_src_op_reg(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return src_op_reg[type];
}
bool ppp_per_p_alpha(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return per_pixel_alpha[type];
}
bool ppp_multi_plane(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return multi_plane[type];
}
diff --git a/drivers/video/msm/mdss/mdss_dsi.c b/drivers/video/msm/mdss/mdss_dsi.c
index 2d0497c..b353c96 100644
--- a/drivers/video/msm/mdss/mdss_dsi.c
+++ b/drivers/video/msm/mdss/mdss_dsi.c
@@ -662,6 +662,43 @@
return rc;
}
+static int mdss_dsi_ctl_partial_update(struct mdss_panel_data *pdata)
+{
+ int rc = -EINVAL;
+ u32 data;
+ struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
+
+ if (pdata == NULL) {
+ pr_err("%s: Invalid input data\n", __func__);
+ return -EINVAL;
+ }
+
+ ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
+ panel_data);
+
+ /* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
+ data = (((pdata->panel_info.roi_w * 3) + 1) << 16) |
+ (pdata->panel_info.mipi.vc << 8) | DTYPE_DCS_LWRITE;
+ MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x60, data);
+ MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x58, data);
+
+ /* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
+ data = pdata->panel_info.roi_h << 16 | pdata->panel_info.roi_w;
+ MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x64, data);
+ MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, data);
+
+ if (ctrl_pdata->partial_update_fnc)
+ rc = ctrl_pdata->partial_update_fnc(pdata);
+
+ if (rc) {
+ pr_err("%s: unable to initialize the panel\n",
+ __func__);
+ return rc;
+ }
+
+ return rc;
+}
+
static int mdss_dsi_event_handler(struct mdss_panel_data *pdata,
int event, void *arg)
{
@@ -728,6 +765,9 @@
rc = mdss_dsi_blank(pdata);
}
break;
+ case MDSS_EVENT_ENABLE_PARTIAL_UPDATE:
+ rc = mdss_dsi_ctl_partial_update(pdata);
+ break;
default:
pr_debug("%s: unhandled event=%d\n", __func__, event);
break;
@@ -1029,7 +1069,6 @@
{
struct mipi_panel_info *mipi;
int rc, i, len;
- u32 tmp[9];
struct device_node *dsi_ctrl_np = NULL;
struct platform_device *ctrl_pdev = NULL;
bool dynamic_fps;
@@ -1208,15 +1247,6 @@
ctrl_pdata->disp_te_gpio);
}
- rc = of_property_read_u32_array(ctrl_pdev->dev.of_node,
- "qcom,platform-reset-sequence", tmp, MDSS_DSI_RST_SEQ_LEN);
- if (rc)
- pr_err("%s:%d, unable to read gpio reset sequence\n",
- __func__, __LINE__);
- else
- for (i = 0; i < MDSS_DSI_RST_SEQ_LEN; ++i)
- ctrl_pdata->rst_seq[i] = tmp[i];
-
ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-reset-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->rst_gpio)) {
diff --git a/drivers/video/msm/mdss/mdss_dsi.h b/drivers/video/msm/mdss/mdss_dsi.h
index 630330a..121d6ff 100644
--- a/drivers/video/msm/mdss/mdss_dsi.h
+++ b/drivers/video/msm/mdss/mdss_dsi.h
@@ -194,8 +194,6 @@
#define MDSS_DSI_LEN 8 /* 4 x 4 - 6 - 2, bytes dcs header+crc-align */
-#define MDSS_DSI_RST_SEQ_LEN 6
-
struct dsi_buf {
u32 *hdr; /* dsi host header */
char *start; /* buffer start addr */
@@ -313,6 +311,7 @@
int ndx; /* panel_num */
int (*on) (struct mdss_panel_data *pdata);
int (*off) (struct mdss_panel_data *pdata);
+ int (*partial_update_fnc) (struct mdss_panel_data *pdata);
struct mdss_panel_data panel_data;
unsigned char *ctrl_base;
int reg_size;
@@ -345,7 +344,6 @@
u32 pclk_rate;
u32 byte_clk_rate;
struct dss_module_power power_data;
- int rst_seq[MDSS_DSI_RST_SEQ_LEN];
u32 dsi_irq_mask;
struct mdss_hw *dsi_hw;
diff --git a/drivers/video/msm/mdss/mdss_dsi_panel.c b/drivers/video/msm/mdss/mdss_dsi_panel.c
index 203900c..262b7bd 100644
--- a/drivers/video/msm/mdss/mdss_dsi_panel.c
+++ b/drivers/video/msm/mdss/mdss_dsi_panel.c
@@ -182,10 +182,11 @@
pinfo = &(ctrl_pdata->panel_data.panel_info);
if (enable) {
- for (i = 0; i < MDSS_DSI_RST_SEQ_LEN; ++i) {
+ for (i = 0; i < pdata->panel_info.rst_seq_len; ++i) {
gpio_set_value((ctrl_pdata->rst_gpio),
- ctrl_pdata->rst_seq[i]);
- msleep(ctrl_pdata->rst_seq[++i]);
+ pdata->panel_info.rst_seq[i]);
+ if (pdata->panel_info.rst_seq[++i])
+ usleep(pdata->panel_info.rst_seq[i] * 1000);
}
if (gpio_is_valid(ctrl_pdata->disp_en_gpio))
gpio_set_value((ctrl_pdata->disp_en_gpio), 1);
@@ -209,6 +210,61 @@
}
}
+static char caset[] = {0x2a, 0x00, 0x00, 0x03, 0x00}; /* DTYPE_DCS_LWRITE */
+static char paset[] = {0x2b, 0x00, 0x00, 0x05, 0x00}; /* DTYPE_DCS_LWRITE */
+
+static struct dsi_cmd_desc partial_update_enable_cmd[] = {
+ {{DTYPE_DCS_LWRITE, 1, 0, 0, 1, sizeof(caset)}, caset},
+ {{DTYPE_DCS_LWRITE, 1, 0, 0, 1, sizeof(paset)}, paset},
+};
+
+static int mdss_dsi_panel_partial_update(struct mdss_panel_data *pdata)
+{
+ struct mipi_panel_info *mipi;
+ struct mdss_dsi_ctrl_pdata *ctrl = NULL;
+ struct dcs_cmd_req cmdreq;
+ int rc = 0;
+
+ if (pdata == NULL) {
+ pr_err("%s: Invalid input data\n", __func__);
+ return -EINVAL;
+ }
+
+ ctrl = container_of(pdata, struct mdss_dsi_ctrl_pdata,
+ panel_data);
+ mipi = &pdata->panel_info.mipi;
+
+ pr_debug("%s: ctrl=%p ndx=%d\n", __func__, ctrl, ctrl->ndx);
+
+ caset[1] = (((pdata->panel_info.roi_x) & 0xFF00) >> 8);
+ caset[2] = (((pdata->panel_info.roi_x) & 0xFF));
+ caset[3] = (((pdata->panel_info.roi_x - 1 + pdata->panel_info.roi_w)
+ & 0xFF00) >> 8);
+ caset[4] = (((pdata->panel_info.roi_x - 1 + pdata->panel_info.roi_w)
+ & 0xFF));
+ partial_update_enable_cmd[0].payload = caset;
+
+ paset[1] = (((pdata->panel_info.roi_y) & 0xFF00) >> 8);
+ paset[2] = (((pdata->panel_info.roi_y) & 0xFF));
+ paset[3] = (((pdata->panel_info.roi_y - 1 + pdata->panel_info.roi_h)
+ & 0xFF00) >> 8);
+ paset[4] = (((pdata->panel_info.roi_y - 1 + pdata->panel_info.roi_h)
+ & 0xFF));
+ partial_update_enable_cmd[1].payload = paset;
+
+ pr_debug("%s: enabling partial update\n", __func__);
+ memset(&cmdreq, 0, sizeof(cmdreq));
+ cmdreq.cmds = partial_update_enable_cmd;
+ cmdreq.cmds_cnt = 2;
+ cmdreq.flags = CMD_REQ_COMMIT | CMD_CLK_CTRL;
+ cmdreq.rlen = 0;
+ cmdreq.cb = NULL;
+
+ mdss_dsi_cmdlist_put(ctrl, &cmdreq);
+
+ return rc;
+}
+
static void mdss_dsi_panel_bl_ctrl(struct mdss_panel_data *pdata,
u32 bl_level)
{
@@ -492,6 +548,35 @@
}
+static int mdss_dsi_parse_reset_seq(struct device_node *np,
+ u32 rst_seq[MDSS_DSI_RST_SEQ_LEN], u32 *rst_len,
+ const char *name)
+{
+ int num = 0, i;
+ int rc;
+ struct property *data;
+ u32 tmp[MDSS_DSI_RST_SEQ_LEN];
+ *rst_len = 0;
+ data = of_find_property(np, name, &num);
+ num /= sizeof(u32);
+ if (!data || !num || num > MDSS_DSI_RST_SEQ_LEN || num % 2) {
+ pr_debug("%s:%d, error reading %s, length found = %d\n",
+ __func__, __LINE__, name, num);
+ } else {
+ rc = of_property_read_u32_array(np, name, tmp, num);
+ if (rc)
+ pr_debug("%s:%d, error reading %s, rc = %d\n",
+ __func__, __LINE__, name, rc);
+ else {
+ for (i = 0; i < num; ++i)
+ rst_seq[i] = tmp[i];
+ *rst_len = num;
+ }
+ }
+ return 0;
+}
+
+
static int mdss_panel_parse_dt(struct device_node *np,
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
@@ -740,6 +825,9 @@
mdss_dsi_parse_fbc_params(np, pinfo);
+ mdss_dsi_parse_reset_seq(np, pinfo->rst_seq, &(pinfo->rst_seq_len),
+ "qcom,mdss-dsi-reset-sequence");
+
mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds,
"qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state");
@@ -759,6 +847,7 @@
int rc = 0;
static const char *panel_name;
bool cont_splash_enabled;
+ bool partial_update_enabled;
if (!node) {
pr_err("%s: no panel node\n", __func__);
@@ -795,6 +884,18 @@
ctrl_pdata->panel_data.panel_info.cont_splash_enabled = 1;
}
+ partial_update_enabled = of_property_read_bool(node,
+ "qcom,partial-update-enabled");
+ if (partial_update_enabled) {
+ pr_info("%s:%d Partial update enabled.\n", __func__, __LINE__);
+ ctrl_pdata->panel_data.panel_info.partial_update_enabled = 1;
+ ctrl_pdata->partial_update_fnc = mdss_dsi_panel_partial_update;
+ } else {
+ pr_info("%s:%d Partial update disabled.\n", __func__, __LINE__);
+ ctrl_pdata->panel_data.panel_info.partial_update_enabled = 0;
+ ctrl_pdata->partial_update_fnc = NULL;
+ }
+
ctrl_pdata->on = mdss_dsi_panel_on;
ctrl_pdata->off = mdss_dsi_panel_off;
ctrl_pdata->panel_data.set_backlight = mdss_dsi_panel_bl_ctrl;
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index 793cbd7..2aaa641 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -376,18 +376,24 @@
mdss_fb_create_sysfs(mfd);
mdss_fb_send_panel_event(mfd, MDSS_EVENT_FB_REGISTERED, fbi);
- if (mfd->timeline == NULL) {
+ mfd->mdp_sync_pt_data.fence_name = "mdp-fence";
+ if (mfd->mdp_sync_pt_data.timeline == NULL) {
char timeline_name[16];
snprintf(timeline_name, sizeof(timeline_name),
"mdss_fb_%d", mfd->index);
- mfd->timeline = sw_sync_timeline_create(timeline_name);
- if (mfd->timeline == NULL) {
+ mfd->mdp_sync_pt_data.timeline =
+ sw_sync_timeline_create(timeline_name);
+ if (mfd->mdp_sync_pt_data.timeline == NULL) {
pr_err("%s: cannot create time line", __func__);
return -ENOMEM;
} else {
- mfd->timeline_value = 0;
+ mfd->mdp_sync_pt_data.timeline_value = 0;
}
}
+ if (mfd->panel.type == WRITEBACK_PANEL)
+ mfd->mdp_sync_pt_data.threshold = 1;
+ else
+ mfd->mdp_sync_pt_data.threshold = 2;
return rc;
}
@@ -1078,7 +1084,8 @@
mutex_init(&mfd->update.lock);
mutex_init(&mfd->no_update.lock);
- mutex_init(&mfd->sync_mutex);
+ mutex_init(&mfd->mdp_sync_pt_data.sync_mutex);
+
init_timer(&mfd->no_update.timer);
mfd->no_update.timer.function = mdss_fb_no_update_notify_timer_cb;
mfd->no_update.timer.data = (unsigned long)mfd;
@@ -1233,18 +1240,18 @@
}
}
-void mdss_fb_wait_for_fence(struct msm_fb_data_type *mfd)
+void mdss_fb_wait_for_fence(struct msm_sync_pt_data *sync_pt_data)
{
int i, ret = 0;
/* buf sync */
- for (i = 0; i < mfd->acq_fen_cnt; i++) {
- ret = sync_fence_wait(mfd->acq_fen[i],
+ for (i = 0; i < sync_pt_data->acq_fen_cnt; i++) {
+ ret = sync_fence_wait(sync_pt_data->acq_fen[i],
WAIT_FENCE_FIRST_TIMEOUT);
if (ret == -ETIME) {
pr_warn("sync_fence_wait timed out! ");
pr_cont("Waiting %ld more seconds\n",
WAIT_FENCE_FINAL_TIMEOUT/MSEC_PER_SEC);
- ret = sync_fence_wait(mfd->acq_fen[i],
+ ret = sync_fence_wait(sync_pt_data->acq_fen[i],
WAIT_FENCE_FINAL_TIMEOUT);
}
if (ret < 0) {
@@ -1252,46 +1259,46 @@
__func__, ret);
break;
}
- sync_fence_put(mfd->acq_fen[i]);
+ sync_fence_put(sync_pt_data->acq_fen[i]);
}
if (ret < 0) {
- while (i < mfd->acq_fen_cnt) {
- sync_fence_put(mfd->acq_fen[i]);
+ while (i < sync_pt_data->acq_fen_cnt) {
+ sync_fence_put(sync_pt_data->acq_fen[i]);
i++;
}
}
- mfd->acq_fen_cnt = 0;
+ sync_pt_data->acq_fen_cnt = 0;
}
-static void mdss_fb_signal_timeline_locked(struct msm_fb_data_type *mfd)
+static void mdss_fb_signal_timeline_locked(
+ struct msm_sync_pt_data *sync_pt_data)
{
- if (mfd->timeline && !list_empty((const struct list_head *)
- (&(mfd->timeline->obj.active_list_head)))) {
- sw_sync_timeline_inc(mfd->timeline, 1);
- mfd->timeline_value++;
+ if (sync_pt_data->timeline && !list_empty((const struct list_head *)
+ (&(sync_pt_data->timeline->obj.active_list_head)))) {
+ sw_sync_timeline_inc(sync_pt_data->timeline, 1);
+ sync_pt_data->timeline_value++;
}
- mfd->last_rel_fence = mfd->cur_rel_fence;
- mfd->cur_rel_fence = 0;
+ sync_pt_data->cur_rel_fence = 0;
}
-void mdss_fb_signal_timeline(struct msm_fb_data_type *mfd)
+void mdss_fb_signal_timeline(struct msm_sync_pt_data *sync_pt_data)
{
- mutex_lock(&mfd->sync_mutex);
- mdss_fb_signal_timeline_locked(mfd);
- mutex_unlock(&mfd->sync_mutex);
+ mutex_lock(&sync_pt_data->sync_mutex);
+ mdss_fb_signal_timeline_locked(sync_pt_data);
+ mutex_unlock(&sync_pt_data->sync_mutex);
}
static void mdss_fb_release_fences(struct msm_fb_data_type *mfd)
{
- mutex_lock(&mfd->sync_mutex);
- if (mfd->timeline) {
- sw_sync_timeline_inc(mfd->timeline, 2);
- mfd->timeline_value += 2;
+
+ mutex_lock(&mfd->mdp_sync_pt_data.sync_mutex);
+ if (mfd->mdp_sync_pt_data.timeline) {
+ sw_sync_timeline_inc(mfd->mdp_sync_pt_data.timeline, 2);
+ mfd->mdp_sync_pt_data.timeline_value += 2;
}
- mfd->last_rel_fence = 0;
- mfd->cur_rel_fence = 0;
- mutex_unlock(&mfd->sync_mutex);
+ mfd->mdp_sync_pt_data.cur_rel_fence = 0;
+ mutex_unlock(&mfd->mdp_sync_pt_data.sync_mutex);
}
static void mdss_fb_pan_idle(struct msm_fb_data_type *mfd)
@@ -1308,11 +1315,11 @@
pr_err("%s wait for commit_comp timeout %d %d",
__func__, ret, mfd->is_committing);
if (ret <= 0) {
- mutex_lock(&mfd->sync_mutex);
- mdss_fb_signal_timeline_locked(mfd);
+ mutex_lock(&mfd->mdp_sync_pt_data.sync_mutex);
+ mdss_fb_signal_timeline_locked(&mfd->mdp_sync_pt_data);
mfd->is_committing = 0;
complete_all(&mfd->commit_comp);
- mutex_unlock(&mfd->sync_mutex);
+ mutex_unlock(&mfd->mdp_sync_pt_data.sync_mutex);
}
}
}
@@ -1337,7 +1344,7 @@
mdss_fb_pan_idle(mfd);
- mutex_lock(&mfd->sync_mutex);
+ mutex_lock(&mfd->mdp_sync_pt_data.sync_mutex);
if (info->fix.xpanstep)
info->var.xoffset =
(var->xoffset / info->fix.xpanstep) * info->fix.xpanstep;
@@ -1353,7 +1360,7 @@
INIT_COMPLETION(mfd->commit_comp);
mfd->is_committing = 1;
schedule_work(&mfd->commit_work);
- mutex_unlock(&mfd->sync_mutex);
+ mutex_unlock(&mfd->mdp_sync_pt_data.sync_mutex);
if (wait_for_finish)
mdss_fb_pan_idle(mfd);
return ret;
@@ -1391,13 +1398,13 @@
info->var.yoffset =
(var->yoffset / info->fix.ypanstep) * info->fix.ypanstep;
- mdss_fb_wait_for_fence(mfd);
+ mdss_fb_wait_for_fence(&mfd->mdp_sync_pt_data);
if (mfd->mdp.dma_fnc)
mfd->mdp.dma_fnc(mfd);
else
pr_warn("dma function not set for panel type=%d\n",
mfd->panel.type);
- mdss_fb_signal_timeline(mfd);
+ mdss_fb_signal_timeline(&mfd->mdp_sync_pt_data);
mdss_fb_update_backlight(mfd);
return 0;
}
@@ -1422,28 +1429,29 @@
struct fb_var_screeninfo *var;
struct fb_info *info;
struct msm_fb_backup_type *fb_backup;
- int ret;
+ int ret = 0;
mfd = container_of(work, struct msm_fb_data_type, commit_work);
fb_backup = (struct msm_fb_backup_type *)mfd->msm_fb_backup;
info = &fb_backup->info;
if (fb_backup->disp_commit.flags &
MDP_DISPLAY_COMMIT_OVERLAY) {
- mdss_fb_wait_for_fence(mfd);
+ mdss_fb_wait_for_fence(&mfd->mdp_sync_pt_data);
if (mfd->mdp.kickoff_fnc)
- mfd->mdp.kickoff_fnc(mfd);
- mdss_fb_update_backlight(mfd);
- mdss_fb_signal_timeline(mfd);
+ ret = mfd->mdp.kickoff_fnc(mfd, &fb_backup->disp_commit);
+ if (!ret)
+ mdss_fb_update_backlight(mfd);
+ mdss_fb_signal_timeline(&mfd->mdp_sync_pt_data);
} else {
var = &fb_backup->disp_commit.var;
ret = mdss_fb_pan_display_sub(var, info);
if (ret)
pr_err("%s fails: ret = %x", __func__, ret);
}
- mutex_lock(&mfd->sync_mutex);
+ mutex_lock(&mfd->mdp_sync_pt_data.sync_mutex);
mfd->is_committing = 0;
complete_all(&mfd->commit_comp);
- mutex_unlock(&mfd->sync_mutex);
+ mutex_unlock(&mfd->mdp_sync_pt_data.sync_mutex);
}
static int mdss_fb_check_var(struct fb_var_screeninfo *var,
@@ -1701,21 +1709,17 @@
return 0;
}
-static int mdss_fb_handle_buf_sync_ioctl(struct msm_fb_data_type *mfd,
- struct mdp_buf_sync *buf_sync)
+static int mdss_fb_handle_buf_sync_ioctl(struct msm_sync_pt_data *sync_pt_data,
+ struct mdp_buf_sync *buf_sync)
{
int i, fence_cnt = 0, ret = 0;
int acq_fen_fd[MDP_MAX_FENCE_FD];
struct sync_fence *fence;
- u32 threshold;
if ((buf_sync->acq_fen_fd_cnt > MDP_MAX_FENCE_FD) ||
- (mfd->timeline == NULL))
+ (sync_pt_data->timeline == NULL))
return -EINVAL;
- if ((!mfd->op_enable) || (!mfd->panel_power_on))
- return -EPERM;
-
if (buf_sync->acq_fen_fd_cnt)
ret = copy_from_user(acq_fen_fd, buf_sync->acq_fen_fd,
buf_sync->acq_fen_fd_cnt * sizeof(int));
@@ -1723,7 +1727,8 @@
pr_err("%s:copy_from_user failed", __func__);
return ret;
}
- mutex_lock(&mfd->sync_mutex);
+
+ mutex_lock(&sync_pt_data->sync_mutex);
for (i = 0; i < buf_sync->acq_fen_fd_cnt; i++) {
fence = sync_fence_fdget(acq_fen_fd[i]);
if (fence == NULL) {
@@ -1732,64 +1737,66 @@
ret = -EINVAL;
break;
}
- mfd->acq_fen[i] = fence;
+ sync_pt_data->acq_fen[i] = fence;
}
fence_cnt = i;
if (ret)
goto buf_sync_err_1;
- mfd->acq_fen_cnt = fence_cnt;
+ sync_pt_data->acq_fen_cnt = fence_cnt;
+
if (buf_sync->flags & MDP_BUF_SYNC_FLAG_WAIT)
- mdss_fb_wait_for_fence(mfd);
+ mdss_fb_wait_for_fence(sync_pt_data);
- if (mfd->panel.type == WRITEBACK_PANEL)
- threshold = 1;
- else
- threshold = 2;
+ sync_pt_data->cur_rel_sync_pt = sw_sync_pt_create(
+ sync_pt_data->timeline, sync_pt_data->timeline_value +
+ sync_pt_data->threshold);
- mfd->cur_rel_sync_pt = sw_sync_pt_create(mfd->timeline,
- mfd->timeline_value + threshold);
- if (mfd->cur_rel_sync_pt == NULL) {
+ if (sync_pt_data->cur_rel_sync_pt == NULL) {
pr_err("%s: cannot create sync point", __func__);
ret = -ENOMEM;
goto buf_sync_err_1;
}
/* create fence */
- mfd->cur_rel_fence = sync_fence_create("mdp-fence",
- mfd->cur_rel_sync_pt);
- if (mfd->cur_rel_fence == NULL) {
- sync_pt_free(mfd->cur_rel_sync_pt);
- mfd->cur_rel_sync_pt = NULL;
+ sync_pt_data->cur_rel_fence = sync_fence_create(
+ sync_pt_data->fence_name, sync_pt_data->cur_rel_sync_pt);
+
+ if (sync_pt_data->cur_rel_fence == NULL) {
+ sync_pt_free(sync_pt_data->cur_rel_sync_pt);
+ sync_pt_data->cur_rel_sync_pt = NULL;
pr_err("%s: cannot create fence", __func__);
ret = -ENOMEM;
goto buf_sync_err_1;
}
/* create fd */
- mfd->cur_rel_fen_fd = get_unused_fd_flags(0);
- if (mfd->cur_rel_fen_fd < 0) {
+ sync_pt_data->cur_rel_fen_fd = get_unused_fd_flags(0);
+ if (sync_pt_data->cur_rel_fen_fd < 0) {
pr_err("%s: get_unused_fd_flags failed", __func__);
ret = -EIO;
goto buf_sync_err_2;
}
- sync_fence_install(mfd->cur_rel_fence, mfd->cur_rel_fen_fd);
+
+ sync_fence_install(sync_pt_data->cur_rel_fence,
+ sync_pt_data->cur_rel_fen_fd);
ret = copy_to_user(buf_sync->rel_fen_fd,
- &mfd->cur_rel_fen_fd, sizeof(int));
+ &sync_pt_data->cur_rel_fen_fd, sizeof(int));
+
if (ret) {
pr_err("%s:copy_to_user failed", __func__);
goto buf_sync_err_3;
}
- mutex_unlock(&mfd->sync_mutex);
+ mutex_unlock(&sync_pt_data->sync_mutex);
return ret;
buf_sync_err_3:
- put_unused_fd(mfd->cur_rel_fen_fd);
+ put_unused_fd(sync_pt_data->cur_rel_fen_fd);
buf_sync_err_2:
- sync_fence_put(mfd->cur_rel_fence);
- mfd->cur_rel_fence = NULL;
- mfd->cur_rel_fen_fd = 0;
+ sync_fence_put(sync_pt_data->cur_rel_fence);
+ sync_pt_data->cur_rel_fence = NULL;
+ sync_pt_data->cur_rel_fen_fd = 0;
buf_sync_err_1:
for (i = 0; i < fence_cnt; i++)
- sync_fence_put(mfd->acq_fen[i]);
- mfd->acq_fen_cnt = 0;
- mutex_unlock(&mfd->sync_mutex);
+ sync_fence_put(sync_pt_data->acq_fen[i]);
+ sync_pt_data->acq_fen_cnt = 0;
+ mutex_unlock(&sync_pt_data->sync_mutex);
return ret;
}
static int mdss_fb_display_commit(struct fb_info *info,
@@ -1816,7 +1823,7 @@
struct mdp_page_protection fb_page_protection;
int ret = -ENOSYS;
struct mdp_buf_sync buf_sync;
-
+ struct msm_sync_pt_data *sync_pt_data = NULL;
if (!info || !info->par)
return -EINVAL;
mfd = (struct msm_fb_data_type *)info->par;
@@ -1846,8 +1853,14 @@
ret = copy_from_user(&buf_sync, argp, sizeof(buf_sync));
if (ret)
return ret;
+ if ((!mfd->op_enable) || (!mfd->panel_power_on))
+ return -EPERM;
+ if (mfd->mdp.get_sync_fnc)
+ sync_pt_data = mfd->mdp.get_sync_fnc(mfd, &buf_sync);
+ if (!sync_pt_data)
+ sync_pt_data = &mfd->mdp_sync_pt_data;
- ret = mdss_fb_handle_buf_sync_ioctl(mfd, &buf_sync);
+ ret = mdss_fb_handle_buf_sync_ioctl(sync_pt_data, &buf_sync);
if (!ret)
ret = copy_to_user(argp, &buf_sync, sizeof(buf_sync));
diff --git a/drivers/video/msm/mdss/mdss_fb.h b/drivers/video/msm/mdss/mdss_fb.h
index fd96e63..1400bdd 100644
--- a/drivers/video/msm/mdss/mdss_fb.h
+++ b/drivers/video/msm/mdss/mdss_fb.h
@@ -53,6 +53,19 @@
int value;
};
+struct msm_sync_pt_data {
+ char *fence_name;
+ u32 acq_fen_cnt;
+ struct sync_fence *acq_fen[MDP_MAX_FENCE_FD];
+ int cur_rel_fen_fd;
+ struct sync_pt *cur_rel_sync_pt;
+ struct sync_fence *cur_rel_fence;
+ struct sw_sync_timeline *timeline;
+ int timeline_value;
+ u32 threshold;
+ struct mutex sync_mutex;
+};
+
struct msm_fb_data_type;
struct msm_mdp_interface {
@@ -63,7 +76,8 @@
int (*off_fnc)(struct msm_fb_data_type *mfd);
/* called to release resources associated to the process */
int (*release_fnc)(struct msm_fb_data_type *mfd);
- int (*kickoff_fnc)(struct msm_fb_data_type *mfd);
+ int (*kickoff_fnc)(struct msm_fb_data_type *mfd,
+ struct mdp_display_commit *data);
int (*ioctl_handler)(struct msm_fb_data_type *mfd, u32 cmd, void *arg);
void (*dma_fnc)(struct msm_fb_data_type *mfd);
int (*cursor_update)(struct msm_fb_data_type *mfd,
@@ -74,6 +88,8 @@
int (*update_ad_input)(struct msm_fb_data_type *mfd);
int (*panel_register_done)(struct mdss_panel_data *pdata);
u32 (*fb_stride)(u32 fb_index, u32 xres, int bpp);
+ struct msm_sync_pt_data *(*get_sync_fnc)(struct msm_fb_data_type *mfd,
+ const struct mdp_buf_sync *buf_sync);
void *private1;
};
@@ -137,17 +153,8 @@
struct msm_mdp_interface mdp;
- u32 acq_fen_cnt;
- struct sync_fence *acq_fen[MDP_MAX_FENCE_FD];
- int cur_rel_fen_fd;
- struct sync_pt *cur_rel_sync_pt;
- struct sync_fence *cur_rel_fence;
- struct sync_fence *last_rel_fence;
- struct sw_sync_timeline *timeline;
- int timeline_value;
- u32 last_acq_fen_cnt;
- struct sync_fence *last_acq_fen[MDP_MAX_FENCE_FD];
- struct mutex sync_mutex;
+ struct msm_sync_pt_data mdp_sync_pt_data;
+
/* for non-blocking */
struct completion commit_comp;
u32 is_committing;
@@ -187,8 +194,8 @@
int mdss_fb_get_phys_info(unsigned long *start, unsigned long *len, int fb_num);
void mdss_fb_set_backlight(struct msm_fb_data_type *mfd, u32 bkl_lvl);
void mdss_fb_update_backlight(struct msm_fb_data_type *mfd);
-void mdss_fb_wait_for_fence(struct msm_fb_data_type *mfd);
-void mdss_fb_signal_timeline(struct msm_fb_data_type *mfd);
+void mdss_fb_wait_for_fence(struct msm_sync_pt_data *sync_pt_data);
+void mdss_fb_signal_timeline(struct msm_sync_pt_data *sync_pt_data);
int mdss_fb_register_mdp_instance(struct msm_mdp_interface *mdp);
int mdss_fb_dcm(struct msm_fb_data_type *mfd, int req_state);
#endif /* MDSS_FB_H */
diff --git a/drivers/video/msm/mdss/mdss_hdmi_cec.c b/drivers/video/msm/mdss/mdss_hdmi_cec.c
index b74f074..ecde0b9 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_cec.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_cec.c
@@ -756,7 +756,7 @@
hdmi_wta_cec_enable);
static DEVICE_ATTR(enable_compliance, S_IRUGO | S_IWUSR,
hdmi_rda_cec_enable_compliance, hdmi_wta_cec_enable_compliance);
-static DEVICE_ATTR(logical_addr, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(logical_addr, S_IRUSR | S_IWUSR,
hdmi_rda_cec_logical_addr, hdmi_wta_cec_logical_addr);
static DEVICE_ATTR(rd_msg, S_IRUGO, hdmi_rda_cec_msg, NULL);
static DEVICE_ATTR(wr_msg, S_IWUSR, NULL, hdmi_wta_cec_msg);
diff --git a/drivers/video/msm/mdss/mdss_hdmi_edid.c b/drivers/video/msm/mdss/mdss_hdmi_edid.c
index 65dc19c..b000e2f 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_edid.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_edid.c
@@ -27,6 +27,8 @@
#define MAX_AUDIO_DATA_BLOCK_SIZE 30
#define MAX_SPKR_ALLOC_DATA_BLOCK_SIZE 3
+#define BUFF_SIZE_3D 128
+
struct hdmi_edid_sink_data {
u32 disp_mode_list[HDMI_VFRMT_MAX];
u32 disp_3d_mode_list[HDMI_VFRMT_MAX];
@@ -249,19 +251,19 @@
if (!hdmi_get_supported_mode(*video_mode))
continue;
if (ret > 0)
- ret += snprintf(buf+ret, PAGE_SIZE-ret, ",%d",
- *video_mode++);
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
+ ",%d", *video_mode++);
else
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
- *video_mode++);
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
+ "%d", *video_mode++);
}
} else {
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%d",
edid_ctrl->video_resolution);
}
DEV_DBG("%s: '%s'\n", __func__, buf);
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
return ret;
} /* hdmi_edid_sysfs_rda_modes */
@@ -279,12 +281,12 @@
return -EINVAL;
}
- ret = snprintf(buf, PAGE_SIZE, "%d\n", edid_ctrl->physical_address);
+ ret = scnprintf(buf, PAGE_SIZE, "%d\n", edid_ctrl->physical_address);
DEV_DBG("%s: '%d'\n", __func__, edid_ctrl->physical_address);
return ret;
} /* hdmi_edid_sysfs_rda_physical_address */
-static DEVICE_ATTR(pa, S_IRUGO, hdmi_edid_sysfs_rda_physical_address, NULL);
+static DEVICE_ATTR(pa, S_IRUSR, hdmi_edid_sysfs_rda_physical_address, NULL);
static ssize_t hdmi_edid_sysfs_rda_scan_info(struct device *dev,
struct device_attribute *attr, char *buf)
@@ -298,7 +300,7 @@
return -EINVAL;
}
- ret = snprintf(buf, PAGE_SIZE, "%d, %d, %d\n", edid_ctrl->pt_scan_info,
+ ret = scnprintf(buf, PAGE_SIZE, "%d, %d, %d\n", edid_ctrl->pt_scan_info,
edid_ctrl->it_scan_info, edid_ctrl->ce_scan_info);
DEV_DBG("%s: '%s'\n", __func__, buf);
@@ -311,7 +313,8 @@
{
ssize_t ret = 0;
int i;
- char buff_3d[128];
+ char buff_3d[BUFF_SIZE_3D];
+
struct hdmi_edid_ctrl *edid_ctrl =
hdmi_get_featuredata_from_sysfs_dev(dev, HDMI_TX_FEAT_EDID);
@@ -327,23 +330,23 @@
for (i = 0; i < edid_ctrl->sink_data.num_of_elements; ++i) {
ret = hdmi_get_video_3d_fmt_2string(*video_3d_mode++,
- buff_3d);
+ buff_3d, sizeof(buff_3d));
if (ret > 0)
- ret += snprintf(buf+ret, PAGE_SIZE-ret,
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
",%d=%s", *video_mode++,
buff_3d);
else
- ret += snprintf(buf+ret, PAGE_SIZE-ret,
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"%d=%s", *video_mode++,
buff_3d);
}
} else {
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%d",
edid_ctrl->video_resolution);
}
DEV_DBG("%s: '%s'\n", __func__, buf);
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
return ret;
} /* hdmi_edid_sysfs_rda_3d_modes */
@@ -816,7 +819,7 @@
static void hdmi_edid_add_sink_3d_format(struct hdmi_edid_sink_data *sink_data,
u32 video_format, u32 video_3d_format)
{
- char string[128];
+ char string[BUFF_SIZE_3D];
u32 added = false;
int i;
@@ -828,7 +831,7 @@
}
}
- hdmi_get_video_3d_fmt_2string(video_3d_format, string);
+ hdmi_get_video_3d_fmt_2string(video_3d_format, string, sizeof(string));
DEV_DBG("%s: EDID[3D]: format: %d [%s], %s %s\n", __func__,
video_format, msm_hdmi_mode_2string(video_format),
diff --git a/drivers/video/msm/mdss/mdss_hdmi_tx.c b/drivers/video/msm/mdss/mdss_hdmi_tx.c
index 0fd3655..7117779 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_tx.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_tx.c
@@ -327,7 +327,7 @@
{
struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
- if (!device || feature_type > HDMI_TX_FEAT_MAX) {
+ if (!device || feature_type >= HDMI_TX_FEAT_MAX) {
DEV_ERR("%s: invalid input\n", __func__);
return NULL;
}
diff --git a/drivers/video/msm/mdss/mdss_hdmi_util.c b/drivers/video/msm/mdss/mdss_hdmi_util.c
index 53dfc71..711ec68 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_util.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_util.c
@@ -123,30 +123,30 @@
return "";
} /* hdmi_get_single_video_3d_fmt_2string */
-ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf)
+ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf, u32 size)
{
ssize_t ret, len = 0;
- ret = snprintf(buf, PAGE_SIZE, "%s",
+ ret = scnprintf(buf, size, "%s",
hdmi_get_single_video_3d_fmt_2string(
format & FRAME_PACKING));
len += ret;
if (len && (format & TOP_AND_BOTTOM))
- ret = snprintf(buf + len, PAGE_SIZE, ":%s",
+ ret = scnprintf(buf + len, size - len, ":%s",
hdmi_get_single_video_3d_fmt_2string(
format & TOP_AND_BOTTOM));
else
- ret = snprintf(buf + len, PAGE_SIZE, "%s",
+ ret = scnprintf(buf + len, size - len, "%s",
hdmi_get_single_video_3d_fmt_2string(
format & TOP_AND_BOTTOM));
len += ret;
if (len && (format & SIDE_BY_SIDE_HALF))
- ret = snprintf(buf + len, PAGE_SIZE, ":%s",
+ ret = scnprintf(buf + len, size - len, ":%s",
hdmi_get_single_video_3d_fmt_2string(
format & SIDE_BY_SIDE_HALF));
else
- ret = snprintf(buf + len, PAGE_SIZE, "%s",
+ ret = scnprintf(buf + len, size - len, "%s",
hdmi_get_single_video_3d_fmt_2string(
format & SIDE_BY_SIDE_HALF));
len += ret;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_util.h b/drivers/video/msm/mdss/mdss_hdmi_util.h
index e99e549..5f7878b 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_util.h
+++ b/drivers/video/msm/mdss/mdss_hdmi_util.h
@@ -256,7 +256,7 @@
int hdmi_get_video_id_code(struct msm_hdmi_mode_timing_info *timing_in);
const struct msm_hdmi_mode_timing_info *hdmi_get_supported_mode(u32 mode);
void hdmi_del_supported_mode(u32 mode);
-ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf);
+ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf, u32 size);
/* todo: Fix this. Right now this is defined in mdss_hdmi_tx.c */
void *hdmi_get_featuredata_from_sysfs_dev(struct device *device, u32 type);
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index 134ffea..f9db498 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -114,6 +114,13 @@
struct mdss_mdp_ctl;
typedef void (*mdp_vsync_handler_t)(struct mdss_mdp_ctl *, ktime_t);
+struct mdss_mdp_img_rect {
+ u16 x;
+ u16 y;
+ u16 w;
+ u16 h;
+};
+
struct mdss_mdp_vsync_handler {
bool enabled;
bool cmd_post_flush;
@@ -165,6 +172,9 @@
struct mdss_panel_data *panel_data;
struct mdss_mdp_vsync_handler vsync_handler;
+ struct mdss_mdp_img_rect roi;
+ u8 roi_changed;
+
int (*start_fnc) (struct mdss_mdp_ctl *ctl);
int (*stop_fnc) (struct mdss_mdp_ctl *ctl);
int (*prepare_fnc) (struct mdss_mdp_ctl *ctl, void *arg);
@@ -191,6 +201,7 @@
u8 params_changed;
u16 width;
u16 height;
+ struct mdss_mdp_img_rect roi;
u8 cursor_enabled;
u8 rotator_mode;
@@ -198,13 +209,6 @@
struct mdss_mdp_pipe *stage_pipe[MDSS_MDP_MAX_STAGE];
};
-struct mdss_mdp_img_rect {
- u16 x;
- u16 y;
- u16 w;
- u16 h;
-};
-
struct mdss_mdp_format_params {
u32 format;
u8 is_yuv;
@@ -460,7 +464,8 @@
int mdss_mdp_video_start(struct mdss_mdp_ctl *ctl);
int mdss_mdp_cmd_start(struct mdss_mdp_ctl *ctl);
int mdss_mdp_writeback_start(struct mdss_mdp_ctl *ctl);
-int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd);
+int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd,
+ struct mdp_display_commit *data);
struct mdss_mdp_ctl *mdss_mdp_ctl_init(struct mdss_panel_data *pdata,
struct msm_fb_data_type *mfd);
@@ -508,33 +513,18 @@
int mdss_hw_init(struct mdss_data_type *mdata);
-int mdss_mdp_pa_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pa_cfg_data *config,
- u32 *copyback);
-int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pcc_cfg_data *cfg_ptr,
- u32 *copyback);
-int mdss_mdp_igc_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_igc_lut_data *config,
- u32 *copyback, u32 copy_from_kernel);
-int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pgc_lut_data *config,
- u32 *copyback);
-int mdss_mdp_hist_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_hist_lut_data *config,
- u32 *copyback);
-int mdss_mdp_dither_config(struct mdss_mdp_ctl *ctl,
- struct mdp_dither_cfg_data *config,
- u32 *copyback);
-int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_gamut_cfg_data *config,
- u32 *copyback);
+int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config, u32 *copyback);
+int mdss_mdp_pcc_config(struct mdp_pcc_cfg_data *cfg_ptr, u32 *copyback);
+int mdss_mdp_igc_lut_config(struct mdp_igc_lut_data *config, u32 *copyback,
+ u32 copy_from_kernel);
+int mdss_mdp_argc_config(struct mdp_pgc_lut_data *config, u32 *copyback);
+int mdss_mdp_hist_lut_config(struct mdp_hist_lut_data *config, u32 *copyback);
+int mdss_mdp_dither_config(struct mdp_dither_cfg_data *config, u32 *copyback);
+int mdss_mdp_gamut_config(struct mdp_gamut_cfg_data *config, u32 *copyback);
-int mdss_mdp_histogram_start(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_start_req *req);
-int mdss_mdp_histogram_stop(struct mdss_mdp_ctl *ctl, u32 block);
-int mdss_mdp_hist_collect(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_data *hist);
+int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req);
+int mdss_mdp_histogram_stop(u32 block);
+int mdss_mdp_hist_collect(struct mdp_histogram_data *hist);
void mdss_mdp_hist_intr_done(u32 isr);
int mdss_mdp_ad_config(struct msm_fb_data_type *mfd,
@@ -583,6 +573,9 @@
int mdss_mdp_get_img(struct msmfb_data *img, struct mdss_mdp_img_data *data);
u32 mdss_get_panel_framerate(struct msm_fb_data_type *mfd);
int mdss_mdp_calc_phase_step(u32 src, u32 dst, u32 *out_phase);
+void mdss_mdp_intersect_rect(struct mdss_mdp_img_rect *res_rect,
+ const struct mdss_mdp_img_rect *dst_rect,
+ const struct mdss_mdp_img_rect *sci_rect);
int mdss_mdp_wb_kickoff(struct msm_fb_data_type *mfd);
int mdss_mdp_wb_ioctl_handler(struct msm_fb_data_type *mfd, u32 cmd, void *arg);
@@ -600,6 +593,8 @@
int mdss_mdp_writeback_display_commit(struct mdss_mdp_ctl *ctl, void *arg);
struct mdss_mdp_ctl *mdss_mdp_ctl_mixer_switch(struct mdss_mdp_ctl *ctl,
u32 return_type);
+void mdss_mdp_set_roi(struct mdss_mdp_ctl *ctl,
+ struct mdp_display_commit *data);
int mdss_mdp_wb_set_format(struct msm_fb_data_type *mfd, int dst_format);
int mdss_mdp_wb_get_format(struct msm_fb_data_type *mfd,
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index bce4248..ec7bc11 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -588,6 +588,11 @@
{
struct mdss_mdp_ctl *ctl;
+ if (!mixer || !mixer->ctl) {
+ pr_err("invalid ctl handle\n");
+ return -ENODEV;
+ }
+
ctl = mixer->ctl;
mixer->rotator_mode = 0;
@@ -716,6 +721,7 @@
ctl->width = width;
ctl->height = height;
+ ctl->roi = (struct mdss_mdp_img_rect) {0, 0, width, height};
if (!ctl->mixer_left) {
ctl->mixer_left =
@@ -734,6 +740,7 @@
ctl->mixer_left->width = width;
ctl->mixer_left->height = height;
+ ctl->mixer_left->roi = (struct mdss_mdp_img_rect) {0, 0, width, height};
if (split_ctl) {
pr_debug("split display detected\n");
@@ -756,6 +763,8 @@
}
ctl->mixer_right->width = width;
ctl->mixer_right->height = height;
+ ctl->mixer_right->roi = (struct mdss_mdp_img_rect)
+ {0, 0, width, height};
} else if (ctl->mixer_right) {
mdss_mdp_mixer_free(ctl->mixer_right);
ctl->mixer_right = NULL;
@@ -906,7 +915,7 @@
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB888;
break;
}
- mdss_mdp_dither_config(ctl, &dither, NULL);
+ mdss_mdp_dither_config(&dither, NULL);
}
return ctl;
@@ -1208,6 +1217,48 @@
return ret;
}
+void mdss_mdp_set_roi(struct mdss_mdp_ctl *ctl,
+ struct mdp_display_commit *data)
+{
+ struct mdss_mdp_img_rect temp_roi, mixer_roi;
+
+ temp_roi.x = data->roi.x;
+ temp_roi.y = data->roi.y;
+ temp_roi.w = data->roi.w;
+ temp_roi.h = data->roi.h;
+
+ /*
+ * No Partial Update for:
+ * 1) dual DSI panels
+ * 2) non-cmd mode panels
+ */
+ if (!temp_roi.w || !temp_roi.h || ctl->mixer_right ||
+ (ctl->panel_data->panel_info.type != MIPI_CMD_PANEL) ||
+ !ctl->panel_data->panel_info.partial_update_enabled) {
+ temp_roi = (struct mdss_mdp_img_rect)
+ {0, 0, ctl->mixer_left->width,
+ ctl->mixer_left->height};
+ }
+
+ ctl->roi_changed = 0;
+ if (((temp_roi.x != ctl->roi.x) ||
+ (temp_roi.y != ctl->roi.y)) ||
+ ((temp_roi.w != ctl->roi.w) ||
+ (temp_roi.h != ctl->roi.h))) {
+ ctl->roi = temp_roi;
+ ctl->roi_changed++;
+
+ mixer_roi = ctl->mixer_left->roi;
+ if ((mixer_roi.w != temp_roi.w) ||
+ (mixer_roi.h != temp_roi.h)) {
+ ctl->mixer_left->roi = temp_roi;
+ ctl->mixer_left->params_changed++;
+ }
+ }
+ pr_debug("ROI requested: [%d, %d, %d, %d]\n",
+ ctl->roi.x, ctl->roi.y, ctl->roi.w, ctl->roi.h);
+}
+
static int mdss_mdp_mixer_setup(struct mdss_mdp_ctl *ctl,
struct mdss_mdp_mixer *mixer)
{
@@ -1217,6 +1268,7 @@
u32 fg_alpha = 0, bg_alpha = 0;
int stage, secure = 0;
int screen_state;
+ int outsize = 0;
screen_state = ctl->force_screen_state;
@@ -1225,6 +1277,9 @@
pr_debug("setup mixer=%d\n", mixer->num);
+ outsize = (mixer->roi.h << 16) | mixer->roi.w;
+ mdp_mixer_write(mixer, MDSS_MDP_REG_LM_OUT_SIZE, outsize);
+
if (screen_state == MDSS_SCREEN_FORCE_BLANK) {
mixercfg = MDSS_MDP_LM_BORDER_COLOR;
goto update_mixer;
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c b/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
index 920c231..addb9b0 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
@@ -428,6 +428,22 @@
return rc;
}
+static int mdss_mdp_cmd_set_partial_roi(struct mdss_mdp_ctl *ctl)
+{
+ int rc = 0;
+ if (ctl->roi.w && ctl->roi.h && ctl->roi_changed &&
+ ctl->panel_data->panel_info.partial_update_enabled) {
+ ctl->panel_data->panel_info.roi_x = ctl->roi.x;
+ ctl->panel_data->panel_info.roi_y = ctl->roi.y;
+ ctl->panel_data->panel_info.roi_w = ctl->roi.w;
+ ctl->panel_data->panel_info.roi_h = ctl->roi.h;
+
+ rc = mdss_mdp_ctl_intf_event(ctl,
+ MDSS_EVENT_ENABLE_PARTIAL_UPDATE, NULL);
+ }
+ return rc;
+}
+
int mdss_mdp_cmd_kickoff(struct mdss_mdp_ctl *ctl, void *arg)
{
struct mdss_mdp_cmd_ctx *ctx;
@@ -450,13 +466,15 @@
WARN(rc, "intf %d panel on error (%d)\n", ctl->intf_num, rc);
}
- mdss_mdp_cmd_clk_on(ctx);
+ mdss_mdp_cmd_set_partial_roi(ctl);
/*
* tx dcs command if had any
*/
mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_DSI_CMDLIST_KOFF, NULL);
+ mdss_mdp_cmd_clk_on(ctx);
+
INIT_COMPLETION(ctx->pp_comp);
mdss_mdp_irq_enable(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num);
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_START, 1);
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_video.c b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
index 8d4ca2b..728269d 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_video.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
@@ -78,11 +78,15 @@
static inline u32 mdss_mdp_video_line_count(struct mdss_mdp_ctl *ctl)
{
- struct mdss_mdp_video_ctx *ctx = ctl->priv_data;
+ struct mdss_mdp_video_ctx *ctx;
u32 line_cnt = 0;
+ if (!ctl || !ctl->priv_data)
+ goto line_count_exit;
+ ctx = ctl->priv_data;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
line_cnt = mdp_video_read(ctx, MDSS_MDP_REG_INTF_LINE_COUNT);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+line_count_exit:
return line_cnt;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 5f0d646..e3e4509 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -547,12 +547,11 @@
pipe->pp_cfg.hist_cfg.frame_cnt;
hist.bit_mask = pipe->pp_cfg.hist_cfg.bit_mask;
hist.num_bins = pipe->pp_cfg.hist_cfg.num_bins;
- mdss_mdp_histogram_start(pipe->mixer->ctl,
- &hist);
+ mdss_mdp_histogram_start(&hist);
} else if (pipe->pp_cfg.hist_cfg.ops &
MDP_PP_OPS_DISABLE) {
- mdss_mdp_histogram_stop(pipe->mixer->ctl,
- pipe->pp_cfg.hist_cfg.block);
+ mdss_mdp_histogram_stop(
+ pipe->pp_cfg.hist_cfg.block);
}
}
len = pipe->pp_cfg.hist_lut_cfg.len;
@@ -826,7 +825,8 @@
activate_event_timer(mdp5_data->cpu_pm_hdl, wakeup_time);
}
-int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd)
+int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd,
+ struct mdp_display_commit *data)
{
struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
struct mdss_mdp_pipe *pipe;
@@ -849,6 +849,9 @@
return ret;
}
+ if (data)
+ mdss_mdp_set_roi(ctl, data);
+
list_for_each_entry(pipe, &mdp5_data->pipes_used, used_list) {
struct mdss_mdp_data *buf;
/*
@@ -1054,7 +1057,7 @@
mutex_unlock(&mdp5_data->ov_lock);
if (cnt)
- mfd->mdp.kickoff_fnc(mfd);
+ mfd->mdp.kickoff_fnc(mfd, NULL);
list_for_each_entry_safe(rot, tmp, &mdp5_data->rot_proc_list, list) {
if (rot->pid == pid) {
@@ -1075,7 +1078,7 @@
if (!mfd)
return -ENODEV;
- ret = mfd->mdp.kickoff_fnc(mfd);
+ ret = mfd->mdp.kickoff_fnc(mfd, NULL);
if (!ret)
pr_err("error displaying\n");
@@ -1097,6 +1100,12 @@
flgs = rot->flags & MDP_SECURE_OVERLAY_SESSION;
+ ret = mdss_mdp_rotator_busy_wait_ex(rot);
+ if (ret) {
+ pr_err("rotator busy wait error\n");
+ return ret;
+ }
+
mdss_mdp_overlay_free_buf(&rot->src_buf);
ret = mdss_mdp_overlay_get_buf(mfd, &rot->src_buf, &req->data, 1, flgs);
if (ret) {
@@ -1112,7 +1121,7 @@
goto dst_buf_fail;
}
- ret = mdss_mdp_rotator_queue(rot, &rot->src_buf, &rot->dst_buf);
+ ret = mdss_mdp_rotator_queue(rot);
if (ret)
pr_err("rotator queue error session id=%x\n", req->id);
@@ -1338,7 +1347,7 @@
if (!fbi->fix.smem_start || fbi->fix.smem_len == 0 ||
mdp5_data->borderfill_enable) {
- mfd->mdp.kickoff_fnc(mfd);
+ mfd->mdp.kickoff_fnc(mfd, NULL);
return;
}
@@ -1412,7 +1421,7 @@
if ((fbi->var.activate & FB_ACTIVATE_VBL) ||
(fbi->var.activate & FB_ACTIVATE_FORCE))
- mfd->mdp.kickoff_fnc(mfd);
+ mfd->mdp.kickoff_fnc(mfd, NULL);
return;
@@ -1812,7 +1821,6 @@
struct msmfb_mdp_pp mdp_pp;
u32 copyback = 0;
u32 copy_from_kernel = 0;
- struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
ret = copy_from_user(&mdp_pp, argp, sizeof(mdp_pp));
if (ret)
@@ -1827,14 +1835,12 @@
switch (mdp_pp.op) {
case mdp_op_pa_cfg:
- ret = mdss_mdp_pa_config(mdp5_data->ctl,
- &mdp_pp.data.pa_cfg_data,
+ ret = mdss_mdp_pa_config(&mdp_pp.data.pa_cfg_data,
©back);
break;
case mdp_op_pcc_cfg:
- ret = mdss_mdp_pcc_config(mdp5_data->ctl,
- &mdp_pp.data.pcc_cfg_data,
+ ret = mdss_mdp_pcc_config(&mdp_pp.data.pcc_cfg_data,
©back);
break;
@@ -1842,7 +1848,6 @@
switch (mdp_pp.data.lut_cfg_data.lut_type) {
case mdp_lut_igc:
ret = mdss_mdp_igc_lut_config(
- mdp5_data->ctl,
(struct mdp_igc_lut_data *)
&mdp_pp.data.lut_cfg_data.data,
©back, copy_from_kernel);
@@ -1850,14 +1855,12 @@
case mdp_lut_pgc:
ret = mdss_mdp_argc_config(
- mdp5_data->ctl,
&mdp_pp.data.lut_cfg_data.data.pgc_lut_data,
©back);
break;
case mdp_lut_hist:
ret = mdss_mdp_hist_lut_config(
- mdp5_data->ctl,
(struct mdp_hist_lut_data *)
&mdp_pp.data.lut_cfg_data.data, ©back);
break;
@@ -1869,13 +1872,11 @@
break;
case mdp_op_dither_cfg:
ret = mdss_mdp_dither_config(
- mdp5_data->ctl,
&mdp_pp.data.dither_cfg_data,
©back);
break;
case mdp_op_gamut_cfg:
ret = mdss_mdp_gamut_config(
- mdp5_data->ctl,
&mdp_pp.data.gamut_cfg_data,
©back);
break;
@@ -1926,7 +1927,6 @@
struct mdp_histogram_data hist;
struct mdp_histogram_start_req hist_req;
u32 block;
- struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
u32 pp_bus_handle;
static int req = -1;
@@ -1945,7 +1945,7 @@
if (ret)
return ret;
- ret = mdss_mdp_histogram_start(mdp5_data->ctl, &hist_req);
+ ret = mdss_mdp_histogram_start(&hist_req);
break;
case MSMFB_HISTOGRAM_STOP:
@@ -1953,7 +1953,7 @@
if (ret)
return ret;
- ret = mdss_mdp_histogram_stop(mdp5_data->ctl, block);
+ ret = mdss_mdp_histogram_stop(block);
if (ret)
return ret;
@@ -1975,7 +1975,7 @@
if (ret)
return ret;
- ret = mdss_mdp_hist_collect(mdp5_data->ctl, &hist);
+ ret = mdss_mdp_hist_collect(&hist);
if (!ret)
ret = copy_to_user(argp, &hist, sizeof(hist));
break;
@@ -2159,9 +2159,9 @@
}
break;
case MSMFB_OVERLAY_COMMIT:
- mdss_fb_wait_for_fence(mfd);
- ret = mfd->mdp.kickoff_fnc(mfd);
- mdss_fb_signal_timeline(mfd);
+ mdss_fb_wait_for_fence(&(mfd->mdp_sync_pt_data));
+ ret = mfd->mdp.kickoff_fnc(mfd, NULL);
+ mdss_fb_signal_timeline(&(mfd->mdp_sync_pt_data));
break;
case MSMFB_METADATA_SET:
ret = copy_from_user(&metadata, argp, sizeof(metadata));
@@ -2236,7 +2236,7 @@
(mfd->panel_info->type != WRITEBACK_PANEL)) {
rc = mdss_mdp_overlay_start(mfd);
if (!IS_ERR_VALUE(rc))
- rc = mdss_mdp_overlay_kickoff(mfd);
+ rc = mdss_mdp_overlay_kickoff(mfd, NULL);
} else {
rc = mdss_mdp_ctl_setup(mdp5_data->ctl);
if (rc)
@@ -2289,7 +2289,7 @@
if (need_cleanup) {
pr_debug("cleaning up pipes on fb%d\n", mfd->index);
- mdss_mdp_overlay_kickoff(mfd);
+ mdss_mdp_overlay_kickoff(mfd, NULL);
}
rc = mdss_mdp_ctl_stop(mdp5_data->ctl);
@@ -2342,6 +2342,7 @@
mdp5_interface->ioctl_handler = mdss_mdp_overlay_ioctl_handler;
mdp5_interface->panel_register_done = mdss_panel_register_done;
mdp5_interface->kickoff_fnc = mdss_mdp_overlay_kickoff;
+ mdp5_interface->get_sync_fnc = mdss_mdp_rotator_sync_pt_get;
mdp5_data = kmalloc(sizeof(struct mdss_overlay_private), GFP_KERNEL);
if (!mdp5_data) {
diff --git a/drivers/video/msm/mdss/mdss_mdp_pipe.c b/drivers/video/msm/mdss/mdss_mdp_pipe.c
index 16ea7dc..79549a1 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pipe.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pipe.c
@@ -481,22 +481,51 @@
}
-static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe)
+void mdss_mdp_crop_rect(struct mdss_mdp_img_rect *src_rect,
+ struct mdss_mdp_img_rect *dst_rect,
+ const struct mdss_mdp_img_rect *sci_rect)
+{
+ struct mdss_mdp_img_rect res;
+ mdss_mdp_intersect_rect(&res, dst_rect, sci_rect);
+
+ if (res.w && res.h) {
+ if ((res.w != dst_rect->w) || (res.h != dst_rect->h)) {
+ src_rect->x = src_rect->x + (res.x - dst_rect->x);
+ src_rect->y = src_rect->y + (res.y - dst_rect->y);
+ src_rect->w = res.w;
+ src_rect->h = res.h;
+ }
+ *dst_rect = (struct mdss_mdp_img_rect)
+ {(res.x - sci_rect->x), (res.y - sci_rect->y),
+ res.w, res.h};
+ }
+}
+
+static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe,
+ struct mdss_mdp_data *data)
{
u32 img_size, src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
u32 width, height;
u32 decimation;
+ struct mdss_mdp_img_rect sci, dst, src;
+ int ret = 0;
pr_debug("pnum=%d wh=%dx%d src={%d,%d,%d,%d} dst={%d,%d,%d,%d}\n",
- pipe->num, pipe->img_width, pipe->img_height,
- pipe->src.x, pipe->src.y, pipe->src.w, pipe->src.h,
- pipe->dst.x, pipe->dst.y, pipe->dst.w, pipe->dst.h);
+ pipe->num, pipe->img_width, pipe->img_height,
+ pipe->src.x, pipe->src.y, pipe->src.w, pipe->src.h,
+ pipe->dst.x, pipe->dst.y, pipe->dst.w, pipe->dst.h);
width = pipe->img_width;
height = pipe->img_height;
mdss_mdp_get_plane_sizes(pipe->src_fmt->format, width, height,
&pipe->src_planes, pipe->bwc_mode);
+ if (data != NULL) {
+ ret = mdss_mdp_data_check(data, &pipe->src_planes);
+ if (ret)
+ return ret;
+ }
+
if ((pipe->flags & MDP_DEINTERLACE) &&
!(pipe->flags & MDP_SOURCE_ROTATED_90)) {
int i;
@@ -512,15 +541,23 @@
pr_debug("Image decimation h=%d v=%d\n",
pipe->horz_deci, pipe->vert_deci);
+ sci = pipe->mixer->ctl->roi;
+ dst = pipe->dst;
+ src = pipe->src;
+
+ mdss_mdp_crop_rect(&src, &dst, &sci);
+
+ src_size = (src.h << 16) | src.w;
+ src_xy = (src.y << 16) | src.x;
+ dst_size = (dst.h << 16) | dst.w;
+ dst_xy = (dst.y << 16) | dst.x;
+
img_size = (height << 16) | width;
- src_size = (pipe->src.h << 16) | pipe->src.w;
- src_xy = (pipe->src.y << 16) | pipe->src.x;
- dst_size = (pipe->dst.h << 16) | pipe->dst.w;
- dst_xy = (pipe->dst.y << 16) | pipe->dst.x;
+
ystride0 = (pipe->src_planes.ystride[0]) |
- (pipe->src_planes.ystride[1] << 16);
+ (pipe->src_planes.ystride[1] << 16);
ystride1 = (pipe->src_planes.ystride[2]) |
- (pipe->src_planes.ystride[3] << 16);
+ (pipe->src_planes.ystride[3] << 16);
if (pipe->overfetch_disable) {
img_size = src_size;
@@ -661,7 +698,7 @@
pr_debug("solid fill setup on pnum=%d\n", pipe->num);
- ret = mdss_mdp_image_setup(pipe);
+ ret = mdss_mdp_image_setup(pipe, NULL);
if (ret) {
pr_err("image setup error for pnum=%d\n", pipe->num);
return ret;
@@ -706,7 +743,8 @@
params_changed = (pipe->params_changed) ||
((pipe->type == MDSS_MDP_PIPE_TYPE_DMA) &&
(pipe->mixer->type == MDSS_MDP_MIXER_TYPE_WRITEBACK)
- && (ctl->mdata->mixer_switched));
+ && (ctl->mdata->mixer_switched)) ||
+ ctl->roi_changed;
if (src_data == NULL) {
mdss_mdp_pipe_solidfill_setup(pipe);
goto update_nobuf;
@@ -721,7 +759,7 @@
goto done;
}
- ret = mdss_mdp_image_setup(pipe);
+ ret = mdss_mdp_image_setup(pipe, src_data);
if (ret) {
pr_err("image setup error for pnum=%d\n", pipe->num);
goto done;
diff --git a/drivers/video/msm/mdss/mdss_mdp_pp.c b/drivers/video/msm/mdss/mdss_mdp_pp.c
index 09b789b..64d0bca 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pp.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pp.c
@@ -1133,7 +1133,7 @@
flush_exit:
writel_relaxed(opmode, basel + MDSS_MDP_REG_DSPP_OP_MODE);
- mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, BIT(13 + dspp_num));
+ ctl->flush_bits |= BIT(13 + dspp_num);
wmb();
dspp_exit:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
@@ -1369,15 +1369,12 @@
return 0;
}
-int mdss_mdp_pa_config(struct mdss_mdp_ctl *ctl, struct mdp_pa_cfg_data *config,
+int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config,
u32 *copyback)
{
int ret = 0;
u32 pa_offset, disp_num, dspp_num = 0;
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1411,8 +1408,6 @@
pa_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
@@ -1542,16 +1537,12 @@
MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rgb_1);
}
-int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pcc_cfg_data *config,
+int mdss_mdp_pcc_config(struct mdp_pcc_cfg_data *config,
u32 *copyback)
{
int ret = 0;
u32 base, disp_num, dspp_num = 0;
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1581,8 +1572,6 @@
pcc_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
@@ -1656,22 +1645,18 @@
config.c0_c1_data = igc_limited;
config.c2_data = igc_limited;
- ret = mdss_mdp_igc_lut_config(ctl, &config, ©back,
+ ret = mdss_mdp_igc_lut_config(&config, ©back,
copy_from_kernel);
return ret;
}
-int mdss_mdp_igc_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_igc_lut_data *config,
+int mdss_mdp_igc_lut_config(struct mdp_igc_lut_data *config,
u32 *copyback, u32 copy_from_kernel)
{
int ret = 0;
u32 tbl_idx, igc_offset, disp_num, dspp_num = 0;
struct mdp_igc_lut_data local_cfg;
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1748,8 +1733,6 @@
igc_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
static void pp_update_gc_one_lut(u32 offset,
@@ -1864,8 +1847,7 @@
writel_relaxed(1, offset + 16);
}
-int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pgc_lut_data *config,
+int mdss_mdp_argc_config(struct mdp_pgc_lut_data *config,
u32 *copyback)
{
int ret = 0;
@@ -1874,9 +1856,6 @@
struct mdp_pgc_lut_data *pgc_ptr;
u32 tbl_size, r_size, g_size, b_size;
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(config->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(config->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1986,20 +1965,14 @@
}
argc_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
-int mdss_mdp_hist_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_hist_lut_data *config,
+int mdss_mdp_hist_lut_config(struct mdp_hist_lut_data *config,
u32 *copyback)
{
int i, ret = 0;
u32 hist_offset, disp_num, dspp_num = 0;
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(config->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(config->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2043,18 +2016,13 @@
}
enhist_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
-int mdss_mdp_dither_config(struct mdss_mdp_ctl *ctl,
- struct mdp_dither_cfg_data *config,
+int mdss_mdp_dither_config(struct mdp_dither_cfg_data *config,
u32 *copyback)
{
u32 disp_num;
- if (!ctl)
- return -EINVAL;
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
@@ -2067,12 +2035,10 @@
mdss_pp_res->dither_disp_cfg[disp_num] = *config;
mdss_pp_res->pp_disp_flags[disp_num] |= PP_FLAGS_DIRTY_DITHER;
mutex_unlock(&mdss_pp_mutex);
- mdss_mdp_pp_setup(ctl);
return 0;
}
-int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_gamut_cfg_data *config,
+int mdss_mdp_gamut_config(struct mdp_gamut_cfg_data *config,
u32 *copyback)
{
int i, j, size_total = 0, ret = 0;
@@ -2084,9 +2050,6 @@
uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2209,8 +2172,6 @@
}
gamut_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
static void pp_hist_read(char __iomem *v_base,
@@ -2253,7 +2214,7 @@
hist_info->col_state = HIST_RESET;
hist_info->col_en = true;
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
- hist_info->is_kick_ready = false;
+ hist_info->is_kick_ready = true;
mdss_mdp_hist_irq_enable(3 << shift_bit);
writel_relaxed(req->frame_cnt, ctl_base + 8);
/* Kick out reset start */
@@ -2263,8 +2224,7 @@
return ret;
}
-int mdss_mdp_histogram_start(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_start_req *req)
+int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req)
{
u32 done_shift_bit;
char __iomem *ctl_base;
@@ -2274,8 +2234,6 @@
u32 mixer_cnt, mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- if (!ctl)
- return -EINVAL;
if ((PP_BLOCK(req->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(req->block) >= MDP_BLOCK_MAX))
@@ -2342,31 +2300,6 @@
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
hist_exit:
- if (!ret && (PP_LOCAT(req->block) == MDSS_PP_DSPP_CFG)) {
- mdss_mdp_pp_setup(ctl);
- /* wait for a frame to let histrogram enable itself */
- /* TODO add hysteresis value to be able to remove this sleep */
- usleep(41666);
- for (i = 0; i < mixer_cnt; i++) {
- dspp_num = mixer_id[i];
- hist_info = &mdss_pp_res->dspp_hist[dspp_num];
- mutex_lock(&hist_info->hist_mutex);
- hist_info->is_kick_ready = true;
- mutex_unlock(&hist_info->hist_mutex);
- }
- } else if (!ret) {
- for (i = 0; i < MDSS_PP_ARG_NUM; i++) {
- if (!PP_ARG(i, req->block))
- continue;
- pr_info("PP_ARG(%d) = %d", i, PP_ARG(i, req->block));
- pipe = mdss_mdp_pipe_get(mdata, BIT(i));
- if (IS_ERR_OR_NULL(pipe))
- continue;
- hist_info = &pipe->pp_res.hist;
- hist_info->is_kick_ready = true;
- mdss_mdp_pipe_unmap(pipe);
- }
- }
return ret;
}
@@ -2395,7 +2328,7 @@
return ret;
}
-int mdss_mdp_histogram_stop(struct mdss_mdp_ctl *ctl, u32 block)
+int mdss_mdp_histogram_stop(u32 block)
{
int i, ret = 0;
char __iomem *ctl_base;
@@ -2405,9 +2338,6 @@
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2472,13 +2402,10 @@
hist_stop_clk:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
hist_stop_exit:
- if (!ret && (PP_LOCAT(block) == MDSS_PP_DSPP_CFG))
- mdss_mdp_pp_setup(ctl);
return ret;
}
-static int pp_hist_collect(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_data *hist,
+static int pp_hist_collect(struct mdp_histogram_data *hist,
struct pp_hist_col_info *hist_info,
char __iomem *ctl_base)
{
@@ -2502,9 +2429,6 @@
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
timeout = HIST_WAIT_TIMEOUT(hist_info->frame_cnt);
mutex_unlock(&hist_info->hist_mutex);
- /* flush updates before wait*/
- if (PP_LOCAT(hist->block) == MDSS_PP_DSPP_CFG)
- mdss_mdp_pp_setup(ctl);
if (PP_LOCAT(hist->block) == MDSS_PP_SSPP_CFG) {
res = container_of(hist_info, struct mdss_pipe_pp_res,
hist);
@@ -2565,8 +2489,7 @@
return ret;
}
-int mdss_mdp_hist_collect(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_data *hist)
+int mdss_mdp_hist_collect(struct mdp_histogram_data *hist)
{
int i, j, off, ret = 0;
struct pp_hist_col_info *hist_info;
@@ -2580,9 +2503,6 @@
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(hist->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(hist->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2609,7 +2529,7 @@
hist_info = &mdss_pp_res->dspp_hist[dspp_num];
ctl_base = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_HIST_CTL_BASE;
- ret = pp_hist_collect(ctl, hist, hist_info, ctl_base);
+ ret = pp_hist_collect(hist, hist_info, ctl_base);
if (ret)
goto hist_collect_exit;
}
@@ -2678,7 +2598,7 @@
hist_info = &pipe->pp_res.hist;
ctl_base = pipe->base +
MDSS_MDP_REG_VIG_HIST_CTL_BASE;
- ret = pp_hist_collect(ctl, hist, hist_info, ctl_base);
+ ret = pp_hist_collect(hist, hist_info, ctl_base);
mdss_mdp_pipe_unmap(pipe);
if (ret)
goto hist_collect_exit;
@@ -2971,8 +2891,6 @@
}
mutex_unlock(&ad->lock);
ctl = mfd_to_ctl(mfd);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
@@ -2980,7 +2898,6 @@
struct mdss_ad_input *input, int wait) {
int ret = 0;
struct mdss_ad_info *ad;
- struct mdss_mdp_ctl *ctl;
u32 bl;
ret = mdss_mdp_get_ad(mfd, &ad);
@@ -3056,8 +2973,6 @@
init_completion(&ad->comp);
mutex_unlock(&ad->lock);
}
- ctl = mfd_to_ctl(mfd);
- mdss_mdp_pp_setup(ctl);
if (wait) {
ret = wait_for_completion_interruptible_timeout(
&ad->comp, HIST_WAIT_TIMEOUT(1));
@@ -3415,7 +3330,7 @@
}
mutex_unlock(&ad->lock);
mutex_lock(&mfd->lock);
- mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, BIT(13 + ad->num));
+ ctl->flush_bits |= BIT(13 + ad->num);
mutex_unlock(&mfd->lock);
/* Trigger update notify to wake up those waiting for display updates */
diff --git a/drivers/video/msm/mdss/mdss_mdp_rotator.c b/drivers/video/msm/mdss/mdss_mdp_rotator.c
index 8381c5b..44734f8 100644
--- a/drivers/video/msm/mdss/mdss_mdp_rotator.c
+++ b/drivers/video/msm/mdss/mdss_mdp_rotator.c
@@ -17,9 +17,12 @@
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/types.h>
+#include <linux/sync.h>
+#include <linux/sw_sync.h>
#include "mdss_mdp.h"
#include "mdss_mdp_rotator.h"
+#include "mdss_fb.h"
#define MAX_ROTATOR_SESSIONS 8
@@ -28,6 +31,11 @@
static LIST_HEAD(rotator_queue);
static int mdss_mdp_rotator_finish(struct mdss_mdp_rotator_session *rot);
+static void mdss_mdp_rotator_commit_wq_handler(struct work_struct *work);
+static int mdss_mdp_rotator_busy_wait(struct mdss_mdp_rotator_session *rot);
+static int mdss_mdp_rotator_queue_helper(struct mdss_mdp_rotator_session *rot);
+static struct msm_sync_pt_data *mdss_mdp_rotator_sync_pt_create(
+ struct mdss_mdp_rotator_session *rot);
struct mdss_mdp_rotator_session *mdss_mdp_rotator_session_alloc(void)
{
@@ -67,6 +75,22 @@
return NULL;
}
+struct msm_sync_pt_data *mdss_mdp_rotator_sync_pt_get(
+ struct msm_fb_data_type *mfd, const struct mdp_buf_sync *buf_sync)
+{
+ struct mdss_mdp_rotator_session *rot;
+
+ rot = mdss_mdp_rotator_session_get(buf_sync->session_id);
+ if (!rot)
+ return NULL;
+ if (!rot->rot_sync_pt_data)
+ rot->rot_sync_pt_data = mdss_mdp_rotator_sync_pt_create(rot);
+ if (rot->rot_sync_pt_data)
+ rot->use_sync_pt = true;
+
+ return rot->rot_sync_pt_data;
+}
+
static struct mdss_mdp_pipe *mdss_mdp_rotator_pipe_alloc(void)
{
struct mdss_mdp_mixer *mixer;
@@ -246,21 +270,84 @@
return ret;
}
-int mdss_mdp_rotator_queue(struct mdss_mdp_rotator_session *rot,
- struct mdss_mdp_data *src_data,
- struct mdss_mdp_data *dst_data)
+static void mdss_mdp_rotator_commit_wq_handler(struct work_struct *work)
+{
+ struct mdss_mdp_rotator_session *rot;
+ int ret;
+
+ rot = container_of(work, struct mdss_mdp_rotator_session, commit_work);
+ ret = mdss_mdp_rotator_queue_helper(rot);
+
+ if (ret) {
+ pr_err("rotator queue failed\n");
+ return;
+ }
+
+ if (rot->rot_sync_pt_data)
+ mdss_fb_signal_timeline(rot->rot_sync_pt_data);
+ else
+ pr_err("rot_sync_pt_data is NULL\n");
+}
+
+static struct msm_sync_pt_data *mdss_mdp_rotator_sync_pt_create(
+ struct mdss_mdp_rotator_session *rot)
+{
+ struct msm_sync_pt_data *sync_pt_data;
+ char timeline_name[16];
+
+ rot->rot_sync_pt_data = kzalloc(
+ sizeof(struct msm_sync_pt_data), GFP_KERNEL);
+ sync_pt_data = rot->rot_sync_pt_data;
+ if (!sync_pt_data)
+ return NULL;
+ sync_pt_data->fence_name = "rot-fence";
+ sync_pt_data->threshold = 1;
+ snprintf(timeline_name, sizeof(timeline_name),
+ "mdss_rot_%d", rot->session_id);
+ sync_pt_data->timeline = sw_sync_timeline_create(timeline_name);
+ if (sync_pt_data->timeline == NULL) {
+ kfree(rot->rot_sync_pt_data);
+ pr_err("%s: cannot create time line", __func__);
+ return NULL;
+ } else {
+ sync_pt_data->timeline_value = 0;
+ }
+ INIT_WORK(&rot->commit_work,
+ mdss_mdp_rotator_commit_wq_handler);
+ mutex_init(&sync_pt_data->sync_mutex);
+ return sync_pt_data;
+}
+
+int mdss_mdp_rotator_busy_wait_ex(struct mdss_mdp_rotator_session *rot)
+{
+
+ struct mdss_mdp_rotator_session *tmp;
+
+ for (tmp = rot; tmp; tmp = tmp->next)
+ mdss_mdp_rotator_busy_wait(tmp);
+
+ if (rot->use_sync_pt)
+ mdss_fb_wait_for_fence(rot->rot_sync_pt_data);
+
+ return 0;
+}
+
+static int mdss_mdp_rotator_queue_helper(struct mdss_mdp_rotator_session *rot)
{
int ret;
- struct mdss_mdp_rotator_session *tmp = rot;
+ struct mdss_mdp_rotator_session *tmp;
ret = mutex_lock_interruptible(&rotator_lock);
- if (ret)
+ if (ret) {
+ pr_err("mutex lock on rotator_lock failed\n");
return ret;
+ }
pr_debug("rotator session=%x start\n", rot->session_id);
for (ret = 0, tmp = rot; ret == 0 && tmp; tmp = tmp->next)
- ret = mdss_mdp_rotator_queue_sub(tmp, src_data, dst_data);
+ ret = mdss_mdp_rotator_queue_sub(tmp,
+ &rot->src_buf, &rot->dst_buf);
mutex_unlock(&rotator_lock);
@@ -272,6 +359,18 @@
for (tmp = rot; tmp; tmp = tmp->next)
mdss_mdp_rotator_busy_wait(tmp);
+ return ret;
+}
+
+int mdss_mdp_rotator_queue(struct mdss_mdp_rotator_session *rot)
+{
+ int ret = 0;
+
+ if (rot->use_sync_pt)
+ schedule_work(&rot->commit_work);
+ else
+ ret = mdss_mdp_rotator_queue_helper(rot);
+
pr_debug("rotator session=%x queue done\n", rot->session_id);
return ret;
@@ -370,6 +469,8 @@
struct mdss_mdp_pipe *rot_pipe;
struct mdss_mdp_ctl *tmp;
int ret = 0;
+ struct msm_sync_pt_data *rot_sync_pt_data;
+ struct work_struct commit_work;
if (!rot)
return -ENODEV;
@@ -384,7 +485,13 @@
mdss_mdp_rotator_busy_wait(rot);
list_del(&rot->head);
}
+
+ rot_sync_pt_data = rot->rot_sync_pt_data;
+ commit_work = rot->commit_work;
memset(rot, 0, sizeof(*rot));
+ rot->rot_sync_pt_data = rot_sync_pt_data;
+ rot->commit_work = commit_work;
+
if (rot_pipe) {
struct mdss_mdp_mixer *mixer = rot_pipe->mixer;
mdss_mdp_pipe_unmap(rot_pipe);
diff --git a/drivers/video/msm/mdss/mdss_mdp_rotator.h b/drivers/video/msm/mdss/mdss_mdp_rotator.h
index 74eeeeb..43e77cc 100644
--- a/drivers/video/msm/mdss/mdss_mdp_rotator.h
+++ b/drivers/video/msm/mdss/mdss_mdp_rotator.h
@@ -43,9 +43,12 @@
struct mdss_mdp_data src_buf;
struct mdss_mdp_data dst_buf;
+ bool use_sync_pt;
struct list_head head;
struct list_head list;
struct mdss_mdp_rotator_session *next;
+ struct msm_sync_pt_data *rot_sync_pt_data;
+ struct work_struct commit_work;
};
static inline u32 mdss_mdp_get_rotator_dst_format(u32 in_format)
@@ -68,11 +71,10 @@
struct mdss_mdp_rotator_session *mdss_mdp_rotator_session_get(u32 session_id);
int mdss_mdp_rotator_setup(struct mdss_mdp_rotator_session *rot);
-int mdss_mdp_rotator_queue(struct mdss_mdp_rotator_session *rot,
- struct mdss_mdp_data *src_data,
- struct mdss_mdp_data *dst_data);
-
+int mdss_mdp_rotator_queue(struct mdss_mdp_rotator_session *rot);
int mdss_mdp_rotator_release(struct mdss_mdp_rotator_session *rot);
int mdss_mdp_rotator_release_all(void);
-
+int mdss_mdp_rotator_busy_wait_ex(struct mdss_mdp_rotator_session *rot);
+struct msm_sync_pt_data *mdss_mdp_rotator_sync_pt_get(
+ struct msm_fb_data_type *mfd, const struct mdp_buf_sync *buf_sync);
#endif /* MDSS_MDP_ROTATOR_H */
diff --git a/drivers/video/msm/mdss/mdss_mdp_util.c b/drivers/video/msm/mdss/mdss_mdp_util.c
index b65d894..1170d1e 100644
--- a/drivers/video/msm/mdss/mdss_mdp_util.c
+++ b/drivers/video/msm/mdss/mdss_mdp_util.c
@@ -237,6 +237,20 @@
return NULL;
}
+void mdss_mdp_intersect_rect(struct mdss_mdp_img_rect *res_rect,
+ const struct mdss_mdp_img_rect *dst_rect,
+ const struct mdss_mdp_img_rect *sci_rect)
+{
+ int l = max(dst_rect->x, sci_rect->x);
+ int t = max(dst_rect->y, sci_rect->y);
+ int r = min((dst_rect->x + dst_rect->w), (sci_rect->x + sci_rect->w));
+ int b = min((dst_rect->y + dst_rect->h), (sci_rect->y + sci_rect->h));
+
+ if (r < l || b < t)
+ *res_rect = (struct mdss_mdp_img_rect){0, 0, 0, 0};
+ else
+ *res_rect = (struct mdss_mdp_img_rect){l, t, (r-l), (b-t)};
+}
int mdss_mdp_get_rau_strides(u32 w, u32 h,
struct mdss_mdp_format_params *fmt,
struct mdss_mdp_plane_sizes *ps)
diff --git a/drivers/video/msm/mdss/mdss_panel.h b/drivers/video/msm/mdss/mdss_panel.h
index c7a219b..25f1e7c 100644
--- a/drivers/video/msm/mdss/mdss_panel.h
+++ b/drivers/video/msm/mdss/mdss_panel.h
@@ -24,6 +24,7 @@
};
#define DEFAULT_FRAME_RATE 60
+#define MDSS_DSI_RST_SEQ_LEN 10
/* panel type list */
#define NO_PANEL 0xffff /* No Panel */
@@ -120,6 +121,7 @@
- 0 clock disable
- 1 clock enable
* @MDSS_EVENT_DSI_CMDLIST_KOFF: kickoff sending dcs command from command list
+ * @MDSS_EVENT_ENABLE_PARTIAL_UPDATE: Event to update ROI of the panel.
*/
enum mdss_intf_events {
MDSS_EVENT_RESET = 1,
@@ -137,6 +139,7 @@
MDSS_EVENT_FB_REGISTERED,
MDSS_EVENT_PANEL_CLK_CTRL,
MDSS_EVENT_DSI_CMDLIST_KOFF,
+ MDSS_EVENT_ENABLE_PARTIAL_UPDATE,
};
struct lcd_panel_info {
@@ -270,7 +273,13 @@
u32 frame_count;
u32 is_3d_panel;
u32 out_format;
+ u32 rst_seq[MDSS_DSI_RST_SEQ_LEN];
+ u32 rst_seq_len;
u32 vic; /* video identification code */
+ u32 roi_x;
+ u32 roi_y;
+ u32 roi_w;
+ u32 roi_h;
int bklt_ctrl; /* backlight ctrl */
int pwm_pmic_gpio;
int pwm_lpg_chan;
@@ -281,6 +290,7 @@
int new_fps;
u32 cont_splash_enabled;
+ u32 partial_update_enabled;
struct ion_handle *splash_ihdl;
u32 panel_power_on;
diff --git a/include/linux/input/ft5x06_ts.h b/include/linux/input/ft5x06_ts.h
index 149133e..7b84534 100644
--- a/include/linux/input/ft5x06_ts.h
+++ b/include/linux/input/ft5x06_ts.h
@@ -58,6 +58,7 @@
bool fw_vkey_support;
bool no_force_update;
bool i2c_pull_up;
+ bool ignore_id_check;
int (*power_init) (bool);
int (*power_on) (bool);
};
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index baa9d6c..077b204 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -838,6 +838,7 @@
struct mdp_buf_sync {
uint32_t flags;
uint32_t acq_fen_fd_cnt;
+ uint32_t session_id;
int *acq_fen_fd;
int *rel_fen_fd;
};
@@ -862,6 +863,7 @@
uint32_t wait_for_finish;
struct fb_var_screeninfo var;
struct mdp_buf_fence buf_fence;
+ struct mdp_rect roi;
};
struct mdp_page_protection {
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 84c59dc..d950b5c 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -154,6 +154,7 @@
KERN_NMI_WATCHDOG=75, /* int: enable/disable nmi watchdog */
KERN_PANIC_ON_NMI=76, /* int: whether we will panic on an unrecovered */
KERN_BOOT_REASON = 77, /* int: identify reason system was booted */
+ KERN_COLD_BOOT = 78, /* int: identify if system cold booted */
};
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index b390dad..d16a59ec 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -1009,7 +1009,15 @@
.maxlen = sizeof(int),
.mode = 0444,
.proc_handler = proc_dointvec,
-},
+ },
+
+ {
+ .procname = "cold_boot",
+ .data = &cold_boot,
+ .maxlen = sizeof(int),
+ .mode = 0444,
+ .proc_handler = proc_dointvec,
+ },
#endif
/*
* NOTE: do not add new entries to this table unless you have read
diff --git a/kernel/sysctl_binary.c b/kernel/sysctl_binary.c
index acb60be..6170f45 100644
--- a/kernel/sysctl_binary.c
+++ b/kernel/sysctl_binary.c
@@ -138,6 +138,7 @@
{ CTL_INT, KERN_MAX_LOCK_DEPTH, "max_lock_depth" },
{ CTL_INT, KERN_PANIC_ON_NMI, "panic_on_unrecovered_nmi" },
{ CTL_INT, KERN_BOOT_REASON, "boot_reason" },
+ { CTL_INT, KERN_COLD_BOOT, "cold_boot" },
{}
};
diff --git a/mm/debug-pagealloc.c b/mm/debug-pagealloc.c
index 789ff70..bc91cba 100644
--- a/mm/debug-pagealloc.c
+++ b/mm/debug-pagealloc.c
@@ -69,6 +69,7 @@
print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 16, 1, start,
end - start + 1, 1);
+ BUG_ON(PANIC_CORRUPTION);
dump_stack();
}
diff --git a/net/caif/caif_socket.c b/net/caif/caif_socket.c
index 5016fa5..c2b18e6 100644
--- a/net/caif/caif_socket.c
+++ b/net/caif/caif_socket.c
@@ -1014,7 +1014,7 @@
caif_assert(sk_unhashed(sk));
caif_assert(!sk->sk_socket);
if (!sock_flag(sk, SOCK_DEAD)) {
- pr_debug("Attempt to release alive CAIF socket: %p\n", sk);
+ WARN(1, "Attempt to release alive CAIF socket: %p\n", sk);
return;
}
sk_stream_kill_queues(&cf_sk->sk);
diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c
index 0b71165..f20b5cc 100644
--- a/net/ipv4/af_inet.c
+++ b/net/ipv4/af_inet.c
@@ -154,12 +154,12 @@
sk_mem_reclaim(sk);
if (sk->sk_type == SOCK_STREAM && sk->sk_state != TCP_CLOSE) {
- pr_err("Attempt to release TCP socket in state %d %p\n",
+ WARN(1, "Attempt to release TCP socket in state %d %p\n",
sk->sk_state, sk);
return;
}
if (!sock_flag(sk, SOCK_DEAD)) {
- pr_err("Attempt to release alive inet socket %p\n", sk);
+ WARN(1, "Attempt to release alive inet socket %p\n", sk);
return;
}
diff --git a/net/iucv/af_iucv.c b/net/iucv/af_iucv.c
index 07d7d55..433f7f7 100644
--- a/net/iucv/af_iucv.c
+++ b/net/iucv/af_iucv.c
@@ -408,7 +408,7 @@
sk_mem_reclaim(sk);
if (!sock_flag(sk, SOCK_DEAD)) {
- pr_err("Attempt to release alive iucv socket %p\n", sk);
+ WARN(1, "Attempt to release alive iucv socket %p\n", sk);
return;
}
diff --git a/net/key/af_key.c b/net/key/af_key.c
index 7e5d927..153fbf1 100644
--- a/net/key/af_key.c
+++ b/net/key/af_key.c
@@ -99,7 +99,7 @@
skb_queue_purge(&sk->sk_receive_queue);
if (!sock_flag(sk, SOCK_DEAD)) {
- pr_err("Attempt to release alive pfkey socket: %p\n", sk);
+ WARN(1, "Attempt to release alive pfkey socket: %p\n", sk);
return;
}
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index 4f2c0df..a72cd66 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -1168,7 +1168,7 @@
WARN_ON(atomic_read(&sk->sk_wmem_alloc));
if (!sock_flag(sk, SOCK_DEAD)) {
- pr_err("Attempt to release alive packet socket: %p\n", sk);
+ WARN(1, "Attempt to release alive packet socket: %p\n", sk);
return;
}
diff --git a/net/rxrpc/af_rxrpc.c b/net/rxrpc/af_rxrpc.c
index 74c064c..798ea39 100644
--- a/net/rxrpc/af_rxrpc.c
+++ b/net/rxrpc/af_rxrpc.c
@@ -670,7 +670,7 @@
WARN_ON(sk->sk_socket);
if (!sock_flag(sk, SOCK_DEAD)) {
- printk("Attempt to release alive rxrpc socket: %p\n", sk);
+ WARN(1, "Attempt to release alive rxrpc socket: %p\n", sk);
return;
}
}
diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
index 109e30b..2a89d01 100644
--- a/net/unix/af_unix.c
+++ b/net/unix/af_unix.c
@@ -357,7 +357,7 @@
WARN_ON(!sk_unhashed(sk));
WARN_ON(sk->sk_socket);
if (!sock_flag(sk, SOCK_DEAD)) {
- printk(KERN_INFO "Attempt to release alive unix socket: %p\n", sk);
+ WARN(1, "Attempt to release alive unix socket: %p\n", sk);
return;
}
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
index 4e07d7f..577c1ed 100644
--- a/sound/soc/codecs/wcd9306.c
+++ b/sound/soc/codecs/wcd9306.c
@@ -1063,6 +1063,25 @@
static const struct snd_kcontrol_new class_h_dsm_mux =
SOC_DAPM_ENUM("CLASS_H_DSM MUX Mux", class_h_dsm_enum);
+static int tapan_hph_impedance_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ uint32_t zl, zr;
+ bool hphr;
+ struct soc_multi_mixer_control *mc;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct tapan_priv *priv = snd_soc_codec_get_drvdata(codec);
+
+ mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+
+ hphr = mc->shift;
+ wcd9xxx_mbhc_get_impedance(&priv->mbhc, &zl, &zr);
+ pr_debug("%s: zl %u, zr %u\n", __func__, zl, zr);
+ ucontrol->value.integer.value[0] = hphr ? zr : zl;
+
+ return 0;
+}
+
static const struct snd_kcontrol_new tapan_common_snd_controls[] = {
SOC_ENUM_EXT("EAR PA Gain", tapan_ear_pa_gain_enum[0],
@@ -1165,6 +1184,11 @@
tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+
+ SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
+ tapan_hph_impedance_get, NULL),
+ SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
+ tapan_hph_impedance_get, NULL),
};
static const struct snd_kcontrol_new tapan_9306_snd_controls[] = {
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index c2d626b..88f46fa 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -125,6 +125,11 @@
#define WCD9XXX_MB_MEAS_DELTA_MAX_MV 80
#define WCD9XXX_CS_MEAS_DELTA_MAX_MV 10
+static int impedance_detect_en;
+module_param(impedance_detect_en, int,
+ S_IRUGO | S_IWUSR | S_IWGRP);
+MODULE_PARM_DESC(impedance_detect_en, "enable/disable impedance detect");
+
static bool detect_use_vddio_switch = true;
struct wcd9xxx_mbhc_detect {
@@ -863,7 +868,7 @@
mbhc->micbias_enable_cb(mbhc->codec, true);
}
- if (mbhc->impedance_detect)
+ if (mbhc->impedance_detect && impedance_detect_en)
wcd9xxx_detect_impedance(mbhc, &mbhc->zl, &mbhc->zr);
pr_debug("%s: Reporting insertion %d(%x)\n", __func__,
@@ -1077,6 +1082,18 @@
mbhc->mbhc_cb->enable_mb_source(codec, true);
/*
+ * setup internal micbias if codec uses internal micbias for
+ * headset detection
+ */
+ if (mbhc->mbhc_cfg->use_int_rbias) {
+ if (mbhc->mbhc_cb && mbhc->mbhc_cb->setup_int_rbias)
+ mbhc->mbhc_cb->setup_int_rbias(codec, true);
+ else
+ pr_err("%s: internal bias is requested but codec did not provide callback\n",
+ __func__);
+ }
+
+ /*
* Request BG and clock.
* These will be released by wcd9xxx_cleanup_hs_polling
*/
@@ -1406,7 +1423,7 @@
(dgnd->_vdces + WCD9XXX_CS_GM_SWAP_THRES_MAX_MV >
maxv))
type = PLUG_TYPE_GND_MIC_SWAP;
- else if (dgnd->_type != PLUG_TYPE_HEADSET) {
+ else if (dgnd->_type != PLUG_TYPE_HEADSET && !dmicbias) {
pr_debug("%s: Invalid, inconsistent types\n", __func__);
type = PLUG_TYPE_INVALID;
}
@@ -2257,8 +2274,11 @@
usleep_range(generic->t_shutdown_plug_rem,
generic->t_shutdown_plug_rem);
- cs_enable = ((mbhc->mbhc_cfg->cs_enable_flags &
- (1 << MBHC_CS_ENABLE_REMOVAL)) != 0);
+ /* If micbias is enabled, don't enable current source */
+ cs_enable = (((mbhc->mbhc_cfg->cs_enable_flags &
+ (1 << MBHC_CS_ENABLE_REMOVAL)) != 0) &&
+ (!(snd_soc_read(codec,
+ mbhc->mbhc_bias_regs.ctl_reg) & 0x80)));
if (cs_enable)
wcd9xxx_turn_onoff_current_source(mbhc, true, false);
@@ -3030,13 +3050,14 @@
change = snd_soc_update_bits(codec, WCD9XXX_A_MAD_ANA_CTRL, 1 << 4,
1 << 0);
usleep_range(1000, 1000 + 1000);
- if (sta_z)
+ if (sta_z) {
*sta_z = wcd9xxx_codec_sta_dce(mbhc, 0, false);
- if (dce_z)
+ pr_debug("%s: sta_z 0x%x\n", __func__, *sta_z & 0xFFFF);
+ }
+ if (dce_z) {
*dce_z = wcd9xxx_codec_sta_dce(mbhc, 1, false);
-
- pr_debug("%s: sta_z 0x%x, dce_z 0x%x\n", __func__, *sta_z & 0xFFFF,
- *dce_z & 0xFFFF);
+ pr_debug("%s: dce_z 0x%x\n", __func__, *dce_z & 0xFFFF);
+ }
/* Connect override from micbias */
if (change)
@@ -4450,6 +4471,7 @@
mbhc->rco_clk_rate = rco_clk_rate;
mbhc->mbhc_cb = mbhc_cb;
mbhc->impedance_detect = impedance_det_en;
+ impedance_detect_en = impedance_det_en ? 1 : 0;
if (mbhc->headset_jack.jack == NULL) {
ret = snd_soc_jack_new(codec, "Headset Jack", WCD9XXX_JACK_MASK,
diff --git a/sound/soc/codecs/wcd9xxx-resmgr.c b/sound/soc/codecs/wcd9xxx-resmgr.c
index 95244c0..cb76342 100644
--- a/sound/soc/codecs/wcd9xxx-resmgr.c
+++ b/sound/soc/codecs/wcd9xxx-resmgr.c
@@ -199,12 +199,17 @@
usleep_range(50, 50);
}
/* Notify */
- if (resmgr->clk_type == WCD9XXX_CLK_RCO)
+ if (resmgr->clk_type == WCD9XXX_CLK_RCO) {
wcd9xxx_resmgr_notifier_call(resmgr,
WCD9XXX_EVENT_POST_RCO_OFF);
- else
+ } else {
+ if (resmgr->codec_type == WCD9XXX_CDC_TYPE_HELICON)
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
+
wcd9xxx_resmgr_notifier_call(resmgr,
WCD9XXX_EVENT_POST_MCLK_OFF);
+ }
pr_debug("%s: leave\n", __func__);
}
diff --git a/sound/soc/msm/msm8x10.c b/sound/soc/msm/msm8x10.c
index 4b61db6..c318849 100644
--- a/sound/soc/msm/msm8x10.c
+++ b/sound/soc/msm/msm8x10.c
@@ -29,6 +29,7 @@
#include <qdsp6v2/msm-pcm-routing-v2.h>
#include <sound/q6afe-v2.h>
#include <linux/module.h>
+#include <mach/gpiomux.h>
#include "../codecs/msm8x10-wcd.h"
#define DRV_NAME "msm8x10-asoc-wcd"
#define BTSCO_RATE_8KHZ 8000
@@ -186,6 +187,10 @@
static int msm_config_mclk(u16 port_id, struct afe_digital_clk_cfg *cfg)
{
+ /* set the drive strength on the clock */
+ msm_tlmm_misc_reg_write(TLMM_CDC_HDRV_CTL, 0x00);
+ msm_tlmm_misc_reg_write(TLMM_CDC_HDRV_PULL_CTL, 0x0006db6d);
+
iowrite32(0x1, pcbcr);
/* Set the update bit to make the settings go through */
iowrite32(0x1, prcgr);
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-lpa-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-lpa-v2.c
index caf77ee..c80d2a3 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-lpa-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-lpa-v2.c
@@ -290,6 +290,7 @@
struct output_meta_data_st output_meta_data;
pr_debug("%s: restart\n", __func__);
+ memset(&output_meta_data, 0x0, sizeof(struct output_meta_data_st));
if (runtime->render_flag & SNDRV_RENDER_STOPPED) {
buf = prtd->audio_client->port[IN].buf;
pr_debug("%s:writing %d bytes of buffer[%d] to dsp 2\n",