commit e01402b115cccb6357f956649487aca2c6f7fbba
author Ralf Baechle <ralf@linux-mips.org> Thu Jul 14 15:57:16 2005 +0000
committer Ralf Baechle <ralf@linux-mips.org> Sat Oct 29 19:31:53 2005 +0100
tree 256e14f8d2762de98b992219b1a47e8f56b4b0da
parent 86071b637db7baf599df26fdf820dce2fc55ca9f

More AP / SP bits for the 34K, the Malta bits and things.  Still wants
a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/mm/c-r4k.c

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index d3e352f..6a1267a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1228,8 +1228,7 @@
 	struct cpuinfo_mips *c = &current_cpu_data;
 
 	/* Default cache error handler for R4000 and R5000 family */
-	memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_generic, 0x80);
-	memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
+	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
 
 	probe_pcache();
 	setup_scache();

arch/mips/mm/c-sb1.c

diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index e65b1bb..d183dbc 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -502,9 +502,8 @@
 	extern char handle_vec2_sb1;
 
 	/* Special cache error handler for SB1 */
-	memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_sb1, 0x80);
-	memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80);
-	memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
+	set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
+	memcpy((void *)KSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
 
 	probe_cache_sizes();