Merge "msm: usbaudio: Add support for USB headset detection" into msm-3.0
diff --git a/arch/arm/boot/dts/msmcopper.dtsi b/arch/arm/boot/dts/msmcopper.dtsi
index ca67181..284426a 100644
--- a/arch/arm/boot/dts/msmcopper.dtsi
+++ b/arch/arm/boot/dts/msmcopper.dtsi
@@ -72,7 +72,7 @@
reg = <0xf980b000 0x1000>;
interrupts = <0 123 0>;
- qcom,sdcc-clk-rates = <400000 24000000 48000000 96000000 192000000>;
+ qcom,sdcc-clk-rates = <400000 25000000 50000000 96000000 192000000>;
qcom,sdcc-sup-voltages = <3300 3300>;
qcom,sdcc-bus-width = <8>;
qcom,sdcc-hs200;
@@ -86,7 +86,7 @@
reg = <0xf984b000 0x1000>;
interrupts = <0 127 0>;
- qcom,sdcc-clk-rates = <400000 24000000 48000000>;
+ qcom,sdcc-clk-rates = <400000 25000000 50000000>;
qcom,sdcc-sup-voltages = <3300 3300>;
qcom,sdcc-bus-width = <4>;
qcom,sdcc-disable_cmd23;
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 1cf5df3..5b77374 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -229,7 +229,8 @@
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_MSM=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+CONFIG_SENSORS_MSM_ADC=y
CONFIG_MARIMBA_CORE=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index 8d31ee6..287e7fb 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -230,7 +230,8 @@
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_MSM=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+CONFIG_SENSORS_MSM_ADC=y
CONFIG_MARIMBA_CORE=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 9c6ebdf..a6bbaf4 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -319,12 +319,18 @@
CONFIG_MFD_PM8XXX_BATT_ALARM=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_USB_VIDEO_CLASS=y
-CONFIG_IMX074=y
+CONFIG_MSM_CAMERA_V4L2=y
CONFIG_WEBCAM_OV9726=y
CONFIG_MT9E013=y
+CONFIG_IMX074=y
+CONFIG_IMX074_ACT=y
+CONFIG_OV7692=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_ACTUATOR=y
CONFIG_MSM_GEMINI=y
CONFIG_RADIO_TAVARUA=y
CONFIG_ION=y
@@ -340,8 +346,10 @@
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_OVERLAY=y
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
+CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
+CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index aae900a..df49bdc 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -320,12 +320,18 @@
CONFIG_MFD_PM8XXX_BATT_ALARM=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_USB_VIDEO_CLASS=y
-CONFIG_IMX074=y
+CONFIG_MSM_CAMERA_V4L2=y
CONFIG_WEBCAM_OV9726=y
CONFIG_MT9E013=y
+CONFIG_IMX074=y
+CONFIG_IMX074_ACT=y
+CONFIG_OV7692=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_ACTUATOR=y
CONFIG_MSM_GEMINI=y
CONFIG_RADIO_TAVARUA=y
CONFIG_ION=y
@@ -341,8 +347,10 @@
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_OVERLAY=y
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
+CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
+CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm8960-perf_defconfig b/arch/arm/configs/msm8960-perf_defconfig
index dc2db27..b5a17cd 100644
--- a/arch/arm/configs/msm8960-perf_defconfig
+++ b/arch/arm/configs/msm8960-perf_defconfig
@@ -90,6 +90,7 @@
CONFIG_MSM_CACHE_ERP=y
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
CONFIG_MSM_DCVS=y
+CONFIG_MSM_HSIC_SYSMON=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index ba616b0..e18f0ea 100644
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -97,6 +97,7 @@
CONFIG_MSM_DCVS=y
CONFIG_MSM_CACHE_DUMP=y
CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
+CONFIG_MSM_HSIC_SYSMON=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index 3dfb62f..7a5b21a 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -141,7 +141,7 @@
unsigned int msmsdcc_fmax;
bool nonremovable;
bool pclk_src_dfab;
- int (*cfg_mpm_sdiowakeup)(struct device *, unsigned);
+ unsigned int mpm_sdiowakeup_int;
unsigned int wpswitch_gpio;
unsigned char wpswitch_polarity;
struct msm_mmc_slot_reg_data *vreg_data;
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 33c84a6..4ea24a4 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -2275,4 +2275,21 @@
want to dump the L1 and L2 caches on panic before any flush occurs.
If unsure, say N
+config MSM_HSIC_SYSMON
+ tristate "MSM HSIC system monitor driver"
+ depends on USB
+ help
+ Add support for bridging with the system monitor interface of MDM
+ over HSIC. This driver allows the local system monitor to
+ communicate with the remote system monitor interface.
+
+config MSM_HSIC_SYSMON_TEST
+ tristate "MSM HSIC system monitor bridge test"
+ depends on USB && MSM_HSIC_SYSMON && DEBUG_FS
+ help
+ Enable the test hook for the Qualcomm system monitor HSIC driver.
+ This will create a debugfs file entry named "hsic_sysmon_test" which
+ can be read and written to send character data to the sysmon port of
+ the modem over USB.
+
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index fec1b4f..3ef61f4 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -168,7 +168,7 @@
obj-$(CONFIG_ARCH_QSD8X50) += devices-qsd8x50.o clock-pcom-lookup.o
obj-$(CONFIG_MACH_QSD8X50_SURF) += board-qsd8x50.o
obj-$(CONFIG_MACH_QSD8X50_FFA) += board-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o
+obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o clock-pll.o
obj-$(CONFIG_ARCH_MSM8X60) += clock-rpm.o
obj-$(CONFIG_ARCH_MSM8X60) += saw-regulator.o
obj-$(CONFIG_ARCH_MSM8X60) += footswitch-8x60.o
@@ -240,10 +240,10 @@
obj-$(CONFIG_MACH_MSM8625_EVB) += board-qrd7627a.o board-7627a-all.o
obj-$(CONFIG_MACH_MSM8625_QRD7) += board-qrd7627a.o board-7627a-all.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
-obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
+obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o clock-pll.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
obj-$(CONFIG_MACH_MSM7X25_FFA) += board-msm7x27.o devices-msm7x25.o
-obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o
+obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o clock-pll.o
obj-$(CONFIG_ARCH_MSM8960) += footswitch-8x60.o
obj-$(CONFIG_ARCH_MSM8960) += acpuclock-8960.o
obj-$(CONFIG_ARCH_MSM8960) += memory_topology.o
@@ -270,8 +270,8 @@
obj-$(CONFIG_MACH_MPQ8064_HRD) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_MPQ8064_DTV) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o board-9615-gpiomux.o board-9615-storage.o board-9615-display.o
-obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o
-obj-$(CONFIG_ARCH_MSMCOPPER) += board-copper.o board-dt.o board-copper-regulator.o
+obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o clock-pll.o
+obj-$(CONFIG_ARCH_MSMCOPPER) += board-copper.o board-dt.o board-copper-regulator.o board-copper-gpiomux.o
obj-$(CONFIG_ARCH_MSMCOPPER) += acpuclock-krait.o acpuclock-copper.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
@@ -345,3 +345,6 @@
obj-$(CONFIG_MSM_RTB) += msm_rtb.o
obj-$(CONFIG_MSM_CACHE_ERP) += cache_erp.o
obj-$(CONFIG_MSM_CACHE_DUMP) += msm_cache_dump.o
+
+obj-$(CONFIG_MSM_HSIC_SYSMON) += hsic_sysmon.o
+obj-$(CONFIG_MSM_HSIC_SYSMON_TEST) += hsic_sysmon_test.o
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 66d2a57..eba5637 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -240,6 +240,7 @@
static int a2_pc_disabled_wakelock_skipped;
static int disconnect_ack;
static LIST_HEAD(bam_other_notify_funcs);
+static DEFINE_MUTEX(smsm_cb_lock);
struct outside_notify_func {
void (*notify)(void *, int, unsigned long);
@@ -1074,7 +1075,7 @@
fail:
pr_err("%s: reverting to polling\n", __func__);
- queue_work(bam_mux_rx_workqueue, &rx_timer_work);
+ queue_work_on(0, bam_mux_rx_workqueue, &rx_timer_work);
}
static void rx_timer_work_func(struct work_struct *work)
@@ -1179,7 +1180,11 @@
}
grab_wakelock();
polling_mode = 1;
- queue_work(bam_mux_rx_workqueue, &rx_timer_work);
+ /*
+ * run on core 0 so that netif_rx() in rmnet uses only
+ * one queue
+ */
+ queue_work_on(0, bam_mux_rx_workqueue, &rx_timer_work);
}
break;
default:
@@ -2112,10 +2117,20 @@
static void bam_dmux_smsm_cb(void *priv, uint32_t old_state, uint32_t new_state)
{
+ static int last_processed_state;
+
+ mutex_lock(&smsm_cb_lock);
bam_dmux_power_state = new_state & SMSM_A2_POWER_CONTROL ? 1 : 0;
DBG_INC_A2_POWER_CONTROL_IN_CNT();
bam_dmux_log("%s: 0x%08x -> 0x%08x\n", __func__, old_state,
new_state);
+ if (last_processed_state == (new_state & SMSM_A2_POWER_CONTROL)) {
+ bam_dmux_log("%s: already processed this state\n", __func__);
+ mutex_unlock(&smsm_cb_lock);
+ return;
+ }
+
+ last_processed_state = new_state & SMSM_A2_POWER_CONTROL;
if (bam_mux_initialized && new_state & SMSM_A2_POWER_CONTROL) {
bam_dmux_log("%s: reconnect\n", __func__);
@@ -2137,6 +2152,7 @@
bam_dmux_log("%s: bad state change\n", __func__);
pr_err("%s: unsupported state change\n", __func__);
}
+ mutex_unlock(&smsm_cb_lock);
}
@@ -2172,7 +2188,13 @@
if (rc)
pr_err("%s: unable to set dfab clock rate\n", __func__);
- bam_mux_rx_workqueue = create_singlethread_workqueue("bam_dmux_rx");
+ /*
+ * setup the workqueue so that it can be pinned to core 0 and not
+ * block the watchdog pet function, so that netif_rx() in rmnet
+ * only uses one queue.
+ */
+ bam_mux_rx_workqueue = alloc_workqueue("bam_dmux_rx",
+ WQ_MEM_RECLAIM | WQ_CPU_INTENSIVE, 1);
if (!bam_mux_rx_workqueue)
return -ENOMEM;
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index 18d4c4b..0a23a17 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -1850,6 +1850,7 @@
&apq_cpudai_stub,
&apq_cpudai_slimbus_1_rx,
&apq_cpudai_slimbus_1_tx,
+ &apq_cpudai_slimbus_2_tx,
&apq8064_rpm_device,
&apq8064_rpm_log_device,
&apq8064_rpm_stat_device,
diff --git a/arch/arm/mach-msm/board-8930-camera.c b/arch/arm/mach-msm/board-8930-camera.c
index 12312ee..1a7e2e1 100644
--- a/arch/arm/mach-msm/board-8930-camera.c
+++ b/arch/arm/mach-msm/board-8930-camera.c
@@ -138,6 +138,13 @@
[GPIOMUX_SUSPENDED] = &cam_settings[0],
},
},
+ {
+ .gpio = 54,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &cam_settings[2],
+ [GPIOMUX_SUSPENDED] = &cam_settings[0],
+ },
+ },
};
static struct msm_gpiomux_config msm8930_cam_2d_configs[] = {
@@ -373,6 +380,7 @@
static struct gpio msm8930_back_cam_gpio[] = {
{107, GPIOF_DIR_OUT, "CAM_RESET"},
+ {54, GPIOF_DIR_OUT, "CAM_STBY_N"},
};
static struct msm_gpio_set_tbl msm8930_front_cam_gpio_set_tbl[] = {
@@ -381,6 +389,8 @@
};
static struct msm_gpio_set_tbl msm8930_back_cam_gpio_set_tbl[] = {
+ {54, GPIOF_OUT_INIT_LOW, 1000},
+ {54, GPIOF_OUT_INIT_HIGH, 4000},
{107, GPIOF_OUT_INIT_LOW, 1000},
{107, GPIOF_OUT_INIT_HIGH, 4000},
};
diff --git a/arch/arm/mach-msm/board-8960-camera.c b/arch/arm/mach-msm/board-8960-camera.c
index a3d9cba..0d1c72d 100644
--- a/arch/arm/mach-msm/board-8960-camera.c
+++ b/arch/arm/mach-msm/board-8960-camera.c
@@ -412,9 +412,11 @@
.cam_bus_scale_table = &cam_bus_client_pdata,
},
{
- .ioclk.mclk_clk_rate = 24000000,
- .ioclk.vfe_clk_rate = 228570000,
.csid_core = 2,
+ .is_csiphy = 1,
+ .is_csid = 1,
+ .is_ispif = 1,
+ .is_vpe = 1,
.cam_bus_scale_table = &cam_bus_client_pdata,
},
};
@@ -630,7 +632,10 @@
};
static struct msm_camera_sensor_flash_data flash_imx091 = {
- .flash_type = MSM_CAMERA_FLASH_NONE,
+ .flash_type = MSM_CAMERA_FLASH_LED,
+#ifdef CONFIG_MSM_CAMERA_FLASH
+ .flash_src = &msm_flash_src
+#endif
};
static struct msm_camera_sensor_platform_info sensor_board_info_imx091 = {
diff --git a/arch/arm/mach-msm/board-8960-display.c b/arch/arm/mach-msm/board-8960-display.c
index 4b887e8..8c41e8c 100644
--- a/arch/arm/mach-msm/board-8960-display.c
+++ b/arch/arm/mach-msm/board-8960-display.c
@@ -480,6 +480,7 @@
return 0;
}
+static char mipi_dsi_splash_is_enabled(void);
static int mipi_dsi_panel_power(int on)
{
int ret;
@@ -497,6 +498,7 @@
static struct mipi_dsi_platform_data mipi_dsi_pdata = {
.vsync_gpio = MDP_VSYNC_GPIO,
.dsi_power_save = mipi_dsi_panel_power,
+ .splash_is_enabled = mipi_dsi_splash_is_enabled,
};
#ifdef CONFIG_MSM_BUS_SCALING
@@ -619,6 +621,11 @@
#endif
}
+static char mipi_dsi_splash_is_enabled(void)
+{
+ return mdp_pdata.cont_splash_enabled;
+}
+
static struct platform_device mipi_dsi_renesas_panel_device = {
.name = "mipi_renesas",
.id = 0,
@@ -1058,12 +1065,21 @@
void __init msm8960_set_display_params(char *prim_panel, char *ext_panel)
{
+ int disable_splash = 0;
if (strnlen(prim_panel, PANEL_NAME_MAX_LEN)) {
strlcpy(msm_fb_pdata.prim_panel_name, prim_panel,
PANEL_NAME_MAX_LEN);
pr_debug("msm_fb_pdata.prim_panel_name %s\n",
msm_fb_pdata.prim_panel_name);
+ if (strncmp((char *)msm_fb_pdata.prim_panel_name,
+ MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
+ strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
+ PANEL_NAME_MAX_LEN))) {
+ /* Disable splash for panels other than Toshiba WSVGA */
+ disable_splash = 1;
+ }
+
if (!strncmp((char *)msm_fb_pdata.prim_panel_name,
HDMI_PANEL_NAME, strnlen(HDMI_PANEL_NAME,
PANEL_NAME_MAX_LEN))) {
@@ -1086,6 +1102,6 @@
msm_fb_pdata.ext_panel_name);
}
- if (hdmi_is_primary)
+ if (disable_splash)
mdp_pdata.cont_splash_enabled = 0;
}
diff --git a/arch/arm/mach-msm/board-8960-gpiomux.c b/arch/arm/mach-msm/board-8960-gpiomux.c
index 2cb923c..9bf80ed 100644
--- a/arch/arm/mach-msm/board-8960-gpiomux.c
+++ b/arch/arm/mach-msm/board-8960-gpiomux.c
@@ -61,6 +61,18 @@
.pull = GPIOMUX_PULL_NONE,
};
+static struct gpiomux_setting gsbi9_active_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting gsbi9_suspended_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
static struct gpiomux_setting gsbi10 = {
.func = GPIOMUX_FUNC_2,
.drv = GPIOMUX_DRV_8MA,
@@ -276,6 +288,37 @@
};
#endif
+static struct msm_gpiomux_config msm8960_fusion_gsbi_configs[] = {
+ {
+ .gpio = 93,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+ {
+ .gpio = 94,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+ {
+ .gpio = 95,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+ {
+ .gpio = 96,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gsbi9_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi9_active_cfg,
+ }
+ },
+};
+
static struct msm_gpiomux_config msm8960_gsbi_configs[] __initdata = {
{
.gpio = 6, /* GSBI1 QUP SPI_DATA_MOSI */
@@ -730,6 +773,10 @@
else
msm_gpiomux_install(msm8960_gsbi5_uart_configs,
ARRAY_SIZE(msm8960_gsbi5_uart_configs));
+ /* For 8960 Fusion 2.2 Primary IPC */
+ if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE)
+ msm_gpiomux_install(msm8960_fusion_gsbi_configs,
+ ARRAY_SIZE(msm8960_fusion_gsbi_configs));
return 0;
}
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index c677d97..a21788b 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -51,6 +51,7 @@
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/msm_spi.h>
+#include <mach/msm_serial_hs.h>
#ifdef CONFIG_USB_MSM_OTG_72K
#include <mach/msm_hsusb.h>
#else
@@ -2214,11 +2215,45 @@
.platform_data = &msm_rpm_regulator_pdata,
},
};
+#ifdef CONFIG_SERIAL_MSM_HS
+static int configure_uart_gpios(int on)
+{
+ int ret = 0, i;
+ int uart_gpios[] = {93, 94, 95, 96};
+
+ for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
+ if (on) {
+ ret = gpio_request(uart_gpios[i], NULL);
+ if (ret) {
+ pr_err("%s: unable to request uart gpio[%d]\n",
+ __func__, uart_gpios[i]);
+ break;
+ }
+ } else {
+ gpio_free(uart_gpios[i]);
+ }
+ }
+
+ if (ret && on && i)
+ for (; i >= 0; i--)
+ gpio_free(uart_gpios[i]);
+ return ret;
+}
+
+static struct msm_serial_hs_platform_data msm_uart_dm9_pdata = {
+ .inject_rx_on_wakeup = 1,
+ .rx_to_inject = 0xFD,
+ .gpio_config = configure_uart_gpios,
+};
+#else
+static struct msm_serial_hs_platform_data msm_uart_dm9_pdata;
+#endif
static struct platform_device *common_devices[] __initdata = {
&msm8960_device_dmov,
&msm_device_smd,
&msm_device_uart_dm6,
+ &msm_device_uart_dm9,
&msm_device_saw_core0,
&msm_device_saw_core1,
&msm8960_device_ext_5v_vreg,
@@ -2317,6 +2352,7 @@
&msm_pcm_routing,
&msm_cpudai0,
&msm_cpudai1,
+ &msm8960_cpudai_slimbus_2_tx,
&msm_cpudai_hdmi_rx,
&msm_cpudai_bt_rx,
&msm_cpudai_bt_tx,
@@ -2372,6 +2408,7 @@
&msm_pcm_routing,
&msm_cpudai0,
&msm_cpudai1,
+ &msm8960_cpudai_slimbus_2_tx,
&msm_cpudai_hdmi_rx,
&msm_cpudai_bt_rx,
&msm_cpudai_bt_tx,
@@ -2809,6 +2846,11 @@
platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
msm8960_init_mmc();
register_i2c_devices();
+
+ /* For 8960 Fusion 2.2 Primary IPC */
+ if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE)
+ msm_device_uart_dm9.dev.platform_data = &msm_uart_dm9_pdata;
+
msm8960_init_fb();
slim_register_board_info(msm_slim_devices,
ARRAY_SIZE(msm_slim_devices));
diff --git a/arch/arm/mach-msm/board-copper-gpiomux.c b/arch/arm/mach-msm/board-copper-gpiomux.c
new file mode 100644
index 0000000..50b03fc
--- /dev/null
+++ b/arch/arm/mach-msm/board-copper-gpiomux.c
@@ -0,0 +1,53 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/gpiomux.h>
+
+static struct gpiomux_setting gpio_uart_config = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_16MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_OUT_HIGH,
+};
+
+static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
+ {
+ .gpio = 45, /* BLSP8 UART TX */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_uart_config,
+ },
+ },
+ {
+ .gpio = 46, /* BLSP8 UART RX */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_uart_config,
+ },
+ },
+};
+
+void __init msm_copper_init_gpiomux(void)
+{
+ int rc;
+
+ rc = msm_gpiomux_init(NR_GPIO_IRQS);
+ if (rc) {
+ pr_err(KERN_ERR "msmcopper_init_gpiomux failed %d\n", rc);
+ return;
+ }
+
+ msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs));
+}
diff --git a/arch/arm/mach-msm/board-copper.c b/arch/arm/mach-msm/board-copper.c
index b074809..83b7212 100644
--- a/arch/arm/mach-msm/board-copper.c
+++ b/arch/arm/mach-msm/board-copper.c
@@ -340,19 +340,6 @@
msm_reserve();
}
-static int __init gpiomux_init(void)
-{
- int rc;
-
- rc = msm_gpiomux_init(NR_GPIO_IRQS);
- if (rc) {
- pr_err("%s: msm_gpiomux_init failed %d\n", __func__, rc);
- return rc;
- }
-
- return 0;
-}
-
static struct platform_device android_usb_device = {
.name = "android_usb",
.id = -1,
@@ -433,8 +420,7 @@
void __init msm_copper_init(struct of_dev_auxdata **adata)
{
- if (gpiomux_init())
- pr_err("%s: gpiomux_init() failed\n", __func__);
+ msm_copper_init_gpiomux();
msm_clock_init(&msm_dummy_clock_init_data);
*adata = msm_copper_auxdata_lookup;
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 5b60af0..c3650fa 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -49,6 +49,7 @@
#include <linux/smsc911x.h>
#include <linux/atmel_maxtouch.h>
#include <linux/fmem.h>
+#include <linux/msm_adc.h>
#include "devices.h"
#include "timer.h"
#include "board-msm7x27a-regulator.h"
@@ -712,6 +713,24 @@
"eth_fifo_sel" },
};
+static char *msm_adc_surf_device_names[] = {
+ "XO_ADC",
+};
+
+static struct msm_adc_platform_data msm_adc_pdata = {
+ .dev_names = msm_adc_surf_device_names,
+ .num_adc = ARRAY_SIZE(msm_adc_surf_device_names),
+ .target_hw = MSM_8x25,
+};
+
+static struct platform_device msm_adc_device = {
+ .name = "msm_adc",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_adc_pdata,
+ },
+};
+
#define ETH_FIFO_SEL_GPIO 49
static void msm7x27a_cfg_smsc911x(void)
{
@@ -814,6 +833,7 @@
&asoc_msm_dai0,
&asoc_msm_dai1,
&msm_batt_device,
+ &msm_adc_device,
};
static struct platform_device *msm8625_surf_devices[] __initdata = {
diff --git a/arch/arm/mach-msm/board-msm8x60-camera.c b/arch/arm/mach-msm/board-msm8x60-camera.c
index 95561e4..c12dce6 100644
--- a/arch/arm/mach-msm/board-msm8x60-camera.c
+++ b/arch/arm/mach-msm/board-msm8x60-camera.c
@@ -12,7 +12,6 @@
*/
#include <asm/mach-types.h>
-#include <devices-msm8x60.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/mfd/pmic8901.h>
@@ -20,6 +19,7 @@
#include <mach/board-msm8660.h>
#include <mach/gpiomux.h>
#include <mach/msm_bus_board.h>
+#include "devices-msm8x60.h"
#include "devices.h"
#define GPIO_EXT_CAMIF_PWR_EN1 (PM8901_MPP_BASE + PM8901_MPPS + 13)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 8e02093..7832b878 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -2630,7 +2630,7 @@
#endif /* CONFIG_FB_MSM_OVERLAY1_WRITEBACK */
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x3BC000
-#define MSM_PMEM_ADSP_SIZE 0x2000000
+#define MSM_PMEM_ADSP_SIZE 0x4200000
#define MSM_PMEM_AUDIO_SIZE 0x4CF000
#define MSM_SMI_BASE 0x38000000
@@ -8311,44 +8311,10 @@
}
#endif
#endif
-
-#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
-static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
-{
- struct platform_device *pdev;
- enum msm_mpm_pin pin;
- int ret = 0;
-
- pdev = container_of(dev, struct platform_device, dev);
-
- /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
- if (pdev->id == 4)
- pin = MSM_MPM_PIN_SDC4_DAT1;
- else
- return -EINVAL;
-
- switch (mode) {
- case SDC_DAT1_DISABLE:
- ret = msm_mpm_enable_pin(pin, 0);
- break;
- case SDC_DAT1_ENABLE:
- ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
- ret = msm_mpm_enable_pin(pin, 1);
- break;
- case SDC_DAT1_ENWAKE:
- ret = msm_mpm_set_pin_wake(pin, 1);
- break;
- case SDC_DAT1_DISWAKE:
- ret = msm_mpm_set_pin_wake(pin, 0);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
#endif
-#endif
+
+#define MSM_MPM_PIN_SDC3_DAT1 21
+#define MSM_MPM_PIN_SDC4_DAT1 23
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
static struct mmc_platform_data msm8x60_sdc1_data = {
@@ -8415,7 +8381,7 @@
.msmsdcc_fmax = 48000000,
.nonremovable = 0,
.pclk_src_dfab = 1,
- .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
+ .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC4_DAT1,
};
#endif
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index 4a6b150..3e8dd8f 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -30,6 +30,7 @@
#include <linux/regulator/consumer.h>
#include <linux/memblock.h>
#include <linux/input/ft5x06_ts.h>
+#include <linux/msm_adc.h>
#include <asm/mach/mmc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -599,6 +600,24 @@
.dev.platform_data = &msm_psy_batt_data,
};
+static char *msm_adc_surf_device_names[] = {
+ "XO_ADC",
+};
+
+static struct msm_adc_platform_data msm_adc_pdata = {
+ .dev_names = msm_adc_surf_device_names,
+ .num_adc = ARRAY_SIZE(msm_adc_surf_device_names),
+ .target_hw = MSM_8x25,
+};
+
+static struct platform_device msm_adc_device = {
+ .name = "msm_adc",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_adc_pdata,
+ },
+};
+
static struct platform_device *common_devices[] __initdata = {
&android_usb_device,
&android_pmem_device,
@@ -610,6 +629,7 @@
&asoc_msm_pcm,
&asoc_msm_dai0,
&asoc_msm_dai1,
+ &msm_adc_device,
};
static struct platform_device *qrd7627a_devices[] __initdata = {
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index f9d8dbe..5951734 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -31,6 +31,7 @@
#include "clock-pcom.h"
#include "clock-voter.h"
#include "proc_comm.h"
+#include "clock-pll.h"
#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
#define REG(off) (MSM_CLK_CTL_SH2_BASE + (off))
@@ -268,6 +269,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(1),
.status_reg = PLL1_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &tcxo_clk.c,
.c = {
.dbg_name = "pll1_clk",
@@ -282,6 +284,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(2),
.status_reg = PLL2_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &tcxo_clk.c,
.c = {
.dbg_name = "pll2_clk",
@@ -296,6 +299,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(3),
.status_reg = PLL3_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &lpxo_clk.c,
.c = {
.dbg_name = "pll3_clk",
@@ -309,6 +313,7 @@
.en_reg = PLL_ENA_REG,
.en_mask = BIT(4),
.status_reg = PLL4_STATUS_BASE_REG,
+ .status_mask = BIT(16),
.parent = &lpxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index bbe7bae..ca5a63d 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -33,6 +33,7 @@
#include "clock-voter.h"
#include "clock-dss-8960.h"
#include "devices.h"
+#include "clock-pll.h"
#define REG(off) (MSM_CLK_CTL_BASE + (off))
#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
@@ -478,7 +479,7 @@
.c = {
.dbg_name = "pll2_clk",
.rate = 800000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
.warned = true,
},
@@ -490,7 +491,7 @@
.c = {
.dbg_name = "pll3_clk",
.rate = 1200000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
.vdd_class = &vdd_sr2_pll,
.fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
CLK_INIT(pll3_clk.c),
@@ -502,6 +503,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
@@ -516,6 +518,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
@@ -530,6 +533,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(14),
.status_reg = BB_PLL14_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
@@ -546,7 +550,7 @@
.c = {
.dbg_name = "pll15_clk",
.rate = 975000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll15_clk.c),
.warned = true,
},
@@ -5226,7 +5230,7 @@
CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"),
- CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"),
CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
@@ -5279,7 +5283,7 @@
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"),
- CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"),
CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
@@ -6032,7 +6036,7 @@
vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
- clk_ops_pll.enable = sr_pll_clk_enable;
+ clk_ops_local_pll.enable = sr_pll_clk_enable;
/* Initialize clock registers. */
reg_init();
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 6c85450..6c23c50 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -31,6 +31,7 @@
#include "clock-local.h"
#include "clock-rpm.h"
#include "clock-voter.h"
+#include "clock-pll.h"
#ifdef CONFIG_MSM_SECURE_IO
#undef readl_relaxed
@@ -304,6 +305,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
@@ -320,7 +322,7 @@
.c = {
.dbg_name = "pll2_clk",
.rate = 800000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
.warned = true,
},
@@ -332,7 +334,7 @@
.c = {
.dbg_name = "pll3_clk",
.rate = 0, /* TODO: Detect rate dynamically */
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll3_clk.c),
.warned = true,
},
@@ -3692,8 +3694,10 @@
CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
+ CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
+ CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "msm_iommu.7"),
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 411e615..b145278 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -32,6 +32,7 @@
#include "clock-voter.h"
#include "clock-rpm.h"
#include "devices.h"
+#include "clock-pll.h"
#define REG(off) (MSM_CLK_CTL_BASE + (off))
#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
@@ -259,6 +260,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll0,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
@@ -275,6 +277,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.soft_vote = &soft_vote_pll0,
.soft_vote_mask = PLL_SOFT_VOTE_ACPU,
.c = {
@@ -290,6 +293,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
@@ -306,6 +310,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll8,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
@@ -322,6 +327,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.soft_vote = &soft_vote_pll8,
.soft_vote_mask = PLL_SOFT_VOTE_ACPU,
.c = {
@@ -338,7 +344,7 @@
.c = {
.dbg_name = "pll9_acpu_clk",
.rate = 440000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll9_acpu_clk.c),
.warned = true,
},
@@ -348,6 +354,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(11),
.status_reg = BB_PLL14_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &cxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
@@ -1742,7 +1749,7 @@
vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
- clk_ops_pll.enable = sr_pll_clk_enable;
+ clk_ops_local_pll.enable = sr_pll_clk_enable;
/* Enable PDM CXO source. */
regval = readl_relaxed(PDM_CLK_NS_REG);
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index 84aa086..d414e44 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -627,158 +627,6 @@
return HANDOFF_ENABLED_CLK;
}
-int pll_vote_clk_enable(struct clk *clk)
-{
- u32 ena;
- unsigned long flags;
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- ena = readl_relaxed(pll->en_reg);
- ena |= pll->en_mask;
- writel_relaxed(ena, pll->en_reg);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-
- /* Wait until PLL is enabled */
- while ((readl_relaxed(pll->status_reg) & BIT(16)) == 0)
- cpu_relax();
-
- return 0;
-}
-
-void pll_vote_clk_disable(struct clk *clk)
-{
- u32 ena;
- unsigned long flags;
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- ena = readl_relaxed(pll->en_reg);
- ena &= ~(pll->en_mask);
- writel_relaxed(ena, pll->en_reg);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
-struct clk *pll_vote_clk_get_parent(struct clk *clk)
-{
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
- return pll->parent;
-}
-
-int pll_vote_clk_is_enabled(struct clk *clk)
-{
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
- return !!(readl_relaxed(pll->status_reg) & BIT(16));
-}
-
-struct clk_ops clk_ops_pll_vote = {
- .enable = pll_vote_clk_enable,
- .disable = pll_vote_clk_disable,
- .auto_off = pll_vote_clk_disable,
- .is_enabled = pll_vote_clk_is_enabled,
- .get_parent = pll_vote_clk_get_parent,
-};
-
-static int pll_clk_enable(struct clk *clk)
-{
- u32 mode;
- unsigned long flags;
- struct pll_clk *pll = to_pll_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- mode = readl_relaxed(pll->mode_reg);
- /* Disable PLL bypass mode. */
- mode |= BIT(1);
- writel_relaxed(mode, pll->mode_reg);
-
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- udelay(10);
-
- /* De-assert active-low PLL reset. */
- mode |= BIT(2);
- writel_relaxed(mode, pll->mode_reg);
-
- /* Wait until PLL is locked. */
- mb();
- udelay(50);
-
- /* Enable PLL output. */
- mode |= BIT(0);
- writel_relaxed(mode, pll->mode_reg);
-
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
- return 0;
-}
-
-static void pll_clk_disable(struct clk *clk)
-{
- u32 mode;
- unsigned long flags;
- struct pll_clk *pll = to_pll_clk(clk);
-
- /*
- * Disable the PLL output, disable test mode, enable
- * the bypass mode, and assert the reset.
- */
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- mode = readl_relaxed(pll->mode_reg);
- mode &= ~BM(3, 0);
- writel_relaxed(mode, pll->mode_reg);
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
-}
-
-static struct clk *pll_clk_get_parent(struct clk *clk)
-{
- struct pll_clk *pll = to_pll_clk(clk);
- return pll->parent;
-}
-
-int sr_pll_clk_enable(struct clk *clk)
-{
- u32 mode;
- unsigned long flags;
- struct pll_clk *pll = to_pll_clk(clk);
-
- spin_lock_irqsave(&local_clock_reg_lock, flags);
- mode = readl_relaxed(pll->mode_reg);
- /* De-assert active-low PLL reset. */
- mode |= BIT(2);
- writel_relaxed(mode, pll->mode_reg);
-
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- udelay(10);
-
- /* Disable PLL bypass mode. */
- mode |= BIT(1);
- writel_relaxed(mode, pll->mode_reg);
-
- /* Wait until PLL is locked. */
- mb();
- udelay(60);
-
- /* Enable PLL output. */
- mode |= BIT(0);
- writel_relaxed(mode, pll->mode_reg);
-
- spin_unlock_irqrestore(&local_clock_reg_lock, flags);
- return 0;
-}
-
-struct clk_ops clk_ops_pll = {
- .enable = pll_clk_enable,
- .disable = pll_clk_disable,
- .auto_off = pll_clk_disable,
- .get_parent = pll_clk_get_parent,
-};
-
struct clk_ops clk_ops_gnd = {
};
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index 3dd849a..0419ede 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -17,12 +17,6 @@
#include <linux/spinlock.h>
#include "clock.h"
-/*
- * Bit manipulation macros
- */
-#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
-#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
-
#define MN_MODE_DUAL_EDGE 0x2
/* MD Registers */
@@ -257,57 +251,6 @@
};
/**
- * struct pll_vote_clk - phase locked loop (HW voteable)
- * @soft_vote: soft voting variable for multiple PLL software instances
- * @soft_vote_mask: soft voting mask for multiple PLL software instances
- * @en_reg: enable register
- * @en_mask: ORed with @en_reg to enable the clock
- * @status_reg: status register
- * @parent: clock source
- * @c: clk
- */
-struct pll_vote_clk {
- u32 *soft_vote;
- const u32 soft_vote_mask;
- void __iomem *const en_reg;
- const u32 en_mask;
-
- void __iomem *const status_reg;
-
- struct clk *parent;
- struct clk c;
-};
-
-extern struct clk_ops clk_ops_pll_vote;
-
-static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
-{
- return container_of(clk, struct pll_vote_clk, c);
-}
-
-/**
- * struct pll_clk - phase locked loop
- * @mode_reg: enable register
- * @parent: clock source
- * @c: clk
- */
-struct pll_clk {
- void __iomem *const mode_reg;
-
- struct clk *parent;
- struct clk c;
-};
-
-extern struct clk_ops clk_ops_pll;
-
-static inline struct pll_clk *to_pll_clk(struct clk *clk)
-{
- return container_of(clk, struct pll_clk, c);
-}
-
-int sr_pll_clk_enable(struct clk *clk);
-
-/**
* struct branch_clk - branch
* @enabled: true if clock is on, false otherwise
* @b: branch
@@ -365,14 +308,6 @@
extern struct fixed_clk gnd_clk;
/*
- * PLL vote clock APIs
- */
-int pll_vote_clk_enable(struct clk *clk);
-void pll_vote_clk_disable(struct clk *clk);
-struct clk *pll_vote_clk_get_parent(struct clk *clk);
-int pll_vote_clk_is_enabled(struct clk *clk);
-
-/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 2d98895..d842d45 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -395,6 +395,7 @@
CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
CLK_LOOKUP("bus_clk", ebi_grp_3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "lcdc.0"),
+ CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "mipi_dsi.1"),
CLK_LOOKUP("mem_clk", ebi_mddi_clk.c, "mddi.0"),
CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index 68c390a..e83f17a 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -17,13 +17,201 @@
#include <linux/err.h>
#include <linux/remote_spinlock.h>
-#include <mach/socinfo.h>
+#include <mach/scm-io.h>
#include <mach/msm_iomap.h>
#include "clock.h"
#include "clock-pll.h"
#include "smd_private.h"
+#ifdef CONFIG_MSM_SECURE_IO
+#undef readl_relaxed
+#undef writel_relaxed
+#define readl_relaxed secure_readl
+#define writel_relaxed secure_writel
+#endif
+
+#define PLL_OUTCTRL BIT(0)
+#define PLL_BYPASSNL BIT(1)
+#define PLL_RESET_N BIT(2)
+#define PLL_MODE_MASK BM(3, 0)
+
+#define PLL_EN_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->en_reg)) : \
+ ((x)->en_reg))
+#define PLL_STATUS_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->status_reg)) : \
+ ((x)->status_reg))
+#define PLL_MODE_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->mode_reg)) : \
+ ((x)->mode_reg))
+
+static DEFINE_SPINLOCK(pll_reg_lock);
+
+int pll_vote_clk_enable(struct clk *clk)
+{
+ u32 ena;
+ unsigned long flags;
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ ena = readl_relaxed(PLL_EN_REG(pll));
+ ena |= pll->en_mask;
+ writel_relaxed(ena, PLL_EN_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+
+ /* Wait until PLL is enabled */
+ while ((readl_relaxed(PLL_STATUS_REG(pll)) & pll->status_mask) == 0)
+ cpu_relax();
+
+ return 0;
+}
+
+void pll_vote_clk_disable(struct clk *clk)
+{
+ u32 ena;
+ unsigned long flags;
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ ena = readl_relaxed(PLL_EN_REG(pll));
+ ena &= ~(pll->en_mask);
+ writel_relaxed(ena, PLL_EN_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+}
+
+struct clk *pll_vote_clk_get_parent(struct clk *clk)
+{
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+ return pll->parent;
+}
+
+int pll_vote_clk_is_enabled(struct clk *clk)
+{
+ struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+ return !!(readl_relaxed(PLL_STATUS_REG(pll)) & pll->status_mask);
+}
+
+struct clk_ops clk_ops_pll_vote = {
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+ .get_parent = pll_vote_clk_get_parent,
+};
+
+static void __pll_clk_enable_reg(void __iomem *mode_reg)
+{
+ u32 mode = readl_relaxed(mode_reg);
+ /* Disable PLL bypass mode. */
+ mode |= PLL_BYPASSNL;
+ writel_relaxed(mode, mode_reg);
+
+ /*
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
+ mb();
+ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ mode |= PLL_RESET_N;
+ writel_relaxed(mode, mode_reg);
+
+ /* Wait until PLL is locked. */
+ mb();
+ udelay(50);
+
+ /* Enable PLL output. */
+ mode |= PLL_OUTCTRL;
+ writel_relaxed(mode, mode_reg);
+
+ /* Ensure that the write above goes through before returning. */
+ mb();
+}
+
+static int local_pll_clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+ struct pll_clk *pll = to_pll_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ __pll_clk_enable_reg(PLL_MODE_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+
+ return 0;
+}
+
+static void __pll_clk_disable_reg(void __iomem *mode_reg)
+{
+ u32 mode = readl_relaxed(mode_reg);
+ mode &= ~PLL_MODE_MASK;
+ writel_relaxed(mode, mode_reg);
+}
+
+static void local_pll_clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+ struct pll_clk *pll = to_pll_clk(clk);
+
+ /*
+ * Disable the PLL output, disable test mode, enable
+ * the bypass mode, and assert the reset.
+ */
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ __pll_clk_disable_reg(PLL_MODE_REG(pll));
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+}
+
+static struct clk *local_pll_clk_get_parent(struct clk *clk)
+{
+ struct pll_clk *pll = to_pll_clk(clk);
+ return pll->parent;
+}
+
+int sr_pll_clk_enable(struct clk *clk)
+{
+ u32 mode;
+ unsigned long flags;
+ struct pll_clk *pll = to_pll_clk(clk);
+
+ spin_lock_irqsave(&pll_reg_lock, flags);
+ mode = readl_relaxed(PLL_MODE_REG(pll));
+ /* De-assert active-low PLL reset. */
+ mode |= PLL_RESET_N;
+ writel_relaxed(mode, PLL_MODE_REG(pll));
+
+ /*
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
+ mb();
+ udelay(10);
+
+ /* Disable PLL bypass mode. */
+ mode |= PLL_BYPASSNL;
+ writel_relaxed(mode, PLL_MODE_REG(pll));
+
+ /* Wait until PLL is locked. */
+ mb();
+ udelay(60);
+
+ /* Enable PLL output. */
+ mode |= PLL_OUTCTRL;
+ writel_relaxed(mode, PLL_MODE_REG(pll));
+
+ /* Ensure that the write above goes through before returning. */
+ mb();
+
+ spin_unlock_irqrestore(&pll_reg_lock, flags);
+
+ return 0;
+}
+
+struct clk_ops clk_ops_local_pll = {
+ .enable = local_pll_clk_enable,
+ .disable = local_pll_clk_disable,
+ .auto_off = local_pll_clk_disable,
+ .get_parent = local_pll_clk_get_parent,
+};
+
struct pll_rate {
unsigned int lvalue;
unsigned long rate;
@@ -95,21 +283,6 @@
}
-static void pll_enable(void __iomem *addr, unsigned on)
-{
- if (on) {
- writel_relaxed(2, addr);
- mb();
- udelay(5);
- writel_relaxed(6, addr);
- mb();
- udelay(50);
- writel_relaxed(7, addr);
- } else {
- writel_relaxed(0, addr);
- }
-}
-
static int pll_clk_enable(struct clk *clk)
{
struct pll_shared_clk *pll = to_pll_shared_clk(clk);
@@ -119,7 +292,7 @@
pll_control->pll[PLL_BASE + pll_id].votes |= BIT(1);
if (!pll_control->pll[PLL_BASE + pll_id].on) {
- pll_enable(pll->mode_reg, 1);
+ __pll_clk_enable_reg(PLL_MODE_REG(pll));
pll_control->pll[PLL_BASE + pll_id].on = 1;
}
@@ -137,7 +310,7 @@
pll_control->pll[PLL_BASE + pll_id].votes &= ~BIT(1);
if (pll_control->pll[PLL_BASE + pll_id].on
&& !pll_control->pll[PLL_BASE + pll_id].votes) {
- pll_enable(pll->mode_reg, 0);
+ __pll_clk_disable_reg(PLL_MODE_REG(pll));
pll_control->pll[PLL_BASE + pll_id].on = 0;
}
@@ -148,12 +321,7 @@
{
struct pll_shared_clk *pll = to_pll_shared_clk(clk);
- return readl_relaxed(pll->mode_reg) & BIT(0);
-}
-
-static bool pll_clk_is_local(struct clk *clk)
-{
- return true;
+ return readl_relaxed(PLL_MODE_REG(pll)) & BIT(0);
}
static enum handoff pll_clk_handoff(struct clk *clk)
@@ -166,7 +334,7 @@
* Wait for the PLLs to be initialized and then read their frequency.
*/
do {
- pll_lval = readl_relaxed(pll->mode_reg + 4) & 0x3ff;
+ pll_lval = readl_relaxed(PLL_MODE_REG(pll) + 4) & 0x3ff;
cpu_relax();
udelay(50);
} while (pll_lval == 0);
@@ -191,6 +359,5 @@
.enable = pll_clk_enable,
.disable = pll_clk_disable,
.handoff = pll_clk_handoff,
- .is_local = pll_clk_is_local,
.is_enabled = pll_clk_is_enabled,
};
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index ae0ca17..26bfc68 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -12,6 +12,9 @@
*
*/
+#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PLL_H
+#define __ARCH_ARM_MACH_MSM_CLOCK_PLL_H
+
/**
* enum - For PLL IDs
*/
@@ -37,6 +40,7 @@
unsigned int id;
void __iomem *const mode_reg;
struct clk c;
+ void *const __iomem *base;
};
extern struct clk_ops clk_pll_ops;
@@ -50,3 +54,67 @@
* msm_shared_pll_control_init() - Initialize shared pll control structure
*/
void msm_shared_pll_control_init(void);
+
+/**
+ * struct pll_vote_clk - phase locked loop (HW voteable)
+ * @soft_vote: soft voting variable for multiple PLL software instances
+ * @soft_vote_mask: soft voting mask for multiple PLL software instances
+ * @en_reg: enable register
+ * @en_mask: ORed with @en_reg to enable the clock
+ * @status_mask: ANDed with @status_reg to determine if PLL is active.
+ * @status_reg: status register
+ * @parent: clock source
+ * @c: clk
+ */
+struct pll_vote_clk {
+ u32 *soft_vote;
+ const u32 soft_vote_mask;
+ void __iomem *const en_reg;
+ const u32 en_mask;
+ void __iomem *const status_reg;
+ const u32 status_mask;
+
+ struct clk *parent;
+ struct clk c;
+ void *const __iomem *base;
+};
+
+extern struct clk_ops clk_ops_pll_vote;
+
+static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
+{
+ return container_of(clk, struct pll_vote_clk, c);
+}
+
+/**
+ * struct pll_clk - phase locked loop
+ * @mode_reg: enable register
+ * @parent: clock source
+ * @c: clk
+ */
+struct pll_clk {
+ void __iomem *const mode_reg;
+
+ struct clk *parent;
+ struct clk c;
+ void *const __iomem *base;
+};
+
+extern struct clk_ops clk_ops_local_pll;
+
+static inline struct pll_clk *to_pll_clk(struct clk *clk)
+{
+ return container_of(clk, struct pll_clk, c);
+}
+
+int sr_pll_clk_enable(struct clk *clk);
+
+/*
+ * PLL vote clock APIs
+ */
+int pll_vote_clk_enable(struct clk *clk);
+void pll_vote_clk_disable(struct clk *clk);
+struct clk *pll_vote_clk_get_parent(struct clk *clk);
+int pll_vote_clk_is_enabled(struct clk *clk);
+
+#endif
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 60be654..fda7175 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -37,6 +37,12 @@
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
+/*
+ * Bit manipulation macros
+ */
+#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
+#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
+
#define MAX_VDD_LEVELS 4
/**
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 5d6a3ae..b760226 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -551,6 +551,11 @@
.id = 0x4003,
};
+struct platform_device apq_cpudai_slimbus_2_tx = {
+ .name = "msm-dai-q6",
+ .id = 0x4005,
+};
+
static struct resource resources_ssbi_pmic1[] = {
{
.start = MSM_PMIC1_SSBI_CMD_PHYS,
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 375aa8d..ef14b93 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -74,6 +74,7 @@
#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
#define MSM_UART6DM_PHYS (MSM_GSBI6_PHYS + 0x40000)
#define MSM_UART8DM_PHYS (MSM_GSBI8_PHYS + 0x40000)
+#define MSM_UART9DM_PHYS (MSM_GSBI9_PHYS + 0x40000)
/* GSBI QUP devices */
#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
@@ -283,6 +284,52 @@
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
+/*
+ * GSBI 9 used into UARTDM Mode
+ * For 8960 Fusion 2.2 Primary IPC
+ */
+static struct resource msm_uart_dm9_resources[] = {
+ {
+ .start = MSM_UART9DM_PHYS,
+ .end = MSM_UART9DM_PHYS + PAGE_SIZE - 1,
+ .name = "uartdm_resource",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = GSBI9_UARTDM_IRQ,
+ .end = GSBI9_UARTDM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MSM_GSBI9_PHYS,
+ .end = MSM_GSBI9_PHYS + 4 - 1,
+ .name = "gsbi_resource",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DMOV_HSUART_GSBI9_TX_CHAN,
+ .end = DMOV_HSUART_GSBI9_RX_CHAN,
+ .name = "uartdm_channels",
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMOV_HSUART_GSBI9_TX_CRCI,
+ .end = DMOV_HSUART_GSBI9_RX_CRCI,
+ .name = "uartdm_crci",
+ .flags = IORESOURCE_DMA,
+ },
+};
+static u64 msm_uart_dm9_dma_mask = DMA_BIT_MASK(32);
+struct platform_device msm_device_uart_dm9 = {
+ .name = "msm_serial_hs",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(msm_uart_dm9_resources),
+ .resource = msm_uart_dm9_resources,
+ .dev = {
+ .dma_mask = &msm_uart_dm9_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
static struct resource resources_uart_gsbi5[] = {
{
@@ -1790,6 +1837,11 @@
.id = 0x4001,
};
+struct platform_device msm8960_cpudai_slimbus_2_tx = {
+ .name = "msm-dai-q6",
+ .id = 0x4005,
+};
+
struct platform_device msm_cpudai_hdmi_rx = {
.name = "msm-dai-q6-hdmi",
.id = 8,
@@ -2796,7 +2848,7 @@
.bus_freq = 0,
},
},
- .init_level = 0,
+ .init_level = 1,
.num_levels = ARRAY_SIZE(grp3d_freq) + 1,
.set_grp_async = NULL,
.idle_timeout = HZ/12,
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index f110a33..0c25434 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -52,6 +52,7 @@
extern struct platform_device msm_device_uart_dm12;
extern struct platform_device *msm_device_uart_gsbi9;
extern struct platform_device msm_device_uart_dm6;
+extern struct platform_device msm_device_uart_dm9;
extern struct platform_device msm8960_device_uart_gsbi2;
extern struct platform_device msm8960_device_uart_gsbi5;
@@ -195,6 +196,7 @@
extern struct platform_device msm_cpudai0;
extern struct platform_device msm_cpudai1;
extern struct platform_device mpq_cpudai_sec_i2s_rx;
+extern struct platform_device msm8960_cpudai_slimbus_2_tx;
extern struct platform_device msm_cpudai_hdmi_rx;
extern struct platform_device msm_cpudai_bt_rx;
extern struct platform_device msm_cpudai_bt_tx;
@@ -256,6 +258,7 @@
extern struct platform_device apq_cpudai_stub;
extern struct platform_device apq_cpudai_slimbus_1_rx;
extern struct platform_device apq_cpudai_slimbus_1_tx;
+extern struct platform_device apq_cpudai_slimbus_2_tx;
extern struct platform_device *msm_footswitch_devices[];
extern unsigned msm_num_footswitch_devices;
diff --git a/arch/arm/mach-msm/hsic_sysmon.c b/arch/arm/mach-msm/hsic_sysmon.c
new file mode 100644
index 0000000..2dedbac
--- /dev/null
+++ b/arch/arm/mach-msm/hsic_sysmon.c
@@ -0,0 +1,449 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* add additional information to our printk's */
+#define pr_fmt(fmt) "%s: " fmt "\n", __func__
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/usb.h>
+#include <linux/debugfs.h>
+
+#include "hsic_sysmon.h"
+#include "sysmon.h"
+
+#define DRIVER_DESC "HSIC System monitor driver"
+
+enum hsic_sysmon_op {
+ HSIC_SYSMON_OP_READ = 0,
+ HSIC_SYSMON_OP_WRITE,
+ NUM_OPS
+};
+
+struct hsic_sysmon {
+ struct usb_device *udev;
+ struct usb_interface *ifc;
+ __u8 in_epaddr;
+ __u8 out_epaddr;
+ unsigned int pipe[NUM_OPS];
+ struct kref kref;
+ struct platform_device pdev;
+ int id;
+
+ /* debugging counters */
+ atomic_t dbg_bytecnt[NUM_OPS];
+ atomic_t dbg_pending[NUM_OPS];
+};
+static struct hsic_sysmon *hsic_sysmon_devices[NUM_HSIC_SYSMON_DEVS];
+
+static void hsic_sysmon_delete(struct kref *kref)
+{
+ struct hsic_sysmon *hs = container_of(kref, struct hsic_sysmon, kref);
+
+ usb_put_dev(hs->udev);
+ hsic_sysmon_devices[hs->id] = NULL;
+ kfree(hs);
+}
+
+/**
+ * hsic_sysmon_open() - Opens the system monitor bridge.
+ * @id: the HSIC system monitor device to open
+ *
+ * This should only be called after the platform_device "sys_mon" with id
+ * SYSMON_SS_EXT_MODEM has been added. The simplest way to do that is to
+ * register a platform_driver and its probe will be called when the HSIC
+ * device is ready.
+ */
+int hsic_sysmon_open(enum hsic_sysmon_device_id id)
+{
+ struct hsic_sysmon *hs;
+
+ if (id >= NUM_HSIC_SYSMON_DEVS) {
+ pr_err("invalid dev id(%d)", id);
+ return -ENODEV;
+ }
+
+ hs = hsic_sysmon_devices[id];
+ if (!hs) {
+ pr_err("dev is null");
+ return -ENODEV;
+ }
+
+ kref_get(&hs->kref);
+
+ return 0;
+}
+EXPORT_SYMBOL(hsic_sysmon_open);
+
+/**
+ * hsic_sysmon_close() - Closes the system monitor bridge.
+ * @id: the HSIC system monitor device to close
+ */
+void hsic_sysmon_close(enum hsic_sysmon_device_id id)
+{
+ struct hsic_sysmon *hs;
+
+ if (id >= NUM_HSIC_SYSMON_DEVS) {
+ pr_err("invalid dev id(%d)", id);
+ return;
+ }
+
+ hs = hsic_sysmon_devices[id];
+ kref_put(&hs->kref, hsic_sysmon_delete);
+}
+EXPORT_SYMBOL(hsic_sysmon_close);
+
+/**
+ * hsic_sysmon_readwrite() - Common function to send read/write over HSIC
+ */
+static int hsic_sysmon_readwrite(enum hsic_sysmon_device_id id, void *data,
+ size_t len, size_t *actual_len, int timeout,
+ enum hsic_sysmon_op op)
+{
+ struct hsic_sysmon *hs;
+ int ret;
+ const char *opstr = (op == HSIC_SYSMON_OP_READ) ?
+ "read" : "write";
+
+ pr_debug("%s: id:%d, data len:%d, timeout:%d", opstr, id, len, timeout);
+
+ if (id >= NUM_HSIC_SYSMON_DEVS) {
+ pr_err("invalid dev id(%d)", id);
+ return -ENODEV;
+ }
+
+ if (!len) {
+ pr_err("length(%d) must be greater than 0", len);
+ return -EINVAL;
+ }
+
+ hs = hsic_sysmon_devices[id];
+ if (!hs) {
+ pr_err("device was not opened");
+ return -ENODEV;
+ }
+
+ if (!hs->ifc) {
+ dev_err(&hs->udev->dev, "can't %s, device disconnected\n",
+ opstr);
+ return -ENODEV;
+ }
+
+ ret = usb_autopm_get_interface(hs->ifc);
+ if (ret < 0) {
+ dev_err(&hs->udev->dev, "can't %s, autopm_get failed:%d\n",
+ opstr, ret);
+ return ret;
+ }
+
+ atomic_inc(&hs->dbg_pending[op]);
+
+ ret = usb_bulk_msg(hs->udev, hs->pipe[op], data, len, actual_len,
+ timeout);
+
+ atomic_dec(&hs->dbg_pending[op]);
+
+ if (ret)
+ dev_err(&hs->udev->dev,
+ "can't %s, usb_bulk_msg failed, err:%d\n", opstr, ret);
+ else
+ atomic_add(*actual_len, &hs->dbg_bytecnt[op]);
+
+ usb_autopm_put_interface(hs->ifc);
+ return ret;
+}
+
+/**
+ * hsic_sysmon_read() - Read data from the HSIC sysmon interface.
+ * @id: the HSIC system monitor device to open
+ * @data: pointer to caller-allocated buffer to fill in
+ * @len: length in bytes of the buffer
+ * @actual_len: pointer to a location to put the actual length read
+ * in bytes
+ * @timeout: time in msecs to wait for the message to complete before
+ * timing out (if 0 the wait is forever)
+ *
+ * Context: !in_interrupt ()
+ *
+ * Synchronously reads data from the HSIC interface. The call will return
+ * after the read has completed, encountered an error, or timed out. Upon
+ * successful return actual_len will reflect the number of bytes read.
+ *
+ * If successful, it returns 0, otherwise a negative error number. The number
+ * of actual bytes transferred will be stored in the actual_len paramater.
+ */
+int hsic_sysmon_read(enum hsic_sysmon_device_id id, char *data, size_t len,
+ size_t *actual_len, int timeout)
+{
+ return hsic_sysmon_readwrite(id, data, len, actual_len,
+ timeout, HSIC_SYSMON_OP_READ);
+}
+EXPORT_SYMBOL(hsic_sysmon_read);
+
+/**
+ * hsic_sysmon_write() - Write data to the HSIC sysmon interface.
+ * @id: the HSIC system monitor device to open
+ * @data: pointer to caller-allocated buffer to write
+ * @len: length in bytes of the data in buffer to write
+ * @actual_len: pointer to a location to put the actual length written
+ * in bytes
+ * @timeout: time in msecs to wait for the message to complete before
+ * timing out (if 0 the wait is forever)
+ *
+ * Context: !in_interrupt ()
+ *
+ * Synchronously writes data to the HSIC interface. The call will return
+ * after the write has completed, encountered an error, or timed out. Upon
+ * successful return actual_len will reflect the number of bytes written.
+ *
+ * If successful, it returns 0, otherwise a negative error number. The number
+ * of actual bytes transferred will be stored in the actual_len paramater.
+ */
+int hsic_sysmon_write(enum hsic_sysmon_device_id id, const char *data,
+ size_t len, int timeout)
+{
+ size_t actual_len;
+ return hsic_sysmon_readwrite(id, (void *)data, len, &actual_len,
+ timeout, HSIC_SYSMON_OP_WRITE);
+}
+EXPORT_SYMBOL(hsic_sysmon_write);
+
+#if defined(CONFIG_DEBUG_FS)
+#define DEBUG_BUF_SIZE 512
+static ssize_t sysmon_debug_read_stats(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char *buf;
+ int i, ret = 0;
+
+ buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ for (i = 0; i < NUM_HSIC_SYSMON_DEVS; i++) {
+ struct hsic_sysmon *hs = hsic_sysmon_devices[i];
+ if (!hs)
+ continue;
+
+ ret += scnprintf(buf, DEBUG_BUF_SIZE,
+ "---HSIC Sysmon #%d---\n"
+ "epin:%d, epout:%d\n"
+ "bytes to host: %d\n"
+ "bytes to mdm: %d\n"
+ "pending reads: %d\n"
+ "pending writes: %d\n",
+ i, hs->in_epaddr & ~0x80, hs->out_epaddr,
+ atomic_read(
+ &hs->dbg_bytecnt[HSIC_SYSMON_OP_READ]),
+ atomic_read(
+ &hs->dbg_bytecnt[HSIC_SYSMON_OP_WRITE]),
+ atomic_read(
+ &hs->dbg_pending[HSIC_SYSMON_OP_READ]),
+ atomic_read(
+ &hs->dbg_pending[HSIC_SYSMON_OP_WRITE])
+ );
+ }
+
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
+ kfree(buf);
+ return ret;
+}
+
+static ssize_t sysmon_debug_reset_stats(struct file *file,
+ const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int i;
+
+ for (i = 0; i < NUM_HSIC_SYSMON_DEVS; i++) {
+ struct hsic_sysmon *hs = hsic_sysmon_devices[i];
+ if (hs) {
+ atomic_set(&hs->dbg_bytecnt[HSIC_SYSMON_OP_READ], 0);
+ atomic_set(&hs->dbg_bytecnt[HSIC_SYSMON_OP_WRITE], 0);
+ atomic_set(&hs->dbg_pending[HSIC_SYSMON_OP_READ], 0);
+ atomic_set(&hs->dbg_pending[HSIC_SYSMON_OP_WRITE], 0);
+ }
+ }
+
+ return count;
+}
+
+const struct file_operations sysmon_stats_ops = {
+ .read = sysmon_debug_read_stats,
+ .write = sysmon_debug_reset_stats,
+};
+
+static struct dentry *dent;
+
+static void hsic_sysmon_debugfs_init(void)
+{
+ struct dentry *dfile;
+
+ dent = debugfs_create_dir("hsic_sysmon", 0);
+ if (IS_ERR(dent))
+ return;
+
+ dfile = debugfs_create_file("status", 0444, dent, 0, &sysmon_stats_ops);
+ if (!dfile || IS_ERR(dfile))
+ debugfs_remove(dent);
+}
+
+static void hsic_sysmon_debugfs_cleanup(void)
+{
+ if (dent) {
+ debugfs_remove_recursive(dent);
+ dent = NULL;
+ }
+}
+#else
+static inline void hsic_sysmon_debugfs_init(void) { }
+static inline void hsic_sysmon_debugfs_cleanup(void) { }
+#endif
+
+static int
+hsic_sysmon_probe(struct usb_interface *ifc, const struct usb_device_id *id)
+{
+ struct hsic_sysmon *hs;
+ struct usb_host_interface *ifc_desc;
+ struct usb_endpoint_descriptor *ep_desc;
+ int i;
+ int ret = -ENOMEM;
+ __u8 ifc_num;
+
+ pr_debug("id:%lu", id->driver_info);
+
+ ifc_num = ifc->cur_altsetting->desc.bInterfaceNumber;
+
+ /* is this the interface we're looking for? */
+ if (ifc_num != id->driver_info)
+ return -ENODEV;
+
+ hs = kzalloc(sizeof(*hs), GFP_KERNEL);
+ if (!hs) {
+ pr_err("unable to allocate hsic_sysmon");
+ return -ENOMEM;
+ }
+
+ hs->udev = usb_get_dev(interface_to_usbdev(ifc));
+ hs->ifc = ifc;
+ kref_init(&hs->kref);
+
+ ifc_desc = ifc->cur_altsetting;
+ for (i = 0; i < ifc_desc->desc.bNumEndpoints; i++) {
+ ep_desc = &ifc_desc->endpoint[i].desc;
+
+ if (!hs->in_epaddr && usb_endpoint_is_bulk_in(ep_desc)) {
+ hs->in_epaddr = ep_desc->bEndpointAddress;
+ hs->pipe[HSIC_SYSMON_OP_READ] =
+ usb_rcvbulkpipe(hs->udev, hs->in_epaddr);
+ }
+
+ if (!hs->out_epaddr && usb_endpoint_is_bulk_out(ep_desc)) {
+ hs->out_epaddr = ep_desc->bEndpointAddress;
+ hs->pipe[HSIC_SYSMON_OP_WRITE] =
+ usb_sndbulkpipe(hs->udev, hs->out_epaddr);
+ }
+ }
+
+ if (!(hs->in_epaddr && hs->out_epaddr)) {
+ pr_err("could not find bulk in and bulk out endpoints");
+ ret = -ENODEV;
+ goto error;
+ }
+
+ hs->id = HSIC_SYSMON_DEV_EXT_MODEM;
+ hsic_sysmon_devices[HSIC_SYSMON_DEV_EXT_MODEM] = hs;
+ usb_set_intfdata(ifc, hs);
+
+ hs->pdev.name = "sys_mon";
+ hs->pdev.id = SYSMON_SS_EXT_MODEM;
+ platform_device_register(&hs->pdev);
+
+ pr_debug("complete");
+
+ return 0;
+
+error:
+ if (hs)
+ kref_put(&hs->kref, hsic_sysmon_delete);
+
+ return ret;
+}
+
+static void hsic_sysmon_disconnect(struct usb_interface *ifc)
+{
+ struct hsic_sysmon *hs = usb_get_intfdata(ifc);
+
+ platform_device_unregister(&hs->pdev);
+ kref_put(&hs->kref, hsic_sysmon_delete);
+ usb_set_intfdata(ifc, NULL);
+}
+
+static int hsic_sysmon_suspend(struct usb_interface *ifc, pm_message_t message)
+{
+ return 0;
+}
+
+static int hsic_sysmon_resume(struct usb_interface *ifc)
+{
+ return 0;
+}
+
+/* driver_info maps to the interface number corresponding to sysmon */
+static const struct usb_device_id hsic_sysmon_ids[] = {
+ { USB_DEVICE(0x5c6, 0x9048), .driver_info = 1, },
+ { USB_DEVICE(0x5c6, 0x904C), .driver_info = 1, },
+ {} /* terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, hsic_sysmon_ids);
+
+static struct usb_driver hsic_sysmon_driver = {
+ .name = "hsic_sysmon",
+ .probe = hsic_sysmon_probe,
+ .disconnect = hsic_sysmon_disconnect,
+ .suspend = hsic_sysmon_suspend,
+ .resume = hsic_sysmon_resume,
+ .id_table = hsic_sysmon_ids,
+ .supports_autosuspend = 1,
+};
+
+static int __init hsic_sysmon_init(void)
+{
+ int ret;
+
+ ret = usb_register(&hsic_sysmon_driver);
+ if (ret) {
+ pr_err("unable to register " DRIVER_DESC);
+ return ret;
+ }
+
+ hsic_sysmon_debugfs_init();
+ return 0;
+}
+
+static void __exit hsic_sysmon_exit(void)
+{
+ hsic_sysmon_debugfs_cleanup();
+ usb_deregister(&hsic_sysmon_driver);
+}
+
+module_init(hsic_sysmon_init);
+module_exit(hsic_sysmon_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/hsic_sysmon.h b/arch/arm/mach-msm/hsic_sysmon.h
new file mode 100644
index 0000000..aa57b93
--- /dev/null
+++ b/arch/arm/mach-msm/hsic_sysmon.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HSIC_SYSMON_H__
+#define __HSIC_SYSMON_H__
+
+/**
+ * enum hsic_sysmon_device_id - Supported HSIC subsystem devices
+ */
+enum hsic_sysmon_device_id {
+ HSIC_SYSMON_DEV_EXT_MODEM,
+ NUM_HSIC_SYSMON_DEVS
+};
+
+#if defined(CONFIG_MSM_HSIC_SYSMON) || defined(CONFIG_MSM_HSIC_SYSMON_MODULE)
+
+extern int hsic_sysmon_open(enum hsic_sysmon_device_id id);
+extern void hsic_sysmon_close(enum hsic_sysmon_device_id id);
+extern int hsic_sysmon_read(enum hsic_sysmon_device_id id, char *data,
+ size_t len, size_t *actual_len, int timeout);
+extern int hsic_sysmon_write(enum hsic_sysmon_device_id id, const char *data,
+ size_t len, int timeout);
+
+#else /* CONFIG_MSM_HSIC_SYSMON || CONFIG_MSM_HSIC_SYSMON_MODULE */
+
+static inline int hsic_sysmon_open(enum hsic_sysmon_device_id id)
+{
+ return -ENODEV;
+}
+
+static inline void hsic_sysmon_close(enum hsic_sysmon_device_id id) { }
+
+static inline int hsic_sysmon_read(enum hsic_sysmon_device_id id, char *data,
+ size_t len, size_t *actual_len, int timeout)
+{
+ return -ENODEV;
+}
+
+static inline int hsic_sysmon_write(enum hsic_sysmon_device_id id,
+ const char *data, size_t len, int timeout)
+{
+ return -ENODEV;
+}
+
+#endif /* CONFIG_MSM_HSIC_SYSMON || CONFIG_MSM_HSIC_SYSMON_MODULE */
+
+#endif /* __HSIC_SYSMON_H__ */
diff --git a/arch/arm/mach-msm/hsic_sysmon_test.c b/arch/arm/mach-msm/hsic_sysmon_test.c
new file mode 100644
index 0000000..9929cb7
--- /dev/null
+++ b/arch/arm/mach-msm/hsic_sysmon_test.c
@@ -0,0 +1,118 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* add additional information to our printk's */
+#define pr_fmt(fmt) "%s: " fmt "\n", __func__
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#include "hsic_sysmon.h"
+#include "sysmon.h"
+
+#define DRIVER_DESC "HSIC System monitor driver test"
+
+#define RD_BUF_SIZE 4096
+
+struct sysmon_test_dev {
+ int buflen;
+ char buf[RD_BUF_SIZE];
+};
+static struct sysmon_test_dev *sysmon_dev;
+
+static ssize_t sysmon_test_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct sysmon_test_dev *dev = sysmon_dev;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ ret = hsic_sysmon_read(HSIC_SYSMON_DEV_EXT_MODEM, dev->buf, RD_BUF_SIZE,
+ &dev->buflen, 3000);
+ if (!ret)
+ return simple_read_from_buffer(ubuf, count, ppos,
+ dev->buf, dev->buflen);
+
+ return 0;
+}
+
+static ssize_t sysmon_test_write(struct file *file, const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct sysmon_test_dev *dev = sysmon_dev;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (copy_from_user(dev->buf, ubuf, count)) {
+ pr_err("error copying for writing");
+ return 0;
+ }
+
+ ret = hsic_sysmon_write(HSIC_SYSMON_DEV_EXT_MODEM,
+ dev->buf, count, 1000);
+ if (ret < 0) {
+ pr_err("error writing to hsic_sysmon");
+ return ret;
+ }
+
+ return count;
+}
+
+static int sysmon_test_open(struct inode *inode, struct file *file)
+{
+ return hsic_sysmon_open(HSIC_SYSMON_DEV_EXT_MODEM);
+}
+
+static int sysmon_test_release(struct inode *inode, struct file *file)
+{
+ hsic_sysmon_close(HSIC_SYSMON_DEV_EXT_MODEM);
+ return 0;
+}
+
+static struct dentry *dfile;
+const struct file_operations sysmon_test_ops = {
+ .read = sysmon_test_read,
+ .write = sysmon_test_write,
+ .open = sysmon_test_open,
+ .release = sysmon_test_release
+};
+
+static int __init sysmon_test_init(void)
+{
+ sysmon_dev = kzalloc(sizeof(*sysmon_dev), GFP_KERNEL);
+ if (!sysmon_dev)
+ return -ENOMEM;
+
+ dfile = debugfs_create_file("hsic_sysmon_test", 0666, NULL,
+ 0, &sysmon_test_ops);
+ return 0;
+}
+
+static void __exit sysmon_test_exit(void)
+{
+ if (dfile)
+ debugfs_remove(dfile);
+ kfree(sysmon_dev);
+}
+
+module_init(sysmon_test_init);
+module_exit(sysmon_test_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index d0235f3..36cdd86 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -423,6 +423,7 @@
int (*dsi_power_save)(int on);
int (*dsi_client_reset)(void);
int (*get_lane_config)(void);
+ char (*splash_is_enabled)(void);
int target_type;
};
@@ -503,6 +504,12 @@
#endif
};
+struct vcap_platform_data {
+ unsigned *gpios;
+ int num_gpios;
+ struct msm_bus_scale_pdata *bus_client_pdata;
+};
+
#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
struct isp1763_platform_data {
unsigned reset_gpio;
@@ -532,6 +539,7 @@
void vic_handle_irq(struct pt_regs *regs);
void msm_copper_reserve(void);
void msm_copper_very_early(void);
+void msm_copper_init_gpiomux(void);
struct mmc_platform_data;
int msm_add_sdcc(unsigned int controller,
diff --git a/arch/arm/mach-msm/include/mach/camera.h b/arch/arm/mach-msm/include/mach/camera.h
index ef9fbc1..59e55de 100644
--- a/arch/arm/mach-msm/include/mach/camera.h
+++ b/arch/arm/mach-msm/include/mach/camera.h
@@ -669,16 +669,16 @@
int msm_camio_csi_config(struct msm_camera_csi_params *csi_params);
int msm_camio_csiphy_config(struct msm_camera_csiphy_params *csiphy_params);
int msm_camio_csid_config(struct msm_camera_csid_params *csid_params);
-void msm_io_read_interrupt(void);
int add_axi_qos(void);
int update_axi_qos(uint32_t freq);
void release_axi_qos(void);
-void msm_io_w(u32 data, void __iomem *addr);
-void msm_io_w_mb(u32 data, void __iomem *addr);
-u32 msm_io_r(void __iomem *addr);
-u32 msm_io_r_mb(void __iomem *addr);
-void msm_io_dump(void __iomem *addr, int size);
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len);
+void msm_camera_io_w(u32 data, void __iomem *addr);
+void msm_camera_io_w_mb(u32 data, void __iomem *addr);
+u32 msm_camera_io_r(void __iomem *addr);
+u32 msm_camera_io_r_mb(void __iomem *addr);
+void msm_camera_io_dump(void __iomem *addr, int size);
+void msm_camera_io_memcpy(void __iomem *dest_addr,
+ void __iomem *src_addr, u32 len);
void msm_camio_set_perf_lvl(enum msm_bus_perf_setting);
void msm_camio_bus_scale_cfg(
struct msm_bus_scale_pdata *, enum msm_bus_perf_setting);
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index d170f5f..fb7f977 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -186,6 +186,12 @@
#define DMOV_HSUART_GSBI6_RX_CHAN 8
#define DMOV_HSUART_GSBI6_RX_CRCI 11
+#define DMOV_HSUART_GSBI9_TX_CHAN 4
+#define DMOV_HSUART_GSBI9_TX_CRCI 13
+
+#define DMOV_HSUART_GSBI9_RX_CHAN 3
+#define DMOV_HSUART_GSBI9_RX_CRCI 12
+
#elif defined(CONFIG_ARCH_MSM9615)
#define DMOV_GP_CHAN 4
diff --git a/arch/arm/mach-msm/include/mach/mpm.h b/arch/arm/mach-msm/include/mach/mpm.h
index 5cf52b9..10a6fb0 100644
--- a/arch/arm/mach-msm/include/mach/mpm.h
+++ b/arch/arm/mach-msm/include/mach/mpm.h
@@ -17,13 +17,6 @@
#include <linux/types.h>
#include <linux/list.h>
-enum msm_mpm_pin {
- MSM_MPM_PIN_SDC3_DAT1 = 21,
- MSM_MPM_PIN_SDC3_DAT3 = 22,
- MSM_MPM_PIN_SDC4_DAT1 = 23,
- MSM_MPM_PIN_SDC4_DAT3 = 24,
-};
-
#define MSM_MPM_NR_MPM_IRQS 64
struct msm_mpm_device_data {
@@ -46,9 +39,9 @@
void msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data);
#ifdef CONFIG_MSM_MPM
-int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable);
-int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on);
-int msm_mpm_set_pin_type(enum msm_mpm_pin pin, unsigned int flow_type);
+int msm_mpm_enable_pin(unsigned int pin, unsigned int enable);
+int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on);
+int msm_mpm_set_pin_type(unsigned int pin, unsigned int flow_type);
bool msm_mpm_irqs_detectable(bool from_idle);
bool msm_mpm_gpio_irqs_detectable(bool from_idle);
void msm_mpm_enter_sleep(bool from_idle);
@@ -60,11 +53,11 @@
{ return -ENODEV; }
static inline int msm_mpm_set_irq_type(unsigned int irq, unsigned int flow_type)
{ return -ENODEV; }
-static inline int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable)
+static inline int msm_mpm_enable_pin(unsigned int pin, unsigned int enable)
{ return -ENODEV; }
-static inline int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on)
+static inline int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on)
{ return -ENODEV; }
-static inline int msm_mpm_set_pin_type(enum msm_mpm_pin pin,
+static inline int msm_mpm_set_pin_type(unsigned int pin,
unsigned int flow_type)
{ return -ENODEV; }
static inline bool msm_mpm_irqs_detectable(bool from_idle)
diff --git a/arch/arm/mach-msm/mpm.c b/arch/arm/mach-msm/mpm.c
index dccdc8b..b395b61 100644
--- a/arch/arm/mach-msm/mpm.c
+++ b/arch/arm/mach-msm/mpm.c
@@ -328,7 +328,7 @@
/******************************************************************************
* Public functions
*****************************************************************************/
-int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable)
+int msm_mpm_enable_pin(unsigned int pin, unsigned int enable)
{
uint32_t index = MSM_MPM_IRQ_INDEX(pin);
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
@@ -345,7 +345,7 @@
return 0;
}
-int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on)
+int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on)
{
uint32_t index = MSM_MPM_IRQ_INDEX(pin);
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
@@ -362,7 +362,7 @@
return 0;
}
-int msm_mpm_set_pin_type(enum msm_mpm_pin pin, unsigned int flow_type)
+int msm_mpm_set_pin_type(unsigned int pin, unsigned int flow_type)
{
uint32_t index = MSM_MPM_IRQ_INDEX(pin);
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
diff --git a/arch/arm/mach-msm/platsmp-8625.c b/arch/arm/mach-msm/platsmp-8625.c
index 82aeb16..23ca454 100644
--- a/arch/arm/mach-msm/platsmp-8625.c
+++ b/arch/arm/mach-msm/platsmp-8625.c
@@ -120,16 +120,11 @@
raw_spin_unlock(&irq_controller_lock);
}
-void clear_pending_spi(unsigned int irq)
+static void clear_pending_spi(unsigned int irq)
{
- struct irq_data *d = irq_get_irq_data(irq);
- struct irq_chip *c = irq_data_get_irq_chip(d);
-
/* Clear the IRQ from the ENABLE_SET */
- c->irq_mask(d);
local_irq_disable();
gic_clear_spi_pending(irq);
- c->irq_unmask(d);
local_irq_enable();
}
@@ -152,6 +147,13 @@
*/
write_pen_release(-1);
+ /* clear the IPC1(SPI-8) pending SPI */
+ if (power_collapsed) {
+ raise_clear_spi(1, false);
+ clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
+ power_collapsed = 0;
+ }
+
/*
* Synchronise with the boot thread.
*/
@@ -246,13 +248,6 @@
udelay(10);
}
- /* Now we should clear the pending SPI */
- if (power_collapsed) {
- raise_clear_spi(1, false);
- clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
- power_collapsed = 0;
- }
-
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
diff --git a/arch/arm/mach-msm/sysmon.c b/arch/arm/mach-msm/sysmon.c
index 3d3824a..ddb8502 100644
--- a/arch/arm/mach-msm/sysmon.c
+++ b/arch/arm/mach-msm/sysmon.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -24,20 +24,34 @@
#include <mach/msm_smd.h>
#include <mach/subsystem_notif.h>
+#include "hsic_sysmon.h"
#include "sysmon.h"
#define MAX_MSG_LENGTH 50
#define TIMEOUT_MS 5000
+enum transports {
+ TRANSPORT_SMD,
+ TRANSPORT_HSIC,
+};
+
struct sysmon_subsys {
struct mutex lock;
struct smd_channel *chan;
bool chan_open;
struct completion resp_ready;
char rx_buf[MAX_MSG_LENGTH];
+ enum transports transport;
};
-static struct sysmon_subsys subsys[SYSMON_NUM_SS];
+static struct sysmon_subsys subsys[SYSMON_NUM_SS] = {
+ [SYSMON_SS_MODEM].transport = TRANSPORT_SMD,
+ [SYSMON_SS_LPASS].transport = TRANSPORT_SMD,
+ [SYSMON_SS_WCNSS].transport = TRANSPORT_SMD,
+ [SYSMON_SS_DSPS].transport = TRANSPORT_SMD,
+ [SYSMON_SS_Q6FW].transport = TRANSPORT_SMD,
+ [SYSMON_SS_EXT_MODEM].transport = TRANSPORT_HSIC,
+};
static const char *notif_name[SUBSYS_NOTIF_TYPE_COUNT] = {
[SUBSYS_BEFORE_SHUTDOWN] = "before_shutdown",
@@ -46,6 +60,39 @@
[SUBSYS_AFTER_POWERUP] = "after_powerup",
};
+static int sysmon_send_smd(struct sysmon_subsys *ss, char *tx_buf, size_t len)
+{
+ int ret;
+
+ if (!ss->chan_open)
+ return -ENODEV;
+
+ init_completion(&ss->resp_ready);
+ pr_debug("Sending SMD message: %s\n", tx_buf);
+ smd_write(ss->chan, tx_buf, len);
+ ret = wait_for_completion_timeout(&ss->resp_ready,
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int sysmon_send_hsic(struct sysmon_subsys *ss, char *tx_buf, size_t len)
+{
+ int ret;
+ size_t actual_len;
+
+ pr_debug("Sending HSIC message: %s\n", tx_buf);
+ ret = hsic_sysmon_write(HSIC_SYSMON_DEV_EXT_MODEM,
+ tx_buf, len, TIMEOUT_MS);
+ if (ret)
+ return ret;
+ ret = hsic_sysmon_read(HSIC_SYSMON_DEV_EXT_MODEM, ss->rx_buf,
+ ARRAY_SIZE(ss->rx_buf), &actual_len, TIMEOUT_MS);
+ return ret;
+}
+
int sysmon_send_event(enum subsys_id dest_ss, const char *event_ss,
enum subsys_notif_type notif)
{
@@ -58,31 +105,34 @@
event_ss == NULL)
return -EINVAL;
- if (!ss->chan_open)
- return -ENODEV;
-
- mutex_lock(&ss->lock);
- init_completion(&ss->resp_ready);
snprintf(tx_buf, ARRAY_SIZE(tx_buf), "ssr:%s:%s", event_ss,
notif_name[notif]);
- pr_debug("Sending message: %s\n", tx_buf);
- smd_write(ss->chan, tx_buf, ARRAY_SIZE(tx_buf));
- ret = wait_for_completion_timeout(&ss->resp_ready,
- msecs_to_jiffies(TIMEOUT_MS));
- if (!ret) {
- ret = -ETIMEDOUT;
- } else if (strncmp(ss->rx_buf, "ssr:ack", ARRAY_SIZE(ss->rx_buf))) {
- pr_debug("Received response: %s\n", ss->rx_buf);
- ret = -ENOSYS;
- } else {
- ret = 0;
- }
- mutex_unlock(&ss->lock);
+ mutex_lock(&ss->lock);
+ switch (ss->transport) {
+ case TRANSPORT_SMD:
+ ret = sysmon_send_smd(ss, tx_buf, ARRAY_SIZE(tx_buf));
+ break;
+ case TRANSPORT_HSIC:
+ ret = sysmon_send_hsic(ss, tx_buf, ARRAY_SIZE(tx_buf));
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ if (ret)
+ goto out;
+
+ pr_debug("Received response: %s\n", ss->rx_buf);
+ if (strncmp(ss->rx_buf, "ssr:ack", ARRAY_SIZE(ss->rx_buf)))
+ ret = -ENOSYS;
+ else
+ ret = 0;
+out:
+ mutex_unlock(&ss->lock);
return ret;
}
-static void sysmon_notify(void *priv, unsigned int smd_event)
+static void sysmon_smd_notify(void *priv, unsigned int smd_event)
{
struct sysmon_subsys *ss = priv;
@@ -104,44 +154,61 @@
}
}
-static const uint32_t ss_map[SMD_NUM_TYPE] = {
- [SMD_APPS_MODEM] = SYSMON_SS_MODEM,
- [SMD_APPS_QDSP] = SYSMON_SS_LPASS,
- [SMD_APPS_WCNSS] = SYSMON_SS_WCNSS,
- [SMD_APPS_DSPS] = SYSMON_SS_DSPS,
- [SMD_APPS_Q6FW] = SYSMON_SS_Q6FW,
-};
-
static int sysmon_probe(struct platform_device *pdev)
{
struct sysmon_subsys *ss;
int ret;
- if (pdev == NULL)
- return -EINVAL;
-
- if (pdev->id < 0 || pdev->id >= SMD_NUM_TYPE ||
- ss_map[pdev->id] < 0 || ss_map[pdev->id] >= SYSMON_NUM_SS)
+ if (pdev->id < 0 || pdev->id >= SYSMON_NUM_SS)
return -ENODEV;
- ss = &subsys[ss_map[pdev->id]];
+ ss = &subsys[pdev->id];
mutex_init(&ss->lock);
- /* Open and configure the SMD channel */
- ret = smd_named_open_on_edge("sys_mon", pdev->id, &ss->chan,
- ss, sysmon_notify);
- if (ret) {
- pr_err("SMD open failed\n");
- return -ENOSYS;
+ switch (ss->transport) {
+ case TRANSPORT_SMD:
+ if (pdev->id >= SMD_NUM_TYPE)
+ return -EINVAL;
+
+ ret = smd_named_open_on_edge("sys_mon", pdev->id, &ss->chan, ss,
+ sysmon_smd_notify);
+ if (ret) {
+ pr_err("SMD open failed\n");
+ return ret;
+ }
+
+ smd_disable_read_intr(ss->chan);
+ break;
+ case TRANSPORT_HSIC:
+ if (pdev->id < SMD_NUM_TYPE)
+ return -EINVAL;
+
+ ret = hsic_sysmon_open(HSIC_SYSMON_DEV_EXT_MODEM);
+ if (ret) {
+ pr_err("HSIC open failed\n");
+ return ret;
+ }
+ break;
+ default:
+ return -EINVAL;
}
- smd_disable_read_intr(ss->chan);
return 0;
}
static int __devexit sysmon_remove(struct platform_device *pdev)
{
- smd_close(subsys[ss_map[pdev->id]].chan);
+ struct sysmon_subsys *ss = &subsys[pdev->id];
+
+ switch (ss->transport) {
+ case TRANSPORT_SMD:
+ smd_close(ss->chan);
+ break;
+ case TRANSPORT_HSIC:
+ hsic_sysmon_close(HSIC_SYSMON_DEV_EXT_MODEM);
+ break;
+ }
+
return 0;
}
diff --git a/arch/arm/mach-msm/sysmon.h b/arch/arm/mach-msm/sysmon.h
index 429a155..d014187 100644
--- a/arch/arm/mach-msm/sysmon.h
+++ b/arch/arm/mach-msm/sysmon.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -15,21 +15,25 @@
#ifndef __MSM_SYSMON_H
#define __MSM_SYSMON_H
+#include <mach/msm_smd.h>
#include <mach/subsystem_notif.h>
/**
* enum subsys_id - Destination subsystems for events.
*/
enum subsys_id {
- SYSMON_SS_MODEM,
- SYSMON_SS_LPASS,
- SYSMON_SS_WCNSS,
- SYSMON_SS_DSPS,
- SYSMON_SS_Q6FW,
+ /* SMD subsystems */
+ SYSMON_SS_MODEM = SMD_APPS_MODEM,
+ SYSMON_SS_LPASS = SMD_APPS_QDSP,
+ SYSMON_SS_WCNSS = SMD_APPS_WCNSS,
+ SYSMON_SS_DSPS = SMD_APPS_DSPS,
+ SYSMON_SS_Q6FW = SMD_APPS_Q6FW,
+
+ /* Non-SMD subsystems */
+ SYSMON_SS_EXT_MODEM = SMD_NUM_TYPE,
SYSMON_NUM_SS
};
-
/**
* sysmon_send_event() - Notify a subsystem of another's state change.
* @dest_ss: ID of subsystem the notification should be sent to.
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index b3b2b52..2e422c4 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -358,8 +358,6 @@
membank0_size = meminfo.bank[0].size;
membank1_start = meminfo.bank[1].start;
-
- pr_info("m0 size %lx m1 start %lx\n", membank0_size, membank1_start);
}
#endif
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 14cdf13..0364b06 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -1745,8 +1745,10 @@
*/
list_del_init(&dev->kobj.entry);
spin_unlock(&devices_kset->list_lock);
- /* Disable all device's runtime power management */
- pm_runtime_disable(dev);
+
+ /* Don't allow any more runtime suspends */
+ pm_runtime_get_noresume(dev);
+ pm_runtime_barrier(dev);
if (dev->bus && dev->bus->shutdown) {
dev_dbg(dev, "shutdown\n");
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index 77d84fd..efe0241 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -497,6 +497,29 @@
CREATE_MSG_MASK_TBL_ROW(21);
CREATE_MSG_MASK_TBL_ROW(22);
}
+
+static void diag_set_msg_mask(int rt_mask)
+{
+ int first_ssid, last_ssid, i;
+ uint8_t *parse_ptr, *ptr = driver->msg_masks;
+
+ mutex_lock(&driver->diagchar_mutex);
+ while (*(uint32_t *)(ptr + 4)) {
+ first_ssid = *(uint32_t *)ptr;
+ ptr += 4;
+ last_ssid = *(uint32_t *)ptr;
+ ptr += 4;
+ parse_ptr = ptr;
+ pr_debug("diag: updating range %d %d\n", first_ssid, last_ssid);
+ for (i = 0; i < last_ssid - first_ssid + 1; i++) {
+ *(int *)parse_ptr = rt_mask;
+ parse_ptr += 4;
+ }
+ ptr += MAX_SSID_PER_RANGE * 4;
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
static void diag_update_msg_mask(int start, int end , uint8_t *buf)
{
int found = 0;
@@ -587,6 +610,24 @@
mutex_unlock(&driver->diagchar_mutex);
}
+static void diag_disable_log_mask(void)
+{
+ int i = 0;
+ struct mask_info *parse_ptr = (struct mask_info *)(driver->log_masks);
+
+ pr_debug("diag: disable log masks\n");
+ mutex_lock(&driver->diagchar_mutex);
+ for (i = 0; i < MAX_EQUIP_ID; i++) {
+ pr_debug("diag: equip id %d\n", parse_ptr->equip_id);
+ if (!(parse_ptr->equip_id)) /* Reached a null entry */
+ break;
+ memset(driver->log_masks + parse_ptr->index, 0,
+ (parse_ptr->num_items + 7)/8);
+ parse_ptr++;
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
static void diag_update_log_mask(int equip_id, uint8_t *buf, int num_items)
{
uint8_t *temp = buf;
@@ -777,6 +818,10 @@
int wr_size = -ENOMEM, retry_count = 0;
unsigned long flags = 0;
+ if (num_bytes == 0) {
+ pr_debug("diag: event mask not set yet, so no update\n");
+ return;
+ }
/* send event mask update */
driver->event_mask->cmd_type = DIAG_CTRL_MSG_EVENT_MASK;
driver->event_mask->data_len = 7 + num_bytes;
@@ -866,7 +911,7 @@
{
uint16_t subsys_cmd_code;
int subsys_id, ssid_first, ssid_last, ssid_range;
- int packet_type = 1, i, cmd_code;
+ int packet_type = 1, i, cmd_code, rt_mask;
unsigned char *temp = buf;
int data_type;
#if defined(CONFIG_DIAG_OVER_USB)
@@ -902,7 +947,34 @@
} else
buf = temp;
#endif
- } /* Check for set message mask */
+ } /* Disable log masks */
+ else if (*buf == 0x73 && *(int *)(buf+4) == 0) {
+ buf += 8;
+ /* Disable mask for each log code */
+ diag_disable_log_mask();
+ diag_update_userspace_clients(LOG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x73;
+ driver->apps_rsp_buf[1] = 0x0;
+ driver->apps_rsp_buf[2] = 0x0;
+ driver->apps_rsp_buf[3] = 0x0;
+ *(int *)(driver->apps_rsp_buf + 4) = 0x0;
+ if (driver->ch_cntl)
+ diag_send_log_mask_update(driver->ch_cntl,
+ *(int *)buf);
+ if (driver->chqdsp_cntl)
+ diag_send_log_mask_update(driver->chqdsp_cntl,
+ *(int *)buf);
+ if (driver->ch_wcnss_cntl)
+ diag_send_log_mask_update(driver->ch_wcnss_cntl,
+ *(int *)buf);
+ ENCODE_RSP_AND_SEND(7);
+ return 0;
+ } else
+ buf = temp;
+#endif
+ } /* Set runtime message mask */
else if ((*buf == 0x7d) && (*(buf+1) == 0x4)) {
ssid_first = *(uint16_t *)(buf + 2);
ssid_last = *(uint16_t *)(buf + 4);
@@ -930,6 +1002,33 @@
} else
buf = temp;
#endif
+ } /* Set ALL runtime message mask */
+ else if ((*buf == 0x7d) && (*(buf+1) == 0x5)) {
+ rt_mask = *(int *)(buf + 4);
+ diag_set_msg_mask(rt_mask);
+ diag_update_userspace_clients(MSG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x7d; /* cmd_code */
+ driver->apps_rsp_buf[1] = 0x5; /* set subcommand */
+ driver->apps_rsp_buf[2] = 1; /* success */
+ driver->apps_rsp_buf[3] = 0; /* rsvd */
+ *(int *)(driver->apps_rsp_buf + 4) = rt_mask;
+ /* send msg mask update to peripheral */
+ if (driver->ch_cntl)
+ diag_send_msg_mask_update(driver->ch_cntl,
+ ALL_SSID, ALL_SSID, MODEM_PROC);
+ if (driver->chqdsp_cntl)
+ diag_send_msg_mask_update(driver->chqdsp_cntl,
+ ALL_SSID, ALL_SSID, QDSP_PROC);
+ if (driver->ch_wcnss_cntl)
+ diag_send_msg_mask_update(driver->ch_wcnss_cntl,
+ ALL_SSID, ALL_SSID, WCNSS_PROC);
+ ENCODE_RSP_AND_SEND(7);
+ return 0;
+ } else
+ buf = temp;
+#endif
} else if (*buf == 0x82) { /* event mask change */
buf += 4;
diag_event_num_bytes = (*(uint16_t *)buf)/8+1;
@@ -1680,6 +1779,7 @@
diag_debug_buf_idx = 0;
driver->read_len_legacy = 0;
driver->use_device_tree = has_device_tree();
+ spin_lock_init(&diag_cntl_lock);
if (driver->event_mask == NULL) {
driver->event_mask = kzalloc(sizeof(
@@ -1764,6 +1864,7 @@
GFP_KERNEL)) == NULL)
goto err;
diag_create_msg_mask_table();
+ diag_event_num_bytes = 0;
if (driver->log_masks == NULL &&
(driver->log_masks = kzalloc(LOG_MASK_SIZE, GFP_KERNEL)) == NULL)
goto err;
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index c76bfd0..83f402b 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -988,17 +988,47 @@
return status;
}
+/* Find a memory structure attached to an adreno context */
+
+struct kgsl_memdesc *adreno_find_ctxtmem(struct kgsl_device *device,
+ unsigned int pt_base, unsigned int gpuaddr, unsigned int size)
+{
+ struct kgsl_context *context;
+ struct adreno_context *adreno_context = NULL;
+ int next = 0;
+
+ while (1) {
+ context = idr_get_next(&device->context_idr, &next);
+ if (context == NULL)
+ break;
+
+ adreno_context = (struct adreno_context *)context->devctxt;
+
+ if (kgsl_mmu_pt_equal(adreno_context->pagetable, pt_base)) {
+ struct kgsl_memdesc *desc;
+
+ desc = &adreno_context->gpustate;
+ if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size))
+ return desc;
+
+ desc = &adreno_context->context_gmem_shadow.gmemshadow;
+ if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size))
+ return desc;
+ }
+ next = next + 1;
+ }
+
+ return NULL;
+}
+
struct kgsl_memdesc *adreno_find_region(struct kgsl_device *device,
unsigned int pt_base,
unsigned int gpuaddr,
unsigned int size)
{
- struct kgsl_memdesc *result = NULL;
struct kgsl_mem_entry *entry;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_ringbuffer *ringbuffer = &adreno_dev->ringbuffer;
- struct kgsl_context *context;
- int next = 0;
if (kgsl_gpuaddr_in_memdesc(&ringbuffer->buffer_desc, gpuaddr, size))
return &ringbuffer->buffer_desc;
@@ -1018,34 +1048,7 @@
if (entry)
return &entry->memdesc;
- while (1) {
- struct adreno_context *adreno_context = NULL;
- context = idr_get_next(&device->context_idr, &next);
- if (context == NULL)
- break;
-
- adreno_context = (struct adreno_context *)context->devctxt;
-
- if (kgsl_mmu_pt_equal(adreno_context->pagetable, pt_base)) {
- struct kgsl_memdesc *desc;
-
- desc = &adreno_context->gpustate;
- if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size)) {
- result = desc;
- return result;
- }
-
- desc = &adreno_context->context_gmem_shadow.gmemshadow;
- if (kgsl_gpuaddr_in_memdesc(desc, gpuaddr, size)) {
- result = desc;
- return result;
- }
- }
- next = next + 1;
- }
-
- return NULL;
-
+ return adreno_find_ctxtmem(device, pt_base, gpuaddr, size);
}
uint8_t *adreno_convertaddr(struct kgsl_device *device, unsigned int pt_base,
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 4885312..48e70c8 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -128,6 +128,9 @@
uint8_t *adreno_convertaddr(struct kgsl_device *device,
unsigned int pt_base, unsigned int gpuaddr, unsigned int size);
+struct kgsl_memdesc *adreno_find_ctxtmem(struct kgsl_device *device,
+ unsigned int pt_base, unsigned int gpuaddr, unsigned int size);
+
void *adreno_snapshot(struct kgsl_device *device, void *snapshot, int *remain,
int hang);
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index be0fc1d..5f16ff7 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -339,7 +339,6 @@
if (status != 0)
return status;
- adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000C0804);
rb->rptr = 0;
rb->wptr = 0;
diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c
index bca7040..2dc6f6c 100644
--- a/drivers/gpu/msm/adreno_snapshot.c
+++ b/drivers/gpu/msm/adreno_snapshot.c
@@ -454,33 +454,36 @@
static void ib_add_gpu_object(struct kgsl_device *device, unsigned int ptbase,
unsigned int gpuaddr, unsigned int dwords)
{
- int i = 0, ret;
+ int i, ret, rem = dwords;
unsigned int *src = (unsigned int *) adreno_convertaddr(device, ptbase,
gpuaddr, dwords << 2);
if (src == NULL)
return;
- while (i < dwords) {
+ for (i = 0; rem != 0; rem--, i++) {
+ int pktsize;
+
+ if (!pkt_is_type0(src[i]) && !pkt_is_type3(src[i]))
+ continue;
+
+ pktsize = type3_pkt_size(src[i]);
+
+ if ((pktsize + 1) > rem)
+ break;
if (pkt_is_type3(src[i])) {
- if ((dwords - i) < type3_pkt_size(src[i]) + 1)
- goto skip;
-
if (adreno_cmd_is_ib(src[i]))
ib_add_gpu_object(device, ptbase,
src[i + 1], src[i + 2]);
else
ib_parse_type3(device, &src[i], ptbase);
-
- i += type3_pkt_size(src[i]);
} else if (pkt_is_type0(src[i])) {
ib_parse_type0(device, &src[i], ptbase);
- i += type0_pkt_size(src[i]);
}
-skip:
- i++;
+ i += pktsize;
+ rem -= pktsize;
}
ret = kgsl_snapshot_get_object(device, ptbase, gpuaddr, dwords << 2,
@@ -571,7 +574,7 @@
while (index != rb->wptr) {
index--;
- if (index < 0) {
+ if (index < 0) {
index = rb->sizedwords - 2;
/*
@@ -587,7 +590,8 @@
}
/* Break if the current packet is a context switch identifier */
- if (adreno_rb_ctxtswitch(&rbptr[index]))
+ if ((rbptr[index] == cp_nop_packet(1)) &&
+ (rbptr[index + 1] == KGSL_CONTEXT_TO_MEM_IDENTIFIER))
break;
}
@@ -657,17 +661,31 @@
parse_ibs = 0;
if (parse_ibs && adreno_cmd_is_ib(rbptr[index])) {
+ unsigned int ibaddr = rbptr[index + 1];
+ unsigned int ibsize = rbptr[index + 2];
+
/*
- * The IB from CP_IB1_BASE goes into the snapshot, all
+ * This will return non NULL if the IB happens to be
+ * part of the context memory (i.e - context switch
+ * command buffers)
+ */
+
+ struct kgsl_memdesc *memdesc =
+ adreno_find_ctxtmem(device, ptbase, ibaddr,
+ ibsize);
+
+ /*
+ * The IB from CP_IB1_BASE and the IBs for legacy
+ * context switch go into the snapshot all
* others get marked at GPU objects
*/
- if (rbptr[index + 1] == ibbase)
+
+ if (ibaddr == ibbase || memdesc != NULL)
push_object(device, SNAPSHOT_OBJ_TYPE_IB,
- ptbase, rbptr[index + 1],
- rbptr[index + 2]);
+ ptbase, ibaddr, ibsize);
else
- ib_add_gpu_object(device, ptbase,
- rbptr[index + 1], rbptr[index + 2]);
+ ib_add_gpu_object(device, ptbase, ibaddr,
+ ibsize);
}
index = index + 1;
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 693aa74..a93529a 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -617,7 +617,6 @@
mutex_lock(&device->mutex);
device->pwrctrl.restore_slumber = 0;
kgsl_pwrctrl_wake(device);
- kgsl_pwrctrl_pwrlevel_change(device, KGSL_PWRLEVEL_TURBO);
mutex_unlock(&device->mutex);
kgsl_check_idle(device);
KGSL_PWR_WARN(device, "late resume end\n");
@@ -1349,7 +1348,7 @@
goto error;
}
- result = kgsl_sharedmem_vmalloc_user(&entry->memdesc,
+ result = kgsl_sharedmem_page_alloc_user(&entry->memdesc,
private->pagetable, len,
param->flags);
if (result != 0)
@@ -1360,7 +1359,7 @@
result = kgsl_sharedmem_map_vma(vma, &entry->memdesc);
if (result) {
KGSL_CORE_ERR("kgsl_sharedmem_map_vma failed: %d\n", result);
- goto error_free_vmalloc;
+ goto error_free_alloc;
}
param->gpuaddr = entry->memdesc.gpuaddr;
@@ -1376,7 +1375,7 @@
kgsl_check_idle(dev_priv->device);
return 0;
-error_free_vmalloc:
+error_free_alloc:
kgsl_sharedmem_free(&entry->memdesc);
error_free_entry:
@@ -1675,11 +1674,8 @@
struct scatterlist *s;
unsigned long flags;
- if (kgsl_ion_client == NULL) {
- kgsl_ion_client = msm_ion_client_create(UINT_MAX, KGSL_NAME);
- if (kgsl_ion_client == NULL)
- return -ENODEV;
- }
+ if (IS_ERR_OR_NULL(kgsl_ion_client))
+ return -ENODEV;
handle = ion_import_fd(kgsl_ion_client, fd);
if (IS_ERR_OR_NULL(handle))
@@ -2441,6 +2437,8 @@
if (status)
goto error;
+ kgsl_ion_client = msm_ion_client_create(UINT_MAX, KGSL_NAME);
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
device->iomemname);
if (res == NULL) {
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index fcd8448..5212d0f 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -33,6 +33,9 @@
#define KGSL_MEMSTORE_MAX (KGSL_MEMSTORE_SIZE / \
sizeof(struct kgsl_devmemstore) - 1)
+/* Timestamp window used to detect rollovers */
+#define KGSL_TIMESTAMP_WINDOW 0x80000000
+
/*cache coherency ops */
#define DRM_KGSL_GEM_CACHE_OP_TO_DEV 0x0001
#define DRM_KGSL_GEM_CACHE_OP_FROM_DEV 0x0002
@@ -96,6 +99,8 @@
struct {
unsigned int vmalloc;
unsigned int vmalloc_max;
+ unsigned int page_alloc;
+ unsigned int page_alloc_max;
unsigned int coherent;
unsigned int coherent_max;
unsigned int mapped;
@@ -203,17 +208,25 @@
}
return 0;
}
+
+static inline void *kgsl_memdesc_map(struct kgsl_memdesc *memdesc)
+{
+ if (memdesc->hostptr == NULL && memdesc->ops->map_kernel_mem)
+ memdesc->ops->map_kernel_mem(memdesc);
+
+ return memdesc->hostptr;
+}
+
static inline uint8_t *kgsl_gpuaddr_to_vaddr(struct kgsl_memdesc *memdesc,
unsigned int gpuaddr)
{
- if (memdesc->gpuaddr == 0 ||
- gpuaddr < memdesc->gpuaddr ||
- gpuaddr >= (memdesc->gpuaddr + memdesc->size) ||
- (NULL == memdesc->hostptr && memdesc->ops->map_kernel_mem &&
- memdesc->ops->map_kernel_mem(memdesc)))
- return NULL;
+ void *hostptr = NULL;
- return memdesc->hostptr + (gpuaddr - memdesc->gpuaddr);
+ if ((gpuaddr >= memdesc->gpuaddr) &&
+ (gpuaddr < (memdesc->gpuaddr + memdesc->size)))
+ hostptr = kgsl_memdesc_map(memdesc);
+
+ return hostptr != NULL ? hostptr + (gpuaddr - memdesc->gpuaddr) : NULL;
}
static inline int timestamp_cmp(unsigned int new, unsigned int old)
@@ -223,7 +236,7 @@
if (ts_diff == 0)
return 0;
- return ((ts_diff > 0) || (ts_diff < -25000)) ? 1 : -1;
+ return ((ts_diff > 0) || (ts_diff < -KGSL_TIMESTAMP_WINDOW)) ? 1 : -1;
}
static inline void
diff --git a/drivers/gpu/msm/kgsl_drm.c b/drivers/gpu/msm/kgsl_drm.c
index 33f4b95..66ac08f 100644
--- a/drivers/gpu/msm/kgsl_drm.c
+++ b/drivers/gpu/msm/kgsl_drm.c
@@ -263,7 +263,7 @@
priv->type & DRM_KGSL_GEM_CACHE_MASK)
list_add(&priv->list, &kgsl_mem_list);
- result = kgsl_sharedmem_vmalloc_user(&priv->memdesc,
+ result = kgsl_sharedmem_page_alloc_user(&priv->memdesc,
priv->pagetable,
obj->size * priv->bufcount, 0);
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 17f978e..6fa7da2 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -505,6 +505,7 @@
}
pwr->num_pwrlevels = pdata->num_levels;
pwr->active_pwrlevel = pdata->init_level;
+ pwr->default_pwrlevel = pdata->init_level;
for (i = 0; i < pdata->num_levels; i++) {
pwr->pwrlevels[i].gpu_freq =
(pdata->pwrlevel[i].gpu_freq > 0) ?
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index 7dd429f..a677fec 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -46,6 +46,7 @@
struct kgsl_pwrlevel pwrlevels[KGSL_MAX_PWRLEVELS];
unsigned int active_pwrlevel;
int thermal_pwrlevel;
+ unsigned int default_pwrlevel;
unsigned int num_pwrlevels;
unsigned int interval_timeout;
bool strtstp_sleepwake;
diff --git a/drivers/gpu/msm/kgsl_pwrscale_trustzone.c b/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
index 4b8c938..e0825c3 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_trustzone.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -116,7 +116,7 @@
priv->governor == TZ_GOVERNOR_ONDEMAND &&
device->pwrctrl.restore_slumber == 0)
kgsl_pwrctrl_pwrlevel_change(device,
- device->pwrctrl.thermal_pwrlevel);
+ device->pwrctrl.default_pwrlevel);
}
static void tz_idle(struct kgsl_device *device, struct kgsl_pwrscale *pwrscale)
diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c
index 63c24f1..a51f29f 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.c
+++ b/drivers/gpu/msm/kgsl_sharedmem.c
@@ -203,6 +203,10 @@
val = kgsl_driver.stats.vmalloc;
else if (!strncmp(attr->attr.name, "vmalloc_max", 11))
val = kgsl_driver.stats.vmalloc_max;
+ else if (!strncmp(attr->attr.name, "page_alloc", 10))
+ val = kgsl_driver.stats.page_alloc;
+ else if (!strncmp(attr->attr.name, "page_alloc_max", 14))
+ val = kgsl_driver.stats.page_alloc_max;
else if (!strncmp(attr->attr.name, "coherent", 8))
val = kgsl_driver.stats.coherent;
else if (!strncmp(attr->attr.name, "coherent_max", 12))
@@ -232,6 +236,8 @@
DEVICE_ATTR(vmalloc, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(vmalloc_max, 0444, kgsl_drv_memstat_show, NULL);
+DEVICE_ATTR(page_alloc, 0444, kgsl_drv_memstat_show, NULL);
+DEVICE_ATTR(page_alloc_max, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(coherent, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(coherent_max, 0444, kgsl_drv_memstat_show, NULL);
DEVICE_ATTR(mapped, 0444, kgsl_drv_memstat_show, NULL);
@@ -241,6 +247,8 @@
static const struct device_attribute *drv_attr_list[] = {
&dev_attr_vmalloc,
&dev_attr_vmalloc_max,
+ &dev_attr_page_alloc,
+ &dev_attr_page_alloc_max,
&dev_attr_coherent,
&dev_attr_coherent_max,
&dev_attr_mapped,
@@ -295,7 +303,7 @@
}
#endif
-static int kgsl_vmalloc_vmfault(struct kgsl_memdesc *memdesc,
+static int kgsl_page_alloc_vmfault(struct kgsl_memdesc *memdesc,
struct vm_area_struct *vma,
struct vm_fault *vmf)
{
@@ -316,18 +324,20 @@
return 0;
}
-static int kgsl_vmalloc_vmflags(struct kgsl_memdesc *memdesc)
+static int kgsl_page_alloc_vmflags(struct kgsl_memdesc *memdesc)
{
return VM_RESERVED | VM_DONTEXPAND;
}
-static void kgsl_vmalloc_free(struct kgsl_memdesc *memdesc)
+static void kgsl_page_alloc_free(struct kgsl_memdesc *memdesc)
{
int i = 0;
struct scatterlist *sg;
- kgsl_driver.stats.vmalloc -= memdesc->size;
- if (memdesc->hostptr)
+ kgsl_driver.stats.page_alloc -= memdesc->size;
+ if (memdesc->hostptr) {
vunmap(memdesc->hostptr);
+ kgsl_driver.stats.vmalloc -= memdesc->size;
+ }
if (memdesc->sg)
for_each_sg(memdesc->sg, sg, memdesc->sglen, i)
__free_page(sg_page(sg));
@@ -339,13 +349,14 @@
}
/*
- * kgsl_vmalloc_map_kernel - Map the memory in memdesc to kernel address space
+ * kgsl_page_alloc_map_kernel - Map the memory in memdesc to kernel address
+ * space
*
* @memdesc - The memory descriptor which contains information about the memory
*
* Return: 0 on success else error code
*/
-static int kgsl_vmalloc_map_kernel(struct kgsl_memdesc *memdesc)
+static int kgsl_page_alloc_map_kernel(struct kgsl_memdesc *memdesc)
{
if (!memdesc->hostptr) {
pgprot_t page_prot = pgprot_writecombine(PAGE_KERNEL);
@@ -363,6 +374,8 @@
pages[i] = sg_page(sg);
memdesc->hostptr = vmap(pages, memdesc->sglen,
VM_IOREMAP, page_prot);
+ KGSL_STATS_ADD(memdesc->size, kgsl_driver.stats.vmalloc,
+ kgsl_driver.stats.vmalloc_max);
vfree(pages);
}
if (!memdesc->hostptr)
@@ -410,13 +423,13 @@
}
/* Global - also used by kgsl_drm.c */
-struct kgsl_memdesc_ops kgsl_vmalloc_ops = {
- .free = kgsl_vmalloc_free,
- .vmflags = kgsl_vmalloc_vmflags,
- .vmfault = kgsl_vmalloc_vmfault,
- .map_kernel_mem = kgsl_vmalloc_map_kernel,
+struct kgsl_memdesc_ops kgsl_page_alloc_ops = {
+ .free = kgsl_page_alloc_free,
+ .vmflags = kgsl_page_alloc_vmflags,
+ .vmfault = kgsl_page_alloc_vmfault,
+ .map_kernel_mem = kgsl_page_alloc_map_kernel,
};
-EXPORT_SYMBOL(kgsl_vmalloc_ops);
+EXPORT_SYMBOL(kgsl_page_alloc_ops);
static struct kgsl_memdesc_ops kgsl_ebimem_ops = {
.free = kgsl_ebimem_free,
@@ -450,7 +463,7 @@
EXPORT_SYMBOL(kgsl_cache_range_op);
static int
-_kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
+_kgsl_sharedmem_page_alloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable,
size_t size, unsigned int protflags)
{
@@ -461,11 +474,13 @@
memdesc->size = size;
memdesc->pagetable = pagetable;
memdesc->priv = KGSL_MEMFLAGS_CACHED;
- memdesc->ops = &kgsl_vmalloc_ops;
+ memdesc->ops = &kgsl_page_alloc_ops;
memdesc->sg = kgsl_sg_alloc(sglen);
if (memdesc->sg == NULL) {
+ KGSL_CORE_ERR("vmalloc(%d) failed\n",
+ sglen * sizeof(struct scatterlist));
ret = -ENOMEM;
goto done;
}
@@ -494,8 +509,8 @@
if (ret)
goto done;
- KGSL_STATS_ADD(size, kgsl_driver.stats.vmalloc,
- kgsl_driver.stats.vmalloc_max);
+ KGSL_STATS_ADD(size, kgsl_driver.stats.page_alloc,
+ kgsl_driver.stats.page_alloc_max);
order = get_order(size);
@@ -510,7 +525,7 @@
}
int
-kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
+kgsl_sharedmem_page_alloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size)
{
int ret = 0;
@@ -518,18 +533,18 @@
size = ALIGN(size, PAGE_SIZE * 2);
- ret = _kgsl_sharedmem_vmalloc(memdesc, pagetable, size,
+ ret = _kgsl_sharedmem_page_alloc(memdesc, pagetable, size,
GSL_PT_PAGE_RV | GSL_PT_PAGE_WV);
if (!ret)
- ret = kgsl_vmalloc_map_kernel(memdesc);
+ ret = kgsl_page_alloc_map_kernel(memdesc);
if (ret)
kgsl_sharedmem_free(memdesc);
return ret;
}
-EXPORT_SYMBOL(kgsl_sharedmem_vmalloc);
+EXPORT_SYMBOL(kgsl_sharedmem_page_alloc);
int
-kgsl_sharedmem_vmalloc_user(struct kgsl_memdesc *memdesc,
+kgsl_sharedmem_page_alloc_user(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable,
size_t size, int flags)
{
@@ -541,10 +556,10 @@
if (!(flags & KGSL_MEMFLAGS_GPUREADONLY))
protflags |= GSL_PT_PAGE_WV;
- return _kgsl_sharedmem_vmalloc(memdesc, pagetable, size,
+ return _kgsl_sharedmem_page_alloc(memdesc, pagetable, size,
protflags);
}
-EXPORT_SYMBOL(kgsl_sharedmem_vmalloc_user);
+EXPORT_SYMBOL(kgsl_sharedmem_page_alloc_user);
int
kgsl_sharedmem_alloc_coherent(struct kgsl_memdesc *memdesc, size_t size)
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index def29b3..fb8dd95 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -32,12 +32,12 @@
/** Set if the memdesc is mapped into all pagetables */
#define KGSL_MEMFLAGS_GLOBAL 0x00000002
-extern struct kgsl_memdesc_ops kgsl_vmalloc_ops;
+extern struct kgsl_memdesc_ops kgsl_page_alloc_ops;
-int kgsl_sharedmem_vmalloc(struct kgsl_memdesc *memdesc,
+int kgsl_sharedmem_page_alloc(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size);
-int kgsl_sharedmem_vmalloc_user(struct kgsl_memdesc *memdesc,
+int kgsl_sharedmem_page_alloc_user(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable,
size_t size, int flags);
@@ -134,7 +134,7 @@
{
if (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_NONE)
return kgsl_sharedmem_ebimem(memdesc, pagetable, size);
- return kgsl_sharedmem_vmalloc(memdesc, pagetable, size);
+ return kgsl_sharedmem_page_alloc(memdesc, pagetable, size);
}
static inline int
@@ -145,7 +145,7 @@
if (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_NONE)
return kgsl_sharedmem_ebimem_user(memdesc, pagetable, size,
flags);
- return kgsl_sharedmem_vmalloc_user(memdesc, pagetable, size, flags);
+ return kgsl_sharedmem_page_alloc_user(memdesc, pagetable, size, flags);
}
static inline int
diff --git a/drivers/gpu/msm/kgsl_snapshot.c b/drivers/gpu/msm/kgsl_snapshot.c
index c24576d..3efafee 100644
--- a/drivers/gpu/msm/kgsl_snapshot.c
+++ b/drivers/gpu/msm/kgsl_snapshot.c
@@ -28,6 +28,7 @@
unsigned int gpuaddr;
unsigned int ptbase;
unsigned int size;
+ unsigned int offset;
int type;
struct kgsl_mem_entry *entry;
struct list_head node;
@@ -229,7 +230,7 @@
* then offset the source pointer
*/
- offset = obj->gpuaddr - obj->entry->memdesc.gpuaddr;
+ offset = obj->offset;
/*
* Then adjust it to account for the offset for the output
@@ -333,6 +334,12 @@
}
}
+ if (kgsl_memdesc_map(&entry->memdesc) == NULL) {
+ KGSL_DRV_ERR(device, "Unable to map GPU buffer %X\n",
+ gpuaddr);
+ return 0;
+ }
+
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
if (obj == NULL) {
@@ -348,6 +355,7 @@
obj->gpuaddr = gpuaddr;
obj->ptbase = ptbase;
obj->size = size;
+ obj->offset = offset;
list_add(&obj->node, &device->snapshot_obj_list);
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 36c370e..3762bac 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -777,7 +777,7 @@
config SENSORS_MSM_ADC
tristate "MSM ADC Driver for current measurement"
- depends on ARCH_MSM7X30 || ARCH_MSM8X60 || ARCH_FSM9XXX
+ depends on ARCH_MSM7X30 || ARCH_MSM8X60 || ARCH_FSM9XXX || ARCH_MSM7X27A
default n
help
Provides interface for measuring the ADC's on AMUX channels of XOADC,
diff --git a/drivers/hwmon/msm_adc.c b/drivers/hwmon/msm_adc.c
index 39bfc3a..e4a607f 100644
--- a/drivers/hwmon/msm_adc.c
+++ b/drivers/hwmon/msm_adc.c
@@ -41,6 +41,9 @@
#define MSM_ADC_DALRC_CONV_TIMEOUT (5 * HZ) /* 5 seconds */
+#define MSM_8x25_ADC_DEV_ID 0
+#define MSM_8x25_CHAN_ID 16
+
enum dal_error {
DAL_ERROR_INVALID_DEVICE_IDX = 1,
DAL_ERROR_INVALID_CHANNEL_IDX,
@@ -1171,18 +1174,26 @@
goto dev_init_err;
}
- /* DAL device lookup */
- rc = msm_adc_getinputproperties(msm_adc, adc_dev->name,
+ if (!pdata->target_hw == MSM_8x25) {
+ /* DAL device lookup */
+ rc = msm_adc_getinputproperties(msm_adc, adc_dev->name,
&target);
- if (rc) {
- dev_err(&pdev->dev, "No such DAL device[%s]\n",
+ if (rc) {
+ dev_err(&pdev->dev, "No such DAL device[%s]\n",
adc_dev->name);
- goto dev_init_err;
+ goto dev_init_err;
+ }
+
+ adc_dev->transl.dal_dev_idx = target.dal.dev_idx;
+ adc_dev->nchans = target.dal.chan_idx;
+ } else {
+ /* On targets prior to MSM7x30 the remote driver has
+ only the channel list and no device id. */
+ adc_dev->transl.dal_dev_idx = MSM_8x25_ADC_DEV_ID;
+ adc_dev->nchans = MSM_8x25_CHAN_ID;
}
- adc_dev->transl.dal_dev_idx = target.dal.dev_idx;
adc_dev->transl.hwmon_dev_idx = i;
- adc_dev->nchans = target.dal.chan_idx;
adc_dev->transl.hwmon_start = hwmon_cntr;
adc_dev->transl.hwmon_end = hwmon_cntr + adc_dev->nchans - 1;
hwmon_cntr += adc_dev->nchans;
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index 212e5d5..741c3a1 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -1465,6 +1465,7 @@
xfr_buf[1] = GET_ABS_VAL(band_low);
xfr_buf[2] = RSH_DATA(band_high, 8);
xfr_buf[3] = GET_ABS_VAL(band_high);
+ xfr_buf[4] = 0; /* Active LOW */
retval = sync_write_xfr(radio, RADIO_CONFIG, xfr_buf);
if (retval < 0) {
FMDERR("Could not set regional settings\n");
@@ -3037,8 +3038,8 @@
} else if (ctrl->value == FM_ANALOG_PATH) {
FMDBG("Analog audio path enabled ...\n");
retval = tavarua_set_audio_path(
- TAVARUA_AUDIO_OUT_ANALOG_ON,
- TAVARUA_AUDIO_OUT_DIGITAL_OFF);
+ TAVARUA_AUDIO_OUT_DIGITAL_OFF,
+ TAVARUA_AUDIO_OUT_ANALOG_ON);
if (retval < 0) {
FMDERR("Error in tavarua_set_audio_path"
" %d\n", retval);
@@ -3891,10 +3892,27 @@
{
struct tavarua_device *radio = private_data;
int rx_on = radio->registers[RDCTRL] & FM_RECV;
+ int retval = 0;
if (!radio)
return -ENOMEM;
/* RX */
FMDBG("%s: digital: %d analog: %d\n", __func__, digital_on, analog_on);
+ if ((radio->pdata != NULL) && (radio->pdata->config_i2s_gpio != NULL)) {
+ if (digital_on) {
+ retval = radio->pdata->config_i2s_gpio(FM_I2S_ON);
+ if (retval) {
+ pr_err("%s: config_i2s_gpio failed\n",
+ __func__);
+ }
+ } else {
+ retval = radio->pdata->config_i2s_gpio(FM_I2S_OFF);
+ if (retval) {
+ pr_err("%s: config_i2s_gpio failed\n",
+ __func__);
+ }
+ }
+ }
+
SET_REG_FIELD(radio->registers[AUDIOCTRL],
((rx_on && analog_on) ? 1 : 0),
AUDIORX_ANALOG_OFFSET,
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 95255fe..07a31a3 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -569,6 +569,14 @@
Say Y here if you want to test video apps or debug V4L devices.
In doubt, say N.
+config MSM_VCAP
+ tristate "Qualcomm MSM VCAP"
+ depends on VIDEO_DEV && VIDEO_V4L2
+ default n
+ ---help---
+ Enables VCAP driver. This device allows for video capture and
+ video processing using the v4l2 api
+
source "drivers/media/video/davinci/Kconfig"
source "drivers/media/video/omap/Kconfig"
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index c4b240f..65a2348 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -156,6 +156,8 @@
obj-$(CONFIG_VIDEO_MEM2MEM_TESTDEV) += mem2mem_testdev.o
obj-$(CONFIG_VIDEO_CX23885) += cx23885/
+obj-$(CONFIG_MSM_VCAP) += vcap_v4l2.o
+obj-$(CONFIG_MSM_VCAP) += vcap_vc.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_OMAP2) += omap2cam.o
diff --git a/drivers/media/video/msm/Makefile b/drivers/media/video/msm/Makefile
index ca80fc1..3dea4e9 100644
--- a/drivers/media/video/msm/Makefile
+++ b/drivers/media/video/msm/Makefile
@@ -3,32 +3,33 @@
CFLAGS_REMOVE_msm_vfe8x.o = -Wframe-larger-than=1024
endif
+obj-$(CONFIG_MSM_CAMERA) += io/
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
EXTRA_CFLAGS += -Idrivers/media/video/msm/csi
EXTRA_CFLAGS += -Idrivers/media/video/msm/io
EXTRA_CFLAGS += -Idrivers/media/video/msm/sensors
obj-$(CONFIG_MSM_CAMERA) += msm_isp.o msm.o msm_mem.o msm_mctl.o msm_mctl_buf.o msm_mctl_pp.o
- obj-$(CONFIG_MSM_CAMERA) += io/ sensors/ actuators/ csi/
+ obj-$(CONFIG_MSM_CAMERA) += sensors/ actuators/ csi/
else
obj-$(CONFIG_MSM_CAMERA) += msm_camera.o
endif
obj-$(CONFIG_MSM_CAMERA) += msm_axi_qos.o gemini/
obj-$(CONFIG_MSM_CAMERA_FLASH) += flash.o
-obj-$(CONFIG_ARCH_MSM_ARM11) += msm_vfe7x.o msm_io7x.o
+obj-$(CONFIG_ARCH_MSM_ARM11) += msm_vfe7x.o
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
- obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a_v4l2.o msm_io_7x27a_v4l2.o
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a_v4l2.o
else
- obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a.o msm_io_7x27a.o
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_vfe7x27a.o
endif
-obj-$(CONFIG_ARCH_QSD8X50) += msm_vfe8x.o msm_vfe8x_proc.o msm_io8x.o
+obj-$(CONFIG_ARCH_QSD8X50) += msm_vfe8x.o msm_vfe8x_proc.o
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
- obj-$(CONFIG_ARCH_MSM8X60) += msm_io_vfe31_v4l2.o msm_vfe31_v4l2.o msm_vpe.o
- obj-$(CONFIG_ARCH_MSM7X30) += msm_io_vfe31_v4l2.o msm_vfe31_v4l2.o msm_vpe.o msm_axi_qos.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_vfe31_v4l2.o msm_vpe.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_vfe31_v4l2.o msm_vpe.o msm_axi_qos.o
else
- obj-$(CONFIG_ARCH_MSM8X60) += msm_vfe31.o msm_io_8x60.o msm_vpe1.o
- obj-$(CONFIG_ARCH_MSM7X30) += msm_vfe31.o msm_io_vfe31.o msm_vpe1.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_vfe31.o msm_vpe1.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_vfe31.o msm_vpe1.o
endif
-obj-$(CONFIG_ARCH_MSM8960) += msm_io_8960.o msm_vfe32.o msm_vpe.o
+obj-$(CONFIG_ARCH_MSM8960) += msm_vfe32.o msm_vpe.o
obj-$(CONFIG_MT9T013) += mt9t013.o mt9t013_reg.o
obj-$(CONFIG_SN12M0PZ) += sn12m0pz.o sn12m0pz_reg.o
obj-$(CONFIG_MT9P012) += mt9p012_reg.o
diff --git a/drivers/media/video/msm/csi/msm_csic.c b/drivers/media/video/msm/csi/msm_csic.c
index 1ca4fa3..00828c9 100644
--- a/drivers/media/video/msm/csi/msm_csic.c
+++ b/drivers/media/video/msm/csi/msm_csic.c
@@ -150,9 +150,9 @@
csic_params = cfg_params->parms;
/* Enable error correction for DATA lane. Applies to all data lanes */
- msm_io_w(0x4, csicbase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csicbase + MIPI_PHY_CONTROL);
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csicbase + MIPI_PROTOCOL_CONTROL);
val = MIPI_PROTOCOL_CONTROL_LONG_PACKET_HEADER_CAPTURE_BMSK |
@@ -163,7 +163,7 @@
val |= csic_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csicbase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PROTOCOL_CONTROL);
val = (csic_params->settle_cnt <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
@@ -172,48 +172,48 @@
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
for (i = 0; i < csic_params->lane_cnt; i++)
- msm_io_w(val, csicbase + MIPI_PHY_D0_CONTROL2 + i * 4);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csicbase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csicbase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_D0_CONTROL);
val = (0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csicbase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csicbase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csicbase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csicbase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csicbase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csicbase + MIPI_PHY_D3_CONTROL);
/* program number of lanes and lane mapping */
switch (csic_params->lane_cnt) {
case 1:
- msm_io_w(csic_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x4,
csicbase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csic_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x5,
csicbase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csic_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x6,
csicbase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csic_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csic_params->lane_assign << 8 | 0x7,
csicbase + MIPI_CAMERA_CNTL);
break;
}
- msm_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits*/
- msm_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xF077F3C0, csicbase + MIPI_INTERRUPT_STATUS);
return rc;
}
@@ -224,11 +224,11 @@
struct csic_device *csic_dev = data;
pr_info("msm_csic_irq: %x\n", (unsigned int)csic_dev->base);
- irq = msm_io_r(csic_dev->base + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csic_dev->base + MIPI_INTERRUPT_STATUS);
pr_info("%s MIPI_INTERRUPT_STATUS = 0x%x 0x%x\n",
- __func__, irq,
- msm_io_r(csic_dev->base + MIPI_PROTOCOL_CONTROL));
- msm_io_w(irq, csic_dev->base + MIPI_INTERRUPT_STATUS);
+ __func__, irq,
+ msm_camera_io_r(csic_dev->base + MIPI_PROTOCOL_CONTROL));
+ msm_camera_io_w(irq, csic_dev->base + MIPI_INTERRUPT_STATUS);
/* TODO: Needs to send this info to upper layers */
if ((irq >> 19) & 0x1)
@@ -305,26 +305,26 @@
val = 0x0;
if (csic_dev->base != NULL) {
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csic_dev->base + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_CL_CONTROL);
msleep(20);
- val = msm_io_r(csic_dev->base + MIPI_PHY_D1_CONTROL);
+ val = msm_camera_io_r(csic_dev->base + MIPI_PHY_D1_CONTROL);
val &=
~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT)
|(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csic_dev->base + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
- msm_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_MASK);
- msm_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_STATUS);
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0x0, csic_dev->base + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csic_dev->base + MIPI_PROTOCOL_CONTROL);
- msm_io_w(0xE400, csic_dev->base + MIPI_CAMERA_CNTL);
+ msm_camera_io_w(0xE400, csic_dev->base + MIPI_CAMERA_CNTL);
}
}
diff --git a/drivers/media/video/msm/csi/msm_csid.c b/drivers/media/video/msm/csi/msm_csid.c
index e531089..21bcac0 100644
--- a/drivers/media/video/msm/csi/msm_csid.c
+++ b/drivers/media/video/msm/csi/msm_csid.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -68,15 +68,15 @@
__func__, csid_lut_params->vc_cfg[i].dt);
return rc;
}
- val = msm_io_r(csidbase + CSID_CID_LUT_VC_0_ADDR +
+ val = msm_camera_io_r(csidbase + CSID_CID_LUT_VC_0_ADDR +
(csid_lut_params->vc_cfg[i].cid >> 2) * 4)
& ~(0xFF << csid_lut_params->vc_cfg[i].cid * 8);
val |= csid_lut_params->vc_cfg[i].dt <<
csid_lut_params->vc_cfg[i].cid * 8;
- msm_io_w(val, csidbase + CSID_CID_LUT_VC_0_ADDR +
+ msm_camera_io_w(val, csidbase + CSID_CID_LUT_VC_0_ADDR +
(csid_lut_params->vc_cfg[i].cid >> 2) * 4);
val = csid_lut_params->vc_cfg[i].decode_format << 4 | 0x3;
- msm_io_w(val, csidbase + CSID_CID_n_CFG_ADDR +
+ msm_camera_io_w(val, csidbase + CSID_CID_n_CFG_ADDR +
(csid_lut_params->vc_cfg[i].cid * 4));
}
return rc;
@@ -100,15 +100,15 @@
val |= 0x1 << 12;
val |= 0x1 << 13;
val |= 0x1 << 28;
- msm_io_w(val, csidbase + CSID_CORE_CTRL_ADDR);
+ msm_camera_io_w(val, csidbase + CSID_CORE_CTRL_ADDR);
rc = msm_csid_cid_lut(&csid_params->lut_params, csidbase);
if (rc < 0)
return rc;
val = ((1 << csid_params->lane_cnt) - 1) << 20;
- msm_io_w(0x7f010800 | val, csidbase + CSID_IRQ_MASK_ADDR);
- msm_io_w(0x7f010800 | val, csidbase + CSID_IRQ_CLEAR_CMD_ADDR);
+ msm_camera_io_w(0x7f010800 | val, csidbase + CSID_IRQ_MASK_ADDR);
+ msm_camera_io_w(0x7f010800 | val, csidbase + CSID_IRQ_CLEAR_CMD_ADDR);
msleep(20);
return rc;
@@ -118,18 +118,18 @@
{
uint32_t irq;
struct csid_device *csid_dev = data;
- irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
+ irq = msm_camera_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID%d_IRQ_STATUS_ADDR = 0x%x\n",
__func__, csid_dev->pdev->id, irq);
if (irq & (0x1 << CSID_RST_DONE_IRQ_BITSHIFT))
complete(&csid_dev->reset_complete);
- msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
+ msm_camera_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
return IRQ_HANDLED;
}
static void msm_csid_reset(struct csid_device *csid_dev)
{
- msm_io_w(CSID_RST_STB_ALL, csid_dev->base + CSID_RST_CMD_ADDR);
+ msm_camera_io_w(CSID_RST_STB_ALL, csid_dev->base + CSID_RST_CMD_ADDR);
wait_for_completion_interruptible(&csid_dev->reset_complete);
return;
}
@@ -193,7 +193,7 @@
}
csid_dev->hw_version =
- msm_io_r(csid_dev->base + CSID_HW_VERSION_ADDR);
+ msm_camera_io_r(csid_dev->base + CSID_HW_VERSION_ADDR);
*csid_version = csid_dev->hw_version;
init_completion(&csid_dev->reset_complete);
diff --git a/drivers/media/video/msm/csi/msm_csiphy.c b/drivers/media/video/msm/csi/msm_csiphy.c
index 0c1e0a4..36385ca 100644
--- a/drivers/media/video/msm/csi/msm_csiphy.c
+++ b/drivers/media/video/msm/csi/msm_csiphy.c
@@ -78,10 +78,10 @@
}
val = 0x3;
- msm_io_w((csiphy_params->lane_mask << 2) | val,
+ msm_camera_io_w((csiphy_params->lane_mask << 2) | val,
csiphybase + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
- msm_io_w(0x1, csiphybase + MIPI_CSIPHY_GLBL_T_INIT_CFG0_ADDR);
- msm_io_w(0x1, csiphybase + MIPI_CSIPHY_T_WAKEUP_CFG0_ADDR);
+ msm_camera_io_w(0x1, csiphybase + MIPI_CSIPHY_GLBL_T_INIT_CFG0_ADDR);
+ msm_camera_io_w(0x1, csiphybase + MIPI_CSIPHY_T_WAKEUP_CFG0_ADDR);
while (lane_mask & 0xf) {
if (!(lane_mask & 0x1)) {
@@ -89,26 +89,27 @@
lane_mask >>= 1;
continue;
}
- msm_io_w(0x10, csiphybase + MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*j);
- msm_io_w(csiphy_params->settle_cnt,
+ msm_camera_io_w(0x10,
+ csiphybase + MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*j);
+ msm_camera_io_w(csiphy_params->settle_cnt,
csiphybase + MIPI_CSIPHY_LNn_CFG3_ADDR + 0x40*j);
- msm_io_w(0x6F,
+ msm_camera_io_w(0x6F,
csiphybase + MIPI_CSIPHY_INTERRUPT_MASK0_ADDR +
0x4*(j+1));
- msm_io_w(0x6F,
+ msm_camera_io_w(0x6F,
csiphybase + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR +
0x4*(j+1));
j++;
lane_mask >>= 1;
}
- msm_io_w(0x10, csiphybase + MIPI_CSIPHY_LNCK_CFG2_ADDR);
- msm_io_w(csiphy_params->settle_cnt,
+ msm_camera_io_w(0x10, csiphybase + MIPI_CSIPHY_LNCK_CFG2_ADDR);
+ msm_camera_io_w(csiphy_params->settle_cnt,
csiphybase + MIPI_CSIPHY_LNCK_CFG3_ADDR);
- msm_io_w(0x24,
+ msm_camera_io_w(0x24,
csiphybase + MIPI_CSIPHY_INTERRUPT_MASK0_ADDR);
- msm_io_w(0x24,
+ msm_camera_io_w(0x24,
csiphybase + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
return rc;
}
@@ -117,36 +118,51 @@
{
uint32_t irq;
struct csiphy_device *csiphy_dev = data;
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS0_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS0_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS0 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS1_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR1_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS1_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR1_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS1 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS2_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR2_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS2_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR2_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS2 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS3_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR3_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS3_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR3_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS3 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS4_ADDR);
- msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR);
+
+ irq = msm_camera_io_r(
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS4_ADDR);
+ msm_camera_io_w(irq,
+ csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS4 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
- msm_io_w(0x1, csiphy_dev->base + 0x164);
- msm_io_w(0x0, csiphy_dev->base + 0x164);
+ msm_camera_io_w(0x1, csiphy_dev->base + 0x164);
+ msm_camera_io_w(0x0, csiphy_dev->base + 0x164);
return IRQ_HANDLED;
}
static void msm_csiphy_reset(struct csiphy_device *csiphy_dev)
{
- msm_io_w(0x1, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
+ msm_camera_io_w(0x1, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
usleep_range(5000, 8000);
- msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
+ msm_camera_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_RESET_ADDR);
}
static int msm_csiphy_subdev_g_chip_ident(struct v4l2_subdev *sd,
@@ -202,11 +218,11 @@
int i;
csiphy_dev = v4l2_get_subdevdata(sd);
for (i = 0; i < 4; i++)
- msm_io_w(0x0, csiphy_dev->base +
+ msm_camera_io_w(0x0, csiphy_dev->base +
MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*i);
- msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_LNCK_CFG2_ADDR);
- msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
+ msm_camera_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_LNCK_CFG2_ADDR);
+ msm_camera_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
#if DBG_CSIPHY
disable_irq(csiphy_dev->irq->start);
diff --git a/drivers/media/video/msm/csi/msm_ispif.c b/drivers/media/video/msm/csi/msm_ispif.c
index f4dde2a..cbb9e03 100644
--- a/drivers/media/video/msm/csi/msm_ispif.c
+++ b/drivers/media/video/msm/csi/msm_ispif.c
@@ -118,7 +118,7 @@
intfnum++;
} /*end while */
if (rc >= 0) {
- msm_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
+ msm_camera_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
rc = wait_for_completion_interruptible(&ispif->reset_complete);
}
@@ -136,7 +136,7 @@
(0x1 << RDI_CSID_RST_STB) +
(0x1 << RDI_1_VFE_RST_STB) +
(0x1 << RDI_1_CSID_RST_STB);
- msm_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
+ msm_camera_io_w(data, ispif->base + ISPIF_RST_CMD_ADDR);
return wait_for_completion_interruptible(&ispif->reset_complete);
}
@@ -162,9 +162,9 @@
if (rc < 0)
pr_err("%s: clk_set_rate failed %d\n", __func__, rc);
- data = msm_io_r(ispif->base + ISPIF_INPUT_SEL_ADDR);
+ data = msm_camera_io_r(ispif->base + ISPIF_INPUT_SEL_ADDR);
data |= csid<<(intftype*4);
- msm_io_w(data, ispif->base + ISPIF_INPUT_SEL_ADDR);
+ msm_camera_io_w(data, ispif->base + ISPIF_INPUT_SEL_ADDR);
}
static void msm_ispif_enable_intf_cids(uint8_t intftype, uint16_t cid_mask)
@@ -173,26 +173,26 @@
mutex_lock(&ispif->mutex);
switch (intftype) {
case PIX0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
data |= cid_mask;
- msm_io_w(data, ispif->base +
+ msm_camera_io_w(data, ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
data |= cid_mask;
- msm_io_w(data, ispif->base +
+ msm_camera_io_w(data, ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
data |= cid_mask;
- msm_io_w(data, ispif->base +
+ msm_camera_io_w(data, ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
}
@@ -208,11 +208,11 @@
params_len = params_list->len;
ispif_params = params_list->params;
CDBG("Enable interface\n");
- data = msm_io_r(ispif->base + ISPIF_PIX_STATUS_ADDR);
- data1 = msm_io_r(ispif->base + ISPIF_RDI_STATUS_ADDR);
+ data = msm_camera_io_r(ispif->base + ISPIF_PIX_STATUS_ADDR);
+ data1 = msm_camera_io_r(ispif->base + ISPIF_RDI_STATUS_ADDR);
if (((data & 0xf) != 0xf) || ((data1 & 0xf) != 0xf))
return -EBUSY;
- msm_io_w(0x00000000, ispif->base + ISPIF_IRQ_MASK_ADDR);
+ msm_camera_io_w(0x00000000, ispif->base + ISPIF_IRQ_MASK_ADDR);
for (i = 0; i < params_len; i++) {
msm_ispif_sel_csid_core(ispif_params[i].intftype,
ispif_params[i].csid);
@@ -220,11 +220,11 @@
ispif_params[i].cid_mask);
}
- msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_MASK_ADDR);
- msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_CLEAR_ADDR);
- msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
return rc;
}
@@ -234,17 +234,17 @@
uint32_t mask = 0;
switch (intftype) {
case PIX0:
- mask = msm_io_r(ispif->base +
+ mask = msm_camera_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
- mask = msm_io_r(ispif->base +
+ mask = msm_camera_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
- mask = msm_io_r(ispif->base +
+ mask = msm_camera_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
@@ -285,7 +285,8 @@
mask >>= 1;
intfnum++;
}
- msm_io_w(global_intf_cmd_mask, ispif->base + ISPIF_INTF_CMD_ADDR);
+ msm_camera_io_w(global_intf_cmd_mask,
+ ispif->base + ISPIF_INTF_CMD_ADDR);
}
static int msm_ispif_abort_intf_transfer(uint8_t intfmask)
@@ -327,7 +328,7 @@
if (intfmask & (0x1 << intfnum)) {
switch (intfnum) {
case PIX0:
- while ((msm_io_r(ispif->base +
+ while ((msm_camera_io_r(ispif->base +
ISPIF_PIX_STATUS_ADDR)
& 0xf) != 0xf) {
CDBG("Wait for pix0 Idle\n");
@@ -335,7 +336,7 @@
break;
case RDI0:
- while ((msm_io_r(ispif->base +
+ while ((msm_camera_io_r(ispif->base +
ISPIF_RDI_STATUS_ADDR)
& 0xf) != 0xf) {
CDBG("Wait for rdi0 Idle\n");
@@ -343,7 +344,7 @@
break;
case RDI1:
- while ((msm_io_r(ispif->base +
+ while ((msm_camera_io_r(ispif->base +
ISPIF_RDI_1_STATUS_ADDR)
& 0xf) != 0xf) {
CDBG("Wait for rdi1 Idle\n");
@@ -449,13 +450,13 @@
static inline void msm_ispif_read_irq_status(struct ispif_irq_status *out)
{
- out->ispifIrqStatus0 = msm_io_r(ispif->base +
+ out->ispifIrqStatus0 = msm_camera_io_r(ispif->base +
ISPIF_IRQ_STATUS_ADDR);
- out->ispifIrqStatus1 = msm_io_r(ispif->base +
+ out->ispifIrqStatus1 = msm_camera_io_r(ispif->base +
ISPIF_IRQ_STATUS_1_ADDR);
- msm_io_w(out->ispifIrqStatus0,
+ msm_camera_io_w(out->ispifIrqStatus0,
ispif->base + ISPIF_IRQ_CLEAR_ADDR);
- msm_io_w(out->ispifIrqStatus1,
+ msm_camera_io_w(out->ispifIrqStatus1,
ispif->base + ISPIF_IRQ_CLEAR_1_ADDR);
CDBG("ispif->irq: Irq_status0 = 0x%x\n",
@@ -473,7 +474,7 @@
ispif_process_irq(out);
}
}
- msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
+ msm_camera_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
}
@@ -543,17 +544,17 @@
int i = 0, j = 0;
switch (intftype) {
case PIX0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
- data = msm_io_r(ispif->base +
+ data = msm_camera_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
diff --git a/drivers/media/video/msm/io/Makefile b/drivers/media/video/msm/io/Makefile
index c567be2..dddcbf6 100644
--- a/drivers/media/video/msm/io/Makefile
+++ b/drivers/media/video/msm/io/Makefile
@@ -1,4 +1,17 @@
GCC_VERSION := $(shell $(CONFIG_SHELL) $(PWD)/scripts/gcc-version.sh $(CROSS_COMPILE)gcc)
+
+obj-$(CONFIG_MSM_CAMERA) += msm_camera_io_util.o
EXTRA_CFLAGS += -Idrivers/media/video/msm
-obj-$(CONFIG_MSM_CAMERA) += msm_camera_i2c.o msm_camera_eeprom.o msm_camera_i2c_mux.o
-obj-$(CONFIG_MSM_CAMERA) += msm_io_util.o
+ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
+ obj-$(CONFIG_MSM_CAMERA) += msm_camera_i2c.o msm_camera_eeprom.o msm_camera_i2c_mux.o
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_io_7x27a_v4l2.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_io_vfe31_v4l2.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_io_vfe31_v4l2.o
+else
+ obj-$(CONFIG_ARCH_MSM7X27A) += msm_io_7x27a.o
+ obj-$(CONFIG_ARCH_MSM8X60) += msm_io_8x60.o
+ obj-$(CONFIG_ARCH_MSM7X30) += msm_io_vfe31.o
+endif
+obj-$(CONFIG_ARCH_MSM_ARM11) += msm_io7x.o
+obj-$(CONFIG_ARCH_QSD8X50) += msm_io8x.o
+obj-$(CONFIG_ARCH_MSM8960) += msm_io_8960.o
diff --git a/drivers/media/video/msm/io/msm_camera_i2c_mux.c b/drivers/media/video/msm/io/msm_camera_i2c_mux.c
index ad3128b..a6fbaf5 100644
--- a/drivers/media/video/msm/io/msm_camera_i2c_mux.c
+++ b/drivers/media/video/msm/io/msm_camera_i2c_mux.c
@@ -21,16 +21,16 @@
static int msm_i2c_mux_config(struct i2c_mux_device *mux_device, uint8_t *mode)
{
uint32_t val;
- val = msm_io_r(mux_device->ctl_base);
+ val = msm_camera_io_r(mux_device->ctl_base);
if (*mode == MODE_DUAL) {
- msm_io_w(val | 0x3, mux_device->ctl_base);
+ msm_camera_io_w(val | 0x3, mux_device->ctl_base);
} else if (*mode == MODE_L) {
- msm_io_w(((val | 0x2) & ~(0x1)), mux_device->ctl_base);
- val = msm_io_r(mux_device->ctl_base);
+ msm_camera_io_w(((val | 0x2) & ~(0x1)), mux_device->ctl_base);
+ val = msm_camera_io_r(mux_device->ctl_base);
CDBG("the camio mode config left value is %d\n", val);
} else {
- msm_io_w(((val | 0x1) & ~(0x2)), mux_device->ctl_base);
- val = msm_io_r(mux_device->ctl_base);
+ msm_camera_io_w(((val | 0x1) & ~(0x2)), mux_device->ctl_base);
+ val = msm_camera_io_r(mux_device->ctl_base);
CDBG("the camio mode config right value is %d\n", val);
}
return 0;
@@ -53,8 +53,8 @@
iounmap(mux_device->ctl_base);
return rc;
}
- val = msm_io_r(mux_device->rw_base);
- msm_io_w((val | 0x200), mux_device->rw_base);
+ val = msm_camera_io_r(mux_device->rw_base);
+ msm_camera_io_w((val | 0x200), mux_device->rw_base);
}
mux_device->use_count++;
return 0;
@@ -65,8 +65,8 @@
int val = 0;
mux_device->use_count--;
if (mux_device->use_count == 0) {
- val = msm_io_r(mux_device->rw_base);
- msm_io_w((val & ~0x200), mux_device->rw_base);
+ val = msm_camera_io_r(mux_device->rw_base);
+ msm_camera_io_w((val & ~0x200), mux_device->rw_base);
iounmap(mux_device->rw_base);
iounmap(mux_device->ctl_base);
}
diff --git a/drivers/media/video/msm/io/msm_io_util.c b/drivers/media/video/msm/io/msm_camera_io_util.c
similarity index 80%
rename from drivers/media/video/msm/io/msm_io_util.c
rename to drivers/media/video/msm/io/msm_camera_io_util.c
index cc6bab2..af60426 100644
--- a/drivers/media/video/msm/io/msm_io_util.c
+++ b/drivers/media/video/msm/io/msm_camera_io_util.c
@@ -14,10 +14,90 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
+#include <linux/io.h>
#include <mach/board.h>
#include <mach/camera.h>
#include <mach/gpiomux.h>
+#define BUFF_SIZE_128 128
+
+void msm_camera_io_w(u32 data, void __iomem *addr)
+{
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ writel_relaxed((data), (addr));
+}
+
+void msm_camera_io_w_mb(u32 data, void __iomem *addr)
+{
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ wmb();
+ writel_relaxed((data), (addr));
+ wmb();
+}
+
+u32 msm_camera_io_r(void __iomem *addr)
+{
+ uint32_t data = readl_relaxed(addr);
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ return data;
+}
+
+u32 msm_camera_io_r_mb(void __iomem *addr)
+{
+ uint32_t data;
+ rmb();
+ data = readl_relaxed(addr);
+ rmb();
+ CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
+ return data;
+}
+
+void msm_camera_io_memcpy_toio(void __iomem *dest_addr,
+ void __iomem *src_addr, u32 len)
+{
+ int i;
+ u32 *d = (u32 *) dest_addr;
+ u32 *s = (u32 *) src_addr;
+
+ for (i = 0; i < len; i++)
+ writel_relaxed(*s++, d++);
+}
+
+void msm_camera_io_dump(void __iomem *addr, int size)
+{
+ char line_str[BUFF_SIZE_128], *p_str;
+ int i;
+ u32 *p = (u32 *) addr;
+ u32 data;
+ CDBG("%s: %p %d\n", __func__, addr, size);
+ line_str[0] = '\0';
+ p_str = line_str;
+ for (i = 0; i < size/4; i++) {
+ if (i % 4 == 0) {
+ snprintf(p_str, 12, "%08x: ", (u32) p);
+ p_str += 10;
+ }
+ data = readl_relaxed(p++);
+ snprintf(p_str, 12, "%08x ", data);
+ p_str += 9;
+ if ((i + 1) % 4 == 0) {
+ CDBG("%s\n", line_str);
+ line_str[0] = '\0';
+ p_str = line_str;
+ }
+ }
+ if (line_str[0] != '\0')
+ CDBG("%s\n", line_str);
+}
+
+void msm_camera_io_memcpy(void __iomem *dest_addr,
+ void __iomem *src_addr, u32 len)
+{
+ CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
+ msm_camera_io_memcpy_toio(dest_addr, src_addr, len / 4);
+ msm_camera_io_dump(dest_addr, len);
+}
+
int msm_cam_clk_enable(struct device *dev, struct msm_cam_clk_info *clk_info,
struct clk **clk_ptr, int num_clk, int enable)
{
diff --git a/drivers/media/video/msm/msm_io7x.c b/drivers/media/video/msm/io/msm_io7x.c
similarity index 82%
rename from drivers/media/video/msm/msm_io7x.c
rename to drivers/media/video/msm/io/msm_io7x.c
index 1befec6..8804106 100644
--- a/drivers/media/video/msm/msm_io7x.c
+++ b/drivers/media/video/msm/io/msm_io7x.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -205,7 +205,7 @@
/* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_SEL_BMSK |
CAM_PCLK_SRC_SEL_BMSK |
@@ -215,23 +215,23 @@
3 << CAM_PCLK_SRC_SEL_SHFT |
0 << CAM_PCLK_INVERT_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
- msleep(10);
+ usleep_range(10000, 11000);
}
void msm_camio_vfe_blk_reset(void)
@@ -239,26 +239,26 @@
uint32_t val;
/* do apps reset */
- val = readl(appbase + 0x00000210);
+ val = msm_camera_io_r_mb(appbase + 0x00000210);
val |= 0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000210);
+ usleep_range(10000, 11000);
- val = readl(appbase + 0x00000210);
+ val = msm_camera_io_r_mb(appbase + 0x00000210);
val &= ~0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000210);
+ usleep_range(10000, 11000);
/* do axi reset */
- val = readl(appbase + 0x00000208);
+ val = msm_camera_io_r_mb(appbase + 0x00000208);
val |= 0x1;
- writel(val, appbase + 0x00000208);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000208);
+ usleep_range(10000, 11000);
- val = readl(appbase + 0x00000208);
+ val = msm_camera_io_r_mb(appbase + 0x00000208);
val &= ~0x1;
- writel(val, appbase + 0x00000208);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + 0x00000208);
+ usleep_range(10000, 11000);
}
void msm_camio_camif_pad_reg_reset_2(void)
@@ -266,17 +266,17 @@
uint32_t reg;
uint32_t mask, value;
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
}
void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
diff --git a/drivers/media/video/msm/msm_io8x.c b/drivers/media/video/msm/io/msm_io8x.c
similarity index 85%
rename from drivers/media/video/msm/msm_io8x.c
rename to drivers/media/video/msm/io/msm_io8x.c
index 6bc92b0..5f1f34f 100644
--- a/drivers/media/video/msm/msm_io8x.c
+++ b/drivers/media/video/msm/io/msm_io8x.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -213,7 +213,7 @@
/* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_SEL_BMSK |
CAM_PCLK_SRC_SEL_BMSK |
@@ -226,24 +226,24 @@
0 << CAM_PCLK_INVERT_SHFT |
0 << EXT_CAM_HSYNC_POL_SEL_SHFT |
0 << EXT_CAM_VSYNC_POL_SEL_SHFT | 0 << MDDI_CLK_CHICKEN_BIT_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- msleep(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
- msleep(10);
+ usleep_range(10000, 11000);
/* todo: check return */
if (camio_vfe_clk)
@@ -254,15 +254,15 @@
{
uint32_t val;
- val = readl(appbase + APPS_RESET_OFFSET);
+ val = msm_camera_io_r_mb(appbase + APPS_RESET_OFFSET);
val |= 0x1;
- writel(val, appbase + APPS_RESET_OFFSET);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + APPS_RESET_OFFSET);
+ usleep_range(10000, 11000);
- val = readl(appbase + APPS_RESET_OFFSET);
+ val = msm_camera_io_r_mb(appbase + APPS_RESET_OFFSET);
val &= ~0x1;
- writel(val, appbase + APPS_RESET_OFFSET);
- mdelay(10);
+ msm_camera_io_w_mb(val, appbase + APPS_RESET_OFFSET);
+ usleep_range(10000, 11000);
}
void msm_camio_camif_pad_reg_reset_2(void)
@@ -270,17 +270,17 @@
uint32_t reg;
uint32_t mask, value;
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r_mb(mdcbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
+ msm_camera_io_w_mb((reg & (~mask)) | (value & mask), mdcbase);
+ usleep_range(10000, 11000);
}
void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
diff --git a/drivers/media/video/msm/msm_io_7x27a.c b/drivers/media/video/msm/io/msm_io_7x27a.c
similarity index 86%
rename from drivers/media/video/msm/msm_io_7x27a.c
rename to drivers/media/video/msm/io/msm_io_7x27a.c
index 7a83721..5ddf504 100644
--- a/drivers/media/video/msm/msm_io_7x27a.c
+++ b/drivers/media/video/msm/io/msm_io_7x27a.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -153,20 +153,6 @@
void __iomem *appbase;
-
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel((data), (addr));
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
int msm_camio_vfe_clk_rate_set(int rate)
{
int rc = 0;
@@ -292,9 +278,9 @@
{
uint32_t irq;
- irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
- msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
/* TODO: Needs to send this info to upper layers */
if ((irq >> 19) & 0x1)
@@ -338,15 +324,15 @@
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
appbase = ioremap(camio_ext.appphy,
camio_ext.appsz);
@@ -381,15 +367,15 @@
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(20);
free_irq(camio_ext.csiirq, 0);
@@ -435,25 +421,25 @@
uint32_t val;
/* do apps reset */
- val = readl_relaxed(appbase + 0x00000210);
+ val = msm_camera_io_r(appbase + 0x00000210);
val |= 0x1;
- writel_relaxed(val, appbase + 0x00000210);
+ msm_camera_io_w(val, appbase + 0x00000210);
usleep_range(10000, 11000);
- val = readl_relaxed(appbase + 0x00000210);
+ val = msm_camera_io_r(appbase + 0x00000210);
val &= ~0x1;
- writel_relaxed(val, appbase + 0x00000210);
+ msm_camera_io_w(val, appbase + 0x00000210);
usleep_range(10000, 11000);
/* do axi reset */
- val = readl_relaxed(appbase + 0x00000208);
+ val = msm_camera_io_r(appbase + 0x00000208);
val |= 0x1;
- writel_relaxed(val, appbase + 0x00000208);
+ msm_camera_io_w(val, appbase + 0x00000208);
usleep_range(10000, 11000);
- val = readl_relaxed(appbase + 0x00000208);
+ val = msm_camera_io_r(appbase + 0x00000208);
val &= ~0x1;
- writel_relaxed(val, appbase + 0x00000208);
+ msm_camera_io_w(val, appbase + 0x00000208);
mb();
usleep_range(10000, 11000);
return;
@@ -488,7 +474,7 @@
pr_err("ioremap failed for CSIBASE\n");
goto ioremap_fail;
}
- msm_io_w(MIPI_PWR_CNTL_DIS, csibase + MIPI_PWR_CNTL);
+ msm_camera_io_w(MIPI_PWR_CNTL_DIS, csibase + MIPI_PWR_CNTL);
iounmap(csibase);
ioremap_fail:
msm_camio_clk_disable(CAMIO_CSI0_PCLK);
@@ -504,9 +490,9 @@
CDBG("msm_camio_csi_config\n");
/* Enable error correction for DATA lane. Applies to all data lanes */
- msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csibase + MIPI_PHY_CONTROL);
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csibase + MIPI_PROTOCOL_CONTROL);
val = MIPI_PROTOCOL_CONTROL_LONG_PACKET_HEADER_CAPTURE_BMSK |
@@ -517,7 +503,7 @@
val |= csi_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
(0x1 <<
@@ -525,7 +511,7 @@
(0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
(0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
val = (csi_params->settle_cnt <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
@@ -533,51 +519,51 @@
(0x1 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
val = (0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
/* program number of lanes and lane mapping */
switch (csi_params->lane_cnt) {
case 1:
- msm_io_w(csi_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x4,
csibase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csi_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x5,
csibase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csi_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x6,
csibase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csi_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x7,
csibase + MIPI_CAMERA_CNTL);
break;
}
- msm_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits - write 1 clears the status*/
- msm_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xFFFFF3FF, csibase + MIPI_INTERRUPT_STATUS);
return rc;
}
diff --git a/drivers/media/video/msm/msm_io_7x27a_v4l2.c b/drivers/media/video/msm/io/msm_io_7x27a_v4l2.c
similarity index 93%
rename from drivers/media/video/msm/msm_io_7x27a_v4l2.c
rename to drivers/media/video/msm/io/msm_io_7x27a_v4l2.c
index 8b977ba..45761d5 100644
--- a/drivers/media/video/msm/msm_io_7x27a_v4l2.c
+++ b/drivers/media/video/msm/io/msm_io_7x27a_v4l2.c
@@ -32,19 +32,6 @@
static int apps_reset;
void __iomem *appbase;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
void msm_camio_clk_rate_set_2(struct clk *clk, int rate)
{
clk_set_rate(clk, rate);
diff --git a/drivers/media/video/msm/msm_io_8960.c b/drivers/media/video/msm/io/msm_io_8960.c
similarity index 74%
rename from drivers/media/video/msm/msm_io_8960.c
rename to drivers/media/video/msm/io/msm_io_8960.c
index 9bfc239..1ab4223 100644
--- a/drivers/media/video/msm/msm_io_8960.c
+++ b/drivers/media/video/msm/io/msm_io_8960.c
@@ -32,82 +32,6 @@
static struct clk *camio_imem_clk;
static struct regulator *fs_ijpeg;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel_relaxed for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[BUFF_SIZE_128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- snprintf(p_str, 12, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- snprintf(p_str, 12, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
-
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
int rc = 0;
diff --git a/drivers/media/video/msm/msm_io_8x60.c b/drivers/media/video/msm/io/msm_io_8x60.c
similarity index 87%
rename from drivers/media/video/msm/msm_io_8x60.c
rename to drivers/media/video/msm/io/msm_io_8x60.c
index 49ec461..4e8dc25 100644
--- a/drivers/media/video/msm/msm_io_8x60.c
+++ b/drivers/media/video/msm/io/msm_io_8x60.c
@@ -104,82 +104,6 @@
static int vpe_clk_rate;
struct msm_bus_scale_pdata *cam_bus_scale_table;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- sprintf(p_str, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- sprintf(p_str, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
-
static void msm_camera_vreg_enable(void)
{
ldo15 = regulator_get(NULL, "8058_l15");
@@ -462,10 +386,10 @@
{
uint32_t irq = 0;
if (csibase != NULL)
- irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
if (csibase != NULL)
- msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
@@ -631,22 +555,22 @@
val = 0x0;
if (csibase != NULL) {
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(20);
- val = msm_io_r(csibase + MIPI_PHY_D1_CONTROL);
+ val = msm_camera_io_r(csibase + MIPI_PHY_D1_CONTROL);
val &=
~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT)
|(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
- msm_io_w(0x0, csibase + MIPI_INTERRUPT_MASK);
- msm_io_w(0x0, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0x0, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0x0, csibase + MIPI_INTERRUPT_STATUS);
csi_free_irq();
iounmap(csibase);
csibase = NULL;
@@ -679,7 +603,7 @@
camio_clk = camdev->ioclk;
msm_camera_vreg_enable();
- msleep(10);
+ usleep_range(10000, 11000);
rc = camdev->camera_gpio_on();
if (rc < 0)
return rc;
@@ -735,10 +659,10 @@
CDBG("msm_camio_csi_config\n");
if (csibase != NULL) {
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
- msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csibase + MIPI_PHY_CONTROL);
/* SW_RST to the CSI core */
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csibase + MIPI_PROTOCOL_CONTROL);
/* PROTOCOL CONTROL */
@@ -750,7 +674,7 @@
val |= csi_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
@@ -761,50 +685,51 @@
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
for (i = 0; i < csi_params->lane_cnt; i++)
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
+ msm_camera_io_w(val,
+ csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
val =
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT)
|(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
/* halcyon only supports 1 or 2 lane */
switch (csi_params->lane_cnt) {
case 1:
- msm_io_w(csi_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x4,
csibase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csi_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x5,
csibase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csi_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x6,
csibase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csi_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x7,
csibase + MIPI_CAMERA_CNTL);
break;
}
/* mask out ID_ERROR[19], DATA_CMM_ERR[11]
and CLK_CMM_ERR[10] - de-featured */
- msm_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits*/
- msm_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xF017F3C0, csibase + MIPI_INTERRUPT_STATUS);
} else {
pr_info("CSIBASE is NULL");
}
diff --git a/drivers/media/video/msm/msm_io_vfe31.c b/drivers/media/video/msm/io/msm_io_vfe31.c
similarity index 85%
rename from drivers/media/video/msm/msm_io_vfe31.c
rename to drivers/media/video/msm/io/msm_io_vfe31.c
index e5b370c..7f3b7ae 100644
--- a/drivers/media/video/msm/msm_io_vfe31.c
+++ b/drivers/media/video/msm/io/msm_io_vfe31.c
@@ -130,82 +130,6 @@
static int reg_count;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- sprintf(p_str, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- sprintf(p_str, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
-
static void msm_camera_vreg_enable(struct platform_device *pdev)
{
int count, rc;
@@ -426,9 +350,9 @@
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
- irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
+ irq = msm_camera_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
- msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
@@ -523,13 +447,13 @@
uint32_t val;
val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
usleep_range(9000, 10000);
free_irq(camio_ext.csiirq, 0);
iounmap(csibase);
@@ -558,23 +482,23 @@
uint32_t reg;
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
- msleep(10);
+ usleep_range(10000, 11000);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x3;
- msm_io_w(reg, camifpadbase);
- msleep(10);
+ msm_camera_io_w(reg, camifpadbase);
+ usleep_range(10000, 11000);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x10;
- msm_io_w(reg, camifpadbase);
- msleep(10);
+ msm_camera_io_w(reg, camifpadbase);
+ usleep_range(10000, 11000);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
/* Need to be uninverted*/
reg &= 0x03;
- msm_io_w(reg, camifpadbase);
- msleep(10);
+ msm_camera_io_w(reg, camifpadbase);
+ usleep_range(10000, 11000);
}
void msm_camio_vfe_blk_reset(void)
@@ -588,16 +512,16 @@
{
uint32_t reg;
uint32_t mask, value;
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
- mdelay(10);
- reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
+ msm_camera_io_w((reg & (~mask)) | (value & mask), camifpadbase);
+ usleep_range(10000, 11000);
+ reg = (msm_camera_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
- mdelay(10);
+ msm_camera_io_w((reg & (~mask)) | (value & mask), camifpadbase);
+ usleep_range(10000, 11000);
}
void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
@@ -707,10 +631,10 @@
CDBG("msm_camio_csi_config\n");
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
- msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
+ msm_camera_io_w(0x4, csibase + MIPI_PHY_CONTROL);
/* SW_RST to the CSI core */
- msm_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
+ msm_camera_io_w(MIPI_PROTOCOL_CONTROL_SW_RST_BMSK,
csibase + MIPI_PROTOCOL_CONTROL);
/* PROTOCOL CONTROL */
@@ -722,7 +646,7 @@
val |= csi_params->dpcm_scheme <<
MIPI_PROTOCOL_CONTROL_DPCM_SCHEME_SHFT;
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
/* SW CAL EN */
val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
@@ -731,7 +655,7 @@
(0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
(0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
@@ -742,49 +666,49 @@
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
for (i = 0; i < csi_params->lane_cnt; i++)
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
val = 0 << MIPI_PHY_D0_CONTROL_HS_REC_EQ_SHFT;
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D0_CONTROL);
val = (0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT);
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
+ msm_camera_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
- msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL);
+ msm_camera_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL);
/* halcyon only supports 1 or 2 lane */
switch (csi_params->lane_cnt) {
case 1:
- msm_io_w(csi_params->lane_assign << 8 | 0x4,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x4,
csibase + MIPI_CAMERA_CNTL);
break;
case 2:
- msm_io_w(csi_params->lane_assign << 8 | 0x5,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x5,
csibase + MIPI_CAMERA_CNTL);
break;
case 3:
- msm_io_w(csi_params->lane_assign << 8 | 0x6,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x6,
csibase + MIPI_CAMERA_CNTL);
break;
case 4:
- msm_io_w(csi_params->lane_assign << 8 | 0x7,
+ msm_camera_io_w(csi_params->lane_assign << 8 | 0x7,
csibase + MIPI_CAMERA_CNTL);
break;
}
/* mask out ID_ERROR[19], DATA_CMM_ERR[11]
and CLK_CMM_ERR[10] - de-featured */
- msm_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_MASK);
+ msm_camera_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_MASK);
/*clear IRQ bits*/
- msm_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_STATUS);
+ msm_camera_io_w(0xFFF7F3FF, csibase + MIPI_INTERRUPT_STATUS);
return rc;
}
diff --git a/drivers/media/video/msm/msm_io_vfe31_v4l2.c b/drivers/media/video/msm/io/msm_io_vfe31_v4l2.c
similarity index 81%
rename from drivers/media/video/msm/msm_io_vfe31_v4l2.c
rename to drivers/media/video/msm/io/msm_io_vfe31_v4l2.c
index 03810f4..451cb5a 100644
--- a/drivers/media/video/msm/msm_io_vfe31_v4l2.c
+++ b/drivers/media/video/msm/io/msm_io_vfe31_v4l2.c
@@ -42,81 +42,6 @@
static struct regulator *fs_vpe;
static int vpe_clk_rate;
-void msm_io_w(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- writel_relaxed((data), (addr));
-}
-
-void msm_io_w_mb(u32 data, void __iomem *addr)
-{
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- wmb();
- writel_relaxed((data), (addr));
- wmb();
-}
-
-u32 msm_io_r(void __iomem *addr)
-{
- uint32_t data = readl_relaxed(addr);
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-u32 msm_io_r_mb(void __iomem *addr)
-{
- uint32_t data;
- rmb();
- data = readl_relaxed(addr);
- rmb();
- CDBG("%s: %08x %08x\n", __func__, (int) (addr), (data));
- return data;
-}
-
-void msm_io_memcpy_toio(void __iomem *dest_addr,
- void __iomem *src_addr, u32 len)
-{
- int i;
- u32 *d = (u32 *) dest_addr;
- u32 *s = (u32 *) src_addr;
- /* memcpy_toio does not work. Use writel for now */
- for (i = 0; i < len; i++)
- writel_relaxed(*s++, d++);
-}
-
-void msm_io_dump(void __iomem *addr, int size)
-{
- char line_str[BUFF_SIZE_128], *p_str;
- int i;
- u32 *p = (u32 *) addr;
- u32 data;
- CDBG("%s: %p %d\n", __func__, addr, size);
- line_str[0] = '\0';
- p_str = line_str;
- for (i = 0; i < size/4; i++) {
- if (i % 4 == 0) {
- snprintf(p_str, 12, "%08x: ", (u32) p);
- p_str += 10;
- }
- data = readl_relaxed(p++);
- snprintf(p_str, 12, "%08x ", data);
- p_str += 9;
- if ((i + 1) % 4 == 0) {
- CDBG("%s\n", line_str);
- line_str[0] = '\0';
- p_str = line_str;
- }
- }
- if (line_str[0] != '\0')
- CDBG("%s\n", line_str);
-}
-
-void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len)
-{
- CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len);
- msm_io_memcpy_toio(dest_addr, src_addr, len / 4);
- msm_io_dump(dest_addr, len);
-}
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
diff --git a/drivers/media/video/msm/msm_vfe31.c b/drivers/media/video/msm/msm_vfe31.c
index 1c9fd03..2929538 100644
--- a/drivers/media/video/msm/msm_vfe31.c
+++ b/drivers/media/video/msm/msm_vfe31.c
@@ -23,14 +23,6 @@
#include "msm_vpe1.h"
atomic_t irq_cnt;
-#define CHECKED_COPY_FROM_USER(in) { \
- if (copy_from_user((in), (void __user *)cmd->value, \
- cmd->length)) { \
- rc = -EFAULT; \
- break; \
- } \
-}
-
static struct vfe31_ctrl_type *vfe31_ctrl;
static struct msm_camera_io_clk camio_clk;
static void *vfe_syncdata;
@@ -505,33 +497,33 @@
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* now enable only halt_irq & reset_irq */
- msm_io_w(0xf0000000, /* this is for async timer. */
+ msm_camera_io_w(0xf0000000, /* this is for async timer. */
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_AXI_HALT,
+ msm_camera_io_w(VFE_IMASK_AXI_HALT,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* then apply axi halt command. */
- msm_io_w_mb(AXI_HALT,
+ msm_camera_io_w_mb(AXI_HALT,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
}
@@ -1020,7 +1012,8 @@
default:
break;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[V31_AXI_OUT_CFG].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[V31_AXI_OUT_CFG].offset,
ao, vfe31_cmd[V31_AXI_OUT_CFG].length - V31_AXI_CH_INF_LEN);
return 0;
@@ -1098,26 +1091,28 @@
vfe31_reset_internal_variables();
vfe31_reset_hist_cfg();
- vfe_version = msm_io_r(vfe31_ctrl->vfebase);
+ vfe_version = msm_camera_io_r(vfe31_ctrl->vfebase);
CDBG("vfe_version = 0x%x\n", vfe_version);
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
- msm_io_w(VFE_IMASK_RESET,
+ msm_camera_io_w(VFE_IMASK_RESET,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
@@ -1127,7 +1122,7 @@
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_RESET_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -1142,11 +1137,11 @@
vfe31_ctrl->stats_comp = *(++p);
vfe31_ctrl->hfr_mode = *(++p);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG_OFF);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG_OFF);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
wmb();
return 0;
}
@@ -1156,9 +1151,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe31_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
@@ -1170,9 +1167,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe31_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1184,9 +1183,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe31_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1198,9 +1199,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe31_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1212,9 +1215,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe31_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1225,9 +1230,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe31_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -1249,23 +1256,23 @@
if (VFE_MODE_OF_OPERATION_VIDEO == vfe31_ctrl->operation_mode)
irq_mask |= 0x4;
- msm_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_RESET,
+ msm_camera_io_w(VFE_IMASK_RESET,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* enable out of order option */
- msm_io_w(0x80000000, vfe31_ctrl->vfebase + VFE_AXI_CFG);
+ msm_camera_io_w(0x80000000, vfe31_ctrl->vfebase + VFE_AXI_CFG);
/* enable performance monitor */
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CFG);
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CMD);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CFG);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_BUS_PM_CMD);
- msm_io_dump(vfe31_ctrl->vfebase, 0x600);
+ msm_camera_io_dump(vfe31_ctrl->vfebase, 0x600);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
wmb();
atomic_set(&vfe31_ctrl->vstate, 1);
@@ -1276,14 +1283,14 @@
msm_camio_set_perf_lvl(S_VIDEO);
usleep(1000);
vfe31_ctrl->recording_state = VFE_REC_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
static int vfe31_stop_recording(void)
{
vfe31_ctrl->recording_state = VFE_REC_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_set_perf_lvl(S_PREVIEW);
return 0;
}
@@ -1309,7 +1316,7 @@
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
vfe31_ctrl->operation_mode, vfe31_ctrl->outpath.output_mode);
@@ -1335,39 +1342,39 @@
(0x1 << (vfe31_ctrl->outpath.out2.ch1 + 8)));
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_P) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_P_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_T) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_S) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch1]);
}
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
vfe31_start_common();
msm_camio_set_perf_lvl(S_ZSL);
usleep(1000);
/* for debug */
- msm_io_w(1, vfe31_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x188);
return 0;
}
@@ -1384,7 +1391,7 @@
}
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if ((vfe31_ctrl->operation_mode ==
VFE_MODE_OF_OPERATION_SNAPSHOT) ||
@@ -1401,15 +1408,15 @@
(0x1 << (vfe31_ctrl->outpath.out1.ch1 + 8)));
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PT) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_S) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
} else { /* this is raw snapshot mode. */
@@ -1417,11 +1424,11 @@
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_S) {
irq_comp_mask |=
(0x1 << (vfe31_ctrl->outpath.out1.ch0 + 8));
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
}
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (p_sync->stereocam_enabled)
msm_camio_set_perf_lvl(S_STEREO_CAPTURE);
else
@@ -1441,7 +1448,7 @@
(vfe31_ctrl->operation_mode != VFE_MODE_OF_OPERATION_VIDEO))
return 0;
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PT) {
irq_comp_mask |= (0x1 << vfe31_ctrl->outpath.out0.ch0 |
@@ -1463,24 +1470,24 @@
0x1 << (vfe31_ctrl->outpath.out2.ch1 + 16));
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PT) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
if (vfe31_ctrl->outpath.out0.ch2 >= 0)
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_P_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
@@ -1500,17 +1507,21 @@
CDBG("vfe31_update\n");
if (vfe31_ctrl->update_gamma) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF))
- msm_io_w(7, vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF))
+ msm_camera_io_w(7,
+ vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
+ msm_camera_io_w(0,
+ vfe31_ctrl->vfebase+V31_GAMMA_CFG_OFF);
vfe31_ctrl->update_gamma = false;
}
if (vfe31_ctrl->update_luma) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF))
- msm_io_w(1, vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF))
+ msm_camera_io_w(1,
+ vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
+ msm_camera_io_w(0,
+ vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
vfe31_ctrl->update_luma = false;
}
spin_lock_irqsave(&vfe31_ctrl->update_ack_lock, flags);
@@ -1518,7 +1529,7 @@
spin_unlock_irqrestore(&vfe31_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
@@ -1534,7 +1545,7 @@
value = 0x40000;
/* Timer Stop */
- msm_io_w_mb(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w_mb(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
}
static void vfe31_sync_timer_start(const uint32_t *tbl)
@@ -1559,29 +1570,30 @@
}
/* Timer Start */
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
4 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
8 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
val = camio_clk.vfe_clk_rate / 10000;
val = 10000000 / val;
val = value * 10000 / val;
- CDBG("%s: Pixel Clk Cycles!!! %d \n", __func__, val);
- msm_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
+ msm_camera_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
12 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
+ msm_camera_io_w(value,
+ vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
wmb();
}
@@ -1591,9 +1603,9 @@
uint32_t value = VFE_DMI_CFG_DEFAULT;
value += (uint32_t)bankSel;
- msm_io_w_mb(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w_mb(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
wmb();
}
static void vfe31_write_gamma_cfg(enum VFE31_DMI_RAM_SEL channel_sel,
@@ -1607,8 +1619,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1620,7 +1634,7 @@
vfe31_program_dmi_cfg(STATS_HIST_RAM);
for (i = 0 ; i < VFE31_HIST_TABLE_LENGTH ; i++)
- msm_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1636,8 +1650,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1725,11 +1741,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1745,11 +1762,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1765,12 +1783,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1786,12 +1805,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1839,14 +1859,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= RS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- */
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1862,14 +1877,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- /*
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- old_val |= CS_ENABLE_MASK;
- msm_io_w(old_val,
- vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- */
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1878,7 +1888,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1894,20 +1904,23 @@
new_val = *cmdp_local;
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
- &new_val, 4);
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
+ &new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
- &new_val, 4);
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
+ &new_val, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp_local, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp_local, (vfe31_cmd[cmd->id].length));
}
break;
case V31_DEMOSAIC_2_UPDATE: /* 38 BPC update */
@@ -1926,15 +1939,17 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
old_val &= BPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
}
break;
@@ -1954,17 +1969,19 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAIC_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp_local, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp_local, (vfe31_cmd[cmd->id].length));
}
break;
case V31_ROLL_OFF_CFG: {
@@ -1979,23 +1996,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, 16);
cmdp_local += 4;
vfe31_program_dmi_cfg(ROLLOFF_RAM);
/* for loop for extrcting init table. */
for (i = 0 ; i < (VFE31_ROLL_OFF_INIT_TABLE_SIZE * 2) ; i++) {
- msm_io_w(*cmdp_local ,
+ msm_camera_io_w(*cmdp_local ,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
- CDBG("done writing init table \n");
+ CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
- msm_io_w(LENS_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(LENS_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe31_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0 ; i < (VFE31_ROLL_OFF_DELTA_TABLE_SIZE * 2) ; i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
@@ -2018,8 +2036,9 @@
}
/* Select Bank 0*/
*cmdp = 0;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
cmdp += 1;
vfe31_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0 , cmdp);
cmdp -= 1;
@@ -2039,7 +2058,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_LUMA_CFG_OFF);
cmdp += 1;
if (old_val != 0x0)
vfe31_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0 , cmdp);
@@ -2063,7 +2083,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
cmdp, V31_SCE_LEN);
}
break;
@@ -2095,7 +2115,7 @@
}
/* Select Bank 0*/
*cmdp = 0;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
vfe31_write_gamma_cfg(RGBLUT_CHX_BANK0, cmdp);
@@ -2114,7 +2134,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_GAMMA_CFG_OFF);
cmdp += 1;
if (!old_val) {
@@ -2128,47 +2149,47 @@
break;
case V31_STATS_AWB_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_AE_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_AF_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_IHIST_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_RS_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case V31_STATS_CS_STOP: {
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
@@ -2205,11 +2226,12 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -2224,8 +2246,15 @@
goto proc_general_done;
}
- CHECKED_COPY_FROM_USER(cmdp);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ if (copy_from_user(cmdp, (void __user *)cmd->value,
+ cmd->length)) {
+ rc = -EFAULT;
+ pr_err("%s copy from user failed for cmd %d",
+ __func__, cmd->id);
+ goto proc_general_done;
+ }
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
}
break;
@@ -2672,34 +2701,34 @@
unsigned long flags;
if (vfe31_ctrl->recording_state == VFE_REC_STATE_START_REQUESTED) {
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_V) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch1]);
}
vfe31_ctrl->recording_state = VFE_REC_STATE_STARTED;
if (vpe_ctrl->dis_en) {
- old_val = msm_io_r(
+ old_val = msm_camera_io_r(
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= RS_CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
}
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe31_ctrl->recording_state
== VFE_REC_STATE_STOP_REQUESTED) {
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_V) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out2.ch1]);
}
/*disable rs& cs when stop recording. */
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= (~RS_CS_ENABLE_MASK);
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
CDBG("stop video triggered\n");
}
@@ -2710,7 +2739,7 @@
if (vfe31_ctrl->recording_state ==
VFE_REC_STATE_STOP_REQUESTED) {
vfe31_ctrl->recording_state = VFE_REC_STATE_STOPPED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
} else if (vfe31_ctrl->recording_state ==
VFE_REC_STATE_STOPPED) {
@@ -2741,67 +2770,74 @@
/* stop the bus output: write master enable = 0*/
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PT) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[
vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_S) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch1]);
}
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* Ensure the read order while reading
to the command register using the barrier */
- temp = msm_io_r_mb(vfe31_ctrl->vfebase +
+ temp = msm_camera_io_r_mb(vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
/* then do reg_update. */
- msm_io_w_mb(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
static void vfe31_set_default_reg_values(void)
{
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
- msm_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- msm_io_w(0xFFFFFFFF, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0xFFFFFFFF,
+ vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
- msm_io_w(0x3980007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
- msm_io_w(0x3A00007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
- msm_io_w(0x3A8000F, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
- msm_io_w(0x3B80007, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
- msm_io_w(0x3C0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
- msm_io_w(0x3E0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ msm_camera_io_w(0x3980007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ msm_camera_io_w(0x3A00007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ msm_camera_io_w(0x3A8000F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ msm_camera_io_w(0x3B80007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ msm_camera_io_w(0x3C0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ msm_camera_io_w(0x3E0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
static void vfe31_process_reset_irq(void)
@@ -2817,7 +2853,7 @@
vfe31_set_default_reg_values();
/* reload all write masters. (frame & line)*/
- msm_io_w_mb(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
+ msm_camera_io_w_mb(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
vfe31_send_msg_no_payload(MSG_ID_RESET_ACK);
}
}
@@ -2827,36 +2863,36 @@
{
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(AXI_HALT_CLEAR,
+ msm_camera_io_w_mb(AXI_HALT_CLEAR,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
vfe31_ctrl->while_stopping_mask = VFE_IMASK_RESET;
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* now enable only halt_irq & reset_irq */
- msm_io_w(0xf0000000, /* this is for async timer. */
+ msm_camera_io_w(0xf0000000, /* this is for async timer. */
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_RESET,
+ msm_camera_io_w(VFE_IMASK_RESET,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
CDBG("%s: about to reset vfe...\n", __func__);
- msm_io_w_mb(VFE_RESET_UPON_STOP_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -2878,9 +2914,9 @@
if (vfe31_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
- temp = msm_io_r_mb(vfe31_ctrl->vfebase +
+ temp = msm_camera_io_r_mb(vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
@@ -2912,7 +2948,7 @@
if (errStatus & VFE31_IMASK_CAMIF_ERROR) {
pr_err("vfe31_irq: camif errors\n");
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
- camifStatus = msm_io_r(temp);
+ camifStatus = msm_camera_io_r(temp);
pr_err("camifStatus = 0x%x\n", camifStatus);
vfe31_send_msg_no_payload(MSG_ID_CAMIF_ERROR);
}
@@ -2980,21 +3016,21 @@
if (errStatus & VFE31_IMASK_AXI_ERROR) {
pr_err("vfe31_irq: axi error\n");
/* read status too when overflow happens.*/
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
pr_debug("VFE_BUS_PING_PONG_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_OPERATION_STATUS);
pr_debug("VFE_BUS_OPERATION_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_AXI_STATUS);
pr_debug("VFE_AXI_STATUS = 0x%x\n", read_val);
}
@@ -3002,17 +3038,18 @@
#define VFE31_AXI_OFFSET 0x0050
#define vfe31_get_ch_ping_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_get_ch_pong_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_get_ch_addr(ping_pong, chn) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_get_ch_pong_addr(chn) : vfe31_get_ch_ping_addr(chn))
#define vfe31_put_ch_ping_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_put_ch_pong_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_w((addr), \
+ vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_put_ch_addr(ping_pong, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_put_ch_pong_addr((chn), (addr)) : \
@@ -3171,7 +3208,7 @@
vfe31_send_msg_no_payload(MSG_ID_SNAPSHOT_DONE);
/* Ensure the write order while writing
to the cmd register using barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
@@ -3215,7 +3252,7 @@
vfe31_send_msg_no_payload(MSG_ID_SNAPSHOT_DONE);
/* Ensure the write order while writing
to the cmd register using barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
}
@@ -3443,7 +3480,7 @@
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_io_r(vfe31_ctrl->vfebase +
+ ((msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
@@ -3452,8 +3489,8 @@
((uint32_t)(vfe31_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
- returnAddr = msm_io_r((uint32_t *)pingpongAddr);
- msm_io_w(newAddr, (uint32_t *)pingpongAddr);
+ returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
+ msm_camera_io_w(newAddr, (uint32_t *)pingpongAddr);
return returnAddr;
}
@@ -3475,7 +3512,7 @@
msg._u.msgStats.buff.rs = vfe31_ctrl->rsStatsControl.bufToRender;
msg._u.msgStats.buff.cs = vfe31_ctrl->csStatsControl.bufToRender;
- temp = msm_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msg._u.msgStats.buff.awb_ymin = (0xFF00 & temp) >> 8;
vfe31_proc_ops(msg._d,
@@ -3736,32 +3773,34 @@
memset(&irq, 0, sizeof(struct vfe31_irq_status));
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_0);
- irq.vfeIrqStatus0 = msm_io_r(val);
+ irq.vfeIrqStatus0 = msm_camera_io_r(val);
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_1);
- irq.vfeIrqStatus1 = msm_io_r(val);
+ irq.vfeIrqStatus1 = msm_camera_io_r(val);
if (irq.vfeIrqStatus1 & VFE_IMASK_AXI_HALT) {
- msm_io_w(VFE_IMASK_RESET, vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
-
- msm_io_w_mb(AXI_HALT_CLEAR,
+ msm_camera_io_w(VFE_IMASK_RESET,
+ vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
+ msm_camera_io_w_mb(AXI_HALT_CLEAR,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
}
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
- irq.camifStatus = msm_io_r(val);
+ irq.camifStatus = msm_camera_io_r(val);
CDBG("camifStatus = 0x%x\n", irq.camifStatus);
val = (uint32_t *)(vfe31_ctrl->vfebase + VFE_BUS_PING_PONG_STATUS);
- irq.vfePingPongStatus = msm_io_r(val);
+ irq.vfePingPongStatus = msm_camera_io_r(val);
/* clear the pending interrupt of the same kind.*/
- msm_io_w(irq.vfeIrqStatus0, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(irq.vfeIrqStatus1, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(irq.vfeIrqStatus0,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(irq.vfeIrqStatus1,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
if ((irq.vfeIrqStatus0 == 0) && (irq.vfeIrqStatus1 == 0)) {
CDBG("vfe_parse_irq: vfeIrqStatus0 & 1 are both 0!\n");
@@ -3785,7 +3824,7 @@
VFE_IRQ_STATUS0_CAMIF_EOF_MASK) &&
vfe31_ctrl->xbar_update_pending) {
CDBG("irq camifEofIrq\n");
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_XBAR_CFG_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_XBAR_CFG_OFF,
(void *)vfe31_ctrl->xbar_cfg, V31_XBAR_CFG_LEN);
vfe31_ctrl->xbar_update_pending = 0;
}
diff --git a/drivers/media/video/msm/msm_vfe31_v4l2.c b/drivers/media/video/msm/msm_vfe31_v4l2.c
index ea181df..da9e071 100644
--- a/drivers/media/video/msm/msm_vfe31_v4l2.c
+++ b/drivers/media/video/msm/msm_vfe31_v4l2.c
@@ -33,17 +33,18 @@
#define VFE31_AXI_OFFSET 0x0050
#define vfe31_get_ch_ping_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_get_ch_pong_addr(chn) \
- (msm_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_r(vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_get_ch_addr(ping_pong, chn) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_get_ch_pong_addr(chn) : vfe31_get_ch_ping_addr(chn))
#define vfe31_put_ch_ping_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe31_put_ch_pong_addr(chn, addr) \
- (msm_io_w((addr), vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_w((addr), \
+ vfe31_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe31_put_ch_addr(ping_pong, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe31_put_ch_pong_addr((chn), (addr)) : \
@@ -378,36 +379,36 @@
/* disable all interrupts. */
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
- msm_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* now enable only halt_irq & reset_irq */
- msm_io_w(0xf0000000, /* this is for async timer. */
+ msm_camera_io_w(0xf0000000, /* this is for async timer. */
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* then apply axi halt command. */
- msm_io_w_mb(AXI_HALT,
+ msm_camera_io_w_mb(AXI_HALT,
vfe31_ctrl->vfebase + VFE_AXI_CMD);
- msm_io_w_mb(VFE_RESET_UPON_STOP_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -478,7 +479,7 @@
return -EINVAL;
}
- msm_io_memcpy(vfe31_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase +
vfe31_cmd[VFE_CMD_AXI_OUT_CFG].offset, axi_cfg,
vfe31_cmd[VFE_CMD_AXI_OUT_CFG].length - V31_AXI_CH_INF_LEN -
V31_AXI_RESERVED);
@@ -544,22 +545,24 @@
vfe31_reset_internal_variables();
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
@@ -569,7 +572,7 @@
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_RESET_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
vfe31_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -581,11 +584,11 @@
vfe31_ctrl->stats_comp = *(++p);
vfe31_ctrl->hfr_mode = *(++p);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
- msm_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p), vfe31_ctrl->vfebase + VFE_STATS_CFG);
return 0;
}
@@ -595,9 +598,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe31_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
@@ -608,9 +613,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe31_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -622,9 +629,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe31_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -636,9 +645,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe31_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -650,9 +661,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe31_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -664,15 +677,17 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe31_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
-static void msm_io_dump2(void __iomem *addr, int size)
+static void msm_camera_io_dump2(void __iomem *addr, int size)
{
char line_str[BUFF_SIZE_128], *p_str;
int i;
@@ -710,16 +725,16 @@
else
irq_mask |= 0x000FE000;
- msm_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(irq_mask, vfe31_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe31_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
- msm_io_dump2(vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
+ msm_camera_io_dump2(vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
atomic_set(&vfe31_ctrl->vstate, 1);
}
@@ -729,7 +744,7 @@
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_VIDEO);
vfe31_ctrl->recording_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
@@ -737,7 +752,7 @@
{
struct msm_sync *sync = vfe_syncdata;
vfe31_ctrl->recording_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
return 0;
@@ -753,7 +768,7 @@
vfe31_ctrl->vfe_capture_count = vfe31_ctrl->outpath.out0.capture_cnt;
vfe31_ctrl->liveshot_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
}
static int vfe31_zsl(void)
@@ -762,7 +777,7 @@
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
vfe31_ctrl->operation_mode, vfe31_ctrl->outpath.output_mode);
@@ -788,42 +803,42 @@
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch2]);
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
vfe31_start_common();
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_ZSL);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x188);
return 0;
}
static int vfe31_capture_raw(uint32_t num_frames_capture)
@@ -835,15 +850,15 @@
vfe31_ctrl->vfe_capture_count = num_frames_capture;
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << (vfe31_ctrl->outpath.out0.ch0));
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe31_start_common();
@@ -869,7 +884,8 @@
}
vfe31_ctrl->vfe_capture_count = num_frames_capture;
- irq_comp_mask = msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ irq_comp_mask = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
vfe31_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
@@ -887,31 +903,31 @@
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
}
vfe31_ctrl->vfe_capture_count = num_frames_capture;
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe31_start_common();
/* for debug */
- msm_io_w(1, vfe31_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe31_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + 0x188);
return 0;
}
@@ -921,7 +937,7 @@
struct msm_sync *sync = vfe_syncdata;
irq_comp_mask =
- msm_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe31_ctrl->outpath.output_mode & VFE31_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << vfe31_ctrl->outpath.out0.ch0 |
@@ -941,41 +957,41 @@
0x1 << (vfe31_ctrl->outpath.out1.ch1 + 8) |
0x1 << (vfe31_ctrl->outpath.out1.ch2 + 8));
}
- msm_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe31_ctrl->vfebase + VFE_IRQ_COMP_MASK);
switch (vfe31_ctrl->operation_mode) {
case VFE_OUTPUTS_PREVIEW:
case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch2]);
}
break;
default:
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
} else if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch2]);
}
break;
@@ -991,18 +1007,18 @@
unsigned long flags;
if (vfe31_ctrl->update_la) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
- msm_io_w(1, vfe31_ctrl->vfebase + V31_LA_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + V31_LA_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase + V31_LA_OFF);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + V31_LA_OFF);
vfe31_ctrl->update_la = false;
}
if (vfe31_ctrl->update_gamma) {
- if (!msm_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF))
- msm_io_w(7, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
+ if (!msm_camera_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF))
+ msm_camera_io_w(7, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
else
- msm_io_w(0, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase+V31_RGB_G_OFF);
vfe31_ctrl->update_gamma = false;
}
@@ -1011,7 +1027,7 @@
spin_unlock_irqrestore(&vfe31_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
@@ -1027,7 +1043,7 @@
value = 0x40000;
/* Timer Stop */
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
}
static void vfe31_sync_timer_start(const uint32_t *tbl)
@@ -1052,14 +1068,14 @@
}
/* Timer Start */
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
4 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
8 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
@@ -1067,14 +1083,15 @@
val = 10000000 / val;
val = value * 10000 / val;
CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
- msm_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
+ msm_camera_io_w(val, vfe31_ctrl->vfebase + V31_SYNC_TIMER_OFF +
12 + ((vfe31_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
+ msm_camera_io_w(value,
+ vfe31_ctrl->vfebase + V31_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + V31_TIMER_SELECT_OFF);
}
static void vfe31_program_dmi_cfg(enum VFE31_DMI_RAM_SEL bankSel)
@@ -1084,9 +1101,9 @@
value += (uint32_t)bankSel;
CDBG("%s: banksel = %d\n", __func__, bankSel);
- msm_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w(value, vfe31_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_DMI_ADDR);
}
static void vfe31_write_gamma_cfg(enum VFE31_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
@@ -1098,8 +1115,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1111,7 +1130,7 @@
vfe31_program_dmi_cfg(channel_sel);
CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
for (i = 0 ; i < VFE31_GAMMA_NUM_ENTRIES ; i++) {
- *tbl = msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *tbl = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *tbl);
tbl++;
}
@@ -1129,8 +1148,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe31_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1363,11 +1384,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_STATS_AF_START:
@@ -1382,11 +1404,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_STATS_AWB_START:
@@ -1401,12 +1424,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
- cmdp, (vfe31_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ cmdp, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_STATS_IHIST_START:
@@ -1421,11 +1445,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -1441,7 +1466,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -1457,7 +1483,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -1466,7 +1493,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1482,19 +1509,22 @@
new_val = *cmdp_local;
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
&new_val, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
break;
case VFE_CMD_CHROMA_SUP_UPDATE:
@@ -1511,7 +1541,7 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF,
cmdp_local, 4);
cmdp_local += 1;
@@ -1519,20 +1549,22 @@
/* Incrementing with 4 so as to point to the 2nd Register as
* the 2nd register has the mce_enable bit
*/
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 4);
old_val &= ~MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase +
V31_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= ~MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_CHROMA_SUP_OFF + 8,
&new_val, 4);
break;
@@ -1548,23 +1580,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, 16);
cmdp_local += 4;
vfe31_program_dmi_cfg(ROLLOFF_RAM);
/* for loop for extrcting init table. */
for (i = 0; i < (V31_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local ,
+ msm_camera_io_w(*cmdp_local ,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
- msm_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe31_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0; i < (V31_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
@@ -1587,17 +1620,17 @@
vfe31_program_dmi_cfg(ROLLOFF_RAM);
CDBG("%s: Mesh Rolloff init Table\n", __func__);
for (i = 0; i < (V31_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
- *cmdp_local =
- msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
- msm_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V31_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe31_ctrl->vfebase + VFE_DMI_ADDR);
CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
for (i = 0; i < (V31_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
- *cmdp_local =
- msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
@@ -1623,7 +1656,8 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
cmdp_local += 1;
@@ -1645,7 +1679,7 @@
}
cmdp_local = cmdp + 1;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_LA_OFF);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + V31_LA_OFF);
if (old_val != 0x0)
vfe31_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
cmdp_local);
@@ -1667,14 +1701,14 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
+ if (msm_camera_io_r(vfe31_ctrl->vfebase + V31_LA_OFF))
vfe31_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
else
vfe31_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
for (i = 0 ; i < (VFE31_LA_TABLE_LENGTH / 2) ; i++) {
- *cmdp_local =
- msm_io_r(vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
- *cmdp_local |= (msm_io_r(vfe31_ctrl->vfebase +
+ *cmdp_local = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_DMI_DATA_LO)) << 16;
cmdp_local++;
}
@@ -1698,7 +1732,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_SCE_OFF,
cmdp, V31_SCE_LEN);
break;
@@ -1734,12 +1768,13 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, V31_DEMOSAICV3_LEN);
break;
@@ -1763,12 +1798,13 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, V31_DEMOSAICV3_LEN);
break;
@@ -1793,16 +1829,18 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp_local, (vfe31_cmd[cmd->id].length));
break;
@@ -1826,15 +1864,17 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
+ old_val = msm_camera_io_r(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF);
old_val &= BPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_OFF,
cmdp_local, V31_DEMOSAICV3_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_DEMOSAICV3_DBPC_CFG_OFF,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + V31_DEMOSAICV3_DBPC_CFG_OFF,
cmdp_local, V31_DEMOSAICV3_DBPC_LEN);
break;
@@ -1850,7 +1890,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
+ msm_camera_io_memcpy(vfe31_ctrl->vfebase + V31_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
@@ -1872,7 +1912,7 @@
goto proc_general_done;
}
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
cmdp += 1;
if (old_val != 0x0) {
vfe31_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp);
@@ -1900,7 +1940,7 @@
}
cmdp_local = cmdp;
- old_val = msm_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + V31_RGB_G_OFF);
temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
RGBLUT_RAM_CH0_BANK0;
for (i = 0; i < 3; i++) {
@@ -1916,42 +1956,42 @@
break;
case VFE_CMD_STATS_AWB_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_AE_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_AF_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_IHIST_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_RS_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
case VFE_CMD_STATS_CS_STOP:
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe31_ctrl->vfebase + VFE_MODULE_CFG);
break;
@@ -1988,11 +2028,12 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -2021,7 +2062,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
cmdp_local = cmdp + V31_ASF_LEN/4;
break;
@@ -2036,7 +2078,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- *cmdp = msm_io_r(vfe31_ctrl->vfebase+V31_GET_HW_VERSION_OFF);
+ *cmdp = msm_camera_io_r(
+ vfe31_ctrl->vfebase+V31_GET_HW_VERSION_OFF);
if (copy_to_user((void __user *)(cmd->value), cmdp,
V31_GET_HW_VERSION_LEN)) {
rc = -EFAULT;
@@ -2054,7 +2097,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- msm_io_dump(vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
+ msm_camera_io_dump(
+ vfe31_ctrl->vfebase, vfe31_ctrl->register_total*4);
CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
vfe31_ctrl->vfebase, temp1);
memcpy_fromio((void *)cmdp, vfe31_ctrl->vfebase, temp1);
@@ -2078,7 +2122,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
vfe31_ctrl->frame_skip_cnt = ((uint32_t)
*cmdp & VFE_FRAME_SKIP_PERIOD_MASK) + 1;
@@ -2099,7 +2144,8 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe31_ctrl->vfebase + vfe31_cmd[cmd->id].offset,
cmdp, (vfe31_cmd[cmd->id].length));
break;
@@ -2186,22 +2232,24 @@
uint32_t *temp;
memset(out, 0, sizeof(struct vfe31_irq_status));
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_0);
- out->vfeIrqStatus0 = msm_io_r(temp);
+ out->vfeIrqStatus0 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_IRQ_STATUS_1);
- out->vfeIrqStatus1 = msm_io_r(temp);
+ out->vfeIrqStatus1 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
- out->camifStatus = msm_io_r(temp);
+ out->camifStatus = msm_camera_io_r(temp);
CDBG("camifStatus = 0x%x\n", out->camifStatus);
/* clear the pending interrupt of the same kind.*/
- msm_io_w(out->vfeIrqStatus0, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(out->vfeIrqStatus1, vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(out->vfeIrqStatus0,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(out->vfeIrqStatus1,
+ vfe31_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_IRQ_CMD);
}
@@ -2212,33 +2260,33 @@
if (vfe31_ctrl->recording_state == VFE_STATE_START_REQUESTED) {
if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
vfe31_ctrl->recording_state = VFE_STATE_STARTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe31_ctrl->recording_state ==
VFE_STATE_STOP_REQUESTED) {
if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
} else if (vfe31_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out1.ch1]);
}
CDBG("stop video triggered .\n");
@@ -2254,7 +2302,7 @@
/* request a reg update and send STOP_REC_ACK
* when we process the next reg update irq.
*/
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe31_ctrl->recording_state ==
VFE_STATE_STOPPED) {
@@ -2277,9 +2325,9 @@
pr_info("%s enabling liveshot output\n", __func__);
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w(1, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
vfe31_ctrl->liveshot_state = VFE_STATE_STARTED;
}
@@ -2289,17 +2337,17 @@
vfe31_ctrl->vfe_capture_count--;
if (!vfe31_ctrl->vfe_capture_count)
vfe31_ctrl->liveshot_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe31_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED) {
CDBG("%s: disabling liveshot output\n", __func__);
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->outpath.out0.ch1]);
vfe31_ctrl->liveshot_state = VFE_STATE_STOPPED;
- msm_io_w_mb(1, vfe31_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe31_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
}
} else if (vfe31_ctrl->liveshot_state == VFE_STATE_STOPPED) {
@@ -2321,23 +2369,23 @@
/* stop the bus output:write master enable = 0*/
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out0.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out0.ch1]);
}
if (vfe31_ctrl->outpath.output_mode &
VFE31_OUTPUT_MODE_SECONDARY) {
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch0]);
- msm_io_w(0, vfe31_ctrl->vfebase +
+ msm_camera_io_w(0, vfe31_ctrl->vfebase +
vfe31_AXI_WM_CFG[vfe31_ctrl->
outpath.out1.ch1]);
}
- msm_io_w_mb
+ msm_camera_io_w_mb
(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
vfe31_ctrl->snapshot_frame_cnt = -1;
@@ -2347,39 +2395,46 @@
} /*if frame is not being dropped*/
vfe31_ctrl->snapshot_frame_cnt++;
/* then do reg_update. */
- msm_io_w(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1, vfe31_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
static void vfe31_set_default_reg_values(void)
{
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080, vfe31_ctrl->vfebase + VFE_DEMUX_GAIN_1);
/* What value should we program CGC_OVERRIDE to? */
- msm_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0xFFFFF, vfe31_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- msm_io_w(0xFFFFFFFF, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0xFFFFFFFF,
+ vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f, vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0xFFFFFFFF,
vfe31_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
+ msm_camera_io_w(0, vfe31_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF, vfe31_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
- msm_io_w(0x3980007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
- msm_io_w(0x3A00007, vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
- msm_io_w(0x3A8000F, vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
- msm_io_w(0x3B80007, vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
- msm_io_w(0x3C0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
- msm_io_w(0x3E0001F, vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ msm_camera_io_w(0x3980007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ msm_camera_io_w(0x3A00007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ msm_camera_io_w(0x3A8000F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ msm_camera_io_w(0x3B80007,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ msm_camera_io_w(0x3C0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ msm_camera_io_w(0x3E0001F,
+ vfe31_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
static void vfe31_process_reset_irq(void)
@@ -2399,7 +2454,7 @@
vfe31_set_default_reg_values();
/* reload all write masters. (frame & line)*/
- msm_io_w(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
+ msm_camera_io_w(0x7FFF, vfe31_ctrl->vfebase + VFE_BUS_CMD);
vfe31_send_isp_msg(vfe31_ctrl, MSG_ID_RESET_ACK);
}
}
@@ -2417,7 +2472,7 @@
if (vfe31_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe31_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
@@ -2446,7 +2501,8 @@
if (errStatus & VFE31_IMASK_CAMIF_ERROR) {
pr_err("vfe31_irq: camif errors\n");
- reg_value = msm_io_r(vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
+ reg_value = msm_camera_io_r(
+ vfe31_ctrl->vfebase + VFE_CAMIF_STATUS);
pr_err("camifStatus = 0x%x\n", reg_value);
vfe31_send_isp_msg(vfe31_ctrl, MSG_ID_CAMIF_ERROR);
}
@@ -2514,21 +2570,21 @@
if (errStatus & VFE31_IMASK_AXI_ERROR) {
pr_err("vfe31_irq: axi error\n");
/* read status too when overflow happens.*/
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
pr_debug("VFE_BUS_PING_PONG_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_OPERATION_STATUS);
pr_debug("VFE_BUS_OPERATION_STATUS = 0x%x\n", read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_0 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1);
pr_debug("VFE_BUS_IMAGE_MASTER_0_WR_PM_STATS_1 = 0x%x\n",
read_val);
- read_val = msm_io_r(vfe31_ctrl->vfebase +
+ read_val = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_AXI_STATUS);
pr_debug("VFE_AXI_STATUS = 0x%x\n", read_val);
}
@@ -2576,7 +2632,7 @@
(vfe31_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe31_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Channel 0*/
@@ -2652,7 +2708,7 @@
(vfe31_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe31_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Y channel */
@@ -2709,7 +2765,7 @@
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_io_r(vfe31_ctrl->vfebase +
+ ((msm_camera_io_r(vfe31_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
@@ -2718,8 +2774,8 @@
((uint32_t)(vfe31_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
- returnAddr = msm_io_r((uint32_t *)pingpongAddr);
- msm_io_w(newAddr, (uint32_t *)pingpongAddr);
+ returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
+ msm_camera_io_w(newAddr, (uint32_t *)pingpongAddr);
return returnAddr;
}
@@ -2807,7 +2863,7 @@
msgStats.rs.buff = vfe31_ctrl->rsStatsControl.bufToRender;
msgStats.cs.buff = vfe31_ctrl->csStatsControl.bufToRender;
- temp = msm_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(vfe31_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msgStats.awb_ymin = (0xFF00 & temp) >> 8;
v4l2_subdev_notify(&vfe31_ctrl->subdev,
@@ -3118,7 +3174,7 @@
if ((vfe31_ctrl->outpath.out0.capture_cnt == 0)
&& (vfe31_ctrl->outpath.out1.
capture_cnt == 0)) {
- msm_io_w_mb(
+ msm_camera_io_w_mb(
CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe31_ctrl->vfebase +
VFE_CAMIF_COMMAND);
@@ -3593,20 +3649,20 @@
msm_vfe_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
usleep_range(10000, 15000);
- reg = (msm_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
reg |= 0x3;
- msm_io_w(reg, vfe31_ctrl->camifbase);
+ msm_camera_io_w(reg, vfe31_ctrl->camifbase);
usleep_range(10000, 15000);
- reg = (msm_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
reg |= 0x10;
- msm_io_w(reg, vfe31_ctrl->camifbase);
+ msm_camera_io_w(reg, vfe31_ctrl->camifbase);
usleep_range(10000, 15000);
- reg = (msm_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
+ reg = (msm_camera_io_r(vfe31_ctrl->camifbase)) & CAMIF_CFG_RMSK;
/* Need to be uninverted*/
reg &= 0x03;
- msm_io_w(reg, vfe31_ctrl->camifbase);
+ msm_camera_io_w(reg, vfe31_ctrl->camifbase);
usleep_range(10000, 15000);
}
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 84b9b28..2f0b6c9 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -28,27 +28,20 @@
atomic_t irq_cnt;
-#define CHECKED_COPY_FROM_USER(in) { \
- if (copy_from_user((in), (void __user *)cmd->value, \
- cmd->length)) { \
- rc = -EFAULT; \
- break; \
- } \
-}
-
#define VFE32_AXI_OFFSET 0x0050
#define vfe32_get_ch_ping_addr(chn) \
- (msm_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe32_get_ch_pong_addr(chn) \
- (msm_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_r(vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe32_get_ch_addr(ping_pong, chn) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe32_get_ch_pong_addr(chn) : vfe32_get_ch_ping_addr(chn))
#define vfe32_put_ch_ping_addr(chn, addr) \
- (msm_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
+ (msm_camera_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn)))
#define vfe32_put_ch_pong_addr(chn, addr) \
- (msm_io_w((addr), vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
+ (msm_camera_io_w((addr), \
+ vfe32_ctrl->vfebase + 0x0050 + 0x18 * (chn) + 4))
#define vfe32_put_ch_addr(ping_pong, chn, addr) \
(((ping_pong) & (1 << (chn))) == 0 ? \
vfe32_put_ch_pong_addr((chn), (addr)) : \
@@ -377,50 +370,50 @@
spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
/* disable all interrupts. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS,
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe32_ctrl->vfebase + VFE_IRQ_CMD);
/* in either continuous or snapshot mode, stop command can be issued
* at any time. stop camif immediately. */
- msm_io_w(CAMIF_COMMAND_STOP_IMMEDIATELY,
+ msm_camera_io_w(CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
/* axi halt command. */
- msm_io_w(AXI_HALT,
+ msm_camera_io_w(AXI_HALT,
vfe32_ctrl->vfebase + VFE_AXI_CMD);
wmb();
while (axiBusyFlag) {
- if (msm_io_r(vfe32_ctrl->vfebase + VFE_AXI_STATUS) & 0x1)
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + VFE_AXI_STATUS) & 0x1)
axiBusyFlag = false;
}
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(AXI_HALT_CLEAR,
+ msm_camera_io_w_mb(AXI_HALT_CLEAR,
vfe32_ctrl->vfebase + VFE_AXI_CMD);
/* after axi halt, then ok to apply global reset. */
/* enable reset_ack and async timer interrupt only while
stopping the pipeline.*/
- msm_io_w(0xf0000000,
+ msm_camera_io_w(0xf0000000,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_STOP_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_STOP_CMD,
vfe32_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -490,9 +483,9 @@
pr_err("%s Invalid AXI mode %d ", __func__, mode);
return -EINVAL;
}
- msm_io_w(*ao, vfe32_ctrl->vfebase +
+ msm_camera_io_w(*ao, vfe32_ctrl->vfebase +
VFE_BUS_IO_FORMAT_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
vfe32_cmd[VFE_CMD_AXI_OUT_CFG].offset, axi_cfg,
vfe32_cmd[VFE_CMD_AXI_OUT_CFG].length - V32_AXI_CH_INF_LEN
- V32_AXI_BUS_FMT_LEN);
@@ -558,22 +551,24 @@
vfe32_reset_internal_variables();
/* disable all interrupts. vfeImaskLocal is also reset to 0
* to begin with. */
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_DISABLE_ALL_IRQS,
+ msm_camera_io_w(VFE_DISABLE_ALL_IRQS,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* clear all pending interrupts*/
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(VFE_CLEAR_ALL_IRQS, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(VFE_CLEAR_ALL_IRQS,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
/* enable reset_ack interrupt. */
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Write to VFE_GLOBAL_RESET_CMD to reset the vfe hardware. Once reset
@@ -583,7 +578,7 @@
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(VFE_RESET_UPON_RESET_CMD,
+ msm_camera_io_w_mb(VFE_RESET_UPON_RESET_CMD,
vfe32_ctrl->vfebase + VFE_GLOBAL_RESET);
}
@@ -595,20 +590,20 @@
vfe32_ctrl->stats_comp = *(++p);
vfe32_ctrl->hfr_mode = *(++p);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CFG);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_PIXEL_IF_CFG);
- if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_PIXEL_IF_CFG);
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
VFE33_HW_NUMBER) {
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI0_CFG);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI1_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI0_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_RDI1_CFG);
} else {
++p;
++p;
}
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_REALIGN_BUF);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CHROMA_UP);
- msm_io_w(*(++p), vfe32_ctrl->vfebase + VFE_STATS_CFG);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_REALIGN_BUF);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_CHROMA_UP);
+ msm_camera_io_w(*(++p), vfe32_ctrl->vfebase + VFE_STATS_CFG);
return 0;
}
@@ -618,9 +613,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
vfe32_ctrl->awbStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
}
@@ -631,9 +628,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_WR_PONG_ADDR);
vfe32_ctrl->aecStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -645,9 +644,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
vfe32_ctrl->afStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -659,9 +660,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
vfe32_ctrl->ihistStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -673,9 +676,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_WR_PONG_ADDR);
vfe32_ctrl->rsStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -687,9 +692,11 @@
uint32_t addr;
addr = ptr[0];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PING_ADDR);
addr = ptr[1];
- msm_io_w(addr, vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
+ msm_camera_io_w(addr,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_WR_PONG_ADDR);
vfe32_ctrl->csStatsControl.nextFrameAddrBuf = in->statsBuf[2];
return 0;
@@ -706,14 +713,14 @@
else
irq_mask |= 0x000FE000;
- msm_io_w(irq_mask, vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
- msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
+ msm_camera_io_w(irq_mask, vfe32_ctrl->vfebase + VFE_IRQ_MASK_0);
+ msm_camera_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
atomic_set(&vfe32_ctrl->vstate, 1);
@@ -725,7 +732,7 @@
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_VIDEO);
vfe32_ctrl->recording_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return 0;
}
@@ -733,7 +740,7 @@
{
struct msm_sync *sync = vfe_syncdata;
vfe32_ctrl->recording_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
return 0;
@@ -749,7 +756,7 @@
vfe32_ctrl->vfe_capture_count = vfe32_ctrl->outpath.out0.capture_cnt;
vfe32_ctrl->liveshot_state = VFE_STATE_START_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
}
static int vfe32_zsl(void)
@@ -758,7 +765,7 @@
uint32_t irq_comp_mask = 0;
/* capture command is valid for both idle and active state. */
irq_comp_mask =
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
CDBG("%s:op mode %d O/P Mode %d\n", __func__,
vfe32_ctrl->operation_mode, vfe32_ctrl->outpath.output_mode);
@@ -784,42 +791,42 @@
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
}
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch2]);
}
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
vfe32_start_common();
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_ZSL);
- msm_io_w(1, vfe32_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe32_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x188);
return 0;
}
static int vfe32_capture_raw(uint32_t num_frames_capture)
@@ -831,15 +838,15 @@
vfe32_ctrl->vfe_capture_count = num_frames_capture;
irq_comp_mask =
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << (vfe32_ctrl->outpath.out0.ch0));
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
}
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe32_start_common();
@@ -865,7 +872,8 @@
}
vfe32_ctrl->vfe_capture_count = num_frames_capture;
- irq_comp_mask = msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ irq_comp_mask = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
@@ -883,31 +891,31 @@
}
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
}
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
}
vfe32_ctrl->vfe_capture_count = num_frames_capture;
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
p_sync->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
vfe32_start_common();
/* for debug */
- msm_io_w(1, vfe32_ctrl->vfebase + 0x18C);
- msm_io_w(1, vfe32_ctrl->vfebase + 0x188);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x18C);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + 0x188);
return 0;
}
@@ -917,7 +925,7 @@
struct msm_sync *sync = vfe_syncdata;
irq_comp_mask =
- msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
if (vfe32_ctrl->outpath.output_mode & VFE32_OUTPUT_MODE_PRIMARY) {
irq_comp_mask |= (0x1 << vfe32_ctrl->outpath.out0.ch0 |
@@ -937,41 +945,41 @@
0x1 << (vfe32_ctrl->outpath.out1.ch1 + 8) |
0x1 << (vfe32_ctrl->outpath.out1.ch2 + 8));
}
- msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
+ msm_camera_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
switch (vfe32_ctrl->operation_mode) {
case VFE_OUTPUTS_PREVIEW:
case VFE_OUTPUTS_PREVIEW_AND_VIDEO:
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch2]);
}
break;
default:
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
} else if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY_ALL_CHNLS) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch2]);
}
break;
@@ -988,38 +996,39 @@
unsigned long flags;
uint32_t value = 0;
if (vfe32_ctrl->update_linear) {
- if (!msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
- msm_io_w(1,
+ if (!msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ msm_camera_io_w(1,
vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
else
- msm_io_w(0,
+ msm_camera_io_w(0,
vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
vfe32_ctrl->update_linear = false;
}
if (vfe32_ctrl->update_rolloff) {
- value = msm_io_r(vfe32_ctrl->vfebase +
+ value = msm_camera_io_r(vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1);
value ^= V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
- msm_io_w(value, vfe32_ctrl->vfebase +
+ msm_camera_io_w(value, vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1);
vfe32_ctrl->update_rolloff = false;
}
if (vfe32_ctrl->update_la) {
- if (!msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
- msm_io_w(1,
+ if (!msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ msm_camera_io_w(1,
vfe32_ctrl->vfebase + V32_LA_OFF);
else
- msm_io_w(0,
+ msm_camera_io_w(0,
vfe32_ctrl->vfebase + V32_LA_OFF);
vfe32_ctrl->update_la = false;
}
if (vfe32_ctrl->update_gamma) {
- value = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ value = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
value ^= V32_GAMMA_LUT_BANK_SEL_MASK;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_RGB_G_OFF);
vfe32_ctrl->update_gamma = false;
}
@@ -1028,7 +1037,7 @@
spin_unlock_irqrestore(&vfe32_ctrl->update_ack_lock, flags);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
return;
}
@@ -1044,7 +1053,7 @@
value = 0x40000;
/* Timer Stop */
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
}
static void vfe32_sync_timer_start(const uint32_t *tbl)
@@ -1069,14 +1078,14 @@
}
/* Timer Start */
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF);
/* Sync Timer Line Start */
value = *tbl++;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
4 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Start */
value = *tbl++;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
8 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Sync Timer Pixel Duration */
value = *tbl++;
@@ -1084,14 +1093,15 @@
val = 10000000 / val;
val = value * 10000 / val;
CDBG("%s: Pixel Clk Cycles!!! %d\n", __func__, val);
- msm_io_w(val, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
+ msm_camera_io_w(val, vfe32_ctrl->vfebase + V32_SYNC_TIMER_OFF +
12 + ((vfe32_ctrl->sync_timer_number) * 12));
/* Timer0 Active High/LOW */
value = *tbl++;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_SYNC_TIMER_POLARITY_OFF);
+ msm_camera_io_w(value,
+ vfe32_ctrl->vfebase + V32_SYNC_TIMER_POLARITY_OFF);
/* Selects sync timer 0 output to drive onto timer1 port */
value = 0;
- msm_io_w(value, vfe32_ctrl->vfebase + V32_TIMER_SELECT_OFF);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + V32_TIMER_SELECT_OFF);
}
static void vfe32_program_dmi_cfg(enum VFE32_DMI_RAM_SEL bankSel)
@@ -1101,9 +1111,9 @@
value += (uint32_t)bankSel;
CDBG("%s: banksel = %d\n", __func__, bankSel);
- msm_io_w(value, vfe32_ctrl->vfebase + VFE_DMI_CFG);
+ msm_camera_io_w(value, vfe32_ctrl->vfebase + VFE_DMI_CFG);
/* by default, always starts with offset 0.*/
- msm_io_w(0, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(0, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
}
static void vfe32_write_gamma_cfg(enum VFE32_DMI_RAM_SEL channel_sel,
const uint32_t *tbl)
@@ -1115,8 +1125,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1128,7 +1140,7 @@
vfe32_program_dmi_cfg(channel_sel);
CDBG("%s: Gamma table channel: %d\n", __func__, channel_sel);
for (i = 0 ; i < VFE32_GAMMA_NUM_ENTRIES ; i++) {
- *tbl = msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *tbl = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *tbl);
tbl++;
}
@@ -1146,8 +1158,10 @@
value = *tbl++;
value1 = value & 0x0000FFFF;
value2 = (value & 0xFFFF0000)>>16;
- msm_io_w((value1), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- msm_io_w((value2), vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value1),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w((value2),
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
}
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
@@ -1225,7 +1239,7 @@
vfe32_program_dmi_cfg(channel_sel);
/* for loop for configuring LUT. */
for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
- msm_io_w(*tbl, vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_w(*tbl, vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
tbl++;
}
CDBG("done writing to linearization table\n");
@@ -1399,12 +1413,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_STATS_AF_START: {
@@ -1419,12 +1434,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_STATS_AWB_START: {
@@ -1439,12 +1455,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1460,12 +1477,13 @@
rc = -EFAULT;
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val |= IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1482,8 +1500,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1499,8 +1518,9 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1509,7 +1529,7 @@
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
/* Incrementing with 4 so as to point to the 2nd Register as
the 2nd register has the mce_enable bit */
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 4);
if (!cmdp) {
rc = -ENOMEM;
@@ -1525,20 +1545,23 @@
new_val = *cmdp_local;
old_val &= MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
- &new_val, 4);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
+ &new_val, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp_local, (vfe32_cmd[cmd->id].length));
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp_local, (vfe32_cmd[cmd->id].length));
}
break;
case VFE_CMD_CHROMA_SUP_UPDATE:
@@ -1555,7 +1578,7 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF,
cmdp_local, 4);
cmdp_local += 1;
@@ -1563,20 +1586,22 @@
/* Incrementing with 4 so as to point to the 2nd Register as
* the 2nd register has the mce_enable bit
*/
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 4);
old_val &= ~MCE_EN_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 4,
&new_val, 4);
cmdp_local += 1;
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V32_CHROMA_SUP_OFF + 8);
new_val = *cmdp_local;
old_val &= ~MCE_Q_K_MASK;
new_val = new_val | old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_CHROMA_SUP_OFF + 8,
&new_val, 4);
}
break;
@@ -1596,23 +1621,24 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
- cmdp_local, 16);
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ cmdp_local, 16);
cmdp_local += 4;
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
/* for loop for extrcting init table. */
for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local ,
+ msm_camera_io_w(*cmdp_local ,
vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
CDBG("done writing init table\n");
/* by default, always starts with offset 0. */
- msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe32_ctrl->vfebase + VFE_DMI_ADDR);
/* for loop for extracting delta table. */
for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
cmdp_local++;
}
@@ -1637,16 +1663,18 @@
CDBG("%s: Mesh Rolloff init Table\n", __func__);
for (i = 0; i < (V32_MESH_ROLL_OFF_INIT_TABLE_SIZE * 2); i++) {
*cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
- msm_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
+ msm_camera_io_w(V32_MESH_ROLL_OFF_DELTA_TABLE_OFFSET,
vfe32_ctrl->vfebase + VFE_DMI_ADDR);
CDBG("%s: Mesh Rolloff Delta Table\n", __func__);
for (i = 0; i < (V32_MESH_ROLL_OFF_DELTA_TABLE_SIZE * 2); i++) {
*cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
@@ -1672,7 +1700,8 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
cmdp_local += 1;
@@ -1694,7 +1723,7 @@
}
cmdp_local = cmdp + 1;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF);
if (old_val != 0x0)
vfe32_write_la_cfg(LUMA_ADAPT_LUT_RAM_BANK0,
cmdp_local);
@@ -1717,14 +1746,15 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_LA_OFF))
vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK1);
else
vfe32_program_dmi_cfg(LUMA_ADAPT_LUT_RAM_BANK0);
for (i = 0 ; i < (VFE32_LA_TABLE_LENGTH / 2) ; i++) {
*cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
- *cmdp_local |= (msm_io_r(vfe32_ctrl->vfebase +
+ msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local |= (msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_DMI_DATA_LO)) << 16;
cmdp_local++;
}
@@ -1748,7 +1778,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_SCE_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_SCE_OFF,
cmdp, V32_SCE_LEN);
}
break;
@@ -1778,10 +1808,12 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1,
cmdp_local, V32_LINEARIZATION_LEN1);
cmdp_local += 4;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
cmdp_local, V32_LINEARIZATION_LEN2);
cmdp_local = cmdp + 17;
@@ -1801,15 +1833,17 @@
}
cmdp_local = cmdp;
cmdp_local++;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1 + 4,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1 + 4,
cmdp_local, (V32_LINEARIZATION_LEN1 - 4));
cmdp_local += 3;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF2,
cmdp_local, V32_LINEARIZATION_LEN2);
cmdp_local = cmdp + 17;
/*extracting the bank select*/
- old_val =
- msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1);
if (old_val != 0x0)
vfe32_write_linear_cfg(BLACK_LUT_RAM_BANK0, cmdp_local);
@@ -1830,14 +1864,15 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- if (msm_io_r(vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
+ if (msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_LINEARIZATION_OFF1))
vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK1);
else
vfe32_program_dmi_cfg(BLACK_LUT_RAM_BANK0);
CDBG("%s: Linearization Table\n", __func__);
for (i = 0 ; i < VFE32_LINEARIZATON_TABLE_LENGTH ; i++) {
- *cmdp_local =
- msm_io_r(vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
+ *cmdp_local = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_DMI_DATA_LO);
CDBG("%s: %08x\n", __func__, *cmdp_local);
cmdp_local++;
}
@@ -1868,15 +1903,16 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
cmdp_local, V32_DEMOSAICV3_1_LEN);
break;
@@ -1900,22 +1936,23 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DEMOSAIC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_0_LEN);
/* As the address space is not contiguous increment by 2
* before copying to next address space */
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_1_OFF,
cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
/* As the address space is not contiguous increment by 2
* before copying to next address space */
cmdp_local += 2;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_2_OFF,
cmdp_local, 2 * V32_DEMOSAICV3_0_LEN);
break;
@@ -1939,16 +1976,18 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= ABF_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
}
break;
@@ -1969,15 +2008,17 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DBCC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF,
cmdp_local, 4);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp_local, (vfe32_cmd[cmd->id].length));
break;
@@ -1997,28 +2038,29 @@
cmdp_local = cmdp;
new_val = *cmdp_local;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
+ old_val = msm_camera_io_r(
+ vfe32_ctrl->vfebase + V32_DEMOSAICV3_0_OFF);
old_val &= DBPC_MASK;
new_val = new_val | old_val;
*cmdp_local = new_val;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_0_OFF,
cmdp_local, V32_DEMOSAICV3_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF0,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF1,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
cmdp_local += 1;
- msm_io_memcpy(vfe32_ctrl->vfebase +
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase +
V32_DEMOSAICV3_DBPC_CFG_OFF2,
cmdp_local, V32_DEMOSAICV3_DBPC_LEN);
break;
@@ -2035,7 +2077,7 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_RGB_G_OFF,
+ msm_camera_io_memcpy(vfe32_ctrl->vfebase + V32_RGB_G_OFF,
cmdp, 4);
cmdp += 1;
@@ -2058,7 +2100,7 @@
goto proc_general_done;
}
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
cmdp += 1;
if (old_val != 0x0) {
vfe32_write_gamma_cfg(RGBLUT_RAM_CH0_BANK0, cmdp);
@@ -2087,7 +2129,7 @@
}
cmdp_local = cmdp;
- old_val = msm_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + V32_RGB_G_OFF);
temp2 = old_val ? RGBLUT_RAM_CH0_BANK1 :
RGBLUT_RAM_CH0_BANK0;
for (i = 0; i < 3; i++) {
@@ -2103,47 +2145,47 @@
break;
case VFE_CMD_STATS_AWB_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AWB_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_AE_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AE_BG_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_AF_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~AF_BF_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_IHIST_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~IHIST_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_RS_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~RS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
case VFE_CMD_STATS_CS_STOP: {
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= ~CS_ENABLE_MASK;
- msm_io_w(old_val,
+ msm_camera_io_w(old_val,
vfe32_ctrl->vfebase + VFE_MODULE_CFG);
}
break;
@@ -2180,11 +2222,12 @@
goto proc_general_done;
}
*cmdp &= ~STATS_ENABLE_MASK;
- old_val = msm_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_MODULE_CFG);
old_val &= STATS_ENABLE_MASK;
*cmdp |= old_val;
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
}
break;
@@ -2214,10 +2257,12 @@
rc = -EFAULT;
goto proc_general_done;
}
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
cmdp_local = cmdp + V32_ASF_LEN/4;
- msm_io_memcpy(vfe32_ctrl->vfebase + V32_ASF_SPECIAL_EFX_CFG_OFF,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V32_ASF_SPECIAL_EFX_CFG_OFF,
cmdp_local, V32_ASF_SPECIAL_EFX_CFG_LEN);
break;
@@ -2238,20 +2283,22 @@
temp1 = *cmdp_local;
cmdp_local++;
- msm_io_memcpy(vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF1,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF1,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN1);
cmdp_local += 4;
- msm_io_memcpy(vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF2,
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF2,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN2);
cmdp_local += 3;
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*(cmdp_local + 1),
+ msm_camera_io_w(*(cmdp_local + 1),
vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2259,9 +2306,9 @@
CDBG("%s: start writing RollOff Ram1 table\n", __func__);
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2287,7 +2334,7 @@
temp1 = *cmdp_local;
cmdp_local += 8;
- temp2 = msm_io_r(vfe32_ctrl->vfebase +
+ temp2 = msm_camera_io_r(vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1)
& V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
@@ -2297,11 +2344,11 @@
else
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK1);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*(cmdp_local + 1),
+ msm_camera_io_w(*(cmdp_local + 1),
vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2313,9 +2360,9 @@
else
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK1);
- msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
+ msm_camera_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*cmdp_local,
+ msm_camera_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
cmdp_local += 2;
}
@@ -2336,7 +2383,7 @@
goto proc_general_done;
}
cmdp_local = cmdp;
- old_val = msm_io_r(vfe32_ctrl->vfebase +
+ old_val = msm_camera_io_r(vfe32_ctrl->vfebase +
V33_PCA_ROLL_OFF_CFG_OFF1) &
V33_PCA_ROLL_OFF_LUT_BANK_SEL_MASK;
@@ -2353,10 +2400,10 @@
else if (!old_val && temp2)
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
- *cmdp_local = msm_io_r(vfe32_ctrl->vfebase +
+ *cmdp_local = msm_camera_io_r(vfe32_ctrl->vfebase +
VFE33_DMI_DATA_LO);
*(cmdp_local + 1) =
- msm_io_r(vfe32_ctrl->vfebase +
+ msm_camera_io_r(vfe32_ctrl->vfebase +
VFE33_DMI_DATA_HI);
CDBG("%s: %08x%08x\n", __func__,
*(cmdp_local + 1), *cmdp_local);
@@ -2379,7 +2426,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- *cmdp = msm_io_r(vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
+ *cmdp = msm_camera_io_r(
+ vfe32_ctrl->vfebase+V32_GET_HW_VERSION_OFF);
if (copy_to_user((void __user *)(cmd->value), cmdp,
V32_GET_HW_VERSION_LEN)) {
rc = -EFAULT;
@@ -2397,7 +2445,8 @@
rc = -ENOMEM;
goto proc_general_done;
}
- msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
+ msm_camera_io_dump(
+ vfe32_ctrl->vfebase, vfe32_ctrl->register_total*4);
CDBG("%s: %p %p %d\n", __func__, (void *)cmdp,
vfe32_ctrl->vfebase, temp1);
memcpy_fromio((void *)cmdp, vfe32_ctrl->vfebase, temp1);
@@ -2416,8 +2465,16 @@
goto proc_general_done;
}
- CHECKED_COPY_FROM_USER(cmdp);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ if (copy_from_user((cmdp), (void __user *)cmd->value,
+ cmd->length)) {
+ rc = -EFAULT;
+ pr_err("%s copy from user failed for cmd %d",
+ __func__, cmd->id);
+ break;
+ }
+
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
vfe32_ctrl->frame_skip_cnt = ((uint32_t)
*cmdp & VFE_FRAME_SKIP_PERIOD_MASK) + 1;
@@ -2433,8 +2490,15 @@
goto proc_general_done;
}
- CHECKED_COPY_FROM_USER(cmdp);
- msm_io_memcpy(vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
+ if (copy_from_user((cmdp), (void __user *)cmd->value,
+ cmd->length)) {
+ rc = -EFAULT;
+ pr_err("%s copy from user failed for cmd %d",
+ __func__, cmd->id);
+ goto proc_general_done;
+ }
+ msm_camera_io_memcpy(
+ vfe32_ctrl->vfebase + vfe32_cmd[cmd->id].offset,
cmdp, (vfe32_cmd[cmd->id].length));
break;
@@ -2521,22 +2585,24 @@
uint32_t *temp;
memset(out, 0, sizeof(struct vfe32_irq_status));
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_IRQ_STATUS_0);
- out->vfeIrqStatus0 = msm_io_r(temp);
+ out->vfeIrqStatus0 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_IRQ_STATUS_1);
- out->vfeIrqStatus1 = msm_io_r(temp);
+ out->vfeIrqStatus1 = msm_camera_io_r(temp);
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
- out->camifStatus = msm_io_r(temp);
+ out->camifStatus = msm_camera_io_r(temp);
CDBG("camifStatus = 0x%x\n", out->camifStatus);
/* clear the pending interrupt of the same kind.*/
- msm_io_w(out->vfeIrqStatus0, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
- msm_io_w(out->vfeIrqStatus1, vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
+ msm_camera_io_w(out->vfeIrqStatus0,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_0);
+ msm_camera_io_w(out->vfeIrqStatus1,
+ vfe32_ctrl->vfebase + VFE_IRQ_CLEAR_1);
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_IRQ_CMD);
}
@@ -2547,33 +2613,33 @@
if (vfe32_ctrl->recording_state == VFE_STATE_START_REQUESTED) {
if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
vfe32_ctrl->recording_state = VFE_STATE_STARTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
CDBG("start video triggered .\n");
} else if (vfe32_ctrl->recording_state ==
VFE_STATE_STOP_REQUESTED) {
if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_VIDEO_AND_PREVIEW) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
} else if (vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_PREVIEW_AND_VIDEO) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
CDBG("stop video triggered .\n");
@@ -2589,7 +2655,7 @@
/* request a reg update and send STOP_REC_ACK
* when we process the next reg update irq.
*/
- msm_io_w_mb(1,
+ msm_camera_io_w_mb(1,
vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->recording_state ==
VFE_STATE_STOPPED) {
@@ -2612,9 +2678,9 @@
pr_info("%s enabling liveshot output\n", __func__);
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w(1, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
vfe32_ctrl->liveshot_state = VFE_STATE_STARTED;
}
@@ -2624,17 +2690,17 @@
vfe32_ctrl->vfe_capture_count--;
if (!vfe32_ctrl->vfe_capture_count)
vfe32_ctrl->liveshot_state = VFE_STATE_STOP_REQUESTED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED) {
CDBG("%s: disabling liveshot output\n", __func__);
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out0.ch1]);
vfe32_ctrl->liveshot_state = VFE_STATE_STOPPED;
- msm_io_w_mb(1, vfe32_ctrl->vfebase +
+ msm_camera_io_w_mb(1, vfe32_ctrl->vfebase +
VFE_REG_UPDATE_CMD);
}
} else if (vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED) {
@@ -2656,23 +2722,23 @@
/* stop the bus output:write master enable = 0*/
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_PRIMARY) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out0.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out0.ch1]);
}
if (vfe32_ctrl->outpath.output_mode &
VFE32_OUTPUT_MODE_SECONDARY) {
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out1.ch0]);
- msm_io_w(0, vfe32_ctrl->vfebase +
+ msm_camera_io_w(0, vfe32_ctrl->vfebase +
vfe32_AXI_WM_CFG[vfe32_ctrl->
outpath.out1.ch1]);
}
- msm_io_w_mb
+ msm_camera_io_w_mb
(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
vfe32_ctrl->snapshot_frame_cnt = -1;
@@ -2682,39 +2748,46 @@
} /*if frame is not being dropped*/
vfe32_ctrl->snapshot_frame_cnt++;
/* then do reg_update. */
- msm_io_w(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
+ msm_camera_io_w(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} /* if snapshot mode. */
}
static void vfe32_set_default_reg_values(void)
{
- msm_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_0);
- msm_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_1);
+ msm_camera_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_0);
+ msm_camera_io_w(0x800080, vfe32_ctrl->vfebase + VFE_DEMUX_GAIN_1);
/* What value should we program CGC_OVERRIDE to? */
- msm_io_w(0xFFFFF, vfe32_ctrl->vfebase + VFE_CGC_OVERRIDE);
+ msm_camera_io_w(0xFFFFF, vfe32_ctrl->vfebase + VFE_CGC_OVERRIDE);
/* default frame drop period and pattern */
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- msm_io_w(0xFFFFFFFF, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
+ msm_camera_io_w(0xFFFFFFFF,
+ vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
+ msm_camera_io_w(0xFFFFFFFF,
vfe32_ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
- msm_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y);
+ msm_camera_io_w(0x1f, vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR);
+ msm_camera_io_w(0xFFFFFFFF,
vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- msm_io_w(0xFFFFFFFF,
+ msm_camera_io_w(0xFFFFFFFF,
vfe32_ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- msm_io_w(0, vfe32_ctrl->vfebase + VFE_CLAMP_MIN);
- msm_io_w(0xFFFFFF, vfe32_ctrl->vfebase + VFE_CLAMP_MAX);
+ msm_camera_io_w(0, vfe32_ctrl->vfebase + VFE_CLAMP_MIN);
+ msm_camera_io_w(0xFFFFFF, vfe32_ctrl->vfebase + VFE_CLAMP_MAX);
/* stats UB config */
- msm_io_w(0x3980007, vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
- msm_io_w(0x3A00007, vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
- msm_io_w(0x3A8000F, vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
- msm_io_w(0x3B80007, vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
- msm_io_w(0x3C0001F, vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
- msm_io_w(0x3E0001F, vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
+ msm_camera_io_w(0x3980007,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AEC_UB_CFG);
+ msm_camera_io_w(0x3A00007,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AF_UB_CFG);
+ msm_camera_io_w(0x3A8000F,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_AWB_UB_CFG);
+ msm_camera_io_w(0x3B80007,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_RS_UB_CFG);
+ msm_camera_io_w(0x3C0001F,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_CS_UB_CFG);
+ msm_camera_io_w(0x3E0001F,
+ vfe32_ctrl->vfebase + VFE_BUS_STATS_HIST_UB_CFG);
}
static void vfe32_process_reset_irq(void)
@@ -2734,7 +2807,7 @@
vfe32_set_default_reg_values();
/* reload all write masters. (frame & line)*/
- msm_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
+ msm_camera_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_RESET_ACK);
}
}
@@ -2752,7 +2825,7 @@
if (vfe32_ctrl->vfe_capture_count == 0) {
/* Ensure the write order while writing
to the command register using the barrier */
- msm_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
+ msm_camera_io_w_mb(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
@@ -2781,7 +2854,8 @@
if (errStatus & VFE32_IMASK_CAMIF_ERROR) {
pr_err("vfe32_irq: camif errors\n");
- reg_value = msm_io_r(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
+ reg_value = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
pr_err("camifStatus = 0x%x\n", reg_value);
vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_CAMIF_ERROR);
}
@@ -2806,8 +2880,8 @@
if (errStatus & VFE32_IMASK_VIOLATION) {
pr_err("vfe32_irq: violation interrupt\n");
- reg_value =
- msm_io_r(vfe32_ctrl->vfebase + VFE_VIOLATION_STATUS);
+ reg_value = msm_camera_io_r(
+ vfe32_ctrl->vfebase + VFE_VIOLATION_STATUS);
pr_err("%s: violationStatus = 0x%x\n", __func__, reg_value);
}
@@ -2901,7 +2975,7 @@
(vfe32_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe32_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Channel 0*/
@@ -2977,7 +3051,7 @@
(vfe32_ctrl->vfe_capture_count <= 1)) || free_buf;
if (out_bool) {
- ping_pong = msm_io_r(vfe32_ctrl->vfebase +
+ ping_pong = msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS);
/* Y channel */
@@ -3033,7 +3107,7 @@
/* must be 0=ping, 1=pong */
pingpongStatus =
- ((msm_io_r(vfe32_ctrl->vfebase +
+ ((msm_camera_io_r(vfe32_ctrl->vfebase +
VFE_BUS_PING_PONG_STATUS))
& ((uint32_t)(1<<(statsNum + 7)))) >> (statsNum + 7);
/* stats bits starts at 7 */
@@ -3042,8 +3116,8 @@
((uint32_t)(vfe32_ctrl->vfebase +
VFE_BUS_STATS_PING_PONG_BASE)) +
(3*statsNum)*4 + (1-pingpongStatus)*4;
- returnAddr = msm_io_r((uint32_t *)pingpongAddr);
- msm_io_w(newAddr, (uint32_t *)pingpongAddr);
+ returnAddr = msm_camera_io_r((uint32_t *)pingpongAddr);
+ msm_camera_io_w(newAddr, (uint32_t *)pingpongAddr);
return returnAddr;
}
@@ -3131,7 +3205,7 @@
msgStats.rs.buff = vfe32_ctrl->rsStatsControl.bufToRender;
msgStats.cs.buff = vfe32_ctrl->csStatsControl.bufToRender;
- temp = msm_io_r(vfe32_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
+ temp = msm_camera_io_r(vfe32_ctrl->vfebase + VFE_STATS_AWB_SGW_CFG);
msgStats.awb_ymin = (0xFF00 & temp) >> 8;
v4l2_subdev_notify(&vfe32_ctrl->subdev,
@@ -3443,7 +3517,7 @@
if ((vfe32_ctrl->outpath.out0.capture_cnt == 0)
&& (vfe32_ctrl->outpath.out1.
capture_cnt == 0)) {
- msm_io_w_mb(
+ msm_camera_io_w_mb(
CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe32_ctrl->vfebase +
VFE_CAMIF_COMMAND);
@@ -3934,7 +4008,7 @@
msm_camio_bus_scale_cfg(
sync->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
- if (msm_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
+ if (msm_camera_io_r(vfe32_ctrl->vfebase + V32_GET_HW_VERSION_OFF) ==
VFE32_HW_NUMBER)
vfe32_ctrl->register_total = VFE32_REGISTER_TOTAL;
else
diff --git a/drivers/media/video/msm/msm_vpe.c b/drivers/media/video/msm/msm_vpe.c
index 5919553..8567fb3 100644
--- a/drivers/media/video/msm/msm_vpe.c
+++ b/drivers/media/video/msm/msm_vpe.c
@@ -48,14 +48,14 @@
static int vpe_start(void)
{
/* enable the frame irq, bit 0 = Display list 0 ROI done */
- msm_io_w_mb(1, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
- msm_io_dump(vpe_ctrl->vpebase, 0x120);
- msm_io_dump(vpe_ctrl->vpebase + 0x10000, 0x250);
- msm_io_dump(vpe_ctrl->vpebase + 0x30000, 0x20);
- msm_io_dump(vpe_ctrl->vpebase + 0x50000, 0x30);
- msm_io_dump(vpe_ctrl->vpebase + 0x50400, 0x10);
+ msm_camera_io_w_mb(1, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_dump(vpe_ctrl->vpebase, 0x120);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x10000, 0x250);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x30000, 0x20);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x50000, 0x30);
+ msm_camera_io_dump(vpe_ctrl->vpebase + 0x50400, 0x10);
/* this triggers the operation. */
- msm_io_w(1, vpe_ctrl->vpebase + VPE_DL0_START_OFFSET);
+ msm_camera_io_w(1, vpe_ctrl->vpebase + VPE_DL0_START_OFFSET);
wmb();
return 0;
}
@@ -69,15 +69,15 @@
static void vpe_config_axi_default(void)
{
- msm_io_w(0x25, vpe_ctrl->vpebase + VPE_AXI_ARB_2_OFFSET);
+ msm_camera_io_w(0x25, vpe_ctrl->vpebase + VPE_AXI_ARB_2_OFFSET);
CDBG("%s: yaddr %ld cbcraddr %ld", __func__,
vpe_ctrl->out_y_addr, vpe_ctrl->out_cbcr_addr);
if (!vpe_ctrl->out_y_addr || !vpe_ctrl->out_cbcr_addr)
return;
- msm_io_w(vpe_ctrl->out_y_addr,
+ msm_camera_io_w(vpe_ctrl->out_y_addr,
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
- msm_io_w(vpe_ctrl->out_cbcr_addr,
+ msm_camera_io_w(vpe_ctrl->out_cbcr_addr,
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
}
@@ -88,32 +88,33 @@
uint32_t rc = 0;
vpe_reset_state_variables();
- vpe_version = msm_io_r(vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
+ vpe_version = msm_camera_io_r(
+ vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
- msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
- msm_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
+ msm_camera_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
- msm_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
+ msm_camera_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
rc =
- msm_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
+ msm_camera_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
- msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
+ msm_camera_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_ctrl->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
- msm_io_w(VPE_CGC_ENABLE_VALUE,
+ msm_camera_io_w(VPE_CGC_ENABLE_VALUE,
vpe_ctrl->vpebase + VPE_CGC_EN_OFFSET);
- msm_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
+ msm_camera_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
+ msm_camera_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
+ msm_camera_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_ctrl->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return rc;
@@ -124,7 +125,7 @@
uint32_t rot_flag, rc = 0;
struct msm_pp_crop *pcrop = (struct msm_pp_crop *)pinfo;
- rot_flag = msm_io_r(vpe_ctrl->vpebase +
+ rot_flag = msm_camera_io_r(vpe_ctrl->vpebase +
VPE_OP_MODE_OFFSET) & 0xE00;
if (pinfo != NULL) {
CDBG("%s: Crop info in2_w = %d, in2_h = %d "
@@ -144,36 +145,40 @@
uint32_t i, offset;
offset = *p;
for (i = offset; i < (VPE_SCALE_COEFF_NUM + offset); i++) {
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SCALE_COEFF_LSBn(i));
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SCALE_COEFF_MSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_SCALE_COEFF_LSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_SCALE_COEFF_MSBn(i));
}
}
void vpe_input_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_ctrl->vpebase + VPE_SRC_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(*p, vpe_ctrl->vpebase + VPE_SRC_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_SRC_XY_OFFSET);
}
void vpe_output_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_ctrl->vpebase + VPE_OUT_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_XY_OFFSET);
+ msm_camera_io_w(*p, vpe_ctrl->vpebase + VPE_OUT_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_ctrl->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
+ msm_camera_io_w(*(++p), vpe_ctrl->vpebase + VPE_OUT_XY_OFFSET);
}
static int vpe_operation_config(uint32_t *p)
{
uint32_t w, h, temp;
- msm_io_w(*p, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(*p, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
- temp = msm_io_r(vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
+ temp = msm_camera_io_r(vpe_ctrl->vpebase + VPE_OUT_SIZE_OFFSET);
w = temp & 0xFFF;
h = (temp & 0xFFF0000) >> 16;
if (*p++ & 0xE00) {
@@ -215,8 +220,8 @@
/* assumption is both direction need zoom. this can be
improved. */
temp =
- msm_io_r(vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
- msm_io_w(temp, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_r(vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
+ msm_camera_io_w(temp, vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
src_ROI_width = pcrop->src_w;
src_ROI_height = pcrop->src_h;
@@ -228,7 +233,7 @@
out_ROI_height);
src_roi = (src_ROI_height << 16) + src_ROI_width;
- msm_io_w(src_roi, vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(src_roi, vpe_ctrl->vpebase + VPE_SRC_SIZE_OFFSET);
src_x = pcrop->src_x;
src_y = pcrop->src_y;
@@ -236,7 +241,7 @@
CDBG("src_x = %d, src_y=%d.\n", src_x, src_y);
src_xy = src_y*(1<<16) + src_x;
- msm_io_w(src_xy, vpe_ctrl->vpebase +
+ msm_camera_io_w(src_xy, vpe_ctrl->vpebase +
VPE_SRC_XY_OFFSET);
CDBG("src_xy = %d, src_roi=%d.\n", src_xy, src_roi);
@@ -376,15 +381,15 @@
CDBG("phase init x = %d, init y = %d.\n",
phase_init_x, phase_init_y);
- msm_io_w(phase_step_x, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_step_x, vpe_ctrl->vpebase +
VPE_SCALE_PHASEX_STEP_OFFSET);
- msm_io_w(phase_step_y, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_step_y, vpe_ctrl->vpebase +
VPE_SCALE_PHASEY_STEP_OFFSET);
- msm_io_w(phase_init_x, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_init_x, vpe_ctrl->vpebase +
VPE_SCALE_PHASEX_INIT_OFFSET);
- msm_io_w(phase_init_y, vpe_ctrl->vpebase +
+ msm_camera_io_w(phase_init_y, vpe_ctrl->vpebase +
VPE_SCALE_PHASEY_INIT_OFFSET);
return 1;
@@ -406,16 +411,16 @@
unsigned long flags;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
- msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_SRCP0_ADDR_OFFSET);
- msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_SRCP1_ADDR_OFFSET);
- msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
- msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
+ msm_camera_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
vpe_ctrl->state = VPE_STATE_ACTIVE;
@@ -457,11 +462,11 @@
static irqreturn_t vpe_parse_irq(int irq_num, void *data)
{
- vpe_ctrl->irq_status = msm_io_r_mb(vpe_ctrl->vpebase +
+ vpe_ctrl->irq_status = msm_camera_io_r_mb(vpe_ctrl->vpebase +
VPE_INTR_STATUS_OFFSET);
- msm_io_w_mb(vpe_ctrl->irq_status, vpe_ctrl->vpebase +
+ msm_camera_io_w_mb(vpe_ctrl->irq_status, vpe_ctrl->vpebase +
VPE_INTR_CLEAR_OFFSET);
- msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
CDBG("%s: vpe_parse_irq =0x%x.\n", __func__, vpe_ctrl->irq_status);
tasklet_schedule(&vpe_tasklet);
return IRQ_HANDLED;
diff --git a/drivers/media/video/msm/msm_vpe1.c b/drivers/media/video/msm/msm_vpe1.c
index 5f128e1..96988a9 100644
--- a/drivers/media/video/msm/msm_vpe1.c
+++ b/drivers/media/video/msm/msm_vpe1.c
@@ -97,10 +97,10 @@
static int vpe_start(void)
{
/* enable the frame irq, bit 0 = Display list 0 ROI done */
- msm_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
- msm_io_dump(vpe_device->vpebase + 0x10000, 0x250);
+ msm_camera_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_dump(vpe_device->vpebase + 0x10000, 0x250);
/* this triggers the operation. */
- msm_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET);
+ msm_camera_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET);
return 0;
}
@@ -117,7 +117,7 @@
static void vpe_config_axi_default(void)
{
- msm_io_w(0x25, vpe_device->vpebase + VPE_AXI_ARB_2_OFFSET);
+ msm_camera_io_w(0x25, vpe_device->vpebase + VPE_AXI_ARB_2_OFFSET);
CDBG("%s: yaddr %ld cbcraddr %ld", __func__,
vpe_ctrl->out_y_addr, vpe_ctrl->out_cbcr_addr);
@@ -125,10 +125,10 @@
if (!vpe_ctrl->out_y_addr || !vpe_ctrl->out_cbcr_addr)
return;
- msm_io_w(vpe_ctrl->out_y_addr,
+ msm_camera_io_w(vpe_ctrl->out_y_addr,
vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
- msm_io_w(vpe_ctrl->out_cbcr_addr,
+ msm_camera_io_w(vpe_ctrl->out_cbcr_addr,
vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
}
@@ -139,39 +139,40 @@
uint32_t rc;
vpe_reset_state_variables();
- vpe_version = msm_io_r(vpe_device->vpebase + VPE_HW_VERSION_OFFSET);
+ vpe_version = msm_camera_io_r(
+ vpe_device->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
- msm_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
- msm_io_w(0x1fffff, vpe_device->vpebase + VPE_INTR_CLEAR_OFFSET);
+ msm_camera_io_w(0x1fffff, vpe_device->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
- msm_io_w(0x10, vpe_device->vpebase + VPE_SW_RESET_OFFSET);
+ msm_camera_io_w(0x10, vpe_device->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
- rc =
- msm_io_r(vpe_device->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
+ rc = msm_camera_io_r(vpe_device->vpebase + VPE_SW_RESET_OFFSET)
+ & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
- msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
+ msm_camera_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_device->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
- msm_io_w(VPE_CGC_ENABLE_VALUE,
+ msm_camera_io_w(VPE_CGC_ENABLE_VALUE,
vpe_device->vpebase + VPE_CGC_EN_OFFSET);
- msm_io_w(1, vpe_device->vpebase + VPE_CMD_MODE_OFFSET);
+ msm_camera_io_w(1, vpe_device->vpebase + VPE_CMD_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
+ msm_camera_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_device->vpebase + VPE_OP_MODE_OFFSET);
- msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
+ msm_camera_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_device->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
@@ -183,7 +184,7 @@
uint32_t rot_flag, rc = 0;
struct video_crop_t *pcrop = (struct video_crop_t *)pinfo;
- rot_flag = msm_io_r(vpe_device->vpebase +
+ rot_flag = msm_camera_io_r(vpe_device->vpebase +
VPE_OP_MODE_OFFSET) & 0xE00;
if (pinfo != NULL) {
CDBG("Crop info in2_w = %d, in2_h = %d "
@@ -203,38 +204,51 @@
uint32_t i, offset;
offset = *p;
for (i = offset; i < (VPE_SCALE_COEFF_NUM + offset); i++) {
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SCALE_COEFF_LSBn(i));
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SCALE_COEFF_MSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SCALE_COEFF_LSBn(i));
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SCALE_COEFF_MSBn(i));
}
}
void vpe_input_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_device->vpebase + VPE_SRC_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(*p,
+ vpe_device->vpebase + VPE_SRC_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_UNPACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_IMAGE_SIZE_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
vpe_ctrl->in_h_w = *p;
- msm_io_w(*(++p), vpe_device->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_SRC_XY_OFFSET);
}
void vpe_output_plane_config(uint32_t *p)
{
- msm_io_w(*p, vpe_device->vpebase + VPE_OUT_FORMAT_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
- msm_io_w(*(++p), vpe_device->vpebase + VPE_OUT_XY_OFFSET);
+ msm_camera_io_w(*p,
+ vpe_device->vpebase + VPE_OUT_FORMAT_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_PACK_PATTERN1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_YSTRIDE1_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
+ msm_camera_io_w(*(++p),
+ vpe_device->vpebase + VPE_OUT_XY_OFFSET);
vpe_ctrl->pcbcr_dis_offset = *(++p);
}
static int vpe_operation_config(uint32_t *p)
{
uint32_t outw, outh, temp;
- msm_io_w(*p, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(*p, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
- temp = msm_io_r(vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OUT_SIZE_OFFSET);
outw = temp & 0xFFF;
outh = (temp & 0xFFF0000) >> 16;
@@ -278,15 +292,15 @@
(pcrop->in2_h >= pcrop->out2_h)) {
CDBG(" =======VPE no zoom needed.\n");
- temp = msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
& 0xfffffffc;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
- msm_io_w(0, vpe_device->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(0, vpe_device->vpebase + VPE_SRC_XY_OFFSET);
- CDBG("vpe_ctrl->in_h_w = %d \n", vpe_ctrl->in_h_w);
- msm_io_w(vpe_ctrl->in_h_w , vpe_device->vpebase +
+ CDBG("vpe_ctrl->in_h_w = %d\n", vpe_ctrl->in_h_w);
+ msm_camera_io_w(vpe_ctrl->in_h_w , vpe_device->vpebase +
VPE_SRC_SIZE_OFFSET);
return rc;
@@ -297,8 +311,8 @@
/* assumption is both direction need zoom. this can be
improved. */
temp =
- msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET) | 0x3;
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
src_ROI_width = pcrop->in2_w;
src_ROI_height = pcrop->in2_h;
@@ -310,7 +324,7 @@
out_ROI_height);
src_roi = (src_ROI_height << 16) + src_ROI_width;
- msm_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
src_x = (out_ROI_width - src_ROI_width)/2;
src_y = (out_ROI_height - src_ROI_height)/2;
@@ -318,7 +332,7 @@
CDBG("src_x = %d, src_y=%d.\n", src_x, src_y);
src_xy = src_y*(1<<16) + src_x;
- msm_io_w(src_xy, vpe_device->vpebase +
+ msm_camera_io_w(src_xy, vpe_device->vpebase +
VPE_SRC_XY_OFFSET);
CDBG("src_xy = %d, src_roi=%d.\n", src_xy, src_roi);
@@ -458,15 +472,15 @@
CDBG("phase init x = %d, init y = %d.\n",
phase_init_x, phase_init_y);
- msm_io_w(phase_step_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_STEP_OFFSET);
- msm_io_w(phase_step_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_STEP_OFFSET);
- msm_io_w(phase_init_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_INIT_OFFSET);
- msm_io_w(phase_init_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_INIT_OFFSET);
return 1;
@@ -502,21 +516,22 @@
if ((pcrop->in2_w >= pcrop->out2_w) &&
(pcrop->in2_h >= pcrop->out2_h)) {
- CDBG(" =======VPE no zoom needed, DIS is still enabled. \n");
+ CDBG(" =======VPE no zoom needed, DIS is still enabled.\n");
- temp = msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
& 0xfffffffc;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
/* no zoom, use dis offset directly. */
src_xy = dis_offset->dis_offset_y * (1<<16) +
dis_offset->dis_offset_x;
- msm_io_w(src_xy, vpe_device->vpebase + VPE_SRC_XY_OFFSET);
+ msm_camera_io_w(src_xy,
+ vpe_device->vpebase + VPE_SRC_XY_OFFSET);
- CDBG("vpe_ctrl->in_h_w = 0x%x \n", vpe_ctrl->in_h_w);
- msm_io_w(vpe_ctrl->in_h_w, vpe_device->vpebase +
- VPE_SRC_SIZE_OFFSET);
+ CDBG("vpe_ctrl->in_h_w = 0x%x\n", vpe_ctrl->in_h_w);
+ msm_camera_io_w(vpe_ctrl->in_h_w,
+ vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
return rc;
}
/* If fall through then scaler is needed.*/
@@ -524,9 +539,9 @@
CDBG("========VPE zoom needed + DIS enabled.\n");
/* assumption is both direction need zoom. this can be
improved. */
- temp = msm_io_r(vpe_device->vpebase +
+ temp = msm_camera_io_r(vpe_device->vpebase +
VPE_OP_MODE_OFFSET) | 0x3;
- msm_io_w(temp, vpe_device->vpebase +
+ msm_camera_io_w(temp, vpe_device->vpebase +
VPE_OP_MODE_OFFSET);
zoom_dis_x = dis_offset->dis_offset_x *
pcrop->in2_w / pcrop->out2_w;
@@ -554,12 +569,12 @@
src_roi = (src_ROI_height << 16) + src_ROI_width;
- msm_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
+ msm_camera_io_w(src_roi, vpe_device->vpebase + VPE_SRC_SIZE_OFFSET);
CDBG("src_x = %d, src_y=%d.\n", src_x, src_y);
src_xy = src_y*(1<<16) + src_x;
- msm_io_w(src_xy, vpe_device->vpebase +
+ msm_camera_io_w(src_xy, vpe_device->vpebase +
VPE_SRC_XY_OFFSET);
CDBG("src_xy = 0x%x, src_roi=0x%x.\n", src_xy, src_roi);
@@ -694,16 +709,16 @@
CDBG("phase init x = %d, init y = %d.\n",
phase_init_x, phase_init_y);
- msm_io_w(phase_step_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_STEP_OFFSET);
- msm_io_w(phase_step_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_step_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_STEP_OFFSET);
- msm_io_w(phase_init_x, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_x, vpe_device->vpebase +
VPE_SCALE_PHASEX_INIT_OFFSET);
- msm_io_w(phase_init_y, vpe_device->vpebase +
+ msm_camera_io_w(phase_init_y, vpe_device->vpebase +
VPE_SCALE_PHASEY_INIT_OFFSET);
return 1;
@@ -716,8 +731,10 @@
CDBG("vpe input, p0_phy_add = 0x%x, p1_phy_add = 0x%x\n",
p0_phy_add, p1_phy_add);
- msm_io_w(p0_phy_add, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
- msm_io_w(p1_phy_add, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
+ msm_camera_io_w(p0_phy_add,
+ vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
+ msm_camera_io_w(p1_phy_add,
+ vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == VPE_STATE_ACTIVE)
CDBG(" =====VPE is busy!!! Wrong!========\n");
@@ -726,25 +743,27 @@
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
- vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->pcbcr_before_dis =
+ msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
- temp_pyaddr = msm_io_r(vpe_device->vpebase +
+ temp_pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + PAD_TO_2K(vpe_ctrl->out_w *
vpe_ctrl->out_h * 2, vpe_ctrl->pad_2k_bool);
- msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
+ msm_camera_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
- vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->pcbcr_before_dis =
+ msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
- temp_pyaddr = msm_io_r(vpe_device->vpebase +
+ temp_pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
- msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
+ msm_camera_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
@@ -988,10 +1007,10 @@
regp1 = &(ad->region[0]);
/* for video Y address */
p1 = (regp1->paddr + regp1->info.planar0_off);
- msm_io_w(p1, vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
+ msm_camera_io_w(p1, vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
p1 = (regp1->paddr + regp1->info.planar1_off);
- msm_io_w(p1, vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
+ msm_camera_io_w(p1, vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
return 0;
}
@@ -1051,7 +1070,8 @@
input_stride = (st_half.buf_p1_stride * (1<<16)) +
st_half.buf_p0_stride;
- msm_io_w(input_stride, vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
+ msm_camera_io_w(input_stride,
+ vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
vpe_update_scaler_with_dis(&(vpe_buf.vpe_crop),
&(vpe_ctrl->dis_offset));
@@ -1118,34 +1138,34 @@
CDBG("vpe left frame done.\n");
vpe_ctrl->output_type = 0;
CDBG("vpe send out msg.\n");
- orig_src_y = msm_io_r(vpe_device->vpebase +
+ orig_src_y = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP0_ADDR_OFFSET);
- orig_src_cbcr = msm_io_r(vpe_device->vpebase +
+ orig_src_cbcr = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP1_ADDR_OFFSET);
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- pcbcraddr = msm_io_r(vpe_device->vpebase +
+ pcbcraddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
CDBG("%s: out_w = %d, out_h = %d\n", __func__,
vpe_ctrl->out_w, vpe_ctrl->out_h);
if ((vpe_ctrl->frame_pack == TOP_DOWN_FULL) ||
(vpe_ctrl->frame_pack == TOP_DOWN_HALF)) {
- msm_io_w(pyaddr + (vpe_ctrl->out_w *
+ msm_camera_io_w(pyaddr + (vpe_ctrl->out_w *
vpe_ctrl->out_h), vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- msm_io_w(pcbcraddr + (vpe_ctrl->out_w *
+ msm_camera_io_w(pcbcraddr + (vpe_ctrl->out_w *
vpe_ctrl->out_h/2),
vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
} else if ((vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_HALF) || (vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_FULL)) {
- msm_io_w(pyaddr + vpe_ctrl->out_w,
+ msm_camera_io_w(pyaddr + vpe_ctrl->out_w,
vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- msm_io_w(pcbcraddr + vpe_ctrl->out_w,
+ msm_camera_io_w(pcbcraddr + vpe_ctrl->out_w,
vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
} else
@@ -1164,13 +1184,13 @@
if ((vpe_ctrl->frame_pack == TOP_DOWN_FULL) ||
(vpe_ctrl->frame_pack == TOP_DOWN_HALF)) {
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET) -
(vpe_ctrl->out_w * vpe_ctrl->out_h);
} else if ((vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_HALF) || (vpe_ctrl->frame_pack ==
SIDE_BY_SIDE_FULL)) {
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET) - vpe_ctrl->out_w;
} else
CDBG("%s: Invalid packing = %d\n", __func__,
@@ -1178,27 +1198,27 @@
pcbcraddr = vpe_ctrl->pcbcr_before_dis;
} else {
- src_y = msm_io_r(vpe_device->vpebase +
+ src_y = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP0_ADDR_OFFSET);
- src_cbcr = msm_io_r(vpe_device->vpebase +
+ src_cbcr = msm_camera_io_r(vpe_device->vpebase +
VPE_SRCP1_ADDR_OFFSET);
- pyaddr = msm_io_r(vpe_device->vpebase +
+ pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- pcbcraddr = msm_io_r(vpe_device->vpebase +
+ pcbcraddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en)
pcbcraddr = vpe_ctrl->pcbcr_before_dis;
- msm_io_w(src_y,
+ msm_camera_io_w(src_y,
vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
- msm_io_w(src_cbcr,
+ msm_camera_io_w(src_cbcr,
vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
- temp = msm_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET) &
- 0xFFFFFFFC;
- msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
+ temp = msm_camera_io_r(vpe_device->vpebase + VPE_OP_MODE_OFFSET)
+ & 0xFFFFFFFC;
+ msm_camera_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
/* now pass this frame to msm_camera.c. */
if (vpe_ctrl->output_type == OUTPUT_TYPE_ST_R) {
@@ -1227,12 +1247,12 @@
CDBG("vpe_parse_irq.\n");
/* read and clear back-to-back. */
- irq_status = msm_io_r_mb(vpe_device->vpebase +
+ irq_status = msm_camera_io_r_mb(vpe_device->vpebase +
VPE_INTR_STATUS_OFFSET);
- msm_io_w_mb(irq_status, vpe_device->vpebase +
+ msm_camera_io_w_mb(irq_status, vpe_device->vpebase +
VPE_INTR_CLEAR_OFFSET);
- msm_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
+ msm_camera_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
if (irq_status == 0) {
pr_err("%s: irq_status = 0,Something is wrong!\n", __func__);
@@ -1343,9 +1363,9 @@
}
vpe_ctrl->state = VPE_STATE_IDLE;
spin_unlock_irqrestore(&vpe_ctrl->ops_lock, flags);
- vpe_ctrl->out_y_addr = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->out_y_addr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
- vpe_ctrl->out_cbcr_addr = msm_io_r(vpe_device->vpebase +
+ vpe_ctrl->out_cbcr_addr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
free_irq(vpe_device->vpeirq, 0);
tasklet_kill(&vpe_tasklet);
diff --git a/drivers/media/video/msm/sensors/mt9e013_v4l2.c b/drivers/media/video/msm/sensors/mt9e013_v4l2.c
index e6e2d52..7f0fbc3 100644
--- a/drivers/media/video/msm/sensors/mt9e013_v4l2.c
+++ b/drivers/media/video/msm/sensors/mt9e013_v4l2.c
@@ -271,6 +271,8 @@
ARRAY_SIZE(mt9e013_prev_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
{&mt9e013_hfr60_settings[0],
ARRAY_SIZE(mt9e013_hfr60_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
+ {&mt9e013_hfr60_settings[0],
+ ARRAY_SIZE(mt9e013_hfr60_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
{&mt9e013_hfr90_settings[0],
ARRAY_SIZE(mt9e013_hfr90_settings), 0, MSM_CAMERA_I2C_WORD_DATA},
{&mt9e013_hfr120_settings[0],
@@ -310,6 +312,15 @@
.y_output = 0x212,
.line_length_pclk = 0x970,
.frame_length_lines = 0x2A1,
+ .vt_pixel_clk = 98400000,
+ .op_pixel_clk = 98400000,
+ .binning_factor = 1,
+ },
+ {
+ .x_output = 0x340,
+ .y_output = 0x212,
+ .line_length_pclk = 0x970,
+ .frame_length_lines = 0x2A1,
.vt_pixel_clk = 146400000,
.op_pixel_clk = 146400000,
.binning_factor = 1,
@@ -339,6 +350,7 @@
&mt9e013_csi_params,
&mt9e013_csi_params,
&mt9e013_csi_params,
+ &mt9e013_csi_params,
};
static struct msm_sensor_output_reg_addr_t mt9e013_reg_addr = {
diff --git a/drivers/media/video/vcap_v4l2.c b/drivers/media/video/vcap_v4l2.c
new file mode 100644
index 0000000..6443250
--- /dev/null
+++ b/drivers/media/video/vcap_v4l2.c
@@ -0,0 +1,908 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <linux/memory_alloc.h>
+
+#include <mach/msm_subsystem_map.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+#include <media/videobuf2-msm-mem.h>
+
+#include <media/videobuf2-vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-common.h>
+#include <linux/regulator/consumer.h>
+#include <mach/clk.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <mach/msm_bus.h>
+#include <mach/msm_bus_board.h>
+
+#include <media/vcap_v4l2.h>
+#include <media/vcap_fmt.h>
+#include "vcap_vc.h"
+
+#define NUM_INPUTS 1
+#define MSM_VCAP_DRV_NAME "msm_vcap"
+
+static struct vcap_dev *vcap_ctrl;
+
+static unsigned debug;
+
+#define dprintk(level, fmt, arg...) \
+ do { \
+ if (debug >= level) \
+ printk(KERN_DEBUG "VCAP: " fmt, ## arg); \
+ } while (0)
+
+int get_phys_addr(struct vcap_dev *dev, struct vb2_queue *q,
+ struct v4l2_buffer *b)
+{
+ struct vb2_buffer *vb;
+ struct vcap_buffer *buf;
+ unsigned long len, offset;
+ int rc;
+
+ if (q->fileio) {
+ dprintk(1, "%s: file io in progress\n", __func__);
+ return -EBUSY;
+ }
+
+ if (b->type != q->type) {
+ dprintk(1, "%s: invalid buffer type\n", __func__);
+ return -EINVAL;
+ }
+
+ if (b->index >= q->num_buffers) {
+ dprintk(1, "%s: buffer index out of range\n", __func__);
+ return -EINVAL;
+ }
+
+ vb = q->bufs[b->index];
+ if (NULL == vb) {
+ dprintk(1, "%s: buffer is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if (vb->state != VB2_BUF_STATE_DEQUEUED) {
+ dprintk(1, "%s: buffer already in use\n", __func__);
+ return -EINVAL;
+ }
+
+ buf = container_of(vb, struct vcap_buffer, vb);
+
+ buf->ion_handle = ion_import_fd(dev->ion_client, b->m.userptr);
+ if (IS_ERR((void *)buf->ion_handle)) {
+ pr_err("%s: Could not alloc memory\n", __func__);
+ buf->ion_handle = NULL;
+ return -ENOMEM;
+ }
+ rc = ion_phys(dev->ion_client, buf->ion_handle,
+ &buf->paddr, (size_t *)&len);
+ if (rc < 0) {
+ pr_err("%s: Could not get phys addr\n", __func__);
+ return -EFAULT;
+ }
+
+ offset = b->reserved;
+ buf->paddr += offset;
+ return 0;
+}
+
+void free_ion_handle_work(struct vcap_dev *dev, struct vb2_buffer *vb)
+{
+ struct vcap_buffer *buf;
+
+ buf = container_of(vb, struct vcap_buffer, vb);
+ if (buf->ion_handle == NULL) {
+ dprintk(1, "%s: no ION handle to free\n", __func__);
+ return;
+ }
+ buf->paddr = 0;
+ ion_free(dev->ion_client, buf->ion_handle);
+ buf->ion_handle = NULL;
+ return;
+}
+
+int free_ion_handle(struct vcap_dev *dev, struct vb2_queue *q,
+ struct v4l2_buffer *b)
+{
+ struct vb2_buffer *vb;
+
+ if (q->fileio)
+ return -EBUSY;
+
+ if (b->type != q->type)
+ return -EINVAL;
+
+ if (b->index >= q->num_buffers)
+ return -EINVAL;
+
+ vb = q->bufs[b->index];
+ if (NULL == vb)
+ return -EINVAL;
+
+ free_ion_handle_work(dev, vb);
+ return 0;
+}
+
+/* Videobuf operations */
+
+static int capture_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
+ unsigned int *nplanes, unsigned long sizes[],
+ void *alloc_ctxs[])
+{
+ *nbuffers = 3;
+ *nplanes = 1;
+ return 0;
+}
+
+static int capture_buffer_init(struct vb2_buffer *vb)
+{
+ return 0;
+}
+
+static int capture_buffer_prepare(struct vb2_buffer *vb)
+{
+ return 0;
+}
+
+static void capture_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(vb->vb2_queue);
+ struct vcap_buffer *buf = container_of(vb, struct vcap_buffer, vb);
+ struct vcap_action *vid_vc_action = &c_data->vid_vc_action;
+ struct vb2_queue *q = vb->vb2_queue;
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(&c_data->cap_slock, flags);
+ list_add_tail(&buf->list, &vid_vc_action->active);
+ spin_unlock_irqrestore(&c_data->cap_slock, flags);
+
+ if (atomic_read(&c_data->dev->vc_enabled) == 0) {
+
+ if (atomic_read(&q->queued_count) > 1)
+ if (vc_hw_kick_off(c_data) == 0)
+ atomic_set(&c_data->dev->vc_enabled, 1);
+ }
+}
+
+static int capture_start_streaming(struct vb2_queue *vq)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(vq);
+ dprintk(2, "VC start streaming\n");
+ return vc_start_capture(c_data);
+}
+
+static int capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(vq);
+ struct vb2_buffer *vb;
+
+ vc_stop_capture(c_data);
+
+ while (!list_empty(&c_data->vid_vc_action.active)) {
+ struct vcap_buffer *buf;
+ buf = list_entry(c_data->vid_vc_action.active.next,
+ struct vcap_buffer, list);
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+ }
+
+ /* clean ion handles */
+ list_for_each_entry(vb, &vq->queued_list, queued_entry)
+ free_ion_handle_work(c_data->dev, vb);
+ return 0;
+}
+
+static int capture_buffer_finish(struct vb2_buffer *vb)
+{
+ return 0;
+}
+
+static void capture_buffer_cleanup(struct vb2_buffer *vb)
+{
+}
+
+static struct vb2_ops capture_video_qops = {
+ .queue_setup = capture_queue_setup,
+ .buf_init = capture_buffer_init,
+ .buf_prepare = capture_buffer_prepare,
+ .buf_queue = capture_buffer_queue,
+ .start_streaming = capture_start_streaming,
+ .stop_streaming = capture_stop_streaming,
+ .buf_finish = capture_buffer_finish,
+ .buf_cleanup = capture_buffer_cleanup,
+};
+
+/* IOCTL vidioc handling */
+
+static int vidioc_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ struct vcap_dev *dev = video_drvdata(file);
+
+ strlcpy(cap->driver, MSM_VCAP_DRV_NAME, sizeof(cap->driver));
+ strlcpy(cap->card, MSM_VCAP_DRV_NAME, sizeof(cap->card));
+ strlcpy(cap->bus_info, dev->v4l2_dev.name, sizeof(cap->bus_info));
+ cap->version = 0x10000000;
+ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
+ return 0;
+}
+
+static int vidioc_enum_input(struct file *file, void *priv,
+ struct v4l2_input *inp)
+{
+ if (inp->index >= NUM_INPUTS)
+ return -EINVAL;
+ return 0;
+}
+
+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ return 0;
+}
+
+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ return 0;
+}
+
+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ int size;
+#ifdef NEW_S_FMT
+ struct v4l2_format_vc_ext *vc_format;
+#endif
+ struct vcap_client_data *c_data = file->private_data;
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+#ifdef NEW_S_FMT
+ vc_format = (struct v4l2_format_vc_ext *) f->fmt.raw_data;
+ c_data->vc_format = *vc_format;
+#else
+ c_data->vc_format =
+ vcap_vc_lut[f->fmt.pix.priv];
+#endif
+
+ config_vc_format(c_data);
+
+ size = (c_data->vc_format.hactive_end -
+ c_data->vc_format.hactive_start);
+
+ if (c_data->vc_format.color_space)
+ size *= 3;
+ else
+ size *= 2;
+
+#ifndef NEW_S_FMT
+ f->fmt.pix.bytesperline = size;
+ size *= (c_data->vc_format.vactive_end -
+ c_data->vc_format.vactive_start);
+ f->fmt.pix.sizeimage = size;
+#endif
+ vcap_ctrl->vc_client = c_data;
+ break;
+ case V4L2_BUF_TYPE_INTERLACED_IN_DECODER:
+ c_data->vp_buf_type_field = V4L2_BUF_TYPE_INTERLACED_IN_DECODER;
+ c_data->vp_format.field = f->fmt.pix.field;
+ c_data->vp_format.height = f->fmt.pix.height;
+ c_data->vp_format.width = f->fmt.pix.width;
+ c_data->vp_format.pixelformat = f->fmt.pix.pixelformat;
+ break;
+ case V4L2_BUF_TYPE_INTERLACED_IN_AFE:
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int vidioc_reqbufs(struct file *file, void *priv,
+ struct v4l2_requestbuffers *rb)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ switch (rb->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return vb2_reqbufs(&c_data->vc_vidq, rb);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+ struct vcap_client_data *c_data = file->private_data;
+
+ switch (p->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return vb2_querybuf(&c_data->vc_vidq, p);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ int rc;
+
+ switch (p->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ if (get_phys_addr(c_data->dev, &c_data->vc_vidq, p))
+ return -EINVAL;
+ rc = vb2_qbuf(&c_data->vc_vidq, p);
+ if (rc < 0)
+ free_ion_handle(c_data->dev, &c_data->vc_vidq, p);
+ return rc;
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ int rc;
+
+ switch (p->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ rc = vb2_dqbuf(&c_data->vc_vidq, p, file->f_flags & O_NONBLOCK);
+ if (rc < 0)
+ return rc;
+ return free_ion_handle(c_data->dev, &c_data->vc_vidq, p);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+ struct vcap_client_data *c_data = file->private_data;
+
+ switch (i) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return vb2_streamon(&c_data->vc_vidq, i);
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ int rc;
+
+ switch (i) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ rc = vb2_streamoff(&c_data->vc_vidq, i);
+ if (rc >= 0)
+ atomic_set(&c_data->dev->vc_enabled, 0);
+ return rc;
+ default:
+ pr_err("VCAP Error: %s: Unknown buffer type", __func__);
+ break;
+ }
+ return 0;
+}
+
+/* VCAP fops */
+
+static void *vcap_ops_get_userptr(void *alloc_ctx, unsigned long vaddr,
+ unsigned long size, int write)
+{
+ struct vcap_buf_info *mem;
+ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+ if (!mem)
+ return ERR_PTR(-ENOMEM);
+ mem->vaddr = vaddr;
+ mem->size = size;
+ return mem;
+}
+
+static void vcap_ops_put_userptr(void *buf_priv)
+{
+ kfree(buf_priv);
+}
+
+const struct vb2_mem_ops vcap_mem_ops = {
+ .get_userptr = vcap_ops_get_userptr,
+ .put_userptr = vcap_ops_put_userptr,
+};
+
+static int vcap_open(struct file *file)
+{
+ struct vcap_dev *dev = video_drvdata(file);
+ struct vcap_client_data *c_data;
+ struct vb2_queue *q;
+ int ret;
+ c_data = kzalloc(sizeof(*c_data), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ c_data->dev = dev;
+
+ spin_lock_init(&c_data->cap_slock);
+
+ /* initialize queue */
+ q = &c_data->vc_vidq;
+ memset(q, 0, sizeof(c_data->vc_vidq));
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ q->io_modes = VB2_USERPTR;
+ q->drv_priv = c_data;
+ q->buf_struct_size = sizeof(struct vcap_buffer);
+ q->ops = &capture_video_qops;
+ q->mem_ops = &vcap_mem_ops;
+
+ ret = vb2_queue_init(q);
+ if (ret < 0)
+ goto open_failed;
+
+ INIT_LIST_HEAD(&c_data->vid_vc_action.active);
+ file->private_data = c_data;
+
+ return 0;
+
+open_failed:
+ kfree(c_data);
+ return ret;
+}
+
+static int vcap_close(struct file *file)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ vb2_queue_release(&c_data->vc_vidq);
+ c_data->dev->vc_client = NULL;
+ c_data->dev->vp_client = NULL;
+ kfree(c_data);
+ return 0;
+}
+
+static unsigned int vcap_poll(struct file *file,
+ struct poll_table_struct *wait)
+{
+ struct vcap_client_data *c_data = file->private_data;
+ struct vb2_queue *q = &c_data->vc_vidq;
+
+ return vb2_poll(q, file, wait);
+}
+/* V4L2 and video device structures */
+
+static const struct v4l2_file_operations vcap_fops = {
+ .owner = THIS_MODULE,
+ .open = vcap_open,
+ .release = vcap_close,
+ .poll = vcap_poll,
+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
+};
+
+static const struct v4l2_ioctl_ops vcap_ioctl_ops = {
+ .vidioc_querycap = vidioc_querycap,
+ .vidioc_enum_input = vidioc_enum_input,
+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
+ .vidioc_reqbufs = vidioc_reqbufs,
+ .vidioc_querybuf = vidioc_querybuf,
+ .vidioc_qbuf = vidioc_qbuf,
+ .vidioc_dqbuf = vidioc_dqbuf,
+ .vidioc_streamon = vidioc_streamon,
+ .vidioc_streamoff = vidioc_streamoff,
+};
+
+static struct video_device vcap_template = {
+ .name = "vcap",
+ .fops = &vcap_fops,
+ .ioctl_ops = &vcap_ioctl_ops,
+ .release = video_device_release,
+};
+
+int vcap_reg_powerup(struct vcap_dev *dev)
+{
+ dev->fs_vcap = regulator_get(NULL, "fs_vcap");
+ if (IS_ERR(dev->fs_vcap)) {
+ pr_err("%s: Regulator FS_VCAP get failed %ld\n", __func__,
+ PTR_ERR(dev->fs_vcap));
+ dev->fs_vcap = NULL;
+ return -EINVAL;
+ } else if (regulator_enable(dev->fs_vcap)) {
+ pr_err("%s: Regulator FS_VCAP enable failed\n", __func__);
+ regulator_put(dev->fs_vcap);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void vcap_reg_powerdown(struct vcap_dev *dev)
+{
+ if (dev->fs_vcap == NULL)
+ return;
+ regulator_disable(dev->fs_vcap);
+ regulator_put(dev->fs_vcap);
+ dev->fs_vcap = NULL;
+ return;
+}
+
+int config_gpios(int on, struct vcap_platform_data *pdata)
+{
+ int i, ret;
+ int num_gpios = pdata->num_gpios;
+ unsigned *gpios = pdata->gpios;
+
+ if (on) {
+ for (i = 0; i < num_gpios; i++) {
+ ret = gpio_request(gpios[i], "vcap:vc");
+ if (ret) {
+ pr_err("VCAP: failed at GPIO %d to request\n",
+ gpios[i]);
+ goto gpio_failed;
+ }
+ ret = gpio_direction_input(gpios[i]);
+ if (ret) {
+ pr_err("VCAP: failed at GPIO %d to set to input\n",
+ gpios[i]);
+ i++;
+ goto gpio_failed;
+ }
+ }
+ } else {
+ for (i = 0; i < num_gpios; i++)
+ gpio_free(gpios[i]);
+ }
+ dprintk(2, "GPIO config done\n");
+ return 0;
+gpio_failed:
+ for (i--; i >= 0; i--)
+ gpio_free(gpios[i]);
+ return -EINVAL;
+}
+
+int vcap_clk_powerup(struct vcap_dev *dev, struct device *ddev)
+{
+ int ret = 0;
+
+ dev->vcap_clk = clk_get(ddev, "core_clk");
+ if (IS_ERR(dev->vcap_clk)) {
+ dev->vcap_clk = NULL;
+ pr_err("%s: Could not clk_get core_clk\n", __func__);
+ clk_put(dev->vcap_clk);
+ dev->vcap_clk = NULL;
+ return -EINVAL;
+ }
+
+ clk_prepare(dev->vcap_clk);
+ ret = clk_enable(dev->vcap_clk);
+ if (ret) {
+ pr_err("%s: Failed core clk_enable %d\n", __func__, ret);
+ goto fail_vcap_clk_unprep;
+ }
+
+ clk_set_rate(dev->vcap_clk, 160000000);
+ if (ret) {
+ pr_err("%s: Failed core set_rate %d\n", __func__, ret);
+ goto fail_vcap_clk;
+ }
+
+ dev->vcap_npl_clk = clk_get(ddev, "vcap_npl_clk");
+ if (IS_ERR(dev->vcap_npl_clk)) {
+ dev->vcap_npl_clk = NULL;
+ pr_err("%s: Could not clk_get npl\n", __func__);
+ clk_put(dev->vcap_npl_clk);
+ dev->vcap_npl_clk = NULL;
+ goto fail_vcap_clk;
+ }
+
+ clk_prepare(dev->vcap_npl_clk);
+ ret = clk_enable(dev->vcap_npl_clk);
+ if (ret) {
+ pr_err("%s:Failed npl clk_enable %d\n", __func__, ret);
+ goto fail_vcap_npl_clk_unprep;
+ }
+
+ dev->vcap_p_clk = clk_get(ddev, "iface_clk");
+ if (IS_ERR(dev->vcap_p_clk)) {
+ dev->vcap_p_clk = NULL;
+ pr_err("%s: Could not clk_get pix(AHB)\n", __func__);
+ clk_put(dev->vcap_p_clk);
+ dev->vcap_p_clk = NULL;
+ goto fail_vcap_npl_clk;
+ }
+
+ clk_prepare(dev->vcap_p_clk);
+ ret = clk_enable(dev->vcap_p_clk);
+ if (ret) {
+ pr_err("%s: Failed pix(AHB) clk_enable %d\n", __func__, ret);
+ goto fail_vcap_p_clk_unprep;
+ }
+ return 0;
+
+fail_vcap_p_clk_unprep:
+ clk_unprepare(dev->vcap_p_clk);
+ clk_put(dev->vcap_p_clk);
+ dev->vcap_p_clk = NULL;
+
+fail_vcap_npl_clk:
+ clk_disable(dev->vcap_npl_clk);
+fail_vcap_npl_clk_unprep:
+ clk_unprepare(dev->vcap_npl_clk);
+ clk_put(dev->vcap_npl_clk);
+ dev->vcap_npl_clk = NULL;
+
+fail_vcap_clk:
+ clk_disable(dev->vcap_clk);
+fail_vcap_clk_unprep:
+ clk_unprepare(dev->vcap_clk);
+ clk_put(dev->vcap_clk);
+ dev->vcap_clk = NULL;
+ return -EINVAL;
+}
+
+void vcap_clk_powerdown(struct vcap_dev *dev)
+{
+ if (dev->vcap_p_clk != NULL) {
+ clk_disable(dev->vcap_p_clk);
+ clk_unprepare(dev->vcap_p_clk);
+ clk_put(dev->vcap_p_clk);
+ dev->vcap_p_clk = NULL;
+ }
+
+ if (dev->vcap_npl_clk != NULL) {
+ clk_disable(dev->vcap_npl_clk);
+ clk_unprepare(dev->vcap_npl_clk);
+ clk_put(dev->vcap_npl_clk);
+ dev->vcap_npl_clk = NULL;
+ }
+
+ if (dev->vcap_clk != NULL) {
+ clk_disable(dev->vcap_clk);
+ clk_unprepare(dev->vcap_clk);
+ clk_put(dev->vcap_clk);
+ dev->vcap_clk = NULL;
+ }
+}
+
+int vcap_get_bus_client_handle(struct vcap_dev *dev)
+{
+ struct msm_bus_scale_pdata *vcap_axi_client_pdata =
+ dev->vcap_pdata->bus_client_pdata;
+ dev->bus_client_handle =
+ msm_bus_scale_register_client(vcap_axi_client_pdata);
+
+ return 0;
+}
+
+int vcap_enable(struct vcap_dev *dev, struct device *ddev)
+{
+ int rc;
+
+ rc = vcap_reg_powerup(dev);
+ if (rc < 0)
+ goto reg_failed;
+ rc = vcap_clk_powerup(dev, ddev);
+ if (rc < 0)
+ goto clk_failed;
+ rc = vcap_get_bus_client_handle(dev);
+ if (rc < 0)
+ goto bus_r_failed;
+ config_gpios(1, dev->vcap_pdata);
+ if (rc < 0)
+ goto gpio_failed;
+ return 0;
+
+gpio_failed:
+ msm_bus_scale_unregister_client(dev->bus_client_handle);
+ dev->bus_client_handle = 0;
+bus_r_failed:
+ vcap_clk_powerdown(dev);
+clk_failed:
+ vcap_reg_powerdown(dev);
+reg_failed:
+ return rc;
+}
+
+int vcap_disable(struct vcap_dev *dev)
+{
+ config_gpios(0, dev->vcap_pdata);
+
+ msm_bus_scale_unregister_client(dev->bus_client_handle);
+ dev->bus_client_handle = 0;
+ vcap_clk_powerdown(dev);
+ vcap_reg_powerdown(dev);
+ return 0;
+}
+
+static irqreturn_t vcap_vc_handler(int irq_num, void *data)
+{
+ return vc_handler(vcap_ctrl);
+}
+
+static int __devinit vcap_probe(struct platform_device *pdev)
+{
+ struct vcap_dev *dev;
+ struct video_device *vfd;
+ int ret;
+
+ dprintk(1, "Probe started\n");
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+ vcap_ctrl = dev;
+ dev->vcap_pdata = pdev->dev.platform_data;
+
+ dev->vcapmem = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "vcap");
+ if (!dev->vcapmem) {
+ pr_err("VCAP: %s: no mem resource?\n", __func__);
+ ret = -ENODEV;
+ goto free_dev;
+ }
+
+ dev->vcapio = request_mem_region(dev->vcapmem->start,
+ resource_size(dev->vcapmem), pdev->name);
+ if (!dev->vcapio) {
+ pr_err("VCAP: %s: no valid mem region\n", __func__);
+ ret = -EBUSY;
+ goto free_dev;
+ }
+
+ dev->vcapbase = ioremap(dev->vcapmem->start,
+ resource_size(dev->vcapmem));
+ if (!dev->vcapbase) {
+ ret = -ENOMEM;
+ pr_err("VCAP: %s: vcap ioremap failed\n", __func__);
+ goto free_resource;
+ }
+
+ dev->vcapirq = platform_get_resource_byname(pdev,
+ IORESOURCE_IRQ, "vcap");
+ if (!dev->vcapirq) {
+ pr_err("%s: no irq resource?\n", __func__);
+ ret = -ENODEV;
+ goto free_resource;
+ }
+
+ ret = request_irq(dev->vcapirq->start, vcap_vc_handler,
+ IRQF_TRIGGER_RISING, "vcap", 0);
+ if (ret < 0) {
+ pr_err("%s: irq request fail\n", __func__);
+ ret = -EBUSY;
+ goto free_resource;
+ }
+
+ disable_irq(dev->vcapirq->start);
+
+ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
+ "%s", MSM_VCAP_DRV_NAME);
+ ret = v4l2_device_register(NULL, &dev->v4l2_dev);
+ if (ret)
+ goto free_resource;
+
+ ret = vcap_enable(dev, &pdev->dev);
+ if (ret)
+ goto unreg_dev;
+ msm_bus_scale_client_update_request(dev->bus_client_handle, 3);
+
+ ret = detect_vc(dev);
+
+ if (ret)
+ goto power_down;
+
+ /* init video device*/
+ vfd = video_device_alloc();
+ if (!vfd)
+ goto deinit_vc;
+
+ *vfd = vcap_template;
+ vfd->v4l2_dev = &dev->v4l2_dev;
+
+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+ if (ret < 0)
+ goto rel_vdev;
+
+ dev->vfd = vfd;
+ video_set_drvdata(vfd, dev);
+
+ dev->ion_client = msm_ion_client_create(-1, "vcap");
+ if (IS_ERR((void *)dev->ion_client)) {
+ pr_err("could not get ion client");
+ goto rel_vdev;
+ }
+
+ atomic_set(&dev->vc_enabled, 0);
+
+ dprintk(1, "Exit probe succesfully");
+ return 0;
+
+rel_vdev:
+ video_device_release(vfd);
+deinit_vc:
+ deinit_vc();
+power_down:
+ vcap_disable(dev);
+unreg_dev:
+ v4l2_device_unregister(&dev->v4l2_dev);
+free_resource:
+ iounmap(dev->vcapbase);
+ release_mem_region(dev->vcapmem->start, resource_size(dev->vcapmem));
+free_dev:
+ vcap_ctrl = NULL;
+ kfree(dev);
+ return ret;
+}
+
+static int __devexit vcap_remove(struct platform_device *pdev)
+{
+ struct vcap_dev *dev = vcap_ctrl;
+ ion_client_destroy(dev->ion_client);
+ video_device_release(dev->vfd);
+ deinit_vc();
+ vcap_disable(dev);
+ v4l2_device_unregister(&dev->v4l2_dev);
+ iounmap(dev->vcapbase);
+ release_mem_region(dev->vcapmem->start, resource_size(dev->vcapmem));
+ vcap_ctrl = NULL;
+ kfree(dev);
+
+ return 0;
+}
+
+struct platform_driver vcap_platform_driver = {
+ .driver = {
+ .name = MSM_VCAP_DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+ .probe = vcap_probe,
+ .remove = vcap_remove,
+};
+
+static int __init vcap_init_module(void)
+{
+ return platform_driver_register(&vcap_platform_driver);
+}
+
+static void __exit vcap_exit_module(void)
+{
+ platform_driver_unregister(&vcap_platform_driver);
+}
+
+module_init(vcap_init_module);
+module_exit(vcap_exit_module);
+MODULE_DESCRIPTION("VCAP driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/vcap_vc.c b/drivers/media/video/vcap_vc.c
new file mode 100644
index 0000000..ed0bc25
--- /dev/null
+++ b/drivers/media/video/vcap_vc.c
@@ -0,0 +1,715 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kthread.h>
+#include <linux/freezer.h>
+#include <mach/camera.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <mach/clk.h>
+#include <linux/clk.h>
+
+#include <media/vcap_v4l2.h>
+#include <media/vcap_fmt.h>
+#include "vcap_vc.h"
+
+static unsigned debug;
+
+#define dprintk(level, fmt, arg...) \
+ do { \
+ if (debug >= level) \
+ printk(KERN_DEBUG "VC: " fmt, ## arg); \
+ } while (0)
+
+struct v4l2_format_vc_ext vcap_vc_lut[] = {
+ /* 1080p */
+ {
+ HAL_VCAP_YUV_1080p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 32, 2200, 192, 2112, 4, 24, 0, 2, 0, 44, 0, 0, 0, 0,
+ 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 1125, 2200, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_1080p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 148.5,
+ 1125, 2200, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_24_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2750, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_24_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 112, 2750, 192, 2112, 4, 110, 0, 2, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_24_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 275, 19, 211, 41, 1121, 0, 5, 0, 16, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_60_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 1125, 200, 22, 182, 41, 1121, 0, 5, 0, 16, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 1125, 2640, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_50_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 148.5,
+ 15, 2640, 192, 2112, 6, 13, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_25_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2640, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0,
+ 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_25_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 10, 2640, 192, 2112, 4, 8, 0, 2, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1080p_30_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2200, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_1080p_25_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 74.25,
+ 1125, 2640, 192, 2112, 41, 1121, 0, 5, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_1080p_25_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 74.25,
+ 10, 2640, 192, 2112, 4, 8, 0, 2, 0, 44, 0, 0, 0,
+ 0, 0, 0
+ },
+ /* 1080i */
+ {
+ HAL_VCAP_YUV_1080i_60_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 2200, 192, 2112, 20, 560, 0, 5, 0, 44, 583, 1123, 1100,
+ 1100, 563, 568
+ },
+ {
+ HAL_VCAP_YUV_1080i_60_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 18, 2200, 192, 2112, 3, 7, 0, 2, 0, 44, 11, 15, 1100,
+ 1100, 8, 10
+ },
+ {
+ HAL_VCAP_YUV_1080i_60_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 1125, 220, 19, 211, 20, 560, 0, 5, 0, 4, 583, 1123, 110,
+ 110, 563, 568
+ },
+ {
+ HAL_VCAP_YUV_1080i_50_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 72.00,
+ 1125, 2640, 192, 2112, 20, 560, 0, 5, 0, 44, 583, 1123, 1320,
+ 1320, 563, 568
+ },
+ {
+ HAL_VCAP_YUV_1080i_50_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 72.00,
+ 52, 2640, 192, 2112, 4, 24, 0, 2, 0, 44, 30, 50, 1320,
+ 1320, 26, 28},
+ {
+ HAL_VCAP_YUV_1080i_50_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 72.00,
+ 1125, 264, 19, 211, 20, 560, 0, 5, 0, 4, 583, 1123, 110,
+ 110, 563, 568
+ },
+ {
+ HAL_VCAP_RGB_1080i_50_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 72.00,
+ 1125, 2640, 192, 2112, 20, 560, 0, 5, 0, 44, 583, 1123, 1320,
+ 1320, 563, 568
+ },
+ {
+ HAL_VCAP_RGB_1080i_50_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 72.00,
+ 52, 2640, 192, 2112, 4, 24, 0, 2, 0, 44, 30, 50, 1320,
+ 1320, 26, 28
+ },
+ /* 480i */
+ {
+ HAL_VCAP_YUV_480i_60_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 20, 1716, 238, 1678, 3, 7, 0, 2, 0, 124, 14, 18, 820,
+ 820, 10, 12
+ },
+ {
+ HAL_VCAP_YUV_480i_60_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 1716, 238, 1678, 18, 258, 0, 3, 0, 124, 281, 521, 858,
+ 858, 262, 265
+ },
+ {
+ HAL_VCAP_YUV_480i_60_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 172, 24, 168, 18, 258, 0, 3, 0, 12, 281, 521, 86,
+ 86, 262, 265
+ },
+ {
+ HAL_VCAP_YUV_2880_480i_60_FL, HAL_VCAP_MODE_INT,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 54.000, 525, 3432, 476, 3356, 18, 258, 0, 3,
+ 0, 248, 281, 521, 1716, 1716, 262, 265
+ },
+ {
+ HAL_VCAP_YUV_2880_480i_60_RH, HAL_VCAP_MODE_INT,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 54.000, 32, 3432, 476, 3356, 4, 14, 0, 3, 0,
+ 248, 20, 30, 1716, 1716, 16, 19
+ },
+ /* 480p */
+ {
+ HAL_VCAP_YUV_480p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 8, 858, 122, 842, 2, 5, 0, 1, 0, 62, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_480p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 27.027,
+ 52, 858, 122, 842, 3, 50, 0, 2, 0, 62, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_480p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 27.027,
+ 525, 858, 122, 842, 36, 516, 0, 6, 0, 62, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_480p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 858, 122, 842, 36, 516, 0, 6, 0, 62, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_480p_60_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.027,
+ 525, 86, 12, 84, 36, 516, 0, 6, 0, 6, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_480p_60_FL, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 525, 3432, 488, 3368, 36, 516, 0, 6,
+ 0, 248, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_480p_60_RH, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 25, 3432, 488, 3368, 8, 22, 0, 6, 0,
+ 248, 0, 0, 0, 0, 0, 0
+ },
+ /* 720p */
+ {
+ HAL_VCAP_YUV_720p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 1650, 260, 1540, 25, 745, 0, 5, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_720p_60_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 74.25,
+ 750, 1650, 260, 1540, 25, 745, 0, 5, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_60_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 165, 26, 154, 25, 745, 0, 5, 0, 4, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_60_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 35, 1650, 260, 1540, 5, 32, 0, 3, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 1980, 260, 1540, 25, 745, 0, 5, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_50_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 750, 198, 26, 154, 25, 745, 0, 5, 0, 4, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_720p_50_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 74.25,
+ 6, 1980, 260, 1540, 2, 5, 0, 1, 0, 40, 0, 0, 0,
+ 0, 0, 0
+ },
+ /* 576p */
+ {
+ HAL_VCAP_YUV_576p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 864, 132, 852, 44, 620, 0, 5, 0, 64, 0, 0, 0,
+ 0, 0, 0},
+ {
+ HAL_VCAP_RGB_576p_50_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 27.0,
+ 625, 864, 132, 852, 44, 620, 0, 5, 0, 64, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_576p_50_RW, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 86, 13, 85, 44, 620, 0, 5, 0, 6, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_576p_50_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 25, 864, 132, 852, 4, 23, 0, 3, 0, 64, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_1440_576p_50_RH, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 54.000, 25, 1728, 264, 1704, 6, 23, 0, 5, 0,
+ 128, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_576p_50_FL, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 625, 3456, 528, 3408, 44, 620, 0, 5,
+ 0, 256, 0, 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_2880_576p_50_RH, HAL_VCAP_MODE_PRO,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_YUV, 108.000, 25, 3456, 528, 3408, 6, 23, 0, 5, 0,
+ 256, 0, 0, 0, 0, 0, 0
+ },
+ /* 576i */
+ {
+ HAL_VCAP_YUV_576i_50_FL, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 1728, 264, 1704, 22, 310, 0, 3, 0, 126, 335, 623, 864,
+ 864, 313, 316
+ },
+ {
+ HAL_VCAP_YUV_576i_50_RW, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 625, 172, 26, 170, 22, 310, 0, 3, 0, 13, 335, 623, 86,
+ 86, 313, 316
+ },
+ {
+ HAL_VCAP_YUV_576i_50_RH, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_NEG, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 27.0,
+ 29, 1728, 264, 1704, 3, 13, 0, 1, 0, 126, 16, 26, 864, 864,
+ 14, 15
+ },
+ /* XGA 1024x768 */
+ {
+ HAL_VCAP_YUV_XGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 63.5,
+ 798, 1328, 256, 1280, 27, 795, 0, 4, 0, 104, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_XGA_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 63.5,
+ 12, 1328, 256, 1280, 6, 10, 0, 4, 0, 104, 0, 0, 0, 0,
+ 0, 0
+ },
+ {
+ HAL_VCAP_YUV_XGA_RB, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 63.5,
+ 12, 1216, 112, 1136, 6, 10, 0, 4, 0, 32, 0, 0, 0, 0,
+ 0, 0
+ },
+ /* SXGA 1280x1024 */
+ {
+ HAL_VCAP_YUV_SXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 109.0,
+ 1063, 1712, 352, 1632, 36, 1060, 0, 7, 0, 136, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_SXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 109.0,
+ 1063, 1712, 352, 1632, 36, 1060, 0, 7, 0, 136, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_SXGA_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 109.0,
+ 17, 1712, 352, 1632, 8, 15, 0, 7, 0, 136, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_SXGA_RB, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 109.0,
+ 17, 1440, 112, 1392, 8, 15, 0, 7, 0, 32, 0, 0, 0, 0,
+ 0, 0
+ },
+ /* UXGA 1600x1200 */
+ {
+ HAL_VCAP_YUV_UXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 161.0,
+ 1245, 2160, 448, 2048, 42, 1242, 0, 4, 0, 168, 0,
+ 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_RGB_UXGA_FL, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_RGB, 161.0,
+ 1245, 2160, 448, 2048, 42, 1242, 0, 4, 0, 168, 0,
+ 0, 0, 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_UXGA_RH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 161.0,
+ 12, 2160, 448, 2048, 6, 10, 0, 4, 0, 168, 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ HAL_VCAP_YUV_UXGA_RB, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_NEG,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_POS, HAL_VCAP_YUV, 161.0,
+ 12, 1808, 112, 1712, 6, 10, 0, 4, 0, 32, 0, 0, 0, 0,
+ 0, 0
+ },
+ /* test odd height */
+ {
+ HAL_VCAP_ODD_HEIGHT, HAL_VCAP_MODE_INT, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_NEG, HAL_VCAP_YUV, 148.5,
+ 65, 1728, 264, 1704, 5, 20, 0, 3, 0, 126, 25, 40, 864,
+ 864, 21, 24
+ },
+ /* test odd width RGB only */
+ {
+ HAL_VCAP_ODD_WIDTH, HAL_VCAP_MODE_PRO, HAL_VCAP_POLAR_POS,
+ HAL_VCAP_POLAR_POS, HAL_VCAP_POLAR_NEG, HAL_VCAP_RGB, 148.5,
+ 52, 859, 122, 843, 3, 50, 0, 2, 0, 62, 0, 0, 0, 0, 0, 0
+ },
+};
+
+void config_buffer(struct vcap_client_data *c_data,
+ struct vcap_buffer *buf,
+ void __iomem *y_addr,
+ void __iomem *c_addr)
+{
+ if (c_data->vc_format.color_space == HAL_VCAP_RGB) {
+ writel_relaxed(buf->paddr, y_addr);
+ } else {
+ int size = ((c_data->vc_format.hactive_end -
+ c_data->vc_format.hactive_start) *
+ (c_data->vc_format.vactive_end -
+ c_data->vc_format.vactive_start));
+ writel_relaxed(buf->paddr, y_addr);
+ writel_relaxed(buf->paddr + size, c_addr);
+ }
+}
+
+irqreturn_t vc_handler(struct vcap_dev *dev)
+{
+ uint32_t irq, timestamp;
+ enum rdy_buf vc_buf_status, buf_ind;
+ struct vcap_buffer *buf;
+ struct vb2_buffer *vb = NULL;
+ struct vcap_client_data *c_data;
+
+ irq = readl_relaxed(VCAP_VC_INT_STATUS);
+
+ dprintk(1, "%s: irq=0x%08x\n", __func__, irq);
+
+ vc_buf_status = irq & VC_BUFFER_WRITTEN;
+
+ dprintk(1, "Done buf status = %d\n", vc_buf_status);
+
+ if (vc_buf_status == VC_NO_BUF) {
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ pr_err("VC IRQ shows some error\n");
+ return IRQ_HANDLED;
+ }
+
+ if (dev->vc_client == NULL) {
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ pr_err("VC: There is no active vc client\n");
+ return IRQ_HANDLED;
+ }
+ c_data = dev->vc_client;
+
+ spin_lock(&dev->vc_client->cap_slock);
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ /* Just leave we have no new queued buffers */
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ spin_unlock(&dev->vc_client->cap_slock);
+ dprintk(1, "We have no more avilable buffers\n");
+ return IRQ_HANDLED;
+ }
+ spin_unlock(&dev->vc_client->cap_slock);
+
+ timestamp = readl_relaxed(VCAP_VC_TIMESTAMP);
+
+ buf_ind = dev->vc_client->vid_vc_action.buf_ind;
+
+ if (vc_buf_status == VC_BUF1N2) {
+ /* There are 2 buffer ready */
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ return IRQ_HANDLED;
+ } else if (buf_ind != vc_buf_status) {
+ /* buffer is out of sync */
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ return IRQ_HANDLED;
+ }
+
+ if (buf_ind == VC_BUF1) {
+ dprintk(1, "Got BUF1\n");
+ vb = &dev->vc_client->vid_vc_action.buf1->vb;
+ spin_lock(&dev->vc_client->cap_slock);
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ spin_unlock(&dev->vc_client->cap_slock);
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ return IRQ_HANDLED;
+ }
+ buf = list_entry(dev->vc_client->vid_vc_action.active.next,
+ struct vcap_buffer, list);
+ list_del(&buf->list);
+ spin_unlock(&dev->vc_client->cap_slock);
+ /* Config vc with this new buffer */
+ config_buffer(c_data, buf, VCAP_VC_Y_ADDR_1,
+ VCAP_VC_C_ADDR_1);
+
+ vb->v4l2_buf.timestamp.tv_usec = timestamp;
+ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+ dev->vc_client->vid_vc_action.buf1 = buf;
+ dev->vc_client->vid_vc_action.buf_ind = VC_BUF2;
+ irq = VC_BUF1;
+ } else {
+ dprintk(1, "Got BUF2\n");
+ spin_lock(&dev->vc_client->cap_slock);
+ vb = &dev->vc_client->vid_vc_action.buf2->vb;
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+ spin_unlock(&dev->vc_client->cap_slock);
+ return IRQ_HANDLED;
+ }
+ buf = list_entry(dev->vc_client->vid_vc_action.active.next,
+ struct vcap_buffer, list);
+ list_del(&buf->list);
+ spin_unlock(&dev->vc_client->cap_slock);
+ /* Config vc with this new buffer */
+ config_buffer(c_data, buf, VCAP_VC_Y_ADDR_2,
+ VCAP_VC_C_ADDR_2);
+
+ vb->v4l2_buf.timestamp.tv_usec = timestamp;
+ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+
+ dev->vc_client->vid_vc_action.buf2 = buf;
+ dev->vc_client->vid_vc_action.buf_ind = VC_BUF1;
+ irq = VC_BUF2;
+ }
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+
+ return IRQ_HANDLED;
+}
+
+int vc_start_capture(struct vcap_client_data *c_data)
+{
+ return 0;
+}
+
+int vc_hw_kick_off(struct vcap_client_data *c_data)
+{
+ struct vcap_action *vid_vc_action = &c_data->vid_vc_action;
+ struct vcap_dev *dev;
+ unsigned long flags = 0;
+ int rc, counter = 0;
+ struct vcap_buffer *buf;
+
+ dev = c_data->dev;
+ vid_vc_action->buf_ind = VC_BUF1;
+ dprintk(2, "Start Kickoff\n");
+
+ if (dev->vc_client == NULL) {
+ pr_err("No active vc client\n");
+ return -ENODEV;
+ }
+ spin_lock_irqsave(&dev->vc_client->cap_slock, flags);
+ if (list_empty(&dev->vc_client->vid_vc_action.active)) {
+ spin_unlock_irqrestore(&dev->vc_client->cap_slock, flags);
+ pr_err("%s: VC We have no more avilable buffers\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ list_for_each_entry(buf, &vid_vc_action->active, list)
+ counter++;
+
+ if (counter < 2) {
+ /* not enough buffers have been queued */
+ spin_unlock_irqrestore(&dev->vc_client->cap_slock, flags);
+ return -EINVAL;
+ }
+
+ vid_vc_action->buf1 = list_entry(vid_vc_action->active.next,
+ struct vcap_buffer, list);
+ list_del(&vid_vc_action->buf1->list);
+
+ vid_vc_action->buf2 = list_entry(vid_vc_action->active.next,
+ struct vcap_buffer, list);
+ list_del(&vid_vc_action->buf2->list);
+
+ spin_unlock_irqrestore(&dev->vc_client->cap_slock, flags);
+
+ config_buffer(c_data, vid_vc_action->buf1, VCAP_VC_Y_ADDR_1,
+ VCAP_VC_C_ADDR_1);
+ config_buffer(c_data, vid_vc_action->buf2, VCAP_VC_Y_ADDR_2,
+ VCAP_VC_C_ADDR_2);
+
+ rc = readl_relaxed(VCAP_VC_CTRL);
+ writel_relaxed(rc | 0x1, VCAP_VC_CTRL);
+
+ writel_relaxed(0x6, VCAP_VC_INT_MASK);
+
+ enable_irq(dev->vcapirq->start);
+ return 0;
+}
+
+void vc_stop_capture(struct vcap_client_data *c_data)
+{
+ struct vcap_dev *dev = c_data->dev;
+ int rc;
+
+ rc = readl_relaxed(VCAP_VC_CTRL);
+ writel_relaxed(rc & ~(0x1), VCAP_VC_CTRL);
+
+ disable_irq(c_data->dev->vcapirq->start);
+}
+
+int config_vc_format(struct vcap_client_data *c_data)
+{
+ struct vcap_dev *dev;
+ unsigned int rc;
+ int timeout;
+ struct v4l2_format_vc_ext *vc_format = &c_data->vc_format;
+ dev = c_data->dev;
+
+ /* restart VC */
+ writel_relaxed(0x00000001, VCAP_SW_RESET_REQ);
+ timeout = 10000;
+ while (1) {
+ rc = (readl_relaxed(VCAP_SW_RESET_STATUS) & 0x1);
+ if (!rc)
+ break;
+ timeout--;
+ if (timeout == 0) {
+ pr_err("VC is not resetting properly\n");
+ return -EINVAL;
+ }
+ }
+ writel_relaxed(0x00000000, VCAP_SW_RESET_REQ);
+
+ writel_relaxed(0x00000102, VCAP_VC_NPL_CTRL);
+ rc = readl_relaxed(VCAP_VC_NPL_CTRL);
+ rc = readl_relaxed(VCAP_VC_NPL_CTRL);
+ writel_relaxed(0x00000002, VCAP_VC_NPL_CTRL);
+
+ dprintk(2, "%s: Starting VC configuration\n", __func__);
+ writel_relaxed(0x00000002, VCAP_VC_NPL_CTRL);
+ writel_relaxed(0x00000004 | vc_format->color_space << 1, VCAP_VC_CTRL);
+
+ writel_relaxed(vc_format->h_polar << 4 |
+ vc_format->v_polar << 0, VCAP_VC_POLARITY);
+
+ writel_relaxed(vc_format->h_polar << 4 |
+ vc_format->v_polar << 0, VCAP_VC_POLARITY);
+ writel_relaxed(((vc_format->htotal << 16) | vc_format->vtotal),
+ VCAP_VC_V_H_TOTAL);
+ writel_relaxed(((vc_format->hactive_end << 16) |
+ vc_format->hactive_start), VCAP_VC_H_ACTIVE);
+
+ writel_relaxed(((vc_format->vactive_end << 16) |
+ vc_format->vactive_start), VCAP_VC_V_ACTIVE);
+ writel_relaxed(((vc_format->f2_vactive_end << 16) |
+ vc_format->f2_vactive_start), VCAP_VC_V_ACTIVE_F2);
+ writel_relaxed(((vc_format->vsync_end << 16) | vc_format->vsync_start),
+ VCAP_VC_VSYNC_VPOS);
+ writel_relaxed(((vc_format->f2_vsync_v_end << 16) |
+ vc_format->f2_vsync_v_start), VCAP_VC_VSYNC_F2_VPOS);
+ writel_relaxed(((vc_format->hsync_end << 16) |
+ vc_format->hsync_start), VCAP_VC_HSYNC_HPOS);
+ writel_relaxed(((vc_format->f2_vsync_h_end << 16) |
+ vc_format->f2_vsync_h_start), VCAP_VC_VSYNC_F2_HPOS);
+ writel_relaxed(0x000033FF, VCAP_VC_BUF_CTRL);
+
+ rc = vc_format->hactive_end - vc_format->hactive_start;
+ if (vc_format->color_space)
+ rc *= 3;
+
+ writel_relaxed(rc, VCAP_VC_Y_STRIDE);
+ writel_relaxed(rc, VCAP_VC_C_STRIDE);
+
+ writel_relaxed(0x00010033 , VCAP_OFFSET(0x0898));
+ writel_relaxed(0x00010fff , VCAP_OFFSET(0x089c));
+ writel_relaxed(0x0a418820, VCAP_VC_IN_CTRL1);
+ writel_relaxed(0x16a4a0e6, VCAP_VC_IN_CTRL2);
+ writel_relaxed(0x2307b9ac, VCAP_VC_IN_CTRL3);
+ writel_relaxed(0x2f6ad272, VCAP_VC_IN_CTRL4);
+ writel_relaxed(0x00006b38, VCAP_VC_IN_CTRL5);
+
+ dprintk(2, "%s: Done VC configuration\n", __func__);
+
+ return 0;
+}
+
+int detect_vc(struct vcap_dev *dev)
+{
+ int result;
+ result = readl_relaxed(VCAP_HARDWARE_VERSION_REG);
+ dprintk(1, "Hardware version: %08x\n", result);
+ if (result != VCAP_HARDWARE_VERSION)
+ return -ENODEV;
+ return 0;
+}
+
+int deinit_vc(void)
+{
+ return 0;
+}
diff --git a/drivers/media/video/vcap_vc.h b/drivers/media/video/vcap_vc.h
new file mode 100644
index 0000000..e431038
--- /dev/null
+++ b/drivers/media/video/vcap_vc.h
@@ -0,0 +1,86 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef VCAP_VC_H
+#define VCAP_VC_H
+
+/* #define NEW_S_FMT */
+#include <linux/interrupt.h>
+
+#include <media/vcap_v4l2.h>
+extern struct v4l2_format_vc_ext vcap_vc_lut[];
+
+#define VCAP_HARDWARE_VERSION 0x10000000
+
+#define VCAP_BASE (dev->vcapbase)
+#define VCAP_OFFSET(off) (VCAP_BASE + off)
+
+#define VCAP_HARDWARE_VERSION_REG (VCAP_BASE + 0x0000)
+
+#define VCAP_SW_RESET_REQ (VCAP_BASE + 0x0024)
+#define VCAP_SW_RESET_STATUS (VCAP_BASE + 0x0028)
+
+#define VCAP_VC_CTRL (VCAP_BASE + 0x0800)
+#define VCAP_VC_NPL_CTRL (VCAP_BASE + 0x0804)
+#define VCAP_VC_POLARITY (VCAP_BASE + 0x081c)
+#define VCAP_VC_V_H_TOTAL (VCAP_BASE + 0x0820)
+#define VCAP_VC_H_ACTIVE (VCAP_BASE + 0x0824)
+#define VCAP_VC_V_ACTIVE (VCAP_BASE + 0x0828)
+#define VCAP_VC_V_ACTIVE_F2 (VCAP_BASE + 0x0830)
+#define VCAP_VC_VSYNC_VPOS (VCAP_BASE + 0x0834)
+#define VCAP_VC_VSYNC_F2_VPOS (VCAP_BASE + 0x0838)
+#define VCAP_VC_HSYNC_HPOS (VCAP_BASE + 0x0840)
+#define VCAP_VC_VSYNC_F2_HPOS (VCAP_BASE + 0x083c)
+#define VCAP_VC_BUF_CTRL (VCAP_BASE + 0x0848)
+
+#define VCAP_VC_Y_STRIDE (VCAP_BASE + 0x084c)
+#define VCAP_VC_C_STRIDE (VCAP_BASE + 0x0850)
+
+#define VCAP_VC_Y_ADDR_1 (VCAP_BASE + 0x0854)
+#define VCAP_VC_C_ADDR_1 (VCAP_BASE + 0x0858)
+#define VCAP_VC_Y_ADDR_2 (VCAP_BASE + 0x085c)
+#define VCAP_VC_C_ADDR_2 (VCAP_BASE + 0x0860)
+#define VCAP_VC_Y_ADDR_3 (VCAP_BASE + 0x0864)
+#define VCAP_VC_C_ADDR_3 (VCAP_BASE + 0x0868)
+#define VCAP_VC_Y_ADDR_4 (VCAP_BASE + 0x086c)
+#define VCAP_VC_C_ADDR_4 (VCAP_BASE + 0x0870)
+#define VCAP_VC_Y_ADDR_5 (VCAP_BASE + 0x0874)
+#define VCAP_VC_C_ADDR_5 (VCAP_BASE + 0x0878)
+#define VCAP_VC_Y_ADDR_6 (VCAP_BASE + 0x087c)
+#define VCAP_VC_C_ADDR_6 (VCAP_BASE + 0x0880)
+
+#define VCAP_VC_IN_CTRL1 (VCAP_BASE + 0x0808)
+#define VCAP_VC_IN_CTRL2 (VCAP_BASE + 0x080c)
+#define VCAP_VC_IN_CTRL3 (VCAP_BASE + 0x0810)
+#define VCAP_VC_IN_CTRL4 (VCAP_BASE + 0x0814)
+#define VCAP_VC_IN_CTRL5 (VCAP_BASE + 0x0818)
+
+#define VCAP_VC_INT_MASK (VCAP_BASE + 0x0884)
+#define VCAP_VC_INT_CLEAR (VCAP_BASE + 0x0888)
+#define VCAP_VC_INT_STATUS (VCAP_BASE + 0x088c)
+#define VCAP_VC_TIMESTAMP (VCAP_BASE + 0x0034)
+
+#define VC_BUFFER_WRITTEN (0x3 << 1)
+
+struct vc_reg_data {
+ unsigned data;
+ unsigned addr;
+};
+
+int vc_start_capture(struct vcap_client_data *c_data);
+int vc_hw_kick_off(struct vcap_client_data *c_data);
+void vc_stop_capture(struct vcap_client_data *c_data);
+int config_vc_format(struct vcap_client_data *c_data);
+int detect_vc(struct vcap_dev *dev);
+int deinit_vc(void);
+irqreturn_t vc_handler(struct vcap_dev *dev);
+#endif
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
index 59a4283..2a25089 100644
--- a/drivers/mfd/wcd9xxx-core.c
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -59,8 +59,8 @@
dev_err(wcd9xxx->dev, "Codec read failed\n");
return ret;
} else
- dev_dbg(wcd9xxx->dev, "Read 0x%02x from R%d(0x%x)\n",
- *buf, reg, reg);
+ dev_dbg(wcd9xxx->dev, "Read 0x%02x from 0x%x\n",
+ *buf, reg);
return 0;
}
@@ -90,8 +90,8 @@
return -EINVAL;
}
- dev_dbg(wcd9xxx->dev, "Write %02x to R%d(0x%x)\n",
- *buf, reg, reg);
+ dev_dbg(wcd9xxx->dev, "Write %02x to 0x%x\n",
+ *buf, reg);
return wcd9xxx->write_dev(wcd9xxx, reg, bytes, src, interface_reg);
}
diff --git a/drivers/mfd/wcd9xxx-slimslave.c b/drivers/mfd/wcd9xxx-slimslave.c
index 6e23930..3b7bdc8 100644
--- a/drivers/mfd/wcd9xxx-slimslave.c
+++ b/drivers/mfd/wcd9xxx-slimslave.c
@@ -356,7 +356,7 @@
if (slave_port_id <=
SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID) {
payload_tx_0 = payload_tx_0 | (1 << slave_port_id);
- } else if (slave_port_id <
+ } else if (slave_port_id <=
SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID) {
payload_tx_1 = payload_tx_1 |
(1 <<
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index ef4ae57..ca86323 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -2084,18 +2084,36 @@
int mmc_detect_card_removed(struct mmc_host *host)
{
struct mmc_card *card = host->card;
+ int ret;
WARN_ON(!host->claimed);
+
+ if (!card)
+ return 1;
+
+ ret = mmc_card_removed(card);
/*
* The card will be considered unchanged unless we have been asked to
* detect a change or host requires polling to provide card detection.
*/
- if (card && !host->detect_change && !(host->caps & MMC_CAP_NEEDS_POLL))
- return mmc_card_removed(card);
+ if (!host->detect_change && !(host->caps & MMC_CAP_NEEDS_POLL) &&
+ !(host->caps2 & MMC_CAP2_DETECT_ON_ERR))
+ return ret;
host->detect_change = 0;
+ if (!ret) {
+ ret = _mmc_detect_card_removed(host);
+ if (ret && (host->caps2 & MMC_CAP2_DETECT_ON_ERR)) {
+ /*
+ * Schedule a detect work as soon as possible to let a
+ * rescan handle the card removal.
+ */
+ cancel_delayed_work(&host->detect);
+ mmc_detect_change(host, 0);
+ }
+ }
- return _mmc_detect_card_removed(host);
+ return ret;
}
EXPORT_SYMBOL(mmc_detect_card_removed);
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 122c891..e1a6ffd 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -54,6 +54,7 @@
#include <mach/clk.h>
#include <mach/dma.h>
#include <mach/sdio_al.h>
+#include <mach/mpm.h>
#include "msm_sdcc.h"
#include "msm_sdcc_dml.h"
@@ -68,6 +69,8 @@
#define SPS_SDCC_CONSUMER_PIPE_INDEX 2
#define SPS_CONS_PERIPHERAL 0
#define SPS_PROD_PERIPHERAL 1
+/* Use SPS only if transfer size is more than this macro */
+#define SPS_MIN_XFER_SIZE MCI_FIFOSIZE
#if defined(CONFIG_DEBUG_FS)
static void msmsdcc_dbg_createhost(struct msmsdcc_host *);
@@ -760,13 +763,32 @@
tasklet_schedule(&host->dma_tlet);
}
-static int msmsdcc_check_dma_op_req(struct mmc_data *data)
+static bool msmsdcc_is_dma_possible(struct msmsdcc_host *host,
+ struct mmc_data *data)
{
- if (((data->blksz * data->blocks) < MCI_FIFOSIZE) ||
- ((data->blksz * data->blocks) % MCI_FIFOSIZE))
- return -EINVAL;
- else
- return 0;
+ bool ret = true;
+ u32 xfer_size = data->blksz * data->blocks;
+
+ if (host->is_sps_mode) {
+ /*
+ * BAM Mode: Fall back on PIO if size is less
+ * than or equal to SPS_MIN_XFER_SIZE bytes.
+ */
+ if (xfer_size <= SPS_MIN_XFER_SIZE)
+ ret = false;
+ } else if (host->is_dma_mode) {
+ /*
+ * ADM Mode: Fall back on PIO if size is less than FIFO size
+ * or not integer multiple of FIFO size
+ */
+ if (xfer_size % MCI_FIFOSIZE)
+ ret = false;
+ } else {
+ /* PIO Mode */
+ ret = false;
+ }
+
+ return ret;
}
static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
@@ -1075,7 +1097,7 @@
if (host->curr.wait_for_auto_prog_done)
datactrl |= MCI_AUTO_PROG_DONE;
- if (!msmsdcc_check_dma_op_req(data)) {
+ if (msmsdcc_is_dma_possible(host, data)) {
if (host->is_dma_mode && !msmsdcc_config_dma(host, data)) {
datactrl |= MCI_DPSM_DMAENABLE;
} else if (host->is_sps_mode) {
@@ -2374,6 +2396,37 @@
return rc;
}
+static int msmsdcc_cfg_mpm_sdiowakeup(struct msmsdcc_host *host,
+ unsigned mode)
+{
+ int ret = 0;
+ unsigned int pin = host->plat->mpm_sdiowakeup_int;
+
+ if (!pin)
+ return 0;
+
+ switch (mode) {
+ case SDC_DAT1_DISABLE:
+ ret = msm_mpm_enable_pin(pin, 0);
+ break;
+ case SDC_DAT1_ENABLE:
+ ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
+ ret = msm_mpm_enable_pin(pin, 1);
+ break;
+ case SDC_DAT1_ENWAKE:
+ ret = msm_mpm_set_pin_wake(pin, 1);
+ break;
+ case SDC_DAT1_DISWAKE:
+ ret = msm_mpm_set_pin_wake(pin, 0);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
static u32 msmsdcc_setup_pwr(struct msmsdcc_host *host, struct mmc_ios *ios)
{
u32 pwr = 0;
@@ -2394,9 +2447,7 @@
switch (ios->power_mode) {
case MMC_POWER_OFF:
pwr = MCI_PWR_OFF;
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_DISABLE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_DISABLE);
/*
* As VDD pad rail is always on, set low voltage for VDD
* pad rail when slot is unused (when card is not present
@@ -2408,9 +2459,7 @@
case MMC_POWER_UP:
/* writing PWR_UP bit is redundant */
pwr = MCI_PWR_UP;
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_ENABLE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_ENABLE);
msmsdcc_set_vddp_high_vol(host);
msmsdcc_setup_pins(host, true);
@@ -2498,9 +2547,7 @@
writel_relaxed(MCI_SDIOINTMASK,
host->base + MMCIMASK0);
mb();
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_ENWAKE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_ENWAKE);
/* configure sdcc core interrupt as wakeup interrupt */
msmsdcc_enable_irq_wake(host);
} else {
@@ -2522,9 +2569,7 @@
*/
writel_relaxed(MCI_SDIOINTMASK, host->base + MMCICLEAR);
msmsdcc_sync_reg_wr(host);
- if (host->plat->cfg_mpm_sdiowakeup)
- host->plat->cfg_mpm_sdiowakeup(
- mmc_dev(mmc), SDC_DAT1_DISWAKE);
+ msmsdcc_cfg_mpm_sdiowakeup(host, SDC_DAT1_DISWAKE);
msmsdcc_disable_irq_wake(host);
} else if (!host->sdio_wakeupirq_disabled) {
disable_irq_nosync(host->plat->sdiowakeup_irq);
@@ -3887,13 +3932,11 @@
/*
* This threshold controls when the BAM publish
* the descriptor size on the sideband interface.
- * SPS HW will only be used when
- * data transfer size > MCI_FIFOSIZE (64 bytes).
- * PIO mode will be used when
- * data transfer size < MCI_FIFOSIZE (64 bytes).
- * So set this thresold value to 64 bytes.
+ * SPS HW will be used for data transfer size even
+ * less than SDCC FIFO size. So let's set BAM summing
+ * thresold to SPS_MIN_XFER_SIZE bytes.
*/
- bam.summing_threshold = 64;
+ bam.summing_threshold = SPS_MIN_XFER_SIZE;
/* SPS driver wll handle the SDCC BAM IRQ */
bam.irq = (u32)host->bam_irqres->start;
bam.manage = SPS_BAM_MGR_LOCAL;
@@ -4074,7 +4117,7 @@
msmsdcc_print_regs("SDCC-CORE", host->base, 28);
if (host->curr.data) {
- if (msmsdcc_check_dma_op_req(host->curr.data))
+ if (!msmsdcc_is_dma_possible(host, host->curr.data))
pr_info("%s: PIO mode\n", mmc_hostname(host->mmc));
else if (host->is_dma_mode)
pr_info("%s: ADM mode: busy=%d, chnl=%d, crci=%d\n",
@@ -4552,7 +4595,7 @@
mmc->caps |= (MMC_CAP_SET_XPC_330 | MMC_CAP_SET_XPC_300 |
MMC_CAP_SET_XPC_180);
- mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
+ mmc->caps2 |= (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_DETECT_ON_ERR);
if (pdev->dev.of_node) {
if (of_get_property((&pdev->dev)->of_node,
"qcom,sdcc-hs200", NULL))
@@ -4623,7 +4666,7 @@
}
}
- if (plat->cfg_mpm_sdiowakeup) {
+ if (host->plat->mpm_sdiowakeup_int) {
wake_lock_init(&host->sdio_wlock, WAKE_LOCK_SUSPEND,
mmc_hostname(mmc));
}
@@ -5069,7 +5112,7 @@
* the SDIO work will be processed.
*/
if (mmc->card && mmc_card_sdio(mmc->card)) {
- if ((host->plat->cfg_mpm_sdiowakeup ||
+ if ((host->plat->mpm_sdiowakeup_int ||
host->plat->sdiowakeup_irq) &&
wake_lock_active(&host->sdio_wlock))
wake_lock_timeout(&host->sdio_wlock, 1);
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index d24ce3f..eea4fa1 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -1168,7 +1168,10 @@
return 0;
/* USB charging */
- val->intval = is_usb_chg_plugged_in(the_chip);
+ if (usb_target_ma < USB_WALL_THRESHOLD_MA)
+ val->intval = is_usb_chg_plugged_in(the_chip);
+ else
+ return 0;
break;
default:
return -EINVAL;
@@ -1717,6 +1720,23 @@
}
EXPORT_SYMBOL(pm8921_is_battery_charging);
+int pm8921_set_usb_power_supply_type(enum power_supply_type type)
+{
+ if (!the_chip) {
+ pr_err("called before init\n");
+ return -EINVAL;
+ }
+
+ if (type < POWER_SUPPLY_TYPE_USB)
+ return -EINVAL;
+
+ the_chip->usb_psy.type = type;
+ power_supply_changed(&the_chip->usb_psy);
+ power_supply_changed(&the_chip->dc_psy);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8921_set_usb_power_supply_type);
+
int pm8921_batt_temperature(void)
{
if (!the_chip) {
diff --git a/drivers/usb/gadget/f_mbim.c b/drivers/usb/gadget/f_mbim.c
index 21b393e..0598c7b 100644
--- a/drivers/usb/gadget/f_mbim.c
+++ b/drivers/usb/gadget/f_mbim.c
@@ -1048,7 +1048,7 @@
pr_info("control request: %02x.%02x v%04x i%04x l%d\n",
ctrl->bRequestType, ctrl->bRequest,
w_value, w_index, w_length);
- req->zero = 0;
+ req->zero = (value < w_length);
req->length = value;
value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
if (value < 0) {
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 420f417..41eeee1 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -1008,6 +1008,33 @@
}
#endif
+static int msm_otg_notify_chg_type(struct msm_otg *motg)
+{
+ static int charger_type;
+ /*
+ * TODO
+ * Unify OTG driver charger types and power supply charger types
+ */
+ if (charger_type == motg->chg_type)
+ return 0;
+
+ if (motg->chg_type == USB_SDP_CHARGER)
+ charger_type = POWER_SUPPLY_TYPE_USB;
+ else if (motg->chg_type == USB_CDP_CHARGER)
+ charger_type = POWER_SUPPLY_TYPE_USB_CDP;
+ else if (motg->chg_type == USB_DCP_CHARGER)
+ charger_type = POWER_SUPPLY_TYPE_USB_DCP;
+ else if ((motg->chg_type == USB_ACA_DOCK_CHARGER ||
+ motg->chg_type == USB_ACA_A_CHARGER ||
+ motg->chg_type == USB_ACA_B_CHARGER ||
+ motg->chg_type == USB_ACA_C_CHARGER))
+ charger_type = POWER_SUPPLY_TYPE_USB_ACA;
+ else
+ charger_type = POWER_SUPPLY_TYPE_BATTERY;
+
+ return pm8921_set_usb_power_supply_type(charger_type);
+}
+
static int msm_otg_notify_power_supply(struct msm_otg *motg, unsigned mA)
{
struct power_supply *psy;
@@ -1051,6 +1078,11 @@
mA > IDEV_ACA_CHG_LIMIT)
mA = IDEV_ACA_CHG_LIMIT;
+ if (msm_otg_notify_chg_type(motg))
+ dev_err(motg->otg.dev,
+ "Failed notifying %d charger type to PMIC\n",
+ motg->chg_type);
+
if (motg->cur_power == mA)
return;
@@ -2079,9 +2111,9 @@
} else {
pr_debug("chg_work cancel");
cancel_delayed_work_sync(&motg->chg_work);
- msm_otg_notify_charger(motg, 0);
motg->chg_state = USB_CHG_STATE_UNDEFINED;
motg->chg_type = USB_INVALID_CHARGER;
+ msm_otg_notify_charger(motg, 0);
msm_otg_reset(otg);
pm_runtime_put_noidle(otg->dev);
pm_runtime_suspend(otg->dev);
@@ -2120,11 +2152,11 @@
test_bit(ID_B, &motg->inputs) ||
!test_bit(B_SESS_VLD, &motg->inputs)) {
pr_debug("!id || id_a/b || !b_sess_vld\n");
+ motg->chg_state = USB_CHG_STATE_UNDEFINED;
+ motg->chg_type = USB_INVALID_CHARGER;
msm_otg_notify_charger(motg, 0);
srp_reqd = otg->gadget->otg_srp_reqd;
msm_otg_start_peripheral(otg, 0);
- motg->chg_state = USB_CHG_STATE_UNDEFINED;
- motg->chg_type = USB_INVALID_CHARGER;
if (test_bit(ID_B, &motg->inputs))
clear_bit(ID_B, &motg->inputs);
clear_bit(B_BUS_REQ, &motg->inputs);
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 562c0c8..b768784 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -467,6 +467,14 @@
{
/* empty */
}
+static inline void mdp4_dtv_overlay_blt_start(struct msm_fb_data_type *mfd)
+{
+ return;
+}
+static inline void mdp4_dtv_overlay_blt_stop(struct msm_fb_data_type *mfd)
+{
+ return;
+}
#endif
void mdp4_dtv_set_black_screen(void);
diff --git a/drivers/video/msm/mipi_NT35510.c b/drivers/video/msm/mipi_NT35510.c
index b84072b..eaf1868 100644
--- a/drivers/video/msm/mipi_NT35510.c
+++ b/drivers/video/msm/mipi_NT35510.c
@@ -384,7 +384,7 @@
0xB6, 0x02,
};
static char video19[3] = {
- 0xB1, 0xFC, 0x06,
+ 0xB1, 0xFC, 0x00,
};
static char video20[4] = {
0xBC, 0x05, 0x05, 0x05,
diff --git a/drivers/video/msm/mipi_dsi.c b/drivers/video/msm/mipi_dsi.c
index b8169d9..baad0a8 100644
--- a/drivers/video/msm/mipi_dsi.c
+++ b/drivers/video/msm/mipi_dsi.c
@@ -432,6 +432,14 @@
if (mipi_dsi_clk_init(pdev))
return -EPERM;
+ if (mipi_dsi_pdata->splash_is_enabled &&
+ !mipi_dsi_pdata->splash_is_enabled()) {
+ mipi_dsi_ahb_ctrl(1);
+ MIPI_OUTP(MIPI_DSI_BASE + 0x118, 0);
+ MIPI_OUTP(MIPI_DSI_BASE + 0x0, 0);
+ MIPI_OUTP(MIPI_DSI_BASE + 0x200, 0);
+ mipi_dsi_ahb_ctrl(0);
+ }
mipi_dsi_resource_initialized = 1;
return 0;
diff --git a/drivers/video/msm/msm_dss_io_7x27a.c b/drivers/video/msm/msm_dss_io_7x27a.c
index 9e77e30..28204a5 100644
--- a/drivers/video/msm/msm_dss_io_7x27a.c
+++ b/drivers/video/msm/msm_dss_io_7x27a.c
@@ -325,6 +325,8 @@
clk_prepare(mdp_dsi_pclk);
clk_prepare(dsi_byte_div_clk);
clk_prepare(dsi_esc_clk);
+ clk_prepare(dsi_clk);
+ clk_prepare(dsi_pixel_clk);
}
void mipi_dsi_unprepare_clocks(void)
@@ -336,6 +338,8 @@
clk_unprepare(ahb_m_clk);
clk_unprepare(ahb_s_clk);
clk_unprepare(dsi_ref_clk);
+ clk_unprepare(dsi_clk);
+ clk_unprepare(dsi_pixel_clk);
}
void mipi_dsi_ahb_ctrl(u32 enable)
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index e19225e..a2ee306 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -249,6 +249,7 @@
#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
MMC_CAP2_HS200_1_2V_SDR)
+#define MMC_CAP2_DETECT_ON_ERR (1 << 8) /* On I/O err check card removal */
mmc_pm_flag_t pm_caps; /* supported pm features */
unsigned int power_notify_type;
#define MMC_HOST_PW_NOTIFY_NONE 0
diff --git a/include/linux/msm_adc.h b/include/linux/msm_adc.h
index 51371a6..c303e69 100644
--- a/include/linux/msm_adc.h
+++ b/include/linux/msm_adc.h
@@ -236,6 +236,7 @@
MSM_7x30,
MSM_8x60,
FSM_9xxx,
+ MSM_8x25,
};
enum epm_gpio_config {
@@ -344,23 +345,23 @@
int32_t adc_channel_request_conv(void *h, struct completion *conv_complete_evt);
int32_t adc_channel_read_result(void *h, struct adc_chan_result *chan_result);
#else
-static int32_t adc_channel_open(uint32_t channel, void **h)
+static inline int32_t adc_channel_open(uint32_t channel, void **h)
{
pr_err("%s.not supported.\n", __func__);
return -ENODEV;
}
-static int32_t adc_channel_close(void *h)
+static inline int32_t adc_channel_close(void *h)
{
pr_err("%s.not supported.\n", __func__);
return -ENODEV;
}
-static int32_t
+static inline int32_t
adc_channel_request_conv(void *h, struct completion *conv_complete_evt)
{
pr_err("%s.not supported.\n", __func__);
return -ENODEV;
}
-static int32_t
+static inline int32_t
adc_channel_read_result(void *h, struct adc_chan_result *chan_result)
{
pr_err("%s.not supported.\n", __func__);
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index e57df1a..1c3da53 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -434,10 +434,20 @@
} data;
};
+struct mdp_qseed_cfg_data {
+ uint32_t block;
+ uint32_t table_num;
+ uint32_t ops;
+ uint32_t len;
+ uint32_t *data;
+};
+
+
enum {
mdp_op_pcc_cfg,
mdp_op_csc_cfg,
mdp_op_lut_cfg,
+ mdp_op_qseed_cfg,
mdp_op_max,
};
@@ -447,6 +457,7 @@
struct mdp_pcc_cfg_data pcc_cfg_data;
struct mdp_csc_cfg_data csc_cfg_data;
struct mdp_lut_cfg_data lut_cfg_data;
+ struct mdp_qseed_cfg_data qseed_cfg_data;
} data;
};
diff --git a/include/media/Kbuild b/include/media/Kbuild
index a60b86c..8dfb0fc 100644
--- a/include/media/Kbuild
+++ b/include/media/Kbuild
@@ -1,6 +1,7 @@
header-y += tavarua.h
header-y += msm_camera.h
+header-y += vcap_fmt.h
header-y += msm_isp.h
header-y += msm_gemini.h
header-y += msm_v4l2_overlay.h
diff --git a/include/media/vcap_fmt.h b/include/media/vcap_fmt.h
new file mode 100644
index 0000000..4a62bc3
--- /dev/null
+++ b/include/media/vcap_fmt.h
@@ -0,0 +1,140 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef VCAP_FMT_H
+#define VCAP_FMT_H
+
+#define V4L2_BUF_TYPE_INTERLACED_IN_AFE (V4L2_BUF_TYPE_PRIVATE)
+#define V4L2_BUF_TYPE_INTERLACED_IN_DECODER (V4L2_BUF_TYPE_PRIVATE + 1)
+
+enum hal_vcap_mode {
+ HAL_VCAP_MODE_PRO = 0,
+ HAL_VCAP_MODE_INT,
+};
+
+enum hal_vcap_polar {
+ HAL_VCAP_POLAR_NEG = 0,
+ HAL_VCAP_POLAR_POS,
+};
+
+enum hal_vcap_color {
+ HAL_VCAP_YUV = 0,
+ HAL_VCAP_RGB,
+};
+
+enum hal_vcap_vc_fmt {
+ /* 1080p */
+ HAL_VCAP_YUV_1080p_60_RH = 0,
+ HAL_VCAP_YUV_1080p_60_FL,
+ HAL_VCAP_RGB_1080p_60_FL,
+ HAL_VCAP_YUV_1080p_24_FL,
+ HAL_VCAP_YUV_1080p_24_RH,
+ HAL_VCAP_YUV_1080p_24_RW,
+ HAL_VCAP_YUV_1080p_60_RW,
+ HAL_VCAP_YUV_1080p_50_FL,
+ HAL_VCAP_YUV_1080p_50_RH,
+ HAL_VCAP_YUV_1080p_25_FL,
+ HAL_VCAP_YUV_1080p_25_RH,
+ HAL_VCAP_YUV_1080p_30_RH,
+ HAL_VCAP_RGB_1080p_25_FL,
+ HAL_VCAP_RGB_1080p_25_RH,
+ /* 1080i */
+ HAL_VCAP_YUV_1080i_60_FL,
+ HAL_VCAP_YUV_1080i_60_RH,
+ HAL_VCAP_YUV_1080i_60_RW,
+ HAL_VCAP_YUV_1080i_50_FL,
+ HAL_VCAP_YUV_1080i_50_RH,
+ HAL_VCAP_YUV_1080i_50_RW,
+ HAL_VCAP_RGB_1080i_50_FL,
+ HAL_VCAP_RGB_1080i_50_RH,
+ /* 480i */
+ HAL_VCAP_YUV_480i_60_RH,
+ HAL_VCAP_YUV_480i_60_FL,
+ HAL_VCAP_YUV_480i_60_RW,
+ HAL_VCAP_YUV_2880_480i_60_FL,
+ HAL_VCAP_YUV_2880_480i_60_RH,
+ /* 480p */
+ HAL_VCAP_YUV_480p_60_RH,
+ HAL_VCAP_RGB_480p_60_RH,
+ HAL_VCAP_RGB_480p_60_FL,
+ HAL_VCAP_YUV_480p_60_FL,
+ HAL_VCAP_YUV_480p_60_RW,
+ HAL_VCAP_YUV_2880_480p_60_FL,
+ HAL_VCAP_YUV_2880_480p_60_RH,
+ /* 720p */
+ HAL_VCAP_YUV_720p_60_FL,
+ HAL_VCAP_RGB_720p_60_FL,
+ HAL_VCAP_YUV_720p_60_RW,
+ HAL_VCAP_YUV_720p_60_RH,
+ HAL_VCAP_YUV_720p_50_FL,
+ HAL_VCAP_YUV_720p_50_RW,
+ HAL_VCAP_YUV_720p_50_RH,
+ /* 576p */
+ HAL_VCAP_YUV_576p_50_FL,
+ HAL_VCAP_RGB_576p_50_FL,
+ HAL_VCAP_YUV_576p_50_RW,
+ HAL_VCAP_YUV_576p_50_RH,
+ HAL_VCAP_YUV_1440_576p_50_RH,
+ HAL_VCAP_YUV_2880_576p_50_FL,
+ HAL_VCAP_YUV_2880_576p_50_RH,
+ /* 576i */
+ HAL_VCAP_YUV_576i_50_FL,
+ HAL_VCAP_YUV_576i_50_RW,
+ HAL_VCAP_YUV_576i_50_RH,
+ /* XGA 1024x768 */
+ HAL_VCAP_YUV_XGA_FL,
+ HAL_VCAP_YUV_XGA_RH,
+ HAL_VCAP_YUV_XGA_RB,
+ /* SXGA 1280x1024 */
+ HAL_VCAP_YUV_SXGA_FL,
+ HAL_VCAP_RGB_SXGA_FL,
+ HAL_VCAP_YUV_SXGA_RH,
+ HAL_VCAP_YUV_SXGA_RB,
+ /* UXGA 1600x1200 */
+ HAL_VCAP_YUV_UXGA_FL,
+ HAL_VCAP_RGB_UXGA_FL,
+ HAL_VCAP_YUV_UXGA_RH,
+ HAL_VCAP_YUV_UXGA_RB,
+ /* test odd height */
+ HAL_VCAP_ODD_HEIGHT,
+ /* test odd width RGB only */
+ HAL_VCAP_ODD_WIDTH,
+};
+
+struct v4l2_format_vc_ext {
+ enum hal_vcap_vc_fmt format;
+ enum hal_vcap_mode mode;
+ enum hal_vcap_polar h_polar;
+ enum hal_vcap_polar v_polar;
+ enum hal_vcap_polar d_polar;
+ enum hal_vcap_color color_space;
+
+ float clk_freq;
+ uint32_t vtotal;
+ uint32_t htotal;
+ uint32_t hactive_start;
+ uint32_t hactive_end;
+ uint32_t vactive_start;
+ uint32_t vactive_end;
+ uint32_t vsync_start;
+ uint32_t vsync_end;
+ uint32_t hsync_start;
+ uint32_t hsync_end;
+ uint32_t f2_vactive_start;
+ uint32_t f2_vactive_end;
+ uint32_t f2_vsync_h_start;
+ uint32_t f2_vsync_h_end;
+ uint32_t f2_vsync_v_start;
+ uint32_t f2_vsync_v_end;
+};
+#endif
diff --git a/include/media/vcap_v4l2.h b/include/media/vcap_v4l2.h
new file mode 100644
index 0000000..57f9703
--- /dev/null
+++ b/include/media/vcap_v4l2.h
@@ -0,0 +1,132 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef VCAP_V4L2_H
+#define VCAP_V4L2_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <media/videobuf2-vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-common.h>
+#include <media/vcap_fmt.h>
+#include <mach/board.h>
+
+struct vcap_client_data;
+
+enum rdy_buf {
+ VC_NO_BUF = 0,
+ VC_BUF1 = 1 << 1,
+ VC_BUF2 = 1 << 2,
+ VC_BUF1N2 = 0x11 << 1,
+};
+
+struct vcap_buf_info {
+ unsigned long vaddr;
+ unsigned long size;
+};
+
+struct vcap_action {
+ struct list_head active;
+
+ /* thread for generating video stream*/
+ struct task_struct *kthread;
+ wait_queue_head_t wq;
+
+ /* Buffer index */
+ enum rdy_buf buf_ind;
+
+ /* Buffers inside vc */
+ struct vcap_buffer *buf1;
+ struct vcap_buffer *buf2;
+
+ /* Counters to control fps rate */
+ int frame;
+ int ini_jiffies;
+};
+
+struct vcap_dev {
+ struct v4l2_device v4l2_dev;
+
+ struct video_device *vfd;
+ struct ion_client *ion_client;
+
+ struct resource *vcapirq;
+
+ struct resource *vcapmem;
+ struct resource *vcapio;
+ void __iomem *vcapbase;
+
+ struct vcap_platform_data *vcap_pdata;
+
+ struct regulator *fs_vcap;
+ struct clk *vcap_clk;
+ struct clk *vcap_p_clk;
+ struct clk *vcap_npl_clk;
+ /*struct platform_device *pdev;*/
+
+ uint32_t bus_client_handle;
+
+ struct vcap_client_data *vc_client;
+ struct vcap_client_data *vp_client;
+
+ atomic_t vc_enabled;
+ atomic_t vc_resource;
+ atomic_t vp_resource;
+};
+
+struct vp_format_data {
+ unsigned int width, height;
+ unsigned int pixelformat;
+ enum v4l2_field field;
+
+};
+
+struct vcap_buffer {
+ /* common v4l buffer stuff -- must be first */
+ struct vb2_buffer vb;
+ struct list_head list;
+ unsigned long paddr;
+ struct ion_handle *ion_handle;
+};
+
+struct vcap_client_data {
+ struct vcap_dev *dev;
+
+ struct vb2_queue vc_vidq;
+ /*struct vb2_queue vb__vidq;*/
+ /*struct vb2_queue vb_cap_vidq;*/
+
+ struct v4l2_format_vc_ext vc_format;
+
+ enum v4l2_buf_type vp_buf_type_field;
+ struct vp_format_data vp_format;
+
+ struct vcap_action vid_vc_action;
+ struct workqueue_struct *vcap_work_q;
+ struct ion_handle *vc_ion_handle;
+
+ uint32_t hold_vc;
+ uint32_t hold_vp;
+
+ spinlock_t cap_slock;
+};
+
+#endif
+#endif
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
old mode 100755
new mode 100644
index f4f833b..598c310
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -1852,11 +1852,29 @@
if (test_bit(HCI_CONN_ENCRYPT_PEND, &conn->pend)) {
if (!ev->status) {
- struct hci_cp_set_conn_encrypt cp;
- cp.handle = ev->handle;
- cp.encrypt = 0x01;
- hci_send_cmd(hdev, HCI_OP_SET_CONN_ENCRYPT,
- sizeof(cp), &cp);
+ if (conn->link_mode & HCI_LM_ENCRYPT) {
+ /* Encryption implies authentication */
+ conn->link_mode |= HCI_LM_AUTH;
+ conn->link_mode |= HCI_LM_ENCRYPT;
+ conn->sec_level =
+ conn->pending_sec_level;
+ clear_bit(HCI_CONN_ENCRYPT_PEND,
+ &conn->pend);
+ hci_encrypt_cfm(conn, ev->status, 1);
+
+ if (test_bit(HCI_MGMT, &hdev->flags))
+ mgmt_encrypt_change(hdev->id,
+ &conn->dst,
+ ev->status);
+
+ } else {
+ struct hci_cp_set_conn_encrypt cp;
+ cp.handle = ev->handle;
+ cp.encrypt = 0x01;
+ hci_send_cmd(hdev,
+ HCI_OP_SET_CONN_ENCRYPT,
+ sizeof(cp), &cp);
+ }
} else {
clear_bit(HCI_CONN_ENCRYPT_PEND, &conn->pend);
hci_encrypt_cfm(conn, ev->status, 0x00);
@@ -2653,6 +2671,7 @@
conn->key_type = ev->key_type;
hci_disconnect_amp(conn, 0x06);
+ conn->link_mode &= ~HCI_LM_ENCRYPT;
pin_len = conn->pin_length;
hci_conn_put(conn);
hci_conn_enter_active_mode(conn, 0);
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index bcd0dd7..8b6f23e 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -1823,7 +1823,7 @@
return cmd_status(sk, index, MGMT_OP_SET_RSSI_REPORTER,
ENODEV);
- hci_dev_lock(hdev);
+ hci_dev_lock_bh(hdev);
conn = hci_conn_hash_lookup_ba(hdev, LE_LINK, &cp->bdaddr);
@@ -1838,7 +1838,7 @@
__le16_to_cpu(cp->interval), cp->updateOnThreshExceed);
failed:
- hci_dev_unlock(hdev);
+ hci_dev_unlock_bh(hdev);
hci_dev_put(hdev);
return err;
@@ -1862,7 +1862,7 @@
return cmd_status(sk, index, MGMT_OP_UNSET_RSSI_REPORTER,
ENODEV);
- hci_dev_lock(hdev);
+ hci_dev_lock_bh(hdev);
conn = hci_conn_hash_lookup_ba(hdev, LE_LINK, &cp->bdaddr);
@@ -1875,7 +1875,7 @@
hci_conn_unset_rssi_reporter(conn);
failed:
- hci_dev_unlock(hdev);
+ hci_dev_unlock_bh(hdev);
hci_dev_put(hdev);
return err;
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 590f1c5..e636bb7 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -34,8 +34,10 @@
#include <linux/gpio.h>
#include "wcd9310.h"
-#define WCD9310_RATES (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|\
- SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_48000)
+#define WCD9310_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
+
#define NUM_DECIMATORS 10
#define NUM_INTERPOLATORS 7
@@ -63,7 +65,9 @@
#define AIF1_PB 1
#define AIF1_CAP 2
#define AIF2_PB 3
-#define NUM_CODEC_DAIS 3
+#define AIF2_CAP 4
+
+#define NUM_CODEC_DAIS 4
#define TABLA_COMP_DIGITAL_GAIN_OFFSET 3
struct tabla_codec_dai_data {
@@ -148,6 +152,8 @@
COMPANDER_FS_16KHZ,
COMPANDER_FS_32KHZ,
COMPANDER_FS_48KHZ,
+ COMPANDER_FS_96KHZ,
+ COMPANDER_FS_192KHZ,
COMPANDER_FS_MAX,
};
@@ -1081,6 +1087,21 @@
"DEC1"
};
+static const char *sb_tx2_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC2"
+};
+
+static const char *sb_tx3_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC3"
+};
+
+static const char *sb_tx4_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC4"
+};
+
static const char *sb_tx5_mux_text[] = {
"ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
"DEC5"
@@ -1217,6 +1238,18 @@
static const struct soc_enum rx6_dsm_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_RX6_B6_CTL, 4, 2, rx_dsm_text);
+static const struct soc_enum sb_tx1_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
+
+static const struct soc_enum sb_tx2_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B2_CTL, 0, 9, sb_tx2_mux_text);
+
+static const struct soc_enum sb_tx3_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B3_CTL, 0, 9, sb_tx3_mux_text);
+
+static const struct soc_enum sb_tx4_mux_enum =
+ SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B4_CTL, 0, 9, sb_tx4_mux_text);
+
static const struct soc_enum sb_tx5_mux_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B5_CTL, 0, 9, sb_tx5_mux_text);
@@ -1239,9 +1272,6 @@
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B10_CTL, 0, 18,
sb_tx7_to_tx10_mux_text);
-static const struct soc_enum sb_tx1_mux_enum =
- SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
-
static const struct soc_enum dec1_mux_enum =
SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B1_CTL, 0, 3, dec1_mux_text);
@@ -1350,6 +1380,18 @@
static const struct snd_kcontrol_new rx6_dsm_mux =
SOC_DAPM_ENUM("RX6 DSM MUX Mux", rx6_dsm_enum);
+static const struct snd_kcontrol_new sb_tx1_mux =
+ SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx2_mux =
+ SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx3_mux =
+ SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx4_mux =
+ SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
+
static const struct snd_kcontrol_new sb_tx5_mux =
SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
@@ -1368,8 +1410,6 @@
static const struct snd_kcontrol_new sb_tx10_mux =
SOC_DAPM_ENUM("SLIM TX10 MUX Mux", sb_tx10_mux_enum);
-static const struct snd_kcontrol_new sb_tx1_mux =
- SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
static int wcd9310_put_dec_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
@@ -2993,6 +3033,15 @@
{"SLIM TX1", NULL, "SLIM TX1 MUX"},
{"SLIM TX1 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX2", NULL, "SLIM TX2 MUX"},
+ {"SLIM TX2 MUX", "DEC2", "DEC2 MUX"},
+
+ {"SLIM TX3", NULL, "SLIM TX3 MUX"},
+ {"SLIM TX3 MUX", "DEC3", "DEC3 MUX"},
+
+ {"SLIM TX4", NULL, "SLIM TX4 MUX"},
+ {"SLIM TX4 MUX", "DEC4", "DEC4 MUX"},
+
{"SLIM TX5", NULL, "SLIM TX5 MUX"},
{"SLIM TX5 MUX", "DEC5", "DEC5 MUX"},
@@ -3018,6 +3067,10 @@
{"SLIM TX8 MUX", "DEC4", "DEC4 MUX"},
{"SLIM TX8 MUX", "DEC5", "DEC5 MUX"},
{"SLIM TX8 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX8 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX8 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX8 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX8 MUX", "DEC10", "DEC10 MUX"},
{"SLIM TX9", NULL, "SLIM TX9 MUX"},
{"SLIM TX9 MUX", "DEC1", "DEC1 MUX"},
@@ -3270,12 +3323,23 @@
{"DEC6 MUX", "ADC1", "ADC1"},
{"DEC6 MUX", NULL, "CDC_CONN"},
{"DEC7 MUX", "DMIC1", "DMIC1"},
+ {"DEC7 MUX", "DMIC6", "DMIC6"},
+ {"DEC7 MUX", "ADC1", "ADC1"},
{"DEC7 MUX", "ADC6", "ADC6"},
{"DEC7 MUX", NULL, "CDC_CONN"},
+ {"DEC8 MUX", "DMIC2", "DMIC2"},
+ {"DEC8 MUX", "DMIC5", "DMIC5"},
+ {"DEC8 MUX", "ADC2", "ADC2"},
{"DEC8 MUX", "ADC5", "ADC5"},
{"DEC8 MUX", NULL, "CDC_CONN"},
+ {"DEC9 MUX", "DMIC4", "DMIC4"},
+ {"DEC9 MUX", "DMIC5", "DMIC5"},
+ {"DEC9 MUX", "ADC2", "ADC2"},
{"DEC9 MUX", "ADC3", "ADC3"},
{"DEC9 MUX", NULL, "CDC_CONN"},
+ {"DEC10 MUX", "DMIC3", "DMIC3"},
+ {"DEC10 MUX", "DMIC6", "DMIC6"},
+ {"DEC10 MUX", "ADC1", "ADC1"},
{"DEC10 MUX", "ADC4", "ADC4"},
{"DEC10 MUX", NULL, "CDC_CONN"},
@@ -3712,7 +3776,7 @@
tabla->dai[dai->id - 1].ch_act = 0;
tabla->dai[dai->id - 1].ch_tot = rx_num;
}
- } else if (dai->id == AIF1_CAP) {
+ } else if (dai->id == AIF1_CAP || dai->id == AIF2_CAP) {
for (i = 0; i < tx_num; i++) {
tabla->dai[dai->id - 1].ch_num[i] = tx_slot[i];
tabla->dai[dai->id - 1].ch_act = 0;
@@ -3760,7 +3824,14 @@
rx_slot[cnt] = rx_ch[5 + cnt];
cnt++;
}
+ } else if (dai->id == AIF2_CAP) {
+ *tx_num = tabla_dai[dai->id - 1].capture.channels_max;
+ tx_slot[0] = tx_ch[cnt];
+ tx_slot[1] = tx_ch[1 + cnt];
+ tx_slot[2] = tx_ch[3 + cnt];
+ tx_slot[3] = tx_ch[5 + cnt];
}
+
return 0;
}
@@ -3799,6 +3870,16 @@
rx_fs_rate = 0x60;
compander_fs = COMPANDER_FS_48KHZ;
break;
+ case 96000:
+ tx_fs_rate = 0x04;
+ rx_fs_rate = 0x80;
+ compander_fs = COMPANDER_FS_96KHZ;
+ break;
+ case 192000:
+ tx_fs_rate = 0x05;
+ rx_fs_rate = 0xA0;
+ compander_fs = COMPANDER_FS_192KHZ;
+ break;
default:
pr_err("%s: Invalid sampling rate %d\n", __func__,
params_rate(params));
@@ -3810,7 +3891,7 @@
* If current dai is a tx dai, set sample rate to
* all the txfe paths that are currently not active
*/
- if (dai->id == AIF1_CAP) {
+ if ((dai->id == AIF1_CAP) || (dai->id == AIF2_CAP)) {
tx_state = snd_soc_read(codec,
TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL);
@@ -3828,7 +3909,7 @@
tx_fs_reg = TABLA_A_CDC_TX1_CLK_FS_CTL
+ (BITS_PER_REG*(path-1));
snd_soc_update_bits(codec, tx_fs_reg,
- 0x03, tx_fs_rate);
+ 0x07, tx_fs_rate);
}
}
if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
@@ -3848,7 +3929,7 @@
break;
}
snd_soc_update_bits(codec, TABLA_A_CDC_CLK_TX_I2S_CTL,
- 0x03, tx_fs_rate);
+ 0x07, tx_fs_rate);
} else {
tabla->dai[dai->id - 1].rate = params_rate(params);
}
@@ -3924,7 +4005,7 @@
.stream_name = "AIF1 Playback",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
@@ -3938,7 +4019,7 @@
.stream_name = "AIF1 Capture",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
@@ -3953,12 +4034,26 @@
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
.rate_min = 8000,
- .rate_max = 48000,
+ .rate_max = 192000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &tabla_dai_ops,
},
+ {
+ .name = "tabla_tx2",
+ .id = AIF2_CAP,
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .rates = WCD9310_RATES,
+ .formats = TABLA_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tabla_dai_ops,
+ },
};
static struct snd_soc_dai_driver tabla_i2s_dai[] = {
@@ -3969,7 +4064,7 @@
.stream_name = "AIF1 Playback",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
@@ -3983,7 +4078,7 @@
.stream_name = "AIF1 Capture",
.rates = WCD9310_RATES,
.formats = TABLA_FORMATS,
- .rate_max = 48000,
+ .rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
@@ -4008,7 +4103,8 @@
switch (event) {
case SND_SOC_DAPM_POST_PMU:
for (j = 0; j < ARRAY_SIZE(tabla_dai); j++) {
- if (tabla_dai[j].id == AIF1_CAP)
+ if ((tabla_dai[j].id == AIF1_CAP) ||
+ (tabla_dai[j].id == AIF2_CAP))
continue;
if (!strncmp(w->sname,
tabla_dai[j].playback.stream_name, 13)) {
@@ -4024,7 +4120,8 @@
break;
case SND_SOC_DAPM_POST_PMD:
for (j = 0; j < ARRAY_SIZE(tabla_dai); j++) {
- if (tabla_dai[j].id == AIF1_CAP)
+ if ((tabla_dai[j].id == AIF1_CAP) ||
+ (tabla_dai[j].id == AIF2_CAP))
continue;
if (!strncmp(w->sname,
tabla_dai[j].playback.stream_name, 13)) {
@@ -4062,6 +4159,9 @@
/* Execute the callback only if interface type is slimbus */
if (tabla_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
return 0;
+
+ pr_debug("%s(): %s %d\n", __func__, w->name, event);
+
switch (event) {
case SND_SOC_DAPM_POST_PMU:
for (j = 0; j < ARRAY_SIZE(tabla_dai); j++) {
@@ -4411,16 +4511,34 @@
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, 0, 0, &sb_tx1_mux),
- SND_SOC_DAPM_AIF_OUT("SLIM TX1", "AIF1 Capture", NULL, SND_SOC_NOPM,
- 0, 0),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX1", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, 0, 0, &sb_tx2_mux),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX2", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, 0, 0, &sb_tx3_mux),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX3", "AIF1 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, 0, 0, &sb_tx4_mux),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX4", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, 0, 0, &sb_tx5_mux),
- SND_SOC_DAPM_AIF_OUT("SLIM TX5", "AIF1 Capture", NULL, SND_SOC_NOPM,
- 4, 0),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX5", "AIF1 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, 0, 0, &sb_tx6_mux),
- SND_SOC_DAPM_AIF_OUT("SLIM TX6", "AIF1 Capture", NULL, SND_SOC_NOPM,
- 5, 0),
+ SND_SOC_DAPM_AIF_OUT_E("SLIM TX6", "AIF2 Capture", 0, SND_SOC_NOPM, 0,
+ 0, tabla_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, 0, 0, &sb_tx7_mux),
SND_SOC_DAPM_AIF_OUT_E("SLIM TX7", "AIF1 Capture", 0, SND_SOC_NOPM, 0,
@@ -7313,6 +7431,9 @@
case AIF2_PB:
ch_cnt = tabla_dai[i].playback.channels_max;
break;
+ case AIF2_CAP:
+ ch_cnt = tabla_dai[i].capture.channels_max;
+ break;
default:
continue;
}
diff --git a/sound/soc/msm/apq8064.c b/sound/soc/msm/apq8064.c
index 26e4263..753ef2e 100644
--- a/sound/soc/msm/apq8064.c
+++ b/sound/soc/msm/apq8064.c
@@ -404,7 +404,7 @@
return 0;
}
-static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
+static const struct snd_soc_dapm_widget apq8064_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
msm_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
@@ -415,26 +415,33 @@
SND_SOC_DAPM_SPK("Ext Spk Top Pos", msm_spkramp_event),
SND_SOC_DAPM_SPK("Ext Spk Top Neg", msm_spkramp_event),
- SND_SOC_DAPM_MIC("Handset Mic", NULL),
+ /************ Analog MICs ************/
+ /**
+ * Analog mic7 (Front Top) on Liquid.
+ * Used as Handset mic on CDP.
+ */
+ SND_SOC_DAPM_MIC("Analog mic7", NULL),
+
SND_SOC_DAPM_MIC("Headset Mic", NULL),
- SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL),
SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL),
+ /*********** Digital Mics ***************/
SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("Digital Mic2", NULL),
SND_SOC_DAPM_MIC("Digital Mic3", NULL),
SND_SOC_DAPM_MIC("Digital Mic4", NULL),
SND_SOC_DAPM_MIC("Digital Mic5", NULL),
SND_SOC_DAPM_MIC("Digital Mic6", NULL),
-
};
-static const struct snd_soc_dapm_route common_audio_map[] = {
+static const struct snd_soc_dapm_route apq8064_audio_map[] = {
{"RX_BIAS", NULL, "MCLK"},
{"LDO_H", NULL, "MCLK"},
+ {"HEADPHONE", NULL, "LDO_H"},
+
/* Speaker path */
{"Ext Spk Bottom Pos", NULL, "LINEOUT1"},
{"Ext Spk Bottom Neg", NULL, "LINEOUT3"},
@@ -442,77 +449,85 @@
{"Ext Spk Top Pos", NULL, "LINEOUT2"},
{"Ext Spk Top Neg", NULL, "LINEOUT4"},
- /* Microphone path */
- {"AMIC1", NULL, "MIC BIAS1 Internal1"},
- {"MIC BIAS1 Internal1", NULL, "Handset Mic"},
+ /************ Analog MIC Paths ************/
+ /**
+ * Analog mic7 (Front Top Mic) on Liquid.
+ * Used as Handset mic on CDP.
+ * Not there on MTP.
+ */
+ {"AMIC1", NULL, "MIC BIAS1 External"},
+ {"MIC BIAS1 External", NULL, "Analog mic7"},
+ /* Headset Mic */
{"AMIC2", NULL, "MIC BIAS2 External"},
{"MIC BIAS2 External", NULL, "Headset Mic"},
- /**
- * AMIC3 and AMIC4 inputs are connected to ANC microphones
- * These mics are biased differently on CDP and FLUID
- * routing entries below are based on bias arrangement
- * on FLUID.
- */
+ /* Headset ANC microphones */
{"AMIC3", NULL, "MIC BIAS3 Internal1"},
{"MIC BIAS3 Internal1", NULL, "ANCRight Headset Mic"},
{"AMIC4", NULL, "MIC BIAS1 Internal2"},
{"MIC BIAS1 Internal2", NULL, "ANCLeft Headset Mic"},
- {"HEADPHONE", NULL, "LDO_H"},
+ /************ Digital MIC Paths ************/
/**
* The digital Mic routes are setup considering
- * fluid as default device.
+ * Liquid as default device.
*/
/**
- * Digital Mic1. Front Bottom left Digital Mic on Fluid and MTP.
- * Digital Mic GM5 on CDP mainboard.
+ * Digital Mic1 (Front bottom left corner) on Liquid.
+ * Digital Mic2 (Front bottom right) on MTP.
+ * Digital Mic GM1 on CDP mainboard.
* Conncted to DMIC2 Input on Tabla codec.
*/
{"DMIC2", NULL, "MIC BIAS1 External"},
{"MIC BIAS1 External", NULL, "Digital Mic1"},
/**
- * Digital Mic2. Front Bottom right Digital Mic on Fluid and MTP.
- * Digital Mic GM6 on CDP mainboard.
- * Conncted to DMIC1 Input on Tabla codec.
- */
- {"DMIC1", NULL, "MIC BIAS1 External"},
- {"MIC BIAS1 External", NULL, "Digital Mic2"},
-
- /**
- * Digital Mic3. Back Bottom Digital Mic on Fluid.
- * Digital Mic GM1 on CDP mainboard.
- * Conncted to DMIC4 Input on Tabla codec.
- */
- {"DMIC4", NULL, "MIC BIAS3 External"},
- {"MIC BIAS3 External", NULL, "Digital Mic3"},
-
- /**
- * Digital Mic4. Back top Digital Mic on Fluid.
+ * Digital Mic2 (Front left side) on Liquid.
* Digital Mic GM2 on CDP mainboard.
+ * Not there on MTP.
* Conncted to DMIC3 Input on Tabla codec.
*/
{"DMIC3", NULL, "MIC BIAS3 External"},
- {"MIC BIAS3 External", NULL, "Digital Mic4"},
+ {"MIC BIAS3 External", NULL, "Digital Mic2"},
/**
- * Digital Mic5. Front top Digital Mic on Fluid.
+ * Digital Mic3. Front bottom left of middle on Liquid.
+ * Digital Mic5 (Top front Mic) on MTP.
+ * Digital Mic GM5 on CDP mainboard.
+ * Conncted to DMIC6 Input on Tabla codec.
+ */
+ {"DMIC6", NULL, "MIC BIAS4 External"},
+ {"MIC BIAS4 External", NULL, "Digital Mic3"},
+
+ /**
+ * Digital Mic4. Back bottom on Liquid.
* Digital Mic GM3 on CDP mainboard.
+ * Top Front Mic on MTP.
* Conncted to DMIC5 Input on Tabla codec.
*/
{"DMIC5", NULL, "MIC BIAS4 External"},
- {"MIC BIAS4 External", NULL, "Digital Mic5"},
+ {"MIC BIAS4 External", NULL, "Digital Mic4"},
- /* Tabla digital Mic6 - back bottom digital Mic on Liquid and
- * bottom mic on CDP. FLUID/MTP do not have dmic6 installed.
+ /**
+ * Digital Mic5. Front bottom right of middle on Liquid.
+ * Digital Mic GM6 on CDP mainboard.
+ * Not there on MTP.
+ * Conncted to DMIC4 Input on Tabla codec.
*/
- {"DMIC6", NULL, "MIC BIAS4 External"},
- {"MIC BIAS4 External", NULL, "Digital Mic6"},
+ {"DMIC4", NULL, "MIC BIAS3 External"},
+ {"MIC BIAS3 External", NULL, "Digital Mic5"},
+
+ /* Digital Mic6 (Front bottom right corner) on Liquid.
+ * Digital Mic1 (Front bottom Left) on MTP.
+ * Digital Mic GM4 on CDP.
+ * Conncted to DMIC1 Input on Tabla codec.
+ */
+ {"DMIC1", NULL, "MIC BIAS1 External"},
+ {"MIC BIAS1 External", NULL, "Digital Mic6"},
};
static const char *spk_function[] = {"Off", "On"};
@@ -709,10 +724,13 @@
int ret = 0;
unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
+ unsigned int user_set_tx_ch = 0;
- pr_debug("%s: ch=%d\n", __func__,
- msm_slim_0_rx_ch);
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+
+ pr_debug("%s: rx_0_ch=%d\n", __func__, msm_slim_0_rx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
@@ -734,20 +752,30 @@
goto end;
}
} else {
+
+ if (codec_dai->id == 2)
+ user_set_tx_ch = msm_slim_0_tx_ch;
+ else if (codec_dai->id == 4)
+ user_set_tx_ch = params_channels(params);
+
+ pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
+ codec_dai->name, codec_dai->id, user_set_tx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
pr_err("%s: failed to get codec chan map\n", __func__);
goto end;
}
+
ret = snd_soc_dai_set_channel_map(cpu_dai,
- msm_slim_0_tx_ch, tx_ch, 0 , 0);
+ user_set_tx_ch, tx_ch, 0 , 0);
if (ret < 0) {
pr_err("%s: failed to set cpu chan map\n", __func__);
goto end;
}
ret = snd_soc_dai_set_channel_map(codec_dai,
- msm_slim_0_tx_ch, tx_ch, 0, 0);
+ user_set_tx_ch, tx_ch, 0, 0);
if (ret < 0) {
pr_err("%s: failed to set codec channel map\n",
__func__);
@@ -824,11 +852,11 @@
if (err < 0)
return err;
- snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
- ARRAY_SIZE(msm_dapm_widgets));
+ snd_soc_dapm_new_controls(dapm, apq8064_dapm_widgets,
+ ARRAY_SIZE(apq8064_dapm_widgets));
- snd_soc_dapm_add_routes(dapm, common_audio_map,
- ARRAY_SIZE(common_audio_map));
+ snd_soc_dapm_add_routes(dapm, apq8064_audio_map,
+ ARRAY_SIZE(apq8064_audio_map));
snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
@@ -1374,6 +1402,17 @@
.be_hw_params_fixup = msm_btsco_be_hw_params_fixup,
.ops = &msm_slimbus_1_be_ops,
},
+ {
+ .name = "SLIMBUS_2 Hostless",
+ .stream_name = "SLIMBUS_2 Hostless",
+ .cpu_dai_name = "msm-dai-q6.16389",
+ .platform_name = "msm-pcm-hostless",
+ .codec_name = "tabla_codec",
+ .codec_dai_name = "tabla_tx2",
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ops = &msm_be_ops,
+ },
+
};
struct snd_soc_card snd_soc_card_msm = {
diff --git a/sound/soc/msm/msm-dai-q6.c b/sound/soc/msm/msm-dai-q6.c
index c876940..e6d5012 100644
--- a/sound/soc/msm/msm-dai-q6.c
+++ b/sound/soc/msm/msm-dai-q6.c
@@ -281,7 +281,7 @@
dev_dbg(dai->dev, "%s:slimbus_dev_id[%hu] bit_wd[%hu] format[%hu]\n"
"num_channel %hu slave_ch_mapping[0] %hu\n"
"slave_port_mapping[1] %hu slave_port_mapping[2] %hu\n"
- "sample_rate %d\n", __func__,
+ "slave_port_mapping[3] %hu\n sample_rate %d\n", __func__,
dai_data->port_config.slim_sch.slimbus_dev_id,
dai_data->port_config.slim_sch.bit_width,
dai_data->port_config.slim_sch.data_format,
@@ -289,6 +289,7 @@
dai_data->port_config.slim_sch.slave_ch_mapping[0],
dai_data->port_config.slim_sch.slave_ch_mapping[1],
dai_data->port_config.slim_sch.slave_ch_mapping[2],
+ dai_data->port_config.slim_sch.slave_ch_mapping[3],
dai_data->rate);
return 0;
@@ -386,6 +387,7 @@
case SLIMBUS_1_RX:
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
rc = msm_dai_q6_slim_bus_hw_params(params, dai,
substream->stream);
break;
@@ -898,13 +900,16 @@
rx_slot[i]);
}
dai_data->port_config.slim_sch.num_channels = rx_num;
- pr_debug("%s:SLIMBUS_0_RX cnt[%d] ch[%d %d]\n", __func__,
+ pr_debug("%s:SLIMBUS_%d_RX cnt[%d] ch[%d %d]\n", __func__,
+ (dai->id - SLIMBUS_0_RX) / 2,
rx_num, dai_data->port_config.slim_sch.slave_ch_mapping[0],
dai_data->port_config.slim_sch.slave_ch_mapping[1]);
break;
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
+
/* channel number to be between 128 and 255. For RX port
* use channel numbers from 138 to 144, for TX port
* use channel numbers from 128 to 137
@@ -919,7 +924,8 @@
__func__, i, tx_slot[i]);
}
dai_data->port_config.slim_sch.num_channels = tx_num;
- pr_debug("%s:SLIMBUS_0_TX cnt[%d] ch[%d %d]\n", __func__,
+ pr_debug("%s:SLIMBUS_%d_TX cnt[%d] ch[%d %d]\n", __func__,
+ (dai->id - SLIMBUS_0_TX) / 2,
tx_num, dai_data->port_config.slim_sch.slave_ch_mapping[0],
dai_data->port_config.slim_sch.slave_ch_mapping[1]);
break;
@@ -1195,6 +1201,22 @@
.remove = msm_dai_q6_dai_remove,
};
+static struct snd_soc_dai_driver msm_dai_q6_slimbus_2_tx_dai = {
+ .capture = {
+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
+ SNDRV_PCM_RATE_192000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 4,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
+
/* To do: change to register DAIs as batch */
static __devinit int msm_dai_q6_dev_probe(struct platform_device *pdev)
{
@@ -1230,7 +1252,6 @@
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_tx_dai);
break;
-
case SLIMBUS_1_RX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_rx_dai);
@@ -1239,6 +1260,10 @@
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_tx_dai);
break;
+ case SLIMBUS_2_TX:
+ rc = snd_soc_register_dai(&pdev->dev,
+ &msm_dai_q6_slimbus_2_tx_dai);
+ break;
case INT_BT_SCO_RX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_bt_sco_rx_dai);
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 9f70ee2..c014ea1 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -679,10 +679,13 @@
int ret = 0;
unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
+ unsigned int user_set_tx_ch = 0;
- pr_debug("%s: ch=%d\n", __func__,
- msm8960_slim_0_rx_ch);
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+
+ pr_debug("%s: rx_0_ch=%d\n", __func__, msm8960_slim_0_rx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
@@ -704,6 +707,15 @@
goto end;
}
} else {
+
+ if (codec_dai->id == 2)
+ user_set_tx_ch = msm8960_slim_0_tx_ch;
+ else if (codec_dai->id == 4)
+ user_set_tx_ch = params_channels(params);
+
+ pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
+ codec_dai->name, codec_dai->id, user_set_tx_ch);
+
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt , rx_ch);
if (ret < 0) {
@@ -711,13 +723,13 @@
goto end;
}
ret = snd_soc_dai_set_channel_map(cpu_dai,
- msm8960_slim_0_tx_ch, tx_ch, 0 , 0);
+ user_set_tx_ch, tx_ch, 0 , 0);
if (ret < 0) {
pr_err("%s: failed to set cpu chan map\n", __func__);
goto end;
}
ret = snd_soc_dai_set_channel_map(codec_dai,
- msm8960_slim_0_tx_ch, tx_ch, 0, 0);
+ user_set_tx_ch, tx_ch, 0, 0);
if (ret < 0) {
pr_err("%s: failed to set codec channel map\n",
__func__);
@@ -1327,6 +1339,16 @@
.be_hw_params_fixup = msm8960_slim_0_tx_be_hw_params_fixup,
.ops = &msm8960_be_ops,
},
+ {
+ .name = "SLIMBUS_2 Hostless",
+ .stream_name = "SLIMBUS_2 Hostless",
+ .cpu_dai_name = "msm-dai-q6.16389",
+ .platform_name = "msm-pcm-hostless",
+ .codec_name = "tabla1x_codec",
+ .codec_dai_name = "tabla_tx2",
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ops = &msm8960_be_ops,
+ },
};
@@ -1357,6 +1379,16 @@
.be_hw_params_fixup = msm8960_slim_0_tx_be_hw_params_fixup,
.ops = &msm8960_be_ops,
},
+ {
+ .name = "SLIMBUS_2 Hostless",
+ .stream_name = "SLIMBUS_2 Hostless",
+ .cpu_dai_name = "msm-dai-q6.16389",
+ .platform_name = "msm-pcm-hostless",
+ .codec_name = "tabla_codec",
+ .codec_dai_name = "tabla_tx2",
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ops = &msm8960_be_ops,
+ },
};
static struct snd_soc_dai_link msm8960_tabla1x_dai[
diff --git a/sound/soc/msm/qdsp6/q6afe.c b/sound/soc/msm/qdsp6/q6afe.c
index 535f39b..f474542 100644
--- a/sound/soc/msm/qdsp6/q6afe.c
+++ b/sound/soc/msm/qdsp6/q6afe.c
@@ -163,6 +163,7 @@
case VOICE_RECORD_TX:
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
case INT_FM_TX:
case VOICE_RECORD_RX:
case INT_BT_SCO_TX:
@@ -202,6 +203,7 @@
case SLIMBUS_0_TX:
case SLIMBUS_1_RX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
case INT_BT_SCO_RX:
case INT_BT_SCO_TX:
case INT_BT_A2DP_RX:
@@ -264,6 +266,7 @@
case SLIMBUS_0_TX: return IDX_SLIMBUS_0_TX;
case SLIMBUS_1_RX: return IDX_SLIMBUS_1_RX;
case SLIMBUS_1_TX: return IDX_SLIMBUS_1_TX;
+ case SLIMBUS_2_TX: return IDX_SLIMBUS_2_TX;
case INT_BT_SCO_RX: return IDX_INT_BT_SCO_RX;
case INT_BT_SCO_TX: return IDX_INT_BT_SCO_TX;
case INT_BT_A2DP_RX: return IDX_INT_BT_A2DP_RX;
@@ -295,6 +298,7 @@
case SLIMBUS_0_TX:
case SLIMBUS_1_RX:
case SLIMBUS_1_TX:
+ case SLIMBUS_2_TX:
ret_size = SIZEOF_CFG_CMD(afe_port_slimbus_sch_cfg);
break;
case RT_PROXY_PORT_001_RX:
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index 04d4ca4..0068c2a 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -67,7 +67,7 @@
* It can be used to eliminate pops between different playback streams, e.g.
* between two audio tracks.
*/
-static int pmdown_time = 5000;
+static int pmdown_time;
module_param(pmdown_time, int, 0);
MODULE_PARM_DESC(pmdown_time, "DAPM stream powerdown time (msecs)");