msm: clock: Move to per-clock voltage class support in the top-level driver
Generalize the voltage voting logic so that it lives in the
top-level clock.c driver. This has a couple of advantages:
- Voltage voting is no longer restricted to clock-local drivers
and need not be duplicated for different driver types.
- Different clocks may specify requirements on different power rails
by using different voltage_class implementations.
- Fmax data (maximum frequency allowed at a given voltage level)
is separated from the frequency tables and captured as a
property of each clock, so that difference SoCs may share the
same frequency tables even if their voltage requirements differ.
- The per-clock lock can be managed entirely at the clock.c level
Change-Id: I2bbd16096c14cedefa2b7fdf77d9f20d842b1e4d
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index e20936f..c4d229d 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -137,36 +137,71 @@
/*
* Clock frequency definitions and macros
*/
-#define F_BASIC(f, s, div, v) \
+#define F_BASIC(f, s, div) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = SDIV(SRC_SEL_##s, div), \
- .sys_vdd = v, \
}
-#define F_MND16(f, s, div, m, n, v) \
+#define F_MND16(f, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-#define F_MND8(f, nmsb, nlsb, s, div, m, n, v) \
+#define F_MND8(f, nmsb, nlsb, s, div, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(m, n), \
.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_ops clk_ops_rcg_7x30;
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ int rc, target_mv;
+
+ static const int mv[] = {
+ [VDD_DIG_NONE] = 1000,
+ [VDD_DIG_LOW] = 1000,
+ [VDD_DIG_NOMINAL] = 1100,
+ [VDD_DIG_HIGH] = 1200
+ };
+
+ target_mv = mv[level];
+ rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
+ if (rc)
+ return rc;
+ if (target_mv)
+ rc = -EINVAL;
+
+ return rc;
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+
#define PCOM_XO_DISABLE 0
#define PCOM_XO_ENABLE 1
#define PCOM_XO_TCXO 0
@@ -290,7 +325,7 @@
static struct clk_ops clk_ops_branch;
static struct clk_freq_tbl clk_tbl_axi[] = {
- F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -308,6 +343,7 @@
.c = {
.dbg_name = "glbl_root_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1),
CLK_INIT(glbl_root_clk.c),
},
};
@@ -948,10 +984,10 @@
};
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(153600000, 24, 17, pll1, 2, 2, 5, NOMINAL),
- F_MND8(192000000, 24, 17, pll1, 4, 0, 0, NOMINAL),
- F_MND8(384000000, 24, 17, pll1, 2, 0, 0, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(153600000, 24, 17, pll1, 2, 2, 5),
+ F_MND8(192000000, 24, 17, pll1, 4, 0, 0),
+ F_MND8(384000000, 24, 17, pll1, 2, 0, 0),
F_END,
};
@@ -973,12 +1009,13 @@
.c = {
.dbg_name = "csi0_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 384000000),
CLK_INIT(csi0_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_tcxo[] = {
- F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+ F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NULL),
F_END,
};
@@ -997,6 +1034,7 @@
.c = {
.dbg_name = "i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_clk.c),
},
};
@@ -1016,6 +1054,7 @@
.c = {
.dbg_name = "i2c_2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_2_clk.c),
},
};
@@ -1035,6 +1074,7 @@
.c = {
.dbg_name = "qup_i2c_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(qup_i2c_clk.c),
},
};
@@ -1054,6 +1094,7 @@
.c = {
.dbg_name = "uart1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart1_clk.c),
},
};
@@ -1073,23 +1114,24 @@
.c = {
.dbg_name = "uart2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart2_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_uartdm[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 3686400, pll3, 3, 3, 200, NOMINAL),
- F_MND16( 7372800, pll3, 3, 3, 100, NOMINAL),
- F_MND16(14745600, pll3, 3, 3, 50, NOMINAL),
- F_MND16(32000000, pll3, 3, 25, 192, NOMINAL),
- F_MND16(40000000, pll3, 3, 125, 768, NOMINAL),
- F_MND16(46400000, pll3, 3, 145, 768, NOMINAL),
- F_MND16(48000000, pll3, 3, 25, 128, NOMINAL),
- F_MND16(51200000, pll3, 3, 5, 24, NOMINAL),
- F_MND16(56000000, pll3, 3, 175, 768, NOMINAL),
- F_MND16(58982400, pll3, 3, 6, 25, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 3686400, pll3, 3, 3, 200),
+ F_MND16( 7372800, pll3, 3, 3, 100),
+ F_MND16(14745600, pll3, 3, 3, 50),
+ F_MND16(32000000, pll3, 3, 25, 192),
+ F_MND16(40000000, pll3, 3, 125, 768),
+ F_MND16(46400000, pll3, 3, 145, 768),
+ F_MND16(48000000, pll3, 3, 25, 128),
+ F_MND16(51200000, pll3, 3, 5, 24),
+ F_MND16(56000000, pll3, 3, 175, 768),
+ F_MND16(58982400, pll3, 3, 6, 25),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -1111,6 +1153,7 @@
.c = {
.dbg_name = "uart1dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart1dm_clk.c),
},
};
@@ -1133,20 +1176,21 @@
.c = {
.dbg_name = "uart2dm_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart2dm_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdh[] = {
- F_BASIC( 0, gnd, 1, NONE),
- F_BASIC( 49150000, pll3, 15, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, NOMINAL),
- F_BASIC(368640000, pll3, 2, NOMINAL),
- F_BASIC(384000000, pll1, 2, NOMINAL),
- F_BASIC(445500000, pll4, 2, NOMINAL),
+ F_BASIC( 0, gnd, 1),
+ F_BASIC( 49150000, pll3, 15),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(245760000, pll3, 3),
+ F_BASIC(368640000, pll3, 2),
+ F_BASIC(384000000, pll1, 2),
+ F_BASIC(445500000, pll4, 2),
F_END,
};
@@ -1166,6 +1210,7 @@
.dbg_name = "emdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(emdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1187,30 +1232,31 @@
.dbg_name = "pmdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(pmdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_grp[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52662875, pll3, 14, NOMINAL),
- F_BASIC( 56713846, pll3, 13, NOMINAL),
- F_BASIC( 61440000, pll3, 12, NOMINAL),
- F_BASIC( 67025454, pll3, 11, NOMINAL),
- F_BASIC( 73728000, pll3, 10, NOMINAL),
- F_BASIC( 81920000, pll3, 9, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(105325714, pll3, 7, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(184320000, pll3, 4, NOMINAL),
- F_BASIC(192000000, pll1, 4, NOMINAL),
- F_BASIC(245760000, pll3, 3, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52662875, pll3, 14),
+ F_BASIC( 56713846, pll3, 13),
+ F_BASIC( 61440000, pll3, 12),
+ F_BASIC( 67025454, pll3, 11),
+ F_BASIC( 73728000, pll3, 10),
+ F_BASIC( 81920000, pll3, 9),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(105325714, pll3, 7),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(184320000, pll3, 4),
+ F_BASIC(192000000, pll1, 4),
+ F_BASIC(245760000, pll3, 3),
/* Sync to AXI. Hence this "rate" is not fixed. */
- F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NOMINAL, NULL),
+ F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NULL),
F_END,
};
@@ -1231,6 +1277,7 @@
.c = {
.dbg_name = "grp_2d_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_2d_clk.c),
.depends = &axi_grp_2d_clk.c,
},
@@ -1250,6 +1297,7 @@
.c = {
.dbg_name = "grp_3d_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_3d_src_clk.c),
.depends = &axi_li_grp_clk.c,
},
@@ -1288,14 +1336,14 @@
};
static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 19, 12, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 19, 12, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 19, 12, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 19, 12, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 19, 12, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 19, 12, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 19, 12, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 19, 12, lpxo, 1, 1, 171),
+ F_MND8( 400000, 19, 12, lpxo, 1, 2, 123),
+ F_MND8(16027000, 19, 12, pll3, 3, 14, 215),
+ F_MND8(17000000, 19, 12, pll3, 4, 19, 206),
+ F_MND8(20480000, 19, 12, pll3, 4, 23, 212),
+ F_MND8(24576000, 19, 12, lpxo, 1, 0, 0),
+ F_MND8(49152000, 19, 12, pll3, 3, 1, 5),
F_END,
};
@@ -1317,6 +1365,7 @@
.c = {
.dbg_name = "sdc1_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc1_clk.c),
},
};
@@ -1339,19 +1388,20 @@
.c = {
.dbg_name = "sdc3_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc3_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 144000, 20, 13, lpxo, 1, 1, 171, NOMINAL),
- F_MND8( 400000, 20, 13, lpxo, 1, 2, 123, NOMINAL),
- F_MND8(16027000, 20, 13, pll3, 3, 14, 215, NOMINAL),
- F_MND8(17000000, 20, 13, pll3, 4, 19, 206, NOMINAL),
- F_MND8(20480000, 20, 13, pll3, 4, 23, 212, NOMINAL),
- F_MND8(24576000, 20, 13, lpxo, 1, 0, 0, NOMINAL),
- F_MND8(49152000, 20, 13, pll3, 3, 1, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 144000, 20, 13, lpxo, 1, 1, 171),
+ F_MND8( 400000, 20, 13, lpxo, 1, 2, 123),
+ F_MND8(16027000, 20, 13, pll3, 3, 14, 215),
+ F_MND8(17000000, 20, 13, pll3, 4, 19, 206),
+ F_MND8(20480000, 20, 13, pll3, 4, 23, 212),
+ F_MND8(24576000, 20, 13, lpxo, 1, 0, 0),
+ F_MND8(49152000, 20, 13, pll3, 3, 1, 5),
F_END,
};
@@ -1373,6 +1423,7 @@
.c = {
.dbg_name = "sdc2_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc2_clk.c),
},
};
@@ -1395,20 +1446,21 @@
.c = {
.dbg_name = "sdc4_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc4_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdp_core[] = {
- F_BASIC( 24576000, lpxo, 1, NOMINAL),
- F_BASIC( 46080000, pll3, 16, NOMINAL),
- F_BASIC( 49152000, pll3, 15, NOMINAL),
- F_BASIC( 52663000, pll3, 14, NOMINAL),
- F_BASIC( 92160000, pll3, 8, NOMINAL),
- F_BASIC(122880000, pll3, 6, NOMINAL),
- F_BASIC(147456000, pll3, 5, NOMINAL),
- F_BASIC(153600000, pll1, 5, NOMINAL),
- F_BASIC(192000000, pll1, 4, HIGH),
+ F_BASIC( 24576000, lpxo, 1),
+ F_BASIC( 46080000, pll3, 16),
+ F_BASIC( 49152000, pll3, 15),
+ F_BASIC( 52663000, pll3, 14),
+ F_BASIC( 92160000, pll3, 8),
+ F_BASIC(122880000, pll3, 6),
+ F_BASIC(147456000, pll3, 5),
+ F_BASIC(153600000, pll1, 5),
+ F_BASIC(192000000, pll1, 4),
F_END,
};
@@ -1429,18 +1481,19 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(mdp_clk.c),
.depends = &axi_mdp_clk.c,
},
};
static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16(30720000, pll3, 4, 1, 6, NOMINAL),
- F_MND16(32768000, pll3, 3, 2, 15, NOMINAL),
- F_MND16(40960000, pll3, 2, 1, 9, NOMINAL),
- F_MND16(73728000, pll3, 2, 1, 5, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(24576000, lpxo, 1, 0, 0),
+ F_MND16(30720000, pll3, 4, 1, 6),
+ F_MND16(32768000, pll3, 3, 2, 15),
+ F_MND16(40960000, pll3, 2, 1, 9),
+ F_MND16(73728000, pll3, 2, 1, 5),
F_END,
};
@@ -1462,6 +1515,7 @@
.c = {
.dbg_name = "mdp_lcdc_pclk_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 73728000),
CLK_INIT(mdp_lcdc_pclk_clk.c),
},
};
@@ -1483,8 +1537,8 @@
};
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NONE, NULL),
- F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NOMINAL, NULL),
+ F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, 0, NULL),
+ F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NULL),
F_END,
};
@@ -1504,14 +1558,15 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 24576000),
CLK_INIT(mdp_vsync_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 2048000, lpxo, 4, 1, 3, NOMINAL),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 2048000, lpxo, 4, 1, 3),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1533,6 +1588,7 @@
.c = {
.dbg_name = "mi2s_codec_rx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_rx_m_clk.c),
},
};
@@ -1571,6 +1627,7 @@
.c = {
.dbg_name = "mi2s_codec_tx_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_tx_m_clk.c),
},
};
@@ -1592,8 +1649,8 @@
};
static struct clk_freq_tbl clk_tbl_mi2s[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16(12288000, lpxo, 2, 0, 0, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16(12288000, lpxo, 2, 0, 0),
F_END,
};
@@ -1615,6 +1672,7 @@
.c = {
.dbg_name = "mi2s_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_m_clk.c),
},
};
@@ -1636,8 +1694,8 @@
};
static struct clk_freq_tbl clk_tbl_midi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(98304000, 19, 12, pll3, 3, 2, 5, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(98304000, 19, 12, pll3, 3, 2, 5),
F_END,
};
@@ -1658,30 +1716,30 @@
.c = {
.dbg_name = "midi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 98304000),
CLK_INIT(midi_clk.c),
},
};
-#define F_SDAC(f, s, div, m, n, v) \
+#define F_SDAC(f, s, div, m, n) \
{ \
.freq_hz = f, \
.md_val = MD16(m, n), \
.ns_val = N16(m, n) | SPDIV(SRC_SEL_SDAC_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
.src_clk = &s##_clk.c, \
}
static struct clk_freq_tbl clk_tbl_sdac[] = {
- F_SDAC( 256000, lpxo, 4, 1, 24, NOMINAL),
- F_SDAC( 352800, lpxo, 1, 147, 10240, NOMINAL),
- F_SDAC( 384000, lpxo, 4, 1, 16, NOMINAL),
- F_SDAC( 512000, lpxo, 4, 1, 12, NOMINAL),
- F_SDAC( 705600, lpxo, 1, 147, 5120, NOMINAL),
- F_SDAC( 768000, lpxo, 4, 1, 8, NOMINAL),
- F_SDAC(1024000, lpxo, 4, 1, 6, NOMINAL),
- F_SDAC(1411200, lpxo, 1, 147, 2560, NOMINAL),
- F_SDAC(1536000, lpxo, 4, 1, 4, NOMINAL),
+ F_SDAC( 256000, lpxo, 4, 1, 24),
+ F_SDAC( 352800, lpxo, 1, 147, 10240),
+ F_SDAC( 384000, lpxo, 4, 1, 16),
+ F_SDAC( 512000, lpxo, 4, 1, 12),
+ F_SDAC( 705600, lpxo, 1, 147, 5120),
+ F_SDAC( 768000, lpxo, 4, 1, 8),
+ F_SDAC(1024000, lpxo, 4, 1, 6),
+ F_SDAC(1411200, lpxo, 1, 147, 2560),
+ F_SDAC(1536000, lpxo, 4, 1, 4),
F_END,
};
@@ -1703,6 +1761,7 @@
.c = {
.dbg_name = "sdac_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 1536000),
CLK_INIT(sdac_clk.c),
},
};
@@ -1724,9 +1783,9 @@
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(27000000, 23, 16, pll4, 2, 2, 33, NOMINAL),
- F_MND8(74250000, 23, 16, pll4, 2, 1, 6, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(27000000, 23, 16, pll4, 2, 2, 33),
+ F_MND8(74250000, 23, 16, pll4, 2, 1, 6),
F_END,
};
@@ -1745,6 +1804,7 @@
.c = {
.dbg_name = "tv_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 74250000),
CLK_INIT(tv_clk.c),
},
};
@@ -1815,8 +1875,8 @@
};
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8(60000000, 23, 16, pll1, 2, 5, 32, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8(60000000, 23, 16, pll1, 2, 5, 32),
F_END,
};
@@ -1835,6 +1895,7 @@
.c = {
.dbg_name = "usb_hs_src_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs_src_clk.c),
.depends = &axi_li_adsp_a_clk.c,
},
@@ -1936,19 +1997,19 @@
};
static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
- F_MND16( 24576000, lpxo, 1, 0, 0, NOMINAL),
- F_MND16( 36864000, pll3, 4, 1, 5, NOMINAL),
- F_MND16( 46080000, pll3, 4, 1, 4, NOMINAL),
- F_MND16( 61440000, pll3, 4, 1, 3, NOMINAL),
- F_MND16( 73728000, pll3, 2, 1, 5, NOMINAL),
- F_MND16( 81920000, pll3, 3, 1, 3, NOMINAL),
- F_MND16( 92160000, pll3, 4, 1, 2, NOMINAL),
- F_MND16( 98304000, pll3, 3, 2, 5, NOMINAL),
- F_MND16(105326000, pll3, 2, 2, 7, NOMINAL),
- F_MND16(122880000, pll3, 2, 1, 3, NOMINAL),
- F_MND16(147456000, pll3, 2, 2, 5, NOMINAL),
- F_MND16(153600000, pll1, 2, 2, 5, NOMINAL),
- F_MND16(192000000, pll1, 4, 0, 0, HIGH),
+ F_MND16( 24576000, lpxo, 1, 0, 0),
+ F_MND16( 36864000, pll3, 4, 1, 5),
+ F_MND16( 46080000, pll3, 4, 1, 4),
+ F_MND16( 61440000, pll3, 4, 1, 3),
+ F_MND16( 73728000, pll3, 2, 1, 5),
+ F_MND16( 81920000, pll3, 3, 1, 3),
+ F_MND16( 92160000, pll3, 4, 1, 2),
+ F_MND16( 98304000, pll3, 3, 2, 5),
+ F_MND16(105326000, pll3, 2, 2, 7),
+ F_MND16(122880000, pll3, 2, 1, 3),
+ F_MND16(147456000, pll3, 2, 2, 5),
+ F_MND16(153600000, pll1, 2, 2, 5),
+ F_MND16(192000000, pll1, 4, 0, 0),
F_END,
};
@@ -1970,6 +2031,7 @@
.c = {
.dbg_name = "jpeg_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(jpeg_clk.c),
.depends = &axi_li_jpeg_clk.c,
},
@@ -1993,6 +2055,7 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(vfe_clk.c),
.depends = &axi_li_vfe_clk.c,
},
@@ -2047,16 +2110,16 @@
};
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_MND16( 0, gnd, 1, 0, 0, NONE),
- F_MND16( 6000000, pll1, 4, 1, 32, NOMINAL),
- F_MND16( 8000000, pll1, 4, 1, 24, NOMINAL),
- F_MND16(12000000, pll1, 4, 1, 16, NOMINAL),
- F_MND16(16000000, pll1, 4, 1, 12, NOMINAL),
- F_MND16(19200000, pll1, 4, 1, 10, NOMINAL),
- F_MND16(24000000, pll1, 4, 1, 8, NOMINAL),
- F_MND16(32000000, pll1, 4, 1, 6, NOMINAL),
- F_MND16(48000000, pll1, 4, 1, 4, NOMINAL),
- F_MND16(64000000, pll1, 4, 1, 3, NOMINAL),
+ F_MND16( 0, gnd, 1, 0, 0),
+ F_MND16( 6000000, pll1, 4, 1, 32),
+ F_MND16( 8000000, pll1, 4, 1, 24),
+ F_MND16(12000000, pll1, 4, 1, 16),
+ F_MND16(16000000, pll1, 4, 1, 12),
+ F_MND16(19200000, pll1, 4, 1, 10),
+ F_MND16(24000000, pll1, 4, 1, 8),
+ F_MND16(32000000, pll1, 4, 1, 6),
+ F_MND16(48000000, pll1, 4, 1, 4),
+ F_MND16(64000000, pll1, 4, 1, 3),
F_END,
};
@@ -2076,18 +2139,19 @@
.c = {
.dbg_name = "cam_m_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(cam_m_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 22, 15, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 22, 15, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 22, 15, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 22, 15, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 22, 15, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 22, 15, pll1, 1, 1, 5, NOMINAL),
+ F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 22, 15, pll3, 4, 1, 6),
+ F_MND8( 61440000, 22, 15, pll3, 4, 1, 3),
+ F_MND8( 81920000, 22, 15, pll3, 3, 1, 3),
+ F_MND8(122880000, 22, 15, pll3, 3, 1, 2),
+ F_MND8(147456000, 22, 15, pll3, 1, 1, 5),
+ F_MND8(153600000, 22, 15, pll1, 1, 1, 5),
F_END,
};
@@ -2109,21 +2173,21 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 153600000),
CLK_INIT(vpe_clk.c),
.depends = &axi_vpe_clk.c,
},
};
-
static struct clk_freq_tbl clk_tbl_mfc[] = {
- F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0, NOMINAL),
- F_MND8( 30720000, 24, 17, pll3, 4, 1, 6, NOMINAL),
- F_MND8( 61440000, 24, 17, pll3, 4, 1, 3, NOMINAL),
- F_MND8( 81920000, 24, 17, pll3, 3, 1, 3, NOMINAL),
- F_MND8(122880000, 24, 17, pll3, 3, 1, 2, NOMINAL),
- F_MND8(147456000, 24, 17, pll3, 1, 1, 5, NOMINAL),
- F_MND8(153600000, 24, 17, pll1, 1, 1, 5, NOMINAL),
- F_MND8(170667000, 24, 17, pll1, 1, 2, 9, NOMINAL),
+ F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0),
+ F_MND8( 30720000, 24, 17, pll3, 4, 1, 6),
+ F_MND8( 61440000, 24, 17, pll3, 4, 1, 3),
+ F_MND8( 81920000, 24, 17, pll3, 3, 1, 3),
+ F_MND8(122880000, 24, 17, pll3, 3, 1, 2),
+ F_MND8(147456000, 24, 17, pll3, 1, 1, 5),
+ F_MND8(153600000, 24, 17, pll1, 1, 1, 5),
+ F_MND8(170667000, 24, 17, pll1, 1, 2, 9),
F_END,
};
@@ -2145,6 +2209,7 @@
.c = {
.dbg_name = "mfc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 170667000),
CLK_INIT(mfc_clk.c),
.depends = &axi_mfc_clk.c,
},
@@ -2167,9 +2232,9 @@
};
static struct clk_freq_tbl clk_tbl_spi[] = {
- F_MND8( 0, 0, 0, gnd, 1, 0, 0, NONE),
- F_MND8( 9963243, 19, 12, pll3, 4, 2, 37, NOMINAL),
- F_MND8(26331429, 19, 12, pll3, 4, 1, 7, NOMINAL),
+ F_MND8( 0, 0, 0, gnd, 1, 0, 0),
+ F_MND8( 9963243, 19, 12, pll3, 4, 2, 37),
+ F_MND8(26331429, 19, 12, pll3, 4, 1, 7),
F_END,
};
@@ -2191,15 +2256,16 @@
.c = {
.dbg_name = "spi_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 26331429),
CLK_INIT(spi_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL), /* src MI2S_CODEC_RX */
- F_RAW(2, NULL, 0, 1, 0, 0, LOW, NULL), /* src ECODEC_CIF */
- F_RAW(3, NULL, 0, 2, 0, 0, LOW, NULL), /* src MI2S */
- F_RAW(4, NULL, 0, 3, 0, 0, LOW, NULL), /* src SDAC */
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL), /* src MI2S_CODEC_RX */
+ F_RAW(2, NULL, 0, 1, 0, 0, NULL), /* src ECODEC_CIF */
+ F_RAW(3, NULL, 0, 2, 0, 0, NULL), /* src MI2S */
+ F_RAW(4, NULL, 0, 3, 0, 0, NULL), /* src SDAC */
F_END,
};
@@ -2219,12 +2285,13 @@
.c = {
.dbg_name = "lpa_codec_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 4),
CLK_INIT(lpa_codec_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_mdc[] = {
- F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL),
+ F_RAW(1, NULL, 0, 0, 0, 0, NULL),
F_END
};
@@ -2244,6 +2311,7 @@
.c = {
.dbg_name = "mdc_clk",
.ops = &clk_ops_rcg_7x30,
+ VDD_DIG_FMAX_MAP1(LOW, 1),
CLK_INIT(mdc_clk.c),
},
};
@@ -2368,32 +2436,6 @@
static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_fixed_clk.c);
static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_fixed_clk.c);
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm7x30_update_sys_vdd(enum sys_vdd_level level)
-{
- int rc, target_mv;
- static const int mv[NUM_SYS_VDD_LEVELS] = {
- [NONE...LOW] = 1000,
- [NOMINAL] = 1100,
- [HIGH] = 1200,
- };
-
- target_mv = mv[level];
- rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
- if (rc)
- goto out;
- if (target_mv) {
- rc = -EINVAL;
- goto out;
- }
-out:
- return rc;
-}
-
#ifdef CONFIG_DEBUG_FS
#define CLK_TEST_2(s) (s)
@@ -2947,8 +2989,6 @@
print_ownership();
set_clock_ownership();
- soc_update_sys_vdd = msm7x30_update_sys_vdd;
-
/* When we have no local clock control, the rest of the code in this
* function is a NOP since writes to shadow regions that we don't own
* are ignored. */
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 0a7f66c..2cc1c5f 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -426,6 +426,41 @@
};
#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 0,
+ [VDD_DIG_LOW] = 945000,
+ [VDD_DIG_NOMINAL] = 1050000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
+ vdd_uv[level], 1150000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
/*
* Clock Descriptions
*/
@@ -556,24 +591,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8960_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 0,
- [LOW] = 945000,
- [NOMINAL] = 1050000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -1187,34 +1204,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1251,29 +1268,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1290,17 +1307,16 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_QDSS(f, s, d, v) \
+#define F_QDSS(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_qdss[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(128000000, pll8, 3, LOW),
- F_QDSS(300000000, pll3, 4, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(128000000, pll8, 3),
+ F_QDSS(300000000, pll3, 4),
F_END
};
@@ -1460,6 +1476,7 @@
.c = {
.dbg_name = "qdss_at_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_at_clk.c),
},
};
@@ -1506,14 +1523,15 @@
.c = {
.dbg_name = "qdss_traceclkin_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
CLK_INIT(qdss_traceclkin_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
- F_QDSS( 27000000, pxo, 1, LOW),
- F_QDSS(200000000, pll3, 6, LOW),
- F_QDSS(400000000, pll3, 3, NOMINAL),
+ F_QDSS( 27000000, pxo, 1),
+ F_QDSS(200000000, pll3, 6),
+ F_QDSS(400000000, pll3, 3),
F_END
};
@@ -1541,6 +1559,7 @@
.c = {
.dbg_name = "qdss_tsctr_clk",
.ops = &clk_ops_qdss,
+ VDD_DIG_FMAX_MAP2(LOW, 200000000, NOMINAL, 400000000),
CLK_INIT(qdss_tsctr_clk.c),
},
};
@@ -1562,16 +1581,15 @@
},
};
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1593,6 +1611,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1611,14 +1630,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1636,11 +1654,12 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
-#define CLK_SDC(name, n, h_b, f_table) \
+#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
struct rcg_clk name = { \
.b = { \
.ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
@@ -1655,85 +1674,54 @@
.root_en_mask = BIT(11), \
.ns_mask = (BM(23, 16) | BM(6, 0)), \
.set_rate = set_rate_mnd, \
- .freq_tbl = f_table, \
+ .freq_tbl = clk_tbl_sdc, \
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
+static struct clk_freq_tbl clk_tbl_sdc[] = {
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
+ F_SDC( 64000000, pll8, 3, 1, 2),
+ F_SDC( 96000000, pll8, 4, 0, 0),
F_END
};
-static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
-static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
+static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
+static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
+static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
+static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
+static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
-static struct clk_freq_tbl clk_tbl_sdc3[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, LOW),
- F_SDC( 64000000, pll8, 3, 1, 2, LOW),
- F_SDC( 96000000, pll8, 4, 0, 0, LOW),
- F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
-
-static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
- F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
- F_END
-};
-
-static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
-static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
-
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1754,20 +1742,20 @@
.c = {
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
CLK_INIT(tsif_ref_clk.c),
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1786,6 +1774,7 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
@@ -1810,22 +1799,22 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1834,8 +1823,8 @@
CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, LOW),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1856,6 +1845,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 60000000),
CLK_INIT(usb_hsic_xcvr_fs_clk.c),
},
};
@@ -1877,14 +1867,13 @@
},
};
-#define F_USB_HSIC(f, s, v) \
+#define F_USB_HSIC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
- F_USB_HSIC(480000000, pll14, LOW),
+ F_USB_HSIC(480000000, pll14),
F_END
};
@@ -1900,6 +1889,7 @@
.c = {
.dbg_name = "usb_hsic_hsic_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 480000000),
CLK_INIT(usb_hsic_hsic_src_clk.c),
},
};
@@ -1919,14 +1909,13 @@
},
};
-#define F_USB_HSIO_CAL(f, s, v) \
+#define F_USB_HSIO_CAL(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
- F_USB_HSIO_CAL(9000000, pxo, LOW),
+ F_USB_HSIO_CAL(9000000, pxo),
F_END
};
@@ -1943,6 +1932,7 @@
.c = {
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 10000000),
CLK_INIT(usb_hsic_hsio_cal_clk.c),
},
};
@@ -1959,7 +1949,7 @@
},
};
-#define CLK_USB_FS(i, n) \
+#define CLK_USB_FS(i, n, fmax_nom) \
struct rcg_clk i##_clk = { \
.ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
.b = { \
@@ -1975,11 +1965,12 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
CLK_INIT(i##_clk.c), \
}, \
}
-static CLK_USB_FS(usb_fs1_src, 1);
+static CLK_USB_FS(usb_fs1_src, 1, 64000000);
static struct branch_clk usb_fs1_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
@@ -2014,7 +2005,7 @@
},
};
-static CLK_USB_FS(usb_fs2_src, 2);
+static CLK_USB_FS(usb_fs2_src, 2, 60000000);
static struct branch_clk usb_fs2_xcvr_clk = {
.b = {
.ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
@@ -2078,18 +2069,17 @@
},
};
-#define F_CE3(f, s, d, v) \
+#define F_CE3(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ce3[] = {
- F_CE3( 0, gnd, 1, NONE),
- F_CE3( 48000000, pll8, 8, LOW),
- F_CE3(100000000, pll3, 12, NOMINAL),
+ F_CE3( 0, gnd, 1),
+ F_CE3( 48000000, pll8, 8),
+ F_CE3(100000000, pll3, 12),
F_END
};
@@ -2107,6 +2097,7 @@
.c = {
.dbg_name = "ce3_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
CLK_INIT(ce3_src_clk.c),
},
};
@@ -2681,10 +2672,11 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2692,21 +2684,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2714,7 +2705,7 @@
static CLK_CAM(cam1_clk, 1, 16);
static CLK_CAM(cam2_clk, 2, 31);
-#define F_CSI(f, s, d, m, n, v) \
+#define F_CSI(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2722,12 +2713,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, 0, 0, NONE),
- F_CSI( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI( 0, gnd, 1, 0, 0),
+ F_CSI( 85330000, pll8, 1, 2, 9),
+ F_CSI(177780000, pll2, 1, 2, 9),
F_END
};
@@ -2747,6 +2737,7 @@
.c = {
.dbg_name = "csi0_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi0_src_clk.c),
},
};
@@ -2801,6 +2792,7 @@
.c = {
.dbg_name = "csi1_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi1_src_clk.c),
},
};
@@ -2855,6 +2847,7 @@
.c = {
.dbg_name = "csi2_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi2_src_clk.c),
},
};
@@ -3076,7 +3069,7 @@
},
};
-#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
+#define F_CSI_PHYTIMER(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3084,12 +3077,11 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
- F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
- F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
- F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
+ F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
+ F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
+ F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
F_END
};
@@ -3109,6 +3101,7 @@
.c = {
.dbg_name = "csiphy_timer_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csiphy_timer_src_clk.c),
},
};
@@ -3261,7 +3254,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3269,22 +3262,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -3324,6 +3316,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -3364,11 +3358,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3376,69 +3372,80 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(300000000, pll3, 1, 4),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 300000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
/* TODO: need to add 325MHz back once it is fixed in the simulation model */
static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, LOW),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
- F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
- F_GFX3D(400000000, pll2, 1, 2, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
+static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 325000000,
+ [VDD_DIG_HIGH] = 400000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -3475,12 +3482,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_VCAP(f, s, m, n, v) \
+#define F_VCAP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3488,18 +3497,17 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcap[] = {
- F_VCAP( 0, gnd, 0, 0, NONE),
- F_VCAP( 27000000, pxo, 0, 0, LOW),
- F_VCAP( 54860000, pll8, 1, 7, LOW),
- F_VCAP( 64000000, pll8, 1, 6, LOW),
- F_VCAP( 76800000, pll8, 1, 5, LOW),
- F_VCAP(128000000, pll8, 1, 3, NOMINAL),
- F_VCAP(160000000, pll2, 1, 5, NOMINAL),
- F_VCAP(200000000, pll2, 1, 4, NOMINAL),
+ F_VCAP( 0, gnd, 0, 0),
+ F_VCAP( 27000000, pxo, 0, 0),
+ F_VCAP( 54860000, pll8, 1, 7),
+ F_VCAP( 64000000, pll8, 1, 6),
+ F_VCAP( 76800000, pll8, 1, 5),
+ F_VCAP(128000000, pll8, 1, 3),
+ F_VCAP(160000000, pll2, 1, 5),
+ F_VCAP(200000000, pll2, 1, 4),
F_END
};
@@ -3538,6 +3546,7 @@
.dbg_name = "vcap_clk",
.ops = &clk_ops_rcg_8960,
.depends = &vcap_axi_clk.c,
+ VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
CLK_INIT(vcap_clk.c),
},
};
@@ -3557,7 +3566,7 @@
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3565,37 +3574,34 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_ijpeg_8960[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_ijpeg[] = {
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
+ F_IJPEG(266667000, pll2, 1, 1, 3),
+ F_IJPEG(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_ijpeg_8064[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, LOW),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
- F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk ijpeg_clk = {
@@ -3613,30 +3619,30 @@
.ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_ijpeg_8960,
+ .freq_tbl = clk_tbl_ijpeg,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -3658,12 +3664,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3671,44 +3678,30 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_mdp_8960[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+static struct clk_freq_tbl clk_tbl_mdp[] = {
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
+ F_MDP(266667000, pll2, 1, 3),
F_END
};
-static struct clk_freq_tbl clk_tbl_mdp_8064[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, LOW),
- F_MDP(128000000, pll8, 1, 3, LOW),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
- F_MDP(266000000, pll2, 1, 3, NOMINAL),
- F_END
+static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000
};
static struct bank_masks bmnd_info_mdp = {
@@ -3741,12 +3734,13 @@
.ns_reg = MDP_NS_REG,
.root_en_mask = BIT(2),
.set_rate = set_rate_mnd_banked,
- .freq_tbl = clk_tbl_mdp_8960,
+ .freq_tbl = clk_tbl_mdp,
.bank_info = &bmnd_info_mdp,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
@@ -3767,15 +3761,14 @@
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -3796,34 +3789,34 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, LOW),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
- F_ROT(200000000, pll2, 4, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
+ F_ROT(200000000, pll2, 4),
F_END
};
@@ -3855,6 +3848,7 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
@@ -3902,7 +3896,7 @@
CLK_INIT(hdmi_pll_clk),
};
-#define F_TV_GND(f, s, p_r, d, m, n, v) \
+#define F_TV_GND(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -3910,9 +3904,8 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk, \
@@ -3920,20 +3913,24 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = (void *)p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
- F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
- F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
- F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
- F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
- F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
+ F_TV_GND( 0, gnd, 0, 1, 0, 0),
+ F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
+ F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
+ F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
+ F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
+ F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
F_END
};
+static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 74250000,
+ [VDD_DIG_NOMINAL] = 149000000
+};
+
/*
* Unlike other clocks, the TV rate is adjusted through PLL
* re-programming. It is also routed through an MND divider.
@@ -3962,6 +3959,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -4065,7 +4063,7 @@
.mode_mask = BM(12, 11),
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4073,18 +4071,17 @@
.ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
.ctl_val = CC_BANKED(6, 11, n), \
.mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -4106,28 +4103,29 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
F_END
};
@@ -4149,12 +4147,13 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -4162,50 +4161,40 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
-static struct clk_freq_tbl clk_tbl_vfe_8960[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
+static struct clk_freq_tbl clk_tbl_vfe[] = {
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
+ F_VFE(320000000, pll2, 1, 2, 5),
F_END
};
-static struct clk_freq_tbl clk_tbl_vfe_8064[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, LOW),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
- F_VFE(320000000, pll2, 1, 2, 5, HIGH),
- F_END
+static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 110000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
+};
+
+static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 266667000,
+ [VDD_DIG_HIGH] = 320000000
};
static struct rcg_clk vfe_clk = {
@@ -4223,11 +4212,12 @@
.ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
.ctl_mask = BM(7, 6),
.set_rate = set_rate_mnd,
- .freq_tbl = clk_tbl_vfe_8960,
+ .freq_tbl = clk_tbl_vfe,
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -4253,28 +4243,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4299,6 +4288,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4323,6 +4313,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -4421,28 +4412,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -4466,6 +4456,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -4490,6 +4481,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_8960,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -5740,6 +5732,14 @@
sizeof(msm_clocks_8960_v1));
if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
+ sizeof(vfe_clk.c.fmax));
+
memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
num_lookups = ARRAY_SIZE(msm_clocks_8960);
@@ -5748,20 +5748,27 @@
}
/*
- * Change the freq tables for gfx3d_clk, ijpeg_clk, mdp_clk,
- * tv_src_clk and vfe_clk at runtime and chain gmem_axi_clk
- * with gfx3d_axi_clk for 8064.
+ * Change the freq tables for and voltage requirements for
+ * clocks which differ between 8960 and 8064.
*/
if (cpu_is_apq8064()) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
- ijpeg_clk.freq_tbl = clk_tbl_ijpeg_8064;
- mdp_clk.freq_tbl = clk_tbl_mdp_8064;
- vfe_clk.freq_tbl = clk_tbl_vfe_8064;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
+ sizeof(gfx3d_clk.c.fmax));
+ memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
+ sizeof(ijpeg_clk.c.fmax));
+ memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
+ sizeof(tv_src_clk.c.fmax));
+ memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
+ sizeof(vfe_clk.c.fmax));
+
gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
}
- soc_update_sys_vdd = msm8960_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -5837,7 +5844,8 @@
rc = clk_enable(cfpb_a_clk);
if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
return rc;
- return local_unvote_sys_vdd(HIGH);
+
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8960_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 4e891d0..b11d773 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -313,6 +313,41 @@
| BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
* !!(n))
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 500000,
+ [VDD_DIG_LOW] = 1000000,
+ [VDD_DIG_NOMINAL] = 1100000,
+ [VDD_DIG_HIGH] = 1200000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], 1200000, 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2), \
+ .fmax[VDD_DIG_##l3] = (f3)
+
static struct msm_xo_voter *xo_pxo, *xo_cxo;
static bool xo_clk_is_local(struct clk *clk)
@@ -498,24 +533,6 @@
writel_relaxed(pll_mode, MM_PLL2_MODE_REG);
}
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* Update the sys_vdd voltage given a level. */
-static int msm8660_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE] = 500000,
- [LOW] = 1000000,
- [NOMINAL] = 1100000,
- [HIGH] = 1200000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -1053,34 +1070,34 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 1843200, pll8, 1, 3, 625),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -1117,29 +1134,29 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
- F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
- F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
- F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
+ F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
+ F_GSBI_QUP(10800000, pxo, 1, 2, 5),
+ F_GSBI_QUP(15060000, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(27000000, pxo, 1, 0, 0),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -1156,16 +1173,15 @@
static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(27000000, pxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(27000000, pxo, 1),
F_END
};
@@ -1187,6 +1203,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
};
@@ -1205,14 +1222,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(64000000, pll8, NOMINAL),
+ F_PRNG(64000000, pll8),
F_END
};
@@ -1230,6 +1246,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -1254,27 +1271,27 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144000, pxo, 3, 2, 125, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC(16000000, pll8, 4, 1, 6, LOW),
- F_SDC(17070000, pll8, 1, 2, 45, LOW),
- F_SDC(20210000, pll8, 1, 1, 19, LOW),
- F_SDC(24000000, pll8, 4, 1, 4, LOW),
- F_SDC(48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144000, pxo, 3, 2, 125),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC(16000000, pll8, 4, 1, 6),
+ F_SDC(17070000, pll8, 1, 2, 45),
+ F_SDC(20210000, pll8, 1, 1, 19),
+ F_SDC(24000000, pll8, 4, 1, 4),
+ F_SDC(48000000, pll8, 4, 1, 2),
F_END
};
@@ -1284,18 +1301,17 @@
static CLK_SDC(sdc4, 4, CLK_HALT_DFAB_STATE_REG, 3);
static CLK_SDC(sdc5, 5, CLK_HALT_DFAB_STATE_REG, 2);
-#define F_TSIF_REF(f, s, d, m, n, v) \
+#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
- F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
- F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
+ F_TSIF_REF( 0, gnd, 1, 0, 0),
+ F_TSIF_REF(105000, pxo, 1, 1, 256),
F_END
};
@@ -1320,16 +1336,15 @@
},
};
-#define F_TSSC(f, s, v) \
+#define F_TSSC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_tssc[] = {
- F_TSSC( 0, gnd, NONE),
- F_TSSC(27000000, pxo, LOW),
+ F_TSSC( 0, gnd),
+ F_TSSC(27000000, pxo),
F_END
};
@@ -1348,22 +1363,22 @@
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
};
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -1386,6 +1401,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -1418,6 +1434,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -2014,7 +2031,7 @@
},
};
-#define F_CAM(f, s, d, m, n, v) \
+#define F_CAM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2022,21 +2039,20 @@
.ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_cam[] = {
- F_CAM( 0, gnd, 1, 0, 0, NONE),
- F_CAM( 6000000, pll8, 4, 1, 16, LOW),
- F_CAM( 8000000, pll8, 4, 1, 12, LOW),
- F_CAM( 12000000, pll8, 4, 1, 8, LOW),
- F_CAM( 16000000, pll8, 4, 1, 6, LOW),
- F_CAM( 19200000, pll8, 4, 1, 5, LOW),
- F_CAM( 24000000, pll8, 4, 1, 4, LOW),
- F_CAM( 32000000, pll8, 4, 1, 3, LOW),
- F_CAM( 48000000, pll8, 4, 1, 2, LOW),
- F_CAM( 64000000, pll8, 3, 1, 2, LOW),
- F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
- F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
+ F_CAM( 0, gnd, 1, 0, 0),
+ F_CAM( 6000000, pll8, 4, 1, 16),
+ F_CAM( 8000000, pll8, 4, 1, 12),
+ F_CAM( 12000000, pll8, 4, 1, 8),
+ F_CAM( 16000000, pll8, 4, 1, 6),
+ F_CAM( 19200000, pll8, 4, 1, 5),
+ F_CAM( 24000000, pll8, 4, 1, 4),
+ F_CAM( 32000000, pll8, 4, 1, 3),
+ F_CAM( 48000000, pll8, 4, 1, 2),
+ F_CAM( 64000000, pll8, 3, 1, 2),
+ F_CAM( 96000000, pll8, 4, 0, 0),
+ F_CAM(128000000, pll8, 3, 0, 0),
F_END
};
@@ -2057,21 +2073,21 @@
.c = {
.dbg_name = "cam_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000),
CLK_INIT(cam_clk.c),
},
};
-#define F_CSI(f, s, d, v) \
+#define F_CSI(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_csi[] = {
- F_CSI( 0, gnd, 1, NONE),
- F_CSI(192000000, pll8, 2, LOW),
- F_CSI(384000000, pll8, 1, NOMINAL),
+ F_CSI( 0, gnd, 1),
+ F_CSI(192000000, pll8, 2),
+ F_CSI(384000000, pll8, 1),
F_END
};
@@ -2089,6 +2105,7 @@
.c = {
.dbg_name = "csi_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 192000000, NOMINAL, 384000000),
CLK_INIT(csi_src_clk.c),
},
};
@@ -2178,7 +2195,7 @@
},
};
-#define F_GFX2D(f, s, m, n, v) \
+#define F_GFX2D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2186,22 +2203,21 @@
.ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx2d[] = {
- F_GFX2D( 0, gnd, 0, 0, NONE),
- F_GFX2D( 27000000, pxo, 0, 0, LOW),
- F_GFX2D( 48000000, pll8, 1, 8, LOW),
- F_GFX2D( 54857000, pll8, 1, 7, LOW),
- F_GFX2D( 64000000, pll8, 1, 6, LOW),
- F_GFX2D( 76800000, pll8, 1, 5, LOW),
- F_GFX2D( 96000000, pll8, 1, 4, LOW),
- F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX2D(228571000, pll2, 2, 7, HIGH),
+ F_GFX2D( 0, gnd, 0, 0),
+ F_GFX2D( 27000000, pxo, 0, 0),
+ F_GFX2D( 48000000, pll8, 1, 8),
+ F_GFX2D( 54857000, pll8, 1, 7),
+ F_GFX2D( 64000000, pll8, 1, 6),
+ F_GFX2D( 76800000, pll8, 1, 5),
+ F_GFX2D( 96000000, pll8, 1, 4),
+ F_GFX2D(128000000, pll8, 1, 3),
+ F_GFX2D(145455000, pll2, 2, 11),
+ F_GFX2D(160000000, pll2, 1, 5),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -2241,6 +2257,8 @@
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -2281,11 +2299,13 @@
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
-#define F_GFX3D(f, s, m, n, v) \
+#define F_GFX3D(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2293,24 +2313,23 @@
.ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gfx3d[] = {
- F_GFX3D( 0, gnd, 0, 0, NONE),
- F_GFX3D( 27000000, pxo, 0, 0, LOW),
- F_GFX3D( 48000000, pll8, 1, 8, LOW),
- F_GFX3D( 54857000, pll8, 1, 7, LOW),
- F_GFX3D( 64000000, pll8, 1, 6, LOW),
- F_GFX3D( 76800000, pll8, 1, 5, LOW),
- F_GFX3D( 96000000, pll8, 1, 4, LOW),
- F_GFX3D(128000000, pll8, 1, 3, NOMINAL),
- F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
- F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
- F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
- F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
- F_GFX3D(228571000, pll2, 2, 7, HIGH),
- F_GFX3D(266667000, pll2, 1, 3, HIGH),
- F_GFX3D(320000000, pll2, 2, 5, HIGH),
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
F_END
};
@@ -2350,12 +2369,14 @@
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 96000000, NOMINAL, 200000000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
};
-#define F_IJPEG(f, s, d, m, n, v) \
+#define F_IJPEG(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2363,19 +2384,18 @@
.ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!n, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_ijpeg[] = {
- F_IJPEG( 0, gnd, 1, 0, 0, NONE),
- F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
- F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
- F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
- F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
- F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
- F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
- F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
- F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
- F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
+ F_IJPEG( 0, gnd, 1, 0, 0),
+ F_IJPEG( 27000000, pxo, 1, 0, 0),
+ F_IJPEG( 36570000, pll8, 1, 2, 21),
+ F_IJPEG( 54860000, pll8, 7, 0, 0),
+ F_IJPEG( 96000000, pll8, 4, 0, 0),
+ F_IJPEG(109710000, pll8, 1, 2, 7),
+ F_IJPEG(128000000, pll8, 3, 0, 0),
+ F_IJPEG(153600000, pll8, 1, 2, 5),
+ F_IJPEG(200000000, pll2, 4, 0, 0),
+ F_IJPEG(228571000, pll2, 1, 2, 7),
F_END
};
@@ -2399,25 +2419,25 @@
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 228571000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
},
};
-#define F_JPEGD(f, s, d, v) \
+#define F_JPEGD(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_jpegd[] = {
- F_JPEGD( 0, gnd, 1, NONE),
- F_JPEGD( 64000000, pll8, 6, LOW),
- F_JPEGD( 76800000, pll8, 5, LOW),
- F_JPEGD( 96000000, pll8, 4, LOW),
- F_JPEGD(160000000, pll2, 5, NOMINAL),
- F_JPEGD(200000000, pll2, 4, NOMINAL),
+ F_JPEGD( 0, gnd, 1),
+ F_JPEGD( 64000000, pll8, 6),
+ F_JPEGD( 76800000, pll8, 5),
+ F_JPEGD( 96000000, pll8, 4),
+ F_JPEGD(160000000, pll2, 5),
+ F_JPEGD(200000000, pll2, 4),
F_END
};
@@ -2439,12 +2459,13 @@
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
},
};
-#define F_MDP(f, s, m, n, v) \
+#define F_MDP(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2452,24 +2473,23 @@
.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
.ctl_val = CC_BANKED(9, 6, n), \
.mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp[] = {
- F_MDP( 0, gnd, 0, 0, NONE),
- F_MDP( 9600000, pll8, 1, 40, LOW),
- F_MDP( 13710000, pll8, 1, 28, LOW),
- F_MDP( 27000000, pxo, 0, 0, LOW),
- F_MDP( 29540000, pll8, 1, 13, LOW),
- F_MDP( 34910000, pll8, 1, 11, LOW),
- F_MDP( 38400000, pll8, 1, 10, LOW),
- F_MDP( 59080000, pll8, 2, 13, LOW),
- F_MDP( 76800000, pll8, 1, 5, LOW),
- F_MDP( 85330000, pll8, 2, 9, LOW),
- F_MDP( 96000000, pll8, 1, 4, NOMINAL),
- F_MDP(128000000, pll8, 1, 3, NOMINAL),
- F_MDP(160000000, pll2, 1, 5, NOMINAL),
- F_MDP(177780000, pll2, 2, 9, NOMINAL),
- F_MDP(200000000, pll2, 1, 4, NOMINAL),
+ F_MDP( 0, gnd, 0, 0),
+ F_MDP( 9600000, pll8, 1, 40),
+ F_MDP( 13710000, pll8, 1, 28),
+ F_MDP( 27000000, pxo, 0, 0),
+ F_MDP( 29540000, pll8, 1, 13),
+ F_MDP( 34910000, pll8, 1, 11),
+ F_MDP( 38400000, pll8, 1, 10),
+ F_MDP( 59080000, pll8, 2, 13),
+ F_MDP( 76800000, pll8, 1, 5),
+ F_MDP( 85330000, pll8, 2, 9),
+ F_MDP( 96000000, pll8, 1, 4),
+ F_MDP(128000000, pll8, 1, 3),
+ F_MDP(160000000, pll2, 1, 5),
+ F_MDP(177780000, pll2, 2, 9),
+ F_MDP(200000000, pll2, 1, 4),
F_END
};
@@ -2509,20 +2529,21 @@
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 85330000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
},
};
-#define F_MDP_VSYNC(f, s, v) \
+#define F_MDP_VSYNC(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
- F_MDP_VSYNC(27000000, pxo, LOW),
+ F_MDP_VSYNC(27000000, pxo),
F_END
};
@@ -2543,11 +2564,12 @@
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
};
-#define F_PIXEL_MDP(f, s, d, m, n, v) \
+#define F_PIXEL_MDP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2555,21 +2577,20 @@
.ns_val = NS_MM(31, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pixel_mdp[] = {
- F_PIXEL_MDP( 0, gnd, 1, 0, 0, NONE),
- F_PIXEL_MDP( 25600000, pll8, 3, 1, 5, LOW),
- F_PIXEL_MDP( 42667000, pll8, 1, 1, 9, LOW),
- F_PIXEL_MDP( 43192000, pll8, 1, 64, 569, LOW),
- F_PIXEL_MDP( 48000000, pll8, 4, 1, 2, LOW),
- F_PIXEL_MDP( 53990000, pll8, 2, 169, 601, LOW),
- F_PIXEL_MDP( 64000000, pll8, 2, 1, 3, LOW),
- F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280, LOW),
- F_PIXEL_MDP( 76800000, pll8, 1, 1, 5, LOW),
- F_PIXEL_MDP( 85333000, pll8, 1, 2, 9, LOW),
- F_PIXEL_MDP(106500000, pll8, 1, 71, 256, NOMINAL),
- F_PIXEL_MDP(109714000, pll8, 1, 2, 7, NOMINAL),
+ F_PIXEL_MDP( 0, gnd, 1, 0, 0),
+ F_PIXEL_MDP( 25600000, pll8, 3, 1, 5),
+ F_PIXEL_MDP( 42667000, pll8, 1, 1, 9),
+ F_PIXEL_MDP( 43192000, pll8, 1, 64, 569),
+ F_PIXEL_MDP( 48000000, pll8, 4, 1, 2),
+ F_PIXEL_MDP( 53990000, pll8, 2, 169, 601),
+ F_PIXEL_MDP( 64000000, pll8, 2, 1, 3),
+ F_PIXEL_MDP( 69300000, pll8, 1, 231, 1280),
+ F_PIXEL_MDP( 76800000, pll8, 1, 1, 5),
+ F_PIXEL_MDP( 85333000, pll8, 1, 2, 9),
+ F_PIXEL_MDP(106500000, pll8, 1, 71, 256),
+ F_PIXEL_MDP(109714000, pll8, 1, 2, 7),
F_END
};
@@ -2593,6 +2614,7 @@
.c = {
.dbg_name = "pixel_mdp_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 85333000, NOMINAL, 170000000),
CLK_INIT(pixel_mdp_clk.c),
},
};
@@ -2612,29 +2634,28 @@
},
};
-#define F_ROT(f, s, d, v) \
+#define F_ROT(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
21, 19, 18, 16, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_rot[] = {
- F_ROT( 0, gnd, 1, NONE),
- F_ROT( 27000000, pxo, 1, LOW),
- F_ROT( 29540000, pll8, 13, LOW),
- F_ROT( 32000000, pll8, 12, LOW),
- F_ROT( 38400000, pll8, 10, LOW),
- F_ROT( 48000000, pll8, 8, LOW),
- F_ROT( 54860000, pll8, 7, LOW),
- F_ROT( 64000000, pll8, 6, LOW),
- F_ROT( 76800000, pll8, 5, LOW),
- F_ROT( 96000000, pll8, 4, NOMINAL),
- F_ROT(100000000, pll2, 8, NOMINAL),
- F_ROT(114290000, pll2, 7, NOMINAL),
- F_ROT(133330000, pll2, 6, NOMINAL),
- F_ROT(160000000, pll2, 5, NOMINAL),
+ F_ROT( 0, gnd, 1),
+ F_ROT( 27000000, pxo, 1),
+ F_ROT( 29540000, pll8, 13),
+ F_ROT( 32000000, pll8, 12),
+ F_ROT( 38400000, pll8, 10),
+ F_ROT( 48000000, pll8, 8),
+ F_ROT( 54860000, pll8, 7),
+ F_ROT( 64000000, pll8, 6),
+ F_ROT( 76800000, pll8, 5),
+ F_ROT( 96000000, pll8, 4),
+ F_ROT(100000000, pll2, 8),
+ F_ROT(114290000, pll2, 7),
+ F_ROT(133330000, pll2, 6),
+ F_ROT(160000000, pll2, 5),
F_END
};
@@ -2666,12 +2687,13 @@
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
},
};
-#define F_TV(f, s, p_r, d, m, n, v) \
+#define F_TV(f, s, p_r, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2679,7 +2701,6 @@
.ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
.extra_freq_data = p_r, \
}
/* Switching TV freqs requires PLL reconfiguration. */
@@ -2691,12 +2712,12 @@
[4] = PLL_RATE(44, 0, 0, 2, 4, 0x6248F), /* 297000000 Hz */
};
static struct clk_freq_tbl clk_tbl_tv[] = {
- F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0, NONE),
- F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0, LOW),
- F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0, LOW),
- F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0, LOW),
- F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0, NOMINAL),
- F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0, NOMINAL),
+ F_TV( 0, gnd, &mm_pll2_rate[0], 1, 0, 0),
+ F_TV( 25200000, pll3, &mm_pll2_rate[0], 2, 0, 0),
+ F_TV( 27000000, pll3, &mm_pll2_rate[1], 2, 0, 0),
+ F_TV( 27030000, pll3, &mm_pll2_rate[2], 4, 0, 0),
+ F_TV( 74250000, pll3, &mm_pll2_rate[3], 2, 0, 0),
+ F_TV(148500000, pll3, &mm_pll2_rate[4], 2, 0, 0),
F_END
};
@@ -2716,6 +2737,7 @@
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
};
@@ -2802,7 +2824,7 @@
},
};
-#define F_VCODEC(f, s, m, n, v) \
+#define F_VCODEC(f, s, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2810,18 +2832,17 @@
.ns_val = NS_MM(18, 11, n, m, 0, 0, 1, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vcodec[] = {
- F_VCODEC( 0, gnd, 0, 0, NONE),
- F_VCODEC( 27000000, pxo, 0, 0, LOW),
- F_VCODEC( 32000000, pll8, 1, 12, LOW),
- F_VCODEC( 48000000, pll8, 1, 8, LOW),
- F_VCODEC( 54860000, pll8, 1, 7, LOW),
- F_VCODEC( 96000000, pll8, 1, 4, LOW),
- F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
- F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
- F_VCODEC(228570000, pll2, 2, 7, HIGH),
+ F_VCODEC( 0, gnd, 0, 0),
+ F_VCODEC( 27000000, pxo, 0, 0),
+ F_VCODEC( 32000000, pll8, 1, 12),
+ F_VCODEC( 48000000, pll8, 1, 8),
+ F_VCODEC( 54860000, pll8, 1, 7),
+ F_VCODEC( 96000000, pll8, 1, 4),
+ F_VCODEC(133330000, pll2, 1, 6),
+ F_VCODEC(200000000, pll2, 1, 4),
+ F_VCODEC(228570000, pll2, 2, 7),
F_END
};
@@ -2845,29 +2866,30 @@
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
.depends = &vcodec_axi_clk.c,
},
};
-#define F_VPE(f, s, d, v) \
+#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vpe[] = {
- F_VPE( 0, gnd, 1, NONE),
- F_VPE( 27000000, pxo, 1, LOW),
- F_VPE( 34909000, pll8, 11, LOW),
- F_VPE( 38400000, pll8, 10, LOW),
- F_VPE( 64000000, pll8, 6, LOW),
- F_VPE( 76800000, pll8, 5, LOW),
- F_VPE( 96000000, pll8, 4, NOMINAL),
- F_VPE(100000000, pll2, 8, NOMINAL),
- F_VPE(160000000, pll2, 5, NOMINAL),
- F_VPE(200000000, pll2, 4, HIGH),
+ F_VPE( 0, gnd, 1),
+ F_VPE( 27000000, pxo, 1),
+ F_VPE( 34909000, pll8, 11),
+ F_VPE( 38400000, pll8, 10),
+ F_VPE( 64000000, pll8, 6),
+ F_VPE( 76800000, pll8, 5),
+ F_VPE( 96000000, pll8, 4),
+ F_VPE(100000000, pll2, 8),
+ F_VPE(160000000, pll2, 5),
+ F_VPE(200000000, pll2, 4),
F_END
};
@@ -2889,12 +2911,14 @@
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 76800000, NOMINAL, 160000000,
+ HIGH, 200000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
};
-#define F_VFE(f, s, d, m, n, v) \
+#define F_VFE(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
@@ -2902,26 +2926,25 @@
.ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
.ctl_val = CC(6, n), \
.mnd_en_mask = BIT(5) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_vfe[] = {
- F_VFE( 0, gnd, 1, 0, 0, NONE),
- F_VFE( 13960000, pll8, 1, 2, 55, LOW),
- F_VFE( 27000000, pxo, 1, 0, 0, LOW),
- F_VFE( 36570000, pll8, 1, 2, 21, LOW),
- F_VFE( 38400000, pll8, 2, 1, 5, LOW),
- F_VFE( 45180000, pll8, 1, 2, 17, LOW),
- F_VFE( 48000000, pll8, 2, 1, 4, LOW),
- F_VFE( 54860000, pll8, 1, 1, 7, LOW),
- F_VFE( 64000000, pll8, 2, 1, 3, LOW),
- F_VFE( 76800000, pll8, 1, 1, 5, LOW),
- F_VFE( 96000000, pll8, 2, 1, 2, LOW),
- F_VFE(109710000, pll8, 1, 2, 7, LOW),
- F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
- F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
- F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
- F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
- F_VFE(266667000, pll2, 1, 1, 3, HIGH),
+ F_VFE( 0, gnd, 1, 0, 0),
+ F_VFE( 13960000, pll8, 1, 2, 55),
+ F_VFE( 27000000, pxo, 1, 0, 0),
+ F_VFE( 36570000, pll8, 1, 2, 21),
+ F_VFE( 38400000, pll8, 2, 1, 5),
+ F_VFE( 45180000, pll8, 1, 2, 17),
+ F_VFE( 48000000, pll8, 2, 1, 4),
+ F_VFE( 54860000, pll8, 1, 1, 7),
+ F_VFE( 64000000, pll8, 2, 1, 3),
+ F_VFE( 76800000, pll8, 1, 1, 5),
+ F_VFE( 96000000, pll8, 2, 1, 2),
+ F_VFE(109710000, pll8, 1, 2, 7),
+ F_VFE(128000000, pll8, 1, 1, 3),
+ F_VFE(153600000, pll8, 1, 2, 5),
+ F_VFE(200000000, pll2, 2, 1, 2),
+ F_VFE(228570000, pll2, 1, 2, 7),
+ F_VFE(266667000, pll2, 1, 1, 3),
F_END
};
@@ -2945,6 +2968,8 @@
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 228570000,
+ HIGH, 266667000),
CLK_INIT(vfe_clk.c),
.depends = &vfe_axi_clk.c,
},
@@ -2987,27 +3012,26 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 768000, pll4, 4, 1, 176, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 132, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 88, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 66, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 44, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 33, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 22, LOW),
- F_AIF_OSR( 8192000, pll4, 2, 1, 33, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 11, LOW),
- F_AIF_OSR(24576000, pll4, 2, 1, 11, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 768000, pll4, 4, 1, 176),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 132),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 88),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 66),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 44),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 33),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 22),
+ F_AIF_OSR( 8192000, pll4, 2, 1, 33),
+ F_AIF_OSR(12288000, pll4, 4, 1, 11),
+ F_AIF_OSR(24576000, pll4, 2, 1, 11),
F_END
};
@@ -3032,6 +3056,7 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -3094,28 +3119,27 @@
static CLK_AIF_BIT(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 264, LOW),
- F_PCM( 768000, pll4, 4, 1, 176, LOW),
- F_PCM( 1024000, pll4, 4, 1, 132, LOW),
- F_PCM( 1536000, pll4, 4, 1, 88, LOW),
- F_PCM( 2048000, pll4, 4, 1, 66, LOW),
- F_PCM( 3072000, pll4, 4, 1, 44, LOW),
- F_PCM( 4096000, pll4, 4, 1, 33, LOW),
- F_PCM( 6144000, pll4, 4, 1, 22, LOW),
- F_PCM( 8192000, pll4, 2, 1, 33, LOW),
- F_PCM(12288000, pll4, 4, 1, 11, LOW),
- F_PCM(24580000, pll4, 2, 1, 11, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 264),
+ F_PCM( 768000, pll4, 4, 1, 176),
+ F_PCM( 1024000, pll4, 4, 1, 132),
+ F_PCM( 1536000, pll4, 4, 1, 88),
+ F_PCM( 2048000, pll4, 4, 1, 66),
+ F_PCM( 3072000, pll4, 4, 1, 44),
+ F_PCM( 4096000, pll4, 4, 1, 33),
+ F_PCM( 6144000, pll4, 4, 1, 22),
+ F_PCM( 8192000, pll4, 2, 1, 33),
+ F_PCM(12288000, pll4, 4, 1, 11),
+ F_PCM(24580000, pll4, 2, 1, 11),
F_END
};
@@ -3139,6 +3163,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8x60,
+ VDD_DIG_FMAX_MAP1(LOW, 24580000),
CLK_INIT(pcm_clk.c),
},
};
@@ -3843,7 +3868,6 @@
/* Local clock driver initialization. */
static void __init msm8660_clock_init(void)
{
- soc_update_sys_vdd = msm8660_update_sys_vdd;
xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8x60");
if (IS_ERR(xo_pxo)) {
pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
@@ -3855,7 +3879,7 @@
BUG();
}
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
/* Initialize clock registers. */
reg_init();
@@ -3893,11 +3917,7 @@
if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
return rc;
- /* Remove temporary vote for HIGH vdd_dig. */
- rc = local_unvote_sys_vdd(HIGH);
- WARN(rc, "local_unvote_sys_vdd(HIGH) failed (%d)\n", rc);
-
- return rc;
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm8x60_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 306de34..734043f 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -185,6 +185,36 @@
#define NS_SRC_SEL(s_msb, s_lsb, s) \
BVAL(s_msb, s_lsb, s)
+enum vdd_dig_levels {
+ VDD_DIG_NONE,
+ VDD_DIG_LOW,
+ VDD_DIG_NOMINAL,
+ VDD_DIG_HIGH
+};
+
+static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
+{
+ /* TODO: Update these voltages when info becomes available. */
+ static const int vdd_uv[] = {
+ [VDD_DIG_NONE] = 1150000,
+ [VDD_DIG_LOW] = 1150000,
+ [VDD_DIG_NOMINAL] = 1150000,
+ [VDD_DIG_HIGH] = 1150000
+ };
+
+ return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
+ vdd_uv[level], vdd_uv[VDD_DIG_HIGH], 1);
+}
+
+static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1)
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+ .vdd_class = &vdd_dig, \
+ .fmax[VDD_DIG_##l1] = (f1), \
+ .fmax[VDD_DIG_##l2] = (f2)
/*
* Clock Descriptions
@@ -283,24 +313,6 @@
},
};
-/*
- * SoC-specific functions required by clock-local driver
- */
-
-/* TODO: Update these voltages when info becomes available. */
-/* Update the sys_vdd voltage given a level. */
-static int msm9615_update_sys_vdd(enum sys_vdd_level level)
-{
- static const int vdd_uv[] = {
- [NONE...LOW] = 1150000,
- [NOMINAL] = 1150000,
- [HIGH] = 1150000,
- };
-
- return rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER3,
- vdd_uv[level], vdd_uv[HIGH], 1);
-}
-
static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
@@ -355,33 +367,33 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_UART(f, s, d, m, n, v) \
+#define F_GSBI_UART(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
- F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
- F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
- F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
- F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
- F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
- F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
- F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
- F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
- F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
- F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
+ F_GSBI_UART( 0, gnd, 1, 0, 0),
+ F_GSBI_UART( 3686400, pll8, 1, 6, 625),
+ F_GSBI_UART( 7372800, pll8, 1, 12, 625),
+ F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART(16000000, pll8, 4, 1, 6),
+ F_GSBI_UART(24000000, pll8, 4, 1, 4),
+ F_GSBI_UART(32000000, pll8, 4, 1, 3),
+ F_GSBI_UART(40000000, pll8, 1, 5, 48),
+ F_GSBI_UART(46400000, pll8, 1, 29, 240),
+ F_GSBI_UART(48000000, pll8, 4, 1, 2),
+ F_GSBI_UART(51200000, pll8, 1, 2, 15),
+ F_GSBI_UART(56000000, pll8, 1, 7, 48),
+ F_GSBI_UART(58982400, pll8, 1, 96, 625),
+ F_GSBI_UART(64000000, pll8, 2, 1, 3),
F_END
};
@@ -411,28 +423,28 @@
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_GSBI_QUP(f, s, d, m, n, v) \
+#define F_GSBI_QUP(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
- F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
- F_GSBI_QUP( 960000, cxo, 4, 1, 5, LOW),
- F_GSBI_QUP( 4800000, cxo, 4, 0, 1, LOW),
- F_GSBI_QUP( 9600000, cxo, 2, 0, 1, LOW),
- F_GSBI_QUP(15058800, pll8, 1, 2, 51, LOW),
- F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
- F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
- F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
- F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
+ F_GSBI_QUP( 0, gnd, 1, 0, 0),
+ F_GSBI_QUP( 960000, cxo, 4, 1, 5),
+ F_GSBI_QUP( 4800000, cxo, 4, 0, 1),
+ F_GSBI_QUP( 9600000, cxo, 2, 0, 1),
+ F_GSBI_QUP(15058800, pll8, 1, 2, 51),
+ F_GSBI_QUP(24000000, pll8, 4, 1, 4),
+ F_GSBI_QUP(25600000, pll8, 1, 1, 15),
+ F_GSBI_QUP(48000000, pll8, 4, 1, 2),
+ F_GSBI_QUP(51200000, pll8, 1, 2, 15),
F_END
};
@@ -442,16 +454,15 @@
static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
-#define F_PDM(f, s, d, v) \
+#define F_PDM(f, s, d) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pdm[] = {
- F_PDM( 0, gnd, 1, NONE),
- F_PDM(19200000, cxo, 1, LOW),
+ F_PDM( 0, gnd, 1),
+ F_PDM(19200000, cxo, 1),
F_END
};
@@ -473,6 +484,7 @@
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 19200000),
CLK_INIT(pdm_clk.c),
},
};
@@ -491,14 +503,13 @@
},
};
-#define F_PRNG(f, s, v) \
+#define F_PRNG(f, s) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_prng[] = {
- F_PRNG(32000000, pll8, LOW),
+ F_PRNG(32000000, pll8),
F_END
};
@@ -516,6 +527,7 @@
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
};
@@ -540,45 +552,44 @@
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(name.c), \
}, \
}
-#define F_SDC(f, s, d, m, n, v) \
+#define F_SDC(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
- F_SDC( 0, gnd, 1, 0, 0, NONE),
- F_SDC( 144300, cxo, 1, 1, 133, LOW),
- F_SDC( 400000, pll8, 4, 1, 240, LOW),
- F_SDC( 16000000, pll8, 4, 1, 6, LOW),
- F_SDC( 17070000, pll8, 1, 2, 45, LOW),
- F_SDC( 20210000, pll8, 1, 1, 19, LOW),
- F_SDC( 24000000, pll8, 4, 1, 4, LOW),
- F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
+ F_SDC( 0, gnd, 1, 0, 0),
+ F_SDC( 144300, cxo, 1, 1, 133),
+ F_SDC( 400000, pll8, 4, 1, 240),
+ F_SDC( 16000000, pll8, 4, 1, 6),
+ F_SDC( 17070000, pll8, 1, 2, 45),
+ F_SDC( 20210000, pll8, 1, 1, 19),
+ F_SDC( 24000000, pll8, 4, 1, 4),
+ F_SDC( 48000000, pll8, 4, 1, 2),
F_END
};
static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
-#define F_USB(f, s, d, m, n, v) \
+#define F_USB(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(16, m, 0, n), \
.ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_usb[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(60000000, pll8, 1, 5, 32),
F_END
};
@@ -601,6 +612,7 @@
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
};
@@ -624,6 +636,7 @@
.c = {
.dbg_name = "usb_hs1_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_sys_clk.c),
},
};
@@ -647,6 +660,7 @@
.c = {
.dbg_name = "usb_hsic_xcvr_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_xcvr_clk.c),
},
};
@@ -670,13 +684,14 @@
.c = {
.dbg_name = "usb_hsic_sys_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hsic_sys_clk.c),
},
};
static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
- F_USB( 0, gnd, 1, 0, 0, NONE),
- F_USB(480000000, pll14, 1, 0, 1, NOMINAL),
+ F_USB( 0, gnd, 1, 0, 0),
+ F_USB(480000000, pll14, 1, 0, 1),
F_END
};
@@ -699,6 +714,7 @@
.c = {
.dbg_name = "usb_hsic_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(NOMINAL, 480000000),
CLK_INIT(usb_hsic_clk.c),
},
};
@@ -980,28 +996,27 @@
/*
* Low Power Audio Clocks
*/
-#define F_AIF_OSR(f, s, d, m, n, v) \
+#define F_AIF_OSR(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD8(8, m, 0, n), \
.ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_aif_osr[] = {
- F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
- F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
- F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
- F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
- F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
- F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
- F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
- F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
- F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
- F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
- F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
- F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
+ F_AIF_OSR( 0, gnd, 1, 0, 0),
+ F_AIF_OSR( 512000, pll4, 4, 1, 192),
+ F_AIF_OSR( 768000, pll4, 4, 1, 128),
+ F_AIF_OSR( 1024000, pll4, 4, 1, 96),
+ F_AIF_OSR( 1536000, pll4, 4, 1, 64),
+ F_AIF_OSR( 2048000, pll4, 4, 1, 48),
+ F_AIF_OSR( 3072000, pll4, 4, 1, 32),
+ F_AIF_OSR( 4096000, pll4, 4, 1, 24),
+ F_AIF_OSR( 6144000, pll4, 4, 1, 16),
+ F_AIF_OSR( 8192000, pll4, 4, 1, 12),
+ F_AIF_OSR(12288000, pll4, 4, 1, 8),
+ F_AIF_OSR(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1148,28 +1163,27 @@
static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
LCC_SPARE_I2S_SPKR_STATUS_REG);
-#define F_PCM(f, s, d, m, n, v) \
+#define F_PCM(f, s, d, m, n) \
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
.md_val = MD16(m, n), \
.ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
.mnd_en_mask = BIT(8) * !!(n), \
- .sys_vdd = v, \
}
static struct clk_freq_tbl clk_tbl_pcm[] = {
- F_PCM( 0, gnd, 1, 0, 0, NONE),
- F_PCM( 512000, pll4, 4, 1, 192, LOW),
- F_PCM( 768000, pll4, 4, 1, 128, LOW),
- F_PCM( 1024000, pll4, 4, 1, 96, LOW),
- F_PCM( 1536000, pll4, 4, 1, 64, LOW),
- F_PCM( 2048000, pll4, 4, 1, 48, LOW),
- F_PCM( 3072000, pll4, 4, 1, 32, LOW),
- F_PCM( 4096000, pll4, 4, 1, 24, LOW),
- F_PCM( 6144000, pll4, 4, 1, 16, LOW),
- F_PCM( 8192000, pll4, 4, 1, 12, LOW),
- F_PCM(12288000, pll4, 4, 1, 8, LOW),
- F_PCM(24576000, pll4, 4, 1, 4, LOW),
+ F_PCM( 0, gnd, 1, 0, 0),
+ F_PCM( 512000, pll4, 4, 1, 192),
+ F_PCM( 768000, pll4, 4, 1, 128),
+ F_PCM( 1024000, pll4, 4, 1, 96),
+ F_PCM( 1536000, pll4, 4, 1, 64),
+ F_PCM( 2048000, pll4, 4, 1, 48),
+ F_PCM( 3072000, pll4, 4, 1, 32),
+ F_PCM( 4096000, pll4, 4, 1, 24),
+ F_PCM( 6144000, pll4, 4, 1, 16),
+ F_PCM( 8192000, pll4, 4, 1, 12),
+ F_PCM(12288000, pll4, 4, 1, 8),
+ F_PCM(24576000, pll4, 4, 1, 4),
F_END
};
@@ -1193,6 +1207,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
};
@@ -1217,6 +1232,7 @@
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_9615,
+ VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
};
@@ -1717,8 +1733,7 @@
BUG();
}
- soc_update_sys_vdd = msm9615_update_sys_vdd;
- local_vote_sys_vdd(HIGH);
+ vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
clk_ops_pll.enable = sr_pll_clk_enable;
@@ -1744,7 +1759,7 @@
static int __init msm9615_clock_late_init(void)
{
- return local_unvote_sys_vdd(HIGH);
+ return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
}
struct clock_init_data msm9615_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index c0af9b5..4e0d3e9 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -170,10 +170,25 @@
static int list_rates_show(struct seq_file *m, void *unused)
{
struct clk *clock = m->private;
- int rate, i = 0;
+ int rate, level, fmax = 0, i = 0;
- while ((rate = clock->ops->list_rate(clock, i++)) >= 0)
- seq_printf(m, "%d\n", rate);
+ /* Find max frequency supported within voltage constraints. */
+ if (!clock->vdd_class) {
+ fmax = ULONG_MAX;
+ } else {
+ for (level = 0; level < ARRAY_SIZE(clock->fmax); level++)
+ if (clock->fmax[level])
+ fmax = clock->fmax[level];
+ }
+
+ /*
+ * List supported frequencies <= fmax. Higher frequencies may appear in
+ * the frequency table, but are not valid and should not be listed.
+ */
+ while ((rate = clock->ops->list_rate(clock, i++)) >= 0) {
+ if (rate <= fmax)
+ seq_printf(m, "%u\n", rate);
+ }
return 0;
}
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index ea76512..4b30896 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -48,9 +48,6 @@
DEFINE_SPINLOCK(local_clock_reg_lock);
struct clk_freq_tbl rcg_dummy_freq = F_END;
-unsigned local_sys_vdd_votes[NUM_SYS_VDD_LEVELS];
-static DEFINE_SPINLOCK(sys_vdd_vote_lock);
-
/*
* Common Set-Rate Functions
*/
@@ -264,81 +261,6 @@
clk->ns_mask = new_bank_masks->ns_mask;
}
-int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
- * SYS_VDD voting functions
- */
-
-/* Update system voltage level given the current votes. */
-static int local_update_sys_vdd(void)
-{
- static int cur_level = NUM_SYS_VDD_LEVELS;
- int level, rc = 0;
-
- if (local_sys_vdd_votes[HIGH])
- level = HIGH;
- else if (local_sys_vdd_votes[NOMINAL])
- level = NOMINAL;
- else if (local_sys_vdd_votes[LOW])
- level = LOW;
- else
- level = NONE;
-
- if (level == cur_level)
- return rc;
-
- rc = soc_update_sys_vdd(level);
- if (!rc)
- cur_level = level;
-
- return rc;
-}
-
-/* Vote for a system voltage level. */
-int local_vote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
- local_sys_vdd_votes[level]++;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]--;
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
-
- return rc;
-}
-
-/* Remove vote for a system voltage level. */
-int local_unvote_sys_vdd(unsigned level)
-{
- int rc = 0;
- unsigned long flags;
-
- /* Bounds checking. */
- if (level >= ARRAY_SIZE(local_sys_vdd_votes))
- return -EINVAL;
-
- spin_lock_irqsave(&sys_vdd_vote_lock, flags);
-
- if (WARN(!local_sys_vdd_votes[level],
- "Reference counts are incorrect for level %d!\n", level))
- goto out;
-
- local_sys_vdd_votes[level]--;
- rc = local_update_sys_vdd();
- if (rc)
- local_sys_vdd_votes[level]++;
-out:
- spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
- return rc;
-}
/*
* Clock enable/disable functions
*/
@@ -486,19 +408,25 @@
}
}
-static void _rcg_clk_enable(struct rcg_clk *clk)
+/* Enable a rate-settable clock. */
+int rcg_clk_enable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_enable_reg(clk);
clk->enabled = true;
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+ return 0;
}
-static void _rcg_clk_disable(struct rcg_clk *clk)
+/* Disable a rate-settable clock. */
+void rcg_clk_disable(struct clk *c)
{
unsigned long flags;
+ struct rcg_clk *clk = to_rcg_clk(c);
spin_lock_irqsave(&local_clock_reg_lock, flags);
__rcg_clk_disable_reg(clk);
@@ -506,32 +434,10 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-/* Enable a clock and any related power rail. */
-int rcg_clk_enable(struct clk *c)
-{
- int rc;
- struct rcg_clk *clk = to_rcg_clk(c);
-
- rc = local_vote_sys_vdd(clk->current_freq->sys_vdd);
- if (rc)
- return rc;
- _rcg_clk_enable(clk);
- return rc;
-}
-
-/* Disable a clock and any related power rail. */
-void rcg_clk_disable(struct clk *c)
-{
- struct rcg_clk *clk = to_rcg_clk(c);
-
- _rcg_clk_disable(clk);
- local_unvote_sys_vdd(clk->current_freq->sys_vdd);
-}
-
/* Turn off a clock at boot, without checking refcounts. */
void rcg_clk_auto_off(struct clk *c)
{
- _rcg_clk_disable(to_rcg_clk(c));
+ rcg_clk_disable(c);
}
/*
@@ -544,25 +450,17 @@
struct clk_freq_tbl *cf;
int rc = 0;
struct clk *chld;
- unsigned long flags;
-
- spin_lock_irqsave(&clk->c.lock, flags);
/* Check if frequency is actually changed. */
cf = clk->current_freq;
if (nf == cf)
- goto unlock;
+ return 0;
if (clk->enabled) {
- /* Vote for voltage and source for new freq. */
- rc = local_vote_sys_vdd(nf->sys_vdd);
- if (rc)
- goto unlock;
+ /* Enable source clock dependency for the new freq. */
rc = clk_enable(nf->src_clk);
- if (rc) {
- local_unvote_sys_vdd(nf->sys_vdd);
- goto unlock;
- }
+ if (rc)
+ return rc;
}
spin_lock(&local_clock_reg_lock);
@@ -608,13 +506,9 @@
spin_unlock(&local_clock_reg_lock);
- /* Release requirements of the old freq. */
- if (clk->enabled) {
+ /* Release source requirements of the old freq. */
+ if (clk->enabled)
clk_disable(cf->src_clk);
- local_unvote_sys_vdd(cf->sys_vdd);
- }
-unlock:
- spin_unlock_irqrestore(&clk->c.lock, flags);
return rc;
}
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index f62e753..873faf1 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -74,22 +74,17 @@
const struct bank_mask_info bank1_mask;
};
-#define F_RAW(f, sc, m_v, n_v, c_v, m_m, v, e) { \
+#define F_RAW(f, sc, m_v, n_v, c_v, m_m, e) { \
.freq_hz = f, \
.src_clk = sc, \
.md_val = m_v, \
.ns_val = n_v, \
.ctl_val = c_v, \
.mnd_en_mask = m_m, \
- .sys_vdd = v, \
.extra_freq_data = e, \
}
#define FREQ_END (UINT_MAX-1)
-#define F_END \
- { \
- .freq_hz = FREQ_END, \
- .sys_vdd = LOW, \
- }
+#define F_END { .freq_hz = FREQ_END }
/**
* struct branch - branch on/off
@@ -156,17 +151,6 @@
struct clk *rcg_clk_get_parent(struct clk *c);
int rcg_clk_handoff(struct clk *c);
-/*
- * SYS_VDD voltage levels
- */
-enum sys_vdd_level {
- NONE,
- LOW,
- NOMINAL,
- HIGH,
- NUM_SYS_VDD_LEVELS
-};
-
/**
* struct fixed_clk - fixed rate clock (used for crystal oscillators)
* @rate: output rate
@@ -301,16 +285,9 @@
/*
* Local-clock APIs
*/
-int local_vote_sys_vdd(enum sys_vdd_level level);
-int local_unvote_sys_vdd(enum sys_vdd_level level);
bool local_clk_is_local(struct clk *clk);
/*
- * Required SoC-specific functions, implemented for every supported SoC
- */
-extern int (*soc_update_sys_vdd)(enum sys_vdd_level level);
-
-/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 58a64a3..de89382 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -24,13 +24,116 @@
#include "clock.h"
+/* Find the voltage level required for a given rate. */
+static int find_vdd_level(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ for (level = 0; level < ARRAY_SIZE(clk->fmax); level++)
+ if (rate <= clk->fmax[level])
+ break;
+
+ if (level == ARRAY_SIZE(clk->fmax)) {
+ pr_err("Rate %lu for %s is greater than highest Fmax\n", rate,
+ clk->dbg_name);
+ return -EINVAL;
+ }
+
+ return level;
+}
+
+/* Update voltage level given the current votes. */
+static int update_vdd(struct clk_vdd_class *vdd_class)
+{
+ int level, rc;
+
+ for (level = ARRAY_SIZE(vdd_class->level_votes)-1; level > 0; level--)
+ if (vdd_class->level_votes[level])
+ break;
+
+ if (level == vdd_class->cur_level)
+ return 0;
+
+ rc = vdd_class->set_vdd(vdd_class, level);
+ if (!rc)
+ vdd_class->cur_level = level;
+
+ return rc;
+}
+
+/* Vote for a voltage level. */
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ vdd_class->level_votes[level]++;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]--;
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+
+ return rc;
+}
+
+/* Remove vote for a voltage level. */
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
+{
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&vdd_class->lock, flags);
+ if (WARN(!vdd_class->level_votes[level],
+ "Reference counts are incorrect for %s level %d\n",
+ vdd_class->class_name, level))
+ goto out;
+ vdd_class->level_votes[level]--;
+ rc = update_vdd(vdd_class);
+ if (rc)
+ vdd_class->level_votes[level]++;
+out:
+ spin_unlock_irqrestore(&vdd_class->lock, flags);
+ return rc;
+}
+
+/* Vote for a voltage level corresponding to a clock's rate. */
+static int vote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return 0;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return level;
+
+ return vote_vdd_level(clk->vdd_class, level);
+}
+
+/* Remove vote for a voltage level corresponding to a clock's rate. */
+static void unvote_rate_vdd(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return;
+
+ level = find_vdd_level(clk, rate);
+ if (level < 0)
+ return;
+
+ unvote_vdd_level(clk->vdd_class, level);
+}
+
/*
* Standard clock functions defined in include/linux/clk.h
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
- unsigned long flags;
+ unsigned long flags, rate;
struct clk *parent;
if (!clk)
@@ -39,22 +142,22 @@
spin_lock_irqsave(&clk->lock, flags);
if (clk->count == 0) {
parent = clk_get_parent(clk);
+ rate = clk_get_rate(clk);
+
ret = clk_enable(parent);
if (ret)
- goto out;
+ goto err_enable_parent;
ret = clk_enable(clk->depends);
- if (ret) {
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_depends;
+ ret = vote_rate_vdd(clk, rate);
+ if (ret)
+ goto err_vote_vdd;
if (clk->ops->enable)
ret = clk->ops->enable(clk);
- if (ret) {
- clk_disable(clk->depends);
- clk_disable(parent);
- goto out;
- }
+ if (ret)
+ goto err_enable_clock;
} else if (clk->flags & CLKFLAG_HANDOFF_RATE) {
/*
* The clock was already enabled by handoff code so there is no
@@ -69,6 +172,16 @@
out:
spin_unlock_irqrestore(&clk->lock, flags);
+ return 0;
+
+err_enable_clock:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ clk_disable(clk->depends);
+err_enable_depends:
+ clk_disable(parent);
+err_enable_parent:
+ spin_unlock_irqrestore(&clk->lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -76,7 +189,6 @@
void clk_disable(struct clk *clk)
{
unsigned long flags;
- struct clk *parent;
if (!clk)
return;
@@ -85,10 +197,13 @@
if (WARN(clk->count == 0, "%s is unbalanced", clk->dbg_name))
goto out;
if (clk->count == 1) {
+ struct clk *parent = clk_get_parent(clk);
+ unsigned long rate = clk_get_rate(clk);
+
if (clk->ops->disable)
clk->ops->disable(clk);
+ unvote_rate_vdd(clk, rate);
clk_disable(clk->depends);
- parent = clk_get_parent(clk);
clk_disable(parent);
}
clk->count--;
@@ -117,10 +232,35 @@
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned long start_rate, flags;
+ int rc;
+
if (!clk->ops->set_rate)
return -ENOSYS;
- return clk->ops->set_rate(clk, rate);
+ spin_lock_irqsave(&clk->lock, flags);
+ if (clk->count) {
+ start_rate = clk_get_rate(clk);
+ /* Enforce vdd requirements for target frequency. */
+ rc = vote_rate_vdd(clk, rate);
+ if (rc)
+ goto err_vote_vdd;
+ rc = clk->ops->set_rate(clk, rate);
+ if (rc)
+ goto err_set_rate;
+ /* Release vdd requirements for starting frequency. */
+ unvote_rate_vdd(clk, start_rate);
+ } else {
+ rc = clk->ops->set_rate(clk, rate);
+ }
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
+
+err_set_rate:
+ unvote_rate_vdd(clk, rate);
+err_vote_vdd:
+ spin_unlock_irqrestore(&clk->lock, flags);
+ return rc;
}
EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index f4a7363..ed5c9c6 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -33,6 +33,32 @@
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
+#define MAX_VDD_LEVELS 4
+
+/**
+ * struct clk_vdd_class - Voltage scaling class
+ * @class_name: name of the class
+ * @set_vdd: function to call when applying a new voltage setting
+ * @level_votes: array of votes for each level
+ * @cur_level: the currently set voltage level
+ * @lock: lock to protect this struct
+ */
+struct clk_vdd_class {
+ const char *class_name;
+ int (*set_vdd)(struct clk_vdd_class *v_class, int level);
+ int level_votes[MAX_VDD_LEVELS];
+ unsigned cur_level;
+ spinlock_t lock;
+};
+
+#define DEFINE_VDD_CLASS(_name, _set_vdd) \
+ struct clk_vdd_class _name = { \
+ .class_name = #_name, \
+ .set_vdd = _set_vdd, \
+ .cur_level = ARRAY_SIZE(_name.level_votes), \
+ .lock = __SPIN_LOCK_UNLOCKED(lock) \
+ }
+
struct clk_ops {
int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
@@ -57,12 +83,16 @@
* @count: enable refcount
* @lock: protects clk_enable()/clk_disable() path and @count
* @depends: non-direct parent of clock to enable when this clock is enabled
+ * @vdd_class: voltage scaling requirement class
+ * @fmax: maximum frequency in Hz supported at each voltage level
*/
struct clk {
uint32_t flags;
struct clk_ops *ops;
const char *dbg_name;
struct clk *depends;
+ struct clk_vdd_class *vdd_class;
+ unsigned long fmax[MAX_VDD_LEVELS];
struct list_head children;
struct list_head siblings;
@@ -104,6 +134,8 @@
extern struct clock_init_data qds8x50_clock_init_data;
void msm_clock_init(struct clock_init_data *data);
+int vote_vdd_level(struct clk_vdd_class *vdd_class, int level);
+int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level);
#ifdef CONFIG_DEBUG_FS
int clock_debug_init(struct clock_init_data *data);