Merge changes I3a605dde,I7386fee3,Id31f289b into msm-3.0
* changes:
msm: 9615: Request maximum bus clock for maximum MMC/SD/SDIO performance
defconfig: 9615: Enable hardware based SD/MMC card detection
msm: 9615: Add hardware based SD/MMC card detection
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index f8ccbb3..9ca6429 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -150,7 +150,7 @@
# CONFIG_MMC_SDHCI is not set
CONFIG_MMC_MSM=y
CONFIG_MMC_MSM_SDIO_SUPPORT=y
-# CONFIG_MMC_MSM_CARD_HW_DETECTION is not set
+CONFIG_MMC_MSM_CARD_HW_DETECTION=y
CONFIG_MMC_MSM_SDC1_SUPPORT=y
# CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT is not set
CONFIG_MMC_MSM_SDC2_SUPPORT=y
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 40cbee0..b54dea0 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -198,7 +198,8 @@
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
-#define GPIO_SDCARD_PWR_EN 18
+#define GPIO_SDCARD_PWR_EN 18
+#define GPIO_SDC1_HW_DET 80
/* MDM9x15 have 2 SDCC controllers */
enum sdcc_controllers {
@@ -371,8 +372,14 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
+ .pclk_src_dfab = 1,
.sdcc_v4_sup = true,
.pin_data = &mmc_slot_pin_data[SDCC1],
+#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
+ .status_gpio = GPIO_SDC1_HW_DET,
+ .status_irq = MSM_GPIO_TO_INT(GPIO_SDC1_HW_DET),
+ .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+#endif
};
static struct mmc_platform_data *msm9615_sdc1_pdata = &sdc1_data;
#else
@@ -389,6 +396,7 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc2_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
+ .pclk_src_dfab = 1,
.sdcc_v4_sup = true,
.pin_data = &mmc_slot_pin_data[SDCC2],
};