msm: board-8064: Create a separate board file for storage devices
Move the APQ8064 SDCC devices and initialization code into
a dedicated board file.
Change-Id: I2f45d453954d6241e3ba11b0290d318a19f8159d
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-apq8064-storage.c b/arch/arm/mach-msm/board-apq8064-storage.c
new file mode 100644
index 0000000..1d0b628
--- /dev/null
+++ b/arch/arm/mach-msm/board-apq8064-storage.c
@@ -0,0 +1,257 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/bootmem.h>
+#include <asm/mach-types.h>
+#include <asm/mach/mmc.h>
+#include <mach/msm_bus_board.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/gpiomux.h>
+#include "devices.h"
+#include "board-apq8064.h"
+
+
+/* APQ8064 has 4 SDCC controllers */
+enum sdcc_controllers {
+ SDCC1,
+ SDCC2,
+ SDCC3,
+ SDCC4,
+ MAX_SDCC_CONTROLLER
+};
+
+/* All SDCC controllers require VDD/VCC voltage */
+static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
+ /* SDCC1 : eMMC card connected */
+ [SDCC1] = {
+ .name = "sdc_vdd",
+ .high_vol_level = 2950000,
+ .low_vol_level = 2950000,
+ .always_on = 1,
+ .lpm_sup = 1,
+ .lpm_uA = 9000,
+ .hpm_uA = 200000, /* 200mA */
+ },
+ /* SDCC3 : External card slot connected */
+ [SDCC3] = {
+ .name = "sdc_vdd",
+ .high_vol_level = 2950000,
+ .low_vol_level = 2950000,
+ .hpm_uA = 600000, /* 600mA */
+ }
+};
+
+/* Only slots having eMMC card will require VCCQ voltage */
+static struct msm_mmc_reg_data mmc_vccq_reg_data[1] = {
+ /* SDCC1 : eMMC card connected */
+ [SDCC1] = {
+ .name = "sdc_vccq",
+ .always_on = 1,
+ .high_vol_level = 1800000,
+ .low_vol_level = 1800000,
+ .hpm_uA = 200000, /* 200mA */
+ }
+};
+
+/* All SDCC controllers may require voting for VDD PAD voltage */
+static struct msm_mmc_reg_data mmc_vddp_reg_data[MAX_SDCC_CONTROLLER] = {
+ /* SDCC3 : External card slot connected */
+ [SDCC3] = {
+ .name = "sdc_vddp",
+ .high_vol_level = 2950000,
+ .low_vol_level = 1850000,
+ .always_on = 1,
+ .lpm_sup = 1,
+ /* Max. Active current required is 16 mA */
+ .hpm_uA = 16000,
+ /*
+ * Sleep current required is ~300 uA. But min. vote can be
+ * in terms of mA (min. 1 mA). So let's vote for 2 mA
+ * during sleep.
+ */
+ .lpm_uA = 2000,
+ }
+};
+
+static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
+ /* SDCC1 : eMMC card connected */
+ [SDCC1] = {
+ .vdd_data = &mmc_vdd_reg_data[SDCC1],
+ .vccq_data = &mmc_vccq_reg_data[SDCC1],
+ },
+ /* SDCC3 : External card slot connected */
+ [SDCC3] = {
+ .vdd_data = &mmc_vdd_reg_data[SDCC3],
+ .vddp_data = &mmc_vddp_reg_data[SDCC3],
+ }
+};
+
+/* SDC1 pad data */
+static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
+ {TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
+ {TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA},
+ {TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA}
+};
+
+static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = {
+ {TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA},
+ {TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA},
+ {TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA}
+};
+
+static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = {
+ {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
+ {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
+ {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
+};
+
+static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
+ {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
+ {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_DOWN},
+ {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_DOWN}
+};
+
+/* SDC3 pad data */
+static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = {
+ {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
+ {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
+ {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
+};
+
+static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = {
+ {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
+ {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
+ {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
+};
+
+static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = {
+ {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
+ {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
+ {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
+};
+
+static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = {
+ {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
+ {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
+ {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
+};
+
+static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = {
+ [SDCC1] = {
+ .on = sdc1_pad_pull_on_cfg,
+ .off = sdc1_pad_pull_off_cfg,
+ .size = ARRAY_SIZE(sdc1_pad_pull_on_cfg)
+ },
+ [SDCC3] = {
+ .on = sdc3_pad_pull_on_cfg,
+ .off = sdc3_pad_pull_off_cfg,
+ .size = ARRAY_SIZE(sdc3_pad_pull_on_cfg)
+ },
+};
+
+static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = {
+ [SDCC1] = {
+ .on = sdc1_pad_drv_on_cfg,
+ .off = sdc1_pad_drv_off_cfg,
+ .size = ARRAY_SIZE(sdc1_pad_drv_on_cfg)
+ },
+ [SDCC3] = {
+ .on = sdc3_pad_drv_on_cfg,
+ .off = sdc3_pad_drv_off_cfg,
+ .size = ARRAY_SIZE(sdc3_pad_drv_on_cfg)
+ },
+};
+
+static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
+ [SDCC1] = {
+ .pull = &mmc_pad_pull_data[SDCC1],
+ .drv = &mmc_pad_drv_data[SDCC1]
+ },
+ [SDCC3] = {
+ .pull = &mmc_pad_pull_data[SDCC3],
+ .drv = &mmc_pad_drv_data[SDCC3]
+ },
+};
+
+static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
+ [SDCC1] = {
+ .pad_data = &mmc_pad_data[SDCC1],
+ },
+ [SDCC3] = {
+ .pad_data = &mmc_pad_data[SDCC3],
+ },
+};
+
+#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
+static unsigned int sdc1_sup_clk_rates[] = {
+ 400000, 24000000, 48000000, 96000000
+};
+
+static struct mmc_platform_data sdc1_data = {
+ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
+#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
+ .mmc_bus_width = MMC_CAP_8_BIT_DATA,
+#else
+ .mmc_bus_width = MMC_CAP_4_BIT_DATA,
+#endif
+ .sup_clk_table = sdc1_sup_clk_rates,
+ .sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
+ .pin_data = &mmc_slot_pin_data[SDCC1],
+ .vreg_data = &mmc_slot_vreg_data[SDCC1],
+};
+static struct mmc_platform_data *apq8064_sdc1_pdata = &sdc1_data;
+#else
+static struct mmc_platform_data *apq8064_sdc1_pdata;
+#endif
+
+#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
+static unsigned int sdc3_sup_clk_rates[] = {
+ 400000, 24000000, 48000000, 96000000
+};
+
+static struct mmc_platform_data sdc3_data = {
+ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
+ .mmc_bus_width = MMC_CAP_4_BIT_DATA,
+ .sup_clk_table = sdc3_sup_clk_rates,
+ .sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
+ .pin_data = &mmc_slot_pin_data[SDCC3],
+ .vreg_data = &mmc_slot_vreg_data[SDCC3],
+};
+static struct mmc_platform_data *apq8064_sdc3_pdata = &sdc3_data;
+#else
+static struct mmc_platform_data *apq8064_sdc3_pdata;
+#endif
+
+void __init apq8064_init_mmc(void)
+{
+ if ((machine_is_apq8064_rumi3()) || machine_is_apq8064_sim()) {
+ if (apq8064_sdc1_pdata) {
+ if (machine_is_apq8064_sim())
+ apq8064_sdc1_pdata->disable_bam = true;
+ apq8064_sdc1_pdata->disable_runtime_pm = true;
+ apq8064_sdc1_pdata->disable_cmd23 = true;
+ }
+ if (apq8064_sdc3_pdata) {
+ if (machine_is_apq8064_sim())
+ apq8064_sdc3_pdata->disable_bam = true;
+ apq8064_sdc3_pdata->disable_runtime_pm = true;
+ apq8064_sdc3_pdata->disable_cmd23 = true;
+ }
+ }
+ apq8064_add_sdcc(1, apq8064_sdc1_pdata);
+ apq8064_add_sdcc(3, apq8064_sdc3_pdata);
+}